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Intel Xeon Phi 7120A

1. Dara 6 6 3 Supported IPMI Commands The SMC supports a subset of the standard IPMI sensor SEL and SDR commands along with several Intel OEM commands for accomplishing things like forcing throttle mode The supported IPMI commands are documented in the following sections Standard IPMI details are not documented in this document For those please refer to the IPMI v2 0 specification For example 488073 the Get SDR command requires additional bytes to complete the command packet and these bytes are defined in the IPMI v2 0 specification 6 6 3 1 Miscellaneous Commands Table 6 2 Miscellaneous Command Details App 0x01 Get Device ID 0x06 App 0x08 Get Device GUID UUID 0x06 6 6 3 2 FRU Related Commands Table 6 3 FRU Related Command Details Storage 0x10 Get FRU Inventory Area Info 0 08 Storage Ox11 Read FRU Data Ox0a Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 69 intel 6 6 3 3 SDR Related Commands Table 6 4 SDR Related Command Details Storage 0x20 Get SDR Repository Info 0 08 Storage 0x21 Get SDR Repository Allocation Info 0 08 Storage 0x23 Get SDR 0 08 Note The SDR can be read in chunks suggested size is 16 bytes or the entire SDR can be read by passing FF as the number of bytes to read 6 6 3 4 SEL Related Commands Table 6 5 SEL Related Command Details Storage 0x40 Get SEL Info 0 08 Storage 0x41 Get SEL Allocation Info
2. intel Intel Xeon Phi Coprocessor Datasheet April 2014 Documen t ID Number 328209 003EN By using this document in addition to any agreements you have with Intel you accept the terms set forth below You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein You agree to grant Intel a non exclusive royalty free license to any patent claim thereafter drafted which includes subject matter disclosed herein INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT A Mission Critical Application is any application in which failure of the Intel Product could result directly or indirectly in personal injury or death SHOULD YOU PURCHASE OR USE INTEL S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES SUBCONTRACTORS AND AFFILIATES AND THE DIRECTORS
3. mi 1 ss me 9 me ser mme 9 mm hem 1 m 1 em mms o Lem mms o m Lm ee 1 eros Ls me ms 1 Lm 9 mm hem EE Lows ma 9 hem ws me 0 me Lm ee Lm ws mms o ws 1 mms 9 em 5 Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 49 intel Table 4 2 5120D DFF SKU Pinout 1 se ss sm av 9 a uw a uw S oum ae S S bee S Ls uw bee S em uw me 695 S 81 uw ami 695 951 uw e 695 51 uw e 695 61 uw Jf ae 6951 uw ms 695 951 uw e 695 71 uw ww 951 um 695 51 uw Jf as 695 S 9651 uw ae 695 51 ai 695 951 uw m 695 51 uw as 695 61 uw m 695 951 uw 1 as
4. DRE 69 Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 4 List of Tables tir Related DOCUMENTS TTE 7 1 2 General Terminology socio 7 2 1 Intel Xeon Phi Coprocessor Product Family es ee ee e e e x e e e e ee ee 13 3 1 Intel Xeon Phi Coprocessor Mechanical Specification 15 3 2 Intel Xeon Phi Coprocessor Thermal Specification w wwamanaanaamanwananuwza 18 3 3 Component Thermal Specification on SE10X 7120X and 7120D 5120D 32 3 4 BOALA ONO Heights penere 35 3 5 Dynamic Load Shift Specification cece eee nennen nnn an nnne 39 4 1 PCI Express Connector Signals on the Intel Xeon Phi Coprocessor 45 4 2 21 1017 DER SKU 101111 a 48 4 3 51xxD Power Rail Requirements on Baseboard csse 51 5 1 Intel Xeon Phi Coprocessor Power StateS ccccccccseeceeeeeeeeeesseeeeeeeeegggeeeeetnseggeees 53 o SMBus VENNENE 68 6 2 Miscellaneous Command Details eee eee eee eee eee aaa eee aaa 69 6 3 FRU Related Command Details sss sss ss oen neon rn nna a amem enn rna 69 6 4 SDR Related Command 8 5 eee eee e eee 5544434485 eee nhanh nnn nnn 70 6 5 SEL Related Command Details nra Er CE SOR x a 70 6 6 Sensor Related Command Details
5. TITLE Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 31 Table 3 3 3 4 1 1 Table 3 3 shows thermal specifications of components present on the SE10X 7120X and 7120D 5120D boards Component Thermal Specification on SE10X 7120X and 7120D 5120D GDDR Tease 85 C VR FET Tue 130 C VR Inductor Tbody 100 C Notes 1 While this is the component specification on the passive and active Intel Xeon Phi coprocessor products the junction temperature is limited to 135 C in order to prevent damage to the PCB VR Temperature and Thermal Throttling Some thermal sensors on the coprocessor are located in the field of the VR inductors and FETs that drive power to the coprocessor silicon GDDR and other circuitry Figure 3 15 These sensors continuously monitor the temperature of the circuit board If the temperature reaches or exceeds 105 C an interrupt will be sent to the SMC In response to this interrupt the SMC will assert PROCHOT to the coprocessor which in turn will force the coprocessor frequency to drop to the minimum supported value approximately 600MHz This frequency drop will reduce the power dissipation of the card and should allow the VR components to cool down Once the temperature has dropped below 105 C the VR controller will send a message to the SMC to de assert PROCHOT This will allow the coprocessor to return to the normal high frequency operating poi
6. 222 2 222 2 2 222222222 22522222 2 5 2222222 5 25 2222 7 GDDR De Ee 8E m See eee 1 3 mm E BRL 8 amp E mH E E m B NM E opa TT T E Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 28 Figure 3 12 51200 Power Profile Memory Centric all values in Watts 0303 03 04 04 04 04 04 04 04 1 9 1 9 Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 29 intel Figure 3 13 7120D Power Profile Coprocessor Centric all values in Watts VR FET DEE Popii MATA 06 06706 06 06 0 6 VR Inductor GDDR Intel Xeon Phi coprocessor silicon SMC UNE T HDD DR TENE E 8 9 1 3 8 L um E en E m E a Ea E 8 TIN Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 30 Figure 3 14 71200 Power Profile Memory Centric all values in Watts 0 5748 Nom Mora 0 58 MIA MIA 06 06 06 06 1 9 EE M HE EE E EE EE EE E E E a 19 amp B 1 9 HE SIE BINNEN SIE EEE 11011111 sinn Pelee
7. eee eee nennen nen nnn 70 6 7 General command DetallS usina ala n Care rd aci oe 71 6 8 CPU Package Config Read Request Format ssesesseessen nennen 71 6 9 CPU Package Config Read Response Format eee eee eee nnne 71 6 10 CPU Package Config Write Request Format ssssessseseeeeen enn nennen nnn 72 6 11 CPU Package Config Write Response Format esssssesseen nnne 72 6 12 Set SM Signal Request Format ccs ee ce e e x e e e e ee 72 6 13 Set SM Signal Response Format iioii ces e cs e cs e e s e e ss ees ai rat eclair tess 73 6 14 OEM Command Details sees enhn nennen roh nnn nnn nnn addas 8899894180 73 6 15 Set Fan PWM Adder Command Request Format aauunnnnnnnnnnnnnnnnnnnennnnnnnnnnnnnnnnnnnnnnnnr 73 6 16 Set Fan PWM Adder Command Response Format eee nnne 74 6 17 Get POST Register Request Format cccccesceee eee eee eere hh 4449 nana 48885 hn nn nn 74 6 18 Get POST Register Response Format es s se rr rr rr 74 6 19 Assert Forced Throttle Request Format aauuuunnnnnnnnnnnnnnnnnnnunnnnnnnnnnnrrrrnnnnnnnnnnnuuvuner 74 6 20 Assert Forced Throttle Response Format sseesssssseseeeee nennen 74 6 21 Enable External Throttle Request Format sseseessssseeeeeeenn nnne nnn nnns 75 6 22 Enable External Throttle Response Format cccceeeee cece cece eee e eee nnne nnn 75 6 23 OEM Get Throttle Reason Request FOrmat
8. nnnm mnn nnn 12 2 14 Intel Xeon Phi Coprocessor Product Family 5 13 2 1 5 Intel Xeon Phi Coprocessor 7120D 5120D Dense Form Factor 13 3 Thermal and Mechanical Specification w wwamanaananwanzananwanunwanzanawunwa 15 L VENNS 15 3 2 Intel Xeon Phi Coprocessor Thermal Specification e e e ee e e e eee 18 3 2 1 Intel Xeon Phi Coprocessor Thermal 18 89 1 18 3 3 Intel Xeon Phi Coprocessor Thermal 501 110 5 x e x e x x x e x K KeK 19 3 3 1 3120A and 7120A Active Cooling Solution eee nnn 20 3 3 2 7120P SE10P 5110P 3120P 31S1P Passive Cooling Solution 21 3 4 Cooling Solution Guidelines for SE10X 7120X and 7120D 5120D 26 BAL Thermal CONSI T NN ee 26 542 Thermal Profile and Colin II 33 3 4 3 Mechanical ConsiderationS es ece e x e ce i an aaa te a dati aa ll 35 3 4 4 Mechanical Shock and Vibration Testing ccm eee mnn 39 3 5 Intel Xeon Phi Coprocessor PCI Express Card Extender Bracket Installation 40 3 5 1 Bracket Installation SES Lue 41 4 Intel Xeon Phi Coprocessor Pin 5 1 110 5 5 5 5 5555505
9. samansananzanzanaananzanaanananzanzanaananzana 75 6 24 OEM Get Throttle Reason Response Format ceeessssssessse n nnne nnn nnns 75 625 TNT NVE 76 6 26 Status Sensor Report Format ssssssssssssassnsssnnanansunnannanannunnnnnnnsnnnunnnnannnnnnnnnnans 77 Fr ENN 78 Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 5 intel Revision History Document Revision Number Number Description Updated product SKU Table 2 1 Added 31S1P 7120A and 7120D Added SKUs 31S1P and 7120A to relevant figures paragraphs and tables throughout document 3282 graag EE Added thermal throttling due to hot to VRs Section 3 4 1 1 BLEUS Minor changes and clarifications in power management and manageability chapter Updated product SKU Table 2 1 Updated mechanical specification Table 3 1 and thermal specification Table 3 2 Other changes in thermal and mechanical specification chapter 328209 002 Added significant information on 5120D in pin list chapter ii eee Updated power state numbers in Table 5 1 and added Turbo in power management chapter Changes and clarifications in manageability chapter 328209 e First Intel Xeon Phi Coprocessor Datasheet release November 2012 Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 6 1 1 Table 1 1 1 2 1 2 1 Table 1 2 Introduction Reference Documentation Table 1 1 lists most of the applicable documents For
10. to adjust airflow The change in airflow over an air cooled heat sink affects the PY value It is common to reduce fan speed when maximum airflow is not needed to save power reduce noise or both In the B C region even though Tiunction IS at a constant value Tease actually goes up a little bit at lower power consumption levels This is because a variable fan speed results in a variable Yea but a fixed T Finally in the C D region where the coprocessor consumes very little power an air cooled heat sink using a variable fan speed to maintain a target junction temperature may slow the airflow down too much If the airflow is too low the junction temperature may be maintained properly but the exhaust air temperature approaches the junction temperature Data center design considerations including safety may dictate that a maximum allowable exhaust air temperature such as 70 C which in turn will set a maximum limit on Yea Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 34 3 4 3 Table 3 4 Document ID Number 328209 003EN intel Mechanical Considerations e In the passive Intel Xeon Phi coprocessor products the only component on the card with IHS load is the coprocessor The compressive load is assumed to be approximately uniformly distributed over the IHS The minimum load is 23lbf and maximum load is 75lbf The mean pressure on the IHS is 3215 e Hitachi Type7 is recommended as the ther
11. CEL PEN ae e 1 RERUMS 67 6 6 2 Polled Master Only Protocol eene enn nnn 67 6 6 3 Supported IPMI Commands e e e ce e e e e K e 69 67 SMC LED ERROR and Fan PWANI 78 Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 3 intel List of Figures 2 1 Intel Xeon Phi Coprocessor Board Schematic cee eee eee nen 9 2 2 Intel Xeon Phi Coprocessor Board Top side for reference only 11 2 3 Intel Xeon Phi Coprocessor Board Back side reference only 11 2 4 Intel Xeon Phi Coprocessor Silicon 0 e eee 12 2 5 7120D 5120D Dense Form Factor Topside secs cs ece eee eee 14 3 1 Location of Mounting Holes on the Intel Xeon Phi Coprocessor Card in mils 16 3 2 Dimensions of the Intel Xeon Phi Coprocessor Card in mils sse 17 3 3 Entering and Exiting Thermal Throttling PROCHOT 555555555 19 3 4 Exploded View of 3120A 7120A Active 55 5344 5 20 3 5 Exploded View of Passive Thermal Solution 44 nnm 21 3 6 Airflow Requirement vs 450C Inlet Temperatur
12. The IPMB slave address self select starting address is nonvolatile starting at the last selected slave address This ensures that the card doesn t move nondeterministically in a static system To determine the address of the Intel Xeon Phi coprocessor card scan the range of addresses issuing the Get Device ID command for each address A valid response indicates the address used is a valid address For the Intel Xeon Phi coprocessor cards the IPMB slave address will be found at 0x30 if only a single card is installed If the motherboard has an exclusive connection to the SMBus on each PCI Express connection then the Intel Xeon Phi coprocessor will assign itself a default address 0x30 If the SMBus connections are shared each Intel Xeon Phi coprocessor in a chassis will negotiate with each other and select addresses in the range from 0x30 to Ox4e If a mux is incorporated into the design to isolate devices on a shared link the address negotiation process should result in each card having address 0x30 However if the mux in use allows for the channels to be merged i e creating a shared bus scenario the address negotiation may result in each card having a unique address behind the mux Power management and power control are performed through the host driver interface in band An SDK is provided as part of the Intel Xeon Phi coprocessor software stack and can be found in the standard MPSS release The SMC s PCI Expres
13. In Band Management Interface SCIF Manageability through the SMC is achievable via the SCIF interface which is part of the MPSS software stack This allows host programs to obtain MIC telemetry and other information from the SMC managed features of the Intel Xeon Phi coprocessor itself as well as control SMC enabled functions The SMC supports a host based SCIF interface The following SMC information and sensors are accessible over the host based user mode SCIF interface e Hardware strapping pins e SMC firmware revision number e UUID e PCI compliant Memory Mapped Input Output MMIO e Fan tachometer e Fan Pulse Width Modulation PWM to boost fan speed for additional cooling e SMC System Event Log SEL e All registers mentioned in the Ganglia support section e Voltage rail discrete monitoring e All discrete temperature sensors Teritical Tcontrol Tcurrent Teontrol offset adder e Thermal throttle duration due to card power throttle threshold in ms free running counter that overflows at 60 seconds e Tinet derived numbers e Toutiet derived numbers e PERF Status Thermal e 32 bit POST register e SMC SEL Entry select and data registers read only e SMC SDR Entry select and data registers read only required to interpret the SEL Each SMC sensor that is exposed over SCIF indicates one of four states in a consistent manner returned in the same register value as the sensor reading itself regardless of sensor type
14. 27 8 29 2 30 9 32 8 17 6 18 4 19 1 20 9 21 9 24 2 25 6 Total Flow ft13 min Primary ft 3 min 144 5 0 O 108 JP 39 o BO ao 39 8 39 L 156 ur lo 4 eo ll 22 1 ads 23 4 ad 4 aa loo gol AS o so 41 ws 185 uml 43 191 148 43 dr 44 23 158 45 Lo 21 1264 NEU a SO o ve 48 H 393 3184 o 5 eee Ass uo 51 ee as 2 2 53 B 365 209 56 Z 22 219 202 23 62 309 22 67 6 aso 256 1 72 Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 24 intel Figure 3 8 Airflow Requirement vs Inlet Temperature for the 5110P Card at 245W TDP EEE EEE EEE EEE EEE EEE EEE 245 W Card Flow vs Inlet Temperature 35 Total Flow ft13 min Primary ft 3 min Flow ft min Serondary ft 3 min 20 25 30 35 40 45 50 Card Inlet Temperature T C o J 228 1 vs 29 01 Notes 1 Refer to Section 5 1 for note on 5110P TDP Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 25 intel 3 4 3 4 1 Figure 3 9 Cooling Solution Guidelines for SE10X 7120X and 7120D 5120D The Intel amp Xeon Phi coprocessor SE10X 7120X and 7120D 5120D SKUs are shipped without a thermal solution which gives system d
15. 31 ft min with no adjacent blockage When an adjacent card is considered the resultant impedance loss causes the flow rate to drop to 23 ft min The active thermal solution is designed to provide sufficient cooling even in the latter scenario Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 20 intel 3 3 2 7120P SE10P 5110P 3120P 31S1P Passive Cooling Solution For the passive heat sink on the 7120P SE10P 5110P 3120P 31S1P SKUs the Intel Xeon Phi coprocessor thermal 8 mechanical solution also utilizes a fuselage supersink approach Figure 3 5 illustrates the key components of the passive design Figure 3 5 Exploded View of Passive Thermal Solution CPU Heat Sink e Vapor chamber based Soldered stamped copper fin bank I O Bracket e Standard 2 slot PCI 9 Structural connection to ID Cover e Aluminum sheet metal e Printed with Intel branding Fuselage Supersink Mechanical interface to system Folded sheet aluminum e Sinks heat from GDDR amp VR system Soldered internal folded fins NS and heat pipes 312 Bracket P Card PBA 95 246mm card length N 2x3 and 2x4 aux power on east edge e PCI Express CEM spec compliant except hockey stick KOZ Backplate Stiffener Heat Sink clamshell Copper plate with soldered heat pipes and copper blocks Supports preload forces 7 4 Sinks heat from backsi shroud e Card to system interface emulating fu
16. 6951 Note The 5120D SKU does not use the 3 3V AUX power pins and baseboard designers have the option to either route these pins or leave them unconnected The PROCHOT N pin on the 5120D SKU follows the definition and routing requirements listed in Section 4 1 1 Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 50 4 3 1 Table 4 3 4 3 2 intel Baseboard Requirements of 5120D Unlike the Intel Xeon Phi coprocessor PCI Express card the 5120D SKU requires the baseboard to implement input filter for the 12V and 3 3V power rails There are no auxiliary or external power connectors on the 5120D and all power is supplied via the 230 pin edge connector e Each 5120D product in the system requires a dedicated input filter for the 12V rail e The filtering circuitry should be placed as close to the connector pins as possible e The 3 3V power rail input must meet the PCI Express CEM specification 51xxD Power Rail Requirements on Baseboard 12V Min VIN 11 04V Max current 22 192A Maximum rated ripple current per capacitor considering 70 of derating 2 254A Maximum input current slew rate at input inductor 0 5A us Maximum operating temperature for the input capacitors LC filter 1059C A typical implementation of the input filter would use 5 x 150uF Sanyo 16SVPC150M capacitors and 1 x 0 2uH Pulse PG0426 201NL inductor 3 3V Decoupling caps Max Current AC Couplin
17. N is 8 3 3 volt active low signal that when deasserted high indicates that the 12V and VCC3 power supplies are stable and within their specified tolerance Intel Xeon Phi Coprocessor Datasheet 45 ntel Table 4 1 PCI Express Connector Signals on the Intel Xeon Phi Coprocessor Signal SMB PCI CLK I O PCI Express System Management Bus Clock SMB PCI CLK is the 3 3 volt clock signal for the SMBus Interface which is normally used for power and or thermal management and for monitoring the card SMB PCI DAT PCI Express System Management Bus Data SMB PCI DAT is the 3 3 volt data signal for the SMBus Interface which is normally used for power and or thermal management and for monitoring the card PRSNT1 N PRSNT2 N Following PCI Express specification PRSNT1 N pin A1 is connected on the coprocessor card to PRSNT2 N pin 581 Remaining PRSNT2 N pins 17 531 548 must be unconnected on the baseboard VCC3 3 3V Supply The positive 3 3 volt power supply to the PCI Express card 12V 12V Supply The positive 12 volt power supply to the PCI Express card V_3P3_PCIAUX 3 3VAux Supply PROCHOT N pin 512 On the Intel 9 Xeon Phi coprocessor the SMC supports an external path from the baseboard to the card s B12 pin which allows system agents such as BMC or ME to throttle the card in response to card thermal events thermal throttling Pin B12 defined as reserved in the PCI Express specificat
18. Ox0a Storage 0x43 Get SEL Entry Ox0a Storage 0x47 Clear SEL 0 08 Storage 0x48 Get SEL Time 0 08 Storage 0x49 Set SEL Time 0 08 6 6 3 5 Sensor Related Commands Table 6 6 Sensor Related Command Details Sensor Ox2b Get Sensor Event Status 0x04 Sensor Ox2d Get Sensor Reading 0x04 Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 70 6 6 3 6 General Commands Table 6 7 General Command Details Intel 0x42 CPU Package Config Read 0x2e Intel 0x43 CPU Package Config Write 0x2e Intel 0x15 Set SM Signal General App 0x30 6 6 3 6 1 CPU Package Configuration Read The CPU Package Config Read command reads power control data For the parameter byte formats refer to the Intel Xeon Processor Family External Design Specification EDS Volume 1 Table 6 8 CPU Package Config Read Request Format 92 e Manufacturer ID LSB format 0x57 0x01 0x00 4 0x PCS Index 3 Accumulated Energy Status 11 Socket Power Throttle Duration 26 Package Power Throttle Threshold Value 1 PL1 27 Package Power Throttle Threshold Value 2 PLO 28 Package Power SKU A 29 Package Power SKU B 30 Package Power SKU Unit All other values reserved Table 6 9 CPU Package Config Read Response Format Ox Compcode 0x00 Normal Oxcc Invalid field Oxal Wrong CPU Number Oxa7 Wrong Read Length Oxab Wrong Command Code Oxff Unspecified Error Manufacturer ID LS
19. P states and Turbo frequencies may vary across SKUS Once the OS requests turbo operation by selecting the PO1 state the coprocessor will automatically select the best POn state that will remain within the specified thermal and power limits Determination of this P state is based on the number of active cores the current draw the average power consumption and the temperature If these conditions change the turbo P state may also change or even be reduced to the non turbo P state of P1 In turbo mode the coprocessor is free to change the P state at any time without giving advanced notice to the OS Although the OS may request 01 there is no guarantee that a turbo frequency will be selected If the conditions are not sufficient to allow the coprocessor to run above P1 then it will remain in P1 The amount of time the processor can spend in turbo mode may be influenced by the workload and the operating environment Turbo mode may be disabled through the SMC Control Panel or by configuring the operating system such that it never requests the PO1 P state Only the 7120A 7120D 7120P and 7120X SKUS support Turbo mode Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 58 Figure 5 8 Intel Xeon Phi coprocessor P States and Turbo P States 6 5 O Core Frequency Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 59 Intel Xeon Phi Coprocessor Datasheet Docume
20. These states do not apply to non sensor information e Normal e Upper critical e Lower critical e Inaccessible sensor not available This minimizes the complexity of host driven software and SMC firmware implementations Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 64 intel The sensors available from the SMC vary within the Intel Xeon Phi coprocessor family of products However the IPMI SDR sensor names will not change from release to release Tinlet and Toutiet are derived numbers based on the Inlet and Outlet temperature sensors The sensors located on the Intel Xeon Phi coprocessor relate information about the CPU temperature as well as the temperature from three locations on the Intel Xeon Phi coprocessor Currently one sensor is located between memory chips near the PCI Express slot while the other two are located on the east and west sides of the card These are sometimes referred to as the inlet and outlet air temperature sensors but they do not actually indicate airflow temperature but rather the temperature of the board The sensors are attached to the 12 inputs from the PCI Express slot the 2x3 connector and the 2x4 connector Input power can be estimated by summing the currents over these three connections For an actively cooled card the SMC can also provide the fan percentage PWM being used Fan speed is a simple PID control with setpoints set rather high to keep
21. board 100MHz 50ppm reference clock and requires only the PCI Express 100MHz reference clock input from the motherboard The Intel Xeon Phi coprocessor provides the following high level features e A many core coprocessor e Maximum 16 channel GDDR memory interface with an option to enable ECC e PCI Express 2 0 x16 interface with optional SMBus management interface e Node Power and Thermal Management including power capping support 9 12V power monitoring and on board fan Proportional Integral Derivative PID controller 3120A and 7120A SKUs e On board flash device that loads the coprocessor OS on boot e Card level RAS features and recovery capabilities Intel Xeon Phi Coprocessor Board Design The Intel Xeon Phi coprocessor is a PCI Express compliant high power add in product with an integrated thermal and mechanical solution see SKU matrix Table 2 1 for exceptions It supports a maximum of 16 GDDR memory channels distributed on both sides of the PCB inside the coprocessor package Each memory channel supports two 16 bit wide GDDR device for a maximum of 32 devices combining to give 32 bit wide data Figure 2 2 and Figure 2 3 show the front and back sides of the PCB The two notches along the top edge of the card are used to attach the cooling plate for the GDDR devices on the backside of the PCB side not containing the Intel Xeon Phi coprocessor silicon The VRs are split right and left to help
22. setting in order to guarantee proper operation and each P state corresponds to one of these frequency and voltage pairs Each device is uniquely calibrated and programmed at the factory with its appropriate frequency and voltage pairs As a result it is possible that two devices with the same frequency specification may have different voltage settings Intel9 Xeon Phi coprocessor supports Turbo Mode which at the request of the operating system will opportunistically and automatically run the coprocessor at a higher frequency than its TDP rated value When the card is operating below its specified power and temperature limits the Power Control Unit PCU within the card will select the highest possible turbo frequency while still remaining within the power and thermal specifications The highest Turbo Mode P state is PO1 followed by sequentially lower frequency states of 02 P03 on down to the lowest Turbo state of POn P states within the standard frequency range are referred to as P1 P2 P3 with Pn being the lowest frequency state Below Pn is one final P state called LFM or Low Frequency Mode LFM is only used by the coprocessor when the device is over the PROCHOT trip temperature and is attempting to cool down by reducing power dissipation LFM reduces the frequency to the absolute lowest possible value but the voltage will remain the same as P state Pn See Figure 5 8 All parts within a given SKU will have the same P states but
23. 000000555599 45 Ql JTPOLEXDISSS SN 4 45 FORENE 46 4 2 Supplemental Power Connector S ERR EG OE a 47 4 3 Dense Form Factor 5120D Edge Connector Pins ccc cece cee eee mnes 47 4 3 1 Baseboard Requirements of 5120D cesssseeeeee nnne nnn nnn 51 252 AC COUDIING Of 5120D D ta PAS ayas rodri 51 5 Power Specification and 13 39 1 4444 53 HP SKU POWER OPON FS 53 5 2 Intel Xeon Phi Coprocessor Power StateS aawavvrnnnnnnnannnnnnnnnnenennnnnnnnnnnnnnnnnnnneer 54 S9 Pestates and TUrDO MN 57 6 Mana gt 01 10 222168 E 61 6 1 Intel Xeon Phi Coprocessor Manageability 1 61 6 2 System Management Controller SMC nnnm nnn nnn 61 6 3 General SMC Features and Capabilities eee eee ee eee aaa eee eee eee nn 63 6 3 1 Catastrophic Shutdown Detection asis 63 6 4 Host In Band Management Interface eee eee 64 6 5 System and Power Management cce ece ce ce e x x x e c e e e e ee 65 6 6 Out of Band PCI Express SMBus IPMB Management Capabilities 66
24. 209 003EN 12 intel 2 1 4 Intel amp Xeon Phi Coprocessor Product Family Table 2 1 Intel Xeon Phi Coprocessor Product Family Notes 1 Passive cooling solution uses topside heatsink vapor chamber and copper fins and backside aluminum plate Active cooling uses on card dual intake blower 2 SE10P SE10X are limited edition one time only SKUs 3 Same performance and card configuration as the 7120P SE10P but without Intel heatsink or chassis retention mechanism allows for custom thermal and mechanical design by users 4 7120P 7120X feature Turbo 5 Dense Form Factor DFF Smaller physical footprint than the other Intel Xeon Phi coprocessor products for innovative platform designs with unique PCI Express interface PCI Express 2 0 specification compliant 6 Refer to Section 5 1 for note on total card TDP of 5110P 2 1 5 Intel Xeon Phi Coprocessor 7120D 5120D Dense Form Factor The Intel Xeon Phi coprocessor 7120D 5120D products also known as Dense Form Factor DFF are derivatives of the standard Intel Xeon Phi coprocessor PCI Express form factor card The high level features of the DFFs are e Maximum TDP of 270W for the 7120D and 245W for the 5120D e GDDR on both sides of the card e 117 35mm 4 62 x 149 86mm 5 9 PCB e 230 pin unique edge finger designed to industry standard x24 PCI Express connector PCI Express 2 0 compliant The unique edge finger pin definition requires sign
25. 28209 003EN 16 D e P TE zm 887811 il lis Hj Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 17 Table 3 2 Intel Xeon Phi Coprocessor Thermal Specification Intel Xeon Phi Coprocessor Thermal Specification 5 C 95 C Ta 3 2 1 Intel Xeon Phi 18 Tthermtrip Throttle T 2096 Notes 1 Tcontrel is the setpoint at which the system fans must ramp up towards full power or RPM to maintain the Intel Xeon Phi coprocessor temperature around Tcontro and prevent throttling It is a requirement that the system BMC use IPMB commands to query the SMC on the coprocessor card for accurate Tcontrol value as this value can vary between 80 C and 84 C 2 When the coprocessor junction temperature Tjunction reaches Tthrottler the SMC will force thermal throttle which will drop frequency to lowest supported value and reduce total coprocessor power It is a requirement that the system BMC query the SMC on the coprocessor card for accurate Tthrottje value 3 If the coprocessor temperature reaches Tthermtrip the coprocessor OS will take action to shutdown the card to prevent damage to the coprocessor This includes shutting down the coprocessor VRs and the only way to restart the coprocessor is by rebooting the host system Tthermtrip Should not be considered a specification it can change between SKUs and is given here as guidan
26. B format 0x57 0x01 0x00 4 7 Data bytes read to 4 bytes Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 71 intel 6 6 3 6 2 CPU Package Configuration Write The CPU Package Config Write command allows the setting of power control data For the parameter byte formats refer to the Intel Xeon Processor Family External Design Specification EDS Volume 1 Figure 2 36 in the EDS shows the format of the data word to effect writing the limits and the time windows The index referenced below can be correlated to figure 2 36 as SMC PLO gt RAPL PL2 8 SMC PL1 gt RAPL PL1 Table 6 10 CPU Package Config Write Request Format e __ TN 4 Ox PCS Index 26 Package Power Throttle Threshold Value 1 PL1 e 27 Package Power Throttle Threshold Value 2 PLO e All other values reserved e 8 11 Data bytes to write Table 6 11 CPU Package Config Write Response Format Ox Compcode 0x00 Normal Oxc7 Request Length Invalid Oxcc Invalid Field Oxa1 Wrong CPU Number 0xa6 Wrong Write Length Oxab Wrong Command Code Oxff Unspecified Error Manufacturer ID LSB format 0x57 0x01 0x00 6 6 3 6 3 Set SM Signal The Set SM Signal command gives you control of firmware signals The primary use of this command is to set the status LED into identify mode In identify mode the status LED flashes on for a short period twice every 2 seconds This allows an administrator to loc
27. Core Core Core L2 Cache 2 L2 Cache L2 wana ip MEME TEN feiet PN TEN Figure 2 4 is a conceptual drawing of the general structure of the Intel Xeon Phi coprocessor architecture and does not imply actual distances latencies etc The cores PCIe Interface logic and GDDR5 memory controllers are connected via an Interprocessor Network IPN ring which can be thought of as independent bidirectional ring The L2 caches are shown here as slices per core but can also be thought of as a fully coherent cache with a total size equal to the sum of the slices Information can be copied to each core that uses it to provide the fastest possible local access or a single copy can be present for all cores to provide maximum cache capacity The Intel Xeon Phi coprocessor can support to 61 cores making a 30 5 MBL2 cache and 8 memory controllers with 2 GDDR5 channels each The maximum number of cores and total card memory varies with Intel Xeon Phi coprocessor SKU refer to the Intel Xeon Phi Coprocessor Specification Update for information Communication around the ring follows a Shortest Distance Algorithm SDA Co resident with each core structure is a portion of a distributed tag directory These tags are hashed to distribute workloads across the enabled cores Physical addresses are also hashed to distribute memory accesses across the memory controllers Intel Xeon Phi Coprocessor Datasheet Document ID Number 328
28. EM Bracket Installation Toe to gi b Install 4 M3 x 6mm Flat Head Screws torque 6inch Ibs shown in Figure 3 28 Figure 3 28 OEM Bracket Installation KE aen E Overlap Lid Units Clearance Lid Units At this point clearance lid units are ready to be mounted in the chassis Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 43 intel 4 Replace Lid on Overlap Lid Units Only a Insert tabs into slots in card assembly shown in Figure 3 29 Figure 3 29 Replace Lid on Overlap Lid Units A r Tabs inserted correctly b Install the lid s screws M3 x 6mm Flat head torque 6 inch Ibs shown in Figure 3 30 Figure 3 30 Replace Lid on Overlap Lid Units cont Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 44 intel 4 Intel Xeon Phi Coprocessor Pin Descriptions 4 1 PCI Express Signals The PCI Express connector for the Intel Xeon Phi coprocessor is a x16 interface and supports signals defined in the PCT Express Card Electromechanical Specification Signals called out in the PCI Express specification but not used on the Intel Xeon Phi coprocessor are listed as not used in Table 4 1 The symbol N at the end of a signal name indicates that the active or asserted state occurs when the signal is at a low voltage level When _N is no
29. Intel Xeon Phi coprocessor card with assembled thermal solution e One Intel Xeon Phi coprocessor card extender bracket e Four M3 x6mm flat head screws Note The SE10X 7120X and 7120D 5120D SKUs are not shipped with the extender bracket Figure 3 22 Contents of Intel Xeon Phi Coprocessor Package Shipment O Intel Xeon Phi Passive SKU Assembly G10078 001 4x M3 x 6mm Flat Head Screw Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 40 3 5 1 Bracket Installation Steps 1 Determine Lid Type If the lid type is overlap where the lid covers the top mounting holes as shown in Figure 3 23 then go to Step 2 If the lid type is clearance where the lid has cut outs for mounting holes as shown in Figure 3 24 then go to Step 3 Figure 3 23 Overlap Lid Figure 3 24 Clearance Lid Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 41 intel 2 Remove Overlap Lid a Remove 2 of the M3x6mm screws retaining the lid as shown in Figure 3 25 Figure 3 25 Overlap Lid Removal b Remove Lid Take care not to bend tabs as shown in Figure 3 26 Figure 3 26 Tilt Overlap Lid and Slide as shown to Disengage Tabs Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 42 intel 3 Install OEM Bracket a Insert the OEM bracket into the Intel Xeon Phi coprocessor card assembly as shown in Figure 3 27 Figure 3 27 O
30. MI Discrete Sensors The SMC s IPMI discrete sensors are defined here because the meaning of each discrete bit cannot be easily derived from the SDR definition Sensor Status The status sensor reports the state of several critical signals on the card such as thermtrip VR phase fault VR hot UV OV Alert and PCI Express Reset The sensor is not mirrored as a register on the in band register interface Status Sensor Report Format em mm P2E RST PCI Express reset asserted e Fans boosted 5 P12V UVOV 9 P12V under voltage over voltage signal asserted e Fans boosted and VR output disabled VR2 HOT 9 VR2 Hot signal asserted Fans boosted and PROCHOT asserted VR1 HOT e VR1 Hot signal asserted Fans boosted and PROCHOT asserted 2 VR2 PHSFLT VR2 Phase Fault asserted Fans boosted and VR output disabled This state is latched until power off 1 VR1 PHSFLT VR1 Phase Fault asserted Fans boosted and VR output disabled This state is latched until power off THERMTRIP Coprocessor thermtrip asserted Fans boosted and VR output disabled This state is latched until power off Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 6 7 SMC LED ERROR and Fan PWM The SMC firmware drives the LED ERROR pin as follows Table 6 27 LED Indicators 0 5HZ Blink e In boot loader mode 2HZ Blink e Firmware update in progress 8HZ Blink 9 Operational code executing Identify Blink 2 short blink
31. OFFICERS AND EMPLOYEES OF EACH HARMLESS AGAINST ALL CLAIMS COSTS DAMAGES AND EXPENSES AND REASONABLE ATTORNEYS FEES ARISING OUT OF DIRECTLY OR INDIRECTLY ANY CLAIM OF PRODUCT LIABILITY PERSONAL INJURY OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN MANUFACTURE OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or go to http www intel com design literature htm This document co
32. SDK packaged in the coprocessor software stack or MPSS http software intel com contains documentation on programming the power and time registers The Out Of Band mechanism is explained in sections 6 6 3 6 1 and 6 6 3 6 2 Out of Band PCI Express SMBus IPMB Management Capabilities The Intel Xeon Phi coprocessor PCI Express card exists as part of a system level ecosystem In order for this system to manage its cooling and power demands the Intel Xeon Phi coprocessor telemetry must be exposed to ensure that the system is adequately cooled and that proper power is maintained Manageability code running elsewhere in the chassis through the SMC can retrieve SMC sensor logs sensor data and vital information required for robust server management Note that logging in this context is completely separate from and has nothing to do with the MCA error log The SMC public interface SMBus is a compliant IPMB interface It supports a minimal IPMB command set in order to interact with manageability devices such as BMCs and the Manageability Engine ME The IPMB implementation on the SMC can receive additional incoming requests while responses are being processed This enables the interleaving of requests and responses from multiple sources using the SMC s IPMB thus minimizing latency Upon initial power on or restart the SMC selects an IPMB slave address from the range 0x30 Ox4e in increments of 2 e g 0x30 0x32 0x34 etc
33. al routing on baseboard and 12V filter per card e All power to the card is supplied through the connector e There is no auxiliary 2x4 or 2x3 power connector on the card e Supports vertical straddle or right angle mating connectors e On board SMC The manageability features and software capabilities remain the same as for other Intel 9 Xeon Phi coprocessor products e To allow for system design innovation and differentiation Intel will ship only the assembled and fully functional PCB without heatsink or chassis retention mechanism This allows system designers to implement their own cooling solution and connector of choice Due to presence of GDDR5 memory components on the backside of the DFF board a custom cooling design must comprehend both sides of the DFF product e Baseboard designers must ensure the signal integrity of all PCI Express signals as they pass the connector of choice and reach the connector fingers of the DFF product Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 13 61 Figure 2 5 Mida 7120D 5120D Dense Form Factor Topside E L a Det e oof sat Sar Se Z vena ba da tas on U M INTEL M C 11 INTEL CONFIDENTIAL QCL5 Intel Xeon Phi Coprocessor Datasheet 14 1925120251 IC connector SMC 10131 morc ro e e 200006 e epu Intel Xeon Phi Coprocessor silicon ne
34. alogous thermal behavior of Tease Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 33 intel Figure 3 17 SE10X 7120X SKU Coprocessor Case Temperature Tcase vs Power Temperature 9C 50 100 150 Intel Xeon Phi Coprocessor Si Power W For the region A B the cooling solution must maintain the case temperature below 95 C which will in turn maintain the coprocessor silicon junction temperature below 104 C Assuming an air cooled heat sink at a maximum coprocessor power dissipation of 198W Figure 3 9 and an inlet air temperature of 459C the following equation between coprocessor junction to case and case to air heat sink rating can be used to determine the minimum necessary performance of a cooling system Tiunction 1 jc N CPU power Pca req CPU power T Tambient The heat sink must have a Vea req value adequate to keep the coprocessor junction temperature at or below 104 C The value for is a characteristic of the Intel Xeon Phi coprocessor and may be treated as 0 047 a constant As the coprocessor power level goes down region B C it is desirable to keep the junction temperature at or below a target temperature here shown at 82 C Since each coprocessor is programmed at the factory with the actual control temperature Teontrol a sophisticated cooling system may continuously read the junction temperature from the card SMC and compare it to the programmed
35. and running normally For cards with a TDP of 250 W or less the deassertion point is 15 W lower than PL1 For 300 W cards the deassertion point is 20 W below PL1 PLO is normally set to a higher power threshold than PL1 By default it is set to 125 of TDP and the time duration allowed at this power level is 50 ms If these conditions are met the SMC will use the thermal throttling mechanism to force the coprocessor to the lowest operating frequency which is around 600 MHz The power reduction from PLO is expected to be much greater than PL1 The thermal throttling state will continue until the total coprocessor power has dropped 40 W below PLO When PLO is exceeded the initial change in power consumption is a result of the lower operating frequency The coprocessor will also reduce the CPU core voltage to a value that is appropriate for the lower frequency and this will provide additional power savings The voltage reduction takes place 3 400 msec after PLO throttling is asserted Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 65 intel 6 6 Note that the PL1 PLO default thresholds are intended to be percentages of the TDP and the SMC will dynamically determine actual values for the thresholds during coprocessor boot up No user intervention is necessary to enable power threshold throttling System administrators may program PL1 PLO thresholds and their respective time durations The Software Development Kit
36. ate occurs when that signal is at a low voltage level The following notations are used to describe the signal type oc Ss eee Power 12V Power supply and GND inputs to the 5120D are sourced from the j baseboard On the 5120D the 3 3V_AUX power supply is not 3 3V electrically routed on the board The baseboard may choose either to oo connect 3 3V_AUX supply to this pin or to leave it as No Connect Indicates the pin is not defined and may be used for future products NC next to this type of signal indicates that this pin must not be routed on the baseboard Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 47 ntel Table 4 2 5120D DFF SKU Pinout me we me m wem sao II 83 GN X 413 0 814 PEU 6 REFCLK O 8155 0 A5 GN gt WC 25 24 LN NN B18 GND mmr 18 GND Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 48 ntel Table 4 2 51200 DFF SKU Pinout 1 RI mme o ae se mm 6 fee e es mm 9 6 9e ww fm 3 ome ss 5 16 he eo ee me 1 se ee frem 5 9 vm 9 9 L3 mo
37. ate the card in a system that has multiple cards Table 6 12 Set SM Signal Request Format Ox e Signal e 1 Identify e All other values reserved Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 72 zy pu D Table 6 12 Set SM Signal Request Format Continued Description 2 0x e Action e If Signal is 1 e 1 Assert Start the identify blink code e 2 Revert Return to normal operation All other values reserved Table 6 13 Set SM Signal Response Format Ox Compcode 0x00 Normal Oxc7 Request Length Invalid Oxc9 Parameter Out of Range Oxcc Invalid Field 6 6 3 7 OEM Commands Table 6 14 OEM Command Details OEM 0x00 e OEM Set Fan PWM Adde OEM 0x04 e OEM Get POST Registe GEM 0x05 e OEM Assert Forced Throttle 0x3e QEM oe OEM Enable External Throttle Ox3e OEM 0x07 e OEM Get Throttle Reason 6 6 3 7 1 OEM Set Fan PWM Adder The Set Fan PWM Adder command allows a PWM percentage to be added to the final fan cooling algorithm for additional cooling based on chassis requirements Table 6 15 Set Fan PWM Adder Command Request Format Ox e PWM percent to add to standard cooling 0x00 0x64 e All other values are reserved Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 73 intel Table 6 16 6 6 3 7 2 Table 6 17 Table 6 18 6 6 3 7 3 Table 6 19 Table 6 20 6 6 3 7 4 Intel Xeon Phi Coprocessor Datash
38. ce Intel Xeon Phi Coprocessor Thermal Management Thermal management on the Intel Xeon Phi coprocessor card is achieved through a combination of coprocessor based sensors card level sensors and inputs and a coprocessor frequency control circuit Reducing card temperature is accomplished by adjusting the frequency of the coprocessor Lowering the coprocessor frequency will reduce the power dissipation and consequently the temperature The coprocessor carries in it a factory calibrated Digital Temperature Sensor DTS that monitors coprocessor temperature also called junction temperature Tiunction Data from this sensor is available to the BMC or other system software via both in band direct software reads and out of band over the PCI Express SMBus interface Refer to chapter titled Manageability for more information on how to read the junction temperature System management software can use this data to monitor the silicon temperature and take any appropriate actions Systems that adjust airflow based on component temperatures must monitor the coprocessor s DTS to ensure sufficient cooling is always available In addition to making thermal information available to system manageability software the DTS is constantly comparing the coprocessor temperature to the factory set maximum permissible temperature called Tihrottje If the measured temperature at any time exceeds Trhrottle a state also known as PROCHOT then the coprocesso
39. complete list of documentation contact your local Intel representative or go to www intel com Related Documents Boman Intel Xeon Phi Coprocessor Specification Update Intel Xeon Phi Coprocessor System Software Developer s Guide Intel Xeon Phi Coprocessor Instruction Set Reference Manual Intel Xeon Processor Family External Design Specification EDS Volume 1 PCI PCI Express Card Electromechanical Specification Revision 2 0 Card Electromechanical Specification Revision 2 0 NAS 3 PCI ci RI 225W 300W High Power Card Electromechanical Specification N A 3 Revision 1 0 Intelligent Platform Management Bus Communications Protocol Specification v1 0 Intelligent Platform Management Interface Specification v2 0 Note 1 http www intel com content www us en processors xeon xeon technical resources html Note 2 http software intel com en us forums intel many integrated core Note 3 http www pcisig com Conventions and Terminology Terminology This section provides the definitions of some of the terms used in this document General Terminology Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 7 intel Table 1 2 General Terminology Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 8 intel 2 Intel Xeon Phi Coprocessor Architecture 2 1 Intel Xeon Phi Coprocessor Product Overview Figure 2 1 Inte
40. e The client sends requests to the SMC using one or more SMC SMBus Write Block commands then at a later time reads the response using one or more SMBus Read Block commands 6 6 2 1 Polled Master Only Protocol Clarifications The polled master only protocol is loosely based on the IPMI defined SSIF protocol however there have been a few changes made and ambiguities clarified in order to make the protocol more reliable e The I2C address for the polled master only protocol and the IPMB protocol are the Same and work together transparently e PEC bytes are required for all write commands and are returned with all valid read responses e The maximum SMBus data length is restricted to 32 bytes e The SMC ignores write commands that occur while it is internally processing a previous command e The SMC does not return valid data while busy internally processing a command e A sequence number has been added to help identify the condition where a new write command using the same NetFn and command as the last command sent was corrupted during transit Without this precaution two sequential requests of the same type i e Get Sensor Reading could result in one sensor s reading being mistaken for the other s e SMBAlert is not supported Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 67 intel 6 6 2 2 SMBus Write and Read Block Command Numbers 6 6 2 3 Write Description Table 6 1 SMBus Write C
41. e Manager mode which adds functionality such as setting power throttle threshold values and time windows Intel Xeon Phi Coprocessor System Manageability Architecture Customer Management Software Host Drivers Custom Firmware Intel Chipset Coprocessor Metrics Drivers Error Handler OS In operational mode the SMC monitors power and temperatures within the Intel Xeon Phi coprocessor and through sensors located on the PCI Express card This information is then used to control the power consumed by the PCI Express card and the rotating speed of the fan s within the PCI Express card cooling system The SMC provides status information temperature fan speed and voltage levels to the Intel Xeon Phi coprocessor drivers which then can be provided to the end user via a GUI The SMC provides a master slave SMBus using the IPMI IPMB protocol so that a platform BMC or ME can control the SMC The SMC on the Intel Xeon Phi coprocessor has the following capabilities e General manageability features e Board ID and SKU definition e Unique identifying number e Fan Control Read fan RPM e Thermal throttling and throttle monitoring Force throttling of the coprocessor Monitor time in throttled state Separated status if power throttle threshold throttling vs over temperature throttling e Card level power throttle threshold capping Power Throttle Threshold Values and 1 tracked o
42. e coprocessor package can reduce the core voltage and enter Deep pC3 The fan on active SKUs can slow to minimum speed VRs enter low power mode Figure 5 5 Package C3 and Memory M2 state Full bandwidth enabled From M1 state memory can be put in self refresh mode to enter the M2 state further reducing memory power Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 56 Figure 5 6 Package C6 and Memory 12 state Full bandwidth enabled The coprocessor OS can reguest that the coprocessor enter package C6 state Core voltage is shut down Coprocessor power is lt 10W in this state Figure 5 7 Package C6 and Memory M3 state Full bandwidth enabled The memory clock can be fully stopped reducing memory power to its minimum state 5 3 P states and Turbo Mode P states or Performance states are different frequency settings requested by the host OS or application when the cores are in the CO active executing state Switching between P states is done by the coprocessor when the OS or application determines that more or less performance is needed All active cores run at the same P state frequency as there is only one clock source in the coprocessor 1 Value may be revised following silicon characterization Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 57 ntel Each frequency setting of the coprocessor requires a specific voltage identification VID voltage
43. e for the 5110P at 225W TDP 23 3 7 Airflow Requirement vs Inlet Temperature for the 31S1P at 270W TDP and SE10P 7120P 3120P at 300W TDP24 3 8 Airflow Requirement vs Inlet Temperature for the 5110P Card at 245W TDP 25 3 9 SE10X 7120X Power Profile for Coprocessor Intensive Workload all values in Watts 26 3 10 SE10X 7120X Power Profile for Memory Intensive Workload all values in Watts 27 3 11 5120D Power Profile Coprocessor Centric all values in Watts seeeee 28 3 12 5120D Power Profile Memory Centric all values in Watts cs ce e c e e e c e e e K eee 29 3 13 7120D Power Profile Coprocessor Centric all values in Watts seeeee 30 3 14 7120D Power Profile Memory Centric all values in Watts cs ce e c eee 31 3 15 7120D 5120D VR Thermal Sensors for Custom Cooling Consideration 3 16 SE10X 7120X SKU Coprocessor Junction Temperature Tjunction vs Power 33 3 17 SE10X 7120X SKU Coprocessor Case Temperature Tcase vs Power 34 3 18 SE10X 7120X Board Top 510 nnne enema eene 8888 449 36 3 19 _5E10X 7120X Board Bottom Side noa cai aaa aia aa uro lea ia a ras 37 3 20 7120D 5120D Board Top Side eee enm meme nnn 449 38 3 21 7120D 5120D Board Bottom Side se ae erai e aa ni a ai a i a i i le i a i a aa 39 3 22 Contents of Intel Xeon Phi Copr
44. ed according to the graph and table in Figure 3 7 Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 22 intel Figure 3 6 Airflow Requirement vs 45 C Inlet Temperature for the 5110P at 225W TDP 225 W Card Flow vs Inlet Temperature 25 20 3 15 E Total Flow ft 3 min 3 10 Primary ft 3 min TW Secondary ft 3 min 20 30 40 50 Inlet Temperature C Pr 37 9009 as us 79 37 9009 a ug 8 37 29009 al 2 083 3 00m ao 2 8 38 a 1 1236 2098 238 02 Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 23 intel Figure 3 7 Airflow Requirement vs Inlet Temperature for the 31S1P at 270W TDP and SE10P 7120P 3120P at 300 TDP 270 300 W Card Flow vs Inlet Temperature gt Total Flow ft 3 min O Primary ft 3 min Secondary ft 3 min 0 25 30 35 40 45 5 Flow ft min O un 0 P Card Inlet Temperature T C Total Flow ft 3 min Primary ft 3 min Secondary ft 3 min Card dP inHa0 20 14 4 10 5 14 7 10 8 11 1 11 3 T 4 5 4 7 5 NIN IN WIN Fe 15 3 15 6 N IN TN IP 12 3 12 7 16 3 16 7 17 1 17 6 NIN 00 IN 13 4 13 8 14 3 14 8 15 3 15 8 16 4 WIN O Fo 18 5 19 1 19 7 20 3 21 7 22 5 23 3 24 3 25 3 26 5
45. ed to be enabled each time a reset or power cycle event occurs Its state is not persistent across these events Document ID Number 328209 003EN intel When the baseboard asserts PROCHOT drives active low signal the coprocessor OS immediately drops the frequency to lowest rated value Pn within 100us of asserting PROCHOT If PROCHOT is deasserted in less than 100ms the coprocessor frequency is restored to the original operational value either P1 or turbo if baseboard continues to assert PROCHOT for more than 100ms the coprocessor OS will respond by reducing the voltage ID VID settings to match the lowest frequency leading to further power savings Upon subsequent deassertion of PROCHOT the VID settings are first restored to support operational frequency followed by the coprocessor frequency itself If a baseboard does not support the B12 capability the external throttle signal via pin B12 can be disabled using this command The card can still be throttled using the SMC by sending the Assert Forced Throttle Command referenced above Table 6 21 Enable External Throttle Request Format OEM Enable External Throttle Ox e Disable external throttle signal e 1 Enable external throttle signal e All other values are reserved Table 6 22 Enable BE x Throttle Response Format E 9 Compcode e 0x00 Normal e OxcO Busy 6 6 3 7 5 OEM Get Throttle Reason The Get Throttle Reason command returns the state of the three t
46. eet 74 Set Fan PWM Adder Command Response Format Description 9 Compcode e 0x00 Normal e Oxc9 Parameter out of range OEM Get POST Register The Get POST Register command allows the BMC to obtain the last POST code written to the SMC by the coprocessor The SMC does not modify this value in any way Get POST Register Request Format e NETFN OEM Get POST Register Response Format Ox 9 Compcode e 0x00 Normal e 32 bit POST code in little endian format OEM Assert Forced Throttle The Assert Forced Throttle command allows the BMC to cause the SMC to assert the PROCHOT pin to the coprocessor Assert Forced Throttle Request Format OEM Assert Forced Throttle 0x e 0 Deassert forced throttle e 1 Assert forced throttle e All other values are reserved Assert Forced Throttle Response Format Ox 9 Compcode e 0x00 Normal OEM Enable External Throttle The Enable External Throttle command causes the SMC to enable a pin on the baseboard connector pin B12 allowing the baseboard BMC to directly assert the PROCHOT signal The baseboard requirements to enable this pin on the baseboard are described in section 4 1 1 The signal to assert emergency throttling via pin B12 is active low on the baseboard and is driven by the BMC However the pin must first be enabled by the SMC This can be accomplished by sending the Enable External Throttle command as described in this section The pin will ne
47. el Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 38 Figure 3 21 71200 51200 Board Bottom Side Bottom side capacitors 3 4 4 Mechanical Shock and Vibration Testing Table 3 5 shows the recommended shock and vibration guidelines and dynamic load shift specifications Table 3 5 Dynamic Load Shift Specification 50g trapezoidal V 170in s Board U kaged Shock 5Hz 0 010 82 to 20Hz 0 02g2 Hz slope up 20Hz to 500Hz 0 02g7 Hz flat Input acceleration is 2313g RMS 10mins per axis in all 3 axis Board Unpackaged Random Vibration Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 39 intel Table 3 5 Dynamic Load Shift Specification 25g trapezoidal Varies by system weight 20 39lbs System Unpackaged Shock 225 in sec 40 79155 205 in sec drops 2x each of 6 faces 5Hz 0 001g2 Hz to 20Hz 0 001g2 Hz slope up System Unpackaged Random 20Hz to 500Hz O 0 001g Hz flat Vibration Input acceleration is 2 20g RMS 10mins per axis in all 3 axis 3 5 Intel Xeon Phi Coprocessor PCI Express Card Extender Bracket Installation Intel Xeon Phi coprocessor cards are shipped without the PCI Express bracket also known as extender bracket being installed on the card The purpose of this bracket is to interface with the chassis mechanical card guides for standard full length PCI Express cards In the shipped package customers should expect to find e One
48. esigners and integrators an opportunity to fit these SKUs into their custom designed chassis These SKUs have GDDR components on the back side that must be cooled in addition to the front side where the coprocessor resides This section documents thermal and mechanical specifications and guidelines that would be useful to developers of custom designs Thermal Considerations Figure 3 9 and Figure 3 10 show a schematic representation of the power profiles of the Intel Xeon Phi coprocessor SE10X 7120X products Figure 3 11 to Figure 3 14 show a schematic representation of the power profiles of the 7120D 5120D product SE10X 7120X Power Profile for Coprocessor Intensive Workload all values in Watts Intel Xeon Coprocessor GDDR VR Inductor Topside GDDR Backside Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 26 intel Figure 3 10 SE10X 7120X Power Profile for Memory Intensive Workload all values in Watts les 1 9 12 1 9 ES las 1 9 1 9 EG BEBE Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 27 intel Figure 3 11 51200 Power Profile Coprocessor Centric all values in Watts VR FET VR Inductor op MOZA oa o Ke 09 OP Kor 04104 Topside GDDR Intel Xeon Phi Coprocessor Ba BS G 3 H 1 3 ES Backside LS 1 3 22
49. essure drop assuming a multi card installation conforming to the PCI Express mechanical specification is 0 21 inch H20 at this flow rate Note For systems with reversed airflow the corresponding airflow requirement is expected to be within 5 tolerance of the values shown in the following tables Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 21 intel If the system is able to provide a temperature lower than 459C at the card inlet then the total airflow can be reduced according to the graph and table in Figure 3 6 If the 5110P SKU is powered by a 2x4 and a 2x3 connector the card can support an additional 20W of power for maximum TDP of 245W see Section 2 1 5 for more details In this case the corresponding airflow requirement for cooling the part as a 245W card is shown in Figure 3 8 3 3 2 2 Airflow Requirement for SE10P 7120P 3120P 31S1P Passive Cooling Solution In order to ensure adequate cooling of the SE10P 7120P 3120P 300W and 31S1P 270W SKUs with a 459C inlet temperature the system must be able to provide 33 ft min of airflow to the card with 7 2 ft min on the secondary side and the remainder on the primary side The total pressure drop assuming a multi card installation conform ing to the PCI Express mechanical specification is 0 54 in H20 at this flow rate If the system is able to provide a temperature lower than 459C at the card inlet then the total airflow can be reduc
50. f current from each of the power rails connected to the coprocessor card Below is the current and power drawn from each source during the power on phase of the SE10P SE10X SKU e 12V 2x4 connector 5 4A 64W A peak current of 7 1A for duration of 40us e 12V 2x3 connector 36W e 12V PCI Express slot pins 1 6A 20W 9 3 3V PCI Express slot pins 1 3A 5W e Measured total power consumption 120W The above power on measurements were taken with a single coprocessor using a specific open chassis system It is not indicative of the coprocessor behavior in all types of systems in which the coprocessor will be used The current and power values are meant to be guidelines for system power planning and not specification of the Intel Xeon Phi Coprocessor 5110P SKU Power Options Most HPC applications running on the 5110P SKU are expected to draw less than 225W but the card is designed to support power surges above 225W If the power surge goes above 236W for more than 300ms then the SMC on the card will instruct the Intel Xeon Phi coprocessor to drop its operating frequency by approximately 100MHz thus reducing power dissipation by approximately 10W If power surge goes above 245W for more than 50ms then the SMC will assert the PROCHOT N signal to the coprocessor Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 53 intel which will cause the frequency to drop to the minimum poss
51. f the step changes may be slightly longer than 10uS Figure 3 3 Entering and Exiting Thermal Throttling PROCHOT 1ms Minimum from Thermal Sensor Filterin 1ms Minimum before next Thermal Event on wi nai AAA 1 PROCHOT PROCHOT Activated ns Deactivated 10 5 30ns V k Step Size of 1 D EA c a 3 ET 1 pl be S0ns Pn P5 P4 P3 P2 P1 PO Activation of PROCHOT by the on die Digital Temperature Sensor DTS initiates the sequence of stepping down the processor frequency from P1 to Pn Deactivation of PROCHOT reverses the process 3 3 Intel Xeon Phi Coprocessor Thermal Solutions There are two types of thermal solutions to address the Intel Xeon Phi coprocessor power limits a passive solution for most SKUs as indicated in Table 2 1 which relies on forced convection airflow provided by the system and an active solution on the 3120A and 7120A SKUs which uses a high performance blower The active solution is designed to operate in an adjacent card configuration such that the impedance from a nearby flow blockage is accounted for within the design Both passive and active solutions come with cooling backplates that augment the stiffness of the Intel9 Xeon Phi coprocessor card by counteracting the preload applied by the primary side housing the coprocessor This also protects the structural integrity of the coprocessor and GDDR packages during a shock event and to provide a protective cover Given the re
52. faces This allows the SMC to have direct connection to the coprocessor I2C interface an on board I2C sensor bus and a third interface through the SMBus pins of the PCI Express connector to the system management solution The I2C interface between the SMC and coprocessor is used for polling coprocessor thermal status information The sensor bus allows board thermal input power and current Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 11 2 1 3 Figure 2 4 sense monitoring for system fan and power control This information is forwarded to the coprocessor for power state control The SMBus interface can be used by system for chassis fan control with the passive heat sink card and for integration with the Node Management controller in the platform Communication with the system baseboard management controller BMC or peripheral control hub PCH occurs over the SMBus using the standard IPMB protocol See chapter on manageability for more details Intel Xeon Phi Coprocessor Silicon Intel Xeon Phi Coprocessor Silicon Layout Coprocessor Coprocessor Coprocessor Core Core Core 2 Cache 828 L2 Coprocessor Coprocessor Coprocessor Coprocessor Core Core Core Core L2 DESEE 2 NN RM L2 28 L2 IPN IPN Coprocessor Coprocessor Coprocessor Coprocessor Core Core Core Core 2 BEES T EE NM NN L2 NN Coprocessor Coprocessor Coprocessor Coprocessor Core
53. g on 5120D Data Pins Each pin on the PETp n 15 0 and PERp n 15 0 buses requires a 0 1uF 0402 AC coupling capacitor on the baseboard The capacitors should be located for differential pair traces at the same location along the differential traces that is they should not be staggered from one trace to the other and should be as close to each other as possible Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 51 Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 52 Table 5 1 5 1 Power Specification and Management Power management on the Intel Xeon Phi coprocessor is primarily managed via the on board resident coprocessor OS with hardware controlled functionality Table 5 1 shows estimates for coprocessor power states and respective memory power states along with estimates of corresponding card power and wakeup times Intel Xeon Phi Coprocessor Power States 7120A D 7120P X Coprocessor 3120A P SE10P X 5110P 5120D Power State 31S1P Power Watts Power Watts Power Watts Wakeup Time 39 5509 ae s as as mm pe Not supported Notes 1 Refer Section 5 1 for information on TDP 2 CO matches the coprocessor TDP other power states are specifications As the Intel Xeon Phi coprocessor is being powered on it is expected to draw measurable amounts o
54. g solutions the SMC will sample a GPIO pin on startup to determine if the closed loop fan control algorithm and monitoring should be disabled on certain SKUs Additionally the SMC supports enabling and disabling an external assertion path from the baseboard to the card pin B12 This allows an external agent such as a BMC or ME to force throttle the Intel Xeon Phi coprocessor during thermal events The SMC is the conduit for doing so Pin B12 defined as reserved in the PCI Express specification has been renamed PROCHOT_N on Intel Xeon Phi coprocessor and is driven by 3 3V power This pin is held in active high deasserted state by the card SMC in the default state and must be driven active low by the baseboard to exert throttling An OEM IPMB message from the baseboard to the SMC is required to enable the external throttling mechanism See Section 4 1 1 for baseboard implementation details Catastrophic Shutdown Detection Catastrophic shutdown is the act of the Intel Xeon Phi coprocessor silicon shutting itself down to prevent damage to the device caused by overheating The SMC monitors THERMTRIP_N to detect this event When THERMTRIP_N is asserted low the SMC detects this and immediately forces the fan s to full speed and shuts down the VRs Removal of power is required to reset the microcontroller to a Known start point Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 63 intel 6 4 Host
55. he PCI Express card The system provides sensor telemetry information for management by in band host software and out of band software via the PCI Express SMBus The SMC also provides additional functionality as described in this chapter The SMC is a microcontroller based thermal management and communications system that provides card level control and monitoring of the Intel Xeon Phi coprocessor Thermal management is achieved through monitoring the Intel Xeon Phi coprocessor and the various temperature sensors located on the PCI Express card Card level power management monitors the card input power and communicates current power conditions to the Intel Xeon Phi coprocessor SMC features include e Four thermal sensor inputs inlet outlet coprocessor die and GDDR e Power alert thermal throttle and THERMTRIP signals The SMC connects to coprocessor silicon via the following I2C and out of band signals e In band Communication Software access to thermal and power metrics via Ganglia gmond exposed via standard Ethernet port Accessible via Control Panel GUI and API e Out of band Communication Access to the SMC via the PCI Express SMBus using the IPMI IPMB protocol 50ms sampling rate for power data Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 61 intel Figure 6 1 The manageability architecture also provides support for the Intel Xeon Phi coprocessor in Nod
56. hrottle sources PL1 RAPL1 PLO RAPL2 and the external B12 pin Table 6 23 OEM Get Throttle Reason Request Format Command OEM Get Throttle Reason Table 6 24 OEM Get Throttle Reason Response Format Ox 9 Compcode e 0x00 Normal e OxcO Busy 1 Ox Bitmask of throttle reasons e 0 RAPL1 PL1 1 RAPL2 PLO e 2 External B12 pin 6 6 3 8 Other IPMI Related Information The SMC SEL is a circular log supporting a minimum of 64 log entries It is resilient to corruption retaining information across an unexpected power loss Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 75 The sensor names in the IPMI SDR are static and do not change from release to release The IPMI sensor numbers are not static and may change between releases hence the sensor number should be discovered during the normal sensor discovery process because additional sensors may be added in the future During the normal sensor discovery process reading the SDR returns the sensors available on the coprocessor There is a sensor name and sensor number associated with each sensor Once the sensor number is determined by comparing the sensor name that is desired to be read the sensor number may be used by the management firmware for reading a particular sensor It is important that the firmware does not hard code the sensor number as it may change in future releases It is strongly recommended to use the sensor name if it is hard coded
57. ible value refer to Section 3 2 1 The level and duration of the power surge are programmable by the end user refer chapter on manageability for more details Additionally there may be applications that draw up to 245W This should be taken into account when choosing one of the three modes of operation as listed below Users can install both the 2x4 and 2x3 power connectors for total available power of 300W In this case the card may draw up to 245W of power depending on the application This mode ensures sufficient power is available and reduces the risk of throttling Users may see power dissipation approach 245W as applications become more highly tuned to take advantage of the Intel Xeon Phi coprocessor architecture Users can install either the 2x4 connector only or two 2x3 connectors for total available power of 225W The card is designed to support power surges of up to 236W If the power surge goes above 236W for more than 300ms then the SMC on the card will instruct the Intel Xeon Phi coprocessor to drop its operating frequency by approximately 100MHz thus reducing power dissipation by approximately 10W If a greater card power limitation is desired users can configure the SMC to further limit the power draw of the 5110P SKU ensuring compatibility with less capable power delivery systems refer to Section 6 5 5 2 Intel Xeon Phi Coprocessor Power States Figure 5 1 to Figure 5 8 are a schematic rep
58. into the management firmware to discover the sensor number this will ensure the correct sensor is read and will return valid data with future releases of the SMC firmware Table 6 25 is a list of the current sensor names Sensor Description Table 6 25 Table of Sensors Sensor Type Intel Xeon Phi Coprocessor Datasheet 76 power pcie power 2x3 power 2x4 power pv power vddq power vddg avg powerO avg power1 Instpwr Instpwrmax VOLTAGE pv volt vddq volt vddg volt TEMP east temp gddr temp west temp pv vrtemp vddq temp vddg temp proc temp exhst temp inlet temp fan pwm Power measured at the PCI e edge fingers input Power measured at the 2x3 Aux connector input N A for 5120D Power measured at the 2x4 Aux connector input N A for 5120D MN mm Temperature sensor on the eastern most side of the board N A for 5120D Temperature sensor on the western most side of the board N A for 5120D Temperature reported by the Intel R Xeon Phi TM chip DTS A Document ID Number 328209 003EN Table 6 25 6 6 3 9 6 6 3 9 Table 6 26 Table of Sensors Sensor Type Sensor Description fan tach Fan tach read by SMC N A for passive SKUs 5120D OTHER status Critical signal states described in the datasheet Tcritical Thermal monitoring control value reported by the Intel R Xeon Phi TM chip Tcontrol Fan thermal control value reported by the Intel R Xeon Phi TM chip SMC IP
59. ion has been renamed PROCHOT on the Intel Xeon Phi coprocessor and is driven by 3 3V power This pin is held in inactive high state by the card SMC and must be driven active low by the baseboard to exert throttling See Section 4 1 1 and Chapter 6 for details WAKE N Not PCI Express Wake Signal Used EXP JTAG 5 1 PCI Express JTAG Interface Used 4 1 1 PROCHOT N Pin B12 System baseboard routing to the PROCHOT N pin must take into consideration the following details e PROCHOT N pin is driven by the 3 3V power rail e PROCHOT pin is connected to a pull down of 100k ohm on the card e The input signal arriving at the pin from the baseboard must meet the following characteristics VIH min 2 2 7V VIL max 0 5V Rise Fall times max 240ns e The baseboard implementation can choose to be either push pull or open drain In particular an open drain implementation must provide a pull up resistor of 10k ohm or less on the baseboard to counteract the pull down on the card Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 46 4 2 4 3 intel Supplemental Power Connector S The Intel Xeon Phi coprocessor gets only maximum 75W from the PCI Express connector per the PCI Express specification The 2x4 and 2x3 supplemental power connectors on the coprocessor card provide the additional 12 volt power needed by the coprocessor Per the PCI Express specifications the 2
60. l Xeon Phi Coprocessor Board Schematic ANNEL 8 CH Power 10 gt Connectors TM Intel Xeon Phi Coprocessor 2x4 12V 150W E Silicon NNEL 13 gt EE es ERI GL TINNY PCle Gen2 x16 waasi PL TINNVHO Fan Control PCle 12V 65W 3 3V 10W Notes 1 On board fan is available on Intel Xeon Phi Coprocessor 3120A and 7120A SKUs only The Intel Xeon Phi coprocessor consists of the following primary subsystems e Many Integrated Core MIC coprocessor silicon and GDDR5 memory e System Management Controller SMC thermal sensors inlet air outlet air coprocessor on die thermal and single GDDR5 sensor and fan only on 3120A and 7120A products see SKU matrix Table 2 1 e Voltage regulators VRs powered by the motherboard through the PCI Express connector a 2x4 150W and a 2x3 75W auxiliary power connector on the east edge of the card Along with power through the PCI Express connector the 300W SKUs need both 2x4 and 2x3 connectors to be driven by system power supplies The 225W SKU may be powered only through the PCI Express connector and the 2x4 connector Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 9 2 1 1 e PCI Express connections e The clock system is integrated in the coprocessor including an on
61. ll length card Backplate Stiffener non clamshell e Spider clip e Supports pre load forces GDDR Polycarbonate insulator Polycarbonate insulator As in the active thermal solution the duct is metallic and performs both structural and thermal roles In its fuselage function the duct provides structural support for the forces generated by the CPU thermal interface protects against shock events and channels airflow through the card In its supersink function the duct contains internal fins and heat pipes The internal heat pipes serve to transmit heat from GDDR both top and bottom side and VR components to the internal fin banks diecast blower frame and metal fuselage structure where it can be effectively transferred to the airstream The passive solution does not have a diecast blower frame as it relies upon forced airflow from the host system In place of the blower and frame an additional fin bank is added to dissipate waste heat from GDDR and VR components The fin spacing of all fin banks as well as of the CPU heat sink fin bank have been optimized for receiving system supplied airflow A backplate stiffener heat sink is used 3 3 2 1 System Airflow for 5110P SKUs In order to ensure adequate cooling of the 5110P SKUs with a 459C inlet temperature the system must be able to provide 20 ft min of airflow to the card with 4 3 ft min on the secondary side and the remainder on the primary side The total pr
62. mal interface material TIM e The gap filler used is the Bergquist 3500535 e The Intel passive heat sink is designed to nominal gaps of GDDR 0 3 0 1225 mm VR FETs 0 511 0 1225 mm VR Inductors 0 5 0 2 Table 3 4 shows the maximum heights of the different components on the SE10X 7120X and 7120D 5120D products along with the heights used in the product board design Figure 3 18 and Figure 3 19 show the front and back sides of the SE10X 7120X SKU Refer to the Intel Xeon Phi Coprocessor Thermal Mechanical Models document for the SE10X 7120X SKU Refer to the Intel Xeon Phi Coprocessor Dense Form Factor Models document for information on 5120D SKU Board Component Heights VR VRInducor Yellow i EI ox RE A We se We me 1 9 1 524 1 o Notes 1 Colors are in reference to Figure 3 18 Figure 3 19 Figure 3 20 and Figure 3 21 Intel Xeon Phi Coprocessor Datasheet 35 DRMOS VR Inductor Top side capacitor Co processor Memory VR Core VR Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 36 Bottom side capacitor ME L L b 1 B Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 37 intel Figure 3 20 7120D 5120D Board Top Side DRMOS V Coprocessor VR Inductor Topside Memory VR Capacitor Coprocessor Int
63. nt Figure 3 15 7120D 5120D VR Thermal Sensors for Custom Cooling Consideration VR thermal sensor VR thermal sensor Intel Xeon Phi Coprocessor Silicon VR thermal sensor Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 32 intel 3 4 2 Thermal Profile and Cooling The simplest cooling mechanism would involve running fans at full speed For those custom air cooled solutions that intend to be economical in fan power usage and acoustics Figure 3 16 represents three regions on the SE10X 7120X coprocessor power consumption curve relevant to system fan control Figure 3 16 SE10X 7120X SKU Coprocessor Junction Temperature Tiynction VS Power T junction Temperature 9C Kk B 100 150 200 Intel Xeon Phi Coprocessor Si Power W Region A B on the line represents the minimum necessary performance of a cooling solution to keep the coprocessor silicon temperature Tiunction below Tthrottie Of 104 C Table 3 2 during high power dissipation In this region a cooling solution based on airflow would ensure the fans are operating at 100 capacity In region B C the coprocessor power consumption is low enough that the cooling solution may be set to maintain the junction temperature at a target temperature Finally in region C D the coprocessor may need to be cooled to below the target temperature to maintain a reasonable exhaust air temperature Figure Figure 3 17 shows the an
64. nt ID Number 328209 003EN 60 6 4 6 2 intel Manageability Intel Xeon Phi Coprocessor Manageability Architecture The server management and control panel component of the Intel Xeon Phi coprocessor architecture provides a system administrator with the runtime status of the Intel Xeon Phi coprocessor installed in a given system There are two access methods by which the server management and control panel component may obtain status information from the Intel Xeon Phi coprocessor The in band method utilizes the Symmetric Communications Interface SCIF network and the capabilities designed into the coprocessor OS and the host driver to deliver the Intel Xeon Phi coprocessor status It also provides a limited ability to set specific parameters that control hardware behavior The same information can be obtained using the out of band method This method starts with the same capabilities in the coprocessor OS but sends the information to the System Management Controller SMC using a proprietary protocol The SMC responds to queries from the platform s BMC using the Intelligent Platform Management Interface IPMI protocol to pass the information upstream to the administrator or user For more information on the tools available for management see the Intel Xeon Phi Coprocessor System Software Developer s Guide System Management Controller SMC Intel Xeon Phi coprocessor manageability relies on a SMC on t
65. ntains information on products in the design phase of development All products computer systems dates and figures specified are preliminary based on current expectations and are subject to change without notice Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families Go to Learn About Intel Processor Numbers Intel Xeon Xeon Phi and the Intel logo are trademarks of Intel Corporation in the U S and or other countries Other names and brands may be claimed as the property of others Copyright 2012 2013 and 2014 Intel Corporation All rights reserved Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 2 Table of Contents 1 TO 9 ss Te c Te PR c 7 1 1 Reference Documentation eee eee eee anno eee nea aaaa raris aaa aaa ann nnam nn L2 Conventions and NNN verd vern 7 Lo TONN 7 2 Intel Xeon Phi Coprocessor Architecture ce e e e e e e KK 9 2 1 Intel Xeon Phi Coprocessor Product Overview ccc cece cece cece 555555 999 999999999494444 9 2 1 1 Intel Xeon Phi Coprocessor Board Design swsamwanwnnanananzunzunzunananza 10 2 1 2 System Management Controller SMC nnne 11 2 1 3 Intel Xeon Phi Coprocessor
66. ocessor Package Shipment eeese 40 o MERO Bc M m 41 324 Clearance Lid PA o Ano on 41 BAZ OY Nap BRENN 42 3 26 Tilt Overlap Lid and Slide as shown to Disengage Tabs eese 42 TENT 43 3 28 OEM Bracket Installation e e ee eee 43 3 29 Replace Lid on Overlap Lid 3 5 3444 rr rr 44 3 30 Replace Lid on Overlap Lid Units cont eee 44 5 1 Coprocessor in CO state and Memory in MO state sssssssssseeeeenn nnn 54 5 2 Some cores are in CO state and other cores in C1 state Memory in MO state 55 5 3 All Cores In C1 state Memory In M1 state sseeeeeeeeen nennen 55 5 4 All Cores In Package C3 State Memory In M1 auauuunnunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnen 56 5 5 Package C3 and Memory M2 state ss sss secs s sss ss sese anana neeaaea 56 5 6 Package C6 and Memory M2 state eee sees eee 4454 99999993344444 57 5 7 Package C6 and Memory M3 state sss sss sss sss s ss css nene nenea 57 5 8 Intel Xeon Phi coprocessor P States and TUrDO wsasamananananzananawananza nakama 59 6 1 Intel Xeon Phi Coprocessor System Manageability Architecture 62 6 1 Write Block Command Diagram nnn nnn 68 6 7 Read Block Command DIGG EA iaa er etienne aa n a 309 a n ai Ubi
67. ommands NN NN o E RR RR 07h Mukt Part Write Middle 08h Multi Part Write End 03h Single Read Start 03h Multi Part Read Start 09h Multi Part Read Middle 09h Multi Part Read End Figure 6 1 Write Block Command Diagram Single Part Write Slave Address YA MetFN LUN Request Sequence 17 11 ShBus CMD 02h 6 2 Humber IPMI MD IPMI Data 35 Fart Write Start Slave Address RAA l MetFN LUN Request Sequence 5 CMD 06h CMD IPMI Data 10h 7 1 6 2 Number Multi Part Write Middle Sava e M SMBusCMD 07h Length 20h Data 205 Multi Part Write End ssi aiae SMBus CMD 08h Length lt 1 20h IPMI Data 1 20 Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 68 6 6 2 4 Read Description Figure 6 2 Read Block Command Diagram Single Part Rend Bai LUR Rai paturica 58 ngih d lengt 2 Shove Address APO Save Addres Ay w MetFH LUA Response Sequence x 11 8 CMD 03h iaj 11 Linggih 20h gih 13 ST lipi CMD Compredo IPHI Dala 14h PEC Hult Part Nes PA edis Slave Address APO a Shove Addres Block 11 picis iun 17 uJ E Hunter ulti Part 8622 End Save Pres N suba ip non SS MS Si S 3 3
68. pper blocks 312 Bracket Supports preload forces e Card to system interface Sinks heat from backside a emulating full length card GDDR Polycarbonate insulator shroud In the fuselage supersink approach the duct is metallic and performs both structural and thermal roles In its fuselage function the duct provides structural support for the forces generated by the coprocessor thermal interface protects against shock events and channels airflow through the card In its supersink function the duct contains internal fins heat pipes and diecast blower frame The internal heat pipes serve to transmit heat from GDDR both top and bottom side and VR components to the internal fin banks diecast blower frame and metal fuselage structure where it can be effectively transferred to the airstream The duct also contains horizontal webs which interface to the east and west GDDR as well as to the VR FETs Together these structures dissipate heat lost from the GDDR and VR components into the air The coprocessor thermal path is separated from the GDDR and VR components and utilizes a heatsink with parallel plate fins and vapor chamber base The active solution also contains a high performance dual intake blower that operates up to 5400 rpm at 20W of motor power The blower has been designed to maximize the pressure drop capability and is able to deliver up to 35 ft min in an open airflow environment When installed on the card the blower delivers
69. quirement to dissipate backside GDDR heat within the 2 67 mm keep in height prescribed by the PCI Express specification the backplate is designed to transfer the GDDR heat from the secondary side via heat pipes to the primary side thermal solution Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 19 Figure 3 4 3120A and 7120A Active Cooling Solution For the 3120A and 7120A SKUs the Intel Xeon Phi coprocessor thermal mechanical solution utilizes a supersink approach in which a primary heatsink is used to cool the coprocessor while a metallic fuselage supersink cools the VR and GDDR components Figure 3 4 illustrates the key components of the active cooling design Exploded View of 3120A 7120A Active Solution Coprocessor Heat Sink ID Cover e Vapor chamber based e Aluminum sheet metal Soldered stamped copper fin e Printed with Intel branding bank Fuselage Supersink I O Bracket Mechanical interface to e Standard 2 slot PCI system e Structural connection to Folded sheet aluminum system Sinks heat from GDDR amp VR Soldered internal folded fins and heat pipes Intel Blower e Customized impeller geometry 7 0 BA 5400 RPM e Diecast aluminum blower Card PBA frame soldered into duct e 246mm card length 2x3 and 2x4 aux power east edge PCI Express CEM spec compliant except hockey stick KOZ Backplate Stiffener Heat Sink e Copper plate with soldered heat pipes and co
70. r will automatically step down the operating frequency or Pstate in an attempt to reduce the temperature this is often referred to as thermal throttling Once the temperature has dropped below Tthrottler the frequency will be brought back up to the original setting See Figure 3 3 below Coprocessor Datasheet Document ID Number 328209 003EN intel Within 50ns of detecting Tihrottle the DTS circuit begins stepping down the P states until Pn is reached Each frequency step is approximately 100MHz the exact value will depend on the starting frequency After each step the DTS will wait 10uS before taking the next step The number of steps or P states depends on the starting frequency and the minimum frequency supported by the processor Once Pn is reached the frequency will be held at that level for approximately 1ms or until the temperature has dropped below Tprochot whichever is longer If throttling continues for more than 100ms the coprocessor OS will reduce the voltage setting in order to further decrease the power dissipation The voltage settings are pre programmed at the factory and cannot be reconfigured Upon removal of the thermal event the process reverses and the voltage and frequency are stepped back up to the P1 state Although the process to reduce frequency is managed by the coprocessor circuits the sequence to bring the coprocessor back to P1 is controlled by the coprocessor OS As a result the precise timings o
71. reduce direct current resistance and current density The Intel Xeon Phi coprocessor supports 2 power groups for a total of 4 primary low voltage rails a group consisting of VDDG VDDQ and VSFR power rails and another group consisting only of VCCP The VCCP VDDG and VDDQ rails are powered from the PCI Express edge connector and the auxiliary 12V inputs The VSFR rail is powered from the PCI Express edge connector 3 3V input 5W VCCP is the coprocessor core voltage rail while VDDQ VDDG and VSFR supply power to memory portions of the coprocessor and miscellaneous circuitry in the coprocessor Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 10 Figure 2 2 Intel Xeon Phi Coprocessor Board Top side for reference only Intel Xeon Phi Coprocessor Silicon Outlet thermal sensor 150W 2x4 power Aarts big fig EN 23 5 5 mm T tni d E 40 m at M connector Inlet thermal sensor aj ge gl ec 23 4 75W 2x3 power connector Voltage regulators Blue Status LED thermal sensor Figure 2 3 Intel Xeon Phi Coprocessor Board Back side reference only System Management Controller Note Figure 2 2 and 2 3 are representative of the final Intel Xeon Phi Coprocessor board without the package thermal and mechanical solution 2 1 2 System Management Controller SMC The SMC has three I2C inter
72. resentation of the inter relationship between the different coprocessor and memory power states on the Intel Xeon Phi coprocessor These schematic representations are only for illustrative purposes and do not represent all possible low power states Cx and Mx refer to coprocessor and memory power states Figure 5 1 Coprocessor in CO state and Memory in MO state CO Fan Full on 10090 Full bandwidth enabled In this power state the card is expected to operate at its maximum TDP rating Note No application is expected to dissipate maximum power from cores and memory simultaneously Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 54 Figure 5 2 Some cores are in CO state and other cores in C1 state Memory in MO state CO Full on Full bandwidth enabled Coprocessor C1 state gates clocks on a core by core basis reducing core power On the active SKU the fan slows to an appropriate speed reducing fan power If all cores enter C1 the coprocessor automatically enters Auto pC3 state Figure 5 3 All Cores In C1 state Memory In M1 state Full bandwidth enabled If clock enable input to memory is pulled high then memory enters M1 state which reduces memory power Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 55 intel Figure 5 4 All Cores In Package C3 State Memory In M1 Full bandwidth enabled When all cores have entered C1 Halt state th
73. ro ro M VUVUD La tlw ne VO 2 woa wye Y pr o cao 7 VR inductor VR FET Document ID Number 328209 003EN intel 3 Thermal and Mechanical Specification 3 1 Mechanical Specifications The mechanical features of the Intel Xeon Phi coprocessor are compliant with the PCI Express 225W 300W High Power Card Electromechanical Specification 1 0 Table 3 1 shows the mechanical specifications of Intel Xeon Phi coprocessor passive and active SKUs Table 3 1 Intel Xeon Phi Coprocessor Mechanical Specification Parameter Specification Product Length 247 9mm Secondary Side Height Keep in 2 67mm 3120A 7120A SKU mass 7120P SE10P 5110P 3120P 31S1P SKUs mass 7120D 5120D SKUs mass 7120X SE10X SKUs mass Notes 1 Inclusive of I O bracket Figure 3 1 shows the mounting holes and Figure 3 2 shows the relevant dimensions of the Intel Xeon Phi coprocessor passive and active cards for chassis retention Refer to the Intel Xeon Phi Coprocessor Thermal Mechanical Models for PTC Creo previously Pro Engineer Icepak and FloTHERM models Document ID Number 328209 003EN Intel Xeon Phi Coprocessor Datasheet 15 intel Figure 3 1 Location of Mounting Holes on the Intel Xeon Phi Coprocessor Card in mils m Tit gensere RR A mm ee THAT ASE DIM 363 COMPLIANT MOUNTING HOLES ARE SIZED FOR M 1 0 5 FLAT HEAD SCREWS Intel Xeon Phi Coprocessor Datasheet Document ID Number 3
74. s SMBus interface operates as an industry standard IPMB with a reduced IPMI command implementation The SMC supports a system event log SEL via the IPMI interface Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 66 intel The SMC supports a read only IPMI SDR It is hard coded and not end user updateable The SDR can be read in chunks suggested size is 16 bytes or the entire SDR can be read passing FF as the number of bytes to read 6 6 1 IPMB Protocol The IPMB protocol is a symmetrical byte level transport for transferring IPMI messages between intelligent I2C devices It is a worldwide standard widely used in the server management industry In this case the client requests are sent to the SMC with a master I2C write Although both devices are a master on the bus at different times the SMC only responds to requests With the exception of the address selection algorithm it does not initiate master transactions on the bus at any other time during normal operation The commands supported by the SMC are documented below The specific information to implement these commands is documented with each command For byte level details refer to the Intelligent Plattorm Management Bus Communications Protocol Specification v1 0 and the Intelligent Platform Management Interface Specification v2 0 6 6 2 Polled Master Only Protocol The polled master only protocol may be used in the event IPMB is not feasibl
75. s every 2 seconds e Initiated by SetSMSignal command The SMC drives the fan PWM to the static rate provided in the IPMI FRU while in boot loader mode Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 78
76. t present after the signal name the signal is asserted when at the high voltage level The following notations are used to describe the signal type I Signal is an Input to the Intel Xeon Phi coprocessor Signal is an Output from the Intel Xeon Phi coprocessor I O Bidirectional Input Output signal S Sense pin P Power supply signal sourced from the PCI Express edge fingers or supplemental power connectors Table 4 1 PCI Express Connector Signals on the Intel Xeon Phi Coprocessor EXP A TX 15 0 DP EXP A TX 15 0 DN EXP A RX 15 0 DP EXP A RX 15 0 DN CK PE 100M 16PORT DP CK PE 100M 16PORT DN RST PCIE N Document ID Number 328209 003EN PCI Express Differential Transmit Pairs 16 channel differential transmit pairs referenced to the Intel Xeon Phi coprocessor The EXP A TX 15 0 DP and EXP A TX 15 0 DP are connected to the PCI Express device transmit pairs on the Intel Xeon Phi coprocessor PCI Express Differential Receive Pairs 16 channel differential receive pairs referenced to the Intel Xeon Phi coprocessor The EXP RX 15 0 DP and EXP A RX 15 0 DP are connected to the PCI Express device receive pairs on the Intel Xeon Phi coprocessor PCI Express Reference Clock 100MHz differential clock I to Intel Xeon Phi coprocessor for use by the coprocessor to properly recover data from the PCI Express Interface PCI Express Reset Signal RST PCIE
77. the sound level low when max cooling is not needed 6 5 System and Power Management The Intel Xeon Phi coprocessor PCI card supports both on card power management and an option for system based management With on card power management the SMC adjusts system power using preprogrammed power throttle threshold values With system based management the SMC receives power control inputs via in band communication from a host application or out of band via IPMB commands from a host BMC The Intel 9 Xeon Phi coprocessor supports 2 power threshold levels PLO and PL1 which determine coprocessor power throttling points These are not to be confused with setting coprocessor power limits that is they do not change the absolute TDP of the product PL1 is defined as the first power threshold When the coprocessor detects that the power consumption stays above PL1 for a specified time period the coprocessor will begin power throttling By default the card s PL1 power threshold is set to 105 of the TDP and the time duration allowed before throttling starts is 300 ms When the SMC detects that these conditions have been met it will assert power throttling causing the frequency to drop by about 100 MHz Throttling will stop once the power consumption drops 15 W or 20 W depending on card TDP below PL1 The difference in the throttling assertion and deassertion thresholds will help prevent the coprocessor from continually cycling between throttling
78. ver separate time windows Intel Xeon Phi Coprocessor Datasheet Document ID Number 328209 003EN 62 6 3 6 3 3 intel P state clamping if the P state requested is not possible within the set power envelope e Power energy measurement Can choose to include or preclude 3 3V power General SMC Features and Capabilities The Intel Xeon Phi coprocessor supports the PCI Express 2 0 standard The SMC located on the card has direct access to information about the card operation Such as fan speeds power usage etc that must be managed from host based software The SMC supports manageability interfaces via the SCIF interface which is part of the MPSS software stack and the preferred PCI Express SMBus IPMI IPMB protocol as well as with polled master only IPMI protocol The SMC firmware update process is resilient against unexpected power loss and resets The SMC supports a read only IPMI compliant Field Replaceable Unit FRU that contains the following information e Manufacturer name e Product name e Part number model number e Universal Unique Identifier UUID e Manufacturer s IPMI ID e Product IPMI ID e Manufacturing time date stamp e Serial number 12 ASCII bytes To keep the Intel Xeon Phi coprocessor within the operational temperature range the SMC boosts the fan to full speed when either PERST or THERMTRIP N are asserted on SKUs with active cooling solutions On SKUs with passive coolin
79. x4 connector must be capable of maximum 150W power draw by the coprocessor and the 2x3 must be capable of maximum 75W power The 300W TDP products of the Intel Xeon Phi coprocessor family must have power supplied to the 2x4 and the 2x3 connectors The 225W products can have either a single 2x4 connector connected to a power supply or two 2x3 connectors each capable of maximum 75W power draw Within the coprocessor the power rails from the three sources are not connected to each other Instead the Intel Xeon Phi coprocessor is designed to draw power proportionally from the three power sources During coprocessor power up sensors on the coprocessor card detect presence of power supplies to the supplemental connectors and depending on the maximum TDP of the coprocessor can determine if sufficient power is available to power up the card For example sensors on a 300W coprocessor card must detect both 2x4 and 2x3 power supplies in order for the card to be powered up and function properly Dense Form Factor 5120D Edge Connector Pins The Intel Xeon Phi coprocessor 5120D SKU DFF uses a 230 pin edge finger designed to industry standard x24 PCI Express connector PCI Express Gen2 compliant Unlike the other SKUs in the Intel Xeon Phi coprocessor family the 5120D SKU requires PCI Express signal routing and 12V filter per card on the baseboard The symbol N at the end of a signal name indicates that the active or asserted st

Intel Xeon Phi 7120A

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