Dataram 4GB DDR3-1600
Contents
1. DTM64370D 240 2Rx8 Registered ECC DDR3 DIMM Emu Optimizing Value and Performance enc rbag UAI DA IE Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high Operating Voltage 1 5V 0 075 Type SSTL 15 On board 12 temperature sensor with integrated serial presence detect SPD EEPROM Data Transfer Rate 12 8 Gigabytes sec Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 6 7 8 9 10 and 11 Bi Directional Differential Data Strobe signals SDRAM Addressing Row Col Bank 15 10 3 Fully RoHS Compliant Pin Configuration Front Side Back Side 1 Vrerpal31 0025 61 2 91 0041 121 151 Vas 181 A1 a Xe 62 Vpp 92 Vss 122004 152 DM3 182 Vpp 000 33 DQS3 63 CK1 93 DQS5 123 005 153 183 Vpp 4 001 34DOS3 64 CK1 94 DQS5 124Vsas 15455 184 CKO 5 Vas 35 Vas 65 Vpp 95 Vss 125 0 0 155 0030 185 6 0050 36 0026 66 Vpp 96 0042 126 156 0031 186 Vpp 7 0050 37 0027 67 VREFCA 97 DQ43 12755 1157 Vss 187 Event 8 Vss 38 Vss 68 Par In 98 Vss 128006 158 188 9 89 69 VDD 99 0048 129 DO7 159 5 189 10003 40 CB1 70A10 AP 100 DQ49 130 Vss 160 Vss 190 BA1 11 41 Vss 71 101 131 0012 161 DM8 191 Vpp 12008 42 00 8 2 102 DQS6f1322. DTM64370D Optimizing Value and Performance 4 240 2Rx8 Registered ECC DDR3 DIMM II DATARAM ptimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06186 Revision A 11 Jan 13 Dataram Corporation 2013 Page 13
3. DMROO ann 4 TDQSR9O TDQSR13 DQR 7 0 0 7 0 RANK 0 0 RANK 1 DQR 39 32 DQSR1O DQSR5O DQSR1 DQSR5O DMR1O DMR5O TDQSR100 TDQSR140 DQR 15 8 DQR 47 40 DQSR2 DQSR6 DQSR2 DQSR6 DMR2O DMR6O ITDQSR110 TDQSR15O DQR 23 16 DQR 55 48 DQSR3 DQSR7 DQSR3 O DQSR7 DMR3O DMR7O TDQSR120 TDQSR16O DQR 31 24 O DQR 63 56 O DQSR8O DQSR8 DMR8O TDQSR170O CBRI7 0 TO SDRAMS All All 15 OHMS 22 OHMS 50 RSO 00 63 0 O A O 0 ns IRSA CB 7 0 O O CBR 7 0 BARUR A 15 0 A 14 0 R 005 8 0 O O DQGSR 8 0 IRAS RASR DQS 8 0 O O DQSR 8 0 ICAS E ANER DM 8 0 O O DMR 8 0 CKEO CKE1 I CKE1R TDQS 17 9 O O TDQSR 17 9 ODTO e ODTOR ODT1 PAR IN OUT GLOBAL SDRAM CONNECTS CKO L R CLK 1 0 120 All 39 OHMS OHMS BA 2 0 R CKO IL R CLK 1 0 A 15 0 R RASR SDRAMS CK1 IWER VTT ICK1 All 240 OHMS All 39 OHMS CKE 1 0 R ODT 1 0 R IRS 1 0 VTT DOE ME Vss 240 2Rx8 Registered ECC DDR3 DIMM VDD D 39 OHMS 100 nF i RCLK 1 0 IRCLK 1 0 DECOUPLING VDDSPD Serial PD Devices SDRAMs Devices All SDRAMs VTT All SDRAMs EVENT Document 06186 Revision A 11 Jan 13 Dataram Corporation
4. 2013 Page 3 DATARAM DIM64370D 4GB 240 2Rx8 Registered ECC DDR3 DIMM Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability Ambient Temperature Operating Oo C DRAM Case Temperature Operating Tos 0 95 C Voltage on relative to Vss V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note I O Reference Voltage 0 49 0 50 0 51 Voo 1 I O Reference Voltage VREFCA 0 49 Vpp 0 50 Vpp 0 51 Vpp 1 Notes 1 The value of Vrer is expected to equal one half Vpp and to track variations the Vpp DC level Peak to peak noise on Vrer may not exceed 1 of its DC value For Reference Vpp 2 15 mV DC Input Logic Levels Single Ended T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Unit Logical Low Logic 0 DC 0 4 AC Input Logic Levels Single Ended 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical Low Logic 0 D AC Vner 0 175 V Document 06186 Revision A 11 Jan 13 Dataram Corporation 2013 Page 4 DTM64370D GEE AGB 240 Pin 2Rx8 Re
5. 7 X OxFC Bit 4 CL 8 X Bit 5 CL 9 X Bit 6 A Bi CL 10 X A Bi CL 10 X 10 X Bit 7 A BitZCL211 X A BitZCL211 X 11 X CAS Latencies Supported Most Significant Byte Bit O 124 12 0 12 Bit 1 Bitf CL213 Bitf CL213 13 Bit 2 BitOL 214 14 BitOL 214 DBit3 CL 15 0x0 4 46 CLEIT 18 6 18 18 o Bit Reserved 7 Reserved inr Minimum CAS Latency Time tAAmin 13 125ns EE Minimum Write Recovery Time tWRmin 18 Minimum RAS to CAS Delay Time tRCDmin 13 125ns 19 Minimum Row Active to Row Active Delay Time fRRDmin 200 Minimum Precharge Delay Time tRPmin 13 125ns Upper Nibbles for tRAS and tRC Bit 3 tRAS Most Significant Nibble 0x11 Bit 7 Bit 4 tRC Most Significant Nibble eem Active to Precharge Delay Time tRASmin Least Significant Minimum Active to Active Refresh Delay Time tRCmin Least 48 125ns 0x84 Significant Byte Em Refresh Recovery Delay Time tRFCmin Least Significant 160 0ns Minimum Refresh Recovery Delay Time tRFCmin Most Significant eoon 26 Minimum Internal Write to Read Command Delay Time tWTRmin Minimum Internal Read to Precharge Command Delay Time 7 515 0x3C tRTPmin Upper Nibble for tFAW 0x00 Bit 3 Bit 0 tFAW Most Significant Nibble 0 Docum
6. DQ13 162 NC 192 RAS 13009 43 DQS8 73 1030056 133 Vss 163 Vss 193 50 14Vss 44 Vss 74 CAS 104Vss 134 DM1 164 194 Vpp 15 DQS1 45 CB2 75 105 0050 135 NC 165 CB7 195 ODTO 16 0051 46 CB3 76151 106 0051 136 Vss 166 Vss 196 13 17 77 ODT1 107 Vss 137 DQ14 167 NC 5 197 18 0010 48 V 7855 108 0056 138 DQ15 168 RESET 198 53 190011 49 Vyr 79152 109 0057 13955 169 CKE1 199 Vss 20 5 50 CKEO 80 Vss 110 Vss 140DQ20 170 200 DQ36 21 DQ16 51 81 DQ32 111 DQS7N41 DQ21 171 A15 201 DQ37 22 DQ17 52 BA2 82 DQ33 1120057 142 Vss 172 14 202 Vss 23Vss 53 Egg 83 Vss 113Vss 143DM2 173 Voo 203 DM4 24 DQS2154 84 0054 1140058 144 NC 174 A12 BC 204 NC 25 DQS2 55 A11 85 2054 1150059 145 5 175 9 205 Vss 26Vss 56 7 86 Vss 116 Vss 146 DQ22 176 206 DQ38 27 DQ18 57 87 DQ34 117 SA0 147 DQ23 177 207 DQ39 28 DQ19 58 A5 88 DQ35 118SCL 148 5 178 208 Vss 29Vss 59 4 89 Vss 119SA2 149 DQ28 179 209 DQ44 30 DQ24 60 90 DQ40 120V 150DQ29 180 210 DQ45 Not used 244 Vas 212 DM5 213 NC 214 Vas 215 0046 216 DQ47 217 Ves 218 DQ52 219 DQ53 220 Vss 221 DM6 222 NC 228 Use 224 DQ54 225 DQ55 226 Vss 227 DQ60 228 DQ61 229 Vss 230 DM7 231 NC 235 Vs 233 DQ62 234 DQ63 235 Vss 236 237 SA1 238 SDA 239 Ves 240 Identification DTM64370D 512MX72 4GB 2Rx8 PC3 12800R 11 11 B1 Performance
7. dress and Command Setup Time before Clock sace 45 Load Mode Command Cycle Time tw e Active to Precharge Time Active to Active Auto Refresh Time c 48754812 ms Average Periodic Refresh Interval 0 C lt Tcase lt 85 C na COEM us Average Periodic Refresh Interval 0 C lt Tcase lt 95 C tn 39 Us Auto Refresh Row Cycle Time Wwe ns Row Precharge Time 137503425 ns Read DQS Preamble Time tere 09 owe lck avg Read DQS Postamble Time Row Active to Row Active Delay mo Max 4nCK 6ns ns Internal Read to Precharge Command Delay Max 4nCK 7 5ns ns Write 005 Preamble Setup Time Write 005 Postamble Time Xe H Write Recovery Time wm Internal Write to Read Command Delay lwTR 4 7 5ns ns Notes 1 maximum preamble is bound by tLZDQS min 2 The maximum postamble is bound by tHZDQS max Document 06186 Revision A 11 Jan 13 Dataram Corporation 2013 Page 7 ZUM 4GB 240 Pin 2Rx8 Registered DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Function Number of Bytes Used Number of Bytes in SPD Device CRC Coverage Bit 3 Bit 0 SPD Bytes Used 176 Ll Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 2 0x0B Key Byte DRAM Device Type SDRAM Key Byte Module Type Byte Value Hex Bit 3 Module Type RDIMM 0x01 Bi
8. ent 06186 Revision 11 Jan 13 Dataram Corporation 2013 Page 9 DATARAM DTM64370D ee 4GB 240 2Rx8 Registered ECC DDR3 DIMM Bit 7 Bit 4 Reserved ____ 0 29 Minimum Four Activate Window Delay Time tFAWmin Least 30 0ns OxFO Significant Byte SDRAM Optional Features Bit 0 RZQ 6 Bit 2 Reserved ii Bit 3 Reserved 0x83 Bit 4 Reserved Bit 5 Reserved Bit 6 Reserved Bit 7 DLL Off Mode Support SDRAM Drivers Supported Extended Temperature Range X Extended Temperature Refresh Rate Auto Self Refresh ASR 31 On die Thermal Sensor ODTS Readout 0x01 Reserved Reserved Reserved Partial Array Self Refresh Module Thermal Sensor 32 Bit 6 Bit 0 Thermal Sensor Accuracy 0 0 80 Bit 7 Thermal Sensor With TS SDRAM Device Type Bit Signal Loading Not specified 33 Bit 3 Bit 2 Reserved 0 Undefined 0 0x00 Bit 6 Bit 4 Die Count Not specified Bit 7 SDRAM Device Type Std Mono Fine Offset for SDRAM Minimum Cycle Time tCKmin UNUSED Fine Offset for Minimum CAS Latency Time tAAmin UNUSED 36 37 Fine Offset for Minimum RAS to CAS Delay Time tRCDmin UNUSED eine Offset for Minimum Active to Active Refresh Delay Time tRCmin UNUSED Module Nominal Height Bit 4 Bit 0 Module Nominal Height max in mm 29 lt h lt 30 OxOF Bit 7 Bitb Reserved 0 Module Maximum T
9. gistered DDR3 DIMM Differential Input Logic Levels 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum _ Unit Differential Input Logic High 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage relative to VDD 2 Vix 0 150 0 150 V Capacitance T4 25 C f 100 MHz 00163 0 CBI7 7 0058 0 DQS 8 0 pF Input Output Capacitance DM 8 0 TDQS 17 9 DC Characteristics T4 0 to 70 C Voltage referenced to Vss Input Leakage Current Le Any input 0 V VIN VDD lot 10 10 UA 2 3 Output Leakage Current OV lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled Document 06186 Revision A 11 Jan 13 Dataram Corporation 2013 Page 5 DTM64370D GEE AGB 240 Pin 2Rx8 Registered DDR3 DIMM lbo Specifications and Conditions 0 to 70 C Voltage referenced to Vss alue Precharge Current Operating One Operating current One bank ACTIVATE to READ to Precharge Current Precharge Power T mns aded power down current Slow exit Ipp2P mA Down Current Precharge Power 2 power down current Fast exit Ipp2P mA Down Current Precharge Quiet 2220 Precharge quiet standby current MA Standby Current Precharge Standby Precharge standby current EI WA C
10. hickness 6 Bit 3 Bit 0 Front in mm baseline thickness 1 mm 1 lt th lt 2 0x11 Bit 7 Bit 4 Back in mm baseline thickness 1 1 lt th lt 2 62 Reference Raw Card Used 0x01 Document 06186 Revision A 11 Jan 13 Dataram Corporation 2013 Page 10 DATARAM DIM64370D 4GB 240 2Rx8 Registered ECC DDR3 DIMM Bit 4 Bit 0 Reference Raw Card R C B Bit 6 Bit 5 Reference Raw Card Revision Rev O Bit 7 Reserved A AL Registered DIMM Module Attributes 63 Bit of Registers used 1 Register 0x05 Bit 3 Bit 2 of Rows of DRAMs on 1 Row Bit 7 Bit 4 Reserved 0 RDIMM Thermal Heat Spreader Solution 64 Bit 6 Heat Spreader Thermal Characteristics 0 0x00 Bit 7 Heat Spreader Solution No HS Register Manufacturer ID Code Least Significant Byte Optional 0x00 66 Register Manufacturer ID Code Most Significant Byte Optional 0x00 Register Revision Number Optional o OXF Register Type Bit 2 0 Support Device SSTE32882 0x00 Bit 7 3 Reserved 0 SSTE32882 RC1 MS Nibble RCO LS Nibble 0x00 SSTE32882 RC3 MS Nibble RC2 LS Nibble Drive Strength Command Address Bit 1 RC2 DA3 4 Value RESERVED Bit Bit 2 RC2 DBAO 1 Value RESERVED Bit 5 Bit 4 RC3 DA4 3 value Command Address A Outputs Moderate Bit 7 Bit 6 RC3 DBAO 1 value Comma
11. nd Address B Outputs Moderate SSTE32882 RC5 MS Nibble RC4 LS Nibble Drive Strength Control and Clock TO 0x50 71 Bit 1 Bit 0 RC4 DA3 4 Control Signals A Outputs Light Bit Bit 2 RCA DBAO 1 Control Signals B Outputs Light Bit 5 Bit 4 RC5 DAA 3 value 1 1 and Y3 Y3 Clock Outputs Light Bit 7 Bit 6 RC5 DBAO 1 value YO YO and Y2 Y2 Clock Outputs Light 72 SSTE32882 RC MS Nibble RC6 LS Nibble UNUSED 0x00 73 SSTE32882 RC9 MS Nibble RC8 LS Nibble UNUSED 0x00 SSTE32882 RC11 MS Nibble RC10 LS Nibble SSTE32882 RC13 MS Nibble RC12 LS Nibble SSTE32882 RC15 MS Nibble RC14 LS Nibble 720 121 Module Manufecuring Date gt lt Document 06186 Revision 11 Jan 13 Dataram Corporation 2013 Page 11 DTM64370D GEE AGB 240 Pin 2Rx8 Registered ECC DDR3 DIMM Cyclical Redundancy Code CRC Lim ee erie no di Module M5 Moern OOO 146 147 Module 48 DRAM Manufacturer ID Code Least Signffcant Bye 49 DRAM Manufacturer ID Code Most Significant Bye Bytes 122 125 change per DIMM Document 06186 Revision A 11 Jan 13 Dataram Corporation 2013 Page 12
12. on input Addr12 Burst Chop A10 AP Combination input Addr10 Auto precharge Vss Ground VppsPp SPD EEPROM Power VREFDO Reference Voltage for DQ s VREFCA Reference Voltage for CA Termination Voltage NC No Connection Document 06186 Revision A 11 Jan 13 Dataram Corporation 2013 Page 1 DIM64370D Optimizing Value and Performance 4GB 240 2Rx8 Registered ECC DDR3 DIMM Front view 133 35 5 250 9 50 0 374 30 00 1 181 17 30 0 681 Y i Y 2 50 0 098 5175 ph 47 00 7100 0 204 1 850 2 795 123 00 4 843 di Back view Side view 4 00 0 157 4 00 0 157 Min 1 27 10 0 0500 0 0040 5 Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches _ 2 Document 06186 Revision A 11 Jan 13 Dataram Corporation 2013 Optimizing Value and Performance LCLK 1 0 LCLK 1 0 IRS1O RSO DIM DQSRO e IDQSR4
13. range Clock Module Speed CL trep trp 800 MHz PC3 12800 11 11 11 667 MHz PC3 10600 10 10 10 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Description DTM64370D is a registered 512Mx72 memory module which conforms to JEDEC s DDR3 PC3 12800 standard The assembly is Dual Rank Each Rank is comprised of nine 256Mx8 DDR3 Hynix SDRAMs One 2K bit EEPROM is used for Serial Presence Detect and a combination register PLL with Address and Command Parity is also used Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals in a Fly by topology A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating temperature of 95C Pin Description Function CB 7 0 Data Check Bits DQ 63 0 Data Bits DQS 8 0 205 8 0 Differential Data Strobes DM 8 0 Data Mask TDQS 17 9 Termination strobes CK 1 0 CK 1 0 Differential Clock Inputs 1 0 Clock Enables ICAS Column Address Strobe RAS Row Address Strobe S 3 0 Chip Selects IWE Write Enable A 15 0 Address Inputs BA 2 0 Bank Addresses ODT 1 0 On Die Termination Inputs SA 2 0 SPD Address SCL SPD Clock Input SDA SPD Data Input Output Temperature Sensing RESET Reset for register and DRAMs PAR_IN Parity bit for Addr Ctrl ERR_OUT Error bit for Parity Error A12 BC Combinati
14. t 7 Bit 4 Reserved 0 SDRAM Density and Banks Bit 3 Total SDRAM capacity in megabits 2Gb 0x03 Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved 0 SDRAM Addressing Bit 2 Bit 0 Column Address Bits 10 Bit 5 Bit 3 Row Address Bits 15 Bit 7 6 Reserved 0x19 Module Nominal Voltage VDD NOT 1 5 V operable Bit 1 1 35 V operable Bit 2 1 2X V operable Bit 3 Reserved Bit 4 Reserved Bit 5 Reserved Bit 6 Reserved Bit 7 Reserved 0x00 Module Organization Bit 2 Bit 0 SDRAM Device Width 8 Bits Bit 5 Bit 3 Number of Ranks 2 Rank Bit 7 6 Reserved 0 0x09 Module Memory Bus Width Bit 2 Primary bus width in bits 64 Bits Bit 4 Bit 3 Bus width extension in bits 8 Bits Bit 7 Bit 5 Reserved 0 OxOB Fine Timebase FTB Dividend Divisor Bit 3 Bit 0 Fine Timebase FTB Divisor 2 0x52 Bit 7 Bit 4 Fine Timebase FTB Dividend 5 1 Medium Timebase Dividend 0 125ns 0x01 Document 06186 Revision A 11 Jan 13 Dataram Corporation 2013 Page 8 DIM64370D 4GB 240 2Rx8 Registered ECC DDR3 DIMM Medium Timebase MTB Divisor 0 125ns SDRAM Minimum Cycle Time tCKmin CAS Latencies Supported Least Significant Byte Bit 0 CL 4 Bit 1 CL 5 Bit 2 CL 6 X Bit 3 CL
15. urrent Active Power Down Active power down current Active Standby Ibo3N Active standby current 414 MA Current Operating Burst Burst write operating current Operating Burst Burst read operating current Read Current Ipo4R 873 mA Burst Refresh e Refresh current Self Refresh Self refresh temperature current MAX Tc 85 Current 1206 216 Operating Bank interleave Read 1527 bank interleaved read current 1278 mA Current One module rank in this operation the rest in IDD2P slow exit All module ranks in this operation Document 06186 Revision A 11 Jan 13 Dataram Corporation 2013 Page 6 DIM64370D 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM AC Operating Conditions Internal read command to first data ns CAS to CAS Command Delay e Clock High Level Width tox Clock Low Level Width tox Data Input Hold Time after DQS Strobe tu 45 qo ps DQ Input Pulse Width tw 30 ps 8005 Output Access Time from Clock ps Write DQS High Level Width tek avo Write DQS Low Level Width DQS Out Edge to Data Out Edge Skew tasa 100 Data Input Setup Time Before DQS Strobe ts 10 fF ps 29 Falling Edge from Clock Hold Time toe 0 18 DQS Falling Edge to Clock Setup Time toss Clock Half Period tw minimum oftcnorta ns Address and Command Hold Time after Clock t 102 o Ad
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