Kingston Technology ValueRAM KVR16LR11D8/8KF memory module
Contents
1. either on the fly using A12 or MRS e Bi directional Differential Data Strobe e Internal self calibration Internal self calibration through ZO pin RZQ 240 ohm 1 e On Die Termination using ODT pin e On DIMM thermal sensor Grade B e Average Refresh Period 7 8us at lower than TCASE 85 C 3 9us at 85 C lt TCASE lt 95 C e Asynchronous Reset e PCB Height 1 180 30 00mm double sided component Continued gt gt kingston com Document No VALUERAM1380 001 A00 12 03 13 Page 1 continued ValueRAM MODULE DIMENSIONS units millimeters D 00 00 00 00 m 010D o M D NT N s NE ae u a N 00 N D 9 i Oo gt N M To O 5 ey e 30 00 29 60x4 H 24 80x2 21 80x2 18 80x2 sed 15 80x2 R 0 65 MAX TYPICAL 11 00x2 D 8 00x2 3 80 2 30x2 A 0 000 X 50 0 10 gt p CHAMFER 0 50 X 45 DEG bb PLACES OOo O LO LO DEW T oe p m LO kingston com Document No VALUERAM1380 001 A00 Page 22. Kingston 1 Cann ORL O G Y Memory Module Specifications Value i KVR16LR11D8 8KF 8GB 2Rx8 1G x 72 Bit PC3L 12800 CL11 Registered w Parity 240 Pin DIMM DESCRIPTION SPECIFICATIONS This document describes ValueRAM s 1G x 72 bit 8GB CL IDD 11 cycles DDR3L 1600 CL11 SDRAM Synchronous DRAM low voltage Row Cycle Time tRCmin 48 125ns min registered w parity 2Rx8 ECC memory module based on Reiresh io Aciive Rafrachi 260ns min eighteen 512M x 8 bit FBGA components The SPD is pro Command Time tRFCmin grammed to JEDEC standard latency DDR3 1600 timing of Row Active Time tRASmin 35ns min 11 11 11 at 1 35V or 1 5V This 240 pin DIMM uses gold Maximum Operating Power 1 35V TBD W contact fingers The electrical and mechanical specifications UL Rating 94V 0 are as follows Operating Temperature 0 G to 85 C Storage Temperature 55 C to 100 C FEATURES Power will vary depending on the SDRAM and Register PLL used e JEDEC standard 1 35V 1 28V 1 45V and 1 5V 1 425V E09 SAE NY SDRAM SUPPORTED e VDDQ 1 35V 1 28V 1 45V and 1 5V 1 425V 1 575V e 800MHz fCK for 1600Mb sec pin SERORA E e 8 independent internal bank e Programmable CAS Latency 11 10 9 8 7 6 e Programmable Additive Latency 0 CL 2 or CL 1 clock e 8 bit pre fetch e Burst Length 8 Interleave without any limit seguential with starting address 000 only 4 with tCCD 4 which does not allow seamless read or write
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