Home

Intel Core i7-4860EQ

Contents

1. Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 3 of 42 Number Sheet 4 of 42 4 Land Name Direction Land Name posed Direction 41 DDR2 DQ 12 SSTL AE25 DDR2 CKE 4 SSTL 43 PE3D TX DP 14 PCIEX3 27 DDR RESET C23 51 5 45 TX DN 12 ACA PE3C TX DNI9 PCIEX3 AER AS GND 49 PCIEX3 DDR2_DQ 63 SSTL 1 0 ACS DDR2 DQS DP 16 SSTL 1 55 GND 5 PCIEX3 AE33 DDR2 001261 SSTL 1 0 AC53 PE3B_RX_DN 6 PCIEX3 5 DDR2 DQI25 SSTL 1 0 55 2 DP 6 PCIEX3 7 DDR2 001151 SSTL 1 0 DDR2 20 DP 05 SSTL AE39 55 GND 41 DDR2 00108 SSTL DDR2 001391 SSTL 1 0 He eee GND AD12 DDR2_DQS_DN 13 SSTL AE45 PWR AD14 DDR2 001361 SSTL AE47 GND DDR2 CS 2 SSTL GND DDR2 0512 5 DDR2 DQ 59 SSTL AD20 DDR2 PAR ERR SSTL 51 55 GND 22 DDR2 SSTL AE53 D META PWR AD24 DDR2 CKEI3 a S AESS 2 PCIEX3 AD26 56 cH 57 2 DP 7 PCIEX3 AD28 DDR2 005 17 SSTL 7 DDR2 01471 SSTL AD32 DDR2 001311 SSTL 1 0 AE9 VSS
2. Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 23 of Number Sheet 24 of pos Land Name pes Direction Land Name Direction 5 DDRO SSTL 1 0 CL9 DDRO DQ 03 SSTL 51 55 GND CM10 vss GND CJ DQ 06 SSTL 1 0 CM12 DDRO_DQ 17 SSTL 9 vss GND 14 vss GND CK10 VSS GND CM16 DDRO DQ 19 SSTL 1 0 CK12 DDRO DQ 16 SSTL 1 0 CM18 DDRO_CKE 1 SSTL CK14 DDRO DQS DP 02 SSTL 1 0 CM20 DDRO BA 2 SSTL CK16 DDRO DQ 18 SSTL CM22 DDRO 071 SSTL CK20 DDRO MA 12 SSTL CM24 DDRO 041 SSTL CK22 DDRO MA 08 SSTL CM26 PAR SSTL CK24 DDRO MA 03 SSTL CM28 DDRO BA 0 SSTL CK26 DDRO MA 10 SSTL CM30 55 GND CK28 DDRO CS N 9 SSTL CM32 VSS GND CK30 0944 sste WO vss GND CK32 DDRO DQS DP 14 SSTL 1 0 36 vss GND CK34 DDRO DQ 46 SSTL 1 0 CM38 55 GND CK36 VSS GND CM4 DDR1 DQ 04 SSTL CK38 DDRO 001571 SSTL 1 0 40 VSS GND 55 GND CM42 VSS GND CK40 DDRO DQS DP 07 SSTL 1 0 CM44 BCLKO DN CMOS CK42 DDRO 001591 SSTL 1 0 6 55 GND 44 5 5 8 55 GND CK6 55 GND 11 VSS GND CK8 DDRO DQ 02 SSTL 1 0 CN13 VSS GND DDRO_DQ 21 SSTL 1 0 CN15 VSS GND pbRo 005 551 55
3. Sheet 29 of 42 Sheet 30 of 42 Land Name ro Direction Land Name pu pulis Direction vss 7 GND VSS AG1 GND vss AA11 GND VSS AG3 GND VSS AA29 GND VSS AG43 GND 55 GND VSS AG5 GND vss AA31 GND VSS AG55 GND 55 AA39 GND VSS AG57 GND VSS AA5 GND VSS AG9 GND VSS AA55 GND VSS AH58 GND VSS AA9 GND VSS AJ 15 GND vss AB14 GND VSS AJ 17 GND vss AB36 GND vss AK10 GND vss AB42 GND vss AK12 GND 55 6 GND VSS 14 GND 55 GND 5 AK16 GND vss AC9 GND VSS AK2 GND 55 AD26 GND VSS GND vss AD34 GND vss AK42 GND vss AD36 GND vss AK44 GND vss AD42 GND vss AK46 GND vss AD44 GND VSS GND VSS AD46 GND VSS AK50 GND VSS AD48 GND VSS AK6 GND VSS AD50 GND VSS AK8 GND VSS AD52 GND VSS AL43 GND VSS AD6 GND VSS AL45 GND 55 GND 5 AL49 GND VSS AE31 GND VSS AL51 GND VSS AE39 GND VSS AL53 GND vss AE43 GND VSS 56 GND 55 AE47 GND vss AN55 GND vss AE49 GND vss AN57 GND VSS AE51 GND VSS 42 GND vss AE9 GND VSS 44 GND 55 AF12 GND VSS AP58 GND vss AF16 GND vss GND vss AF20 GND vss AR11 GND VSS AF26 GND VSS AR13 GND VSS AF34 GND VSS 15 GND vss AF36 GND vss AR17 GND 55 4 GND VSS AR3 GND vss AF42 GND vss AR5 GND VSS AF54 GND VSS AR7 GND lvss AF56 GND 5 AR9 GND lvss GND 5 AT10 GND Datasheet Processor Land Listing Datasheet inte
4. 33 Coordination of Thread Power States at the Core 35 LVEx t MWALIT Conversions iere re ex he n RERO C e n 35 Coordination of Core Power States at the Package 38 Package C State Power Specifications 40 Memory Channel DDRO DDR1 DDR2 mmm eee 44 Memory Channel Miscellaneous e emnes 45 PCI Express Port L Signals 45 PCI Express Port 2 Signals 45 PCI Express Port 3 Signals terim creen EE EPeE 46 PCI Express Miscellaneous Signals sss mmn 46 DMI2 and PCI Express Port 0 Signals eren reme nne ek ERR RR RES ERE pA d 47 Platform Environment Control Interface 47 System Reference Clock BCLK 0 1 5 47 Joint Test Action Group TAG and Test Access Port TAP Signals 47 Serial Voltage Identification SVID 5 2 48 Processor Asynchronous Sideband Signals 48 Miscellaneous Signals 5 rore 50 Power and Ground 51 5 ene ce need 51 Power and Ground MANS
5. Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 41 of Number Sheet 42 of rog Land Name Direction po Land Name m Direction W11 DDR2 DQS DP 06 SSTL 46 PE3C TX DP 11 PCIEX3 w13 vss GND YA8 RSVD W15 RSVD 50 DP 4 PCIEX3 W17 DDR2 CS N 8 SSTL Y52 DP 5 PCIEX3 W19 DDR2_ODT 1 SSTL Y54 VTTA PWR W21 DDR2 DNI 2 SSTL Y56 55 GND W23 SSTL Y6 DDR2 01411 SSTL 1 0 W25 DDR2_MA 14 SSTL Y8 DDR2 DQS DP 14 SSTL 1 0 w29 DDR2_DQ 18 SSTL W3 DDR2 001561 SSTL W31 DDR2 005 DN 02 SSTL 1 0 5 w33 vss GND W35 DDR2_DQ 29 SSTL w37 55 GND w39 DDR2 DQS DN O9 SSTL w41 55 GND w43 VSS GND w45 VSS GND w47 VSS GND w49 VTA PWR w5 vss GND w51 55 GND w53 VSS GND w55 PE2A_RX_DN 3 PCI EX3 W7 DDR2 001451 SSTL w9 vss GND 10 vss GND vi2 vss GND Yl4 DDR23 RCOMP 2 Analog 16 DDR2_CS_N 7 SSTL Y18 DDR2 ODT 3 SSTL Y20 DDR2 ODT 0 SSTL Y22 DDR2_CLK_DN 1 SSTL Y24 2 SSTL Y28 55 GND Y30 55 GND 2 55 GND Y34 DDR2 005 DP 12 SSTL 1 0 vss GND vss GND YA DDR2 001571 SSTL vss GND YA2 1 55 GND PE3D TX DP 13 PCIEX3 114 Package Mechanical Specifications tel 9 Package Mechanical Specifi
6. 7 5 3 Signal DC Specifications DC specifications are defined at the processor pads unless otherwise noted DC specifications are only valid while meeting specifications for case temperature clock frequency and input voltages Care should be taken to read all notes associated with each specification Table 7 13 DDR3 and DDR3L Signal DC Specifications Symbol Parameter Min Typ Max Units Notes lu Input Leakage Current 1 4 1 4 mA 10 Data Signals Vu Input Low Voltage 0 43 V 2 3 Input High Voltage 0 57 V 2 4 5 DDR3 Data Buffer On Resistance 21 31 6 On Die Termination for Data 45 55 Data ODT Signals 90 B 110 2 On Die Termination for ERRi N ODT Parity Error Signals 59 E 12 Reference Clock Signals Command and Data Signals Output Low Voltage Vecp 2 V CCD V 2 7 oF TERMI Output High Voltage Vccp 2 V V 2 5 7 TERM Reference Clock Signal DDR3 Clock Buffer On RoN Resistance 21 n n 6 Command Signals Ron Ren Command Buffer On 16 24 6 esistance DDR3 Reset Buffer On RoN Resistance 75 Output Low Voltage Signals VoL 51 5 DDR RESET C 01 23 0 2 M 1 2 Output High Voltage 51 5 Signals 0 9 1 2 E DDR RESET C 01 23 _N liL 51 5 Input Leakage Current 100 100 1 2 Control Signals DDR3 Control Buffer On R
7. CHE R33 DDR2_DQ 17 SSTL 1 0 N55 2 PCIEX3 R35 wes GND N7 5583 50150 R37 DDR2 001061 SSTL 1 0 NS lee TE R39 vss GND GO VS R41 DDR2_DQ 04 SSTL SD ves END R43 DDR SDA C23 ODCMOS 1 0 Pa vec CND R45 PE3C TX DP 10 PCIEX3 DDR2 WE 57 R47 TX DP 2 PCIEX3 112 intel Processor Land Listing Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 39 of Number Sheet 40 of pos Land Name 5 Direction w Land Name Direction R49 PE3B TX DPI 7 PCIEX3 U3 DDR2_DQ 60 SSTL 1 0 R5 VSS GND U31 DDR2 005 DP 02 SSTL 1 0 R51 PE3B_TX_DP 5 PCIEX3 033 DDR2 DQ 16 SSTL 1 0 R53 PRDY_N CMOS 035 VSS GND R55 VSS GND U37 DDR2 001071 SSTL 1 0 R7 vss GND U39 DDR2_DQS_DP 09 SSTL 1 0 R9 DDR2 DQ 54 SSTL 1 0 U41 DDR2_DQ 05 SSTL 1 0 T10 DDR2 DQ 50 SSTL 1 0 U43 DDR_SCL_C23 ODCMOS 1 0 T12 DDR2_DQS_DP 15 SSTL 1 0 U45 PE3C_TX_DN 10 PCIEX3 14 DDR2 DQ 52 SSTL 1 0 U47 PE3A_TX_DN 2 PCIEX3 T16 0082 CAS SSTL 049 _ 7 PCIEX3 T18 DDR2 MA 10 SSTL U5 vss GND T20 DDR2 MA 03 SSTL 051 PE3B TX DN 5 PCIEX3 T22 DDR2 MA 08 SSTL 053 CMOS 1 0 T24 DDR2 MA 12 SSTL 055 2 DP 3 PCIEX3 T26 DDR2 CKE 1 SSTL 07 DDR2 DQ 44 SSTL 1 0 T2
8. The PECI is a one wire interface that provides a communication channel between a PECI client the processor and a PECI master the PCH Refer to the Processor Thermal Mechanical Specifications and Design Guide for additional details on PECI services available in the processor Refer to the Related Documents section Supports operation at up to 2 Mbps data transfers Link layer improvements to support additional services and higher efficiency over PECI 2 0 generation Services include processor thermal and estimated power information control functions for power limiting P state and T state control and access for Machine Check Architecture registers and PCI configuration space both within the processor package and downstream devices Single domain Domain 0 is supported Power Management Support Processor Package and Core States Advance Configuration and Power Interface ACPI C states as implemented by the following processor C states Package PCO PC1 PC1E PC2 PC6 Package C7 is not supported Core 6 CC7 Enhanced Intel SpeedStep Technology System States Support 50 S1 S3 54 S5 Memory Controller Multiple CKE power down modes Multiple self refresh modes e Memory thermal monitoring using MEM HOT 01 MEM HOT C23 signals PCI Express L1 ASPM power management capability LOs is not supported Thermal Management Support
9. 23 in System 53 Standby 130W 6 core 4 core 0 5 4 tate Notes 1 Unless otherwise noted all specifications in this table apply to all processors These specifications are based on final silicon characterization 2 Thermal Design Current is the sustained DC equivalent current that the processor is capable of drawing indefinitely and should be used for the voltage regulator thermal assessment The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion 3 Specification is at Tcase 50 C Characterized by design not tested 4 lccp o1 23 max refers only to the processor current draw and does not account for the current consumption by the memory devices Memory Standby Current is characterized by design and not tested 5 Minimum Vcc and maximum are specified at the maximum processor case temperature TcAsg Icc 15 specified at the relative Vcc max point on the Vcc load line The processor is capable of drawing Icc max for up to 5 seconds Refer to Figure 7 3 for further details on the average processor current draw over various time durations Datasheet 65 Electrical Specifications 7 5 2 Die Voltage Validation Core voltage Vcc overshoot events at the processor must meet the specifications in Table 7 12
10. DDR3 005 DP 07 SSTL 1 0 P20 DDR2_MA 04 SSTL M40 DDR3_DQ 12 SSTL 1 0 P22 DDR2 MA 07 SSTL M42 vss GND P24 DDR2 BA 2 SSTL M44 vss GND P26 55 GND M46 55 GND P28 DDR3 DQS DN 03 SSTL 1 0 M48 5 P30 VSS GND M50 vss GND P32 vss GND M52 vss GND P34 DDR2_DQ 21 SSTL 1 0 M54 1 _ 5 PCIEX3 P36 DDR2 001021 SSTL 1 0 M56 PE1B_RX_DN 7 PCIEX3 P38 VSS GND M6 DDR3 DQ 55 SSTL 1 0 P4 DDR3 DQ 59 SSTL 1 0 M8 55 GND 40 VSS GND N11 DDR3 DQS DP 05 SSTL 1 0 2 DDR VREFDQTX C2 DC N13 55 GND 3 5 VCCD 23 BWR PE3D TX DN 15 PCIEX3 17 VCCD 23 BUR 6 PE3C TX DP 8 PCIEX3 9 VCCD 23 PUR 8 TX PCIEX3 N21 VCCD 23 BUR P50 TX DP 6 PCIEX3 N23 VCCD 23 PUR P52 PE3B TX 4 PCIEX3 N25 DDR3_CKE 3 SSTL qus EP N27 DDR3 001301 SSTL Nae N29 DDR3_DQS_DP 03 SSTL 1 0 BRE 1 9 DDR3 DQ 58 SSTL GND N31 DDR3_DQS_DP 12 SSTL Rit vss GND aga Ge R13 0082 001481 SSTL 1 0 ser R15 10082 MA 13 SSTL wee SNB R17 DDR2_BA O SSTL N39 R19 DDR2_MA 01 SSTL END R21 DDR2_MA 06 SSTL ua wee END R23 0082 MA 09 SSTL ME VSA PUR R25 DDR3_CKE 4 SSTL a T HD R27 DDR3_CKE 5 SSTL ae WSS CND R29 vss GND NE CHE R3 55 GND NER EUR R31 55 GND
11. Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 15 of Number Sheet 16 of ue Land Name m Direction 5 Land Name gd Direction BM16 VSS GND BR57 VSS GND BM2 vss GND BR7 PWR BM4 vss GND BR9 PWR 42 PWR BT10 PWR BM44 RSVD BT12 VCC PWR 46 RSVD 14 VCC PWR BM6 55 GND BT16 VCC PWR BM8 vss GND 2 vcc PWR PWR vcc PWR 11 PWR 42 55 VTTD SENSE BN13 PWR BT44 RSVD BN15 VCC PWR BT46 VSS GND BN17 PWR 55 GND BN3 PWR BT50 55 GND BN43 vss GND BT52 55 GND BN45 vss GND 54 55 GND 7 RSVD BT56 55 GND BN5 VCC PWR BT6 vcc PWR BN7 VCC PWR BT8 PWR BN9 vcc PWR BU1 vcc PWR VCC PWR PWR BP12 VCC PWR vcc PWR BPl4 VCC PWR 015 VCC PWR 16 VCC PWR 017 PWR BP2 VCC PWR PWR BP4 vcc PWR BU43 RSVD BP42 VTTD_SENSE BUA5 vss GND BP44 RSVD BUA7 VTTD PWR BP46 RSVD 049 5 BP58 VSS GND BUS VCC PWR BP6 PWR BU51 VSS GND vcc PWR BU7 vcc PWR PWR vcc PWR BR11 PWR 10 vcc PWR BR13 VCC PWR BV12 VCC PWR BR15 VCC PWR 14 VCC PWR BR17 VCC PWR BV16 VCC PWR PWR BV2 PWR BRA3 RSVD 4 PWR BRA5 SVIDDATA ODCMOS 1 0 42 VTTD PWR BRA7 RSVD 4
12. DP 2 054 DDR3 117 SSTL DP 3 E55 PCIEX3 DDR3 00141 014 SSTL 0 TX K42 PCIEX3 DDR3_ODT 5 PUB SS 9 TX DN 1 43 G21 Su TX DNI2 K44 DER B16 9 TX DNI 3 145 DDR3 WE A15 SSTL TX DPIO H42 DMI E47 _ _ 1 143 PCIEX3 DMI DNI1 D48 PCIEX TX DPI2 H44 DMI RX DAS E49 PCIEX i TX Jas DHL BA DNA D50 PCIEX DNIA 153 RX DP 0 c47 l PE1B_RX_DN 5 M54 DMI DP 1 B48 PCIEX l PE1B_RX_DN 6 L57 PCI EX3 DMI DPI2 C49 PCIEX 1 _ _ 7 M56 PCIEX3 _ _ 3 850 DP 4 153 PCIEX3 DMI TX D42 PCIEX 80 81 intel Processor Land Listing Table 8 1 Land List by Land Name Table 8 1 LandList by Land Name Sheet 17 of 42 Sheet 18 of 42 Land Name rond Direction Land Name poo pubs Direction 1 DP 5 K54 PCIEX3 PE2C DN 11 057 1 DP 6 157 PCIEX3 PE2C DNI 8 AK56 PCIEX3 DP 7 K56 P
13. tel Processor Land Listing Table 8 1 Land List by Land Name Table 8 1 LandList by Land Name Sheet 9 of 42 Sheet 10 of 42 Land Name rod Direction Land Name pon puis Direction DDR2 CLK DNI 2 W21 SSTL DDR2 001281 5 SSTL 1 0 DDR2 CLK DN 3 W23 SSTL DDR2 001291 w35 SSTL 1 0 DDR2_CLK_DP 0 AB24 SSTL DDR2 001301 2 SSTL 1 0 DDR2_CLK_DP 1 AB22 SSTL DDR2 0901311 AD32 SSTL 1 0 DDR2_CLK_DP 2 AA21 SSTL DDR2 001321 AC13 SSTL 1 0 DDR2_CLK_DP 3 AA23 SSTL DDR2 001331 AE13 SSTL 1 0 DDR2_CS_N 0 AB20 SSTL DDR2 001341 AG11 SSTL 1 0 DDR2_CS_N 1 AE19 SSTL DDR2 001351 10 5511 DDR2 CS N 2 AD16 SSTL DDR2 001361 AD14 SSTL 1 0 DDR2_CS_N 3 15 5511 DDR2 001371 AA13 SSTL 1 0 DDR2_CS_N 4 19 5511 DDR2 DQ 38 AB10 SSTL 1 0 DDR2_CS_N 5 P18 SSTL DDR2 DQ 39 AD10 SSTL 1 0 DDR2 CS NI6 AB16 SSTL DDR2 DQ 40 V6 SSTL 1 0 DDR2 CS_N 7 Y16 SSTL 5582 Ye ssi DDR2 CS N 8 W17 SSTL DDR2 DQ 42 AF8 SSTL 1 0 DDR2 CS N 9 AA17 SSTL DDR2 001431 AG7 SSTL 1 0 DDR2_DQ 00 T40 SSTL 1 0 DDR2 DQ 44 U7 SSTL 1 0 DDR2_DQ 01 40 5511 1 0 DDR2 DQ 45 W7 SSTL 1 0 DDR2_DQ 02 P36 SSTL 1 0 DDR2 DQ 46 AD8 SSTL 1 0 DDR2_DQ 03 T36 SSTL 1 0 DDR2_DQ 47 AE7 SSTL 1 0 DDR2_DQ 04 R41 SSTL 1 0 DDR2 DQ 48 R13 SSTL 1 0 DDR2_DQ 05 U41 SSTL
14. 16 VSS GND 45 PWR CP18 DDRO CKE 3 SSTL CRA7 55 GND DDR1_DQ 01 SSTL 49 55 GND CP20 01 PWR CR5 vss GND CP22 VCCD 01 PWR CR51 PWR CP24 VCCD 01 PWR CR7 DDR1_DQ 16 SSTL 1 0 CP26 VCCD_01 PWR CR9 vss GND CP28 VCCD 01 PWR DDR1 001181 SSTL 1 0 CP30 DDR1_DQ 33 SSTL 1 0 2 1 01281 SSTL 1 0 CP32 DDR1 005 DP 04 SSTL 1 0 4 DDR1_DQS_DP 12 SSTL 1 0 CP34 DDR1 DQ 35 SSTL 1 0 CT16 DDR1 DQ 30 SSTL 1 0 CP36 VSS GND CT18 DDR1 CKE 5 SSTL CP38 DDR1 DQS DP 15 SSTL 1 0 CT2 DDR1_DQS_DP 09 SSTL 1 0 DDR1 DQ 00 SSTL CT20 DDR1 SSTL CP40 vss GND CT22 DDR1_ODT O SSTL CP42 vss GND CT24 DDR1 CS 5 SSTL 44 VSS GND CT26 DDR1 CS N 7 SSTL CP46 VSS GND CT28 VSS GND 48 VSS GND CT30 DDR1 001321 SSTL 1 0 CP50 VSS GND CT32 DDR1 DQS DN 04 SSTL 1 0 CP52 vss GND CT34 DDR1 01341 SSTL 1 0 54 RSVD CT36 1 01521 SSTL 1 0 56 VSS GND CT38 DDR1 DQS DN 15 SSTL 1 0 CP6 DDR1_DQ 20 SSTL 1 005 DN OO SSTL 1 0 CP8 DDR1_DQS_DP 11 SSTL 1 0 DDR1 01541 SSTL 1 0 DDR1_DQS_DN 09 SSTL 42 vss GND 11 55 GND CT54 TRST_N CMOS CR13 DDR1 001241 SSTL 1 001211 SSTL 1 0 15 DDR1_DQS_DN 03 SSTL 1 005 DN 11 SSTL 1 0 CR17 DDR1_DQ 26 SSTL CUl 55 GND CR19 DDR1_CKE 4 SSTL
15. 5 2 DF36 VSS GND F20 DDR3_MA 02 SSTL DF38 0957 sst F22 DDR3 061 SSTL DF40 DQ 63 sst F24 DDR3 151 SSTL 109 Datasheet Processor Land Listing Datasheet intel Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 33 of Number Sheet 34 of rog Land Name Direction po Land Name 4 Direction F28 DDR3 DQS DP 17 SSTL G7 DDR3 005 DP 15 SSTL 1 0 2 DDR3_DQ 19 SSTL 1 0 G9 55 GND F34 DDR3_DQ 17 SSTL 1 0 H10 vss GND F36 vss GND H12 vss GND F38 DDR3 DQ 06 SSTL 1 0 H14 55 GND F4 DDR3 DQ 60 SSTL H16 23 PWR F40 DDR3_DQ 04 SSTL 1 0 H18 VCCD_23 PWR F42 vss GND H2 DDR3 DQ 57 SSTL 1 0 F44 vss GND H20 VCCD_23 PWR F46 RSVD H22 VCCD_23 PWR F48 vss GND H24 VCCD 23 PWR F50 vss GND H28 005 DN 17 SSTL 1 0 F52 DN 1 PCIEX3 H32 55 GND F54 PE1A DN 2 PCIEX3 H34 55 GND F56 RSVD H36 DDR3 001151 SSTL 1 0 F58 RSVD H38 vss GND F6 DDR3_DQ 49 SSTL 1 0 DDR3 DQ 61 SSTL 1 0 F8 VSS GND 40 55 GND 61 55 GND H42 TX DP 0 PCIEX3 G11 DDR3 005 DN 13 SSTL 1 0 DP 2 PCIEX3 G13 2
16. TX 11 PCIEX3 11 vss GND 48 RSVD AA13 DDR2 001371 SSTL 1 0 50 4 PCIEX3 AA15 DDR2 CS N 3 SSTL AB52 DN 5 PCIEX3 AA17 DDR2 CS N 9 SSTL 54 2 DP 4 PCIEX3 AA19 DDR2 CS N 4 SSTL AB56 2 DP 5 PCIEX3 AA21 DP 2 SSTL AB6 vss GND AA23 DP 3 SSTL DDR2_DQS DN 05 SSTL 1 0 AA25 DDR2 CKE 0 SSTL 11 DDR2 DQS DN 04 5511 1 0 AA29 VSS GND AC13 DDR2 001321 SSTL 1 0 AA3 55 GND 15 DDR23_RCOMP 1 Analog AA31 vss GND 17 23 PWR AA33 DDR2 DQS DN 03 SSTL 19 VCCD 23 PWR AA35 DDR2 001281 SSTL AC21 VCCD 23 PWR AA37 DDR2 DQ 10 SSTL 1 0 AC23 VCCD 23 PWR AA39 VSS GND AC25 VCCD 23 PWR 41 DDR2 DQ 13 SSTL AC27 DDR2 005 DP 08 SSTL 1 0 AA43 TX DN 14 PCIEX3 AC29 DDR2 005 DP 17 SSTL 1 0 45 TX DP 12 PCIEX3 DDR2 005 DN O7 SSTL 1 0 47 PE3C TX 9 PCIEX3 1 vss GND 49 PCIEX3 AC33 DDR2 005 DP 03 SSTL 1 0 5 55 GND AC35 DDR2_DQ 24 SSTL 1 0 51 DP 7 PCIEX3 AC37 DDR2 01111 SSTL 1 0 AA53 DP 6 PCIEX3 AC39 DDR2 005 DN 10 5511 1 0 94 95 intel Processor Land Listing
17. pter xor 54 Serial Voltage Identification SVID Address 57 VR12 0 Reference Code Voltage Identification VID 58 Signal Description Buffer 0 000 59 Signal 59 Signals with On Die Termination 2 memes enn 62 Power On Configuration Option Lands sss 62 Processor Absolute Minimum and Maximum 63 Storage gt 63 gt em D OOANDAUBWNEF O COON NJ NJ Voltage Specifications iecit RR T 64 65 Overshoot 5 11 66 DDR3 DDR3L Signal DC 5 5 1 67 DG Specifications dete 68 System Reference Clock BCLK 0 1 DC 68 SMBus DC SpecifiCatioris oce e e HR ERAT TE ER EE XA VERE RA 69 Joint Test Action Group J TAG and Test Access Point TAP Signals DC Specifications 69 Serial VID Interfac
18. 23 2122 Intel VP Features AA 24 3 1 3 Intel VT d OD CCU Ss vna bone 24 3 1 4 Intel virtualization Technology Processor 25 23 2 Security Technologies trag eene REA 26 3 2 1 Intel Advanced Encryption Standard New Instructions Intel AES NI I ristpuctioris cineri attire Pret Endo egenis 26 3 2 2 Execute Disable 26 3 3 Intel Hyper Threading Technology Intel HT 26 3 4 Intel Turbo Boost Technology ntex ot a tes e ck trier aine 27 3 4 1 Intel Turbo Boost Operating Frequency 4744 441 27 3 5 Enhanced Intel SpeedStep Henne 27 3 6 Intel Advanced Vector Extensions Intel AVX 28 4 Power Management ore c en ka aT Naa 30 4 1 Advanced Configuration and Power Interface ACPI States Supported 30 4 1 L System States EYE 30 4 1 2 Processor Package and Core 30 4 1 3 Integrated Memory Controller 5 5 32 4 1
19. 44 ODCMOS DDRO CS N 5 CF26 SSTL BPM NIA BB44 ODCMOS 1 0 DDRO CS N 6 CB26 SSTL N 5 Aw43 ODCMOS 1 0 DDRO CS N 7 CC25 SSTL NI6 BA43 ODCMOS 1 0 DDRO CS N 8 CL27 SSTL NI7 AY44 ODCMOS 1 0 DDRO CS N 9 CK28 SSTL CAT ERR ODCMOS 1 0 DDRO 0010017 CC7 SSTL 1 0 CPU ONLY RESET AN43 ODCMOS 1 0 DDRO_DQ 01 CD8 SSTL 1 0 DDR_RESET_CO1_N 18 CMOS1 5 DDRO_DQ 02 CK8 SSTL 1 0 DDRO DQ 03 CL9 SSTL DDR RESET C23 N CMOSLS UG DDR SCL 01 opcwos 1 0 DDR0_DQ 05 CAI 288 DDR SCL C23 043 opcwos 1 0 25106 illa DDR SDA 01 CW41 ODCMOS 1 0 DDRO_DQ 07 SSTL 1 0 DDR_SDA_C23 843 ODCMOS DDRO_DQ 08 CB2 SSTL 1 0 DDR_VREFDQRX_C BY16 DC DDRO 001091 SSTL 1 0 01 DDRO DQ 10 SSTL 1 0 11 DDRO DQ 11 5 SSTL 1 0 DDR VREFDQTX C 41 DC 74 01 DDRO DQ 13 CA3 SSTL 1 0 DDR VREFDQTX C P42 DC DDRO_DQ 14 CG3 SSTL 23 DDRO 09115 CG5 SSTL DDR0_BA O0 i DDRO 09116 CKIZ SSTL DDRO_BA 1 997 o DDRO_DQ 17 CM12 SSTL DERE Bele DDRO 00118 16 SSTL DDRO CAS N CL29 SSTL DDRO DOLS Tm DDRO SSTL DDRO 50020 Ud DDRO_CKE 1 CM18 SSTL DDRO DOLI TTE SET TIS DDRO CKE 2 CH20 SSTL 5085 cHs Sem DDRO_CKE 3 9 DDRO DQI23 CL15 SSTL
20. MWAIT redirection is used By default P LVLx I O redirections enable the MWAIT break on EFLAGS IF feature which triggers a wakeup on an interrupt even if interrupts are masked by EFLAGS IF 35 intel m 4 2 4 4 2 4 1 4 2 4 2 4 2 4 3 4 2 4 4 4 2 4 5 36 Core C states The following are general rules for all core C states unless specified otherwise core C state is determined by the lowest numerical thread state such as Thread 0 requests while Thread 1 requests resulting a core CIE state See Table 4 6 Acore transitions to CO state when an interrupt occurs there is an access to the monitored address if the state was entered using an MWAIT instruction For core 1 and core an interrupt directed toward a single thread wakes only that thread However since both threads are no longer at the same core C state the core resolves to CO An interrupt only wakes the target thread for both C3 and C6 states Any interrupt coming into the processor package may wake any core Core CO State The normal operating state of a core where code is being executed Core C1 CIE State C1 C1E is a low power state entered when all threads within a core execute HLT or MWAIT C1 C1E instruction A System Management Interrupt SMI handler returns execution to either Normal state or the C1 CIE state See the Intel 64 and 1 32 Architecture Software Develope
21. Chip Select Each signal selects one rank as the target of the command and address DDR 0 1 2 3 _DQ 63 00 Data Bus DDR3 Data bits DDR 0 1 2 3 _DQS_DP 17 00 DDR 0 1 2 3 _DQS_DN 17 00 Data strobe This is a differential pair Data Strobe Differential strobes latch data for each DRAM Different numbers of strobes are used depending on whether the connected DRAMs are x4 x8 Driven with edges in center of data receive edges are aligned with data edges DDR 0 1 2 3 _MA 15 00 Memory Address Selects the Row address for Reads and writes and the column address for activates Also used to set values for DRAM configuration registers DDR 0 1 2 3 _ODT 5 0 On Die Termination Enables DRAM on die termination during Data Write or Data Read transactions DDR 0 1 2 3 _RAS_N Row Address Strobe DDR 0 1 2 3 _WE_N Write Enable Datasheet Signal Descriptions Table 6 2 6 2 Note Table 6 3 Table 6 4 Datasheet Memory Channel Miscellaneous intel Signal Name Description DDR RESET 01 DDR RESET C23 N System Memory Reset Reset signal from processor to DRAM devices on the DIMMs DDR RESET 01 N is used for memory channels 0 and 1 while DDR RESET C23 N is used for memory channels 2 and 3 SMBus clock for the dedicated interface to the serial presence detect SPD and DDR SCL CO1 thermal sensors TSoD the DIMMs DDR SCL 1 is u
22. Digital Thermal Sensor with multiple on die temperature zones Adaptive Thermal Monitor THERMTRIP N and PROCHOT N signal support On Demand mode clock modulation Fan speed control with DTS Two integrated SMBus masters for accessing thermal data from DI MMs New Memory Thermal Throttling features using MEM HOT 01 23 signals 13 1 7 Table 1 1 14 I ntroduction Package Summary The processor socket type is noted as LGA2011 The processor package is a 52 5 x 45 mm FC LGA package LGA2011 Refer to the Processor Thermal Mechanical Specification and Design Guide see Related Documents section for the package mechanical specifications Terminology Terminology Sheet 1 of 3 Term Description ACPI Advanced Configuration and Power Interface ASPM Active State Power Management CCM Continuous Conduction Mode DCM Discontinuous Conduction Mode DDR3 Third generation Double Data Rate SDRAM memory technology that is the successor to DDR2 SDRAM DMA Direct Memory Access DMI Direct Media Interface DMI2 Direct Media Interface Gen 2 DTS Digital Thermal Sensor Enhanced Intel SpeedStep Technology EIST Allows the operating system to reduce power consumption when performance is not needed EPT Extended Page Tables ESD Electro Static Discharge Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or non executable when combine
23. SSTL J39 55 GND L13 DDR3 SSTL 55 GND 15 DRAM PWR OK C2 51 5 1 1 145 TX PCIEX3 L17 DDR2_BA 1 SSTL 147 TX DP 5 PCIEX3 119 DDR3_ODT 0 SSTL TX S L21 DDR3 DP 1 SSTL 5 1965 L23 DDR3 SSTL J51 TX DP 1 PCIEX3 125 55 GND J53 PCIEX3 127 DDR3 001271 SSTL 1 0 155 55 GND 129 55 GND 57 DP 6 PCIEX3 E Liu J7 DDR3 005 SSTL 1 0 L31 01251 SSTL 70 Jo 50142 UM TS L33 5083 001281 SSTL K10 00146 SSTL 1 0 L35 DDR3_DQ 10 SSTL 1 0 K12 DDR3_DQS_DP 14 SSTL 70 137 005 SSTL 1 0 14 20144 SSTL 1 0 L39 DDR3_DQ 09 SSTL 1 0 K16 CS 9 SSTL 1 DDR3 CS S L43 PE1A TX DN 1 PCIEX3 EH 145 TX PCIEX3 K20 5083 DP 2 SSTL L47 1 _ 5 PCIEX3 K22 DDR3 DN 3 SSTL 149 PEIB TX DNI7 PCIEX3 K24 DDR3 SSTL L5 55 GND vss SND L51 TX vss L53 PCIEX3 SND L55 2 DP O 5083 00129 L57 DN 6 K34 vss END L7 DDR3 DQ 54
24. DDR 0 1 2 3 BA 2 0 DDR 0 1 2 3 CAS DDR 0 1 2 3 _MA 15 00 SSTL Output Single ended ds DDR 0 1 2 3 DDR 0 1 2 3 RAS 00840 1 2 3 WE CMOS1 5v Output DDR_RESET_C 01 23 _N 59 intel Table 7 5 Signal Groups Sheet 2 of 3 Electrical Specifications Differential Single Ended Buffer Signals DDR3 Control Signals CMOS1 5v Output DDR 0 1 2 3 _CS_N 9 0 DDR 0 1 2 3 _ ODT 5 0 DDR 0 1 2 3 _CKE 5 0 andis ended Reference Output DDR VREFDQTX C 01 23 Reference Input DDR VREFDQRX C 01 23 DDR 01 23 RCOMP 2 0 DDR3 Data Signals Differential SSTL Input Output DDR 0 1 2 3 _DQS_D N P 17 00 SSTL Input Output Single ended SSTL Input DDR 0 1 2 3 _DQ 63 00 208 0 1 2 3 PAR ERR DDR3 Miscellaneous Signals Single ended CMOS1 5v Input DRAM PWR 01 23 PCI Express Port 1 2 and 3 Signals Differential PCI Express Input D N P 3 0 PE1B D N P 7 4 PE2A D N P 3 0 PE2B D N P 7 4 2 D N P 11 8 2 D N P 15 12 D N P 3 0 7 41 D N P 11 8 D N P 15 12 Differential PCI Express Output TX D N P 3 0 PE1B TX D N P 7 4 PE2A TX D N P 3 0 PE2B TX DI N P 7 4 PE2C TX D N P 11 8 PE2D TX D N P 15 12 PE3A TX D N P 3 0 PE3B TX DI N P
25. DDRO_CKE 4 9 DDRO DQI24 SSTL 1 0 DDRO CKE 5 CE19 SSTL 0 DDRO 001251 12 SSTL DDRO CLK DN O CF24 SSTL DDRO 50026 TIS DDRO DN 1 CE23 SSTL 00027 PT US DDRO CLK DN 2 CE21 SSTL 50228 BUS TIS DDRO CLK DN 3 CF22 SSTL 5929 TE SEND TIS DDRO DP 0 CH24 SSTL 50130 PH Datasheet Processor Land Listing Datasheet intel Table 8 1 Land List by Land Name Table 8 1 Land List by Land Name Sheet 3 of 42 Sheet 4 of 42 Land Name po 2 Direction Land Name pong pod Direction DDRO 001311 CF10 SSTL DDRO 005 DN 11 CL13 SSTL 1 0 DDRO DQ 32 CE31 SSTL 1 0 DDRO DQS DN 12 CC11 SSTL 1 0 DDRO_DQ 33 CC31 SSTL DDRO 005 DN 13 CB32 SSTL 1 0 DDRO DQ 34 CE35 SSTL 1 0 DDRO DQS DN 14 CH32 SSTL 1 0 DDRO_DQ 35 CC35 SSTL DDRO 005 DN 15 CE39 SSTL 1 0 DDRO_DQ 36 CD30 SSTL DDRO 005 DN 16 CL39 SSTL 1 0 DDRO_DQ 37 CB30 SSTL DDRO 005 DN 17 16 SSTL 1 0 DDRO DQ 38 CD34 SSTL DDRO 005 DP 00 CH8 SSTL 1 0 DDRO 001391 CB34 SSTL DDRO 005 DP 01 CF4 SSTL 1 0 DDRO_DQ 40 CL31 SSTL DDRO 005 DP 02 14 SSTL 1 0 DDRO DQ 41 CJ31 SSTL DDRO 005 DP 03 11 SSTL 1 0 DDRO DQ 42 CL35 SSTL DDRO 005 DP 04 SSTL
26. 5 1 00 mmm 45 6 3 Direct Media Interface Gen 2 DMI2 PCI Express Port 0 47 6 4 Platform Environment Control Interface 2 1 7 47 6 5 System Reference Clock Signals 47 6 6 Joint Test Action Group TAG and Test Access Point 51 5 47 6 7 Serial Voltage Identification SVID 0 02 4 0 0 48 6 8 Processor Asynchronous Sideband and Miscellaneous 5 48 6 9 Processor Power and Ground Supplies emm 51 Electrical Specifications 0 0000102 52 7 1 Processor Signalin guaniinissa erede reet orte idees ever 52 7 1 1 System Memory Interface Signal 00 222 52 7 1 2 PCLExpress Signals oreet ERA ERE RE 52 7 1 3 Direct Media Interface Gen 2 DMI2 PCI Express Signals 52 7 1 4 Platform Environmental Control Interface 53 7 1 5 System Reference Clocks BCLK 0 1 DP BCLK 0 1 53 7 1 6 Joint Test Action Group TAG and Test Access Port TAP Signals otto e pest
27. A 3 1 2 Intel VT x Features The processor core supports the following Intel VT x features Extended Page Tables EPT hardware assisted page table virtualization eliminates VM exits from guest operating system to the VMM for shadow page table maintenance Virtual Processor IDs VPID Ability to assign a VM ID to tag processor core hardware structures such as TLBs This avoids flushes on VM transitions to give a lower cost VM transition time and an overall reduction in virtualization overhead Guest Preemption Timer Mechanism for a VMM to preempt the execution of a guest operating system after an amount of time specified by the VMM The VMM sets a timer value before entering a guest The feature aids VMM developers in flexibility and Quality of Service QoS guarantees Descriptor Table Exiting Descriptor table exiting allows a VMM to protect a guest operating system from internal malicious software based attack by preventing relocation of key system data structures like IDT interrupt descriptor table GDT global descriptor table LDT local descriptor table and TSS task segment selector A VMM using this feature can intercept by a VM exit attempts to relocate these data structures and prevent them from being tampered by malicious software Pause Loop Exiting PLE PLE aims to improve virtualization performance and enhance the scaling of virtual machines w
28. DDR1 DQ 10 SSTL 1 0 DA21 DDR1_CLK_DN 3 SSTL DC15 DDR1 005 DP 08 SSTL 1 0 DA23 DDR1_MA 03 SSTL DC17 DDR1 15 SSTL DA25 DDR1 11 SSTL DC19 DDR1 MA 12 SSTL DA27 DDR1 CS N 9 SSTL DC21 DDR1 SSTL DA29 DDR1 CS N 6 SSTL DC23 DDR1 001 SSTL 1 55 GND DC25 DDR1 1 SSTL DA31 DDR1_DQ 44 SSTL DC3 55 GND DA33 DDR1 DQ 40 SSTL 1 0 DC33 DDR1 005 DP 14 SSTL 1 0 DA35 DDR1 DQI 43 SSTL 1 0 DC35 DDR1_DQ 42 SSTL DA37 DDR1 001601 SSTL DC37 DDR1 001611 SSTL 1 0 DA39 DDR1_DQ 62 SSTL DC39 DDR1 005 DP 07 SSTL 1 0 DA41 VSS GND 1 VSS GND DA43 VSS GND DC5 55 GND DA45 VSS GND DC55 RSVD DA47 VSS GND DC7 1 01091 SSTL 1 0 108 tel Processor Land Listing Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 31 of Number Sheet 32 of 4 Land Direction Land Name d Direction DC9 1 005 DN Ol SSTL 1 0 DF42 vss GND DD10 55 GND 44 vss GND DD12 VSS GND DF46 vss GND DD14 vss GND DFA8 55 GND DD18 VCCD 01 PWR DF50 55 GND DD20 VCCD 01 PWR DF52 55 GND DD22 VCCD 01 PWR DF8 55 GND DD24 VCCD 01 PWR E1 vss GND DD26 VCCD 01 PWR E11 0083 005 DP 13 SSTL 1 0 0032 DDR1_DQ 41 SSTL 1 0 E13 HOT C23 ODCMOS 1 0 0034 vss GND E15
29. DDR3 CS NI7 SSTL 0036 vss GND E17 DDR3 0017121 SSTL 0038 vss GND E19 DDR3 BA 1 SSTL DD40 DQ 58 sst E21 DDR3 MA O1 SSTL 0054 RSVD E23 DDR3_MA 12 SSTL 006 55 GND E27 0083 005 DP 08 SSTL 1 0 DD8 DDR1_DQS_DP 10 SSTL 1 0 E29 vss GND DE11 DDR1_DQ 11 SSTL 1 0 vss GND DE15 DDR1_DQS_DN 08 SSTL 1 0 vss GND DE17 vss GND E33 DDR3 005 021 SSTL 1 0 DE19 DDR1_MAI 11 SSTL 9 E35 DDR3 DQI20 SSTL 1 0 DE21 DDR1_MA 06 SSTL 7 DDR3_DQ 03 SSTL 1 0 DE23 DDR1 MA 01 SSTL 9 DDR3_DQS_DP 09 SSTL 1 0 DE25 DDR1_MA_PAR SSTL E41 vss GND DE33 DDRI 005 DN 14 SSTL 1 0 E43 DMI TX DNI1 PCIEX DE35 1 00147 551 E45 TX DN3 o DE37 DDR1 001561 SSTL 1 0 E47 DMI_RX_DN 0 PCIEX DE39 1 005 DN 07 SSTL 1 0 E49 DNI2 PCIEX DE41 vss GND E5 VSS GND DE53 vss GND E51 1 DNIO PCIEX3 DE55 RSVD E53 RSVD DE7 vss GND E55 PE1A DPI3 PCIEX3 DE9 DDR1_DQS_DP 01 SSTL 1 0 E57 RSVD DF10 DDR1_DQ 15 SSTL 1 0 E7 DDR3 DQIA8 SSTL 1 0 DF12 VSS GND E9 DDR3 001351 SSTL 1 0 DF18 DDR1_BA 2 SSTL F10 DDR3_DQ 38 SSTL 1 0 DF20 DDR1 07 SSTL F12 DDR3_DQ 36 SSTL 1 0 DF22 DDR1 MA 05 SSTL F14 DDR3 CS 2 SSTL DF24 DDR1 MA 02 SSTL 9 F16 DDR3 CS 6 SSTL DF26 DDR1 MA 10 SSTL F18 _ 1 SSTL 9 DF34 DDRI1 001461 SSTL 1 0
30. Discontinuous Conduction Mode mode Datasheet m 9 Electrical Specifications n tel Figure 7 2 7 1 8 3 6 Table 7 2 Datasheet reduce the switching frequency or pulse skip or change to asynchronous regulation For example typical power states are 00 run in normal mode a command of O1h shed phases mode and 02h pulse skip The VR may reduce the number of active phases from PS 00h to PS O1h or 5 00 to PS 02h for example There are multiple VR design schemes that can be used to maintain a greater efficiency in these different power states work with your VR controller suppliers for optimizations The SetPS command sends a byte that is encoded as to what power state the VR should transition to If a power state is not supported by the controller the slave should acknowledge with command rejected 11b If the VR is in a low power state and receives a SetVID command moving the VID up the VR exits the low power state to normal mode 50 to move the voltage up as fast as possible The processor must re issue the low power state PS1 or PS2 command if it is in a low current condition at the new higher voltage See Figure 7 2 for VR power state transitions Voltage Regulator VR Power State Transitions d SVID Voltage Rail Addressing The processor addresses four different voltage rail control segments within VR12 Vcc Vccp 1 23 and The SVID data packet contai
31. VCCD 23 14 lands must be supplied a fixed 1 0V supply 19 Vttp lands must be supplied by a fixed 1 0V supply Each VSA land must be supplied with the voltage determined by the 25 SVID Bus signals typically set at 0 940V has VBOOT setting of 0 9V Vss 548 Ground Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Large electrolytic bulk capacitors help maintain the output voltage during current transients such as transients when coming out of an idle condition Care must be used in the baseboard design to ensure that the voltages provided to the processor remain within the specifications listed in Table 7 10 Failure to do so can result in timing violations or reduced lifetime of the processor Voltage Identification VID The reference voltage or the VID setting is set using the SVID communication bus between the processor and the voltage regulator controller chip The VID settings are the nominal voltages to be delivered to the processor VCC VSA VCCD lands Table 7 3 specifies the reference voltage level corresponding to the VID value transmitted over serial VID The VID codes will change due to temperature and or current
32. VSS GND CR21 DDR1 CS N 8 SSTL CU13 DDR1 001251 SSTL 1 0 CR23 DDR1_CS_N 2 SSTL CU15 DDR1 005 DP 03 SSTL 1 0 CR25 DDRO 011 SSTL CU17 DDR1_DQ 27 SSTL 1 0 CR27 DDR1_CS_N 3 SSTL CU19 DDR1_CKE 1 SSTL CR29 DDR1 001371 SSTL CU21 DDRI1 PAR ERR SSTL DDR1_DQS_DP 00 SSTL 1 0 CU23 DDR1_CS_N 1 SSTL CR31 DDR1 005 DN 13 SSTL CU25 1 CS N 4 SSTL 106 intel 107 Processor Land Listing Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 27 of Number Sheet 28 of pos Land Name Direction w Land Name d Direction CU27 DDRI1 ODI 4 SSTL CW25 VCCD 01 PWR CU29 DDR1 001361 SSTL 1 0 CW27 VCCD 01 PWR vss GND CW29 55 GND CU31 DDR1 005 DP 13 SSTL 1 0 CW3 DDR1_DQ 07 SSTL CU33 DDR1 DQ 38 SSTL 1 0 CW31 VSS GND CU35 VSS GND CW33 VSS GND CU37 DDR1 DQ 49 SSTL 1 0 CW35 VSS GND CU39 DDR1 005 DP 06 SSTL 1 0 CW37 VSS GND CU41 DDR1_DQ 51 SSTL 1 0 CW39 55 GND 5 vss GND CW41 DDR SDA 01 ODCMOS 1 0 CU7 DDR1_DQ 17 SSTL 1 0 CW5 55 GND CU9 DDR1_DQS_DP 02 SSTL 1 0 CW51 VSS GND CV10 DDR1 001231 SSTL 1 0 CW53 VSS GND CV12 DDR1 001291 SSTL 1 0 CW55 55 GND 14 vss GND CW57 VSS GND CV16 1 001311 SSTL 1 0 cw7 vss G
33. 1 0 DDR2 DQ 49 U13 SSTL 1 0 DDR2_DQ 06 R37 SSTL 1 0 DDR2 DQ 50 T10 SSTL 1 0 DDR2_DQ 07 U37 SSTL 1 0 DDR2 DQ 51 V10 SSTL DDR2 001081 AE41 SSTL 1 0 DDR2 DQ 52 T14 SSTL 1 0 DbR2 9 551 1 0 0082 2959 sst wo DDR2_DQ 10 AA37 SSTL 1 0 DDR2_DQ 54 R9 SSTL 1 0 DDR2_DQ 11 AC37 SSTL DDR2 DQ 55 U9 SSTL 1 0 DDR2_DQ 12 AC41 SSTL 1 0 DDR2 DQ 56 W3 SSTL 1 0 DDR2_DQ 13 AA41 SSTL 1 0 DDR2 DQ 57 Y4 SSTL 1 0 DDR2_DQ 14 AF38 SSTL 1 0 DDR2 DQ 58 4 5511 1 0 DDR2_DQ 15 AE37 SSTL 1 0 DDR2 DQ 59 AE5 SSTL 1 0 DDR2_DQ 16 U33 SSTL 1 0 DDR2_DQ 60 U3 SSTL 1 0 DDR2_DQ 17 R33 SSTL 1 0 DDR2 DQ 61 V4 SSTL 1 0 DDR2_DQ 18 w29 SSTL 1 0 DDR2 DQ 62 AF2 SSTL 1 0 DDR2_DQ 19 U29 SSTL 1 0 DDR2 DQ 63 AE3 SSTL 1 0 DDR2_DQ 20 T34 SSTL 1 0 DDR2 DQS DN 00 T38 SSTL 1 0 DDR2_DQ 21 P34 SSTL 1 0 DDR2_DQS_DN 01 AD38 SSTL 1 0 DDR2_DQ 22 SSTL 1 0 DDR2 DQS DN 02 W31 SSTL 1 0 DDR2_DQ 23 T30 SSTL 1 0 DDR2 DQS DN 03 AA33 SSTL 1 0 DDR2_DQ 24 AC35 SSTL 1 0 DDR2_DQS_DN 04 11 5511 1 0 DDR2_DQ 25 AE35 SSTL 1 0 DDR2_DQS_DN 05 AB8 SSTL 1 0 DDR2_DQ 26 5511 05 sst vo DDR2 DQI27 AF32 551 1 0 0082 05 sst 0 Datasheet Processor Land Listing Datasheet intel Table 8 1 Land List by Land Na
34. 14 PCIEX3 11 vss GND 48 PWR AR13 VSS GND 50 2 TX DP 1 PCIEX3 AR15 VSS GND 52 2 TX PCIEX3 AR17 VSS GND 54 vrTA PwR AR3 55 GND AM56 55 GND ODCMOS 58 2 DN 9 PCIEX3 5 DN 15 PCIEX3 AM6 VCC PWR 47 PE3D DN 13 PCIEX3 8 VCC PWR 49 TX DNI O PCIEX3 AN1 VCC PWR ARS 55 GND 11 VCC PWR AR51 2 TX DNI2 PCIEX3 AN13 VCC PWR AR53 2 TX DNI6 PCIEX3 15 VCC PWR 55 RSVD AN17 VCC PWR AR57 DP 11 PCIEX3 AN3 VCC PWR AR7 55 GND 4 CPU ONLY RESET 5 AR9 VSS GND 45 PE3D_RX_DP 15 PCIEX3 10 55 GND 47 DP 13 PCIEX3 12 VSS GND 49 2 TX PCIEX3 14 55 GND AN5 VCC PWR AT16 55 GND 51 PE2A_TX_DP 2 PCIEX3 2 55 GND AN53 PE2B TX DP 6 PCIEX3 55 GND AN55 1 66 GND AT42 PWR Datasheet Processor Land Listing Datasheet intel Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 9 of 42 Number Sheet 10 of 3 Land 5 Direction pow Land Name Direction _ 1 ODCMO
35. 4 14 Q IL Leakage Current 50 200 Output Edge Rate 50 ohm to Vy between Vi and 0 05 0 6 V ns Table 7 17 Joint Test Action Group J TAG and Test Access Point TAP Signals DC Specifications Symbol Parameter Min Max Units Notes Input Low Voltage 0 3 V r V Input High Voltage 0 7 Vir V Input Low Voltage PREQ N 0 4 VT V Input High Voltage PREQ N 0 8 Vir V VoL Output Low Voltage 0 2 V r V Vuysteresis Hysteresis 0 1 V Buffer On Resistance R 4 14 Q ON BPM_N 7 0 PRDY_N TDO lu Input Leakage Current 50 200 uA Input Edge Rate Signals BPM N 7 0 EAR N PREQ N TCK TDI 0 05 x V ns 1 2 TMS TRST N Output Edge Rate 50 ohm to 0 2 1 5 V 1 Signal N 7 0 PRDY TDO ins Note 1 These signals are measured between and 2 The signal edge rate must be met or the signal must transition monotonically to the asserted state Table 7 18 Serial VID Interface SVID DC Specifications Symbol Parameter Min Typ Max Units Notes Vit Processor 1 Voltage 3 1 0 VTT 396 V Input Low Voltage Signals SVIDDATA SVIDALERT E E y 1 Input High Voltage Signals SVIDDATA SVIDALERT Output Low Voltage Vor Signals SVIDCLK SVIDDATA ori 1 Vuysteresis Hysteresis 0 05 Vir V 1 Buffer On Resistance RON Signals SVIDCLK SVIDDATA i i n 2 lu Input Leakage Current x50 200 uA 3 Input Edge Rate Signal SVIDA
36. 7 4 PE3C TX DI N P 11 8 PE3D TX D N P 15 12 PCI Express Miscellaneous Signals Analog Input PE RBIAS SENSE Single ended Reference Input Output PE RBIAS PE VREF CAP DMI 2 PCI Express Signals DMI2 Input Differential D N P 3 0 DMI2 Output TX D N P 3 0 Platform Environmental Control I nterface Single ended PECI PECI System Reference Clock BCLK 0 1 Differential CMOS1 0v Input SMBus 60 BCLK 0 1 _D N P Datasheet Electrical Specifications Table 7 5 Datasheet Signal Groups Sheet 3 of 3 Differential i 1 Single Ended Buffer Signals DDR SCL C 01 23 Open Drain CMOS DDR SDA 01 23 Single ended Input Output PEHPSDA JTAG and TAP Signals CMOS1 0v Input TCK TDI TMS TRST N CMOS1 0v Input Output PREQ N Single ended CMOS1 0v Output PRDY_N Open Drain CMOS BPM N 7 0 Input Output EAR N Open Drain CMOS Output TDO Serial VID Interface SVI D Signals CMOS1 0v Input SVIDALERT N Open Drain CMOS SVIDDATA Single ended Input Output Open Drain CMOS Output SVIDCLK Processor Asynchronous Sideband Signals BIST ENABLE PWRGOOD PMSYNC CMOS1 0v Input RESET N SAFE MODE BOOT TXT AGENT Single ended PLTEN B ERR pen Drain Input Output MEM C 01 23 PROCHOT N ERROR N 2 0 Open Drain CMOS Outp
37. DDR1 005 DN 05 CY34 SSTL DDR1 MA 12 DC19 SSTL DDR1 005 DN 06 CR39 SSTL DDR1 131 0830 SSTL DDR1 005 DN 07 DE39 SSTL DDR1 MA 14 DB18 SSTL DDR1 005 DN 08 15 SSTL DDR1 151 DC17 SSTL DDR1 005 DN 09 1 SSTL 1 0 DDR1_ODT 0 22 SSTL DDR1 DQS DN 10 088 SSTL DDR1 ODI 1 DA25 SSTL DDR1 005 DN 11 CT8 SSTL 1 0 DDR1 ODT 2 CY26 SSTL DDR1 DQS DN 12 14 SSTL DDR1 ODT 3 CV26 SSTL DDR1 005 DN 13 CR31 SSTL 1 0 DDR1_ODT 4 CU27 SSTL DDR1 DQS DN 14 SSTL 1 0 DDR1_ODT 5 CY28 SSTL DDR1 005 DN 15 CT38 SSTL 1 0 DDR1_PAR_ERR_N CU21 SSTL DDR1 005 DN 16 CY38 SSTL DDR1 RAS DB28 SSTL DDR1 DQS DN 17 0814 SSTL DDR1 WE CV28 SSTL DDR1 DQS DP 00 SSTL 1 0 DDR2_BA 0 R17 SSTL DDR1_DQS_DP 01 SSTL 1 0 DDR2_BA 1 L17 SSTL DDR1 DQS DP 02 Cu9 SSTL DDR2 BA 2 P24 SSTL DDR1 DQS DP 03 CUI5 SSTL DDR2 CAS N T16 SSTL DDR1 DQS DP 04 CP32 SSTL DDR2 CKE 0 AA25 SSTL DDR1 DQS DP 05 0834 SSTL 1 0 DDR2_CKE 1 T26 SSTL DDR1 DQS DP 06 CU39 SSTL 1 0 DDR2_CKE 2 U27 SSTL DDR1 DQS DP 07 DC39 SSTL DDR2 CKE 3 AD24 SSTL DDR1 DQS DP 08 DC15 SSTL DDR2 CKE 4 AE25 SSTL DDR1 DQS DP 09 SSTL DDR2 CKE 5 AE23 SSTL DDR1 DQS DP 10 008 SSTL 1 0 DDR2_CLK_DN 0 Y24 SSTL DDR1 DQS DP 11 8 SSTL 1 0 DDR2_CLK_DN 1 Y22 SSTL 76
38. DDRO 005 DN 05 CL33 SSTL 1 0 DDRO MA 12 CK20 SSTL DDRO 005 DN 06 40 SSTL 1 0 DDRO MA 13 CG29 SSTL DDRO 005 DN 07 40 SSTL 1 0 DDRO MA 14 CG19 SSTL DDRO_DQS_DN 08 17 SSTL DDRO 151 CN19 SSTL DDRO 005 DN 09 CF8 SSTL 1 0 DDRO ODT O0 CE25 SSTL DDRO DQS DN 10 SSTL 1 0 DDRO_ODT 1 CE27 SSTL 74 75 intel Processor Land Listing Table 8 1 Land List by Land Name Table 8 1 Land List by Land Name Sheet 5 of 42 Sheet 6 of 42 Land Name big Direction Land Name pou 1 Direction DDRO ODT 2 CH28 SSTL DDR1 001061 2 5511 1 0 DDRO_ODT 3 CF28 SSTL DDR1 DQ O07 CW3 SSTL 1 0 DDRO_ODT 4 CB24 SSTL DDR1 001081 DA7 SSTL 1 0 DDRO_ODT 5 CC27 SSTL DDR1 001091 DC7 SSTL 1 0 DDRO_PAR_ERR_N CC21 SSTL DDR1 DQ 10 DC11 SSTL 1 0 DDRO_RAS_N CE29 SSTL DDR1 001111 DE11 SSTL 1 0 DDRO_WE_N CN29 SSTL DDR1 DQ 12 CY6 SSTL 1 0 DDRO1_RCOMP 0 CA17 Analog 2081_00 13 086 5511 DDRO1 RCOMP 1 CC19 Analog DDR1 DQ 14 DB10 SSTL 1 0 DDRO1_RCOMP 2 CB20 Analog DDR1 DQ 15 DF10 SSTL 1 0 DDR1 DB26 SSTL DDR1 001161 5511 1 0 DDR1 BA 1 DC25 SSTL DDR1 0901171 CU7 SSTL 1 0 DDR1_BA 2 DF18 SSTL DDR1 001181 CT10 SSTL 1 0 DDR1_CAS_N CY30 SSTL DDR1 DQ 19 CP10 SSTL 1 0 DDR1_CKE 0 CT20 SSTL DDR1 DQ 20 CP6 SST
39. GND WES SND AF10 DDR2 DQ 35 SSTL AD36 55 GND ARIS 5 GND AD38 DDR2 505 DNIOl SSTL jo AF14 VSS VSA SENSE DDR2 005 DN 16 SSTL 1 0 16 55 GND 40 DDR2 9 SSTL AF18 IVSA PWR vss END AF2 DDR2 DQ 62 SSTL AD44 55 GND AF20 VSS GND AD46 55 GND 22 PWR AD48 55 GND PWR ADSO 55 GND AF26 GND AD52 VSS GND AF32 DDR2_DQ 27 SSTL 1 0 54 2 PCIEX3 nre 52 GND AD56 PE2B 5 PCIEX3 AF30 7 GND ADS vss SND AF38 DDR2 DQ 14 SSTL DDR2 DQ 46 SSTL 1 0 AF4 DDR2_DQ 58 SSTL 1 0 11 DDR2 DQS DP 04 SSTL 1 0 BU GND AE13 DDR2 00133 SSTL AF42 V55 GND IVSA BWR AF44 DP O PCIEX3 BUE AF46 DP 2 PCIEX3 AE19 DDR2 CS 1 SSTL 48 DP 8 PCIEX3 AE21 DDR2 ODTIS 5 AF50 PE3C_RX_DP 10 PCIEX3 AE23 DDR2 5 TET AF52 PE RBIAS SENSE PCIEX3 Datasheet Processor Land Listing Datasheet intel Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 5 of 42 Number Sheet 6 of 42 Land Direction po Land Name dm Direction AF54 55 GND 50 DN 10 PCIEX3 AF56 55 GND AH52 RBIAS 1
40. GND 15 DDRO 001231 SSTL 1 0 CN19 DDRO MA 15 SSTL CL17 vss GND CN21 DDRO MA 09 SSTL CL19 DDRO CKE 0 SSTL CN23 DDRO MA 06 SSTL CL21 DDRO MA 11 SSTL CN25 _ 5_ 0 SSTL CL23 DDRO MA 05 SSTL CN27 DDRO 1 SSTL CL25 DDRO MA 00 SSTL CN29 DDRO WE SSTL CL27 DDRO CS 8 SSTL vss GND CL29 DDRO CAS N SSTL CN31 55 GND DDR1_DQ 05 SSTL 1 0 CN33 VSS GND CL31 DDRO DQ 40 SSTL 1 0 CN35 55 GND CL33 DDRO DQS DN 05 SSTL 1 0 CN37 VSS GND CL35 DDRO_DQ 42 SSTL 1 0 CN39 vss GND CL37 DDRO DQ 61 SSTL 1 0 CN41 DDR VREFDQTX CO DC CL39 DDRO 005 DN 16 SSTL 1 0 1 CL41 DDRO DQ 63 SSTL 1 0 Dp 1 CLA3 VSS GND 083 SND wee CHE CN53 vss GND CL7 DDRO_DQ 07 SSTL 1 0 GND 105 Datasheet Processor Land Listing Datasheet intel Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 25 of Number Sheet 26 of Land aA Direction pow Land Name 4 Direction CN57 VSS GND CR33 DDR1 001391 SSTL 1 0 CN7 vss GND CR35 55 GND CN9 vss GND CR37 DDR1 001481 SSTL 1 0 CP10 DDR1_DQ 19 SSTL CR39 1 005 DN O6 SSTL 1 0 CP12 VSS GND CR41 DDR1 DQ 50 SSTL 1 0 CPl4 DDR1 005 DN 12 SSTL SVIDALERT CMOS
41. Output DMI TX DNI 3 0 Platform Environment Control nterface Signal Platform Environment Control I nterface PECI Signals Signal Name Description Platform Environment Control I nterface This signal is the serial sideband PECI interface to the processor and is used primarily for thermal power and error management System Reference Clock Signals System Reference Clock BCLK 0 1 Signals Signal Name Description Reference Clock Differential input These signals provide the PLL reference BCLK 0 1 DIN P clock differential input into the processor 100 MHz typical BCLKO is the system clock and BCLK1 is the PCI Express reference clock Joint Test Action Group J TAG and Test Access Point TAP Signals Joint Test Action Group J TAG and Test Access Port TAP Signals Sheet 1 of 2 Signal Name Description Breakpoint and Performance Monitor Signals O signals from the processor BPM N 7 0 that indicate the status of breakpoints and programmable counters used for monitoring processor performance These are 100 MHz signals External Alignment of Reset This signal is used to bring the processor up into EAR N a deterministic state This signal is pulled up on the die refer to Table 7 6 for details Probe Mode Ready This signal is a processor output used by debug tools to determine processor debug readiness N Probe Mode R
42. PCI Express Lane Partitioning and Direct Media Interface Gen 2 DMI2 12 PCI Express Layering 19 Packet Flow through the 20 Idle Power Management Breakdown of the Processor 34 Thread and Core C State Entry and Exit 34 Package C State Entry and 1 6 nn nnn 38 Input Device Hysteresis icc coded roter ror ____ 53 Voltage Regulator VR Power State Transitions sss nmn 57 Overshoot Example Waveform sss nee 66 dees 14 Processor 9 16 P blic Specifications x ri exe Ek RR REX TR RO 17 System e RIEN ECT NERO 30 Package C State 5 ii Rr FERE er 31 Core C State SUppOLE ics tie sea ERN Qo Ax RR AERE E ES TET EK ER 31 System Memory Power 54 11 02 2 11 6 6 32 DMI2 Express Link States reete rte enr Ra ek ee Der 32 5 and C State Combinations
43. PWR BJA5 RSVD BF12 VCC PWR 47 1 0 14 VCC PWR BJ5 VCC PWR BF16 VCC PWR BJ53 PWRGOOD CMOS vcc PWR BJ55 vss GND 4 vcc PWR BJ57 vss GND BF42 vss GND BJ7 vcc PWR BF44 VSS GND VCC PWR 46 RSVD BK10 VCC PWR 48 PEHPSDA ODCMOS BK12 VCC PWR BF6 Vcc PWR 14 VCC PWR BF8 VCC PWR BK16 PWR PWR BK2 vcc PWR BGll VCC PWR BK4 PWR BG13 PWR BK42 VSS GND 15 PWR BK44 RSVD BG17 PWR BK46 vss GND PWR 48 vss GND BG43 RSVD BK50 vss GND BG45 5 BK52 VSS GND BG47 VSS GND BK54 VSS GND BG5 PWR BK56 VTTD PWR BG7 PWR BK6 PWR BG9 PWR BK8 PWR 10 PWR BL1 vss GND BH12 VCC PWR 11 VSS GND 14 VCC PWR BL13 VSS GND 16 VCC PWR BL15 VSS GND BH2 VCC PWR BL17 VSS GND PWR BL3 vss GND 42 VTTD PWR BLA3 BH44 RSVD BL45 5 BH46 RSVD 8147 ODCMOS 48 PEHPSCL ODCMOS 1 0 8149 VSS GND BH58 vss GND BL5 vss GND PWR BL51 VTTD PWR BH8 VCC PWR BL7 vss GND 1 PWR BL9 55 GND 11 VCC PWR 10 VSS GND BJ13 VCC PWR 12 VSS GND BJ15 VCC PWR 14 VSS GND 100 intel Processor Land Listing
44. PWR VCC BR9 PWR VCC BH8 PWR VCC BT10 PWR VCC BJ1 PWR VCC BT12 PWR VCC BJ11 PWR VCC BT14 PWR VCC BJ 13 PWR VCC BT16 PWR VCC BJ15 PWR BT2 PWR BJ BT4 PWR VCC BJ3 PWR BT6 PWR VCC BJ5 PWR VCC BT8 PWR VCC BJ7 PWR VCC BU1 PWR VCC BJ9 PWR VCC BU11 PWR VCC BK10 PWR VCC BU13 PWR VCC BK12 PWR VCC BU15 PWR VCC BK14 PWR VCC BU17 PWR VCC BK16 PWR VCC BU3 PWR VCC BK2 PWR VCC BU5 PWR VCC BK4 PWR VCC BU7 PWR VCC BK6 PWR VCC BU9 PWR BV10 PWR VCC BN1 PWR VCC BV12 PWR VCC BN11 PWR VCC BV14 PWR VCC BN13 PWR VCC BV16 PWR VCC BN15 PWR VCC BV2 PWR VCC BN17 PWR VCC BV4 PWR VCC BN3 PWR VCC BV6 PWR VCC BN5 PWR VCC BV8 PWR VCC BN7 PWR VCC BY18 PWR VCC BN9 PWR VCC BY26 PWR VCC BP10 PWR VCC BY28 PWR VCC BP12 PWR VCC BY30 PWR VCC BP14 PWR VCC BY32 PWR VCC BP16 PWR VCC BY34 PWR VCC BP2 PWR VCC BY36 PWR VCC BP4 PWR VCC BY38 PWR VCC BP6 PWR VCC BY40 PWR 25 PWR PWR CA29 PWR Datasheet Processor Land Listing Datasheet intel Table 8 1 Land List by Land Name Table 8 1 Land List by Land Name Sheet 27 of 42 Sheet 28 of 42 Land Name pog reed Direction Land Name pong 5 Direction VCC SENSE BW3 VCCD 23 N19 PWR VCCD 01 CD20 PWR VCCD 23 N21 PWR VCCD 01
45. SERR activity is associated with Device 0 Processor PCH Compatibility Assumptions The processor is compatible with the PCH and is not compatible with any previous Intel Memory Controller Hub MCH and Integrated Controller Hub ICH products DMI 2 Link Down The DMI2 link going down is a fatal unrecoverable error If the DMI2 data link goes to data link down after the link was up then the DMI2 link hangs the system by not allowing the link to retrain to prevent data corruption This is controlled by the PCH Downstream transactions that had been successfully transmitted across the link prior to the link going down may be processed as normal No completions from downstream non posted transactions are returned upstream over the DMI2 link after a link down event Platform Environment Control I nterface The Platform Environment Control Interface PECI uses a single wire for self clocking and data transfer The bus requires no additional control lines The physical layer is a self clocked one wire bus that begins each bit with a driven rising edge from an idle level near zero volts The duration of the signal driven high depends on whether the bit value is a logic 0 or logic 1 also includes variable data transfer rate established with every message In this way it is highly flexible even though underlying logic is simple 21 22 The interface design was optimized for interfacing to Intel
46. SSTL 1 0 DDR1_DQ 05 CL3 SSTL DDR1 DQ 49 CU37 SSTL 1 0 Datasheet Processor Land Listing Datasheet intel Table 8 1 Land List by Land Name Table 8 1 Land List by Land Name Sheet 7 of 42 Sheet 8 of 42 Land Name 2 Direction Land Name pong pod Direction DDR1 DQ 50 CR41 SSTL DDR1 005 DP 12 14 SSTL 1 0 DDR1 DQ 51 CU41 SSTL DDR1 005 DP 13 CU31 SSTL 1 0 DDR1_DQ 52 CT36 SSTL DDR1 005 DP 14 DC33 SSTL 1 0 DDR1_DQ 53 CV36 SSTL DDR1 005 DP 15 CP38 SSTL 1 0 DDR1 DQ 54 SSTL 1 0 DDR1 005 DP 16 0838 SSTL 1 0 DDR1 DQ 55 40 SSTL 1 0 DDR1_DQS_DP 17 14 SSTL 1 0 DDR1_DQ 56 DE37 SSTL DDR1 DE25 SSTL DDR1 DQ 57 DF38 SSTL DDR1 MA 00 DC23 SSTL DDR1 DQ 58 0040 SSTL 1 0 DDR1_MA 01 DE23 SSTL DDR1 DQ 59 0840 SSTL 1 0 DDR1 MA 02 DF24 SSTL DDR1 001601 DA37 SSTL DDR1 MA 03 DA23 SSTL DDR1 001611 DC37 SSTL DDR1 041 DB22 SSTL DDR1 DQ 62 DA39 SSTL 1 0 DDR1 MA 05 DF22 SSTL DDR1 001631 DF40 SSTL DDR1 MA 06 DE21 SSTL DDR1 005 01 SSTL 1 0 DDR1 071 DF20 SSTL DDR1 DQS DN Ol DC9 SSTL 1 0 DDR1 MA 08 DB20 SSTL DDR1 005 DN 02 CV8 SSTL DDR1 MA 09 DA19 SSTL DDR1 005 DN 03 15 SSTL 1 0 DDR1_MA 10 DF26 SSTL DDR1 005 DN O4 CT32 SSTL 1 0 DDR1_MA 11 DE19 SSTL
47. Solution Thermal solution assembly Thermal interface material pre applied Installation and warranty manual Datasheet
48. Transmit Data Output PE3B TX DN 7 4 PE3B TX DP 7 4 PCIe Transmit Data Output PE3C TX DN 11 8 PE3C TX DP 11 8 PCIe Transmit Data Output PE3D TX DN 15 12 PE3D TX DP 15 12 PCIe Transmit Data Output PCI Express Misce llaneous Signals Signal Name Description PE RBIAS PCI RBIAS This input is used to control PCI Express bias currents 50 ohm 196 tolerance resistor must be connected from this land to Vss by the platform RBIAS is required to be connected as if the link is being used even when is not used PE RBIAS SENSE PCI RBIAS Sense This signal provides dedicated bias resistor sensing to minimize the voltage drop caused by packaging and platform effects PE RBIAS SENSE is required to be connected as if the link is being used even when PCle is not used PE VREF CAP 46 PCI Express Voltage Reference PE VREF CAP is used to measure the actual output voltage and comparing it to the assumed voltage A 0 01 uF capacitor must be connected from this land to Vss Datasheet Signal Descriptions n tel 6 3 Table 6 7 6 4 Table 6 8 6 5 Table 6 9 6 6 Table 6 10 Datasheet Direct Media nterface Gen 2 DMI2 PCI Express Port O Signals DMI 2 and PCI Express Port 0 Signals Signal Name Description DN 3 0 2 Receive Data Input DP 3 0 TX DP 3 0 DMI2 Transmit Data
49. VTTD BK56 PWR VTTD BL51 PWR VTTD BM42 PWR VTTD BR55 PWR VTTD 8047 PWR Datasheet Processor Land Listing Datasheet intel Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 1 of 42 Number Sheet 2 of 42 Land Direction pow Land Name Direction 11 DDR3 DQ 33 SSTL 55 VSS GND A13 0083 13 SSTL AA7 2 005 DN 14 SSTL 1 0 A15 DDR3_WE_N SSTL AA9 vss GND A17 0083 01 SSTL DDR2 DQ 38 SSTL 1 0 A19 DDR3 MA 00 SSTL 12 DDR2 005 DP 13 SSTL 1 0 A21 DDR3 MA 05 SSTL 14 VSS GND A23 DDR3 11 SSTL AB16 DDR2 CS N 6 SSTL A33 DDR3 001221 SSTL AB18 DDR2 MA 00 SSTL A35 0083 00 16 SSTL 1 0 AB20 DDR2_CS_N O SSTL A37 0083 001071 SSTL 1 0 AB22 DDR2 DP 1 SSTL A39 DDR3 001011 SSTL AB24 DDR2 SSTL 41 VSS GND AB28 DDR2 DQS DN 08 SSTL 1 0 4 55 GND AB32 DDR2 DQ 30 SSTL 1 0 A45 VSS GND AB34 DDR2 DQS DN 12 SSTL 1 0 47 VSS GND AB36 vss GND A49 55 GND AB38 DDR2_DQS_DP 01 SSTL 1 0 A5 VSS GND DDR2 005 DP 07 SSTL 1 0 A51 55 GND 40 DDR2 005 DP 10 SSTL 1 0 A53 RSVD 42 VSS GND A7 1 55 GND 44 PE3D TX DN 13 PCIEX3 A9 DDR3_DQ 39 SSTL 46
50. e SetVID fast 20mV ys for 10mV us for VsA Vccp 55 m n tel Electrical Specifications 7 1 8 3 2 7 1 8 3 3 7 1 8 3 4 7 1 8 3 5 56 e SetVID slow 5mV us for 2 5mV ys for VsA Vccp and Slew Rate Decay downward voltage only and it is a function of the output capacitance time constant commands Table 7 3 includes SVID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 7 10 The VRM or EVRD used must be capable of regulating its output to the value defined by the new VID Power source characteristics must be ensured to be stable when the supply to the voltage regulator is stable SetVI D Fast Command The SetVI D fast command contains the target VID in the payload byte The range of voltage is defined in the VID table The VR should ramp to the new VID setting with a fast slew rate as defined in the slew rate data register typically 10 to 20 mV us depending on platform voltage rail and the amount of decoupling capacitance The SetVI D fast command is preemptive the VR interrupts its current processes and moves to the new VID The SetVID fast command operates on one VR address at a time This command is used in the processor for package C6 fast exit and entry SetVI D Slow Command The SetVI D slow command contains the target VID in the payload byte The range of voltage is defined in the VID table The VR should ramp to the new VID setting with
51. fixed analog and digital power supply for 1 0 sections of the processor VTID Direct Media Interface Gen 2 DMI2 interface and PCI Express interface These signals will also be referred to as VTT m 88 51 m e n tel Electrical Specifications 7 7 1 7 1 1 7 1 2 7 1 3 52 Electrical Specifications This chapter covers the following topics Processor Signaling Signal Group Summary Power On Configuration POC Options Absolute Maximum and Minimum Ratings DC Specifications Processor Signaling The processor includes 2011 lands that use various signaling technologies Signals are grouped by electrical characteristics and buffer type into various signal groups These include DDR3 Reference Clock Command Control and Data PCI Express DMI2 Platform Environmental Control Interface PECI System Reference Clock SMBus JTAG and Test Access Port TAP SVID Interface Processor Asynchronous Sideband Miscellaneous and Power Other signals Refer to Table 7 5 for details System Memory I nterface Signal Groups The system memory interface uses DDR3 technology that consists of numerous signal groups These include Reference Clocks Command Signals Control Signals and Data Signals Each group consists of numerous signals that may use various signaling technologies Refer to Table 7 5 for further details Throughout this chapter the system memory interface may be referred to as DDR3 PCI Exp
52. processor and chipset components in both single processor and multiple processor environments The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components Bus speed error checking and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information Interfaces Datasheet Technologies 3 3 1 3 1 1 Datasheet Technologies This chapter covers the following technologies Intel virtualization Technology Intel VT Security Technologies Intel Hyper Threading Technology Intel HT Technology Intel Turbo Boost Technology Enhanced Intel SpeedStep Technology Intel Advanced Vector Extensions Intel AVX I ntel virtualization Technology Intel VT Intel virtualization Technology Intel VT makes a single system appear as multiple independent systems to software This allows multiple independent operating systems to run simultaneously on a single system Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets Intel Virtualization Technology Intel VT for Intel 64 and 32 Intel Architecture Intel VT x adds hardware support in the processor to improve the virtualization performance and robustness Intel VT x s
53. their specifications 7 Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until the supplies come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD PWRGOOD transitions from inactive to active when all supplies except are stable Vcc has VBOOT of zero volts and is not included in PWRGOOD indication in this phase However for the active to inactive transition if any processor power supply Vcc is about to fail or is out of regulation the PWRGOOD is to be negated The signal must be supplied to the processor It is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation Note Vcc has a VBOOT setting of 0 0V is not included in the PWRGOOD indication and VSA has a Vboot setting of 0 9V RESET N Reset Asserting the RESET N signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents Some PLL and error states are not effected by reset and only PWRGOOD forces them to a known state SAFE MODE BOOT Safe Mode Boot Strap signal SAFE MODE BOOT allows the processor to
54. wake up safely by disabling all clock gating This allows BIOS to load registers or patches if required This signal is sampled after PWRGOOD assertion The signal is pulled down on the die refer to Table 7 6 for details TEST 4 0 Test Test 4 0 must be individually connected to an appropriate power source or ground through a resistor for proper processor operation Thermal Trip Assertion indicates of two possible critical over temperature conditions The processor junction temperature has reached a level beyond which permanent silicon damage may occur and The system memory interface has exceeded a critical temperature limit set by BIOS Measurement of the processor junction temperature is accomplished through multiple internal thermal sensors that are monitored by the Digital Thermal Sensor DTS Simultaneously the Power Control Unit PCU monitors external memory temperatures using the dedicated SMBus interface to the DIMMs If any of the DIMMs exceed the BIOS defined limits the PCU will signal THERMTRIP to prevent damage to the DIMMs Once activated the processor will stop all execution and shut down all PLLs To further protect the processor its core voltage Vcc Vsa supplies must be removed following the assertion of THERMTRIP Once activated THERMTRIP N remains latched until RESET N is asserted W
55. when measured across the VCC SENSE and VSS VCC SENSE lands Overshoot events that are 10 ns in duration may be ignored These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope 7 5 2 1 Vcc Overshoot Specifications The processor can tolerate short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos Vos is the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the VCC SENSE and VSS VCC SENSE lands Table 7 12 Vcc Overshoot Specifications Symbol Parameter Min Max Units Figure Notes Vos MAX Magnitude of Vcc overshoot above VID 65 7 3 Time duration of Vcc overshoot above VccMAX Tos value at the new lighter load 25 ms Figure 7 3 Vcc Overshoot Example Waveform VID Vos max Vos gt 9 VccMAX 11 5 E Tos 0 5 10 15 20 25 Time us 66 Notes 1 Vos is the measured overshoot voltage 2 Tos wax 5 the measured time duration above VccMAX I1 3 Load Release Current Step for example 12 to 11 where 12 gt 11 4 VccMAX 11 VID I1 RLL 15mV Datasheet Electrical Specifications intel
56. 0 TX 45 DDR3 005 21 N31 SSTL 1 0 DMI_TX_DP 0 B42 PCIEX DDR3 005 DPL13 E11 SSTL 1 0 C43 PCIEX DDR3 005 141 12 SSTL 1 0 DMI_TX_DP 2 B44 PCIEX DDR3 005 51 G7 SSTL 1 0 DMI_TX_DP 3 C45 PCIEX DDR3 005 161 13 SSTL 1 0 TXT_PLTEN V52 CMOS DDR3 DQS DP 17 F28 SSTL 1 0 DRAM PWR OK CO 17 CMOS1 5 DDR3 MA PAR B18 SSTL 1 s T DRAM PWR C2 115 CMOS1 5 DDR3 01 E21 SSTL 0 EAR CH56 ODCMOS 1 0 DDR3 MA 02 F20 SSTL 0 ERROR BD50 5 DDR3 031 B20 SSTL ERROR N 1 CB54 ODCMOS DDR3 MA 04 D20 0 ERROR 2 BC51 ODCMOS DDR3 MA 05 A21 SSTL VT IDN 5 DDR3 MA 06 22 SSTL AGENT AK52 CMOS DDR3 822 SSTL MEM HOT CO CB22 1 0 DDR3_MA 08 D22 SSTL MEM HOT C23 N E13 1 0 DbR3 MALOS G23 SSTL o PE RBIAS AH52 PCIEX3 1 0 DDR3_MA 10 DIR is PE RBIAS SENSE AF52 PCIEX3 DDR3_MA 11 A23 SUE 9 PE VREF CAP DDR3 MA 12 E23 SSTL E51 PCIEX3 DDR3 MA 13 A13 SSTL 52 PCIEX3 DDR3 MA 14 D24 SSTL DN 2 F54 PCIEX3 DDR3_MA 15 F24 ds o DNI3 655 DDR3 ODT O L19 Sum C51 DDR3_ODT 1 F18 S d 052 PCIEX3 DDR3_ODT 2 E17 SSTL
57. 0 AF58 2 DNI 7 PCIEX3 54 TX 5 PCIEX3 AF6 vss GND 56 DP 8 PCIEX3 AF8 DDR2 001421 SSTL 1 0 AH58 VSS GND AG1 55 GND AH6 5 PWR AG11 DDR2 DQ 34 SSTL 1 0 AH8 5 PWR AG13 VSA SENSE AJi VSA PWR AG15 VSA PWR 11 VSA PWR AG17 VSA PWR 13 VSA PWR AG19 VCC PWR 15 vss GND AG21 PWR AJi7 vss GND AG23 PWR AJ3 VSA PWR AG25 VCC PWR 43 PE VREF CAP PCIEX3 1 0 AG27 PWR 45 DNI 1 PCIEX3 29 Vcc PWR 47 DN 12 PCIEX3 55 GND AJ49 DN 11 PCIEX3 AG31 PWR 5 VSA PWR AG33 PWR AJ51 DNI 9 PCIEX3 AG35 PWR AJ53 2 TX DNI4 PCIEX3 AG37 PWR AJ55 RSVD AG39 vcc PWR AJ57 2 DP 10 PCIEX3 41 PWR 7 VSA PWR 43 VSS GND 9 VSA PWR 45 DP 1 PCIEX3 10 vss GND 47 PE3D DP 12 PCIEX3 12 vss GND 49 DP 11 PCIEX3 14 vss GND AG5 55 GND AK16 vss GND 51 DP 9 PCIEX3 2 55 GND AG53 2 TX DP 4 PCIEX3 AKA 55 GND AG55 55 GND 42 VSS GND AG57 VSS GND 44 vss GND AG7 DDR2 001431 SSTL 46 vss GND 9 55 GND 48 vss GND 10 5 PWR 50 vss GND AH12 VSA PWR AK52 AGENT CMOS 14 VSA PWR AK54 2 TX DN 5 PCIEX3 AH
58. 0 140 V 6 VTH Threshold Voltage Single Ended Vcross 0 1 Vcross 0 1 V lu Input Leakage Current N A 1 50 8 Cpad Pad Capacitance N A 0 9 1 2 pF Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies These specifications are specified at the processor pad 2 Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK 0 1 DN is equal to the falling edge of BCLK 0 1 DP 3 iS the statistical average of the VH measured by the oscilloscope 68 Datasheet Electrical Specifications n tel The crossing point must meet the absolute and relative crossing point specifications simultaneously be measured directly using Vtop on Agilent and High on Tektronix oscilloscopes Vcnoss is defined as the total variation of all crossing voltages as defined in Note 3 The rising edge of 1 DN is equal to the falling edge BCLK 0 1 DP For Vin between 0 and Table 7 16 SMBus DC Specifications Symbol Parameter Min Max Units Notes Input Low Voltage m 0 3 Vir V Input Voltage 0 7 VIT V Vuysteresis Hysteresis 0 1 VIT V VoL Output Low Voltage 02 V Buffer On Resistance
59. 1 0 DDRO_DQ 43 CJ35 SSTL 1 0 DDRO_DQS_DP 05 SSTL 1 0 DDRO_DQ 44 CK30 SSTL DDRO 005 DP 06 CD40 SSTL 1 0 DDRO_DQ 45 CH30 SSTL DDRO 005 DP 07 CK40 SSTL 1 0 DDRO_DQ 46 CK34 SSTL DDRO 005 DP 08 17 SSTL 1 0 DDRO_DQ 47 CH34 SSTL DDRO 005 DP 09 SSTL 1 0 DDRO_DQ 48 CB38 SSTL DDRO 005 DP 10 5 SSTL 1 0 DDRO_DQ 49 CD38 SSTL 1 0 DDRO_DQS_DP 11 CJ13 SSTL 1 0 DDRO DQ 50 41 SSTL 1 0 DDRO 005 DP 12 10 SSTL 1 0 DDRO DQ 51 CD42 SSTL DDRO 005 DP 13 CD32 SSTL 1 0 DDRO_DQ 52 CC37 SSTL DDRO 005 DP 14 CK32 SSTL 1 0 DDRO_DQ 53 CE37 SSTL DDRO 005 DP 15 CC39 SSTL 1 0 DDRO_DQ 54 1 SSTL 1 0 DDRO_DQS_DP 16 SSTL 1 0 DDRO DQ 55 CB42 SSTL DDRO 005 DP 17 CD16 SSTL 1 0 DDRO_DQ 56 CH38 SSTL 1 0 DDRO_MA_PAR CM26 SSTL DDRO 001571 CK38 SSTL DDRO MA 00 CL25 SSTL DDRO 001581 CH42 SSTL 1 0 DDRO MA 01 CR25 SSTL DDRO DQ 59 CK42 SSTL 1 0 DDRO MA 02 CG25 SSTL DDRO 001601 CJ 37 SSTL 1 0 DDRO MA 03 CK24 SSTL DDRO 001611 CL37 SSTL DDRO MA 04 CM24 SSTL DDRO 001621 41 SSTL 1 0 DDRO MA 05 CL23 SSTL DDRO 001631 CL41 SSTL 1 0 DDRO MA 06 CN23 SSTL DDRO 005 DN OO CG7 SSTL DDRO MA 07 CM22 SSTL DDRO DQS DN O1 SSTL DDRO MA 08 CK22 SSTL DDRO DQS DN 02 14 SSTL DDRO MA 09 CN21 SSTL DDRO 005 DN 03 CD10 SSTL DDRO MA 10 CK26 SSTL DDRO DQS DN 04 CE33 SSTL 1 0 DDRO MA 11 CL21 SSTL
60. 1371 SSTL 1 0 48 PE2D TX DP 14 PCIEX3 B14 DDR3_CAS_N SSTL AV50 PE2D TX DP 12 PCIEX3 Bl6 DDR3_RAS_N SSTL AV52 2 TX DP 8 PCIEX3 B18 _ PAR SSTL 54 vss GND B20 0083_ 03 SSTL 56 vss GND B22 071 SSTL AV58 PE2D DN 12 PCIEX3 B24 DDR3_BA 2 SSTL AV6 PWR B32 DDR3_DQ 23 SSTL 1 0 AV8 PWR B34 DDR3 005 DN 11 SSTL 1 0 1 PWR B36 55 GND 98 tel Processor Land Listing Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 11 of Number Sheet 12 of 4 Land pe Direction p Land Name d Direction B38 DDR3_DQS DN 00 SSTL 1 0 BB8 PWR B40 DDR3_DQ 00 SSTL 1 0 BCl 55 GND B42 DMI TX PCIEX 11 vss GND 44 DMI TX DPI 2 PCIEX BC13 vss GND B46 RSVD 15 VSS GND B48 0 DP 1 PCIEX BC17 VSS GND B50 0 DP 3 PCIEX BC3 55 GND B52 vss GND BC43 vss GND 854 5 PWR 45 vss GND vss GND 47 RSVD VsS GND BC5 VSS GND PWR BC51 ERROR_N 2 ODCMOS 11 VCC PWR BC53 VSS GND Ba3 vcC PwR BC55 vss GND 15 PWR BC57 VSS GND 17 PWR VSS GND PWR BC9 55 GND BA43 61 OD
61. 16 5 PWR 56 2 DNI 8 PCIEX3 VSA PWR 58 2 DP 9 PCIEX3 VSA PWR AK6 55 GND 42 IVT ID AK8 55 GND 44 PCIEX3 AL1 VCC PWR AH46 PE3A_RX_DN 2 PCIEX3 111 VCC PWR 48 PE3C 8 PCIEX3 VCC PWR 96 tel Processor Land Listing Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 7 of 42 Number Sheet 8 of 42 poss Land Name 1 Direction w Land Name d Direction 115 PWR AN57 VSS GND AL17 vcc PWR AN7 PWR AL3 vcc PWR AN9 vcc PWR AL43 vss GND AP10 PWR AL45 55 GND 12 VCC PWR AL49 55 GND 14 PWR AL5 VCC PWR AP16 VCC PWR AL51 vss GND 2 VCC PWR ALS3 vss GND VCC PWR 155 RSVD AP42 VSS GND ALS7 2 DN 10 PCIEX3 55 GND AL7 PWR AP46 DN 14 PCIEX3 AL9 VCC PWR 8 RSVD amo vcc AP50 2 TX DNI1 PCIEX3 12 Vcc PWR AP52 2 TX DNI 3 PCIEX3 14 PWR 54 2 TX DP 7 PCIEX3 16 PWR AP56 PE2D DP 13 PCIEX3 AM2 VCC PWR 58 55 GND AMA PWR 6 VCC PWR 42 VTTD PWR VCC PWR 44 RSVD AR1 vss GND 46 DP
62. 28 GND 55 46 GND 55 34 GND 55 M50 GND 55 v36 GND 55 M52 GND 55 42 GND 55 M8 GND 55 44 GND 55 N13 GND 55 46 GND 55 N33 GND 55 48 GND 55 N35 GND 55 v50 GND 55 N37 GND 55 v8 GND 55 N41 GND 55 W13 GND 55 N43 GND 55 w33 GND 55 47 GND 55 w37 GND 55 N49 GND 55 W41 GND 55 N5 GND 55 W43 GND 55 N53 GND 55 45 GND 55 GND 55 W47 GND VSS P10 GND VSS w5 GND 92 e n tel Processor Land Listing Table 8 1 Land List by Land Name Table 8 1 Land List by Land Name Sheet 41 of 42 Sheet 42 of 42 Land Name ro Direction Land Name pon pulis Direction VSS w51 GND VTTD BV42 PWR vss W53 GND VTTD BY20 PWR vss w9 GND VTTD BY22 PWR 55 Y10 GND VTTD CA21 PWR vss Y12 GND VTTD CA23 PWR vss Y28 GND VTTD_SENSE BP42 VSS Y30 GND VSS Y32 GND VSS Y36 GND VSS Y38 GND VSS Y40 GND vss Y42 GND 55 Y56 GND vss 5 VSS VSA SENSE AF14 VSS VITD SENSE 42 45 PWR VTTA AE53 PWR VTTA 48 PWR VTTA 54 PWR VTTA AU53 PWR CA53 PWR VTTA CC45 PWR VTTA CG55 PWR VTTA CJ49 PWR VTTA CR45 PWR CR51 PWR VTTA 49 PWR VTTA w49 PWR Y54 PWR VTTD AF22 PWR VTTD AF24 PWR VTTD AG21 PWR VTTD AG23 PWR VTTD 42 PWR VTTD AT42 PWR VTTD AY42 PWR VTTD BD42 PWR VTTD BH42 PWR
63. 3 PE2D TX DN 14 AY48 PCIEX3 PE2A TX DP 3 52 PCIEX3 PE2D TX DN 15 47 PCIEX3 PE2B 4 AD54 PCIEX3 PE2D TX DP 12 AV50 PCIEX3 PE2B RX DN 5 AD56 PCIEX3 PE2D TX DP 13 49 PCIEX3 PE2B RX DN 6 AE55 PCIEX3 PE2D TX DP 14 AV48 PCIEX3 PE2B DN 7 AF58 PCIEX3 PE2D TX DP 15 47 PCIEX3 2 4 54 PCIEX3 AH44 PCIEX3 2 DP 5 AB56 PCIEX3 DNI1 45 PCIEX3 2 DP 6 55 PCIEX3 2 46 PCIEX3 2 DP 7 AE57 PCIEX3 49 PCIEX3 PE2B DN 4 53 RX DP 0 44 PCIEX3 PE2B TX DN 5 AK54 PCIEX3 1 45 PCIEX3 PE2B TX DN 6 AR53 PCIEX3 DPI 2 AF46 PCIEX3 PE2B TX 7 AT54 PCIEX3 49 PE2B TX DP 4 AG53 PCIEX3 PE3A_TX_DN 0 K50 PCI EX3 PE2B TX DP 5 AH54 PCIEX3 PE3A_TX_DN 1 L51 PCIEX3 PE2B TX DP 6 AN53 PCIEX3 PE3A_TX_DN 2 047 PE2B TX DP 7 54 PCIEX3 T48 PCIEX3 PE2C RX DN 10 AL57 PCIEX3 TX DP 0 H50 PCIEX3 Datasheet Processor Land Listing Datasheet intel Table 8 1 Land List by Land Name Table 8 1 La
64. 3 PWR TX DP 4 PCIEX3 615 _ 5_ 3 SSTL 48 TX DP 6 PCIEX3 G17 _ 5_ 5 SSTL H50 TX DP 0 PCIEX3 G19 DDR3 CS SSTL 52 55 GND G21 DDR3 PAR ERR SSTL H54 VSS GND G23 DDR3 MA 09 SSTL H56 5 625 vss GND H58 RSVD G27 DDR3 005 DN 08 SSTL 1 0 H6 DDR3 DQS DN 15 SSTL 1 0 G3 DDR3 DQ 56 SSTL H8 VSS GND G31 55 GND Ji DDR VREFDQRX C2 DC G33 DDR3 005 DN 02 SSTL 1 0 3 G35 vss GND GND T WE 113 DDR3 DQ 40 SSTL 1 0 G39 DDR3_DQS_DN 09 SSTL J137 RVD ves ND 117 DDR3_ODT 3 SSTL WER aur 119 DDR3_CS_N 1 SSTL eae NES ae 121 DDR3 DNI 1 SSTL CUP 123 DDR3_CLK_DN O SSTL PRG NER SIR 125 DDR3_CKE 2 SSTL aa es CND 127 55 GND Wee 13 DDR3 005 DP 16 SSTL 1 0 653 vss GND ee Pu G55 1 DN 3 PCIEX3 es SND PET Vs END 35 DDR3 DQ 11 SSTL 1 0 110 tel Processor Land Listing Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 35 of Number Sheet 36 of pos Land Name pes Direction Land Name poe Direction 137 005 DP O1 SSTL 2083 20 DN 05
65. 4 TMS CMOS BR5 PWR BV6 PWR BR53 VSS GND BV8 PWR BR55 VTTD PWR BW1 vss GND 101 Datasheet Processor Land Listing Datasheet intel Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 17 of Number Sheet 18 of Direction pow Land Name 4 Direction BW11 55 GND C37 DDR3 001021 SSTL 1 0 BW13 55 GND C39 vss GND BW15 55 GND 41 vss GND BW17 VSS GND DMI TX 11 PCIEX SENSE C45 DMI TX PCIEX BW43 CMOS 47 DMI DP 0 PCIEX BW5 55 GND C49 DMI 2 PCIEX BW7 55 GND C5 vss GND BW9 DDRO 001281 SSTL 1 0 C51 DP 0 PCIEX3 BY10 DDRO 001241 SSTL C53 RSVD BY12 DDRO 001251 SSTL 1 0 C55 1 65 GND 14 VCCPLL PWR C7 DDR3 DQ 52 SSTL 1 0 16 DDR VREFDQRX CO DC C9 DDR3 001341 SSTL 1 0 CA1 DDRO_DQ 12 SSTL 1 0 BY18 PWR PATI Wee SHE 55 SENSE PADS BUR eee DR 15 VCCPLL PWR Byz CA17 DDRO1 RCOMP O Analog BY24 vss GND WEE CHE BY26 VCC PWR WR BY28 VCC PWR ID PWR BY30 VCC P
66. 4 Direct Media Interface Gen 2 DMI2 PCI Express Link States 32 4 1 5 S and C State Combinations 33 Datasheet 3 intel 4 2 Processor Core Package Power Management 33 4 2 1 Enhanced Intel SpeedStep Technology 33 4 2 2 Low Power Idle 5 cece eee ees 34 4 2 3 Requesting Low Power Idle States 35 4 2 4 5 serons ea CE Ea RE nea LOU e a Dae sib dede 36 4 2 5 Package C States b MU eK taa RR SE 37 4 2 6 Package C State Power 40 4 3 System Memory Power Management 40 4 3 1 CRE PoWer DOWDL s iecore tha ena ERR RR Ea e ER peda HORREA CE 41 4 3 2 Self RefresLi eee re YEN EL 41 4 3 3 DRAM I O Power eese nnne 42 4 4 Direct Media Interface 2 DMI2 PCI Express Power 42 Thermal Management 5 43 Signal Descriptions x tx pdt qute epee anna 44 6 1 System Memory Interface 5 nee 44 6 2 PCI Express Based Interface
67. 4 PWR VCC BA17 PWR VCC AP16 PWR VCC BA3 PWR VCC AP2 PWR VCC BA5 PWR VCC AP4 PWR VCC BA7 PWR VCC AP6 PWR VCC BA9 PWR VCC AP8 PWR VCC BB10 PWR VCC AU1 PWR VCC BB12 PWR VCC AU11 PWR VCC BB14 PWR VCC AU13 PWR VCC BB16 PWR VCC AU15 PWR VCC BB2 PWR VCC AU17 PWR VCC BB4 PWR VCC AU3 PWR VCC BB6 PWR VCC AU5 PWR VCC BB8 PWR VCC AU7 PWR VCC PWR VCC AU9 PWR VCC BE11 PWR VCC AV10 PWR VCC BE13 PWR VCC AV12 PWR VCC BE15 PWR VCC AV14 PWR VCC BE17 PWR VCC AV16 PWR VCC BE3 PWR VCC AV2 PWR VCC BE5 PWR VCC AV4 PWR VCC BE7 PWR VCC AV6 PWR VCC BE9 PWR VCC AV8 PWR VCC BF10 PWR VCC AW1 PWR VCC BF12 PWR VCC AW11 PWR VCC BF14 PWR VCC AW13 PWR VCC BF16 PWR VCC AW15 PWR VCC BF2 PWR VCC AW17 PWR VCC BF4 PWR VCC AW3 PWR VCC BF6 PWR VCC AW5 PWR VCC BF8 PWR VCC AW7 PWR VCC BG1 PWR VCC AW9 PWR VCC BG11 PWR VCC AY10 PWR VCC BG13 PWR VCC AY12 PWR VCC BG15 PWR VCC AY14 PWR VCC BG17 PWR VCC AY16 PWR VCC BG3 PWR VCC AY2 PWR VCC BG5 PWR VCC AY4 PWR VCC BG7 PWR 84 e n tel Processor Land Listing Table 8 1 Land List by Land Name Table 8 1 LandList by Land Name Sheet 25 of 42 Sheet 26 of 42 Land Name rod Direction Land Name pw puis Direction VCC BG9 PWR VCC BR11 PWR VCC BH10 PWR VCC BR13 PWR VCC BH12 PWR VCC BR15 PWR VCC BH14 PWR VCC BR17 PWR VCC BH16 PWR VCC BR3 PWR VCC BH2 PWR VCC BR5 PWR VCC BH4 PWR VCC BR7 PWR VCC BH6
68. 5 GND VSS DB12 GND VSS G37 GND VSS DB2 GND VSS G41 GND VSS DB32 GND VSS G45 GND VSS DB36 GND VSS G47 GND VSS DB58 GND VSS G5 GND VSS DC3 GND VSS G51 GND VSS DC41 GND vss G53 GND vss DC5 GND vss G57 GND 55 0010 GND VSS G9 GND vss DD12 GND vss H10 GND VSS DD14 GND VSS H12 GND lvss 55 H14 GND 55 0036 55 H32 GND Datasheet Processor Land Listing Datasheet intel Table 8 1 Land List by Land Name Table 8 1 Land List by Land Name Sheet 39 of 42 Sheet 40 of 42 Land Name pog Direction Land Name pong ee Direction 55 H34 GND 55 12 GND 55 H38 GND 55 P14 GND VSS H40 GND VSS P26 GND VSS H52 GND VSS P30 GND VSS H54 GND VSS P32 GND VSS H8 GND VSS P38 GND VSS J11 GND VSS P40 GND 55 127 GND 55 P54 GND 55 731 GND 55 P56 GND 55 133 GND 55 P8 GND 55 139 GND 55 R11 GND 55 41 GND 55 R29 GND 55 5 GND 55 R3 GND VSS 155 GND 55 R31 GND VSS K2 GND VSS R35 GND VSS K26 GND VSS R39 GND VSS K28 GND VSS R5 GND VSS K30 GND VSS R55 GND VSS K34 GND VSS R7 GND VSS K8 GND VSS T28 GND 55 125 GND 55 T4 GND 55 129 GND 55 T42 GND 55 141 GND 55 T6 GND 55 15 GND 55 GND 55 M34 GND 55 U35 GND 55 M36 GND 55 U5 GND 55 42 GND 55 v26 GND 55 M44 GND 55 v
69. 7 1 16000 DA 1 33500 FD 1 51000 4F 0 64000 72 0 81500 95 0 99000 B8 1 16500 DB 1 34000 FE 1 51500 50 0 64500 73 0 82000 96 0 99500 B9 1 17000 DC 1 34500 FF 1 52000 51 0 65000 74 0 82500 97 1 00000 BA 1 17500 DD 1 35000 52 0 65500 75 0 83000 98 1 00500 BB 1 18000 DE 1 35500 53 0 66000 76 0 83500 99 1 01000 BC 1 18500 DF 1 36000 54 0 66500 77 0 84000 9A 1 01500 BD 1 19000 1 36500 Notes 1 00h Off State 2 VID Range HEX 01 32 are not used by the processor 3 For VID Ranges supported see Table 7 10 4 Vccp is a fixed voltage of 1 35V or 1 5V 58 Datasheet Electrical Specifications n tel 7 1 9 7 2 Table 7 4 Table 7 5 Datasheet Reserved or Unused Signals Reserved RSVD signals must not be connected Connection of these signals to Vccp 5 or to any other signal including each other can result in component malfunction or incompatibility with future processors See Chapter 8 for a land listing of the processor and the location of all Reserved RSVD signals For reliable operation always connect unused inputs or bi directional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground Vss Unused outputs may be left unconnected however this may interfere with some Test Access Port TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bi dire
70. 70000 7E 0 87500 Al 1 05000 4 1 22500 E7 1 40000 39 0 53000 5C 0 70500 7F 0 88000 A2 1 05500 C5 1 23000 E8 1 40500 3A 0 53500 5D 0 71000 80 0 88500 A3 1 06000 C6 1 23500 E9 1 41000 3B 0 54000 5E 0 71500 81 0 89000 A4 1 06500 C7 1 24000 EA 1 41500 3C 0 54500 5F 0 72000 82 0 89500 A5 1 07000 C8 1 24500 EB 1 42000 3D 0 55000 60 0 72500 83 0 90000 A6 1 07500 C9 1 25000 EC 1 42500 3E 0 55500 61 0 73000 84 0 90500 A7 1 08000 CA 1 25500 ED 1 43000 3F 0 56000 62 0 73500 85 0 91000 A8 1 08500 CB 1 26000 EE 1 43500 40 0 56500 63 0 74000 86 0 91500 A9 1 09000 CC 1 26500 EF 1 44000 41 0 57000 64 0 74500 87 0 92000 AA 1 09500 CD 1 27000 1 44500 42 0 57500 65 0 75000 88 0 92500 1 10000 1 27500 F1 1 45000 43 0 58000 66 0 75500 89 0 93000 AC 1 10500 CF 1 28000 F2 1 45500 44 0 58500 67 0 76000 8A 0 93500 AD 1 11000 DO 1 28500 F3 1 46000 45 0 59000 68 0 76500 8B 0 94000 AE 1 11500 D1 1 29000 4 1 46500 46 0 59500 69 0 77000 8C 0 94500 AF 1 12000 D2 1 29500 F5 1 47000 47 0 60000 6A 0 77500 8D 0 95000 BO 1 12500 D3 1 30000 F6 1 47500 48 0 60500 6B 0 78000 8E 0 95500 B1 1 13000 D4 1 30500 F7 1 48000 49 0 61000 6C 0 78500 8F 0 96000 B2 1 13500 D5 1 31000 F8 1 48500 4A 0 61500 6D 0 79000 90 0 96500 B3 1 14000 D6 1 31500 F9 1 49000 4B 0 62000 6E 0 79500 91 0 97000 B4 1 14500 D7 1 32000 FA 1 49500 4C 0 62500 6F 0 80000 92 0 97500 B5 1 15000 D8 1 32500 FB 1 50000 4D 0 63000 70 0 80500 93 0 98000 B6 1 15500 D9 1 33000 FC 1 50500 4E 0 63500 71 0 81000 94 0 98500 B
71. 8 VSS GND U9 DDR2 DQ 55 SSTL 1 0 T30 DDR2_DQ 23 SSTL 1 0 V10 DDR2 DQ 51 SSTL 1 0 T32 DDR2 005 DN 11 SSTL 1 0 V12 DDR2 DQS DN 15 SSTL T34 DDR2_DQ 20 SSTL 1 0 V14 DDR2 DQ 53 SSTL 1 0 T36 DDR2_DQ 03 SSTL 1 0 V16 23 PWR T38 DDR2 005 DN 00 SSTL 1 0 18 23 PWR T4 VSS GND V20 VCCD 23 PWR 740 DDR2 001001 SSTL 1 0 V22 23 PWR T42 VSS GND 24 VCCD 23 PWR T44 PE3D TX DP 15 PCIEX3 V26 VSS GND T46 PE3C_TX_DN 8 PCI EX3 V28 VSS GND T48 PE3A_TX_DN 3 PCI EX3 DDR2 001221 5511 1 0 T50 PE3B TX DNI 6 PCIEX3 V32 DDR2_DQS_DP 11 SSTL 1 0 T52 PE3B_TX_DN 4 PCIEX3 V34 VSS GND T54 PE2A_RX_DP 1 PCI EX3 6 55 GND T56 2 DP 2 PCIEX3 2 005 DP 00 SSTL 76 VSS GND V4 DDR2 DQ 61 SSTL 8 VSS GND 40 DDR2 001011 5511 1 0 U11 DDR2 DQS DN 06 SSTL 1 0 V42 VSS GND U13 DDR2 001491 SSTL 1 0 V44 vss GND U15 DDR23 Analog 46 VSS GND U17 DDR2 RAS N SSTL V48 vss GND U19 DDR2_MA 02 SSTL V50 55 GND U21 DDR2 MA 05 SSTL 52 PLTEN CMOS 023 DDR2 MA 11 SSTL 54 PE2A RX DN 1 PCIEX3 025 DDR2 MA 15 SSTL v56 PE2A_RX_DN 2 PCI EX3 027 DDR2 CKE 2 SSTL V6 DDR2 DQ 40 SSTL 1 0 U29 DDR2_DQ 19 SSTL 1 0 V8 VSS GND 113 Datasheet Processor Land Listing Datasheet intel
72. A two wire interface through which simple system and SMBus power management related devices can communicate with the rest of the system It is based on the principals of the operation of the 12 two wire serial bus from Philips Semiconductor SSE Intel Streaming SIMD Extensions Intel SSE STD Suspend to Disk STR Suspend to RAM SVID Serial Voltage dentification TAC Thermal Averaging Constant TAP Test Access Port TCC Thermal Control Circuit TDP Thermal Design Power TLP Transaction Layer Packet TSOD Thermal Sensor on DIMM UDIMM Unbuffered Dual In line Module 15 intel Table 1 1 Terminology Sheet 3 of 3 Term Description Uncore The portion of the processor comprising the shared cache I MC HA PCU and UBox Signaling convention that is binary and unidirectional In this binary signaling one bit is sent for every edge of the forwarded clock whether it be a rising edge or a falling Unit I nterval edge If a number of edges are collected at instances t t t then the UI at uen instance n is defined as Ul t t 1 Processor core power supply Mer was Variable power supply for the processor system memory interface Vccp is the generic term for Vccp o1 Vccp 23 VID Voltage Identification VM Virtual Machine VMM Virtual Machine Monitor VPID Virtual Processor 10 VR Voltage Regulator VRD Voltage Regulator Down VR
73. Architectures Software Developer s Manuals Volume 1 Basic Architecture Volume 2A Instruction Set Reference A M Volume 2B Instruction Set Reference N Z Volume 3A System Programming Guide Volume 3B System Programming Guide Intel 64 and 32 Architectures Optimization Reference Manual http www intel com products proce ssor manuals index htm Intel Virtualization Technology Specification for Directed 1 0 Architecture Specification http download intel com technolog y computing vptech Intel r VT for Direct National Institute of Standards and Technology NIST SP800 90 http csrc nist gov publications Pubs SPs html 8 17 intel T 2 1 2 1 1 2 1 2 18 nterfaces This chapter describes the functional behaviors supported by the processor Topics covered include System Memory Interface PCI Express Interface Direct Media Interface 2 DMI2 PCI Express Interface Platform Environment Control Interface PECI System Memory nterface System Memory Technology Support The Integrated Memory Controller supports DDR3 protocols with four independent 64 bit memory channels and supports 1 unbuffered DIMM per channel System Memory Timing Support The IMC supports the following DDR3 Speed Bin CAS Write Latency CWL and command signal mode timings on the main memory interface tCL CAS Latency tRCD Activate Command to READ or WRITE
74. CD22 PWR VCCD 23 N23 PWR VCCD 01 CD24 PWR VCCD 23 V16 PWR VCCD 01 CD26 PWR VCCD 23 v18 PWR VCCD_01 CD28 PWR VCCD 23 v20 PWR VCCD 01 CJ19 PWR VCCD 23 v22 PWR VCCD 01 CJ21 PWR VCCD 23 24 PWR VCCD 01 CJ23 PWR VCCPLL BY14 PWR VCCD_01 CJ25 PWR VCCPLL CA13 PWR VCCD 01 CJ27 PWR VCCPLL CA15 PWR VCCD 01 CP20 PWR VSA AE15 PWR VCCD 01 CP22 PWR VSA AE17 PWR VCCD 01 CP24 PWR VSA AF18 PWR VCCD 01 CP26 PWR VSA 15 PWR VCCD 01 CP28 PWR VSA AG17 PWR VCCD 01 CW19 PWR VSA AH10 PWR VCCD 01 CW21 PWR VSA AH12 PWR VCCD 01 CW23 PWR VSA AH14 PWR VCCD_01 CW25 PWR VSA AH16 PWR VCCD 01 CW27 PWR VSA AH2 PWR VCCD 01 DD18 PWR VSA PWR VCCD 01 DD20 PWR VSA AH6 PWR VCCD 01 DD22 PWR VSA AH8 PWR VCCD 01 DD24 PWR VSA AJ1 PWR VCCD 01 DD26 PWR VSA 11 PWR VCCD 23 AC17 PWR VSA 13 PWR VCCD 23 19 PWR VSA AJ3 PWR VCCD 23 AC21 PWR VSA 5 PWR VCCD 23 AC23 PWR VSA 7 PWR VCCD 23 AC25 PWR VSA AJ9 PWR VCCD 23 C15 PWR VSA B54 PWR VCCD 23 C17 PWR VSA G43 PWR VCCD 23 C19 PWR VSA G49 PWR VCCD_ 23 C21 PWR VSA N45 PWR VCCD 23 C23 PWR VSA N51 PWR VCCD 23 G13 PWR VSA SENSE AG13 VCCD 23 H16 PWR 55 41 GND VCCD 23 H18 PWR 55 A43 GND VCCD 23 H20 PWR 55 45 GND VCCD 23 H22 PWR 55 47 GND VCCD 23 H24 PWR 55 49 GND VCCD 23 N15 PWR 55 5 GND VCCD 23 N17 PWR 55 51 GND 86 e n tel Processor Land Listing Table 8 1 Land List by Land Name Table 8 1 Land List by Land Name
75. CIEX3 2 DN 9 58 1 DN 4 K46 PCIEX3 PE2C RX DP 10 AJ57 PCIEX3 PE1B TX DN 5 147 PCIEX3 PE2C RX DP 11 AR57 PCIEX3 PE1B TX DN 6 K48 PCIEX3 PE2C RX DP 8 AH56 PCIEX3 1 TX DN 7 149 PCIEX3 PE2C RX DP 9 AK58 PCIEX3 1 TX H46 PCIEX3 PE2C TX DN 10 54 PCIEX3 1 TX DP 5 147 PCIEX3 PE2C TX DN 11 BA51 PCIEX3 1 TX DP 6 H48 PCIEX3 PE2C TX DN 8 AY52 PCIEX3 1 TX DP 7 149 PCIEX3 PE2C TX DN 9 BA53 PCIEX3 PE2A_RX_DN 0 N55 PCIEX3 PE2C TX DP 10 AY54 PCIEX3 PE2A DN 1 54 PE2C 111 51 PCIEX3 PE2A DN 2 56 PE2C TX DP 8 AV52 PCIEX3 2 DN 3 W55 PCIEX3 PE2C DP 9 AW53 PCIEX3 2 DP O 155 PCIEX3 PE2D DN 12 AV58 PCIEX3 2 DP 1 T54 PCIEX3 PE2D DN 13 AT56 PCIEX3 DP 2 T56 PCIEX3 PE2D DN 14 BA57 PCIEX3 055 PCIEX3 PE2D DN 15 BB56 PCIEX3 PE2A AR49 PCIEX3 PE2D RX DP 12 AT58 PCIEX3 PE2A TX 1 AP50 PCIEX3 PE2D DP 13 AP56 PCIEX3 PE2A TX 2 51 PCIEX3 PE2D DP 14 AY58 PCIEX3 PE2A TX AP52 PCIEX3 PE2D DP 15 AY56 PCIEX3 PE2A TX DP 0 AN49 PCIEX3 PE2D TX DN 12 AY50 PCIEX3 PE2A TX DP 1 50 PE2D TX DN 13 BA49 PCIEX3 PE2A TX DP 2 51 PCIEX
76. CMOS 1 0 8010 VSS GND BA45 DN CMOS 8012 VSS GND BA47 PE2D TX DN 15 PCIEX3 14 VSS GND BA49 PE2D TX DN 13 PCIEX3 8016 VSS GND 5 vcc PWR BD2 vss GND BA51 2 TX 111 PCIEX3 55 GND BA53 PE2C TX DN 9 PCIEX3 BD42 PWR BA55 5 4 8044 5 BA57 PE2D 41 PCIE BD46 RSVD PWR 048 RSVD BA9 Vcc PWR BD50 ERROR ODCMOS 10 VCC PWR BD52 PROCHOT ODCMOS BB12 VCC PWR BD54 VSS GND 14 VCC PWR BD56 VSS GND BB16 PWR BD6 vss GND BB2 vcc PWR BD8 vss GND PWR PWR 42 VSS GND 11 VCC PWR BB44 BPM_N 4 ODCMOS 1 0 BE13 VCC PWR 46 VSS GND 15 VCC PWR 48 vss GND BE17 vcc PWR BB50 vss GND vcc PWR BB52 vss GND BE43 RSVD BB54 2 TX DN 10 PCIEX3 BE45 RSVD BB56 PE2D DN 15 PCIEX3 47 RSVD 58 vss GND BE49 VSS GND pee PWR Datasheet Processor Land Listing Datasheet intel Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 13 of Number Sheet 14 of roe Land Name rx Direction po Land Name Direction BE51 VSS GND BJ17 VCC PWR vcc PWR BJ3 Vcc PWR BE9 vcc PWR BJA3 RSVD BF10 VCC
77. CN11 GND 55 CV34 GND 55 CN13 GND 55 CV38 GND 55 15 GND 55 42 GND 55 CN17 GND 55 54 GND 55 CN3 GND 55 CV58 GND 55 CN31 GND 55 CV6 GND 55 CN33 GND 55 CW11 GND 55 CN35 GND 55 CW13 GND 55 CN37 GND 55 CW15 GND VSS CN39 GND VSS CW29 GND 55 CN5 GND 55 CW31 GND 55 CN53 GND 55 CW33 GND 90 e n tel Processor Land Listing Table 8 1 Land List by Land Name Table 8 1 LandList by Land Name Sheet 37 of 42 Sheet 38 of 42 Land Name ro Direction Land Name pn pulis Direction vss CW35 GND vss DD38 GND vss CW37 GND VSS DD6 GND VSS CW39 GND VSS DE17 GND 55 CW5 GND VSS DE41 GND vss CW51 GND VSS DE53 GND 55 CW53 GND VSS DE7 GND VSS CW55 GND VSS DF12 GND VSS CW57 GND VSS DF36 GND VSS CW7 GND VSS DF42 GND vss CY10 GND VSS DF44 GND vss CY12 GND VSS DF46 GND vss CY16 GND VSS DF48 GND 55 CY2 GND VSS DF50 GND lvss GND 5 DF52 GND vss 40 GND VSS DF8 GND 55 44 GND VSS 1 GND vss CY50 GND VSS E29 GND vss CY8 GND VSS E3 GND vss D2 GND vss E31 GND vss D26 GND VSS E41 GND VSS D36 GND VSS E5 GND VSS D8 GND VSS F36 GND VSS DA11 GND VSS F42 GND VSS DA3 GND VSS F44 GND VSS DA41 GND VSS F48 GND 55 p 3 55 F50 GND VSS DA45 GND VSS F8 GND VSS DA47 GND VSS G1 GND VSS DA5 GND VSS G25 GND VSS DA51 GND VSS G31 GND VSS DA9 GND VSS G3
78. Command delay e PRECHARGE Command Period CWL CAS Write Latency Command Signal modes 1n indicates a new command may be issued every clock and 2n indicates a new command may be issued every 2 clocks Command launch mode programming depends on the transfer rate and memory configuration Datasheet intel 2 2 PCI Express I nterface This section describes the PCI Express 3 0 interface capabilities of the processor See the PCI Express Base Specification for details of PCI Express 3 0 2 2 1 PCI Express Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged The PCI Express configuration uses standard mechanisms as defined in the PCI Plug and Play specification The PCI Express architecture is specified in three layers Transaction Layer Data Link Layer and Physical Layer The partitioning in the component is not necessarily along these same boundaries Refer to the following figure for the PCI Express Layering Diagram Figure 2 1 Express Layering Diagram Transaction Transaction Data Link Data Link Physical Physical Logical Sub Block Logical Sub Block Electrical Sub Block Electrical Sub Block RX TX RX TX PCI Express uses packets to communicate information between components Packets are formed in the Transaction and Data Link Layers to carry the information from th
79. DDR3 DQ 03 E37 SSTL 1 0 DDR3_DQ 47 M10 SSTL DDR3 DQ 04 F40 SSTL 1 0 DDR3_DQ 48 E7 SSTL 1 0 DDR3 DQ 05 040 SSTL 1 0 DDR3_DQ 49 F6 SSTL DDR3 DQ 06 F38 SSTL 1 0 DDR3 DQ 50 N7 SSTL DDR3 DQ 07 A37 SSTL DDR3 DQ 51 P6 SSTL 1 0 DDR3_DQ 08 N39 SSTL 1 0 DDR3_DQ 52 C7 SSTL DDR3 DQ 09 L39 SSTL 1 0 DDR3 DQ 53 D6 SSTL 1 0 DDR3 DQ 10 L35 SSTL 1 0 DDR3 DQ 54 L7 SSTL DDR3 DQ 11 135 SSTL 1 0 DDR3 DQ 55 M6 SSTL DDR3 DQ 12 M40 SSTL 1 0 DDR3 DQ 56 G3 SSTL DDR3 DQ 13 K40 SSTL 1 0 DDR3 DQ 57 H2 SSTL 1 0 DDR3 DQ 14 K36 SSTL DDR3 DQ 58 N3 SSTL DDR3 DQ 15 H36 SSTL 1 0 DDR3 DQ 59 PA SSTL 1 0 DDR3_DQ 16 A35 SSTL 1 0 DDR3 DQ 60 F4 SSTL 1 0 DDR3 DQ 17 F34 SSTL 1 0 DDR3_DQ 61 H4 SSTL DDR3 001181 032 SSTL 1 0 DDR3_DQ 62 L1 SSTL 1 0 DDR3 DQ 19 F32 SSTL 1 0 DDR3_DQ 63 M2 SSTL DDR3 DQ 20 E35 SSTL 1 0 DDR3 DQS DN OO B38 SSTL 1 0 DDR3_DQ 21 C35 SSTL DDR3 005 DN O1 137 SSTL DDR3 DQ 22 A33 SSTL 1 0 DDR3 DQS DN O2 G33 SSTL DDR3 001231 B32 SSTL 1 0 DDR3_DQS_DN 03 P28 SSTL DDR3 001241 M32 SSTL 1 0 DDR3 DQS DN O4 B10 SSTL 1 0 DDR3 DQ 25 L31 SSTL 1 0 DDR3 DQS DN 05 111 SSTL DDR3 DQ 26 M28 SSTL 1 0 DDR3 DQS DN 06 7 SSTL 1 0 DDR3_DQ 27 L27 SSTL 1 0 DDR3 DQS DN 07 L3 SSTL 1 0 DDR3_DQ 28 L33 SSTL 1 0 DDR3_DQS_DN 08 G27 SSTL 1 0 DDR3_DQ 29 K32 SSTL 1 0 DDR3 DQS DN O9 G39 SSTL DDR3 001301 N27 SSTL 1 0 DDR3 DQS DN 10 K38 SSTL DDR3 001311 26 S
80. DDRO 001371 SSTL 1 0 CD18 55 GND CB32 DDRO DQS DN 13 SSTL 1 0 CD20 01 PWR CB34 DDRO 001391 SSTL 1 0 CD22 01 PWR CB36 55 GND CD24 vCCD 01 PWR CB38 DDRO 001481 SSTL 1 0 CD26 01 PWR DDRO DQ 09 SSTL 1 0 CD28 VCCD_01 PWR CB40 DDRO DQS DN 06 SSTL 1 0 CD30 DDRO DQ 36 SSTL CB42 DDRO 00155 555 CD32 005 551 44 SVIDCLK ODCMOS CD34 SSTL CB46 55 GND CD36 vss GND 48 VSS GND CD38 DDRO DQ 49 SSTL 1 0 CB50 55 GND DDRO_DQS_DN 10 SSTL 1 0 CB52 VSS GND CD40 DDRO DQS 061 SSTL CB54 _ 1 ODCMOS CD42 DDRO DQ 51 SSTL 1 0 CB56 55 GND CD44 RSVD CB6 vss GND vss GND 55 GND CD8 DDRO 01011 SSTL DDRO 005 DN 12 SSTL 1 0 CE11 DDRO DQS DP 03 SSTL 13 VSS GND CE13 VSS GND 17 DDRO 095 DP 08 SSTL 005 DN OS 5511 CC19 DDRO1_RCOMP 1 Analog CE19 DDRO_CKE 5 SSTL CC21 DDRO PAR ERR SSTL CE21 DDRO DN 2 SSTL CC23 DDRO CS N 2 SSTL CE23 DDRO DN 1 SSTL 25 DDRO CS N 7 SSTL CE25 _ 0 SSTL CC27 DDRO 001151 SSTL CE27 DDRO_ODT 1 SSTL CC29 vss GND CE29 DDRO RAS N SSTL CC3 55 GND 0 005 SSTL CC31 DDRO 001331 SSTL 1 0 DDRO DQ 32 SSTL 1 0 CC33 DDRO_DQS_DP 04 SSTL 1 0 CE33
81. DDRO DQS DN 04 SSTL 1 0 CC35 DDRO DQ 35 SSTL 1 0 CE35 DDRO DQ 34 SSTL CC37 DDRO DQ 52 SSTL 1 0 CE37 DDRO DQ 53 SSTL CC39 DDRO 005 DP 15 SSTL 1 0 CE39 DDRO DQS DN 15 SSTL CC41 DDRO 001541 SSTL 1 0 CE41 DDRO_DQ 50 SSTL CC43 vss GND CE43 RSVD 45 PWR CES VSS GND CC47 VSS GND CE7 DDRO_DQS_DP 09 SSTL 1 0 vss ceo vs Teo ccs DDRO DQS DP 10 SSTL sst 103 Datasheet Processor Land Listing Datasheet intel Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 21 of Number Sheet 22 of Fae Land Name aA Direction pow Land Name ny Direction 12 VSS GND CH16 VSS GND 14 vss GND CH20 DDRO 2 SSTL CF16 DDRO DQS DN 17 SSTL 1 0 CH22 DDRO DP 3 SSTL 20 DDRO_CKE 4 SSTL CH24 DDRO DP 0 SSTL 22 DDRO DN 3 SSTL CH26 DDRO_CS_N 1 SSTL CF24 DDRO SSTL CH28 DDRO ODT 2 SSTL CF26 DDRO CS 5 SSTL CH30 DDRO DQ 45 SSTL 1 0 CF28 DDRO ODT 3 SSTL CH32 DDRO DQS DN 14 SSTL 1 0 CF30 vss GND CH34 DDRO 01471 SSTL 1 0 CF32 vss GND CH36 55 GND CF34 VSS GND CH38 DDRO 001561 SSTL 1 0 CF36 VSS GND DDRO D
82. Electrical Specifications 7 1 5 1 7 1 6 7 1 7 7 1 8 7 1 8 1 Table 7 1 54 Clock multiplying within the processor is provided by the internal phase locked loop PLL that requires a constant frequency 0 1 DP BCLK 0 1 DN input with exceptions for spread spectrum clocking DC specifications for the BCLK 0 1 DP BCLK 0 1 _DN inputs are provided in Table 7 15 PLL Power Supply An on die PLL filter solution is implemented on the processor Refer to Table 7 10 for DC specifications Joint Test Action Group J TAG and Test Access Port TAP Signals Due to the voltage levels supported by other components in the JTAG and Test Access Port TAP logic Intel recommends the processor be first in the TAP chain followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Two copies of each signal may be required with each driving a different voltage level Processor Sideband Signals The processor includes asynchronous sideband signals that provide asynchronous input output or I O signals between the processor and the platform or PHC Details are in Table 7 5 All processor asynchronous sideband input signals are required to be asserted de asserted for a defined number of BCLKs for the processor to recognize the proper signal state Power Ground and Sens
83. GND VSS CB16 GND VSS CH36 GND lvss cB x GND 5 CH44 GND lvss cBMe 5 CH46 GND Datasheet Processor Land Listing Datasheet intel Table 8 1 Land List by Land Name Table 8 1 Land List by Land Name Sheet 35 of 42 Sheet 36 of 42 Land Name pg pred Direction Land Name pong Direction 55 GND 55 CN55 GND 55 CH50 GND 55 CN57 GND VSS CH52 GND VSS CN7 GND VSS CH54 GND VSS CN9 GND 55 CH6 GND 55 12 GND 55 CJ11 GND 55 16 GND 55 17 GND 55 6 GND 55 CJ29 GND 55 40 GND 55 GND 55 42 GND 55 CJ43 GND 55 44 GND 55 45 GND 55 CP46 GND VSS 0147 GND 55 48 GND 55 51 GND 55 CP50 GND VSS 9 GND 55 52 GND VSS CK10 GND VSS CP56 GND VSS CK36 GND VSS CR11 GND 55 GND 55 CR35 GND 55 CK6 GND 55 47 GND 55 CL17 GND 55 49 GND 55 CL43 GND VSS CR5 GND VSS CL5 GND VSS CR9 GND 55 10 GND 55 28 GND 55 14 GND 55 42 GND 55 GND 55 CUI GND 55 CM32 GND 55 GND 55 CM34 GND 55 GND 55 CM36 GND 55 CU35 GND 55 CM38 GND 55 CU5 GND 55 40 GND 55 14 GND 55 42 GND 55 CV18 GND 55 CM6 GND 55 GND 55 CM8 GND 55 2 GND 55
84. Intel i7 Processor Family for LGA2011 Socket Datasheet Volume 1 of 2 Supporting Desktop Intel Core i7 4960X Extreme Edition Processor Series for the LGA2011 Socket Supporting Desktop Intel Core i7 49xx and i7 48xx Processor Series for the LGA2011 Socket May 2014 329366 002 By using this document in to any agreements you have with Intel you accept the terms set forth below You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein You agree to grant Intel a non exclusive royalty free license to any patent claim thereafter drafted which includes subject matter disclosed herein INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLI ED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTI ES RELATI NG TO FITNESS FOR A PARTI CULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT A Mission Critical Application is any application in which failure of the Intel Product could result directly or indirectly in personal injur
85. L 1 0 DDR1_CKE 1 CU19 SSTL DDR1 DQ 21 CT6 SSTL 1 0 DDR1_CKE 2 CY18 SSTL DDR1 DQ 22 CW9 SSTL 1 0 DDR1_CKE 3 DA17 SSTL DDR1_DQ 23 CV10 SSTL 1 0 DDR1_CKE 4 CR19 SSTL DDR1 001241 CR13 SSTL 1 0 DDR1_CKE 5 CT18 SSTL DDR1 DQ 25 CU13 SSTL 1 0 DDR1_CLK_DN 0 CV20 SSTL DDR1 001261 CR17 SSTL 1 0 DDR1_CLK_DN 1 CV22 SSTL DDR1 001271 CU17 SSTL 1 0 DDR1_CLK_DN 2 CY24 SSTL DDR1 001281 CT12 SSTL 1 0 DDR1 CLK DN 3 DA21 SSTL DDR1 DQ 29 CV12 SSTL DDR1 DP 0 CY20 SSTL DDR1 0091301 CT16 SSTL 1 0 DDR1_CLK_DP 1 CY22 SSTL DDR1 DQ 31 CV16 SSTL 1 0 DDR1_CLK_DP 2 CV24 SSTL DDR1 001321 CT30 SSTL 1 0 DDR1 CLK DP 3 DC21 SSTL DDR1 0901331 5511 1 0 DDR1_CS_N 0 DB24 SSTL DDR1 DQ 34 CT34 SSTL 1 0 DDR1_CS_N 1 CU23 SSTL DDR1 DQ 35 CP34 SSTL 1 0 DDR1_CS_N 2 CR23 SSTL DDR1 DQ 36 CU29 SSTL 1 0 DDR1_CS_N 3 CR27 SSTL DDR1 0091371 CR29 SSTL 1 0 DDR1_CS_N 4 CU25 SSTL DDR1 001381 CU33 SSTL 1 0 DDR1_CS_N 5 CT24 SSTL DDR1 0091391 CR33 SSTL 1 0 DDR1_CS_N 6 DA29 SSTL DDR1 DQ 40 DA33 SSTL 1 0 DDR1_CS_N 7 CT26 SSTL DDR1 DQ 41 DD32 SSTL 1 0 DDR1_CS_N 8 CR21 SSTL DDR1 DQ 42 DC35 SSTL 1 0 DDR1_CS_N 9 DA27 SSTL DDR1 DQ 43 DA35 SSTL 1 0 DDR1_DQ 00 4 5511 1 0 DDR1 DQ 44 DA31 SSTL 1 0 DDR1_DQ 01 CP2 SSTL 1 0 DDR1 DQ 45 CY32 SSTL 1 0 DDR1_DQ 02 4 5511 1 0 DDR1 DQ 46 DF34 SSTL 1 0 DDR1_DQ 03 cy4 SSTL 1 0 DDR1 DQ 47 DE35 SSTL 1 0 DDR1_DQ 04 CM4 SSTL 1 0 DDR1 DQ 48 CR37
86. LERT N 00 vins 55 Output Edge Rate 50 ohm to 0 20 1 5 V ns 4 Notes Datasheet 69 intel Table 7 19 Processor Asynchronous Sideband Specifications refers to instantaneous Measured at 0 31 Vin between These are measured between and The signal edge rate must be met or the signal must transition monotonically to the asserted state Electrical Specifications Symbol Parameter Min Max Units Notes CMOS1 0v Signals ViL 51 0 Input Low Voltage 0 3 Vir V 51 0 Input High Voltage 0 7 V V Vuysteresis Hysteresis 0 1 V V 51 0 Input Leakage Current 50 200 i Open Drain CMOS ODCMOS Signals Input Low Voltage Signals MEM HOT C01 23 N PROCHOT E Dus Y Input Low Voltage 4 Signals ERR Heg 12 V H ODCMOS Input High Voltage 0 7 V 5 Output Low Voltage 0 2 Vir V 2 Hysteresis Vhysteresis Signals MEM_HOT_C01 23_N PROCHOT_N m But Y da Hysteresis x Vnysteresis Signal ERR Y tie Leak Input Leakage Current 50 200 Buffer Resistance 4 14 Ww 1 2 Output Edge Rate Signal MEM HOT C 01 23 ERROR N 2 0 0 05 0 60 V ns 3 THERMTRIP PROCHOT N Output Edge Ra
87. M Voltage Regulator Module Vss Processor ground x1 Refers to a Link or Port with one Physical Lane x16 Refers to a Link or Port with sixteen Physical Lanes x4 Refers to a Link or Port with four Physical Lanes x8 Refers to a Link or Port with eight Physical Lanes 1 8 Related Documents Refer to the following documents for additional information Table 1 2 Processor Documents Document Number Document E Location Intel Core i7 Processor Family for LGA2011 Socket Datasheet Volume 2 of 329367 2 Intel i7 Processor Families for the LGA2011 0 Socket Thermal 329368 Mechanical Specifications and Design Guide IIntel9 Core i7 Processor Family for LGA2011 Socket Specification Update 326199 16 Datasheet Introduction Table 1 3 Datasheet Public Specifications intel Document Document Number Location Advanced Configuration and Power Interface Specification 3 0 http www acpi info PCI Local Bus Specification 3 0 http www pcisig com specifications PCI Express Base Specification Revision 2 1 and 1 1 PCI Express Base Specification Revision 3 0 http www pcisig com System Management Bus SMBus Specification Revision 2 0 http smbus org DDR3 SDRAM Specification http www jedec org Low J ESD22 A119 and High J ESD A103 Temperature Storage Life Specifications http www jedec org Intel 64 and 32
88. ND CV18 55 GND DDR1_DQ 22 SSTL 1 0 CV2 DDR1_DQ 06 SSTL 1 0 CY10 VSS GND CV20 DDR1 DN 0 SSTL CY12 VSS GND CV22 DDR1 11 SSTL 1 005 DP 17 SSTL CV24 0081 DP 2 SSTL CY16 vss GND CV26 DDR1_ODT 3 SSTL CY18 DDR1 CKE 2 SSTL CV28 DDR1 WE SSTL 2 VSS GND CV30 55 GND CY20 DDR1 DP O0 SSTL 2 55 GND CY22 DDR1 DP 1 SSTL CV34 VSS GND CY24 DDR1 DN 2 SSTL CV36 DDR1 DQ 53 SSTL 1 0 CY26 DDR1 ODT 2 SSTL 8 vss GND CY28 DDR1 ODT 5 SSTL 1 DQ 02 SSTL 1 0 CY30 DDR1_CAS_N SSTL CV40 DDR1 001551 SSTL 1 0 CY32 DDR1_DQ 45 SSTL 1 0 cv42 VSS GND CY34 DDR1 DQS DN 05 SSTL 1 0 cv54 vss GND CY36 vss GND CV58 vss GND CY38 DDR1 005 DN 16 SSTL 55 GND CY4 DDR1 001031 SSTL DDR1_DQS_DN 02 SSTL 1 0 40 55 GND 1 42 DDR SCL 1 ODCMOS 1 0 cw11 VSS GND 44 55 GND CW13 VSS GND 46 RSVD CW15 VSS GND 48 RSVD CW17 DRAM PWR OK CO 51 5 CY50 vss GND M CY56 RSVD CW19 VCCD 01 PWR IBEUD VERRE RT PAR DDR1 001121 SSTL 1 0 CW23 VCCD 01 PWR use SNB Datasheet Processor Land Listing Datasheet intel Table 8 2 Land Li
89. PCIEX3 RSVD AY46 PE3C_RX_DP 9 51 PCIEX3 RSVD B46 PE3C TX DN 10 045 PCIEX3 RSVD BC47 PE3C_TX_DN 11 AB46 PCIEX3 RSVD 8044 TX 81 T46 PCI EX3 RSVD BD46 TX DN 9 47 PCIEX3 RSVD 8048 TX DP 10 R45 PCIEX3 RSVD 4 PE3C TX DP 11 146 PCIEX3 RSVD BE45 PE3C_TX_DP 8 P46 PCIEX3 RSVD 47 DP 9 AAAT PCIEX3 RSVD BF46 PE3D_RX_DN 12 47 PCIEX3 RSVD BG43 PE3D RX DN 13 47 RSVD 8645 0 1141 46 PCIEX3 RSVD BH44 PE3D RX DN 15 AR45 PCIEX3 RSVD BH46 PE3D RX DP 12 47 RSVD BJ43 PE3D RX DP 13 AN47 PCIEX3 RSVD BJ45 DP 14 46 PCIEX3 RSVD BK44 DP 15 45 PCIEX3 RSVD BL43 PE3D_TX_DN 12 AC45 PCIEX3 RSVD BL45 82 tel Processor Land Listing Table 8 1 Land List by Land Name Table 8 1 Land List by Land Name Sheet 21 of 42 Sheet 22 of 42 Land Name r5 Direction Land Name pou Edid Direction RSVD BM44 SVIDDATA BR45 ODCMOS RSVD BM46 TCK BY44 CMOS RSVD BN47 TDI BW43 CMOS RSVD BP44 TDO ODCMOS RSVD BP46 TESTO DB4 RSVD BR43 TEST1 RSVD BR47 TEST2 F2 RSVD BT44 TEST3 D4 RSVD BU43 TEST4 BA55 RSVD 46 BL47 ODCMOS R
90. Q 10 SSTL 1 0 CF38 VSS GND CH40 DDRO 005 DN O7 SSTL 1 0 CFA DDRO_DQS_DP 01 SSTL 1 0 CH42 DDRO DQ 58 SSTL 1 0 40 vss GND 44 55 GND CF42 vss GND CH46 55 GND CF44 RSVD 48 VSS GND CF6 55 GND CH50 VSS GND DDRO DQS DN O9 SSTL CH52 VSS GND 11 RSVD 54 vss GND CG13 DDRO DQ 20 SSTL CH56 ODCMOS 1 0 CG15 vss GND CH6 vss GND CG19 DDRO MA 14 SSTL DDRO_DQS_DP 00 SSTL 1 0 CG21 DDRO DP 2 SSTL 11 VSS GND CG23 DDRO DP 1 SSTL CJ13 DDRO DQS DP 11 SSTL 1 0 CG25 DDRO MA 02 SSTL CJ15 DDRO 001221 SSTL 1 0 CG27 DDRO CS N 4 SSTL 17 55 GND CG29 DDRO MA 13 SSTL CJi9 01 PWR CG3 DDRO DQ 14 SSTL CJ21 01 PWR CG31 55 GND CJ23 VCCD 01 PWR CG33 55 GND CJ25 VCCD 01 PWR CG35 vss GND CJ27 01 PWR CG37 vss GND CJ29 vss GND CG39 vss GND g3 vss GND 41 vss GND CJ31 DDRO_DQ 41 SSTL 1 0 CG43 vss GND CJ33 DDRO DQS DP 05 SSTL 1 0 CG5 DDRO DQ 15 SSTL 035 DDRO 001431 SSTL 1 0 CG53 vss GND CJ37 DDRO 001601 SSTL 1 0 CG55 PWR CJ39 DDRO 005 DP 16 SSTL 1 0 CG7 0 DQS DN OO SSTL 1 0 DDRO DQI 62 SSTL 1 0 CG9 vss GND CJA3 VSS GND CH10 DDRO DQ 30 SSTL 45 VSS GND CH12 VSS GND CJA7 55 GND CH14 DDRO 005 DN O2 SSTL 49 PWR 104 tel Processor Land Listing
91. R consumes the minimum possible power 40 Datasheet intel 4 3 1 4 3 2 4 3 2 1 Datasheet CKE Power Down The CKE input land is used to enter and exit different power down modes The memory controller has a configurable activity timeout for each rank When no reads are present to a given rank for the configured interval the memory controller will transition the rank to power down mode The memory controller transitions the DRAM to power down by de asserting CKE and driving a NOP command The memory controller will tri state all DDR interface lands except CKE de asserted and ODT while in power down The memory controller will transition the DRAM out of power down state by synchronously asserting CKE and driving a NOP command When CKE is off the internal DDR clock is disabled and the DDR power is significantly reduced The DDR defines three levels of power down Active power down This mode is entered if there are open pages when CKE is de asserted this mode the open pages are retained Existing this mode is 3 5 DCLK cycles Pre charge power down fast exit This mode is entered if all banks in DDR are pre charged when de asserting CKE Existing this mode is 3 5 DCLK cycles Difference from the active power down mode is that when waking up all page buffers are empty Pre charge power down slow exit In this mode the data in DLLs on DDR are off Existing this mode is 3 5 DCLK cycles until the firs
92. R3 DN O 123 SSTL DDR2 005 DP 14 Y8 SSTL DDR3 DN 1 121 SSTL DDR2 005 DP 15 112 SSTL 1 0 DDR3_CLK_DN 2 M20 SSTL DDR2 DQS DP 16 5 SSTL 1 0 DDR3_CLK_DN 3 K22 SSTL DDR2 DQS DP 17 29 SSTL DDR3 123 SSTL DDR2 MA PAR M18 SSTL DDR3 DP 1 L21 SSTL DDR2 MA 00 AB18 SSTL DDR3 CLK DP 2 K20 SSTL DDR2_MA 01 R19 SSTL DDR3 CLK DP 3 M22 SSTL DDR2 MA 02 U19 SSTL DDR3 CS G19 SSTL DDR2 MA 03 T20 SSTL DDR3 CS 719 SSTL DDR2 041 P20 SSTL DDR3_CS_N 2 F14 SSTL DDR2 MA 05 U21 SSTL DDR3 CS G15 SSTL DDR2 MA 06 R21 SSTL DDR3 CS N 4 K18 SSTL DDR2 071 P22 SSTL DDR3 CS N 5 G17 SSTL DDR2 081 T22 SSTL DDR3 CS N 6 F16 SSTL DDR2 MA 09 R23 SSTL DDR3_CS_N 7 E15 SSTL DDR2 MA 10 T18 SSTL DDR3 CS NI 8 D16 SSTL DDR2 MA 11 U23 SSTL DDR3 CS N 9 K16 SSTL DDR2 MA 12 T24 SSTL DDR3 DQ 00 B40 SSTL 1 0 DDR2 MA 13 R15 SSTL DDR3 001011 A39 SSTL 1 0 DDR2 MA 14 W25 SSTL DDR3 DQ 02 C37 SSTL 1 0 78 intel Processor Land Listing 79 Table 8 1 Land List by Land Name Table 8 1 Land List by Land Name Sheet 13 of 42 Sheet 14 of 42 Land Name rod Direction Land Name pon puis Direction
93. S AW11 PWR 6 55 GND AW13 PWR 48 5 ENABLE 5 AW15 PWR AT52 VSS GND AW17 PWR 54 2 TX DN 7 PCIEX3 AW3 VCC PWR 56 2 DN 13 PCIEX3 AW43 BPM N 5 ODCMOS 1 0 58 PE2D_RX_DP 12 PCIEX3 AW45 DP CMOS AT6 55 GND AWA47 PE2D TX DP 15 PCIEX3 55 GND AWA49 PE2D TX DP 13 PCIEX3 1 vcc PWR 5 VCC PWR AU11 VCC PWR 51 PE2C TX DP 11 PCIEX3 AU13 VCC PWR AW53 2 TX DP 9 PCIEX3 AU15 VCC PWR 55 VSS GND AU17 VCC PWR 57 VSS GND AU3 PWR AW7 vcc PWR BPM NI2 ODCMOS 1 0 AW9 PWR AU45 55 GND AY10 PWR AU47 55 GND AY12 VCC PWR AUA9 VSS GND 14 VCC PWR AUS vcc PWR AY16 vcc PWR AUS1 vss GND AY2 PWR 53 PWR AYA PWR 55 RSVD 42 PWR 57 PE2C DN 11 PCIEX3 44 N 7 ODCMOS 1 0 AU7 VCC PWR 46 RSVD 09 VCC PWR 48 PE2D TX DN 14 PCIEX3 AV10 PWR 50 PE2D TX DN 12 PCIEX3 AV12 PWR AY52 2 TX DNI8 PCIEX3 14 PWR AY54 2 TX DP 10 PCIEX3 AV16 VCC PWR AY56 2 DP 15 PCIEX3 AV2 VCC PWR AY58 PE2D DP 14 PCIEX3 vcc PWR AY6 PWR 42 vss GND AY8 vcc PWR 44 NI3 ODCMOS 1 0 B10 DDR3_DQS DN O4 SSTL 46 RSVD B12 DDR3 00
94. SSTL K36 141 SSTL 1 0 L9 2608 SSTL 1 0 K38 DDR3 205 DN 10 SSTL M10 DDR3 01471 SSTL DDR3 DNII6 SSTL TS M12 DDR3 20 DN i4 SSTL DDR3 DQ 13 SSTL M14 DDR3 001451 SSTL K42 TX PCIEX3 M16 DDR3 5 SSTL TX DNI 2 PCIEX3 MIS SSTL TX PCIEX3 M2 DDR3 001631 SSTL 1 0 TX DN 6 5 M20 DDR3_CLK_DN 2 SSTL KS0 TX BOIEXS M22 DDR3_CLK_DP 3 SSTL K52 M24 0083 1 SSTL 54 DP 5 PCIEX3 M26 DDR3_DQ 31 SSTL K56 DP 7 PCIEX3 M28 DDR3 09126 SSTL 1 0 RSVD M30 DDR3 DQS DN 12 SSTL DDR3 005 DP 06 SSTL M32 001241 SSTL 70 VSS GND M34 55 GND L1 DDR3 001621 SSTL M36 55 GND 111 Datasheet Processor Land Listing Datasheet intel Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 37 of Number Sheet 38 of poe Land Name 2 Direction po Land Name 4 Direction M38 DDR3_DQS_DP 10 SSTL P18 DDR2 CS N 5 SSTL
95. STL 1 0 DDR3 DQS DN 11 B34 SSTL 1 0 DDR3_DQ 32 D12 SSTL 1 0 DDR3_DQS_DN 12 M30 SSTL DDR3 00133 11 SSTL 1 0 DDR3 DQS DN 13 611 SSTL DDR3 001341 C9 SSTL 1 0 DDR3 DQS DN 14 M12 SSTL DDR3 001351 E9 SSTL 1 0 DDR3_DQS_DN 15 H6 SSTL DDR3 001361 12 SSTL 1 0 DDR3 DQS DN 16 SSTL 1 0 DDR3_DQ 37 B12 SSTL 1 0 DDR3 DQS DN 17 H28 SSTL 1 0 DDR3_DQ 38 F10 SSTL 1 0 DDR3_DQS_DP 00 D38 SSTL 1 0 DDR3_DQ 39 A9 SSTL 1 0 DDR3_DQS_DP 01 J37 SSTL DDR3 DQ 40 J13 SSTL 1 0 DDR3_DQS_DP 02 E33 SSTL 1 0 DDR3 DQ 41 L13 SSTL 1 0 DDR3 DQS DP 03 N29 SSTL 1 0 DDR3 01421 J9 SSTL 1 0 DDR3 DQS DP 04 010 SSTL DDR3 DQ 43 L9 SSTL 1 0 DDR3 DQS DP 05 11 SSTL 1 0 DDR3_DQ 44 K14 SSTL 1 0 DDR3_DQS_DP 06 K6 SSTL 1 0 DDR3 DQ 45 M14 SSTL 1 0 DDR3_DQS_DP 07 M4 SSTL DDR3 DQ 46 K10 SSTL 1 0 DDR3_DQS_DP 08 E27 SSTL 1 0 Datasheet Processor Land Listing Datasheet intel Table 8 1 Land List by Land Name Table 8 1 Land List by Land Name Sheet 15 of 42 Sheet 16 of 42 Land Name pg 2 Direction Land Name pong Direction DDR3 DQs DP O9 9 SSTL 1 0 DMI_TX_DN 1 E43 PCIEX DDR3 005 DP 10 M38 SSTL 1 0 DMI_TX_DN 2 044 PCIEX DDR3 005 1 034 SSTL 1
96. SVD C53 TMS BV44 CMOS RSVD CA45 TRST_N CT54 CMOS RSVD CD44 VCC AG19 PWR ca3 AG25 PWR RSVD CF44 VCC AG27 PWR RSVD CG11 VCC AG29 PWR RSVD CP54 VCC AG31 PWR RSVD CY46 VCC AG33 PWR RSVD 48 VCC AG35 PWR RSVD CY56 VCC AG37 PWR RSVD CY58 VCC AG39 PWR RSVD D46 VCC AG41 PWR RSVD D56 VCC AL1 PWR RSVD DA57 VCC AL11 PWR RSVD DB56 VCC AL13 PWR pcs 115 PWR RSVD 0054 VCC AL17 PWR RSVD DE55 VCC AL3 PWR RSVD E53 VCC AL5 PWR RSVD E57 VCC AL7 PWR RSVD F46 VCC AL9 PWR RSVD F56 VCC AM10 PWR RSVD F58 VCC AM12 PWR RSVD H56 VCC AM14 PWR RSVD H58 VCC AM16 PWR RSVD J15 VCC AM2 PWR RSVD K58 VCC AM4 PWR RSVD M48 VCC AM6 PWR RSVD w15 VCC AM8 PWR RSVD Y48 VCC AN1 PWR SAFE_MODE_BOOT DA55 CMOS VCC AN11 PWR SKTOCC_N BU49 VCC AN13 PWR sVIDALERT N cmos AN15 PWR cB44 AN17 PWR Datasheet Processor Land Listing Datasheet Table 8 1 Land List by Land Name Sheet 23 of 42 Table 8 1 intel Land List by Land Name Sheet 24 of 42 Land Name pg Direction Land Name pog pond Direction VCC AN3 PWR VCC AY6 PWR VCC AN5 PWR VCC AY8 PWR VCC AN7 PWR VCC BA1 PWR VCC AN9 PWR VCC BA11 PWR VCC AP10 PWR VCC BA13 PWR VCC AP12 PWR VCC BA15 PWR VCC AP1
97. The processor does not support LLC flush under any condition Datasheet intel 4 2 4 6 Delayed Deep C States The Delayed Deep C states DDCst feature on this processor replaces the C state auto demotion scheme used in the previous processor generation Deep C states are defined as CC3 through CC7 refer to Table 4 3 for supported deep C states The Delayed Deep C states are intended to allow a staged entry into deeper C states whereby the processor enters a lighter short exit latency C state core C1 for a period of time before committing to a long exit latency deep C state core C3 and core C6 This is intended to allow the processor to get past the cluster of short duration idles providing each of those with a very fast wake up time but to still get the power benefit of the deep C states on the longer idles 4 2 5 Package C States The processor supports CO C1 C1E C2 C6 power states The following is a summary of the general rules for package C state entry These apply to all package C states unless specified otherwise A package C state request is determined by the lowest numerical core C state amongst all cores A package C state is automatically resolved by the processor depending on the core idle power states and the status of the platform components Each core can be at a lower idle power state than the package if the platform does not grant the processor permission to enter a requested pa
98. VSS BP58 GND VSS BD12 GND VSS BR53 GND 88 e n tel Processor Land Listing Table 8 1 Land List by Land Name Table 8 1 LandList by Land Name Sheet 33 of 42 Sheet 34 of 42 Land Name rod Direction Land Name pulis Direction vss BR57 GND vss CB48 GND vss BT46 GND vss CB50 GND vss BT48 GND vss CB52 GND vss BT50 GND vss CB56 GND vss BT52 GND VSS CB6 GND 55 54 GND VSS CB8 GND VSS BT56 GND VSS CC13 GND VSS BU45 GND VSS CC29 GND VSS BU51 GND VSS GND vss BW1 GND vss GND vss BW11 GND vss CC47 GND vss BW13 GND vss 49 GND 55 BW15 GND VSS 9 GND lvss Bwi7 55 CD18 GND vss BW5 GND VSS CD36 GND 55 BW7 GND VSS CD6 GND vss BY24 GND vss CE13 GND vss BY4 GND vss CE5 GND vss BY42 GND vss CE9 GND 55 BY58 GND VSS CF12 GND VSS BY8 GND VSS CF14 GND VSS C11 GND VSS CF30 GND VSS C13 GND VSS CF32 GND VSS C3 GND VSS CF34 GND vss C33 GND vss CF36 GND lvss ex 5 CF38 GND VSS C41 GND VSS CF40 GND VSS 5 GND VSS 42 GND vss C55 GND VSS CF6 GND 55 CA11 GND VSS CG15 GND 55 19 GND VSS CG31 GND VSS CA27 GND VSS CG33 GND vss CA31 GND vss CG35 GND vss CA33 GND vss CG37 GND vss CA35 GND vss CG39 GND vss CA37 GND vss CG41 GND VSS 9 GND VSS CG43 GND vss CA41 GND vss CG53 GND vss CA5 GND vss CG9 GND 55 55 GND VSS CH12 GND vss CA57 GND vss CH16
99. WR UGE PR BY32 VCC PWR PIT Wee SHE BY34 VCC PWR HUE BY36 PWR DDRO_DQ 13 SSTL 1 0 BY38 PWR Wee SHE BYA es SND CA33 55 GND BY40 VCC PWR PASE WE GND BYA2 VSS GND NSS SHE 4 CMOS Wee CHE DAR pave 41 55 GND CA43 TDO ODCMOS BYG DDRO_DQ 04 SSTL PER IRSE BY8 vss GND SE GND CA53 PWR E13 V55 GND CA55 55 GND C15 VCCD 23 PWR Wee CA7 DDRO_DQ 05 SSTL 1 0 914 CA9 DDRO_DQ 29 SSTL 1 0 Eel eee eS PWR CB10 DDRO 005 DP 12 SSTL 1 0 din CB12 DDRO 001261 SSTL 1 0 SH CB16 vss GND wem cnp CB18 DDR_RESET_C01_N 51 5 C35 DDR3 001211 SSTL v 102 tel Processor Land Listing Table 8 2 Land List by Land Table 8 2 Land List by Land Number Sheet 19 of Number Sheet 20 of po Land Name pes Direction Land Name Direction CB2 DDRO DQ 08 SSTL 1 0 CC51 ERR ODCMOS CB20 DDRO1 2 Analog CC7 DQ 00 SSTL 1 0 22 MEM HOT COL ODCMOS 1 0 CC9 vss GND CB24 DDRO_ODT 4 SSTL CD10 DDRO 005 DN 03 SSTL CB26 DDRO CS N 6 SSTL CD12 DDRO_DQ 27 SSTL CB28 DDRO CS SSTL CD16 DDRO DQS DP 17 SSTL CB30
100. XSRD cycles e Issue to each rank The global scheduler will be enabled to issue commands DLL and PLL Shutdown Self refresh according to configuration may be a trigger for master DLL shut down and PLL shut down The master DLL shut down is issued by the memory controller after the DRAMs have entered self refresh The PLL shut down and wake up is issued by the PCU The memory controller gets a signal from the PLL indicating that the memory controller can start working again DRAM 1 Power Management Unused signals are tri stated to save power This includes all signals associated with an unused memory channel The 1 buffer for an unused signal should be tri stated output driver disabled the input receiver differential sense amp should be disabled The input path must be gated to prevent spurious results due to noise on the unused signals typically handled automatically when input receiver is disabled Direct Media nterface 2 DMI2 PCI Express Power Management Active State Power Management ASPM support using L1 state LOs is not supported 55 Datasheet m 9 Thermal Management Specifications n tel 5 Thermal Management Specifications The processor requires a thermal solution to maintain temperatures within operating limits Any attempt to operate the processor outside these limits may result in permanent damage to the processor and potentially other components within the system Maintaini
101. a slow slew rate as defined in the slow slew rate data register The SetVID Slow is 1 4 slower than the SetVID fast slew rate The SetVID slow command is preemptive that is the VR interrupts its current processes and moves to the new VID This is the instruction used for normal P state voltage change This command is used in the processor for the Intel Enhanced SpeedStep Technology transitions SetVI D Decay Command The SetVI D Decay command is the slowest of the DVID transitions It is only used for VID down transitions The VR does not control the slew rate the output voltage declines with the output load current only The SetVI D Decay command is preemptive that is the VR interrupts its current processes and moves to the new VID SVI D Power State Functions SetPS The processor has three power state functions and these states will be set seamlessly with the SVID bus using the SetPS command Based on the power state command the SetPS commands send information to the VR controller to configure the VR to improve efficiency especially at light loads For example typical power states are PS 00h Represents full power or active mode PS 01h Represents a light load 5A to 20A PS 02h Represents a very light load 5A The VR may change its configuration to meet the processor power needs with greater efficiency For example it may reduce the number of active phases transition from CCM Continuous Conduction Mode to DCM
102. age regulator Once the voltage is established the PLL locks on to the target frequency If the target frequency is lower than the current frequency the PLL locks to the target frequency then transitions to a lower voltage by signaling the target voltage on the SVID Bus All active processor cores share the same frequency and voltage In a multi core processor the highest frequency P state requested amongst all active cores is selected Software requested transitions are accepted at any time The processor has a new capability from the previous processor generation it can preempt the previous transition and complete the new request without waiting for this request to complete The processor controls voltage ramp rates internally to ensure glitch free transitions Because there is low transition latency between P states a significant number of transitions per second are possible 33 intel E 4 2 2 Low Power Idle States When the processor is idle low power idle states C states are used to save power More power savings actions are taken for numerically higher C States However higher C states have longer exit and entry latencies Resolution of C states occurs at the thread processor core and processor package level Thread level C states are available if Intel Hyper Threading Technology is enabled Entry and exit of the C states at the thread and core level are shown in Figure 4 2 Figure 4 1 Idle Pow
103. aluable for a wide range of applications The architecture consists of six instructions that offer full hardware support for Intel AES NI Four instructions support the Intel AES NI encryption and decryption and the other two instructions support the Intel AES NI key expansion Together they offer a significant increase in performance compared to pure software implementations The Intel AES NI instructions have the flexibility to support all three standard Intel AES NI key lengths all standard modes of operation and even some nonstandard or future variants Beyond improving performance the Intel AES NI instructions provide important security benefits Since the instructions run in data independent time and do not use lookup tables the instructions help in eliminating the major timing and cache based attacks that threaten table based software implementations of Intel AES NI In addition these instructions make AES simple to implement with reduced code size This helps reducing the risk of inadvertent introduction of security flaws such as difficult to detect side channel leaks Execute Disable Bit The Intel Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks when combined with a supporting operating system Allows the processor to classify areas in memory by where application code can execute and where it cannot When a malicious worm attempts to insert code in the buffer the pr
104. and or data manipulation primitives 28 Datasheet intel e Compatibility Intel AVX is backward compatible with previous ISA extensions including Intel 55 4 Existing Intel SSE applications library can Run unmodified and benefit from processor enhancements Recompile existing Intel SSE intrinsic using compilers that generate Intel AVX code nter operate with library ported to Intel AVX Applications compiled with Intel AVX can inter operate with existing Intel SSE libraries 88 Datasheet 29 intel 4 1 4 1 1 Table 4 1 4 1 2 30 Power Management This chapter provides information on the following power management topics Advanced Configuration and Power Interface ACPI States Supported Processor Core Package Power Management System Memory Power Management Direct Media Interface 2 DMI2 PCI Express Power Management Advanced Configuration and Power Interface ACPI States Supported The ACPI states supported by the processor are described in this section System States System States State Description G0 SO Full On G1 S3 Cold Suspend to RAM STR Context saved to memory G1 S4 Suspend to Disk STD All power lost except wakeup on PCH G2 S5 Soft off All power lost except wakeup on PCH Total reboot G3 Mechanical off All power removed from system Processor Package and Core States The following table lists the
105. baee rente nette m p RF ka rade Ve S i ER ed 54 7 1 7 Processor Sideband 5 8 54 7 1 8 Power Ground and Sense Signals sss emnes 54 7 1 9 Reserved or Unused Signals cece eee 59 7 2 Signal Group Summary er ei beu p Reime ved aere rel bred RED INED 59 7 3 Power On Configuration 5 62 7 4 Absolute Maximum and Minimum 05 62 7 4 1 Storage Conditions 5 63 7 5 SpecifiCatlOnis s ses ILI 64 7 5 1 Voltage and Current 5 111 64 7 5 2 Die Voltage 66 7 5 3 Signal DC Specifications iere 67 Processor Land Listing EUM 72 Package Mechanical mee 115 Boxed Processor 1 4 116 TOL 116 10 2 Boxed Processor 5 116 Datasheet 6 4 6 6 6 7 6 8 6 9 6 10 6 11 6 12 6 13 6 14 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 Datasheet Processor Platform Block Diagram 1 mns 9
106. cations The processor is in a Flip Chip Land Grid Array FCLGA12 package that interfaces with the baseboard using an LGA2011 0 socket The package consists of a processor mounted on a substrate land carrier An integrated heat spreader IHS is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions such as a heatsink Refer to the Processor Thermal Mechanical Specifications and Design Guidelines see Related Documents section for complete details on the LGA2011 0 socket 88 Datasheet 115 m e n te D Boxed Processor Specifications 10 10 1 10 2 116 Boxed Processor Specifications ntroduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels The processors LGA2011 0 are offered as Intel boxed processors however the thermal solutions is sold separately Boxed processors do not include a thermal solution in the box Intel offers boxed thermal solutions separately through the same distribution channels Refer to the Processor Thermal Mechanical Specifications and Design Guidelines see Related Documents section for a description of Boxed Processor thermal solutions Boxed Processor Contents The Boxed processor and Boxed Thermal Solution contents are outlined below Boxed Processor Processor Installation and warranty manual ntel Inside Logo Boxed Thermal
107. cessor This signal is pulled up on the die refer to Table 7 6 for details CAT ERR N Catastrophic Error This signal indicates that the system has experienced a fatal or catastrophic error and cannot continue to operate The processor will assert CAT ERR N for nonrecoverable machine check errors and other internal unrecoverable errors It is expected that every processor in the system will wire OR CAT ERR for all processors Since this is an 1 signal external agents are allowed to assert this signal which will cause the processor to take a machine check exception This signal is sampled after PWRGOOD assertion On the processor CAT ERR N is used for signaling the following types of errors Legacy MCERRs CAT ERR N is asserted for 16 BCLKs Legacy IERRs CAT ERR N remains asserted until warm or cold reset CPU ONLY RESET CPU Only Reset Reserved not used ERROR 2 01 Error These are error status signals for integrated 1 0 unit Error NO Hardware correctable error no operating system or firmware action necessary Error 1 Non fatal error operating system or firmware action required to contain and recover Error 2 Fatal error system reset likely required to recover MEM HOT 01 MEM HOT C23 N Memory Throttle Control HOT 01 MEM HOT C23 signals have two modes of operation input and output mode Input mode is externally asserted and is used to dete
108. cifications RESET must not be kept asserted for more than 100 ms while PWRGOOD is asserted RESET N must be held asserted for at least 3 5 millisecond before it is de asserted again RESET must be held asserted before PWRGOOD is asserted This signal does not have on die termination and must be terminated on the system board 88 71 inte 8 Processor Land Listing This chapter provides the processor land lists Table 8 1 is a listing of all processor lands ordered alphabetically by land name Table 8 2 is a listing of all processor lands ordered by land number 72 Datasheet 73 intel Processor Land Listing Table 8 1 Land List by Land Name Table 8 1 LandList by Land Name Sheet 1 of 42 Sheet 2 of 42 Land Name ro pos Direction Land Name po 3 Direction BCLKO DN CM44 5 DDRO_CLK_DP 1 CG23 SSTL BCLKO DP CN43 CMOS DDRO DP 2 CG21 SSTL BCLK1_DN BA45 CMOS DDRO CLK DP 3 CH22 SSTL DP AW45 CMOS DDRO CS 0 CN25 SSTL BIST ENABLE AT48 CMOS DDRO CS 1 CH26 SSTL opcwos 1 0 DDRO CS N 2 CC23 SSTL NI1 ODCMOS 1 0 DDRO CS N 3 CB28 SSTL BPM 2 AU43 opcwos 1 0 DDRO CS N A CG27 SSTL
109. ckage C state The platform may allow additional power savings to be realized in the processor For package C states the processor is not required to enter CO before entering any other C state The processor exits a package C state when a break event is detected Depending on the type of break event the processor does the following f a core break event is received the target core is activated and the break event message is forwarded to the target core f the break event is not masked the target core enters the core CO state and the processor enters package CO f the break event is masked the processor attempts to re enter its previous package state f the break event was due to a memory access or snoop request But the platform did not request to keep the processor in a higher package C state the package returns to its previous C state And the platform requests a higher power C state the memory access or snoop request is serviced and the package remains in the higher power C state The package C states fall into two categories independent and coordinated CO C1 CIE are independent while C2 C3 C6 are coordinated Starting with the 2nd Generation Intel Core processor family package C states are based on exit latency requirements that are accumulated from the PCle devices PCH and software sources The level of power savings that can be achieved is a function of the exit latency requirem
110. cket Occupied SKTOCC N is used to indicate that a processor is present This SKTOCC N is pulled to ground on the processor package there is no connection to the processor silicon for this signal 5 48 Test High XX signal must be pulled up on the board TESTHI BF48 5 50 Datasheet Signal Descriptions 6 9 Processor Power and Ground Supplies Table 6 14 Power and Ground Signals Datasheet Signal Name Description Variable power supply for the processor cores lowest level caches LLC ring interface and home agent It is provided by a VRM EVRD 12 0 compliant regulator for each processor socket The output voltage of this supply is selected by the VCC processor using the serial voltage ID SVID bus Note Vcc has a Vboot setting of 0 0 V and is not included in the PWRGOOD indication VCC_SENSE and VSS_VCC_SENSE provide an isolated low impedance connection VCC_SENSE to the processor core power and ground These signals must be connected to the VSS_VCC_SENSE VSA_SENSE VSS_VSA_SENSE voltage regulator feedback circuit that insures the output voltage that is processor voltage remains within specification VSA_SENSE and VSS_VSA_SENSE provide an isolated low impedance connection to the processor system agent VSA power plane These signals must be connected to the voltage regulator feedback circuit that insures the output voltage that is processor voltage
111. ct external events such as HOT4 from the memory voltage regulator and causes the processor to throttle the appropriate memory channels Output mode is asserted by the processor known as level mode In level mode the output indicates that a particular branch of memory subsystem is hot MEM 01 is used for memory channels 0 and 1 while MEM HOT C23 is used for memory channels 2 and 3 PMSYNC Power Management Sync A sideband signal to communicate power management status from the Platform Controller Hub PCH to the processor 48 Datasheet Signal Descriptions intel Table 6 12 Processor Asynchronous Sideband Signals Sheet 2 of 3 Datasheet Signal Name Description PROCHOT N Processor Hot PROCHOT N will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit has been activated if enabled This signal can also be driven to the processor to activate the Thermal Control Circuit This signal is sampled after PURGOOD assertion If PROCHOT is asserted at the de assertion of RESET the processor will tri state its outputs PWRGOOD Power Good This is a processor input The processor requires this signal to be a clean indication that BCLK Vro VCccPLL and Vccp 01 23 supplies are stable and within
112. ction for processor specific implementation details for PECI interface operates at a nominal voltage set by The set of DC electrical specifications shown in Table 7 14 is used with devices normally operating from a interface supply Input Device Hysteresis The PECI client and host input buffers must use a Schmitt triggered input design for improved noise immunity Refer to Figure 7 1 and Table 7 14 Input Device Hysteresis Vrv Maximum Ve Mnimum Vg gt Valid Input Signal Range Maximum Mnimum Ground System Reference Clocks BCLK 0 1 DP BCLK 0 1 DN The processor core processor uncore PCI Express and DDR3 memory interface frequencies are generated from BCLK 0 1 DP BCLK1 0 1 DN signals The processor maximum core frequency and DDR memory frequency are set during manufacturing It is possible to override the processor core frequency setting using software This permits operation at lower core frequencies than the factory set maximum core frequency The processor core frequency is configured during reset by using values stored within the device during manufacturing The stored value sets the lowest core multiplier at which the particular processor can operate If higher speeds are desired the appropriate ratio can be configured using the 2 PERF MSR MSR 199h Bits 15 0 53 m n tel
113. ctional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Signal Group Summary Signals are grouped by buffer type and similar characteristics as listed in Table 7 5 The buffer type indicates which signaling technology and specifications apply to the signals Signal Description Buffer Types Signal Description Analog Analog reference or output May be used as a threshold voltage or for buffer compensation Asynchronous Signal has no timing relationship with any system reference clock CMOS CMOS buffers 1 0V or 1 5V tolerant DDR3 DDR3 buffers 1 5V and 1 35V tolerant DMI2 Direct Media Interface Gen 2 signals These signals are compatible with PCI Express 2 0 and 1 0 Signaling Environment AC Specifications Open Drain CMOS Open Drain CMOS ODCMOS buffers 1 0V tolerant PCI Express PCI Express interface signals These signals are compatible with PCI Express 3 0 Signalling Environment AC Specifications and are AC coupled The buffers are not 3 3 V tolerant Refer to the PCI Express specification Reference Voltage reference signal SSTL Source Series Terminated Logic JEDEC SSTL 15 Note 1 Qualifier for a buffer type Signal Groups Sheet 1 of 3 Differential Single En Buffer Type Signals DDR3 Reference Clocks Differential SSTL Output DDR 0 1 2 3 D N P 3 0 DDR3 Command Signals
114. d with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system See the Intel 64 and 1A 32 Architectures Software Developer s Manuals for more detailed information Functional Operation Refers to the normal operating conditions in which all processor specifications including DC AC system bus signal quality mechanical and thermal are satisfied Integrated Heat Spreader A component of the processor package used to enhance IHS the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface The Integrated I O Controller 1 0 controller that is integrated in the processor die IMC The Integrated Memory Controller A Memory Controller that is integrated in the processor die Intel 64 Technology 64 bit memory extensions to the 32 architecture Further details on Intel 64 architecture and programming model can be found at http developer intel com technology intel64 Intel ME Intel9 Management Engine Intel ME Intel Turbo Boost Technology Intel Turbo Boost Technology is a way to automatically run the processor core faster than the marked frequency if the part is operating under power tem
115. down to x2 or x1 When negotiating down to narrower widths there are caveats as to how lane reversal is supported Address Translation Services ATS 1 0 support Hierarchical PCI compliant configuration mechanism for downstream devices Traditional PCI style traffic asynchronous snooped PCI ordering PCI Express extended configuration space The first 256 bytes of configuration space aliases directly to the PCI compatibility configuration space The remaining portion of the fixed 4 KB block of memory mapped space above that starting at 100h is known as extended configuration space PCI Express Enhanced Access Mechanism accessing the device configuration space in a flat memory mapped fashion Automatic discovery negotiation and training of link out of reset Supports receiving and decoding 64 bits of address from PCI Express Memory transactions received from PCI Express that go above the top of physical address space when Intel VT d is enabled the check would be against the translated Host Physical Address HPA are reported as errors by the processor Outbound access to PCI Express will always have address bits 63 46 cleared Re issues Configuration cycles that have been previously completed with the Configuration Retry status Power Management Event PME functions Message Signaled Interrupt MSI and MSI X messages Degraded Mode support and Lane Reversal support Static lane numbering reversal and polarity i
116. e SVID DC Specifications 0 1 69 Processor Asynchronous Sideband DC 70 Miscellaneous Signals DC Hs 70 Land EisE by Land 73 List Land N mbet 94 Datasheet Revision History Revision Number Description Date 001 Initial release September 2013 Chapter 1 Introduction 9 002 Section 1 3 1 System Memory Support corrected DDR3 DRAM technologies May 2014 supported Datasheet 8 intel T Note Note Note Note Note ntroduction The Intel Core i7 processor family for LGA2011 socket are the next generation of 64 bit multi core desktop processors built on 22 nanometer process technology Based the low power high performance Intel Core i7 processor micro architecture the processor is designed for a two chip platform instead of to the traditional three chip platforms processor Memory Controller Hub and Platform Controller Hub The two chip platform consists of a processor and the Platform Controller Hub PCH enabling higher performance easier validation and improved footprint Refer to Figure 1 1 for a platform block diagram The processor features per socket up to 40 lanes
117. e transmitting component to the receiving component As the transmitted packets flow through the other layers the packets are extended with additional information necessary to handle packets at those layers At the receiving side the reverse process occurs and packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally for Transaction Layer Packets to the form that can be processed by the Transaction Layer of the receiving device Datasheet 19 intel Figure 2 2 Packet Flow through the Layers vu T ransaction Layer Data Link Layer Physical Layer 2 2 1 1 Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer The Transaction Layer s primary responsibility is the assembly and disassembly of Transaction Layer Packets TLPs TLPs are used to communicate transactions such as read and write as well as certain types of events The Transaction Layer also manages flow control of TLPs 2 2 1 2 Data Link Layer The middle layer in the PCI Express stack the Data Link Layer serves as an intermediate stage between the Transaction Layer and the Physical Layer Responsibilities of Data Link Layer include link management error detection and error correction The transmission side of the Data Link Layer accepts TLPs assembled by the Transaction Layer calculates and applies data protection code and TLP sequence n
118. e Signals Processors also include various other signals including power ground and sense points Details are in Table 7 5 Power and Ground Lands All VCC VCCPLL VSA VCCD VTTA and VITD lands must be connected to their respective processor power planes while all 55 lands must be connected to the system ground plane For clean on chip power distribution processors include lands for all required voltage supplies The lands are listed in Table 7 1 Power and Ground Lands Sheet 1 of 2 Power and Number of Ground Lands Lands Comments Each VCC land must be supplied with the voltage determined by the Vcc 208 SVID Bus signals Table 7 3 defines the voltage level associated with each core SVID pattern Vcc has a VBOOT setting of 0 0V Each VCCPLL land is connected to a 1 70 V supply to power the Phase VccPLL 3 Lock Loop PLL clock generation circuitry An on die PLL filter solution is implemented within the processor Datasheet m 9 Electrical Specifications n tel Table 7 1 7 1 8 2 7 1 8 3 7 1 8 3 1 Datasheet Power and Ground Lands Sheet 2 of 2 Power and Number of Ground Lands Lands Comments Each VCCD land is connected to a switchable 1 50V and 1 35V supply 01 51 to provide power to the processor DDR3 interface These supplies 23 also power the DDR3 memory subsystem is also controlled by T the SVID Bus VCCD is the generic term for VCCD 01
119. e based on pre silicon characterization 2 Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have different settings 3 These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required 4 The voltage specification requirements are measured across the remote sense pin pairs SENSE and VSS VCC SENSE on the processor package Voltage measurement should be taken with a DC to 100 MHz bandwidth oscilloscope limit or DC to 20 MHz for older model oscilloscopes using a 1 5 pF maximum probe capacitance and 1 minimum impedance The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe 64 Datasheet Electrical Specifications n tel 10 11 12 13 14 15 16 17 18 19 The V a and voltage specification requirements are measured across the remote sense pin pairs VTTD SENSE and VSS SENSE the processor package Voltage measurement should be taken with DC to 100 MHz bandwidth oscilloscope limit or DC to 20MHz for older model oscilloscopes using a 1 5 pF maximum probe capacitance and 1 minimum impedance The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe T
120. e coordinated exit latency requirements are too stringent for the package to take any power saving actions If the exit latency requirements are high enough the package will transition to C3 or C6 state depending on the state of the cores 4 2 5 4 Package C3 State A processor enters the package C3 low power state when At least one core is in the C3 state The other cores are in a C3 or lower power state and the processor has been granted permission by the platform 3 shared cache retains context and becomes inaccessible in this state Additional power savings actions as allowed by the exit latency requirements include putting PCle links in L1 the uncore is not available further voltage reduction can be taken In package C3 state the ring will be off and as a result no accesses to the LLC are possible The content of the LLC is preserved Datasheet 39 intel E 4 2 5 5 Package C6 State A processor enters the package C6 low power state when At least one core is in the C6 state The other cores are in a C6 or lower power state and the processor has been granted permission by the platform 3 shared cache retains context and becomes inaccessible in this state Additional power savings actions as allowed by the exit latency requirements include putting PCle links in L1 the uncore is not available further voltage reduction can be taken In package C6 state all cores have saved their architectura
121. e desired exit latency parameters 4 gt CC3 CC6 will all use a voltage below the VccMin operational point The exact voltage selected will be a function of the snoop and interrupt response time requirements made by the devices PCle and DMI and the operating system Core C State Support Core C State Global Clock PLL L1 L2 Cache Core VCC Context Running On Coherent Active Maintained 1 Stopped On Coherent Active Maintained CCIE Stopped On Coherent Request LFM Maintained Stopped On Flushed to LLC Request Retention Maintained 6 Stopped Off Flushed to LLC Power Gate Flushed to LLC CC7 Stopped Off Flushed to LLC Power Gate Flushed to LLC 31 m e n tel Power Management 4 1 3 ntegrated Memory Controller MC States Table 4 4 System Memory Power States State Description Power Up Normal Operation CKE asserted Active Mode highest power consumption Opportunistic per rank control after idle time Active Power Down APD default mode de asserted Power savings in this mode relative to active idle state is about 5596 of the memory power Exiting this mode takes 3 5 DCLK cycles Pre charge Power Down Fast Exit PPDF de asserted DLL On Also known as Fast Power savings in this mode relative to active idle state is about 6096 of the memory power Exiting this mode takes 3 5 DCLK cycles CKE Power Dow
122. ecification update for details Datasheet intel Figure 1 1 Processor Platform Block Diagram Example 1 1 Processor Feature Details Up to 6 execution cores Each core supports two threads Intel Hyper Threading Technology up to 12 threads per socket 32KB instruction and 32 KB data first level cache L1 for each core 256KB shared instruction data mid level L2 cache for each core Up to 15MB last level cache LLC up to 2 5MB per core instruction data last level cache LLC shared among all cores Datasheet I ntroduction 1 2 Supported Technologies Intel virtualization Technology Intel VT Intel Virtualization Technology Intel VT for Directed 1 0 Intel VT d Intel Virtualization Technology Intel VT Processor Extensions Intel 64 Architecture Intel Streaming SIMD Extensions 4 1 Intel SSE4 1 Intel Streaming SIMD Extensions 4 2 Intel SSE4 2 Intel Advanced Vector Extensions Intel AVX Intel AVX Floating Point Bit Depth Conversion Float 16 Intel Hyper Threading Technology Execute Disable Bit Intel Turbo Boost Technology Enhanced Intel SpeedStep Technology 1 3 Interfaces 1 3 1 System Memory Support 10 Supports four DDR3 channels Unbuffered DDR3 DIMMs supported Independent channel mode or lockstep mode Data burst length of eight cycles for all memory organization modes Memory DDR3 data transfer rates of 1066 MT
123. ed to be the VID value tolerance at processor pins Tolerance for VR at remote sense is 3 390 The 1 2 voltage specification requirements are measured across vias on the platform Choose Vecpo1 Vccp23 vias close to the socket and measure with DC to 100MHz bandwidth oscilloscope limit or DC to 20 MHz for older model oscilloscopes using 1 5 pF maximum probe capacitance and 1M minimum impedance The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe has a Vboot setting of 0 0V and is not included in the PWRGOOD indication has a Vboot setting of 0 9V Table 7 11 Current Specifications Parameter Symbol and Definition Core TDC A Max A Notes lec Core Supply Processor Current on 130W 6 core 4 core 135 165 4 5 I O Termination Supply Processor Current 130W 6 core 4 core 20 24 4 5 Isa System Agent Supply Processor Current on 130W 6 core 4 core 20 24 4 5 Vsa 1 _01 DDR3 Supply Processor Current Vccp 01 130W 6 core 4 core 3 4 4 5 23 DDR3 Supply Processor Current 23 130W 6 4 3 4 4 5 PLL Supply Processor Current on 130W 6 4 2 2 4 5 Iccp 01 23 23 23 DDR3 Supply Current on
124. ent from the platform As a result there is no fixed relationship between the coordinated C state of a package and the power savings that will be obtained from the state Coordinated package C states offer a range of power savings that is a function of the guaranteed exit latency requirement from the platform Datasheet 37 intel m There is also a concept of Execution Allowed EA When EA status is 0 the cores in a Socket are in C3 or a deeper state a socket initiates a request to enter a coordinated package C state The coordination is across all sockets and the PCH Table 4 9 shows an example of a dual core processor package C state resolution Figure 4 3 summarizes package C state transitions with package C2 as the interim between PCO and prior to and PC6 Table 4 9 Coordination of Core Power States at the Package Level Core 1 Package C State C6 CO cii cil Core 0 cii C3 C3 C6 CO cii C3 C6 Note 1 The package C state will be if all actives cores have resolved a core 1 state or higher Figure 4 3 Package C State Entry and Exit 7 b ff m FAN 4 2 5 1 Package CO State The normal operating state for the processor The processor remains in the normal state when at least one of its cores is in the CO or C1 state or when the platform has not granted per
125. equest This signal is used by debug tools to request debug operation of the processor TCK Test Clock This signal provides the clock input for the processor Test Bus also known as the Test Access Port TDI Test Data In This signal transfers serial test data into the processor TDI provides the serial input needed for specification support Test Data Out This signal transfers serial test data out of the processor provides the serial output needed for J TAG specification support 47 intel Signal Descriptions Table 6 10 Joint Test Action Group J TAG and Test Access Port TAP Signals Sheet 2 of 2 Signal Name Description TMS Test Mode Select This signal is a J TAG specification support signal used by debug tools Test Reset This signal resets the Test Access Port TAP logic TRST_N must be TRST_N driven low during power on Reset 6 7 Serial Voltage dentification SVI D Signals Table 6 11 Serial Voltage Identification SVI D Signals Signal Name Description SVIDALERT N Serial VID alert SVIDCLK Serial VI D clock SVIDDATA Serial VI D data out 6 8 Processor Asynchronous Sideband and Miscellaneous Signals Table 6 12 Processor Asynchronous Sideband Signals Sheet 1 of 3 Signal Name Description BIST ENABLE BIST Enable Strap This input allows the platform to enable or disable built in self test BIST on the pro
126. er Management Breakdown of the Processor Cores Thread 0 Thread 1 Thread 0 Thread 1 Core 0 State Core N State Processor Package State Figure 4 2 Thread and Core C State Entry and Exit acy HUT MWATT C7 LVLA Read C1 HU MWAIT C6 MWAIT C3 P_LVL3 Read 4 O V X While individual threads can request low power C states power saving actions only take place once the core C state is resolved Core C states are automatically resolved by the processor For thread and core C states a transition to and from CO is required before entering any other C state 34 Datasheet intel Table 4 7 4 2 3 Note Table 4 8 Note Datasheet Coordination of Thread Power States at the Core Level Thread 1 Processor Core 1 7 cii cii cil Thread 0 cil C3 C3 C3 C6 cii C3 C6 C6 C7 CO cii C3 C6 C7 Note 1 If enabled the core C state will be if all actives cores have also resolved a core C1 state or higher Requesting Low Power Idle States The core C state will be if all actives cores have also resolved a core C1 state higher The primary software interfaces for requesting low power idle states are through the MWAIT instruction with sub s
127. ese signals are programmable by BIOS to one of the pairs 9 COMP resistance must be provided the system board with 1 resistors 1 RCOMP 2 0 and DDR23 RCOMP 2 0 resistors are terminated to Vss 10 Input leakage current is specified for all DDR3 signals 11 DRAM PWR 01 23 must have a maximum of 30 ns rise or fall time over 0 55 300mV and 200mV and the edge must be monotonic 12 The 1 23 RCOMP error tolerance is 15 from the compensated value 13 DRAM C 01 23 Data Scrambling must be enabled for production environments Disabling Data scrambling be used for debug and testing purposes only Running systems with Data Scrambling off will make the configuration out of specification For details refer to the processor Datasheet Volume 2 of 2 see Related Documents section Table 7 14 PECI DC Specifications Symbol Definition and Conditions Min Max Units Figure Notes Vin Input Voltage Range 0 150 Vir V Vuysteresis Hysteresis 0 100 V V VN Negative edge threshold voltage 0 275 V 0 500 V 7 1 2 Vp Positive edge threshold voltage 0 550 V 0 725 V 7 1 2 High level output source SOURCE 6 0 mA B m 0 75 M ve impedance state leakage to 50 200 3 OL Ron Buffer On Resistance 20 36 Q Bus capacitance per node N A 10
128. essor System M Core Description State S State State Clocks C State GO 50 Full On On Full On GO 50 C1 C1E Auto Halt On Auto Halt GO 50 Deep Sleep On Deep Sleep Deep Power Deep Power Down GO 50 6 7 Down On G1 53 Power off Off except RTC Suspend to RAM G1 S4 Power off Off except RTC Suspend to Disk G2 S5 Power off Off except RTC Soft Off G3 N A Power off Power off Hard off Processor Core Package Power Management While executing code Enhanced Intel SpeedStep Technology optimizes the processor frequency and core voltage based on workload Each frequency and voltage operating point is defined by ACPI as a P State When the processor is not executing code it is idle A low power idle state is defined by ACPI as a C state In general lower power States have longer entry and exit latencies Enhanced Intel SpeedStep Technology The following are the key features of Enhanced Intel SpeedStep Technology Multiple frequency and voltage points for optimal performance and power efficiency These operating points are known as P States Frequency selection is software controlled by writing to processor MSRs The voltage is optimized based on temperature leakage power delivery loadline and dynamic capacitance f the target frequency is higher than the current frequency Vcc is ramped up to an optimized voltage This voltage is signaled by the SVID Bus to the volt
129. functionality NEBS Network Equipment Building System NEBS is the most common set of environmental design guidelines applied to telecommunications equipment in the United States Platform Controller Hub The next generation chipset with centralized platform PCH capabilities including the main 1 interfaces along with display connectivity audio features power management manageability security and storage features PCI Express PCI Express Generation 2 0 3 0 PCI Express 2 PCI Express Generation 2 0 PCI Express 3 PCI Express Generation 3 0 PCU Power Control Unit PECI Platform Environment Control Interface PLE Pause Loop Exiting Processor The 64 bit single core or multi core component package Processor Core The term processor core refers to silicon die itself that can contain multiple execution cores Each execution core has an instruction cache data cache and 256 KB L2 cache All execution cores share the cache DC and AC timing and signal integrity specifications are measured at the processor die pads unless otherwise noted QoS Quality of Service Rank A unit of DRAM corresponding four to eight devices in parallel These devices are usually but not always mounted on a single side of a DDR3 DIMM System Control Interrupt Used in Advanced Configuration and Power Interface SCI ACPI protocol System Management Bus
130. he Vs voltage specification requirements are measured across the remote sense pin pairs 5 SENSE and VSS VSA SENSE on the processor package Voltage measurement should be taken with a DC to 100 MHz bandwidth oscilloscope limit or DC to 20 MHz for older model oscilloscopes using a 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe The processor should not be subjected to any static Vcc level that exceeds the associated with any particular current Failure to adhere to this specification can shorten processor lifetime Minimum Vcc and maximum are specified at the maximum processor case temperature TcAsg Icc max is specified at the relative Vcc point on the Vcc load line The processor is capable of drawing for up to 5 seconds The processor should not be subjected to any static level that exceeds the max associated with any particular current Failure to adhere to this specification can shorten processor lifetime This specification represents the Vcc reduction or Vcc increase due to each VID transition see Section 7 1 8 3 Baseboard bandwidth is limited to 20 MHz N A DC AC Ripple Total Tolerance For Power State Functions see Section 7 1 8 3 5 Vsa vip does not have a loadline the output voltage is expect
131. hile the assertion of the RESET N signal may de assert THERMTRIP N if the processor s junction temperature remains at or above the trip level THERMTRIP will again be asserted after RESET N is de asserted This signal can also be asserted if the system memory interface has exceeded a critical temperature limit set by BIOS This signal is sampled after PWRGOOD assertion 49 intel Table 6 12 Table 6 13 50 Signal Descriptions Processor Asynchronous Sideband Signals Sheet 3 of 3 Signal Name Description Intel Trusted Execution Technology Intel TXT Agent This is a strap signal 0 Default The socket is not the Intel TXT Agent 1 The socket is the Intel TXT Agent TXT AGENT In non Scalable dual processor DP platforms the legacy socket identified by SOCKET ID 1 0 00b with Intel TXT Agent should always set the TXT AGENT to 1b On Scalable DP platforms the TXT AGENT is at the Node Controller This signal is pulled down on the die refer to Table 7 6 for details Intel Trusted Execution Technology Intel TXT Platform Enable This is a strap signal 0 The platform is not Intel TXT enabled sockets should be set to zero Scalable DP sDP platforms should choose this setting if the Node Controller TXT PLTEN does not support Intel TXT 1 Default The platform is Intel TXT enabled sockets should be set to one In a non Scalable DP platform this is the default When t
132. his is set Intel TXT functionality requires the user to explicitly enable Intel TXT using BIOS setup This signal is pulled up on the die refer to Table 7 6 for details Miscellaneous Signals Signal Name Description BCLK SELECT 1 0 BCLK Select These configuration straps are used to inform the processor that a non standard value for BCLK will be applied at reset A 11 encoding on these inputs informs the processor to run at DEFAULT BCLK 100 MHz These signals have internal pull up to The encoding is as follows BCLK SELECT1 BCLK SELECTO BCLK Selected X X 100 MHz default 1 1 100 MHz 1 0 125 MHz 0 1 Reserved 0 0 Reserved CORE VREF CAP A capacitor must be connected from this land CORE RBIAS This input is used to control bias currents CORE RBIAS SENSE This signal provides dedicated bias resistor sensing to minimize the voltage drop caused by packaging and platform effects Processor Selected This output can be used by the platform to determine if the installed processor is an Intel Core i7 processor family for LGA2011 socket or a PROC SEL N future processor There is no connection to the processor silicon for this signal This signal is also used by the and Vy rails to switch their output voltage to support future processors RSVD RESERVED signals that are RSVD must be left unconnected on the board Refer to Section 7 1 9 for details So
133. ie oen 13 1 4 4 PCI EXDEGSS bins end tac A RO aol SU 13 1 5 Thermal Management 2 02 21 1 see enemies senis 13 1 6 Package SUMMAN tese turgida ta resa ta pine Dads 14 1 7 Termlihology c eode 14 1 Related Doc mxents denke repu ma dx perte 16 2 5 EM 18 2 1 System Memory Interface 18 2 1 1 System Memory Technology 5 18 2 1 2 System Memory Timing cece nemen 18 2 2 PCI Express 25245225 eee reser be cepa bad bia Fer b 19 2 2 1 Express Architect re isi e oen CR 19 2 2 2 gt Express Configuration 2 20 2 3 Direct Media Interface 2 DMI2 PCI Express Interface 21 24351 Ades EE 21 2 3 2 Processor PCH Compatibility 21 23 32 LINK ee Derek E 21 2 4 Platform Environment Control Interface 21 3 Technologies 23 PEU 23 3 1 Intel Virtualization Technology Intel eec c e ea a 23 3 1 1 Intel
134. ith all operating systems Please check with your application vendor Intel Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability Intel Turbo Boost Technology performance varies depending on hardware software and overall system configuration Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology For more information see http www intel com technology turboboost 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 architecture Performance will vary depending on your hardware and software configurations Consult with your system vendor for more information A Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor96 5Fnumber for details 12 is a two wire communications bus protocol developed by Philips SMBus is a subset of the 12 bus protocol and was developed by Intel Implementations of the 12 bus protocol may require licenses from various entities including Philips Electronics N V and North American Philips Corporation Intel Intel Enhanced Intel SpeedStep Technology Intel 64 Technology Intel Virtualization Technology Intel VT Intel VT d Intel Turbo Boos
135. ith multiple virtual processors PLE attempts to detect lock holder preemption in a VM and helps the VMM to make better scheduling decisions 3 1 3 I ntel VT d Objectives The key Intel VT d objectives are domain based isolation and hardware based virtualization A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated Virtualization allows for the creation of one or more partitions on a single system This could be multiple partitions in the same operating system or there can be multiple operating system instances running on the same system offering benefits such as system consolidation legacy migration activity partitioning or security 24 Datasheet intel 3 1 3 1 Intel VT d Features Supported The processor supports the following Intel VT d features Root entry context entry and default context Support for 4 K page sizes only Support for register based fault recording only for single entry only and support for MSI interrupts for faults Support for fault collapsing based on Requester ID Support for both leaf and non leaf caching Support for boot protection of default page table Support for non caching of invalid page table entries Support for hardware based flushing of translated but pending writes and pending reads upon invalidation Support for page selective I OTLB invalidation Support for ARI Alte
136. ive Data Input 1 _ DN 7 4 DP 7 4 Receive Data Input TX DN 3 0 TX DP 3 0 Transmit Data Output TX DN 7 4 TX DP 7 4 PCIe Transmit Data Output PCI Express Port 2 Signals Sheet 1 of 2 Signal Name Description PE2A DN 3 0 PE2A RX DP 3 0 PCI e Receive Data PE2B RX DN 7 4 PE2B RX DP 7 4 PCI e Receive Data Input PE2C RX DN 11 8 PE2C RX DP 11 8 PCI e Receive Data Input PE2D RX DN 15 12 PE2D DP 15 12 PCle Receive Data Input PE2A TX DN 3 0 PE2A TX DP 3 0 PCI e Transmit Data Output PE2B TX DN 7 4 PE2B TX DP 7 4 PCI e Transmit Data Output 45 intel Table 6 4 Signal Descriptions PCI Express Port 2 Signals Sheet 2 of 2 Signal Name Description PE2C TX DN 11 8 PE2C TX DP 11 8 PCIe Transmit Data Output PE2D TX DN 15 12 PE2D TX DP 15 12 PCIe Transmit Data Output Table 6 5 PCI Express Port 3 Signals Signal Name Description Table 6 6 DN 3 0 DP 3 0 PCI Receive Data Input DN 7 4 PE3B RX DP 7 4 PCI e Receive Data Input PE3C RX DN 11 8 DP 11 8 PCI e Receive Data PE3D RX DN 15 12 PE3D RX DP 15 12 PCI e Receive Data Input PE3A TX DN 3 0 PE3A TX DP 3 0 PCIe
137. l Table 8 1 Land List by Land Name Table 8 1 Land List by Land Name Sheet 31 of 42 Sheet 32 of 42 Land Name po ped Direction Land Name pong pod Direction 55 12 GND 55 8014 GND 55 AT14 GND VSS BD16 GND VSS AT16 GND VSS BD2 GND VSS AT2 GND VSS BD4 GND VSS AT4 GND VSS BD54 GND VSS AT46 GND VSS BD56 GND VSS AT52 GND VSS BD6 GND VSS AT6 GND VSS BD8 GND VSS GND 55 4 GND 55 AU45 GND VSS BE51 GND VSS 7 GND 55 BF42 GND VSS AU49 GND VSS BF44 GND VSS AU51 GND VSS BG47 GND VSS AV42 GND VSS BH58 GND VSS AV54 GND VSS BJ55 GND 55 AV56 GND 55 BJ57 GND 55 AW55 GND 55 BK42 GND 55 AW57 GND 55 BK46 GND VSS B36 GND VSS BK48 GND VSS B52 GND VSS BK50 GND VSS B6 GND VSS BK52 GND VSS B8 GND VSS BK54 GND VSS BB42 GND VSS BL1 GND VSS BB46 GND VSS BL11 GND VSS BB48 GND VSS BL13 GND VSS BB50 GND 55 BL15 GND 55 BB52 GND 55 BL17 GND 55 BB58 GND 55 BL3 GND 55 GND 55 BL49 GND VSS 11 GND 55 BL5 GND 55 BC13 GND 55 BL7 GND 55 BC15 GND VSS BL9 GND 55 BC17 GND 55 10 GND 55 BC3 GND 55 12 GND 55 BC43 GND VSS BM14 GND VSS BC45 GND VSS BM16 GND VSS BC5 GND VSS BM2 GND VSS BC53 GND VSS BM4 GND VSS BC55 GND VSS BM6 GND 55 BC57 GND 55 GND 55 BC7 GND 55 BN43 GND 55 BC9 GND 55 BN45 GND VSS BD10 GND
138. l state and have had their core voltages reduced to zero volts The LLC retains context but no accesses can be made to the LLC in this state the cores must break out to the internal state package C2 for snoops to occur 4 2 6 Package C State Power Specifications The following table lists the processor package C state power specifications for various processor SKUs The C state power specification is based on post silicon validation results The processor case temperature is assumed at 50 C for all C states Most of the idle power is attributed to the significant increase in higher speed 1 0 interfaces for the processor PCle DDR3 Table 4 10 Package C State Power Specifications TDP SKUs W C3 w c6 W 6 Core 130W 6 core 53 28 13 4 Core 130W 4 core 53 28 13 Notes 1 SKUs are subject to change Contact your Intel Field Representative to obtain the latest SKU information 2 Package CIE power specified at Tease 60 3 Package C3 C6 power specified at Tease 50 C 4 3 System Memory Power Management The DDR3 power states can be summarized as the following Normal operation highest power consumption CKE Power Down Opportunistic per rank control after idle time There may be different levels Active Power Down Pre charge Power Down with Fast Exit Pre charge power Down with Slow Exit Self Refresh In this mode no transaction is executed The DD
139. lectro Static Discharge ESD precautions should always be taken to avoid high static voltages or electric fields Datasheet 9 Electrical Specifications tel Table 7 8 7 4 1 Table 7 9 Datasheet Processor Absolute Minimum and Maximum Ratings Symbol Parameter Min Max Unit Notes Vcc Processar core voltage with respect to 0 3 14 55 2 PLL voltage with respect to 0 3 2 0 V SS Processor I O supply voltage DDR3 standard voltage with respect to Vss 0 3 1 85 Processor I O supply voltage for DDR3L _ low Voltage with respect to Vss 0 3 1 7 Processor SA voltage with respect to Vss 0 3 1 4 V Processor analog I O voltage with Vitp respect to Vss 0 3 1 4 Notes 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor Storage Conditions Specifications Environmental storage condition limits define the temperature and relative humidity limits to which the device is exposed to while being stored in a Moisture Barrier Bag The specified storage conditions are for component level prior to board attach see notes in Table 7 9 for post board attach limits Table 7 9 specifies absolute maximum and minimum storage temperature limit
140. load changes to minimize the power and to maximize the performance of the part The specifications are set so that a voltage regulator can operate with all supported frequencies Individual processor VID values may be calibrated during manufacturing such that two processor units with the same core frequency may have different default VID settings The processor uses voltage identification signals to support automatic selection of Vcc and Vccp power supply voltages If the processor socket is empty 5 high or a not supported response is received from the SVID bus the voltage regulation circuit cannot supply the voltage that is requested the voltage regulator must disable itself or not power on The Vout MAX register 30h is programmed by the processor to set the maximum supported VID code and if the programmed VID code is higher than the VID supported by the VR the VR will respond with a not supported acknowledgement Serial Voltage dentification SVID Commands The processor provides the ability to operate while transitioning to a new VID setting and its associated processor voltage rails Vcc and This is represented by a DC shift It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target voltage Transitions above the maximum specified VID are not supported The processor supports the following VR commands
141. me Table 8 1 Land List by Land Name Sheet 11 of 42 Sheet 12 of 42 Land Name pg 2 Direction Land Name pong pod Direction DDR2 DQS DN 08 AB28 SSTL DDR2 151 025 SSTL DDR2 005 DN 09 SSTL 1 0 DDR2_ODT 0 Y20 SSTL DDR2 005 DN 10 AC39 SSTL DDR2 ODI 1 W19 SSTL DDR2_DQS_DN 11 T32 SSTL 1 0 DDR2_ODT 2 AD18 SSTL DDR2 005 DN 12 AB34 SSTL DDR2 0017131 Y18 SSTL DDR2 005 DN 13 012 SSTL 1 0 DDR2_ODT 4 AD22 SSTL 0082 005 DN 14 SSTL 1 0 DDR2 ODT 5 AE21 SSTL DDR2 005 DN 15 v12 SSTL 1 0 DDR2_PAR_ERR_N AD20 SSTL DDR2 005 DN 16 AD4 SSTL DDR2 RAS N U17 SSTL DDR2 005 DN 17 AD28 SSTL DDR2 WE N P16 SSTL DDR2 005 DP 00 38 SSTL DDR23 RCOMP O0 U15 Analog DDR2 005 011 AB38 SSTL 1 0 DDR23_RCOMP 1 15 Analog DDR2 005 DP 02 031 SSTL DDR23 RCOMP 2 14 Analog DDR2 005 DP 03 SSTL 1 0 DDR3_BA 0 A17 SSTL DDR2 DQS DP 04 11 SSTL 1 0 DDR3_BA 1 E19 SSTL DDR2 DQS DP 05 SSTL 1 0 DDR3_BA 2 B24 SSTL DDR2 DQS DP 06 W11 SSTL DDR3 CAS N Bl4 SSTL DDR2 DQS DP 07 SSTL DDR3 CKE 0 K24 SSTL DDR2 DQS DP 08 27 SSTL 1 0 DDR3_CKE 1 M24 SSTL DDR2 DQS DP 09 039 SSTL DDR3 CKE 2 125 SSTL DDR2 DQS DP 10 AB40 SSTL DDR3 CKE 3 N25 SSTL DDR2 DQS DP 11 v32 SSTL DDR3 CKE 4 R25 SSTL DDR2 005 DP 12 Y34 SSTL 1 0 DDR3_CKE 5 R27 SSTL DDR2 DQS DP 13 12 SSTL DD
142. mission to the processor to go into a low power state Individual cores may be in lower power idle states while the package is in CO state 38 Datasheet intel 4 2 5 2 Package C1 CIE State No additional power reduction actions are taken in the package C1 state However if the substate is enabled the processor automatically transitions to the lowest supported core clock frequency followed by a reduction in voltage Autonomous power reduction actions that are based on idle timers can trigger depending on the activity in the system The package enters the C1 low power state when At least one core is in the C1 state The other cores are in a C1 or lower power state The package enters the state when All cores have directly requested using MWAIT C1 with sub state hint All cores are in a power state lower that 1 but the package low power state is limited to C1 C1E using the PMG CST CONFIG CONTROL MSR cores have requested using HLT MWAIT C1 and auto promotion is enabled in POWER CTL No notification to the system occurs upon entry to 1 1 4 2 5 3 Package C2 State Package C2 state is an intermediate state which represents the point at which the system level coordination is in progress The package cannot reach this state unless all cores are in at least C3 The package will remain in C2 when itis awaiting for a coordinated response th
143. n Pre charge Power Down Slow Exit PPDS de asserted DLL Off Also known as Slow CKE Power savings in this mode relative to active idle state is about 8796 of the memory power Exiting this mode takes 3 5 DCLK cycles until the first command is allowed and 16 cycles until first data is allowed Register CKE Power Down BT ON mode Both CKEs are de asserted the Input Buffer Terminators 5 are left on BT OFF mode Both CKEs are de asserted the Input Buffer Terminators IBTs are turned off CKE de asserted In this mode no transactions are executed and the system memory consumes the minimum possible power Self refresh modes apply to all memory channels for the processor O MDLL Off Option that sets the IO master DLL off when self refresh occurs PLL Off Option that sets the PLL off when self refresh occurs Self Refresh 4 1 4 Direct Media I nterface Gen 2 DMI2 PCI Express Link States Table 4 5 2 PCI Express Link States State Description LO Full on Active transfer state L1 Lowest Active State Power Management ASPM Longer exit latency Note 11 is only supported when the DMI2 PCI Express port is operating as a PCI Express port 32 Datasheet intel 4 1 5 Table 4 6 4 2 4 2 1 Datasheet G S and C State Combinations G S and C State Combinations Global G Sleep Processor Proc
144. nd List by Land Name Sheet 19 of 42 Sheet 20 of 42 Land Name pg ped Direction Land Name pong 5 Direction TX DP 1 51 PCIEX3 PE3D TX DN 13 44 PCIEX3 PE3A_TX_DP 2 R47 PCIEX3 PE3D TX DN 14 AA43 PCIEX3 PE3A_TX_DP 3 P48 PCIEX3 PE3D TX DN 15 PCIEX3 PE3B 4 AB50 PCIEX3 PE3D TX DP 12 45 PCIEX3 DN 5 52 PCIEX3 TX DP 13 44 PE3B RX DN 6 AC53 PCIEX3 PE3D TX DP 14 PCIEX3 PE3B_RX_DN 7 AC51 PCIEX3 PE3D TX DP 15 744 PCIEX3 PE3B_RX_DP 4 Y50 PCIEX3 BJ47 PECI 1 0 PE3B_RX_DP 5 Y52 PCIEX3 PEHPSCL 48 ODCMOS 1 0 PE3B_RX_DP 6 AA53 PCIEX3 PEHPSDA BF48 ODCMOS DP 7 51 PCIEX3 PMSYNC K52 CMOS TX 4 T52 PCI EX3 PRDY R53 CMOS PE3B TX DN 5 U51 PCIEX3 _ 053 5 1 0 PE3B TX DN 6 T50 PCIEX3 _ 8052 ODCMOS 1 0 PE3B_TX_DN 7 049 PCIEX3 PWRGOOD BJ53 CMOS TX 4 P52 PCIEX3 RESET N CK44 CMOS TX DP 5 R51 PCIEX3 RSVD A53 TX DP 6 P50 PCIEX3 RSVD AB48 PE3B_TX_DP 7 R49 PCIEX3 RSVD AJ55 DN 10 AH50 PCIEX3 RSVD AL55 PE3C_RX_DN 11 49 PCIEX3 RSVD 44 DNI 8 AH48 PCIEX3 RSVD AP48 PE3C_RX_DN 9 AJ51 PCIEX3 RSVD 55 PE3C RX DP 10 AF50 PCIEX3 RSVD 55 DP 11 49 PCIEX3 RSVD 46 DP 8 AF48
145. ng the proper thermal environment is key to reliable long term system operation A complete solution includes both component and system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader IHS Typical system level thermal solutions may consist of system fans combined with ducting and venting This section provides data necessary for developing a complete thermal solution For more information on designing a component level thermal solution refer to the Processor Thermal Mechanical Specifications and Design Guidelines see Related Documents section 88 Datasheet 43 6 6 1 Table 6 1 44 intel Signal Descriptions Signal Descriptions This chapter describes the processor signals The signals are arranged in functional groups according to their associated interface or category System Memory nterface Signals Memory Channel DDRO DDR1 DDR2 DDR3 Signal Name Description DDR 0 1 2 3 _BA 2 0 Bank Address These signals define the bank which is the destination for the current Activate Read Write or PRECHARGE command DDR 0 1 2 3 _CAS_N Column Address Strobe DDR 0 1 2 3 _CKE 5 0 Clock Enable DDR 0 1 2 3 _CLK_DN 3 0 DDR 0 1 2 3 _CLK_DP 3 0 Differential Clocks to the DI MM All command and control signals are valid on the rising edge of clock DDR 0 1 2 3 CS N 9 0
146. nnected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation refer to the processor case temperature specifications in the appropriate processor Thermal Mechanical Specifications and Design Guide see Related Documents section 63 7 95 1 These ratings apply to the Intel component and do not include the tray or packaging Failure to adhere to this specification can affect the long term reliability of the processor Non operating storage limits post board attach Storage condition limits for the component once attached Electrical Specifications to the application board are not specified Intel does not conduct component level certification assessments post board attach given the multitude of attach methods socket types and board types used by customers Provided as general guidance only Intel board products are specified and certified to meet the following temperature and humidity limits Non Operating Temperature Limit 40 to 70 and Humidity 50 to 9096 non condensing with a maximum wet bulb of 28 C 5 Device storage temperature qualification methods follow JEDEC High and Low Temperature Storage Life Standards JESD22 A119 low temperature and ESD22 A103 high temperature DC Specifications DC specifications are defined at the processor pads unless otherwise noted DC specifications are only valid while meeting specification
147. ns 4 bit addressing code Serial Voltage dentification SVI D Address Usage PWM Address Hex Processor 00 01 Vea 02 01 03 1 not used 04 Vccp 23 05 1 not used Notes 1 Check with VR vendors for determining the physical address assignment method for their controllers 2 addressing is assigned a per voltage rail basis 57 Electrical Specifications 3 Dual VR controllers will have two addresses with the lowest order address always being the higher phase 4 For future platform flexibility the VR controller should include an address offset as shown with 1 not used Table 7 3 12 0 Reference Code Voltage Identification VI D Table Hex cc Hex cc Hex cc Hex cc Hex cc Hex cc Vsa Vccp Vccp 00 0 00000 55 0 67000 78 0 84500 9B 1 02000 BE 1 19500 1 1 37000 33 0 50000 56 0 67500 79 0 85000 9C 1 02500 BF 1 20000 E2 1 37500 34 0 50500 57 0 68000 7A 0 85500 9D 1 03000 1 20500 1 38000 35 0 51000 58 0 68500 7B 0 86000 9E 1 03500 C1 1 21000 4 1 38500 36 0 51500 59 0 69000 7C 0 86500 9F 1 04000 C2 1 21500 E5 1 39000 37 0 52000 5A 0 69500 7D 0 87000 1 04500 1 22000 6 1 39500 38 0 52500 5B 0
148. nversion support Support for PCle 3 0 atomic operation PCle 3 0 optional extension on atomic read modify write mechanism 11 intel PCI Express Lane Partitioning and Direct Media nterface Gen 2 DMI2 Figure 1 2 1 3 3 12 I ntroduction Port 0 Port 1 Port 2 1012 1000 PCIe PCle LT E Physical 0 3 4 4 4 4 4 4 4 d 4 DMI Portla 10 Port2a 2 2 Port2d Port 1 Port 2a Port 2c X16 Port 2a Port 3 1001 NN 4 4 4 Port Port3b Port Port 3c X16 Port Direct Media nterface Gen 2 DMI2 Serves as the chip to chip interface to the PCH The DMI2 port supports x4 link width and only operates in a x4 mode when in DMI2 Operates at PCI Express 1 0 or 2 0 speeds Transparent to software Processor and peer to peer writes and reads with 64 bit address support APIC and Message Signaled Interrupt MSI support Will send Intel defined End of Interrupt broadcast message when initiated by the processor System Management Interrupt SMI SCI and SERR error indication Static lane numbering reversal support Supports DMI2 virtual channels VCO VC1 VCm and VCp Datasheet Introduction 1 3 4 1 4 1 4 1 1 4 2 1 4 3 1 4 4 1 5 Datasheet Platform Environment Control nterface
149. oN Resistance 31 8 DDRO1 RCOMP 0 COMP Resistance 128 7 130 131 3 9 12 DDRO1 RCOMP 1 COMP Resistance 25 839 26 1 26 361 Q 9 12 DDRO1 RCOMP 2 COMP Resistance 198 200 202 Q 9 12 DDR23 RCOMP O COMP Resistance 128 7 130 131 3 Q 9 12 DDR23 RCOMP 1 COMP Resistance 25 839 26 1 26 361 Q 9 12 DDR23 RCOMP 2 COMP Resistance 198 200 202 Q 9 12 DDR3 Miscellaneous Signals Input Low Voltage 0 55 Vccp 2 3 DRAM PWR C 01 23 0 2 id 11 13 Input High Voltage 0 55 Vccp 2 4 5 DRAM PWR 101 23 0 3 11 13 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies Datasheet 67 intel Electrical Specifications 2 voltage rail Vccp which will be set to 1 50V or 1 35V nominal depending on the voltage of all DIMMs connected to the processor 3 is the maximum voltage level at a receiving agent that will be interpreted as a logical low value 4 is the minimum voltage level at a receiving agent that will be interpreted as a logical high value 5 and may experience excursions above Vccp However input signal drivers must comply with the signal quality specifications 6 This is the pull down driver resistance Reset drive does not have a termination 7 Tern is the termination on the DIMM not controlled by the processor Refer to the applicable DI MM datasheet 8 The minimum and maximum values for th
150. ocessor disables code execution preventing damage and worm propagation Intel Hyper Threading Technology Intel HT Technology The processor supports Intel Hyper Threading Technology Intel HT Technology that allows an execution core to function as two logical processors While some execution resources such as caches execution units and buses are shared each logical processor has its own architectural state with its own set of general purpose registers and control registers This feature must be enabled using the BIOS and requires operating system support For more information on Intel Hyper Threading Technology see http www intel com products ht hyperthreading_more htm Datasheet Technologies 3 4 3 4 1 Note 3 5 Datasheet intel Intel Turbo Boost Technology Intel Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster than its rated operating frequency if it is operating below power temperature and current limits The result is increased performance in multi threaded and single threaded workloads It should be enabled in the BIOS for the processor to operate with maximum performance Intel Turbo Boost Operating Frequency The processor s rated frequency assumes that all execution cores are running an application at the thermal design power TDP However under typical operation not all cores are active Therefore most applications are cons
151. of PCI Express 3 0 links capable of 8 0 GT s and 4 lanes of DMI2 PCI Express 2 0 interface with a peak transfer rate of 5 0 GT s The processor supports up to 46 bits of physical address space and a 48 bit virtual address space Included in this family of processors is an integrated memory controller IMC and integrated I O such as PCI Express and DMI2 on a single silicon die This single die solution is known as a monolithic processor The Datasheet Volume 1 covers DC electrical specifications land and signal definitions differential signaling specifications interface functional descriptions power management descriptions and additional feature information pertinent to the implementation and operation of the processor on its platform Volume 2 provides register information Refer to the Related Documents section for access to Volume 2 Throughout this document the Intel Core i7 processor family for LGA2011 socket may be referred to as processor Throughout this document the Intel Core i7 49xx processor series for the LGA2011 socket refers t the Intel i7 4930K processor Throughout this document the Intel Core i7 48xx processor series for the LGA2011 socket refers to the Intel i7 4820K processor Throughout this document the Intel X79 Chipset Platform Controller Hub may be referred to as PCH Some processor features are not available on all platforms Refer to the processor sp
152. onversion Float 16 A group of 4 instructions that accelerate data conversion between 16 bit floating point format to 32 bit and vice versa This benefits image processing and graphical applications allowing compression of data so less memory and bandwidth is required The key advantages of Intel AVX are Performance Intel AVX can accelerate application performance using data parallelism and scalable hardware infrastructure across existing and new application domains 256 bit vector data sets can be processed up to twice the throughput of 128 bit data sets Application performance can scale up with the number of hardware threads and number of cores Application domain can scale out with advanced platform interconnect fabrics Power Efficiency Intel AVX is extremely power efficient Incremental power is insignificant when the instructions are unused or scarcely used Combined with the high performance that it can deliver applications that lend themselves heavily to using Intel AVX can be much more energy efficient and realize a higher performance per watt e Extensibility Intel AVX has built in extensibility for the future vector extensions Operating System context management for vector widths beyond 256 bits is streamlined Efficient instruction encoding allows unlimited functional enhancements Vector width support beyond 256 bits 256 bit Vector Integer processing Additional computational
153. ower performance balance Clock Partitioning and Recovery The bus clock continues running during state transition even when the core clock and Phase Locked Loop are stopped which allows logic to remain active The core clock can also restart more quickly under Enhanced Intel SpeedStep Technology For additional information on Enhanced Intel SpeedStep Technology refer to Section 4 2 1 27 intel 3 6 I ntel Advanced Vector Extensions Intel AVX Intel Advanced Vector Extensions Intel AVX is a new 256 bit vector SIMD extension of Intel Architecture The introduction of Intel AVX started with the 2nd Generation Intel9 Core processor family Intel AVX accelerates the trend of parallel computation in general purpose applications like image video and audio processing engineering applications such as 3D modeling and analysis scientific simulation and financial analysts Intel AVX is a comprehensive ISA extension of the Intel 64 Architecture The main elements of Intel AVX are Support for wider vector data up to 256 bit for floating point computation Efficient instruction encoding scheme that supports 3 operand syntax and headroom for future extensions Flexibility in programming environment ranging from branch handling to relaxed memory alignment requirements New data manipulation and arithmetic compute primitives including broadcast permute fused multiply add and so on Floating point bit depth c
154. pF 4 5 Signal noise immunity above 300 MHz 0 100 N A Vp p Output Edge Rate 50 ohm to VSS between Vi 15 4 Vins u a and Notes 1 supplies the interface behavior does not affect minimum maximum specification 2 Itis expected that the driver will take into account the variance in the receiver input thresholds and be able to drive its output within safe limits 0 150V to 0 275 for the low level and 0 725 to 0 150 for the high level 3 The leakage specification applies to powered devices on the PECI bus 4 One node is counted for each client and one node for the system host Extended trace lengths might appear as additional nodes 5 Excessive capacitive loading on the PECI line may slow down the signal rise fall times and consequently limit the maximum bit rate at which the interface can operate Table 7 15 System Reference Clock BCLK 0 1 DC Specifications Symbol Parameter Signal Min Max Unit Figure Notes Differential Input High Voltage Differential 0 150 N A V dit ij Differential Input Low Voltage Differential 0 150 V Vcross abs Absolute Crossing Point Single Ended 0 250 0 550 V 2 4 7 Relative Crossing Point 0 250 0 550 Veross rel Single Ended 0 5 0 5 V 3 4 5 V cross Range of Crossing Points Single Ended N A
155. package C state support as 1 the shallowest core C state that allows entry into the package C state 2 the additional factors that will restrict the state from going any deeper and 3 the actions taken with respect to the Ring Vcc PLL state and LLC Table 4 3 lists the processor core C states support Datasheet Power Management Table 4 2 Table 4 3 Datasheet Package C State Support i LLC Package C Core 4 4 Retention and 1 State States Limiting Factors PLL Off Basi Notes PCO Active 2 e PCle PCH and Remote Socket Snoops e PCle PCH and Remote Socket 2 VccMin Snoopable CC3 CC7 Interrupt response time MinFreq 2 Idle requirement PLL ON DMI Sidebands Configuration Constraints Core C State PC3 Light at least Snoop Response Time Vcc retention 2 3 4 Retention S 13 Interrupt Response Time OFF 9 Non Snoop Response Time LLC ways open PC6 B Deeper CC6 CC7 Snoop Response Time cn 2 3 4 Retention Non Snoop Response Time nterrupt Response Time Notes 1 Package C7 is not supported 2 package states are defined to be E states such that the states always exit back into the LFM point upon execution resume 3 The mapping of actions for PC3 and PC6 are suggestions microcode will dynamically determine which actions should be taken based on th
156. pecifications and functional descriptions are included in the Intel 64 and 32 Architectures Software Developer s Manual Volume 3B and is available at http www intel com products processor manuals index htm Intel Virtualization Technology Intel VT for Directed 1 Intel VT d adds processor and uncore implementations to support and improve 1 0 virtualization performance and robustness The Intel VT d specification and other Intel VT documents can be referenced at http www intel com technology virtualization index htm Intel VT x Objectives Intel VT x provides hardware acceleration for virtualization of 1 platforms Virtual Machine Monitor VMM can use Intel VT x features to provide improved reliable virtualized platforms By using Intel VT x a VMM is Robust VMMs no longer need to use para virtualization or binary translation This means that off the shelf operating systems and applications can be run without any special steps Enhanced Intel VT enables VMMs to run 64 bit guest operating systems on 1 x86 processors More reliable Due to the hardware support VMMs can now be smaller less complex and more efficient This improves reliability and availability and reduces the potential for software conflicts More secure The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system 23 intel
157. perature and current specifications limits of the Thermal Design Power TDP This results in increased performance of both single and multi threaded applications Intel Virtualization Technology Intel VT Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple robust independent software environments inside a single platform Datasheet Introduction Table 1 1 Datasheet intel Terminology Sheet 2 of 3 Term Description Intel virtualization Technology Intel VT for Directed 1 0 Intel VT d is a hardware assist under system software Virtual Machine Manager or operating system Intel control for enabling 1 0 device virtualization Intel VT d also brings robust security by providing protection from errant DMAs by using DMA remapping a key feature of Intel VT d Virtualization Jitter Any timing variation of a transition edge or edges from the defined Unit Interval UI JTAG Joint Test Action Group LGA2011 0 Socket The LGA2011 0 land FCLGA package mates with the system board through this surface mount LGA2011 0 contact socket LLC Last Level Cache MCH Memory Controller Hub Non Critical to Function NCTF locations are typically redundant ground or non NCTF critical reserved thus the loss of the solder joint continuity at end of life conditions will not affect the overall product
158. r s Manual Volume 3A 3B System Programmer s Guide for more information While a core is C1 CIE state it processes bus snoops and snoops from other threads For more information on see Section 4 2 5 2 Core C3 State Individual threads of a core can enter the state by initiating a LVL2 1 0 read to the P or an MWAIT C3 instruction A core in state flushes the contents of its L1 instruction cache L1 data cache and L2 cache to the shared L3 cache while maintaining its architectural state All core clocks are stopped at this point Because the core caches are flushed the processor does not wake any core that is in the C3 state when either a snoop is detected or when another core accesses cacheable memory Core C6 State Individual threads of a core can enter the state by initiating a P LVL3 1 0 read or an MWAIT C6 instruction Before entering core C6 the core saves its architectural state to a dedicated SRAM Once complete a core will have its voltage reduced to zero volts In addition to flushing core caches the core architecture state is saved to the uncore Once the core state save is completed core voltage is reduced to zero During exit the core is powered on and its architectural state is restored Core C7 State Individual threads of a core can enter the C7 state by initiating a P_LVL4 I O read to the P BLK or by an MWAIT C7 instruction Core C7 and core C7 substate are the same as Core C6
159. remains within specification VTTD_SENSE VSS_VTTD_SENSE VTTD_SENSE and VSS_VTTD_SENSE provide an isolated low impedance connection to the processor 1 0 power plane These signals must be connected to the voltage regulator feedback circuit that insures the output voltage that is processor voltage remains within specification VCCD_01 and VCCD_23 Variable power supply for the processor system memory interface These signals are provided by two VRM EVRD 12 0 compliant regulators per processor socket VCCD_01 and 23 are used for memory channels 0 1 2 and 3 respectively The valid voltage of this supply 1 50V or 1 35V is configured by BIOS after determining the operating voltages of the installed memory VCCD_01 and VCCD_23 will also be referred to as VCCD Note The processor must be provided 01 and 23 for proper operation even in configurations where no memory is populated A VRM EVRD 12 0 controller is recommended but not required VCCPLL Fixed power supply 1 7V for the processor phased lock loop PLL Variable power supply for the processor system agent units These include logic non 1 O for the integrated I O controller the integrated memory controller VSA IMC and the Power Control Unit PCU The output voltage of this supply is selected by the processor using the serial voltage 10 SVID bus Note VSA has a Vboot setting of 0 9V VSS Processor ground node VTTA Combined
160. ress Signals The PCI Express Signal Group consists of PCI Express ports 1 2 and 3 and PCI Express miscellaneous signals Refer to Table 7 5 for further details Direct Media nterface Gen 2 DMI2 PCI Express Signals The Direct Media Interface Gen 2 DMI 2 sends and receives packets and or commands to the PCH The DMI2 is an extension of the standard PCI Express Specification The DMI2 PCI Express Signals consist of DMI2 receive and transmit input output signals and a control signal to select DMI2 or PCle 2 0 operation for port 0 Refer to Table 7 5 for further details Datasheet 7 1 4 7 1 4 1 Figure 7 1 7 1 5 Datasheet Platform Environmental Control nterface PECI PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external system management logic and thermal monitoring devices The processor contains a Digital Thermal Sensor DTS that reports a relative die temperature as an offset from Thermal Control Circuit TCC activation temperature Temperature sensors located throughout the die are implemented as analog to digital converters calibrated at the factory PECI provides an interface for external devices to read processor temperature perform processor manageability functions and manage processor interface tuning and diagnostics Refer to the Processor Thermal Mechanical Specifications and Design Guidelines see Related Documents se
161. rnative Requester ID a PCI SIG ECR for increasing the function number count in PCle device to support 1 0 Virtualization 10 devices Improved invalidation architecture End point caching support ATS Interrupt remapping 3 1 4 Intel Virtualization Technology Processor Extensions The processor supports the following Intel VT processor extension features Large Intel VT d Pages Adds 2MB and 1GB page sizes to Intel VT d implementations Matches current support for Extended Page Tables EPT Ability to share processor EPT page table with super pages with Intel VT d Benefits Less memory foot print for 1 page tables when using super pages Potential for improved performance due to shorter page walks allows hardware optimization for Transition latency reductions expected to improve virtualization performance without the need for VMM enabling This reduces the VMM overheads further and increase virtualization performance Datasheet 25 intel 3 2 3 2 1 3 2 2 3 3 26 Security Technologies Intel Advanced Encryption Standard New Instructions Intel AES NI Instructions These instructions enable fast and secure data encryption and decryption using the Advanced Encryption Standard Intel AES NI which is defined by FIPS Publication number 197 Since Intel AES NI is the dominant block cipher and it is deployed in various protocols the new instructions will be v
162. s 1333 MT s 1600 MT s and 1866 MT s 64 bit wide channels DDR3 standard 1 0 Voltage of 1 5 1 Gb 2 Gb and 4 Gb DDR3 DRAM technologies supported for these devices UDIMMSs x8 x16 Up to 4 ranks supported per memory channel 1 2 or 4 ranks per DIMM Open with adaptive idle page close timer or closed page policy Per channel memory test and initialization engine can initialize DRAM to all logical zeros or a predefined test pattern Minimum memory configuration independent channel support with 1 DIMM populated Command launch modes of 1n 2n Improved Thermal Throttling Memory thermal monitoring support for DIMM temperature using two memory signals MEM HOT C 01 23 Datasheet Introduction intel 1 3 2 PCI Express Datasheet The PCI Express port s are fully compliant with the PCI Express Base Specification Revision 3 0 3 0 Support for PCI Express 3 0 8 0 GT s 2 0 5 0 GT s and 1 0 2 5 GT s Up to 40 lanes of PCI Express interconnect for general purpose PCI Express devices at PCle 3 0 speeds that are configurable for up to 10 independent ports 4 lanes of PCI Express at PCle 2 0 speeds when not using DMI2 port Port 0 also can be downgraded to x2 or x1 Negotiating down to narrower widths is supported see Figure 1 2 X16 port Port 2 and Port 3 may negotiate down to x8 x4 x2 or x1 x8 port Port 1 may negotiate down to x4 x2 or x1 x4 port Port 0 may negotiate
163. s for case temperature clock frequency and input voltages Care should be taken to read all notes associated with each specification For case temperature specifications refer to the appropriate processor Thermal Mechanical Specifications and Design Guide see Related Documents section Voltage and Current Specifications Table 7 10 Voltage Specifications Symbol Parameter Voltage Min Typ Max Unit Notes Plane Vcc VID Vcc VID Range 0 6 1 35 V 2 3 V Retention Voltage VID in package 0 65 V 2 3 and C6 states VecLL Vcc Loadline Slope Vec 0 8 Vac 15 mV 1 ru B VccRipple Vcc Ripple Vcc 5 mV 142 STEP VID step size during Vcc Vsa transition 5 0 mV 10 Vccd PLL Voltage 11 12 13 3 0 955 VccpLL_TYP 1 7 1 045 VccpLL_TYP V 17 Vccp 1 O Voltage for 11 13 14 oi DDR3 Standard Vccp 0 95 Vccp 1 5 1 05 Vccp V 16 17 Vccp 23 Voltage Uncore Voltage 0 957 1 00 1 043 3 EE 12 Vsa VID Range Vsa 0 6 0 940 1 25 V 2 3 14 15 System Agent 3 6 12 Vsa Voltage Vsa Vsa vip 0 057 vip 0 057 V 14 19 Notes 1 Unless otherwise noted all specifications in this table apply to all processors These specifications ar
164. s that represent the maximum or minimum device condition beyond which damage latent or otherwise may occur The table also specifies sustained storage temperature relative humidity and time duration limits These limits specify the maximum or minimum device storage conditions for a sustained period of time At conditions outside sustained limits but within absolute maximum and minimum ratings quality and reliability may be affected Storage Condition Ratings Symbol Parameter Min Max Unit The minimum maximum device storage temperature Tabsolute storage beyond which damage latent or otherwise may 25 125 occur when subjected to for any length of time 1 The minimum maximum device storage temperature 5 40 ec sustained storage for a sustained period of time 1 The ambient storage temperature in shipping media 20 85 ec short term storage for a short period of time The maximum device storage relative humidity for a 8 RHsustained storage sustained period of time 60 24 c A prolonged or extended period of time typically associated with sustained storage conditions Timesustained storage Unopened bag includes 6 months storage time by 0 30 months customer Timeshort term storage A short period of time in shipping media 0 72 hours Notes 1 Storage conditions are applicable to storage environments only In this scenario the processor must not receive a clock and no lands can be co
165. sed for memory DDR SCL channels 0 and 1 while DDR SCL C23 is used for memory channels 2 and 3 DDR SDA 01 SMBus data for the dedicated interface to the serial presence detect SPD and DDR SDA C23 thermal sensors TSoD the DIMMs DDR SDA is used for memory channels 0 and 1 while DDR SDA C23 is used for memory channels 2 and 3 DDR VREFDQRX 01 DDR VREFDQRX C23 Voltage reference for system memory reads DDR VREFDQRX 1 is used for memory channels 0 and 1 while DDR VREFDQRX C23 is used for memory channels 2 and 3 DDR VREFDQTX 01 DDR VREFDQTX C23 Voltage reference for system memory writes DDR VREFDQTX 1 is used for memory channels 0 and 1 while DDR VREFDQTX C23 is used for memory channels 2 and 3 These signals are not connected and there is no functionality provided on these two signals The signals are unused by the processor DDR 01 23 _RCOMP 2 0 System memory impedance compensation Impedance compensation must be terminated on the system board using a precision resistor DRAM_PWR_OK_CO1 DRAM_PWR_OK_C23 Power good input signal used to indicate that the Vccp power supply is stable for memory channels 0 and 1 and channels 2 and 3 PCI Express Based nterface Signals PCI Express Ports 1 2 and 3 signals are receive and transmit differential pairs PCI Express Port 1 Signals Signal Name Description DN 3 0 DP 3 0 PCle Rece
166. st 256 bytes of a logical device s configuration space and an extended PCI Express region which consists of the remaining configuration space The PCI compatible 20 Datasheet Interfaces 2 3 Note 2 3 1 2 3 2 2 3 3 2 4 Datasheet region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express configuration access mechanism described in the Express Enhanced Configuration Mechanism section The PCI Express Host Bridge is required to translate the memory mapped Express configuration space accesses from the host processor to PCI Express configuration cycles To maintain compatibility with configuration addressing mechanisms it is recommended that system software access the enhanced configuration space using 32 bit operations 32 bit aligned only See the Express Base Specification for details of both the PCl compatible and Express Enhanced configuration mechanisms and transaction rules Direct Media Interface 2 DMI2 Express Interface Direct Media Interface 2 DMI2 connects the processor to the Platform Controller Hub PCH DMI2 is similar to a four lane Express supporting a speed of 5 GT s per lane Refer to Section 6 3 for additional details Only DMI2 x4 configuration is supported DMI 2 Error Flow DMI2 can only generate SERR in response to errors never SCI SMI MSI PCI INT or GPE Any DMI2 related
167. st by Land Table 8 2 Land List by Land Number Sheet 29 of Number Sheet 30 of cand Land Name ria Direction po Land Name Direction 010 DDR3_DQS_DP 04 SSTL 1 0 DA49 PWR 012 DDR3_DQ 32 SSTL DAS vss GND 014 DDR3_ODT 4 SSTL DA51 vss GND 016 DDR3_CS_N 8 SSTL DA55 SAFE MODE BOOT CMOS 018 DDR3_MA 10 SSTL DA57 RSVD 02 vss GND DA7 1 01081 SSTL 1 0 D20 DDR3_MA 04 SSTL DA9 VSS GND D22 DDR3_MA 08 SSTL DB10 DDR1 001141 SSTL 1 0 D24 DDR3_MA 14 SSTL DB12 VSS GND D26 55 GND DBl4 DDR1 005 DN 17 SSTL 1 0 032 DDR3 DQ 18 SSTL 1 0 DB18 DDR1 MA 14 SSTL 034 DDR3 DQS DP 11 SSTL 082 VSS GND 036 55 GND 0820 DDR1 08 SSTL D38 DDR3 005 DP 00 SSTL 1 0 0822 DDR1_MA 04 SSTL 04 TEST3 0824 DDR1_CS 0 SSTL D40 DQ 05 SSTL 0826 DDR1 SSTL D42 DMI TX 0 PCIEX 0828 DDR1 RAS SSTL D44 DMI TX DNI 2 PCIEX DB30 DDR1 MA 13 SSTL 046 RSVD 0832 VSS GND 048 DN 1 PCIEX 0834 DDR1 005 DP 05 SSTL 1 0 050 PCIEX DB36 55 GND D52 DP 1 PCIEX3 DB38 DDR1 005 DP 16 SSTL 054 DP 2 PCIEX3 084 TESTO 056 RSVD 0840 DDR1 DQ 59 SSTL 1 0 D6 DDR3 DQ 53 SSTL 0856 RSVD D8 vss GND DB58 55 GND 2 11 VSS GND DB6 DDR1_DQ 13 SSTL 1 0 DA17 DDR1_CKE 3 SSTL DB8 DDRI 005 DN 10 SSTL 1 0 DA19 DDR1 MA 09 SSTL DC11
168. t Technology Intel Hyper Threading Technology Intel HT Technology Intel Streaming SIMD Extensions 1 ntel SSE Intel Core and the Intel logo are trademarks of Intel Corporation in the U S and or other countries Other names and brands be claimed as the property of others Copyright 2014 Intel Corporation All rights reserved 2 Datasheet Table of Contents 1 lntrod ctlioh deed nana dena E E d 8 1 1 Processor Feature Details eee nee eee ee eee ses 9 1 2 Supported Technologies cierra ee 10 1 37 10 1 371 System 5 2 lt 55 kba pr emen bene han ETE 10 1 3 2 PGI 55 tee HR ad 11 1 33 Direct Media Interface Gen 2 2 1 1 4 12 1 3 4 Platform Environment Control Interface 13 1 4 Power Management 5 ne enhn nn nnn nnn nn nn 13 1 4 1 Processor Package and Core 13 1 4 2 System States Support 13 1 4 3 Memory Controller
169. t by another reset transition of the latching signal RESET_N or PWRGOOD Power On Configuration Option Lands Configuration Option Land Name Notes Output tri state PROCHOT_N 1 Execute BIST Built In Self Test BIST_ENABLE 2 Enable Intel Trusted Execution Technology 1 ntel TXT Platform TXT_PLTEN 3 Power up Sequence Halt for ITP configuration EAR_N 3 Enable Intel Trusted Execution Technology Intel TXT Agent TXT_AGENT 3 Enable Safe Mode Boot SAFE MODE BOOT 3 Notes 1 Output tri state option enables Fault Resilient Booting FRB The RESET N signal is used to latch PROCHOT N for enabling FRB mode 2 BIST ENABLE is sampled at RESET N de assertion on the falling edge 3 This signal is sampled after PWRGOOD assertion Absolute Maximum and Minimum Ratings Table 7 8 specifies absolute maximum and minimum ratings At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional however with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits Although the processor contains protective circuitry to resist damage from E
170. t command is allowed but about 16 cycles until first data is allowed Self Refresh The Power Control Unit PCU may request the memory controller to place the DRAMs in self refresh state Self refresh per channel is supported The BIOS can put the channel in self refresh if software remaps memory to use a subset of all channels Also processor channels can enter self refresh autonomously without a PCU instruction when the package is in a package CO state Self Refresh Entry Self refresh entrance can be either disabled or triggered by an idle counter Idle counter always clears with any access to the memory controller and remains clear as long as the memory controller is not drained soon as the memory controller is drained the counter starts counting When it reaches the idle count the memory controller will place the DRAMs in self refresh state Power may be removed from the memory controller core at this point But Vccp supply 1 5V or 1 35V to the DDR I O must be maintained 41 intel E 4 3 2 2 4 3 2 3 4 3 3 4 4 42 Self Refresh Exit Self refresh exit can be either a message from an external unit PCU in most cases but also possibly from any message channel master or as reaction for an incoming transaction Here are the proper actions on self refresh exit CK is enabled and four CK cycles driven When proper skew between Address Command and CK are established assert CKE Issue NOPs for t
171. tate hints and the HLT instruction for C1 and However software may make C state requests using the legacy method of I O reads from the ACPI defined processor clock control registers referred to as P_LVLx This method of requesting C states provides legacy support for operating systems that initiate C state transitions using 1 0 reads For legacy operating systems LVLx 1 0 reads are converted within the processor to the equivalent MWAIT C state request Therefore P LVLx reads do not directly result in reads to the system The feature known as I O MWAIT redirection must be enabled in the BIOS The P LVLx 1 0 Monitor address needs to be set up before using the P LVLx I O read interface Each P LVLx is mapped to the supported MWAIT Cx instruction as shown in the following table P LVLx to MWAI T Conversion P LVLx MWAI T Cx Notes P_LVL2 MWAIT C3 P_LVL3 MWAIT C6 C6 No sub states allowed P_LVL4 MWAIT C7 C7 No sub states allowed The BIOS can write to the C state range field of the IO CAPTURE Model Specific Register MSR to restrict the range I O addresses that are trapped and emulate MWAIT like functionality Any LVLx reads outside of this range do not cause 1 0 redirection to MWAIT Cx like request The reads fall through like a normal I O instruction When P LVLx 1 0 instructions are used MWAIT substates cannot be defined MWAIT substate is always zero
172. te Signal ERR 55 m ns 3 Notes 1 This table applies to the processor sideband and miscellaneous signals specified in Table 7 5 2 Unless otherwise noted all specifications in this table apply to all processor frequencies 3 These signals are measured between Vj and Table 7 20 Miscellaneous Signals DC Specifications Symbol Parameter Min Typical Max Units Notes IVT ID N Signal Vo ABS MAX Output Absolute Maximum Voltage 1 10 1 80 V lo Output Current 0 uA 1 SKTOCC N Signal Vo ABS MAX Output Absolute Maximum Voltage 3 30 3 50 V l OMAX Output Max Current 1 mA Notes 4 ID N land is a no connect on the die 70 Datasheet 7 5 3 1 7 5 3 2 7 5 3 3 Datasheet PCI Express DC Specifications The processor DC specifications for the PCI Express are available in the PCI Express Base Specification Revision 3 0 This document will provide only the processor exceptions to the PCI Express Base Specification Revision 3 0 DMI 2 PCI Express DC Specifications The processor DC specifications for the DMI2 PCI Express are available in the PCI Express Base Specification Revisions 2 0 and 1 0 This document will provide only the processor exceptions to the PCI Express Base Specification Revisions 2 0 and 1 0 Reset and Miscellaneous Signal DC Specifications For a power on Reset RESET N must stay active for at least 3 5 millisecond after Vcc and BCLK 0 1 have reached their proper spe
173. umber and submits them to Physical Layer for transmission across the Link The receiving Data Link Layer is responsible for checking the integrity of received TLPs and for submitting them to the Transaction Layer for further processing On detection of TLP error s this layer is responsible for requesting retransmission of TLPs until information is correctly received or the Link is determined to have failed The Data Link Layer also generates and consumes packets that are used for Link management functions 2 2 1 3 Physical Layer The Physical Layer includes all circuitry for interface operation including driver and input buffers parallel to serial and serial to parallel conversion PLL s and impedance matching circuitry It also includes logical functions related to interface initialization and maintenance The Physical Layer exchanges data with the Data Link Layer in an implementation specific format and is responsible for converting this to an appropriate serialized format and transmitting it across the PCI Express Link at a frequency and width compatible with the remote device 2 2 2 PCI Express Configuration Mechanism The PCI Express link is mapped through a PCI to PCI bridge structure PCI Express extends the configuration space to 4096 bytes per device function as compared to 256 bytes allowed by the Conventional PCI Specification PCI Express configuration space is divided into a PCI compatible region which consists of the fir
174. uming less than the TDP at the rated frequency To take advantage of the available TDP headroom the active cores can increase their operating frequency To determine the highest performance frequency amongst active cores the processor takes the following into consideration number of cores operating in the CO state estimated current consumption estimated power consumption die temperature Any of these factors can affect the maximum frequency for a given workload If the power current or thermal limit is reached the processor will automatically reduce the frequency to stay with its TDP limit Intel Turbo Boost Technology is only active if the operating system is requesting the PO state For more information on P states and C states refer to Chapter 4 Enhanced Intel SpeedStep Technology The processor supports Enhanced Intel SpeedStep Technology as an advanced means of enabling very high performance while also meeting the power conservation needs of the platform Enhanced Intel SpeedStep Technology builds upon that architecture using design strategies that include the following Separation between Voltage and Frequency Changes By stepping voltage up and down in small increments separately from frequency changes the processor is able to reduce periods of system unavailability that occur during frequency change Thus the system is able to transition between voltage and frequency states more often providing improved p
175. ut THERMTRIP Miscellaneous Signals IVT ID N N A Output SKTOCC Power Other Signals Power Ground Vita 01 23 VccPLL and Vss Sense Points VCC SENSE VSS VCC SENSE VSS VITD SENSE SENSE VSA SENSE VSS VSA SENSE Notes 1 Refer to Chapter 6 for signal description details 2 DDR 0 1 2 3 refers to DDR3 Channel 0 DDR3 Channel 1 DDR3 Channel 2 and DDR3 Channel 3 61 intel Table 7 6 7 3 Table 7 7 7 4 62 Electrical Specifications Signals with On Die Termination Signal Name hie ed Rail Value Units Notes DDR 0 1 PAR ERR N Pull Up VCCD 01 65 Q DDR 2 3 PAR ERR N Pul Up VCCD 23 65 Q TXT AGENT Pull Down 55 2K Q SAFE_MODE_BOOT Pull Down vss 2K Q BIST_ENABLE Pul Up VIT 2K Q PLTEN Pul Up VIT 2K Q EAR N Pull Up VIT 2K Q 1 Notes 1 Refer to Table 7 17 for details on the Buffer on Resistance value for this signal Power On Configuration POC Options Several configuration options can be configured by hardware The processor samples its hardware configuration at reset on the active to inactive transition of RESET_N or upon assertion of PWRGOOD inactive to active transition For specifics on these options refer to Table 7 7 The sampled information configures the processor for subsequent operation These configuration options cannot be changed excep
176. with Intel virtualization Technology an Intel TXT enabled processor chipset BIOS Authenticated Code Modules and an Intel TXT compatible measured launched environment MLE The MLE could consist of a virtual machine monitor an OS or an application In addition Intel TXT requires the system to contain a TPM v1 2 as defined by the Trusted Computing Group and specific software for some uses For more information see http www intel com technology security Hyper Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology enabled chipset BIOS and operating system Performance will vary depending on the specific hardware and software you use For more information including details on which processors support HT Technology see http www intel com products ht hyperthreading_more htm Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain computer system software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible w
177. y or death SHOULD YOU PURCHASE OR USE INTEL S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES SUBCONTRACTORS AND AFFILIATES AND THE DIRECTORS OFFICERS AND EMPLOYEES OF EACH HARMLESS AGAINST ALL CLAIMS COSTS DAMAGES AND EXPENSES AND REASONABLE ATTORNEYS FEES ARISING OUT OF DIRECTLY OR INDIRECTLY ANY CLAIM OF PRODUCT LI ABILITY PERSONAL OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN MANUFACTURE OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request No computer system can provide absolute security under all conditions Intel Trusted Execution Technology Intel TXT requires a computer system

Download Pdf Manuals

Related Search

Related Contents

80/105# Landcruiser Castor Bushes  Les timbres distributeurs ou ATM au Maroc  Employee Login FULL User Manual  「これから頑張る合同会社の 法人税申告お助けくん」の サンプル会社の  取扱説明書等（1）    

Copyright © All rights reserved. Failed to retrieve file