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Intel Itanium 9560

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2. OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOQOQOQQ 1 Intel Itanium Processor 9300 Series Package Drawing Sheet 4 of 4 intel Figure 4 5 Intel Itanium Processor 9300 Series 9500 Series Datasheet 124 intel 125
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4. Intel Itanium Processor 9300 Series and 9500 Series Datasheet 121 m n tel Mechanical Specifications Figure 4 3 Intel Itanium Processor 9300 Series Processor Package Drawing Sheet 2 122 Intel Itanium Processor 9300 Series 9500 Series Datasheet intel Mechanical Specifications Intel I tanium Processor 9300 Series Package Drawing Sheet 3 of 4 Figure 4 4 xim xi 000000000000 000000000000 000000000000 0000000000000 0000000000000 0000000000000 000000000000 OOOO ROR OO 000000000000 0000000000 OOOOOOOOO
5. Cored Corel Core2 Core3 CPEO CPE1 CPE2 CPE3 Intel sM lt a m gt Intel SMI 1 4 5 Zbox0 Bbox0 gt Rbox lt gt Bboxt Zbox1 lt Intel SMI lt gt 5 4 m lt gt Intel SMI 1 X 1 5 Y Y Pbox Pbox Pbox Pbox Pbox Pbox 4 PRO PR1 PR2 PR3 PHS 1 Intel Intel Intel Intel Intel 1 2 2 Intel Itanium Processor 9500 Series Overview The Intel Itanium Processor 9500 Series is an eight core architecture It supports up to eight cores each with its own First Level Cache FLC and Mid Level Cache MLC both of which are split into instruction and data caches FLI FLD and MLI MLD respectively The Last Level Cache LLC is shared among the cores and supports up to 32 MB Also supported are the following page sizes for purges or inserts 4K 8K 16K 64K 256K 1M 4M 16M 64M 256M 1G 4G The architecture interfacing the cores to the system is referred to as the uncore Each Intel Itanium Processor 9500 Series core interfaces to the Ring The Ring provides connectivity to the Last Level Cache via the Cache Controllers Cboxes The Ring also provides connectivity to Intel via Ring Sbox The Sbox and provide the supports for the two Intel Caching Agents The proces
6. Table 3 3 5 J1 Connector Two Dimensional Table Intel Itanium Processor 9300 Series Sheet 2 of 2 1 2 3 4 AC vss AC AD vss AD AE VCCCACHE AE vss AG AH vss AH AJ VCCCORE AL vss AL AM vss AM AN VCCCORE AN AP VCCCORE AP AR vss AR AT vss AT AU Reserved Reserved AU AV VSSCACHESENSE VCCCACHESENSE AV NO CONNECT NO CONNECT AW VROUTPUT ENABLEO CPU PRESA N AW AY VR PROCTYPE 0 VR PROCTYPE 1 AY 1 2 3 4 3 2 1 2 Top Side J 1 Connector Two Dimensional Table for the ntel tanium Processor 9500 Series Table 3 4 is a two dimensional table of the Intel Itanium Processor 9500 Series package top side J 1 connector Table 3 4 Top Side J1 Connector Two Dimensional Table Intel Itanium Processor 9500 Series Sheet 1 of 3 1 2 3 4 A A NO CONNECT B NO CONNECT NO CONNECT B NO CONNECT RESERVED VSS E 1 2 3 4 106 Intel Itanium Processor 9300 Series and 9500 Series Datasheet Pin Listing Table 3 4 Top Side J 1 Connector Two Dimensional Table Intel Itanium Processor 9500 Series Sheet 2 of 3 intel 1 F VSS F G VCCCORE G H VCCCORE H J VCCCORE J K
7. Hex Vipe VID VID VID VID VID vip v VID6 VIDS VID2 00 0 0 0 0 OFF 2E 0 1 0 1 1 1 o 1 0375 01 0 0 0 0 1 1 6000 2 0 1 0 1 1 1 1 1 0250 02 0 0 0 0 1 15875 30 0 1 1 0 0 o 1 0125 03 0 0 0 0 1 1 15750 31 0 1 1 0 0 1 1 000 04 0 0 0 0 1 o 15625 2 0 1 1 0 0 1 0 0 9875 05 0 0 0 0 1 1 15500 33 0 1 1 0 0 1 1 0 9750 06 0 0 0 0 1 1 15375 34 0 1 1 0 1 o 0 9625 07 0 0 0 0 1 1 1 15250 35 0 1 1 0 1 o 0 9500 08 0 0 0 1 15125 36 0 1 1 0 1 1 0 0 9375 09 0 0 0 1 1 15000 37 0 1 1 0 1 1 1 0 9250 0A 0 0 0 1 1 14875 38 0 1 1 1 0 0 9125 0 0 0 1 1 1 14750 39 0 1 1 1 0 0 9000 oc 0 0 0 1 1 14625 0 1 1 1 0 1 o 0 8875 0 0 0 1 1 1 1 4500 3B 0 1 1 1 0 1 1 0 8750 0 0 0 1 1 1 14375 3C 0 1 1 1 1 0 8625 0 0 0 1 1 1 1 14250 0 1 1 1 1 1 0 8500 10 0 0 1 0 14125 0 1 1 1 1 1 0 0 8375 11 0 0 1 0 1 14000 0 1 1 1 1 1 1 0 8250 12 0 0 1 0 1 13875 40 1 1 1 0 0 o 0 8125 13 0 0 1 0 1 1 13750 41 1 1 1 0 0 o 0 8000 14 0 0 1 0 1 o 13625 42 1 1 1 0 0 1 0 0 7875 15 0 0 1 0 1 1
8. Pin Listing Table 3 1 Pin List by Pin Name Sheet 5 Table 3 1 Pin List by Pin Name Sheet 6 of 33 of 33 o Pin Name M Direction LUN Pin Name AN29 CSI1TNDAT 3 Differentia 21 5128 1 Differentia 1 CSI1TNDAT 4 Differentia G20 CSI2RNDAT 2 Differentia AL30 CSI1TNDAT 5 Differentia 221 CSI2RNDAT 3 Differentia 2 CSI1TNDAT 6 Differentia E23 CSI2RNDAT 4 Differentia 4 CSI1TNDAT 7 Differentia 20 CSI2RNDAT 5 Differentia 1 CSI1TNDAT 8 Differentia 021 CSI2RNDATT 6 Differentia AL33 CSI1TNDAT 9 Differentia 21 CSI2RNDAT 7 Differentia CSI1TNDAT 10 Differentia 20 CSI2RNDAT 8 Differentia 4 CSI1TNDAT 11 Differentia C22 CSI2RNDAT 9 Differentia AH32 CSI1TNDAT 12 Differentia B23 CSI 2RNDAT 10 Differentia CSI1TNDAT 13 Differentia 25 CSI 2RNDAT 11 Differentia CSI1TNDAT 14 Differentia 26 CSI 2RNDAT 12 Differentia 4 511 15 Differentia 25 CSI2RNDAT 13 Differentia AC34 CSI1TNDAT 16 Differentia 026 CSI2RNDAT 14 Differentia AB34 CSI1TNDAT 17 Differentia C27 CSI 2RNDAT 15 Differentia 5 CSI1TNDAT 18 Differentia 28 CSI 2RNDAT 16 Differentia 4 CSI1TNDAT 19 Differentia 0 CSI2RNDAT 17 Differentia 2 5 Differentia
9. 0 1 6 6 eene nnns 27 2 4 Differential Edge Rate 28 2 5 VRB and TStable 5 28 2 6 TX Equalization Diagram 1 e enn nns 31 27 TX LOSS entend na Oc FUTT FU EU UMANE NRI 32 2 8 RX Ret rr sectas I ded E SER VI E IRA UE 32 2 9 Processor Load Current versus 42 2 10 VCCUNCORE Static and Transient Tolerance for Intel Itanium Processor 9300 Series 4 45 2 11 VCCCORE Static and Transient Tolerance for Intel tanium Processor 9300 Series 47 2 12 VCCCACHE Static and Transient Tolerance for Intel Itanium Processor 9300 Series Fete reel aa 48 2 13 VCCUNCORE Static and Transient Tolerance for the Intel tanium Processor 9500 5 eene 50 2 14 VCCUNCORE Load Line for the Intel Itanium Processor 9500 Series 50 2 15 VCCCORE Load Line for the Intel Itanium Processor 9500 Series 51 2 16 VR Sense Point Representation 57 2 17 Supported Power up Voltage Sequence Timing Requirements for the Intel Itanium Processor 9300 Series
10. 29 Intel Itanium Processor 9300 Series Transmitter Parameter Values for Intel QuickPath Interconnect and Intel SMI Channels 9 4 8 GT s 29 Intel Itanium Processor 9300 Series Receiver Parameter Values for Intel QuickPath Interconnect and Intel SMI Channels 4 8 30 Intel tanium Processor 9500 Series Clock Frequency 33 Intel Itanium Processor 9500 Series Link Speed Independent Specifications 33 Intel Itanium Processor 9500 Series Transmitter and Receiver Parameter Values for Intel Channel at 4 8 5 34 Intel Itanium Processor 9500 Series Transmitter and Receiver Parameter Values for Intel at 6 4 5 35 Intel tanium Processor 9500 Series Transmitter and Receiver Parameter Values for Intel SMI at 6 4 GT s and 37 PLL Specification for TX and RX teer tee rere reet eria sa eiae pe 38 Intel Itanium Processor 9300 Series Absolute Maximum 39 Intel Itanium Processor 9500 Series Processor Absolute Maximum Ratings 39 FMB Voltage Specifications for the Intel Itanium Processor 9300 Series 40 130W Current Specifications for the Intel Itanium Proce
11. Tsustained storage The minimum maximum device storage 5 40 1 2 3 4 temperature for a sustained period of time RHsustained storage The maximum device storage relative 60 24 1 2 3 4 humidity a sustained period of time Timesustained storage A prolonged or extended period of time 0 months 12 months 1 2 3 4 typically associated with sustained storage conditions Notes 1 Storage conditions are applicable to storage environments only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation please refer to the processor case temperature specifications These ratings apply to the Intel component and do not include the tray or packaging Failure to adhere to this specification can affect the long term reliability of the processor Device storage temperature qualification methods follow ESD22 A119 low temp and ESD22 A103 high temp standards Bum 8 Intel Itanium Processor 9300 Series and 9500 Series Datasheet 141 tel Thermal Specifications 142 Intel Itanium Processor 9300 Series and 9500 Series Datasheet System Management Bus 1 tel 6 6 1 System Management Bus Interface The Intel Itanium Processor 9300 Series Intel Itanium Processor 9500 Ser
12. eese 141 Processor Information ROM Data 4 4 00 nnn nnn nnn 144 Read Byte SMBUS Packet occid RM ER E RR ERR NR EAR ERO EXER ei aed 150 Write Byte SMBus Packet petu ter het MERE 150 Offset 78h 79h Definitions 222 22 2 0 4 1 nnns 156 128 Byte Checksum 2 157 Signal Definitions for the Intel Itanium Processor 9300 Series and Intel Itanium 9500 Series 2 000 159 Intel Itanium Processor 9300 Series and 9500 Series Datasheet
13. Table 7 1 Signal Definitions for the Intel Itanium Processor 9300 Series and Intel Itanium 9500 Series Sheet 4 of 8 Name Type Description FBDINBI C D P N 12 0 These differential pair data signals generated from the branch channel C and D of FB DIMMs are input to the processor Fp 1 NB C D P N 12 0 DI MM Interface Branch North Input Channel Differential Lane Name Number Bound Pair Number Polarity Positive Negative Example FBD1NBICP 0 represents FB DIMM branch 1 northbound data input lane 0 signal of channel C and positive bit of the differential pair FBDINBI C D P N 13 These signals spare lanes are intended for Reliability Availability Serviceability RAS coverage on the Intel Itanium 9500 Processor Series These signals are not used by Intel Itanium 9300 Processor Series FBDOSBO A B P N 9 0 These differential pair output data signals generated from the processor to the branch zero channel A and B of FB DIMMs Fp 0 SB P N 9 0 DIMM 3 Interface Branch South Output Channel Differential Lane Name Number Bound Pair Number Polarity Positive Negative Example FBDOSBOAP 0 represents FB DIMM branch 1 southbound data output lane 0 signal of channel and positive bit of the differential pair FBDOSBO A B P N 10 These signals are spare lanes intended for Reliability Availability Se
14. 55 vss G H VCCCORE H J VCCCORE J K vss K L vss L M VCCCORE M N VCCCORE N 55 R vss R T VCCUNCORE T U VCCUNCORE U v VSS 1 2 3 4 108 Intel Itanium Processor 9300 Series 9500 Series Datasheet intel Pin Listing Table 3 5 Top Side J2 Connector Two Dimensional Table Intel Itanium Processor 9300 Series Sheet 2 of 2 1 3 4 VSS VCCUNCORE VCCUNCORE AA AB VCCUNCORE AB AC VSS AC AD VSS AD AE VCCUNCORE AE AF VCCUNCORE AF AG VSS AG AH VSS AH AJ VCCCORE AJ AK VCCCORE AK AL vss AL AM vss AM AN VCCCORE AN AP VCCCORE AP AR vss AR AT vss AT AU Reserved Reserved AU VCCCORESENSE VR_THERMTRIP_N AV NO CONNECT NO CONNECT AW VSSCORESENSE VR_THERMALERT_N AW AY vID_VCCCORE 0 CPU_PRESB_N AY 1 2 3 4 3 2 2 2 Top Side J 2 Connector Two Dimensional Table for the ntel Itanium Processor 9500 Series Table 3 6 is a two dimensional table of the Intel Itanium Processor 9500 Series package top side J 2 connector Intel Itanium Processor 9300 Series 9500 Series Datasheet 109 intel Table 3 6 9500 Series Sheet 1 of 2 Pin Listing Top Side J 2 Connector Two Dimensional Table Intel Itanium Processor
15. 15 1 2 1 Intel Itanium Processor 9300 Series Overview 15 1 2 2 Intel Itanium Processor 9500 Series Overview 16 1 3 Processor Feature Comparison 19 1 4 Processor Abstraction 4 4 2 4 0 9 1 20 1 5 Mixing Processors of Different Frequencies and Cache Sizes 20 1 6 Terminology viec m 20 1 7 State Of TRE 21 1 8 Reference EE EAE DEES nnne 21 2 Electrical 022 23 2 1 Intel QuickPath Interconnect and Intel Scalable Memory Interconnect Differential Signaling Re De xU DR DERE Rad n 23 22 Signal MEE 24 2 3 Reference Clocking Specifications 26 2 4 Intel QuickPath Interconnect and Intel SMI Signaling Specifications 28 2 4 1 Intel Itanium Processor 9300 Series Int
16. 110 1 2 3 4 A NO CONNECT NO CONNECT A B NO CONNECT NO CONNECT VR_READY B NO CONNECT RESERVED RESERVED 55 VSS VCCCORE G H VCCCORE H J VCCCORE J K VCCCORE K L VSS L M VSS M N VSS N VSS R T v w VSS w VSS Y AA VSS AA AB VSS AB AC VCCCORE AC AD VCCCORE AD AE VCCCORE AE AF VSS AG AH VSS AH AJ VSS VSS AK 1 2 3 4 Intel Itanium Processor 9300 Series and 9500 Series Datasheet Pin Listing ntel Table 3 6 5 J2 Connector Two Dimensional Table Intel Itanium Processor 9500 Series Sheet 2 of 2 1 2 3 4 AL VCCCOCRE AL AM VCCCORE AM AN VSS AR AT VSS AT AU vss vss AU AV CPU PRESB N VR_THERMTRIP_N AV NO CONNECT NO CONNECT AW NO CONNECT VR_THERMALERT_N AW AY NO CONNECT NO CONNECT AY 1 2 3 4 3 2 3 Top Side J3 Connector Two Dimensional Table 3 2 3 1 Top Side J3 Connector Two Dimensional Table for the Intel Itanium Processor 9300 Series Table 3 7 is a two dimensional table of the Intel Itanium Processor 9300 Series package top side J 3 connector Table 3 7 5 J3 Connector Two Dimensional Table Intel Processor 930
17. 152 6 4 4 Processor Uncore Data 1 1 4 153 6 4 5 Cache FREE TAY 154 6 4 6 EE REPE UR 155 6 4 7 Part Number 6 155 6 4 8 Thermal Reference Data 1 1 0402 2 442 11 nnns 155 6 4 9 Feature Data denis xen aie pipe d a ac pee ie Rc kdo e ERE Gd 156 64 10 Other Data er raa ha erac Ru en Ca RR C ER AU EE es 157 6 4 11 CHECKSUMS oes eder iaa ne Roe nne Pon ea b s ord mgr rca RD 157 7 Signal Definitions eser tU RR RAN E R 159 168 Intel Itanium Processor 9300 Series and 9500 Series Datasheet 1 1 Intel Itanium Processor 9300 Series Processor Block 16 1 2 Intel Itanium Processor 9500 Series Processor Block 17 1 3 Intel Itanium Processor 9500 Series Firmware 18 2 1 Active ODT for a Differential Link Example 23 2 2 Single ended Maximum and Minimum Levels and Vcross 27 2 3 Vcross delta
18. Table 3 2 Pin List by Pin Number Sheet Table 3 2 Pin List by Pin Number Sheet 19 of 32 20 of 32 SN Pin Name Direction Pisis Pin Name Direction C29 Other 031 vss Power Other C30 VSS Power Other D32 Power Other C31 CSI2RNDATT 18 Differentia 033 VSS Power Other C32 512 191 Differentia 034 CSIORNDAT 1 Differential C33 CSI2RNDAT 19 Differentia 035 CSIORNDAT 3 Differential C34 CSIORPDAT 1 Differentia 036 CSIORPDAT 4 Differential 5 55 Power Other D37 CPU_PRES2_N 1 0 C36 CSI ORNDAT 4 Differentia 038 RSVD C37 RSVD El VSS Power Other C38 VSS Power Other E2 FBDISBODP 4 Differential 01 RSVD E3 FBD1SBOCLKDPO Differential D2 FBDISBODN 4 Differentia 4 FBD1SBOCLKDNO Differential 03 VSS Power Other E5 VCCIO_FBD Power Other D4 FBDISBODP 5 Differentia 55 Other 05 FBDISBODN 7 Differentia 7 FBD1SBOCN 2 Differential D6 FBD1SBODP 7 Differentia 8 FBD1SBOCN 1 Differential 07 FBD1SBOCP 2 Differentia 10 VCCIO_FBD Power Other D8 vss Power Other E11 vss Power Other 09 FBD1SBOCP 3 Differentia 12 VCCIO_FBD Power Other D10 vss Power Other E13 VSS Power Other D11 FBD1SBOCP 0 Differentia 14 VCCIO Power Other D12 FBD1SBOCN 0 Differentia E15 VSS Power Other D13 VSS Power Other E16 VSS Power Other D14 VSS Power Other E17 CSI4RNDAT 7 Differentia 015 CSI4RNDAT 1 Differentia
19. 50 51 52 53 54 55 56 57 58 59 5 5 5 50 5 5 60 61 62 63 64 Intel Processor 9300 Series 9500 Series Datasheet 60 intel Electrical Specifications for ion Intel Itanium Processor 9500 Series VCCCORE VID VCCCORE and VCCUNCORE and VID VCCUNCORE Voltage Identification Def Sheet 3 of 4 Ararat Table 2 37 VID V 0 950 0 955 0 960 0 965 0 970 0 975 0 980 0 985 0 990 0 995 1 000 1 005 1 010 1 015 1 020 1 025 1 030 1 235 1 240 1 245 1 250 1 255 1 260 1 265 1 270 1 275 1 280 1 285 1 290 1 295 1 300 1 305 1 310 1 315 1 320 1 325 1 330 1 335 1 340 1 345 DO 1 0 1 0 I 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 VID VID VID VID VID VID VI 7 Hex 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 7 8 C9 CA CB D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC 0 750 0 755 0 760 0 765 0 770 0 775 0 780 0 785 0 790 0 795 0 800 0 805 0 810 0 815 0 8
20. Core Static and Transient Tolerances Table 2 24 and Figure 2 15 specify static and transient tolerances for the core outputs Intel Itanium Processor 9300 Series 9500 Series Datasheet Electrical Specifications intel Table 2 24 Vccconr Static and Transient Tolerance for the Intel Itanium Processor 9500 Series Notes 1 The Vcc Vcc load lines represent static and transient limits 2 This table is intended to 3 The load lines specify vo aid in reading discrete points on Figure 2 15 tage limits at the die measured at the VCCCORESENSE and VSSCORESENSE pins Core Current A Voltage Deviation from VID Setting V 1 2 3 4 Vcc Max Vcc Typ Vcc win 0 VID 0 015 VID VID 0 015 5 VID 0 005 VID 0 010 VID 0 025 10 VID 0 005 VID 0 020 VID 0 035 15 VID 0 015 VID 0 030 VID 0 045 20 VID 0 025 VID 0 040 VID 0 055 25 VID 0 035 VID 0 050 VID 0 065 30 VID 0 045 VID 0 060 VID 0 075 Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins Refer to the Ararat 11 Voltage Regulator Module Design Guide for socket load line guidelines and VR implementation 4 15 mV Vpc min 1 15 mV 2 mOhms Figure 2 15 Vcccore Load Line for the Intel Itanium Pro
21. of 32 of 32 NN Pin Name Direction Direction AH7 FBDOSBOBPI2 Differential A9 xpPocrD2 N AH8 XDPOCPD 0 _N AJ10 XDPOCPD 6 _N 9 XDPOCPD 4 _N 11 XDPOCP_STRB_IN_N 10 VSS Power Other AJ12 VSS Power Other 11 XDPOCP STRB OUT 13 vss Power Other AH12 VCCIO Power Other AJ14 515 1 Differentia AH13 515 0 Differentia 15 CSI5TNDAT 2 Differentia 14 CSI5TNDAT 1 Differentia 16 VSS Power Other AH15 VSS Power Other AJ17 515 4 Differentia AH16 5 Differential 18 vss Power Other AH17 CSI5TNDAT 4 Differentia 19 515 5 Differentia 18 vss Power Other AJ20 CSI5TNDAT 8 Differentia AH19 CSIS5TNDATI5 Differential 0 21 CSISTPDAT 8 Differentia 20 VSS Power Other AJ22 CSI5TNCLK Differentia 21 RSVD AJ 23 VSS Power Other AH22 VCCIO Power Other AJ24 PIR A1 Power Other AH23 VSS Power Other 25 0 Power Other 24 SDA Power Other 26 VSS Power Other AH25 VSS Power Other AJ27 CSI3TNDAT 9 Differentia 26 VSS Power Other AJ28 VSS Power Other AH27 VCCIO Power Other AJ29 CSI3TPDAT 10 Differentia 28 SKTID 1 30 CSI3TNDAT 11 Differentia 0 AH29 CSI 3TNDAT 10 Differentia 1 CSI 3TPDAT 11 Differentia VSS Power Other AJ32 CSI1TN
22. odd ana EINE awl eee 137 5 1 5 Thermal E x E 137 5 1 6 Thermal Eripe aped D 137 517 PROGCHOT citro titre he seman ERIS 138 5 1 8 5 138 5 1 9 Ararat Voltage Regulator Thermal Signals 138 5 2 Package Thermal Specifications and Considerations 139 5 3 Storage Conditions 5 140 6 System Management Bus 143 6 1 Introduction an 143 6 2 SMBus Memory 144 6 2 1 Processor Information ROM 144 0 2 2 Scratch EEPROM 2 Y ede e reu ere ur ede dui 149 6 2 3 and Scratch EEPROM Supported SMBus Transactions 150 6 3 Memory Component memes eese 150 6 4 PIROMField 5 essem nemen emen 152 6 41 Generale TM NE 152 6 4 2 Processor Rat RE d dE aed oe 152 6 4 3 Processor Core
23. T7 __ Power other VROUTPUT_ENABLEO T35 VCCIO Power Other AMI VRPWRGD Intel Itanium Processor U28 Power Other 9300 Series w35 VCCIO Power Other YR READY Intel Y27 VCCIO Power Other 9500 Series Y30 VCCIO Power Other Al4 VSS Power Other Y33 Power Other 16 55 Power Other 1 VCCIO FBD Power Other A19 vss Power Other VCCIO_FBD Power Other A24 VSS Power Other AB4 VCCIO FBD Power Other A29 vss Power Other ABO VCCIO_FBD Power Other A3 vss Power Other AC2 VCCIO_FBD Power Other A34 VSS Power Other VCCIOFBD Power Other A36 vss Power Other AE4 VCCIO_FBD Power Other 9 vss Power Other AE8 VCCIO_FBD Power Other 10 VSS Power Other AG4 VCCIO_FBD Power Other 28 vss Power Other 1 VCCIO_FBD Power Other AA29 vss Power Other 5 VCCIO_FBD Power Other AA30 vss Power Other AM4 VCCIO_FBD Power Other 4 vss Power Other AN7 VCCIO FBD Power Other vss Power Other AP10 VCCIO_FBD Power Other AAS VSS Power Other 5 VCCIO_FBD Power Other AAS vss Power Other 8 VCCIO_FBD Power Other AB10 vss Power Other 7 VCCIO_FBD Power Other 11 55 Power Other E10 VCCIO FBD Power Other AB12 vss Power Other E12 VCCIO_FBD Power Other AB2 vss Power Other E5 VCCIO_FBD Power Other AB27 VSS Power Other r8 VCCIO Power Other AB29 vss Power Other AB32 vss Power Other 84 Intel Itanium Processor 9300 Series 9500
24. 16 CSI5RPDAT 3 Differentia AL3 FBDONBIAN 9 Differentia 14 CSI5RPDAT 4 Differentia AL1 FBDONBIAN 10 Differentia AU13 CSI5RPDAT 5 Differentia 2 FBDONBIAN 11 Differentia AV14 CSI5RPDAT 6 Differentia 2 12 Differentia 15 CSI5RPDAT 7 Differentia FBDONBIAN 13 Differentia AU16 CSI5RPDAT 8 Differentia 11 FBDONBI ANI 14 Differentia 17 CSI5RPDAT 9 Differentia AU11 FBDONBIAP 0 Differentia 22 CSISTNCLK Differentia 010 FBDONBIAP 1 Differentia AG13 CSI5TNDAT O Differentia FBDONBIAP 2 Differentia 14 CSI5TNDAT 1 Differentia 10 FBDONBIAP 3 Differentia 15 515 21 Differentia 08 FBDONBIAP 4 Differentia 16 515 31 Differentia AU6 FBDONBIAP 5 Differentia 17 CSI5TNDAT 4 Differentia 4 FBDONBIAP 6 Differentia 19 CSI5TNDAT 5 Differentia 2 FBDONBIAP 7 Differentia 18 CSI5TNDAT 6 Differentia 4 FBDONBIAP 8 Differentia 78 Intel Itanium Processor 9300 Series 9500 Series Datasheet intel Pin Listing Table 3 1 Pin List by Pin Name Sheet 13 Table 3 1 Pin List by Pin Name Sheet 14 of 33 of 33 ML Pin Name Direction Direction AM3 FBDONBIAP 9 Differentia 16 FBDOREFSYSCLKN Dif
25. 51 01 Differentia C34 CSIORPDAT 1 Differentia B35 CSIORPDAT 2 Differentia 5 CSIORPDAT 3 Differentia 036 CSIORPDAT 4 Differentia 8 CSIORPDAT 5 Differentia 7 51 61 Differentia G36 CSIORPDAT 7 Differentia H37 CSIORPDAT 8 Differentia 136 51 91 Differentia 137 CSIORPDAT 10 Differentia M38 CSIORPDAT 11 Differentia N38 CSIORPDAT 12 Differentia P37 CSIORPDAT 13 Differentia 838 CSIORPDAT 14 Differentia T37 CSIORPDAT 15 Differentia 038 CSIORPDAT 16 Differentia V36 CSIORPDAT 17 Differentia V37 CSIORPDAT 18 Differentia W36 CSIORPDAT 19 Differentia CSIOTNCLK Differentia K30 510 01 Differentia 31 CSIOTNDAT 1 Differentia G31 CSIOTNDAT 2 Differentia CSIOTNDAT 3 Differentia K32 CSIOTNDAT 4 Differentia F31 CSIOTNDAT 5 Differentia 2 51 61 Differentia 73 intel Pin Listing Table 3 1 Pin List by Pin Name Sheet Table 3 1 Pin List by Pin Name Sheet 4 of 33 of 33 Direction LA Pin Name mL Direction F33 CSIOTNDAT 7 Differentia 6 5118 5 Differentia H33 CSIOTNDAT 8 Differentia 7 CSI I1RNDATT 6 Differentia 131 CSIOTNDAT 9 Differentia 7 CSI1RNDA
26. load lines specify voltage limits at the die measured at the and Vsscoresense PINS Voltage regulation feedback for voltage regulator circuits must be taken from processor Vcc and Vss pins Refer to the Ararat Voltage Regulator Module Design Guide for socket load line guidelines and VR implementation 4 Vpc max zVID 4 mV VID 19 mV Vpc min zVID 34 Ry 0 85 Figure 2 11 Static and Transient Tolerance for Intel Itanium Processor 9300 2 6 3 3 Intel Itanium Processor 9300 Series and 9500 Series Datasheet Series VccCORE Tolerance Bands AC V 0 00 DC V Typical Vcc V m yp V DC min V 0 04 AC min V 0 06 z 8 0 08 gt N 010 042 0 14 0 16 0 18 0 20 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 Cache Static and Transient Tolerances Table 2 22 and Figure 2 12 specify static and transient tolerances for the cache outputs 47 intel Electrical Specifications Table 2 22 Veccacne Static and Transient Tolerance for Intel Itanium Processor 9300 Series Cache Current A Voltage Deviation from VID Setting V 1 2 3 4
27. max load lines represent static and transient limits 2 This table is intended to aid in reading discrete points on Figure 2 14 3 The load lines specify voltage limits at the die measured at the VCCUNCORESENSE and VSSUNCORESENSE pins Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins Refer to the Ararat 11 Voltage Regulator Module Design Guide for socket load line guidelines and VR implementation 4 Vpc max zVID Rj lcc 15 mV Vpc min VID Ri lcc 15 mV Ry 1 25 mOhm 49 intel Figure 2 13 Static and Transient Tolerance for the I ntel Itanium Processor Figure 2 14 2 6 4 2 50 9500 Series 2 2 2 gt T 2 20 Electrical Specifications VccUnCore Tolerance Band VccUnCore ACMax V VccUnCore DCMax V Normalized VccUnCore V DCMin V amp VccUnCore ACMin V 40 60 80 IccUnCore A Load Line for the Intel Itanium Processor 9500 Series 0 0150 0 0050 0 0250 0 0450 0 0650 0 0850 0 1050 0 1250 0 1450 0 1650 Normalized VccUnCore V 20 VccUnCore Tolerance Band VccUnCore ACMax V qg VccUnCore DCMax V Normalized V ccUnCore V 3 MccUnCore V V ccUnCore V 40 60 80 100 120 IccUnCore A
28. 12 Power Other AT14 VSS Power Other AR13 CSI5RNDAT 4 Differentia 15 CSI5RPDAT 7 Differentia 14 CSI5RPDAT 4 Differentia 16 CSI5RNDAT 9 Differentia 15 CSI5RNDAT 7 Differentia 17 CSI5RPDAT 9 Differentia 16 VSS Power Other AT18 CSI3RPDAT 7 Differentia AR17 CSI 5RPCLK Differentia 19 VSS Power Other AR18 CSI3RPDAT 5 Differentia 20 CSI3RNDAT 9 Differentia Intel Itanium Processor 9300 Series and 9500 Series Datasheet 95 intel Pin Listing Table 3 2 Pin List by Pin Number Sheet Table 3 2 Pin List by Pin Number Sheet 15 of 32 16 of 32 Direction Direction AT21 CSI3RPCLK Differential AU23 CSI 3RNDAT 11 Differentia 22 CSI3RNDAT 10 Differential AU24 CSI 3RPDAT 13 Differentia AT23 CSI 3RPDAT 11 Differential AU25 CSI 3RNDAT 13 Differentia 24 VSS Power Other AU26 CSI 14 Differentia 25 Power Other AU27 VSS Power Other AT26 CSI 3RPDAT 14 Differential 028 CSI 3RNDAT 16 Differentia 27 CSI3RNDAT 15 Differential 029 CSI 3RPDAT 18 Differentia 28 CSI 3RPDAT 161 Differential AU30 CSI 181 Differentia 29 VSS Power Other AU31 CSI 3RPDAT 19 Differentia AT30 SPDCLK 1 0 AU32 vss Powe
29. SPDDAT 3 SPDCLK SPDCLK 8 BOOTMODE 1 BOOTMODE 1 BOOTMODE 0 BOOTMODE 0 THERMALERT THERMALERT N 5 SKTID 0 Sk TID Jo q SKTID 1 4 SKTID 1 SKTID 2 lt Intel Itanium Processor 9300 Series 9500 Series Datasheet 151 6 4 1 6 4 2 6 4 3 6 4 3 1 6 4 3 2 152 n tel System Management Bus I nterface PI ROM Field Definitions PIROM data is divided into sections containing similar data Each section contains specific fields defined in the following sections General To maintain backward compatibility the General section defines the starting address for each subsequent section of the PIROM Software should check for the offset before reading data from a particular section of the ROM The General section begins with offset 00h which contains Data Format Revision information followed by the EEPROM size both formatted in Hex bytes The data format revision is used whenever fields within the PIROM are updated with new values Normally the revision would begin at a value of 1 If a field or bit assignment within a field is changed such that software needs to discern between the old and new definition then the data format revision field should be incremented Processor Data This section contains
30. Pin Listing Table 3 1 Pin List by Pin Name Sheet 17 Table 3 1 Pin List by Pin Name Sheet 18 of 33 of 33 M Pin Name M Direction Direction 012 15 0 Differentia D6 FBD1SBODP 7 Differential 8 FBD1SBOCN 1 Differentia F6 FBD1SBODP 8 Differential 7 15 2 Differentia 5 FBD1SBODP 9 Differential C9 FBD1SBOCN 3 Differentia 6 FBD1SBODP 10 Differential C8 FBD1SBOCN 4 Differentia 28 FLASHROM_CFG 0 10 FBD1SBOCN 5 Differentia 28 FLASHROM_CFG 1 11 FBD1SBOCN 6 Differentia 128 FLASHROM_CFG 2 12 15 7 Differentia 27 FLASHROM_CLK 1 FBD1SBOCN 8 Differentia 130 FLASHROM CS 0 N 9 FBD1SBOCN 9 Differentia 29 FLASHROM_CS 1 _N B13 FBD1SBOCNI10 Differentia 829 FLASHROM_CS 2 _N 011 FBD1SBOCP 0 Differentia 29 FLASHROM_CS 3 _N 9 FBD1SBOCP 1 Differentia T28 FLASHROM DATI 07 FBD1SBOCP 2 Differentia 0 R28 FLASHROM_DATO 0 D9 FBD1SBOCP 3 Differentia 0 L27 FLASHROM_WP_N 7 FBD1SBOCP 4 Differentia K10 FORCEPR_N 10 FBD1SBOCP 5 Differentia 0 M11 LRGSCLSYS 11 FBD1SBOCP 6 Differentia 0 K12 MEM_THROTTLE_L 11 FBD1SBOCP 7 Differentia 25 0 Power Other C12 FBD1SBOCP 8 Differentia 24 1 Power Other l B8 FBD1SBOCP 9 Differentia 24 SCL Power Other 13 FBD1SBOCP 10 Differentia 24 PIR_SDA Power Other 1
31. Symbol Parameter Min Nom Max Unit Notes TXcik acc jit N Ul 1E 7 accumulated jitter out of 0 0 15 UI transmitter over 0 lt lt NUI where 12 measured with 1 7 probability TXclk acc jit N_UI 1E 9 accumulated jitter out of 0 0 17 UI 7 transmitter over 0 lt lt NUI where N 12 measured with 1 9 probability TTx data clk skew pin Delay of any data lane relative to 0 5 0 5 Ul clock lane as measured at Tx output Vnx diff pp pin Voltage eye opening at the end of 225 1200 mV channel for any data or clock channel measured with a cumulative probability of 1E 9 UI TRx diff pp pin Timing eye opening at the end of 0 63 1 UI Tx channel for any data or clock channel measured with a cumulative probability of 1E 9 UI TRx data clk skew pin Delay of any data lane relative to 1 3 UI the clock lane as measured at the end of Tx channel This parameter is a collective sum of effects of data clock mismatches in Tx and on the medium connecting Tx and Rx VRx CLK Forward CLK Rx input voltage 180 mV sensitivity differential pp Vnx cm dc pin DC common mode ranges at the 125 350 mV Rx input for any data or clock channel Vnx cm ac pin AC common mode ranges at the 50 50 2 Rx input for data or clock channel defined as 2 7 VRX cm dc pin Notes 1 1300 mVpp swing is recommended when CPU to CPU o
32. 24 VSS Power Other G26 512 41 Differentia 25 CSI2TNDAT 2 Differentia 627 VSS Power Other F26 512 51 Differentia G28 512 81 Differentia 227 512 51 Differentia 629 Power Other F28 512 81 Differentia G30 CSIOTPDAT 2 Differentia F29 VSS Power Other G31 CSIOTNDAT 2 Differentia CSIOTNDAT 3 Differentia G32 VSS Power Other F31 CSIOTNDAT 5 Differentia G33 CSIOTPDAT 7 Differentia 2 CSIOTPDAT 5 Differentia G34 Power Other F33 CSIOTNDAT 7 Differentia G35 CSI ORNDAT 7 Differentia 4 VSS Power Other G36 CSIORPDAT 7 Differentia Intel Itanium Processor 9300 Series and 9500 Series Datasheet 99 intel Table 3 2 Pin List by Pin Number Sheet Table 3 2 Pin List by Pin Number Sheet 23 of 32 24 of 32 SN Pin Name Buses deos Direction hc m Pin Name Direction 67 vss PoweyOther 1 VCCIO Power Other G38 RSVD 12 FBDOSBOAN 10 Differential 1 FBDISBODN O0 Differential 13 VSS Power Other H2 FBDISBODP O Differential 14 VCCIO_FBD Power Other H3 FBDISBODP 1 Differential 5 VSS Power Other H4 VSS Power Other 16 VSS Power Other H5 VSS Power Other 7 FBD1NBIDN 11 Differential 6 FBD1SBODP 10 Differentia 18 vss Power Other H7 VCCIO FBD
33. 9500 Series Datasheet 115 intel 3 2 4 2 Processor 9500 Series Pin Listing Top Side J 4 Connector Two Dimensional Table for the I ntel Itanium9 Table 3 10 is a two dimensional table of the Intel Itanium Processor 9500 Series package top side J 4 connector Table 3 10 Top Side 4 Connector Two Dimensional Table Intel Itanium Processor 9500 Series Sheet 1 of 2 116 1 2 3 4 A NO CONNECT NO CONNECT NO CONNECT NO CONNECT A B RESERVED RESERVED B RESERVED RESERVED vss F vss VCCCORE G H VCCCORE H L vss L M vss M N vss N vss R VCCCORE R T VCCCORE T w vss w Y vss Y AA vss AA AB vss AB AC VCCCORE AC AD VCCCORE AD AE VCCCORE AE AF VCCCORE AF AG vss AG 1 2 3 4 Intel Itanium Processor 9300 Series 9500 Series Datasheet Pin Listing Table 3 10 Top Side 4 Connector Two Dimensional Table Intel Itanium Processor 9500 Series Sheet 2 of 2 intel 1 2 3 4 AH VSS AH AJ VSS VSS AK AL VCCCORE AL AM VCCCORE AM AN VCCCORE AN AP VCCCORE AP AR VSS AR AT VSS AT AU VCCIO VSS AU RESERVED AV NO CONNECT NO CONNECT AW
34. Intel Itanium Processor 9300 Series 9500 Series Datasheet Mechanical Specifications Figure 4 10 Processor Marking Zones Bottom Side Intel Itanium Processor 9300 Series and 9500 Series Datasheet tel Mechanical Specifications 132 Intel Itanium Processor 9300 Series and 9500 Series Datasheet m Thermal Specifications tel 5 5 1 Note Thermal Specifications This chapter provides the thermal specifications of the Intel Itanium Processor 9300 Series and the Intel Itanium Processor 9500 Series processors The Intel Itanium Processor 9300 Series and the Intel Itanium Processor 9500 Series processors power and thermal management is built from four subsystems or components These are power measurement components the temperature measurement components the frequency control components and the voltage control components that work in concert allowing the management system to maximize performance within a given power and thermal envelope This results in higher average core frequency performance compared to a worst case fixed frequency It boosts performance based on application activity The power and thermal management system is fully integrated within the Intel Itanium Processor 9300 Series and Intel Itanium9 Processor 9500 Series The power and thermal management system is designed for repeatable performance under the same
35. Power Other H33 CSIOTNDAT 8 Differentia 35 CSIORNDAT 9 Differential H34 CSIOTPDAT 8 Differentia 136 CSIORPDAT 9 Differential H35 VSS Power Other 137 CSIORNCLK Differential H36 CSI ORNDAT 8 Differentia 138 VSS Power Other H37 CSIORPDAT 8 Differentia K1 VSS Power Other H38 VRTHERMRIPN FBDOSBOAP 10 Differential 0 100 Intel Itanium Processor 9300 Series 9500 Series Datasheet intel Pin Listing Table 3 2 Pin List by Pin Number Sheet Table 3 2 Pin List by Pin Number Sheet 25 of 32 26 of 32 A Direction ie Pin Name BE eae Direction K3 VSS Power Other 15 FBD1NBIDP 7 Differential K4 FBD1NBIDN 9 Differentia 16 FBD1NBIDP 10 Differential 5 FBD1NBIDP 9 Differentia 17 FBD1NBIDN 10 Differential K6 VSS Power Other L8 FBD1NBICLKCNO Differential 7 FBD1NBI DP 11 Differentia 19 VSS Power Other K8 1 6 Differentia 110 PROCHOT_N K9 FBD1NBICN 6 Differentia 111 FBD1NBICP 12 Differential K10 FORCEPR_N 112 FBD1NBI CN 12 Differential K11 VSS Power Other L13 RSVD K12 MEM THROTTLE L 114 vss Power Other K13 CSI4TNDAT 1 Differentia 115 VCCIO Power Other K14 CSI4TPDAT 1 Differentia 116 VSS Power Other K15 CSI4TNDAT 2 Different
36. V7 FBDINBICN 1 Differentia W37 CSIORNDAT 19 Differentia FBDINBICP 1 Differentia w38 VSS Power Other FBDINBICNIO Differential 1 vi vss Power Other V10 VSS Power Other Y2 VCCIO FBD Power Other V11 SYSUTST REFCLK Differentia FBDOSBOBN 10 Differential vi2 RESETN YA FBDOSBOBP 10 Differential V27 RSVD Y5 VSS Power Other V28 TESTHI 4 VSS Power Other V29 RSVD Y7 FBD1NBIDP 2 Differential v30 VSS Power Other Y8 FBDINBICN 14 Differential V31 CSI 2TPDAT 18 Differentia Y9 FBDINBICP 14 Differential V32 CSIOTNDAT 17 Differentia 10 RSVD V33 CSIOTPDAT 17 Differentia 11 VSS Power Other V34 CSI OTNDAT 18 Differentia Y12 SYSCLK Differential V35 VSS Power Other Y27 VCCIO Power Other V36 CSIORPDAT 17 Differentia Y28 TESTHI 1 V37 CSIORPDAT 18 Differentia 29 VSS Power Other v38 CSIORNDAT 18 Differential Y30 VCCIO Power Other W1 FBDOSBOAN 1 Differentia 1 VSS Power Other 2 FBDOSBOAP 1 Differentia Y32 CSIOTPDAT 19 Differentia w3 VSS Power Other Y33 Power Other WA FBDOSBOAP O0 Differentia Y34 CSI1TNDAT 19 Differentia w5 VCCIO FBD Power Other Y35 CSI1TPDAT 19 Differentia W6 FBDINBIDN 3 Differentia 6 VSS Power Other W7 FBD1NBIDN 2 Differentia 7 511 191 Differentia w8 VSS Power Other Y38 CSI1RNDAT 19 Differentia w9 FBDINBICP 0 Differentia 9 10 RSV
37. dani 130 5 Thermal Specifications 2 eee 133 5 1 Thermal Features RENE 133 5 1 1 Digital Thermometer 1111 134 5 1 2 Thermal Management id cscs dd 135 51 38 Thermal ERE ER eot iid 136 5 14 TCONTROL i i reo 137 5145 Thermal xci ence tlie 137 5 16 Thermal Trip iei eric rere Dee 137 551 7 IMMER ML E 138 5 1 8 FORCEPR 5 Piiira naina iis 138 5 1 9 Ararat Voltage Regulator Thermal Signals 138 5 2 Package Thermal Specifications and 139 5 3 Storage Conditions Specifications cece emnes 140 6 System Management Bus 1 enna 143 6 1 introduction ici 143 6 2 SMBus Memory nn nnn nn nnn 144 6 2 1 Processor Inform
38. iff dB diff RL TDR POL2 RXdata 50ohm OC S 1 1 dB d freq GHz Intel Itanium Processor 9500 Series Requirements for Intel QuickPath I nterconnect for 4 8 and 6 4 GT s The applicability of this section applies to Intel Itanium9 Processor 9500 Series This section contains information for slow boot up speed 1 4 frequency of the reference clock 4 8 GT s and 6 4 GT s for Intel and Intel 5 For Intel slow boot up speed the signaling rate is defined as 1 4 the rate of the system reference clock For example a 133 MHz system reference clock would have a forwarded clock frequency of 33 33 MHz and the signaling rate would be 66 67 MT s Intel Itanium Processor 9300 Series 9500 Series Datasheet Electrical Specifications Table 2 7 Table 2 8 intel The transfer rates available for the processor are shown in Table 2 7 Transmitter and receiver parameters for Intel slow mode Intel and Intel SMI are shown in Table 2 8 and Table 2 9 respectively Intel I tanium Processor 9500 Series Clock Frequency Table Intel QuickPath I nterconnect Data Transfer Rate Intel QuickPath I nterconnect Forwarded Clock Frequency 33 33 MHz 66 66 MT s see note 1 2 40 GHz 4 8 GT s 3 2 GHz 6 4 GT s Notes 1 This speed is the 1 4 SysCIk Frequency The applicability of this section applies to Intel for the Intel
39. sss mme 66 2 18 Supported Power up Sequence Timing Requirements for Intel Itanium Processor 9500 67 2 19 Supported Power down Voltage Sequence Timing 5 69 2 20 RESET and SKITID Timing for Warm and Cold Resets 70 4 1 Processor Package Assembly Sketch 2 7 2 2 119 4 2 Intel Itanium Processor 9300 Series Package Drawing Sheet 1 of 4 121 4 3 Intel Itanium Processor 9300 Series Processor Package Drawing Sheet 2 of 4 122 4 4 Intel Itanium Processor 9300 Series Package Drawing Sheet of 4 123 4 5 Intel Itanium Processor 9300 Series Package Drawing Sheet 4 of 4 124 4 6 Intel Itanium Processor 9500 Series Package Drawing Sheet 1 of 4 125 4 7 Intel Itanium Processor 9500 Series Package Drawing Sheet 2 of 4 126 4 8 Intel Itanium Processor 9500 Series Package Drawing Sheet of 4 127 4 9 Intel Itanium Processor 9500 Series Package Drawing Sheet 4 of 4 128 4 10 Processor Marking eene pei eoa ec va e d da eu dtr rc 131 5 1 Intel Itanium Processor 9300 Series and Intel tanium Processor 9500 Series Thermal States 134 5 2 Intel Itanium Processor 9300 Series and Intel
40. 1 1 11 0 280 1 0 1 1 1 o 0 475 08 0 0 0 1 o o 0 285 0 1 0 1 1 1 1 0 480 09 0 0 1 o o 1 0 290 30 1 1 o 0 485 0 0 0 1 o 1 o 0 295 31 0 1 1 o 1 0 490 0 0 0 1 o 1 1 0 300 32 0 1 1 1 0 0 495 0 0 1 1 o 0 305 33 0 1 1 1 1 0 500 0 0 0 1 1 1 0 310 34 0 1 1 0 1 0 0 505 0 0 1 1 1 o 0 315 35 0 1 1 0 1 1 0 510 0 0 0 1 1 1 1 0 320 36 1 1 0 1 1 0 0 515 10 0 0 1 o 0 325 37 0 1 1 0 1 1 1 0 520 11 0 0 1 o 1 0 30 38 0 1 1 1 o 0 525 12 0 0 1 1 0 335 39 1 1 1 1 0 530 13 0 0 1 1 1 0 340 0 1 1 1 0 1 0 0 535 14 0 0 1 1 fo 0 0 345 3B 1 1 1 0 1 11 0 540 15 0 0 1 1 1 0 350 3c 1 1 1 1 0 0 545 Intel Itanium Processor 9300 Series and 9500 Series Datasheet 59 Electrical Specifications intel for ion Intel I tanium Processor 9500 Series VCCCORE VID VCCCORE VCCUNCORE and VID VCCUNCORE Voltage Identification Def Sheet 2 of 4 Ararat 11 Table 2 37 VID V 0 550 0 555 0 560 0 565 0 570 0 575 0 580 0 585 0 590 0 595 0 600
41. 12 Differential 29 512 111 Differentia 7 FBDINBICLKDPO Differential 30 512 11 Differentia 8 VSS Power Other M31 CSI 2TNDAT 13 Differentia 9 FBDINBI CN 5 Differential M32 VSS Power Other P10 RSVD1 Intel M33 CSIOTPDAT 10 Differentia M34 CSIOTNDAT 11 Differentia SVID CLK2 Intel Itanium Processor M35 CSIOTPDAT 11 Differentia 9500 Series M36 RSVD 11 37 VSS Power Other P12 TDI 38 CSIORPDAT 11 Differential 27 RSVD 1 FBDOSBOAP 6 Differential 28 VSS Power Other N2 FBDOSBOAP 5 Differential 29 FLASHROM_CS 1 _N N3 FBDOSBOAN 5 Differential 0 CSI2TNDAT 12 Differential 4 VCCIO FBD Power Other P31 CSI2TPDAT 12 Differential 5 VSS Power Other P32 CSI2TNDAT 15 Differential 6 FBD1NBI DP 6 Differential P33 VSS Power Other N7 FBD1NBI DP 8 Differential 4 CSI OTPDAT 13 Differential FBD1NBIDN 8 Differential P35 VSS Power Other 102 Intel Itanium Processor 9300 Series and 9500 Series Datasheet intel Pin Listing Table 3 2 Pin List by Pin Number Sheet Table 3 2 Pin List by Pin Number Sheet 29 of 32 30 of 32 T Direction Direction P36 CSIORNDAT 13 Differential
42. CACHE Vcc Max Vcc Typ Vcc win 0 VID 0 VID 0 02 VID 0 04 5 VID 0 017 VID 0 037 VID 0 057 10 VID 0 035 VID 0 055 VID 0 075 15 VID 0 052 VID 0 072 VID 0 092 20 VID 0 069 VID 0 089 VID 0 109 25 VID 01 086 VID 0 106 VID 0 126 30 VID 0 104 VID 0 124 VID 0 144 35 VID 0 121 VID 0 141 VID 0 161 40 VID 0 138 VID 0 158 VID 0 178 45 VID 0 155 VID 0 175 VID 0 195 50 VID 0 173 VID 0 193 VID 0 213 55 VID 0 19 VID 0 21 VID 0 23 Notes 1 The Vcc min max load lines represent static and transient limits 2 This table is intended to aid in reading discrete points on Figure 2 12 3 The load lines specify voltage limits at the die measured at the and VsscacHeEsENseE 0115 Voltage regulation feedback for voltage regulator circuits must be taken from processor Vcc and Vss pins Refer to the Ararat Voltage Regulator Module Design Guide for socket load line guidelines and VR implementation 4 Vpc max zVID Rj lcc 5 mV Vpc min ZVID Ry l cc 35 mV Ry 3 45 mW Figure 2 12 Static and Transient Tolerance for Intel Itanium Processor 9300 Series VccCACHE Tolerance Bands s max V 0 00 DC max Typical Vcc V 0 02 3 DC min 0 04 AC min V 0 06 gt 0 08 o gt 5 0 10 4 0 12 4 2 20
43. UI mV Intel Itanium Processor 9300 Series and 9500 Series Datasheet 37 intel Electrical Specifications Table 2 11 Intel Itanium Processor 9500 Series Transmitter and Receiver Parameter Values for Intel SMI at 6 4 GT s and lower Sheet 2 of 2 Symbol Parameter Min Nom Max Unit Notes VRx Vmargin Any data lane Rx input voltage 100 mV differential pp measured at BER 1E 9 TRx Tmargin Timing width for any data lane using 0 8 Ul repetitive patterns and clean forwarded CLK measured at BER 1E 9 VRx cm dc pin DC common mode ranges at the Rx input 125 350 mV for any data or clock channel defined as average of VD and VD Vnx cm ac pin AC common mode ranges at the Rx input 50 50 mV for any data or clock channel defined as Vp4 2 7 VRx cm dc pin Notes 1 This is the swing specification for the forwarded CLK output Note that this specification will also have to be suitably de embedded for package PCB loss to translate the value to the pad since there is a significant variation between traces in a setup 2 While the X talk is off on die noise similar to that occurring with all the transmitter and receiver lanes toggling will still need to be present When a socket is not present in the transmitter measurement setup in many cases the contribution of the cross talk is not significant or can be estimated within tolerable error even with all the transmitte
44. VCCCORE This provides power to the Cores on the processor This is on the top of the package and is driven by the Ararat Voltage Regulator Actual value of the voltage is determined by the settings of VID VCCCOREL 6 0 VCCCORESENSE VSSCORESENSE Remote sense lines used by the Ararat Voltage Regulator to sense VCCCORE die voltage The Voltage Regulator should not draw more than 0 1 from these pads VCCUNCORE This provides power to the Uncore on the processor This is on the top of the package and is driven by the Ararat Voltage Regulator Actual value of the voltage is determined by the settings of VID VCCUNCORE 6 0 VCCUNCORESENSE VSSUNCORESENSE Remote sense lines used by the Ararat Voltage Regulator to sense VCCUNCORE die voltage The Voltage Regulator should not draw more than 0 1 from these pads VCCUNCOREREADY This signal is sent to the processor from the Ararat When high the VCCUNCORE rail has completed its startup sequence and is at a nominal operating voltage VCCIO provides power to the input output interface the processor die VCCIO FBD VCCIO FBD provides power to the FBD DIMM input output interface on the processor die VFUSERM This pin must be tied to VCCIO or connected to VCCIO via 0 ohm resistor VID VCCCORE 6 0 VID VCCUNCORE 6 0 VID VCCCACHE 5 0 VCCCORE VID VCCUNCORE VID and VID VCCCACHE Voltage ID pads are used to support automatic s
45. 012 VSS Power Other R38 CSI ORPDAT 14 Differentia 027 VSS Power Other T1 FBDOSBOAN 4 Differentia 028 VCCIO Power Other T2 FBDOSBOAP 4 Differentia 029 CSI 2TNDAT 17 Differentia T3 VCCIO FBD Power Other U30 CSI2TPDAT 17 Differentia VSS Power Other U31 CSI 2TNDAT 18 Differentia 5 FBD1NBI DP 13 Differential 032 VSS Power Other T6 FBD1NBIDP 5 Differential 033 CSI OTNDAT 16 Differentia T7 FBDINBIDN 5 Differential 034 CSI OTPDAT 16 Differentia T8 FBDINBICN 2 Differential 035 VSS Power Other T9 VSS Power Other U36 CSI ORNDAT 17 Differentia T10 VCCIO FBD Power Other U37 VSS Power Other Intel Itanium Processor 9300 Series and 9500 Series Datasheet 103 intel Table 3 2 Pin List by Pin Number Sheet Table 3 2 Pin List by Pin Number Sheet 31 of 32 32 of 32 MN Pin Name Direction 038 CSIORPDAT16 Differential 1 w30 CSI2TNDATI19 Differential V1 FBDOSBOAP 3 Differentia W31 CSI2TPDAT 19 Differentia V2 FBDOSBOAN 2 Differentia W32 CSIOTNDAT 19 Differentia V3 FBDOSBOAP 2 Differentia w33 VSS Power Other V4 FBDOSBOAN 0 Differentia W34 CSI OTPDAT 18 Differentia v5 VSS Power Other W35 Power Other V6 FBD1NBI DP 3 Differentia W36 CSIORPDAT 19 Differentia
46. 1 CSI 2RNDAT 18 Differentia 126 CSI1TPDAT O Differentia C33 CSI 2RNDAT 19 Differentia AN27 CSI1TPDAT 1 Differentia 22 512 Differentia 28 CSI1TPDAT 2 Differentia 21 512 0 Differentia 29 CSI1TPDAT 3 Differentia 621 CSI2RPDATT 1 Differentia CSI1TPDAT 4 Differentia G19 512 21 Differentia 0 511 51 Differentia 20 512 31 Differentia 2 511 61 Differentia 22 512 41 Differentia AN33 CSI1TPDAT 7 Differentia 020 512 51 Differentia 1 CSI1TPDAT 8 Differentia 022 CSI2RPDATT 6 Differentia AL32 CSI1TPDAT 9 Differentia 21 5128 7 Differentia AK34 CSI1TPDAT 10 Differentia 20 5128 8 Differentia 34 CSI1TPDAT 11 Differentia C23 5128 9 Differentia CSI1TPDAT 12 Differentia 2 CSI2RPDAT 10 Differentia AG34 CSI1TPDAT 13 Differentia 24 CSI2RPDAT 11 Differentia CSI1TPDAT 14 Differentia 26 CSI2RPDAT 12 Differentia 5 CSI1TPDAT 15 Differentia 26 CSI2RPDAT 13 Differentia AD34 CSI1TPDAT 16 Differentia 027 CSI2RPDAT 14 Differentia 5 CSI1TPDAT 17 Differentia 28 CSI2RPDAT 15 Differentia 6 CSI1TPDAT 18 Differentia 29 CSI2RPDAT 16 Differentia 5 CSI1TPDAT 19 Differentia CSI2RPDAT 17 Differenti
47. CX 19 OX ie OOOO OX 19 DEPARTWENT T 19 ie ie OO0000000000000000000000000000000000000 90090090090000009000000900000000000900000000 0900909099000009090009909090000900090009000900 jet OX 9 9 9 OX Q 999609005060 9 09600000000 3 N Y AB AD AF AH AK AP AT AV AY AC AE AG AJ AL AN AR AU AW VIEW AY Ay AT AP AM AK AH Ar AD AB AW AU AR AN AL AJ AG AE gt 4321 128 Intel Itanium Processor 9300 Series 9500 Series Datasheet Mechanical Specifications 4 3 4 4 Table 4 1 4 5 Table 4 2 intel Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements A thermal and mechanical solution design must not intrude into the required keepout zones Decoupling capacitors are typically mounted to both the top side and bottom side of the package substrate See Figure 4 4 for Intel Itanium 9300 Series Processor
48. Itanium Processor 9300 Series 0000 45 VCCCORE Static and Transient Tolerance for Intel Itanium Processor 9300 47 Static and Transient Tolerance for Intel ltanium Processor 9300 Series tre itr 48 VCCUNCORE Static and Transient Tolerance for the Intel Itanium Processor 9500 Series E e d ba Pera 50 VCCUNCORE Load Line for the Intel Itanium Processor 9500 Series 50 VCCCORE Load Line for the Intel Itanium Processor 9500 Series 51 VR Sense Point Representation 57 Supported Power up Voltage Sequence Timing Requirements for the Intel Itanium Processor 9300 2 0000 0 4 4 0 66 Supported Power up Sequence Timing Requirements for Intel Itanium Processor 9500 2 4 67 Supported Power down Voltage Sequence Timing 69 RESET and SKITID Timing for Warm and Cold Resets 2 70 Processor Package Assembly Sketch emen 119 Intel Itanium Processor 9300 Series Package Drawing Sheet 1 of 4 121 Intel tanium Processor 9300 Series Processor Package Drawing Sheet 2 of 4 122 Intel Itanium Processor
49. Itanium Processor 9300 Series Absolute Maximum Ratings 39 2 5 2 Intel Itanium Processor 9500 Series Absolute Maximum Ratings 39 2 6 Processor DC 5 exo eR eR teers cae RENE 39 2 6 1 Flexible Motherboard Guidelines for the Intel Itanium Processor 9300 1 4 2 0 6 6 n 40 2 6 2 Flexible Motherboard Guidelines for the Intel Itanium Processor 9500 Series edere dt d enne dot P ERU ER Ra ted 43 2 6 3 Intel Itanium Processor 9300 Series Uncore Core and Cache Tolerances 44 2 6 4 Intel Itanium Processor 9500 Series Uncore and Core Tolerances 49 2 6 5 Overshoot and Undershoot Guidelines essem 52 2 6 6 Signal DC Specifications orisiirisii 53 2 6 7 Motherboard Socket Specification for VR Sense 57 2 7 Core and Uncore Voltage 57 2 7 1 Core and Uncore Voltage Identification for the Intel Processor 9300 Series 58 2 7 2 Core and Uncore Voltage Identification for the Intel Itanium Processor 9500 Series 59 2 8 Cache Voltage Identification Intel tanium Processor 9300 Series only 62 2 9 RSVD Unused and DEBUG 4 4 44444 0 nnne nn nnn 63 2 10 M
50. Output High Voltage VCCIO 0 2 VCCIO V VoL Output Low Voltage 0 0 25 1 lot Output Low Current 16 23 mA 1 liLeak Input Leakage Current 1000 200 2 Output Leakage Current 1000 200 Notes 1 With 50W termination to VCCIO at the far end Intel Itanium Processor 9300 Series 9500 Series Datasheet Electrical Specifications 2 6 6 1 Table 2 31 2 6 6 2 Table 2 32 intel 2 With input leakage current measured at the pin with OV and with 1 1 V supplied to the pin System designers are advised to check the tolerance of their voltage regulator solutions to ensure a voltage of 1 1 V at the pin VID VCCCORE VID VCCUNCORE and VID VCCCACHE DC Specifications for the Intel Itanium Processor 9300 Series The Intel tanium9 Processor 9300 Series processor supplies top side VID signal pins to the Arafat Voltage Regulator Module as shown in Table 2 31 VID VCCCORE 6 0 VID VCCUNCORE 6 0 and VID VCCCACHE 5 0 DC Specifications for the I ntel tanium Processor 9300 Series Symbol Parameter Min Max Unit Notes Vou Output High Voltage VCCIO 0 1 V 1 VoL Output Low Voltage 0 0 1 V 1 l OLeak Output Leakage Current 200 200 1 2 Notes 1 These parameters are not tested and are based on design simulations 2 Leakage to VSS with pin held at 1 1 V and leakage to 1 1 V with pin held at VSS SVI D Group DC Specifications for the I ntel Itanium Proce
51. Package Handling Guidelines Parameter Maximum Recommended Unit Notes Shear 356 N 1 4 Tensile 156 N 2 4 Torque 8 N m 3 4 Note 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 tensile load is defined as a pulling load applied to the IHS in the direction normal to the IHS surface 3 A torque load is defined as a twisting load applied to the IHS an axis of rotation normal to the IHS top surface 4 These guidelines are based on limited testing for design characterization The Intel Itanium9 Processor 9300 Series can be inserted into and removed from a LGA1248 socket and engaged and disengaged with the Ararat voltage regulator up to a maximum limit as specified in Table 4 3 Intel Itanium Processor 9300 Series 9500 Series Datasheet 129 m e n tel Mechanical Specifications Table 4 3 4 7 Note Table 4 4 4 8 Table 4 5 130 Processor Package nsertion Specification Package Durability Limit 1248 Land FCLGA 15 Processor Mass Specifications The typical mass of the Intel Itanium Processor 9300 Series and 9500 Series is 55 0 This mass weight includes all the components that are included in the package Processor Materials Table 4 4 lists some of the package components and associated materials Lead and other materials banned in Restriction on Hazardous Substances RoHS Directive ar
52. Processor 9300 Series and 9500 Series Datasheet Signal Definitions intel Table 7 1 Signal Definitions for the Intel Itanium Processor 9300 Series and Intel Itanium 9500 Series Sheet 5 of 8 Name Type Description FORCEPR_N When logic 0 forces processor power reduction Refer to the Intel Itanium 9300 Series Processor and Intel Itanium Processor 9500 Series Platform Design Guide for a detailed signal description LRGSCLSYS The header mode is selected by the LRGSCLSYS strapping pin value sampled only during COLD reset LRGSCLSYS when tied to VCCIO using a 50 ohm resistor puts the processor in extended header mode and LRGSCLSYS when tied to GND puts the processor in standard header mode MEM_THROTTLE_L When this pin is asserted on the Intel Itanium Processor 9300 Series the internal memory controllers throttle the memory command issue rate to a configurable fraction of the nominal command rate settings This pin is not used on the Intel Itanium 9500 Processor Series PIR_SCL Processor Information ROM Serial Clock The PIR_SCL input clock is used to clock data into and out of the on package PIROM device This signal applies to the EEPROM which is composed of the PIROM and the OEM Scratch PAD PIR SDA 1 0 Processor Information ROM Serial Data The PIR_SDA pin is a bidirectional signal for serial data transfer This signal applies to the EEPROM which is compo
53. T11 RSVD1 Intel P37 CSIORPDAT 13 Differential 8 VSS Power Other SVID_ALERT_N Intel Itanium Processor R1 VSS Power Other 9500 Series R2 FBDOSBOCLKANO Differentia T12 VFUSERM R3 FBDOSBOCLKAPO Differentia T27 Power Other R4 VSS Power Other T28 FLASHROM_DATI 5 FBD1NBI DN 13 Differentia T29 vss Power Other R6 VSS Power Other T30 512 14 Differential 7 FBDINBICLKDNO Differentia T31 CSI 2TNDATT 16 Differential R8 FBDINBICP 4 Differentia T32 CSI 2TPDAT 16 Differential R9 FBDINBICN 4 Differentia T33 CSIOTPDAT 15 Differential R10 RSVD1 Intel T34 VSS Power Other Itanium Processor 9300 Series T35 VCCIO Power Other SVID DATIO Intel T36 CSIORNDAT 15 Differential Itanium Processor 9500 Series T37 CSI ORPDAT 15 Differential R11 VSS Power Other T38 CSIORNDAT 16 Differential R12 TMS 01 FBDOSBOAN 3 Differential R27 RSVD U2 VSS Power Other R28 FLASHROM_DATO 93 vss Power Other R29 FLASHROM_CS 2 _N U4 RSVD R30 512 141 Differentia U5 FBDINBIDN 4 Differentia 831 VSS Power Other U6 FBDINBIDP 4 Differentia 832 CSI2TPDAT 15 Differentia 07 VSS Power Other R33 CSIOTNDAT 15 Differentia FBDINBICP 2 Differentia R34 CSIOTNDAT 14 Differentia 09 FBDINBICP 3 Differentia 835 CSIOTPDAT 14 Differentia 010 FBDINBICN 3 Differentia R36 VSS Power Other 011 SYSUTST_REFCLK_N Differentia 837 CSIORNDAT 14 Differentia
54. Voltage Regulator Module Design Guide for termination requirements for the Intel Itanium 9500 Processor Series SVID DATIO 1 0 This is a bi directional data signal between the Intel Itanium 9500 Processor Series and the Ararat voltage regulator This is an open drain signal See Ararat 11 Voltage Regulator Module Design Guide for termination requirements for the Intel Itanium 9500 Processor Series SVID_ALERT_N This is an asynchronous signal driven by the Ararat voltage regulator to indicate the need to read the status register See Ararat Voltage Regulator Design Guide for termination requirements for the Intel Itanium 9500 Processor Series SYSCLK SYSCLK The differential clock pair SYSCLK SYSCLK N provides the fundamental clock source for the processor processor link agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of SYSCLK crossing the falling edge of SYSCLK N This differential clock pair should not be asserted until VCCA VCCIO VCC33 SM and VCC 12 V Ararat are stabilized SYSUTST REFCLK SYSUTST REFCLK N These serve as reference clocks for the processor socket logic analyzer interposer device during debug It is not used by the processor and is not connected internally to the die Electrical specifications on these clocks are identical to SYSCLK SYSCLK N
55. With reference to the power sequencing timing requirements imposed by the Ararat VR as shown in Figure 2 17 and Figure 2 18 timing specifications for the elapsed time taken for an Ararat regulator to bring up each of its output voltages can be found in the Ararat 170 Watt Voltage Regulator Module Design Guide for the Intel Itanium Processor 9300 Series and the Ararat 11 Voltage Regulator Module Design Guide for the Intel Itanium Processor 9500 Series When the platform asserts PWRGOOD to the processor the Intel Itanium Processor 9300 Series requires a minimum of 10 ms to complete its internal reset sequence before deasserting RESET while the Intel Itanium Processor 9500 Series requires a minimum of 15 ms For platforms that use both processors a minimum of 15 ms is needed to meet the requirements of both processors During platform initialization the RESET pin to any component in the platform can be removed ONLY after all other components have had sufficient time to sample their respective reset pins This is needed to prevent unknown behavior that may result if any one system component comes out of reset before other components have received the reset signal With the exception of standby miscellaneous pins all input pins bi directional pins and terminated output pins must not be allowed to exceed the processor s actual VCCIO voltage prior to and during ramp up of the VCCIO supply Intel Itanium Processor 9300
56. tel Figure 2 19 Supported Power down Voltage Sequence Timing Requirements le As fast as possible RESET_N c PWGOOD VR OUTPUT t Possi after PWRGOOD deassertion gt l 4 gt 0us I 9 AU Supplies to ower down as fastas t e VIDs change to safe VID All signal inputs plane fan power down with VCCIO VCCUNCORE gt 1 8 X gt Ous REFCLK 133 MHz IN MUST UNPOWER ALONG WITH VCCIO 10 for Intel Itanium 9300 Series Processor 15ms for Poulson MC Processor _ 2 13 Timing Relationship Between RESET and SKTID In the processor the SKTID pins are time shared SKTID 0 is interpreted as a NodelD bit during cold reset and pwrgood reset It is interpreted as the error reset modifier during warm logic reset if SKTID 0 is asserted SKTID 2 is interpreted as a NodelD bit during cold reset and pwrgood reset and it is interpreted as an error input being signaled by the system at all other times except during non cold resets when it is ignored Figure 2 20 and Table 2 40 show the timing relationship between RESET and SKTID pins for different reset cases The LRGSCLSYS pin is sampled only during the P
57. 510 9 Differentia 6 511 71 Differentia M33 CSIOTPDAT 10 Differentia 5 CSI1RPDAT 8 Differentia M35 CSI OTPDAT 11 Differentia AL36 CSI1RPDAT 9 Differentia 33 CSIOTPDAT 12 Differentia AJ36 CSI TRPDAT 10 Differentia 4 CSIOTPDAT 13 Differentia 7 511 111 Differentia 35 CSI OTPDAT 14 Differentia 6 511 121 Differentia T33 CSI OTPDAT 15 Differentia AG38 511 131 Differentia 034 CSI OTPDAT 16 Differentia 7 511 141 Differentia V33 CSIOTPDAT 17 Differentia AE38 511 151 Differentia W34 CSI OTPDAT 181 Differentia AD37 511 161 Differentia 2 CSI OTPDAT 19 Differentia AC38 511 171 Differentia AK38 CSI1RNCLK Differentia AB38 CSI1RPDAT 18 Differentia AU33 5118 0 Differentia 7 511 191 Differentia 5118 1 Differentia 32 CSI1TNCLK Differentia 4 5118 2 Differentia 127 CSI1TNDAT O Differentia 4 CSI1RNDAT 3 Differentia 28 CSI1TNDAT 1 Differentia 5 5118 4 Differentia 128 511 21 Differentia 74 Intel Itanium Processor 9300 Series 9500 Series Datasheet intel
58. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 2 6 Processor DC Specifications Table 2 15 through Table 2 35 list the DC specifications for the Intel Itanium Processor 9300 Series and 9500 Series and are valid only while meeting specifications for case temperature clock frequency and input voltages The following notes apply Intel Itanium Processor 9300 Series and 9500 Series Datasheet intel Electrical Specifications Unless otherwise noted all specifications in the tables apply to all frequencies For the Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series these specifications are based on characterized data from silicon measurements 2 6 1 Flexible Motherboard Guidelines for the Intel I tanium Processor 9300 Series The Flexible Motherboard FMB guidelines are estimates of the maximum ratings that the processor will have over certain time periods The ratings are only estimates as actual specifications for future processors may differ The processor may or may not have specifications equal to the FMB value in the foreseeable future Table 2 15 defines the FMB voltage specification values applied to the 130W and 155W 185W Intel Itanium Processor 9300 Series stock keeping units SKUs Current specifications are identi
59. Figure 2 6 4 termination small signal resistance tolerance over the entire signalling voltage range shall not exceed 5 ohms 5 Requires Matlab script 6 Refer to Intel QuickPath Interconnect Intel Electrical Specifications for calculation of this value Note that UI to UI definition is used herein where the value of UI UI DCD 2 UI DCD 7 Figure 2 7 8 Applies to Vtx diff pp pin 9 Peak to peak value of the ripple Table 2 6 Intel Itanium Processor 9300 Series Receiver Parameter Values for Intel QuickPath Interconnect and Intel SMI Channels 4 8 GT Sheet 1 of 2 Symbol Parameter Min Nom Max Units Notes RX termination resistance 37 4 47 6 Q 3 Trx data clk skew pin Delay of any data lane relative to the clock lane as measured at the end of Tx channel This parameter is 0 5 3 5 UI 2 a collective sum of effects of data clock mismatches in Tx the medium connecting Tx Delay of any data lane relative to the clock lane as _ measured at the end of Tx channel This parameter is TRx data clk skew pin collective sum of effects of data clock mismatches in 0 48 9l Tx the medium connecting Tx and RLrx DIFF Receiver differential return loss from 50 MHz to 2 GHz 10 dB 6 RLRX DIFF Receiver differential return loss from 2GHz to 4GHz 6 dB 6 VRx data cm pin Receiver data
60. Itanium Processor 9500 Series This section contains information for slow boot up speed 1 4 frequency of the reference clock 4 8 GT s and 6 4 GT s Specifications for link speed independent specifications are called out in Table 2 8 Electrical specifications for Transmit and Receive for 4 8 GT s are captured in Table 2 9 and for 6 4 GT s are captured in Table 2 10 Intel Itanium Processor 9500 Series Link Speed ndependent Specifications Sheet 1 of 2 Symbol Parameter Min Nom Max Unit Notes 0 999 nominal Ulavg Average UI size at G 1000 G GT s Where G 4 8 6 4 and so on 1 001 psec nominal Defined as the slope of 9 20 the rising or falling waveform as measured between 100mvV of the differential transmitter output for any data or clock Defined as 6 6 maX Zrx Low cM min Zrx tow pc LOW cM pc expressed in 96 over full range of Tx single ended voltage Tslew rise fall pin V nsec of AZTX LOW CM DC LOW CM DC Defined as 6 0 6 max Zrx Low cM min Zrx pc expressed in 96 over full range of Tx single ended voltage 96 of AZgx CM DC u LOW CM DC of UI over which the eye mask voltage and timing spec needs to be validated NyIN Ul Validation 1 000 000 Single ended DC 4k Q impedance to GND for either D or D of any data bit at Tx HIGH CM DC Si
61. SOR Hex characters Number 4Fh 0x30 50 0 49 81 51 51 0 4 52 0 54 82 52h 53h 0x33 83 53h 84 54h Substrate Revision Hex 2 bit substrate revision number 00b MSB Software ID Intel 2 Bits MSB 000000b Reserved Itanium Processor 6 Bits reserved LSB Intel Itanium 9300 Series Intel Itanium Processor 9300 Processor 9300 Series Series RESERVED Intel Reserved for future use for Intel 0x00 Intel Itanium Itanium Processor Itanium amp Processor 9500 Series Processor 9500 Series 9500 Series 85 55h Checksum Hex Add up by byte and take 2 s complement Part Numbers 86 56h Processor Part Number Seven 8 bit ASCII Processor Part Number PPN 80603LW Hex Characters 87 57h 56h 0x57 Ww 88 58h 57h 0 4 1 89 59h 58h 0x33 3 59h 0x30 0 90 5Ah 5Ah 0x36 6 91 5Bh 5Bh 0x30 0 92 5Ch 5Ch 0x38 8 Intel Itanium Processor 9300 Series and 9500 Series Datasheet 147 intel System Management Bus I nterface Table 6 1 Processor nformation ROM Data Sheet 5 of 6 Sec Offset Field Name Data Type Description Example 93 5Dh Processor Electronic 16 Digit Hex 64 bit identification number Signature Number may have padded zeros 94 5Eh 95 5Fh 96 60h 97 61h 98 62h 99 63h 100 64h 101 65h Base Core Freq 4 bcd digits Base Core Frequency
62. to maintain timing reference at either end of the link Intel QuickPath 5 0 CLKO Interconnect Interface Name Port Number Transmitter Differential ClockO Pair Polarity Positive Negative Example CSI4TPCLK represents port 5 clock transmit signal and positive bit of the differential pair Intel Itanium Processor 9300 Series and 9500 Series Datasheet 159 intel Signal Definitions Table 7 1 Signal Definitions for the Intel Itanium Processor 9300 Series and Intel Itanium 9500 Series Sheet 2 of 8 Name Type Description CSI 3 0 R P N Dat 19 0 These input data signals provide means of communication between two ports CSI 5 4 R P N Dat 9 0 one uni directional transfer link In The RX links are terminally ground referenced The ports 3 0 with 19 0 bit lanes can be configured as a full width link with all 20 active lanes a half width link with 10 active lanes or as a quarter width link with five active lanes Intel QuickPath 5 0 R P N DAT 19 0 Interconnect Interface Name Port Receiver Differential Lane Number Pair Number Polarity Positive Negative Example 514 0 represents port 5 Data lane 0 receive signal and positive bit of the differential pair CSI 3 0 T P N Dat 19 0 These output data signals provide means of communication between two ports CSI 5 4 T P
63. 0 1 1625 05 0 0 0 1 0 1 1 5500 25 1 0 0 1 0 1 1 1500 0 0 0 1 1 1 5375 26 1 0 0 1 1 0 1 1375 07 0 0 0 1 1 1 1 5250 27 1 0 0 1 1 1 1 1250 o 0 1 0 0 0 15125 28 1 0 1 0 0 1 1125 09 0 0 1 0 0 1 1 5000 29 1 0 1 0 0 1 11000 oa 0 1 0 1 0 1 4875 2 1 0 1 0 1 1 0875 0 0 1 0 1 1 1 4750 28 1 0 1 0 1 1 1 0750 0 1 1 0 1 4625 2c 1 0 1 1 0 0 1 0625 0 1 1 0 1 1 4500 2 0 1 1 0 1 1 0500 0 0 1 1 1 1 4375 2 1 0 1 1 1 1 0375 OF 0 0 1 1 1 1 1 4250 2 1 0 1 1 1 1 1 0250 10 0 1 0 0 0 0 14125 30 1 1 0 0 0 1 0125 11 0 1 0 0 0 1 1 4000 1 1 1 0 0 0 1 1 000 12 0 1 0 0 1 1 3875 2 1 1 0 0 1 0 9875 13 0 1 0 0 1 1 1 3750 1 1 0 0 1 1 0 9750 14 0 1 0 1 0 1 3625 1 1 0 1 0 0 9625 15 0 1 0 1 0 1 1 3500 35 1 1 0 1 0 1 0 9500 16 0 1 0 1 1 1 3375 36 1 1 0 1 1 0 9375 17 0 1 0 1 1 1 1 3250 7 1 1 0 1 1 1 0 9250 18 0 1 1 0 0 0 13125 38 1 1 1 0 0 0 9125 19 0 1 1 0 0 1 1 3000 39 1 1 1 0 0 1 0 9000 1 0 1 1 0 1 1 2870 1 1 1 0 1 0 8875 18 1 1 0 1 1 1 2750 1 1 1 0 1 1 0 8750 ic 1 1 1 0 0 1 2625 1 1 1 1 0 0 8625 ip 1 1 1 0 1 1 2500 1 1 1 1 0 1 0 8500 0 1 1 1 1 12375 1 1 1 1 1 0 8375 1F 0 1 1 1 1 1 1 2250 1 1 1 1 1 1 0 8250 2 9 RSVD Unused and DEBUG Pins A
64. 0 H1 FBD1SBODN 0 Differentia 11 PRBMODE_RDY_N G3 FBD1SBODN 1 Differentia 0 AF12 PRBMODE_REQST_N G4 FBD1SBODN 2 Differentia 10 PROCHOT_N 2 FBD1SBODN 3 Differentia 0 1 02 FBD1SBODN 4 Differentia ARQ PWRGOOD FBD1SBODN 5 Differentia V12 RESET N Power Other 6 FBD1SBODN 6 Differentia 0 AD12 RSVD 05 FBD1SBODN 7 Differentia 0 1 RSVD F7 FBD1SBODN 8 Differentia 0 A2 RSVD B4 FBD1SBODN 9 Differentia 0 A35 RSVD G6 FBD1SBODN 10 Differentia 7 RSVD H2 FBD1SBODP 0 Differentia 8 RSVD H3 FBD1SBODP 1 Differentia 0 A4 RSVD G5 FBD1SBODP 2 Differentia 0 AA11 RSVD F3 FBD1SBODP 3 Differentia 0 AA27 RSVD E2 FBD1SBODP 4 Differentia 0 AC12 RSVD D4 FBD1SBODP 5 Differentia 0 AC27 RSVD C6 FBD1SBODP 6 Differentia 28 RSVD Intel Itanium Processor 9300 Series and 9500 Series Datasheet 81 intel Table 3 1 Pin List by Pin Name Sheet 19 Table 3 1 Pin List by Pin Name Sheet 20 of 33 of 33 Pin Signal Pin Signal Number Pin Name Buffer Type Direction Number Pin Name Buffer Type Direction AC29 RSVD C37 RSVD AD27 RSVD D1 RSVD AD29 RSVD D38 RSVD AD30 RSVD Fl RSVD AE12 RSVD F38 RSVD AE27 RSVD Gl RSVD AE30 RSVD G38 RSVD AG21 RSVD H13 RSVD AH21 RSVD 20 RSVD AK12 RSVD L13
65. 0 605 0 610 0 615 0 620 0 625 0 630 0 835 0 840 0 845 0 850 0 855 0 860 0 865 0 870 0 875 0 880 0 885 0 890 0 895 0 900 0 905 0 910 0 915 0 920 0 925 0 930 0 935 0 940 0 945 DO 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 VID VID VID VID VID VID VID 7 Hex 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 76 77 78 79 7 7 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C VID V 0 355 0 360 0 365 0 370 0 375 0 380 0 385 0 390 0 395 0 400 0 405 0 410 0 415 0 420 0 425 0 430 0 435 0 635 0 640 0 645 0 650 0 655 0 660 0 665 0 670 0 675 0 680 0 685 0 690 0 695 0 700 0 705 0 710 0 715 0 720 0 725 0 730 0 735 0 740 0 745 VID 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 VID VID VID 4 D vi 7 Hex 16 17 18 19 1A 1B 1 10 20 21 22 23 24 25 26 4
66. 1 Processor Information ROM Data Sheet 6 of 6 Sec Offset Field Name Data Type Description Example Features 114 72h Processor Core Feature 8 digit Hex From CPUID Flag 0x4387FBFF Flags number 115 73h 4 72h OxFF 73h OxFB 116 74h 74h 0x87 117 75h 75h 0x43 Intel Itanium amp Processor 9300 Series 72h 0x00 RESERVED Reserved for future use Intel 73h 0x00 Intel Itanium amp Itanium Processor 9500 Series 74h 0x00 Processor 9500 Series 75h 0x00 Intel Itanium Processor 9500 Series 118 76h RESERVED Hex Reserved for future use 76h 0x00 119 77h 77h 0x00 120 78h Package Feature Flags Hex Bit 7 4 reserved 0 000 Bit 3 THERMALERT_N 78h OxOE 121 79h threshold values present 79h 0x00 Bit 2 SCRATCH EEPROM B present Bit 1 Core VID present Bit 0 reserved where a 1 indicates valid data 122 7Ah RESERVED Hex Reserved for future use 7Ah 0x00 123 7Bh Number of Devices in Hex Bits 7 4 Number Devices in 5 devices for Intel TAP Chain processor TAP chain Itanium Processor Bits 3 0 Reserved 9300 Series 0x50 9 devices for Intel amp Itanium Processor 9500 Series 0x90 124 7Ch Checksum Hex Add up by byte and take 2 s complement Other 125 7Dh RESERVED Hex Reserved for future use 7Dh 0x00 126 0 00 7 0 00 127 6 2 2 Scratch EEPROM Intel Itanium Processor 9300 Series and Intel Itanium9 Processor 9500 Series support a Scratch EEPROM section wh
67. 1 1 1 1 0 1 355 7 1 0 1 1 0 1 1 1 1 160 1 1 0 1 1 1 1 1 1 360 B8 1 0 1 1 1 0 0 0 1 165 1 1 1 0 0 0 0 0 1 365 9 1 0 1 1 1 0 0 1 1 170 1 1 1 1 0 0 0 0 1 1 370 1 0 1 1 1 0 1 0 1 175 2 1 1 1 0 0 0 1 0 1 375 1 0 1 1 1 0 1 1 1 180 1 1 1 0 0 0 1 1 1 380 1 0 1 1 1 1 0 0 1 185 4 1 1 1 0 0 1 0 0 1 385 BD 1 0 1 1 1 1 0 1 1 190 5 1 1 1 0 0 1 0 1 1 390 1 0 1 1 1 1 1 0 1 195 1 1 1 0 0 1 1 0 1 395 1 0 1 1 1 1 1 1 1 200 7 1 1 1 0 0 1 1 1 1 400 1 1 0 0 0 0 0 0 1 205 E8 1 1 1 0 1 0 0 0 1 405 1 1 1 0 0 0 0 0 1 1 210 9 1 1 1 0 1 0 0 1 1 410 2 1 1 0 0 0 0 1 0 1 215 1 1 1 0 1 0 1 0 1 415 C3 1 1 0 0 0 0 1 1 1 220 1 1 1 0 1 0 1 1 1 420 C4 1 1 0 0 0 1 0 0 1 225 1 1 1 0 1 1 0 0 1 425 5 1 1 0 0 0 1 0 1 1 230 1 1 1 0 1 1 0 1 1 430 1 1 1 0 1 1 1 0 1 435 7 1 1 1 1 0 1 1 1 1 480 1 1 1 0 1 1 1 1 1 440 F8 1 1 1 1 1 0 0 0 1 485 1 1 1 1 0 0 0 0 1 445 9 1 1 1 1 1 0 0 1 1 490 Fl 1 1 1 1 0 0 0 1 1 450 FA 1 1 1 1 1 0 1 0 1 495 2 1 1 1 1 0 0 1 0 1 455 1 1 1 1 1 0 1 1 1 500 1 1 1 1 0 0 1 1 1 460 1 1 1 1 1 1 0 0 1 505 1 1 1 1 0 1 0 0 1 465 FD 1 1 1 1 1 1 0 1 1 510 5 1 1 1 1 0 1 0 1 1 470 1 1 1 1 1 1 1 0 1 515 F6 1 1 1 1 0 1 1 0 1 475 1 1 1 1 1 1 1 1 1 520 2 8 Cache Voltage Identification Intel I tanium 62 Processor 9300 Series only The Cache Voltage Identification CVID value supplies the voltage for VCCCACHE the L3 cache voltag
68. 1 3500 43 1 0 1 0 0 1 1 0 7750 16 0 0 1 0 1 1 13375 44 1 0 0 0 1 0 7625 17 0 0 1 0 1 1 1 13250 45 1 0 0 0 1 0 7500 18 0 0 1 1 13125 46 1 0 0 0 1 1 0 0 7375 19 0 0 1 1 1 1 3000 47 1 0 0 0 1 1 1 0 7250 1 0 0 1 1 1 12870 48 1 0 0 1 0 0 7125 1B 0 0 1 1 1 1 12750 49 1 0 0 1 0 0 7000 1 0 0 1 1 1 12625 4 1 0 0 1 0 1 0 0 6875 1 0 0 1 1 1 1 12500 4B 1 0 0 1 0 1 1 0 6750 1 0 0 1 1 1 1 12375 4 1 0 0 1 1 0 6625 1 0 0 1 1 1 1 1 12250 4 1 0 0 1 1 0 6500 20 0 1 0 0 12125 4E 1 0 0 1 1 1 0 0 6375 21 0 1 0 0 o o i 1 2000 1 0 0 1 1 1 1 0 6250 22 0 1 0 0 1 11875 50 1 0 0 0 0 0 6125 23 0 1 0 0 1 1 11750 51 1 0 0 0 0 o 0 6000 24 0 1 0 0 1 11625 52 1 0 0 0 0 1 o 0 5875 58 Intel Processor 9300 Series and 9500 Series Datasheet Electrical Specifications intel Table 2 36 Intel Itanium Processor 9300 Series VCCCORE VID VCCCORE and VCCUNCORE and VID VCCUNCORE Voltage Identification Definition for Arara
69. 18 CSI4RNDAT 8 Differentia 016 514 1 Differentia 19 514 81 Differentia 017 CSI ARPDAT 7 Differentia 20 CSI2RNDAT 5 Differentia 018 vss Power Other E21 VSS Power Other D19 CSI4RNDAT 6 Differentia 22 512 41 Differentia 020 512 51 Differentia 23 CSI2RNDAT 4 Differentia 021 CSI2RNDATT 6 Differentia 24 512 31 Differentia 022 512 61 Differentia 25 CSI 2TPDAT 2 Differentia 023 vss Power Other E26 VSS Power Other D24 512 31 Differentia 27 Power Other D25 VSS Power Other E28 VSS Power Other D26 CSI2RNDAT 14 Differentia 29 512 61 Differential D27 CSI2RPDAT 14 Differentia E30 CSI OTPDAT 3 Differential 028 VSS Power Other E31 vss Power Other D29 512 6 Differentia 2 510 6 Differential 030 VSS Power Other E33 CSI OTPDAT 6 Differential 98 Intel Itanium Processor 9300 Series and 9500 Series Datasheet intel Pin Listing Table 3 2 Pin List by Pin Number Sheet Table 3 2 Pin List by Pin Number Sheet 21 of 32 22 of 32 No n Pin Name Direction mum Pin Name NEL m Direction E34 VCCIO Power Other F35 VCCIO Power Other E35 CSIORPDAT
70. 3Eh provides minimum operating memory transfer rate on the Intel Scalable Memory Interconnect Six 4 bit BCD digits are used to provide the minimum transfer rate in MT s Uncore Voltage Offset 3Fh 40h is the nominal processor Uncore voltage for this part rounded to the next thousandthin mV and reflected in BCD Example 1200 mV is stored as 3Fh 00h 40h 12h Uncore Voltage Tolerance Offset 41h and 42h contain the Uncore voltage tolerances high and low respectively These use a decimal to Hexadecimal conversion Example 20 mV tolerance would be saved as 14h Cache Data This section contains cache related data L3 Cache Size Offset 46h 47h is the L3 cache size field The field reflects the size of the level three cache in MBytes in bcd format Example The Intel Itanium Processor 9300 Series has 24 MB cache Thus offsets 46h amp 47h will contain 24 amp 00 respectively Cache Voltage Offset 48h 49h is the nominal processor cache voltage for the Intel Itanium Processor 9300 Series processor rounded to the next thousandth in mV and is reflected in bcd These fields are RESERVED for the Intel Itanium Processor 9500 Series Cache Voltage Tolerance Offset 4Ah and 4Bh contain the cache voltage tolerances high and low respectively These use a decimal to Hexadecimal conversion Example 20 mV tolerance would be saved as 14h These fields are RESERVED for the Intel Itanium Processo
71. 6 Differentia C8 FBD1SBOCN 4 Differentia 7 VSS Power Other C9 FBD1SBOCN 3 Differentia FBD1SBOCP 9 Differentia 10 VSS Power Other B9 FBD1SBOCN 9 Differentia 11 FBD1SBOCN 6 Differentia B10 FBD1SBOCN 5 Differentia 12 FBD1SBOCP 8 Differentia 11 FBD1SBOCP 6 Differentia 1 FBD1SBOCN 8 Differentia B12 VSS Power Other C14 Power Other B13 FBD1SBOCN 10 Differentia 15 VSS Power Other 14 VSS Power Other C16 CSI ARNDAT 2 Differentia 15 5148 0 Differentia 17 CSI ARNDAT 5 Differentia 16 CSI4RPDAT 2 Differentia 18 CSI4RPDAT 5 Differentia 17 VSS Power Other C19 5148 6 Differentia 18 CSI4RNDAT 4 Differentia 20 VSS Power Other B19 CSI4RPDAT 4 Differentia C21 CSI 2RNDAT 7 Differentia 20 CSI2RNDAT 8 Differentia C22 CSI 2RNDAT 9 Differentia 21 512 71 Differentia C23 CSI2RPDAT 9 Differentia B22 VSS Power Other C24 Power Other B23 CSI2RNDAT 10 Differentia C25 VSS Power Other B24 512 111 Differentia C26 CSI 2RNDAT 12 Differential 25 CSI2RNDAT 11 Differentia 27 CSI 2RNDAT 15 Differential 26 512 121 Differentia 28 5128 15 Differential Intel Itanium Processor 9300 Series and 9500 Series Datasheet 97 intel Pin Listing
72. CPU_PRESA_N NO CONNECT AW AY NO CONNECT NO CONNECT AY 1 2 3 4 Intel Itanium Processor 9300 Series 9500 Series Datasheet 117 intel 118 Intel Itanium Processor 9300 Series and 9500 Series Datasheet Mechanical Specifications tel 4 Figure 4 1 Intel Itanium Processor 9300 Series and 9500 Series Datasheet Mechanical Specifications The Intel Itanium Processor 9300 Series and 9500 Series are packaged in a FC LGA package that interfaces with the motherboard via an LGA1248 socket The package top side consists of lands that interface with a LGA connector for direct power delivery to the core cache and system interface The package also consists of an integrated heatsink spreader IHS which is attached to the package substrate and die and serves as the mating surface for the processor component thermal solutions such as a heatsink The bottom side of the package has 1248 lands a 38 x 38 mm pad array which interfaces with the LGA1248 socket Figure 4 1 shows a sketch of the processor package components and how they are assembled together The package components shown in Figure 4 1 include the following 1 Integrated Heat Spreader IHS Processor die Internal test pads for power delivery LGA lands for I O Decoupling and server management components 6 LGA lands for power delivery Processor Package Assembly Sketch B 5 4 Note This
73. Core Offset 65h 66h contain a bcd representation of core base frequency Example A processor with a core base frequency of 1600 MHz will have data as 00 16 starting at offset 65h Base Frequency Uncore Offset 67h 68h contain the uncore frequency for the Intel Itanium Processor 9500 Series Example a processor with an uncore frequency of 2 4 GHz will have data as 00 24 starting at offset 67h Thermal Reference Data Recommended Thermalert Hot Assertion Byte Offset 6Bh contains the thermalert threshold expressed as the number of degrees C below the PROCHOT N thermal throttling temperature in Hex format Intel Itanium Processor 9300 Series and 9500 Series Datasheet 155 m e te System Management Bus I nterface 6 4 8 2 6 4 8 3 6 4 8 4 6 4 9 6 4 9 1 6 4 9 2 Table 6 4 6 4 9 3 156 Recommended Thermalert Hot De assertion Hysteresis The de assertion threshold is expressed as the number of degrees C below the thermalert hot threshold value in Hex format Example reading offset 6Bh 00001010 6Ch 0000010 then programming the CSRs with these values means THERMALERT will be asserted when junction temperature rises to 10C below the PROCHOT N thermal throttle threshold and will remain asserted until the junction temperature drops to 12 below the PROCHOT N threshold Thermal Design Power Offset 6Dh is programmed with 2 Hex digits representing the max TDP of the part Examp
74. Differentia 20 CSI 3RPDAT 9 Differentia 1 CSI 2TPDAT 12 Differentia 22 CSI3RPDAT 10 Differentia 31 512 13 Differentia AT23 CSI 3RPDAT 11 Differentia T30 512 141 Differentia AV23 CSI 3RPDAT 12 Differentia 832 CSI 2TPDAT 15 Differentia 024 CSI 3RPDAT 13 Differentia T32 CSI 2TPDAT 16 Differentia 26 CSI 3RPDAT 14 Differentia 030 512 17 Differentia 27 CSI3RPDAT 15 Differentia 76 Intel Itanium Processor 9300 Series and 9500 Series Datasheet intel Pin Listing Table 3 1 Pin List by Pin Name Sheet 9 Table 3 1 Pin List by Pin Name Sheet 10 of 33 of 33 Direction LUN Pin Name 28 CSI3RPDAT 16 Differentia 2 CSI3TPDAT 14 Differentia 28 CSI3RPDAT 17 Differentia 2 513 15 Differentia 029 CSI3RPDAT 18 Differentia 2 CSI3TPDAT 16 Differentia AU31 CSI3RPDAT 19 Differentia CSI3TPDAT 17 Differentia 29 CSI3TNCLK Differentia 1 513 18 Differentia 120 5 01 Differentia CSI3TPDAT 19 Differentia 20 CSI3TNDAT 1 Differentia 18 CSI4RNCLK Differentia AM23 CSI3TNDAT 2
75. Differentia 815 514 01 Differentia 21 CSI3TNDAT 3 Differentia 015 CSI4RNDAT 1 Differentia 23 CSI3TNDAT 4 Differentia 16 CSI4RNDAT 2 Differentia 24 CSI3TNDAT 5 Differentia 17 CSI4RNDAT 3 Differentia 25 CSI3TNDAT 6 Differentia 18 CSI4RNDAT 4 Differentia 26 CSI3TNDAT 7 Differentia 17 CSI4RNDAT 5 Differentia 26 CSI3TNDAT 8 Differentia 019 CSI4RNDAT 6 Differentia AJ27 CSI3TNDAT 9 Differentia 17 CSI4RNDAT 7 Differentia 29 CSI3TNDAT 10 Differentia 18 CSI4RNDAT 8 Differentia 30 CSI3TNDAT 11 Differentia 17 CSI4RNDAT 9 Differentia 1 CSI3TNDAT 12 Differentia 18 514 Differentia CSI3TNDAT 13 Differentia 15 CSI4RPDAT O Differentia 1 CSI3TNDAT 14 Differentia 016 CSI 4RPDATT 1 Differentia AD32 CSI3TNDAT 15 Differentia B16 514 21 Differentia 1 CSI3TNDAT 16 Differentia 18 514 31 Differentia CSI3TNDAT 17 Differentia 19 514 41 Differentia 1 CSI3TNDAT 18 Differentia 18 CSI4RPDAT 5 Differentia 2 CSI3TNDAT 19 Differentia 19 514 61 Differentia 28 CSI 3TPCLK Differentia 017 514 71 Differentia 20 CSI3TPDAT O Differentia 19 514 81 Differentia 21 CSI 3TPDAT 1 Differentia 18 514 91 Different
76. ERRAT A 157 7 Signal Definitions AR XR ERISQUE NE 159 4 Intel Itanium Processor 9300 Series and 9500 Series Datasheet Figures 1 1 NNNNNNNNNNE FUOONOUBWNFWYDN 2 18 2 19 2 20 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 10 5 1 5 2 6 1 Intel Itanium Intel Itanium Processor 9300 Series Processor Block 16 Intel Itanium Processor 9500 Series Processor Block 17 Intel Itanium Processor 9500 Series Firmware 18 Active ODT for a Differential Link 23 Single ended Maximum and Minimum Levels Vcross 5 27 Veross Definition Rr HO ER ERE EK ERE ERROR UU PX RT RR UC n 27 Differential Edge Rate 1 000 memes 28 TStable 5 2222 2 1 2 2 0 4 1 nennen nnne nn 28 TX Equalization Diagratn e doa 31 TX ReturM LOSS e Pr UD 32 REtUMMLOSS BRUM DENN KT Kus 32 Processor Load Current versus 42 VCCUNCORE Static and Transient Tolerance for Intel
77. F29 VSS Power Other K25 VSS Power Other F34 VSS Power Other K26 vss Power Other F4 VSS Power Other K3 VSS Power Other F5 VSS Power Other K31 VSS Power Other F9 VSS Power Other K36 VSS Power Other G12 VSS Power Other K6 VSS Power Other G14 VSS Power Other L14 VSS Power Other Intel Itanium Processor 9300 Series and 9500 Series Datasheet 87 intel Pin Listing Table 3 1 Pin List by Pin Name Sheet 31 Table 3 1 Pin List by Pin Name Sheet 32 of 33 of 33 pone Direction ie Pin Name Direction L16 VSS Power Other R6 vss Power Other L17 VSS Power Other T29 VSS Power Other L19 VSS Power Other T34 VSS Power Other L23 VSS Power Other T4 VSS Power Other L24 VSS Power Other T9 VSS Power Other L25 VSS Power Other U12 vss Power Other L26 VSS Power Other U2 VSS Power Other L29 VSS Power Other U27 VSS Power Other L34 VSS Power Other U3 vss Power Other L35 VSS Power Other U32 vss Power Other L4 VSS Power Other U35 vss Power Other 19 VSS Power Other U37 VSS Power Other M12 VSS Power Other U7 vss Power Other M16 vss Power Other V10 vss Power Other M17 vss Power Other v30 VSS Power Other M19 VSS Power Other V35 VSS Power Other M2 VSS Power Other v5 VSS Power Other M22 VSS Power Other Wil VSS Power Other M24 VSS Power Other W28 VSS Power Other M25 vss Power Other w3 VSS Power Other M27 v
78. Pin List by Pin Name Sheet 16 of 33 of 33 Tu Direction T Pin Name Direction AD4 FBDOSBOBP 5 Differentia 10 FBDINBICP 11 Differentia FBDOSBOBP 6 Differentia 111 FBDINBI CP 12 Differentia 5 FBDOSBOBP 7 Differentia 10 FBD1NBICP 13 Differentia FBDOSBOBP 8 Differentia 9 FBD1NBICP 14 Differentia 7 FBDOSBOBP 9 Differentia 6 1 1 0 Differentia YA FBDOSBOBP 10 Differentia 6 FBDINBIDN 1 Differentia R2 FBDOSBOCLKANO Differentia W7 FBDINBIDN 2 Differentia R3 FBDOSBOCLKAPO Differentia W6 FBDINBIDN 3 Differentia 5 FBDOSBOCLKBNO Differentia 05 FBD1NBI DN 4 Differentia 5 FBDOSBOCLKBPO Differentia T7 FBD1NBIDN 5 Differentia 18 FBD1NBICLKCNO Differentia 6 FBD1NBIDN 6 Differentia 8 FBD1NBICLKCPO Differentia 5 FBD1NBIDN 7 Differentia R7 FBD1NBICLKDNO Differentia N8 FBD1NBI DN 8 Differentia 7 FBD1NBICLKDPO Differentia K4 FBD1NBI DN 9 Differentia v9 FBD1NBICN 0 Differentia 17 FBD1NBIDN 10 Differentia V7 FBD1NBICN 1 Differentia 7 FBD1NBIDN 11 Differentia FBDINBICN 2 Differentia 5 FBDINBIDN 12 Differentia 010 FBD1NBICN 3 Differentia R5 FBD1NBIDN 13 Differentia R9 FBD1NBICN 4 Differentia AC8 FBD1NBIDN 14 Differentia 9 FBD1NBICN 5 Differentia 5 FBD1NBIDP 0 Differentia K9 FBD1NBICN 6 Differentia 7 FBD1NBIDP 1 Differentia j
79. Power Other 19 FBD1NBICP 10 Differential H8 FBDINBICP 9 Differential 1 J10 FBDINBICP 7 Differential 9 FBD1NBICN 10 Differentia J11 FBDINBICN 7 Differential 10 VSS Power Other J12 ERROR 1 _N 0 FBDINBICP 8 Differential 1 J13 vss Power Other H12 ERROR 0 N 0 14 CSI 4TNDAT 3 Differentia H13 RSVD 115 CSI4TPDAT 2 Differentia 14 CSIATPDAT 3 Differential 16 CSI4TNDAT 5 Differentia 15 VSS Power Other J17 514 61 Differentia 16 CSI4TPDAT 5 Differential 18 VSS Power Other H17 VCCIO Power Other 19 CSI 4TPDAT 8 Differentia 18 CSI4RNCLK Differential 120 RSVD H19 Power Other 121 512 01 Differentia 20 VSS Power Other 122 5128 0 Differentia 21 5128 1 Differential 123 VSS Power Other H22 Power Other 124 VSS Power Other H23 CSI2TNDAT O Differential J25 vss Power Other H24 VCCIO Power Other 26 CSI 2TNDAT 7 Differentia 25 VSS Power Other 127 CSI 2TPDAT 7 Differentia 26 512 41 Differentia 28 VSS Power Other H27 CSI2TNDAT 9 Differentia 129 CSI2TPCLK Differentia H28 CSI2TPDAT 9 Differentia 130 CSIOTPDAT 0 Differentia 29 CSI2TNCLK Differentia 131 CSIOTNDAT 1 Differentia H30 VSS Power Other 32 CSIOTPDAT 4 Differentia H31 CSIOTPDAT 1 Differentia 133 VSS Power Other H32 Power Other 134
80. Requirements for Intel Itanium Processor 9500 Series 20 gt 1 gt ae lt gt 0s VCCA i 0us gt VROUTPUT ENABLEO gt 100 gt 1ms All inputs low prior to VCCIO 9l 4 amp 1000ms VOCSTBY33 3 3V i PROCTYPE Pulled to 3 3VSM platform VR PROCTYPE Pulea to Ararat intemal 3 3V rail on Ararat itself SYSCLK 133 2 1212401 svids change to hfuse values Vstrap Vhfuse VOCUNCORE 09 gp VCCVUNCOREREADY m Svid vcocore svi anges cha may change to viuse y response to y V vfuse V hfuse l 1 4 Y Pwrgd reset can change core VR set VR_READY lt 200ms 2 4 gt 05 gt 4 gt 15 gt Intel Itanium Processor 9300 Series 9500 Series Datasheet 67 intel 2 11 3 Table 2 39 Power up Voltage Sequence Timing Requirements 2 12 68 Electrical Specifications Power up Voltage Sequence Timing Requirements Processor 9500 Series Parameter Min Max Unit VCC33 SM stable high to VCCA delay 20 to VCCIO delay time 0 us VCCI O to PWRGOOD high delay time 1000 ms VCCIO stable high to SYSCLK 20 us SYSCLK valid before VROUTPUTENABLEO high 20 us VCCIO stable befo
81. SKTID TIMING socer aon recor rea petente eere ce RD Re DNIT 70 Pin List by Pity d seni terc e eU 73 Pin List by xr pete od 89 Top Side J1 Connector Two Dimensional Table Intel Itanium Processor 9300 105 Top Side J1 Connector Two Dimensional Table Intel Itanium Processor 9500 0 106 Top Side J2 Connector Two Dimensional Table Intel Itanium Processor 9300 00 108 Top Side J2 Connector Two Dimensional Table Intel Itanium Processor 9500 0 0 044 11 4 110 Top Side J3 Connector Two Dimensional Table Intel Itanium Processor 9300 Series eene 111 Top Side J3 Connector Two Dimensional Table Intel Itanium Processor 9500 Series eene 113 Top Side J4 Connector Two Dimensional Table Intel Itanium Processor 9300 5 5 114 Top Side J4 Connector Two Dimensional Table Intel Itanium Processor 9500 Series eene 116 Processor Loading Specifications 2 129 Package Handling 1 1 mmm 129 Processor Package Insertion 130 Package
82. Sensor DTS readout and use the Value as the threshold at which active system thermal management must be engaged This will ensure reliable processor operation over its expected life Note that no internal response is generated by the processor at Customers can utilize THERMALERT N as an interrupt to program an alternative temperature monitoring threshold value to provide margin in their cooling solution design See Intel Itanium9 Processor 9300 Series Thermal Mechanical Design Guide for additional guidance on implementing a compliant processor thermal solution Thermal Warning THERMWARN is the temperature beyond which data integrity is not guaranteed and PROCHOT N remains asserted Thermal Trip The Intel Itanium Processor 9300 Series nd Intel Itanium Processor 9500 Series protects itself from catastrophic overheating by use of an internal thermal sensor The sensor trip point is set well above the maximum operating temperature to ensure that there are no false trips The Intel Itanium Processor 9300 Series and Intel Itanium9 Processor 9500 Series will issue THERMTRIP and stop all execution when the junction temperature exceeds a safe operating level At this point THERMTRIP N is asserted If THERMTRIP N is asserted processor voltages VCCCORE VCCUNCORE AND VCCCACHE must be removed within the timeframe defined in Table 2 36 Data will be lost or corrupt and transaction time outs will oc
83. Series 9500 Series Datasheet 65 intel 221141 2 17 Electrical Specifications Supported Power up Voltage Sequence for the I ntel Itanium Processor 9300 Series Supported Power up Voltage Sequence Timing Requirements for the Intel Itanium Processor 9300 Series PROCTYPE 4 pulled to VSS on package for Intel Itanium processor 9300 series VCC33_SM for other products 0us cx VecArarat 12V 1 VR PROCTYPE 1 0 pulled to VSS on package for Intel Itanium processor 9300 series VCC33_SM for other products gt gt 05 4 SYSCLK 133 2 gt gt 005 46 gt 1us a Uncore Vid re and Cache Vids Core Vid may VROUTPUT_ENABLEO change to on die may change to viuse values change in respon fuse based value to power manag VCCUNCORE VID Value t Value VID Value VRPWRGD PWRGOOD RESET_N T Nominal value refer to Ararat Spec for actual number 66 Intel Itanium Processor 9300 Series and 9500 Series Datasheet Electrical Specifications 2 11 2 Itanium Processor 9500 Series Supported Power up Voltage Sequence for the Intel Figure 2 18 Supported Power up Sequence Timing
84. Series Intel Itanium Processor 9300 Series and 9500 Series Datasheet intel Intel Itanium Processor 9500 Series Intel Itanium Processor Eight Core 2 53 GHz with 32 MB LLC Cache 9560 Intel I tanium Processor Four Core 2 40 GHz with 32 MB LLC Cache 9550 Intel Itanium Processor Eight Core 2 13 GHz with 24 MB LLC Cache 9540 Intel tanium Processor Four Core 1 73 GHz with 20 MB LLC Cache 9520 Product Features m Eight Core Eight complete 64 bit processing cores on one processor with two threads per core Each core provides in order issue and execution of up to twelve instructions per cycle ncludes dynamic domain partitioning and static hard partitioning m Advanced EPIC Explicitly Parallel Instruction Computing Architecture for current and future requirements high end enterprise and technical workloads Provide a variety of advanced implementations of parallelism predication and speculation ng superior Instruction Level Parallelism ILP Intel Hyper Threading Technology Dual Domain Multithreading with independent front end and back end thread domains providing hardware support for 2 threads per core Support for Intel Itanium Processor New Instructions m Wide parallel hardware based on Intel Itanium architecture for high performance ntegrated on die LLC cache of up to 32MB cache hints for and LLC caches for reduced m
85. TCK Test Clock TCK provides the clock input for the processor TAP TDI TDO Test Data In TDI transfers serial test data into the processor TDI provides the serial input needed for JTAG specification support Test Data Out TDO transfers serial test data out of the processor TDO provides the serial output needed for J TAG specification support TESTHI 1 This pin must be tied to VCCIO using a 50 ohm resistor TESTHI 2 This pin must be tied to VCCIO using a 50 ohm resistor TESTHI 4 This pin must be tied to VCCIO using a 5k ohm resistor THERMALERT N Thermal Alert THERMALERT_N is an output signal and is asserted when the on die thermal sensors readings exceed a pre programmed threshold The processor protects itself from catastrophic overheating by use of an internal thermal sensor Thermal Trip will activate at a temperature that is significantly above the maximum case temperature TCASE to ensure that there are no false trips Once activated the processor will stop all execution and the signal remains latched until RESET goes active There is no hysteresis built into the thermal sensor itself as long as the die temperature drops below the trip level a RESET N pulse will reset the processor and execution will continue If the temperature has not dropped below the trip level the processor will continue to drive THERMTRIP N and remain stopped TMS Test Mod
86. VSS Power Other AN19 CSI3RPDAT 4 Differentia 18 CSI3RPDAT O Differentia 20 VSS Power Other AM19 VCCIO Power Other AN21 CSI 31 Differentia 20 CSI3TNDAT 1 Differentia AN22 CSI 3TPDAT 4 Differentia 21 CSI 3TPDAT 1 Differentia AN23 CSI 3TNDAT 4 Differentia 22 VSS Power Other AN24 CSI3TPDAT 5 Differentia 23 CSI3TNDAT 2 Differentia AN25 VSS Power Other AM24 CSI3TNDAT 5 Differentia 26 CSI 3TNDAT 7 Differentia 25 CSI 3TPDAT 8 Differentia 27 CSI1TPDAT 1 Differentia 26 CSI3TNDAT 8 Differentia 28 CSI1TNDAT 1 Differentia 27 VSS Power Other AN29 CSI ITNDAT 3 Differentia 28 CSI1TPDAT 2 Differentia VSS Power Other AM29 VCCIO Power Other AN31 511 81 Differentia CSI1TPDAT 5 Differentia AN32 CSI1TNDAT 6 Differentia 1 CSI1TNDAT 8 Differentia AN33 CSI1TPDAT 7 Differentia 2 vss Power Other AN34 CSI ITNDAT 7 Differentia VCCIO Power Other AN35 vss Power Other AM34 VSS Power Other AN36 CSI IRPDAT 7 Differentia 5 CSI1RPDAT 8 Differential AN37 CSI1RNDAT 7 Differentia 6 511 81 Differential AN38 RSVD AM37 VSS Power Other 1 AM38 RSVD AP2 FBDONBIAP 7 Differentia 1 VR_FAN_N vss Power Other AN2 FBDONBIAN 7 Differential FBDONBIAN 6 Differentia FBDONBIAN 8 Differential 5 V
87. address data the _N notation implies that the signal is inverted For example D 3 0 refers to a Hex A D 3 0 LHLH also refers to a Hex A H High logic level L Low logic level A signal name has all capitalized letters for example VCTERM A symbol referring to a voltage level current level or a time value carries a plain subscript for example Vccio or a capitalized abbreviated subscript for example TCO State of Data The data contained in this document is subject to change It is the best information that Intel is able to provide at the publication date of this document Reference Documents The reader of this specification should also be familiar with material and concepts presented in the following documents Document Name Intel Itanium Processor 9300 Series and 9500 Series Specification Update Intel Itanium Architecture Software Developer s Manual Volume 1 Application Architecture Intel Itanium Architecture Software Developer s Manual Volume 2 System Architecture Intel tanium Architecture Software Developer s Manual Volume 3 Instruction Set Reference Intel Itanium Architecture Software Developer s Manual Volume 4 1 32 Instruction Set Reference Intel Itanium 9300 Series Processor Reference Manual for Software Development and Optimization Intel Itanium 9500 Series Processor Reference Manual for Software
88. at That is when DT readout is equal to zero Tcase Cannot be used as proxy for power dissipation due to the variation in work load imbalances between cores TDPmax is 170W or 130W depending on the SKU Figure 5 2 contains dimensions for the thermocouple location on the Intel Itanium Processor 9300 Series Intel Itanium9 Processor 9500 Series This location must be used for the placement of a thermocouple for case temperature measurement Intel Itanium Processor 9300 Series and 9500 Series Datasheet 139 intel Figure 5 2 5 3 140 Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series Package Thermocouple Location Substrate Substrate Thermocouple Attach Point Not to scale Note Refer to the Package Mechanical Drawings in Chapter 4 Storage Conditions Specifications Environmental Storage Condition limits define the temperature and relative humidity limits to which the device is exposed to while being stored The specified storage conditions are for component level prior to installation onto board Non operating storage condition limits for the co
89. buffer type indicates which signaling technology and specifications apply to the signals Signal Groups Sheet 1 of 3 Signal Group Buffer Type Signals 1 2 3 Differential System Reference Clock Differential CMOS In Differential Pair SYSCLK SYSCLK_N SYSUTST_REFCLK_N SYSUTST_REFCLK Intel QuickPath I nterconnect Signal Groups Differentia Input CSI 3 0 RIP N Dat 19 0 CSI 5 4 R P N 9 0 CSI 5 Differentia Output CSI 3 0 T P N Dat 19 0 CSI 5 4 T P N 9 0 CSI 5 0 T P N CLK FB DI MM Signals Differentia Input FBDONBICLK A B P N O FBDINBICLK C D P N O Differentia Output FBDOSBOCLK A B P N O FBDISBOCLK C D P N O Differentia Input FBDONBI A B P N 13 0 FBDINBI C D P N 13 0 Differentia Output FBDOSBO A B P N 10 0 FBD1SBO C D P N 10 0 TAP Intel Itanium Processor 9300 Series 9500 Series Datasheet Electrical Specifications Table 2 2 Signal Groups Sheet 2 of 3 Signal Group Buffer Type Signals 1 2 3 Single ended CMOS Inputs TCK TDI TMS TRST_N GTL Open Drain Output TDO SMBus Single ended GTL I O SMBCLK SMBDAT SPD Bus Single ended GTL I O SPDCLK SPDDAT Setup Single ended GTL Input BOOTMODE 1 0 SKTID 2 0 System Management Single ended CMOS Input LRGSCLSYS Flash ROM Port Single ended GTL open Drain Inpu
90. can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD The PWRGOOD signal must be supplied to the processor This signal is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation RESET_N Asserting the RESET_N signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents BOOTMODE 0 1 signals are sampled during all RESET_N assertions for selecting appropriate BOOTMODE RSVD These pins are reserved and must be left unconnected SKTID 2 0 Socket ID strapping pins To pull any of these inputs high they should be strapped to VCCIO and to pull them low they should be strapped to VSS SKTID 2 0 partially determine the node address SMBCLK The SMBus Clock SMBCLK signal is an input clock to the system management logic which is required for operation of the system management features of the Intel Itanium Processor 9300 Series and Intel Itanium9 9500 Series processors This clock is driven by the SMBus controller and is asynchronous to other clocks the processor This is an open drain signal Intel Itanium Processor 9300 Series and Intel Itanium 9500 Series are Slave only SMBDAT 1 0 The SMBus Data SMBDAT signal is the data signal for the SMBus This signal provides the single bit mec
91. drawing is not to scale and is for reference only Processor power delivery and thermal solutions and the socket are not shown 119 intel Package Mechanical Drawing The package mechanical drawings are shown in Figure 4 2 Figure 4 3 Figure 4 4 and Figure 4 5 The package mechanical drawings for the Intel Itanium amp Processor 9500 Series processor are shown in Figure 4 6 Figure 4 7 Figure 4 8 and Figure 4 9 The drawings include dimensions necessary to design a thermal solution for the processor These dimensions will include 120 1 2 3 4 5 Mechanical Specifications Package reference with tolerances total height length width and so on 5 parallelism and tilt Land dimensions Top side and back side component keepout dimensions Reference datums All drawing dimensions are in mm Intel Itanium Processor 9300 Series and 9500 Series Datasheet Mechanical Specifications 4 2 Intel Itanium Processor 9300 Series Figure 4 2 Intel I tanium Processor 9300 Series Package Drawing Sheet 1 of 4 010101 mun EMTS DRAWING
92. following pieces of data Sample or Production field to identify a pre production sample or a production unit Required voltage regulator field VCCA and VCCIO voltage specs The sample or production field is a two bit LSB aligned value 0x00 indicates unlocked PI ROM section This is the case in most samples 0x01 indicates a locked PIROM section Some samples and all production parts will be locked The required voltage regulator field for the Intel Itanium Processor 9300 Series is 0x00 The required voltage regulator field for the Intel Itanium Processor 9500 Series is 0 01 Processor Core Data This section contains silicon related data relevant to the processor cores CPUID Offset 22h 25h contains a copy of the results in EAX 31 0 from Function 1 of the CPUID instruction Boost Core Frequency Offset 26h 27h provides the boost core frequency for the processor The frequency should equate to the markings on the processor even if the parts are not limited or locked to the intended speed Format of this field is in MHz rounded to a whole number and encoded as four 4 bit bcd digits Offset 26h contains the core count for the Intel tanium Processor 9500 Series while offset 27h is RESERVED for the Intel Itanium Processor 9500 Series Example For the Intel Itanium processor 9300 series the 1733 GHz processor will have a value of 1733 For the Intel Itanium Processor 9500 Series eight core SKU 0x26 wi
93. intel Introduction E Intel Itanium Processor 9300 Intel Itanium Processor 9500 escription i Series Series Memory patrolling Supported Supported Memory migration Supported Supported Support for mixing of x4 and x8 on the Not Supported Supported same DDR channel Online Offline CPU OS assisted Supported Supported Online Offline Memory OS assisted Supported Supported Online Offline 1 0 Hub Supported Supported Thermal Design Power TDP SKUs 130W 155W 185W 130W and 170W Notes 1 OEM responsible for specifying platform specific retraining interval 2 Electrical isolation only no physical add remove supported 3 Assume spare is installed 1 4 1 5 1 6 20 Processor Abstraction Layer The Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series require implementation specific Processor Abstraction Layer PAL firmware PAL firmware supports processor initialization error recovery and other functionality It provides a consistent interface to system firmware and operating systems across processor hardware implementations The Intel Itanium Architecture Software Developer s Manual Volume 2 System Architecture describes PAL Platforms must provide access to the firmware address space and PAL at reset to allow the processors to initialize The System Abstraction Layer SAL firmware contains platform specific firmware to initialize the platform b
94. of PIROM Ox6B 0x00 if not Address containing Processor Thermal present Reference Data 10 Feature Data Address Hex Byte pointer Pointer to the section of 0x72 0x00 if not containing Processor Features present Data 11 OBh Other Data Address Hex Byte pointer Pointer to the section of 0 70 0x00 if not containing Processor Other Data present 12 OCh RESERVED Hex Reserved for future use OCh 0x00 13 0 00 14 Checksum Hex Add up by byte and take 2 s complement Processor 21 15h Sample Production Hex Identifies sample parts separately 0x01 Production from production parts 0x00 Sample 22 16h Voltage Regulator Type Hex Identifies Ararat type required 0x00 for Intel Required Itanium amp Processor 9300 Series 0x01 for Intel amp Itanium Processor 9500 Series 23 17h VCCA 4 binary coded Processor Analog Voltage Supply 1 800V 1800 decimal bcd in four 4 bit Hex digits in mV 17h 00 24 18h digits 144 Intel Itanium Processor 9300 Series 9500 Series Datasheet System Management Bus 1 intel Table 6 1 Processor Information ROM Data Sheet 2 of 6 Sec Offset Field Name Data Type Description Example 25 19h VCCA Voltage Tolerance 2 Hex digits Total tolerance DC AC in mV 61 3Dh High 26 1Ah VCCA Voltage Tolerance 2 Hex digits Total toleranc
95. of the document February 2010 8 8 Intel Itanium Processor 9300 Series and 9500 Series Datasheet Introduction 1 1 1 intel Introduction Overview The Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series employ Explicitly Parallel Instruction Computing EPIC design concepts for a tighter coupling between hardware and software In this design style the interface between hardware and software is designed to enable the software to exploit all available compile time information and efficiently deliver this information to the hardware It addresses several fundamental performance bottlenecks in modern computers such as memory latency memory address disambiguation and control flow dependencies The EPIC constructs provide powerful architectural semantics and enable the software to make global optimizations across a large scheduling scope thereby exposing available Instruction Level Parallelism ILP to the hardware The hardware takes advantage of this enhanced ILP and provides abundant execution resources Additionally it focuses on dynamic run time optimizations to enable the compiled code schedule to flow at high throughput This strategy increases the synergy between hardware and software and leads to greater overall performance The Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series system interface with its 4 full width and 2 half width Intel QuickPath Interc
96. output voltage state and the low output voltage state for that pin 5 HVM guaranteed error free value for stressed 1010 signaling across PVT Link BER is the dominant spec of which eye dimensions are only one factor and improving another factor could compensate for eye height or width 6 Figure 2 8 Figure 2 6 TX Equalization Diagram C4 C2 C4 C2 Vpost 1 C2 Vsust 1 2 C2 1 sum of abs value of other coeficents Vpost Vsust C 4 Co 1 Peaking Vpost Vsust Example A 500mV C 0 035 0 685 0 28 C2 0 Vpre 0 500 0 035 0 685 0 28 0 5 0 44 220mV Vpost 0 500 0 035 0 685 0 28 0 5 0 93 465mV Vsust 0 500 0 035 0 685 0 28 0 5 0 37 185 TXEQ BOOST 20log Vpost Vsust 20109 465 185 8dB Peaking 465 185 251 Intel Itanium Processor 9300 Series and 9500 Series Datasheet 31 intel Figure 2 7 TX Return Loss 0058 POL2 TX data 50ohm 80 5 1 1 0 5 1 1 diabled 50oh disabled 50oh POL2 TXdata POL2 TXdata dB diff RL TDR iff_RL_TDR dB d freq GHz Figure 2 8 RX Return Loss 2 4 2 32 TDOP 0058 POL2 RXDATA 50ohm POL2_RXdata_50ohm_80C S 1 1
97. two dimensional table of the Intel Itanium Processor 9300 Series package top side J 4 connector Table 3 9 Top Side J 4 Connector Two Dimensional Table Intel Itanium Processor 9300 Series Sheet 1 of 2 1 2 3 4 VCCCACHEIO VID_VCCCACHE 1 A 5 VID_VCCCACHE 2 B NO CONNECT 4 VID_VCCCACHE 3 VSS F G vss G H VCCCORE H J VCCCORE J 1 2 3 4 114 Intel Itanium Processor 9300 Series 9500 Series Datasheet Pin Listing Table 3 9 Top Side J4 Connector Two Dimensional Table Intel Itanium Processor 9300 Series Sheet 2 of 2 intel 1 2 3 4 K VSS K L VSS L M VCCCORE M N VCCCORE N P VSS P R VSS R T VCCUNCORE T U VCCUNCORE U vss vss w Y VCCUNCORE Y AA VCCUNCORE AA AB VCCUNCORE AB AC VSS AC AD VSS AD AE VCCUNCORE AE AF VCCUNCORE AF AG VSS AG AH VSS AH AJ VCCCORE AJ AK VCCCORE AK AL VSS AL AM VSS AM AN VCCCORE AN AP VCCCORE AP AR VSS AR AT VSS AT AU Reserved AU AV Reserved Reserved AV NO CONNECT NO CONNECT AW Reserved CPU_PRESA_N AW AY Reserved Reserved AY 1 2 3 4 Intel Itanium Processor 9300 Series
98. will resume including the Intel Itanium Processor 9300 Series being allowed to operate at boost frequency if appropriate If gt the Intel Itanium Processor 9500 Series thermal management system will reduce the activity factor maximum limit After a delay if the processor temperature is below threshold normal operation will resume and the previous Intel Itanium Processor 9500 Series activity factor maximum limit will be restored b gt and the Intel Itanium Processor 9300 Series is already at or below base voltage and frequency then the thermal management system will assert PROCHOT N and the processor will enter Single Issue Mode SIM and transition to the voltage and frequency of the lowest supported P state Intel Itanium Processor 9300 Series and 9500 Series Datasheet 135 m e tel Thermal Specifications 5 1 2 2 5 1 3 136 A Corrected Machine Check Interrupt is issued when processor enters and exits SIM If T gt the Intel Itanium Processor 9500 Series the activity factor maximum limit is already reduced then the thermal management system will assert PROCHOT N and the processor will enter Single Issue Mode SIM and transition to the lowest P state The Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series will remain in this low power mode until the temperature decreases and dro
99. 0 Series Sheet 1 of 2 1 2 3 4 A Reserved Reserved A B VR_FAN_N NO CONNECT Reserved B NO CONNECT Reserved VRPWRGD VCCCORE E F vss F G VSS G H VCCCORE H J VCCCORE J K VSS K L vss L M VCCCORE M L qp Intel Itanium Processor 9300 Series 9500 Series Datasheet 111 intel Table 3 7 5 J3 Connector Two Dimensional Table Intel Itanium Processor 9300 Series Sheet 2 of 2 1 2 3 4 N VCCCORE N P VSS P R VSS R T VCCCACHE T U VCCCACHE U vss VSS vss AC AD ME AD AE VCCCACHE AE AF VCCCACHE AF AG vss AG AH VSS AH AJ VCCCORE AJ AK VCCCORE AK AL VSS AL AM VSSVSS AM AN VCCCORE AN AP VCCCORE AP AR VSS AR AT VSS AT AU Reserved Reserved AU AV CPU_PRESB_N VSSUNCORESENSE AV NO CONNECT NO CONNECT AW VID VCCUNCOREI O VCCUNCORESENSE AW AY Reserved Reserved AY 1 2 3 4 112 Intel Itanium Processor 9300 Series 9500 Series Datasheet Pin Listing intel 3 2 3 2 Top Side J Connector Two Dimensional Table for the ntel Itanium Processor 9500 Series Table 3 8 is a two dimensional table of the Intel Itanium Processor 9
100. 0 mV measurement window is centered on the differential zero crossing See Figure 2 4 5 Measured at crossing point where the instantaneous voltage value of the rising edge SYSCLK equals the falling edge SYSCLK N See Figure 2 2 6 Refers to the total variation from the lowest crossing point to the highest regardless of which edge is crossing Refers to all crossing points for this measurement See Figure 2 3 7 Defined as the total variation of all crossing voltages of Rising SYSCLK and falling SYSCLK N This is the maximum allowed variance in Vcross for any particular system See Figure 2 2 8 Defined as the maximum instantaneous voltage including overshoot See Figure 2 2 9 Defined as the minimum instantaneous voltage including undershoot See Figure 2 2 10 Tsiapie is the time the differential clock must maintain a minimum 150 mV differential voltage after rising falling edges before it is allowed to droop back into the 100 mV range See Figure 2 5 Figure 2 2 Single ended Maximum and Minimum Levels Veross Levels Ving FAAS Vo REFCLK V cross max 550 mV Voss MIN 250 mV REFCLK Figure 2 3 Vcross delta Definition REFCLK V 140 mv crossdelta REFCLK Intel Itanium Processor 9300 Series and 9500 Series Datasheet 27 inte Figure 2 4 Differential Edge Rate Definition E Rnercik di
101. 00 Series 46 2 22 VCCCACHE Static and Transient Tolerance for Intel Itanium Processor 9300 eene 48 2 23 VCCUNCORE Static and Transient Tolerance for the Intel Itanium Processor 9500 Series eene 49 2 24 VCCCORE Static and Transient Tolerance for the Intel tanium Processor 9500 Series 51 2 25 Overshoot and Undershoot Specifications For Differential Intel QuickPath Interconnect and Intel SMI and Single Ended Signals for the Intel Itanium Processor 9300 Series eene 52 2 26 Overshoot and Undershoot Specifications For Differential Intel QuickPath Interconnect and Intel SMI and Single Ended Signals for the Intel Itanium Processor 9500 53 2 27 Voltage Regulator Signal Group DC 5 nn nnn 53 2 28 Voltage Regulator Control Group DC ee 54 2 29 and System Management Group DC Specifications sss 54 2 30 Error FLASHROM Power Up Setup and Thermal Group DC Specifications 54 2 31 VID VCCCORE 6 0 VID VCCUNCORE 6 0 and VID VCCCACHE 5 0 DC Specifications for the Intel Itanium Processor 9300 55 2 32 SVID Group DC Specifications for the Intel Itanium Processor 9500 Series 55 2 33 SMBus and Serial Presence Detect SPD B
102. 00 Series Datasheet Thermal Specifications tel 5 1 4 5 1 5 5 1 6 QR CSR IPF THERM CONFIG thermalert deassert thresh Intel recommends using the values listed in the when programming QR CSR IPF THERM CONFIG thermalert assert hot thresh and QR CSR IPF THERM CONFIG thermalert deassert thresh The default values for QR CSR IPF THERM CONFIG thermalert assert hot thresh and QR CSR IPF THERM CONFIG thermalert deassert thresh are 10 and 4 respectively for the Intel Itanium Processor 9300 Series For the Intel Itanium Processor 9500 Series the default values are 0 This signal can be used by the platform to implement thermal regulation features such as generating an external interrupt to tell the operating system that the processor core die temperature is increasing TCONTROL iS a thermal monitoring setpoint which is specified as a relative temperature in degrees Celsius below the PROCHOT_N threshold The minimum value of the Tcontrotthreshold is specified in Table 5 3 for the Intel Itanium9 Processor 9300 Series and Table 5 4 for the Intel Itanium Processor 9500 Series and the default value is available in the PIROM value applies to the full range of the processor operating power and is independent of the processor core configuration or executed applications A server thermal management controller can monitor the processor temperature via the Digital Thermal
103. 000000000 02000 000000000000 0000 000000000000 FJ 0000 000000000000 5 000000000000 000000000000000 r4 9999889955 020000000000000000000000000 90000000000 000000000000 T E th fe Les 25 4 28 E Ps 2 k B5 ze 5 iz 5 E 28 amp uy 1 a us i XD 1 LII 1 EM is Me S 1 E EN _______ 2 Y p 5 5 20 i IM HB 1 0000 L2 0500 000 ib is E Intel Itanium Processor 9300 Series and 9500 Series Datasheet 127 m e n te Mechanical Specifications Figure 4 9 Intel Itanium Processor 9500 Series Package Drawing Sheet 4 of 4 3 3 ipe MEET 4 or 4 63135 5 63135 DO NOT SCALE DRAWING SIRE RAFTING QOOOQO 33 35 31 20 22 24 26 28 30 32 34 36 38 2200 MISSION COLLEGE BLVD P O 58119 23 25 27 29 3 BOTTOM VIEW
104. 055 VID 0 075 VID 0 095 70 VID 0 06 VID 0 08 VID 0 1 75 VID 0 064 VID 0 084 VID 0 104 80 VID 0 068 VID 0 088 VID 0 108 85 VID 0 072 VID 0 092 VID 0 112 90 VID 0 077 VID 0 097 VID 0 117 95 VID 0 081 VID 0 101 VID 0 121 100 VID 0 085 VID 0 105 VID 0 125 105 VID 0 089 VID 0 109 VID 0 129 110 VID 0 094 VID 0 114 VID 0 134 115 VID 0 098 VID 0 118 VID 0 138 120 VID 0 102 VID 0 122 VID 0 142 125 VID 0 106 VID 0 126 VID 0 146 130 VID 0 111 VID 0 131 VID 0 151 135 VID 0 115 VID 0 135 VID 0 155 140 VID 0 119 VID 0 139 VID 0 159 145 VID 0 123 VID 0 143 VID 0 163 150 VID 0 128 VID 0 148 VID 0 168 155 VID 0 132 VID 0 152 VID 0 172 160 VID 0 136 VID 0 156 VID 0 176 165 VID 0 14 VID 0 16 VID 0 18 46 Intel Itanium Processor 9300 Series 9500 Series Datasheet Electrical Specifications Table 2 21 intel Vcccore Static and Transient Tolerance for Intel Itanium Processor 9300 Series Sheet 2 of 2 Core Current A Voltage Deviation from VID Setting V 1 2 3 4 1 _ _ Vcc _ 170 VID 0 145 VID 0 165 VID 0 185 175 VID 0 149 VID 0 169 VID 0 189 180 Notes 1 The min Vcc max load lines represent static and transient limits 2 This table is intended to aid in reading discrete points on Figure 2 11 3
105. 1 Intel Itanium Processor 9300 Series and 9500 Series Datasheet 55 m tel Electrical Specifications Notes 1 These parameters are based on design characterization and are not tested 2 With 50Q termination to VCCIO at the far end Table 2 34 Debug Signal Group DC Specifications Symbol Parameter Min Max Unit Notes ViL Input Low Voltage 0 VCCI O 0 67 0 2 V Input High Voltage VCCIO 0 67 0 2 VCCIO V Output High Voltage VCCIO 0 2 VCCIO V VoL Output Low Voltage 0 0 35 V 1 lot Output Low Current 13 23 mA 1 Input Leakage Current 1000 200 2 Output Leakage Current 1000 200 Notes 1 With 2 parallel 50Q termination to VCCIO at the far end 2 With input leakage current measured at the pin with OV and with 1 1V supplied to the pin System designers are advised to check the tolerance of their voltage regulator solutions to ensure Vpin of 1 1 V Table 2 35 PIROM Signal Group DC Specifications Symbol Parameter Min TYP Max Unit Notes Input Low Voltage 0 6 Vcc 0 3 2 1 Input High Voltage Vcc 0 7 Vcc 0 5 2 1 2 Output Low Voltage loj 0 4 2 2 1 mA Output Low Voltage 0 2 2 0 15 mA liLeak Input Leakage Current 0 1 3 0 2 OLeak Output Leakage Current 0 05 3 0 2 Notes 1 min and are reference only and are not tes
106. 1 5 Mixing Processors of Different Frequencies and Cache Sizes 20 1 6 Terminology tected tities Dir lega da v EFT EDS DEn S 20 Dark Rn orn aD 21 1 8 Reference DOCUMENES 21 2 Electrical 5 1 23 2 1 Intel QuickPath Interconnect and Intel Scalable Memory Interconnect Differential Signaling sana ndangade tates 23 2 22 Signal GrOUPS eed 24 2 3 Reference Clocking Specifications memes 26 2 4 Intel QuickPath Interconnect and Intel SMI Signaling 5 28 2 4 1 Intel Itanium Processor 9300 Series Intel QuickPath Interconnect and Intel SMI Specifications for 4 8 28 2 4 2 Intel Processor 9500 Series Requirements for Intel QuickPath Interconnect for 4 8 and 6 4 5 32 2 4 3 Intel Itanium Processor 9500 Series Processor Requirements for Intel SMI Specifications for 6 4 5 2 40 37 2 5 Processor Absolute Maximum 05 1 38 2 5 1 Intel
107. 2 10 specify static and transient tolerances for the uncore outputs Intel Itanium Processor 9300 Series 9500 Series Datasheet m Electrical Specifications tel Table 2 20 Vccuncore Static and Transient Tolerance for Intel Itanium Processor 9300 Series A Voltage Deviation from VID Setting V 1 2 3 4 cc UNCORE Vcc Max Vcc Typ Vcc Min 0 VID 0 VID 0 02 VID 0 04 5 VID 0 02 VID 0 04 VID 0 06 10 VID 0 04 VID 0 06 VID 0 08 15 VID 0 06 VID 0 08 VID 0 1 20 VID 0 08 VID 0 1 VID 0 12 25 VID 0 1 VID 0 12 VID 0 14 30 VID 0 12 VID 0 14 VID 0 16 35 VID 0 14 VID 0 16 VID 0 18 40 VID 0 16 VID 0 18 VID 0 2 45 VID 0 18 VID 0 2 VID 0 22 50 VID 0 2 VID 0 22 VID 0 24 Notes 1 Vcc min Vcc load lines represent static and transient limits 2 This table is intended to aid in reading discrete points on Figure 2 10 3 load lines specify voltage limits at the die measured at the VssuncoreEsENsE Pins Voltage regulation feedback for voltage regulator circuits must be taken from processor Vcc and Vss pins Refer to the Ararat Voltage Regulator Module Design Guide for socket load line guidelines and VR implementation 4 Vpc max VI D Ry lec 5 mV Vpc min zVI D Rj lcc 35mV Ry 4 mW Figure 2 10 Static and Transient Tolerance for
108. 20 0 825 0 830 1 035 1 040 1 045 1 050 1 055 1 060 1 065 1 070 1 075 1 080 1 085 1 090 1 095 1 100 1 105 1 110 1 115 1 120 1 125 1 130 1 135 1 140 1 145 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1D VID vip 2 3 VID VID 4 D vipe VI 7 Hex 65 66 67 68 69 6A 6B 6 60 70 71 72 73 74 75 9 OF AO Al A2 A3 4 5 7 8 9 1 B2 B3 B4 61 Intel Itanium Processor 9300 Series 9500 Series Datasheet intel Electrical Specifications Table 2 37 Intel Itanium amp Processor 9500 Series VCCCORE VID VCCCORE and VCCUNCORE and VID VCCUNCORE Voltage Identification Definition for Ararat 11 Sheet 4 of 4 Hex M d VID6 VID VID V 56 5 1 0 1 1 0 1 0 1 1 150 1 1 0 1 1 1 0 1 1 350 6 1 0 1 1 0 1 1 0 1 155 1 1 0
109. 2V allows the PIROM to be read before the processor is powered Once started the power up sequence must complete within 1000 ms as defined by the time limit for PWRGOOD to be asserted VCC33 SM is brought up first to allow platforms to read the socket Processor Information data and the PROCTYPE pin VccArarat 12V is the input voltage to the Ararat regulator The VCCA supply is used to power the processor s analog circuits VCCIO is used to power the 1 circuits Once VCCIO is up and stable the external environment can generate the SYSINT clock signals Once the SYSINT clocks are valid the external environment can assert the 64 Intel Itanium Processor 9300 Series 9500 Series Datasheet Electrical Specifications tel VROUTPUT_ENABLEO signal After VROUTPUT_ENABLEO is asserted the sequence of powering up the VCCUNCORE and VCCCORE supplies and the VCCCACHE Intel Itanium Processor 9300 Series begins For the Intel Itanium9 Processor 9300 Series the VCCUNCORE VCCCORE and VCCCACHE supplies power the sysint cores and large cache arrays respectively For the Intel Itanium Processor 9500 Series the VCCUNCORE VCCCORE supplies power the sysint the cores and the large cache arrays respectively When all supplies are up and stable Ararat asserts VRPWRGD which signals the external environment that it can assert the PWRGOOD signal PWRGOOD assertion initiates the processor internal cold reset sequence
110. 3 Differentia 6 CSIORNDAT 6 Differential 6 VSS Power Other F37 CSIORPDAT 6 Differential 7 CSIORNDAT 5 Differentia F38 RSVD E38 CSIORPDAT 5 Differentia G1 RSVD E9 FBD1SBOCP 1 Differentia G2 VSS Power Other Fl RSVD G3 FBD1SBODN 1 Differentia 0 F2 FBD1SBODN 3 Differentia G4 FBD1SBODN 2 Differentia FBD1SBODP 3 Differentia G5 FBD1SBODP 2 Differentia VSS Power Other G6 FBD1SBODN 10 Differentia 5 VSS Power Other G7 vss Power Other F6 FBD1SBODP 8 Differential G8 FBDINBI CN 9 Differentia 7 FBD1SBODN 8 Differential G9 BOOTMODE 1 8 VCCIO_FBD Power Other G10 BOOTMODE 0 F9 VSS Power Other G11 FBDINBICN 8 Differential 10 FBDINBICP 11 Differential 12 VSS Power Other F11 FBDINBICN 11 Differential 1 Power Other F12 VSS Power Other G14 VSS Power Other F13 VSS Power Other G15 CSI4TNDAT 4 Differentia 14 VSS Power Other G16 CSI4TPDAT 4 Differentia F15 VSS Power Other G17 VSS Power Other F16 VCCIO Power Other G18 CSIARPCLK Differentia 217 CSI4RNDAT 9 Differential 19 CSI2RPDAT 2 Differentia 18 CSI4RPDAT 9 Differential G20 CSI 2RNDAT 2 Differentia 19 VSS Power Other G21 CSI2RPDAT 1 Differentia 20 CSI2RPDAT 3 Differential 622 VSS Power Other F21 CSI2RNDAT 3 Differential 623 512 0 Differentia 22 VSS Power Other G24 CSI2TNDAT 1 Differentia 223 VCCIO Power Other G25 CSI2TPDAT 1 Differentia
111. 4 PIR_SCL Power Other AF9 VSS Power Other AG25 Power Other AF10 VCCIO Power Other AG26 VSS Power Other AF11 PRBMODE RDY N 27 VSS Power Other AF12 PRBMODE_REQST_N 28 SKTID 2 27 VCCIO Power Other AG29 SKTID O 28 vss Power Other AG30 5 13 Differentia 29 VSS Power Other AG31 CSI3TNDAT 12 Differentia AF30 CSI3TNDAT 13 Differential 2 VSS Power Other AF31 CSI3TNDAT 14 Differential CSI1TNDAT 13 Differentia AF32 CSI3TPDAT 14 Differential AG34 CSI1TPDAT 13 Differentia CSI1TPDAT 14 Differential 5 Power Other AF34 VSS Power Other AG36 CSI IRNDAT 12 Differentia 5 VSS Power Other AG37 VSS Power Other AF36 CSI1RNDAT 14 Differentia AG38 511 131 Differentia 7 CSI 1RPDAT 14 Differentia 1 FBDONBIBP 6 Differentia AF38 511 131 Differentia 2 FBDONBIBN 12 Differentia 1 FBDONBIBN 6 Differentia FBDONBICLKBNO Differentia 2 VSS Power Other AH4 FBDONBICLKBPO Differentia FBDONBIBP 7 Differentia 5 VSS Power Other AG4 VCCIO FBD Power Other AH6 FBDOSBOBN 2 Differentia Intel Itanium Processor 9300 Series and 9500 Series Datasheet 91 intel Table 3 2 Pin List by Pin Number Sheet 7 Table 3 2 Pin List by Pin Number Sheet 8
112. 44 0 16 0 18 0 20 0 22 0 5 10 15 20 25 30 35 40 45 50 1 48 Intel Processor 9300 Series and 9500 Series Datasheet Electrical Specifications 2 6 4 2 6 4 1 Table 2 23 Intel Itanium Processor 9300 Series 9500 Series Datasheet Intel tanium Processor 9500 Series Uncore and Core Tolerances Uncore Static and Transient Tolerances Table 2 23 and Figure 2 13 specify static and transient tolerances for the uncore outputs intel VccuNcont Static and Transient Tolerance for the Intel Itanium Processor 9500 Series Uncore Current A Voltage Deviation from VID Setting V 1 2 3 4 l cc UNCORE Vcc Typ Vcc Min 0 VID 0 015 VID VID 0 015 5 VID 0 00875 VID 0 00625 VID 0 02125 10 VID 0 0025 VID 0 0125 VID 0 0275 15 VID 0 00375 VID 0 01875 VID 0 03375 20 VID 0 01 VID 0 025 VID 0 04 25 VID 0 01625 VID 0 03125 VID 0 04625 30 VID 0 0225 VID 0 0375 VID 0 0525 35 VID 0 02875 VID 0 04375 VID 0 05875 40 VID 0 035 VID 0 05 VID 0 065 45 VID 0 04125 VID 0 05625 VID 0 07125 50 VID 0 0475 VID 0 0625 VID 0 0775 55 VID 0 05375 VID 0 06875 VID 0 08375 60 VID 0 06 VID 0 075 VID 0 09 65 VID 0 06625 VID 0 08125 VID 0 09625 70 VID 0 0725 VID 0 0875 VID 0 1025 Notes 1 The min
113. 500 Series package top side J3 connector Table 3 8 5 J3 Connector Two Dimensional Table Intel Itanium Processor 9500 Series Sheet 1 of 2 Intel Itanium Processor 9300 Series 9500 Series Datasheet 1 2 3 4 A NO CONNECT NO CONNECT A B VR_FAN_N NO CONNECT NO CONNECT B NO CONNECT C D VCCCORE D VSS E VSS H J VCCCORE VSS K L 55 M N VCCCORE N R VCCCORE R T VSS T U VSS v VSS V w VCCUNCORE w Y VCCUNCORE Y AA VCCUNCORE AA AB VCCUNCORE AB AC VSS AC AD vss AD AE VSS AE AF VCCUNCORE VCCUNCORE AG 1 2 3 4 113 intel Pin Listing Table 3 8 5 J3 Connector Two Dimensional Table Intel Itanium Processor 9500 Series Sheet 2 of 2 1 2 3 4 AH VCCUNCORE AH AJ VCCUNCORE VSS AK AL VSS AL AM VCCCORE AM AN VCCCORE AN AP VCCCORE AP AR VSS AR AT VSS AT AU SVID_DATA SVID_CLK AU AV VSS VSS AV NO CONNECT NO CONNECT AW SVID_ALERT_N CPU_PRESB_N AW AY NO CONNECT Reserved AY 1 2 3 4 3 2 4 Top Side 4 Connector Two Dimensional Table 3 2 4 1 Top Side J 4 Connector Two Dimensional Table for the ntel tanium Processor 9300 Series Table 3 9 is a
114. 9300 Series Package Drawing Sheet 3 4 123 Intel Itanium Processor 9300 Series Package Drawing Sheet 4 014 124 Intel Itanium Processor 9500 Series Package Drawing Sheet 1 of 4 125 Intel Itanium Processor 9500 Series Package Drawing Sheet 2 014 126 Intel Itanium Processor 9500 Series Package Drawing Sheet 3 of 4 127 Intel Itanium Processor 9500 Series Package Drawing Sheet 4 of 4 128 Processor Marking 2 5 131 Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series Thermal States 134 Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series Package Thermocouple Location 140 Intel tanium Processor 9300 Series and Intel Itanium Processor 9500 Series 151 Processor 9300 Series and 9500 Series Datasheet 5 2 20 2 21 2 22 2 23 2 24 2 25 Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series Feature 19 Iri 24 Signal GEOUDS errs RATER Pr Eire vidas 24 Intel QuickPath Interconnect Intel Scalable Memory Interconnect Reference Clock Specifications26 Intel tanium Processor 9300 Series Clock Frequency
115. All pins are defined for both Intel Processor 9300 Series and Intel Itanium Processor 9500 Series except where noted Package Bottom Pin Listing by Pin Name 3 1 3 1 1 Table 3 1 Pin List by Pin Name Sheet 1 of 33 Direction G10 BOOTMODE 0 G9 BOOTMODE 1 CPU_PRES1_N 1 0 D37 CPU_PRES2_N 1 0 AT36 CPU_PRES3_N 1 0 AT3 CPU_PRES4_N 1 0 137 CSIORNCLK Differentia B33 CSIORNDAT 0 Differentia 034 CSIORNDAT 1 Differentia 834 CSIORNDAT 2 Differentia 035 CSIORNDAT 3 Differentia C36 CSIORNDAT 4 Differentia 7 CSIORNDAT 5 Differentia 6 CSIORNDAT 6 Differentia G35 CSIORNDAT 7 Differentia H36 CSIORNDAT 8 Differentia 135 CSIORNDAT 9 Differentia 136 CSIORNDAT 10 Differentia 138 CSIORNDAT 11 Differentia 37 CSIORNDAT 12 Differentia P36 CSIORNDAT 13 Differentia 37 CSIORNDAT 14 Differentia T36 CSIORNDAT 15 Differentia T38 CSIORNDAT 16 Differentia 036 CSIORNDAT 17 Differentia 38 CSIORNDAT 18 Differentia W37 CSIORNDAT 19 Differentia K37 CSI ORPCLK Differentia Intel Itanium Processor 9300 Series 9500 Series Datasheet Table 3 1 Pin List by Pin Name Sheet 2 of 33 Direction
116. CCIO FBD Power Other AN4 81 Differential 6 31 Differentia 5 VSS Power Other AP7 FBDONBI BN 2 Differentia 6 FBDONBIBP 3 Differential VSS Power Other AN7 VCCIO FBD Power Other AP9 FBDONBI BP 0 Differentia AN8 VSS Power Other AP10 VCCIO_FBD Power Other AN9 FBDONBIBN 0 Differential 11 TRIGGER 1 _N 1 0 AN10 VSS Power Other AP12 VSS Power Other AN11 RSVD AP13 VSS Power Other AN12 Power Other AP14 CSI 5RPDAT 2 Differential AN13 CSI 5RPDAT 1 Differential 15 CSI5RNDAT 3 Differential 14 CSI 5RNDAT 2 Differential 16 CSI5RPDAT 3 Differential 94 Intel Itanium Processor 9300 Series and 9500 Series Datasheet intel Pin Listing Table 3 2 Pin List by Pin Number Sheet Table 3 2 Pin List by Pin Number Sheet 13 of 32 14 of 32 m m Pin Name Direction mum Pin Name E Direction AP17 CSISRNCLK Differential 19 CSI 3RNDAT 5 Differential 18 VSS Power Other AR20 CSI3RPDAT 9 Differential 19 CSI3RNDAT 4 Differential 21 VSS Power Other AP20 VCCIO Power Other AR22 5 101 Differential 21 CSI3TPDAT 3 Differential 23 Power Other AP22 VSS Power Other AR24 VSS Power Other AP23 VSS P
117. CLK Differentia AH31 CSI 3TPDAT 12 Differentia AJ33 VSS Power Other AH32 CSI1TNDAT 12 Differentia AJ34 CSI TTPDAT 11 Differentia CSI1TPDAT 12 Differentia AJ35 VSS Power Other AH34 CSI1TNDAT 11 Differentia 36 511 101 Differentia 5 VSS Power Other AJ37 CSI IRNDATT 10 Differentia 6 511 121 Differentia AJ38 VSS Power Other AH37 511 111 Differentia AK1 VSS Power Other AH38 CSI 3RNDAT 11 Differentia 2 FBDONBIAN 11 Differentia 1 VCCIO FBD Power Other AK3 FBDONBI AP 11 Differentia AJ2 FBDONBIBP 12 Differentia FBDONBIBP 13 Differentia VSS Power Other AK5 FBDONBIBN 5 Differentia 4 13 Differentia 6 VSS Power Other AJ5 VCCIO FBD Power Other AK7 FBDOSBOBP 1 Differentia 6 VSS Power Other AK8 FBDOSBOBN O0 Differentia AJ7 FBDOSBOBN 1 Differential FBDOSBOBP 0 Differentia A8 vss ____ A10 XDPPOCPD7Z N 92 Intel Itanium Processor 9300 Series 9500 Series Datasheet intel Pin Listing Table 3 2 Pin List by Pin Number Sheet 9 Table 3 2 Pin List by Pin Number Sheet of 32 10 of 32 m M Pin Name Direction mu
118. D W11 VSS Power Other W12 RSVD W27 RSVD W28 VSS Power Other w29 TESTHI 2 104 Intel Itanium Processor 9300 Series 9500 Series Datasheet Pin Listing 2 2 3 2 1 3 2 1 1 Table 3 3 intel Processor Package Top Pin Assignments This section provides two dimensional tables of the package top pin assignments These pins connect to the Ararat Voltage Regulator Power Module and do not connect to the motherboard Top Side 1 Connector Two Dimensional Table Top Side J 1 Connector Two Dimensional Table for the I ntel Itanium9 Processor 9300 Series Table 3 3 is a two dimensional table of the Intel Itanium Processor 9300 Series package top side J 1 connector Top Side J 1 Connector Two Dimensional Table Intel Itanium Processor 9300 Series Sheet 1 of 2 1 2 3 4 VID_VCCCORE 1 VID_VCCCORE 2 A B VID VCCCOREI3 NO CONNECT VID VCCCOREIA B NO CONNECT c VID VCCCORE 5 VID VCCCOREI6 C D VCCCORE D E VCCCORE E F VSS G VSS G H VCCCORE H J VCCCORE VSS K L VSS L M VCCCORE M N VCCCORE N VSS R VSS R T VCCCACHE v VSS w VSS w AA AB VCCCACHE AB 1 2 3 4 Intel Itanium Processor 9300 Series 9500 Series Datasheet 105 intel Pin Listing
119. DC spec AC tolerance VCC33 SM 3 3 V supply voltage 3 135 3 3 3 465 V Notes 1 The voltage specification requirements are measured across the VCCUNCORESENSE and VSSUNCORESENSE pins using oscilloscope set to a 100 MHz bandwidth and probes that are 1 5 pF maximum capacitance and 1 mOhms minimum impedance at the processor socket The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the scope probe 40 Intel Processor 9300 Series 9500 Series Datasheet Electrical Specifications intel 2 These voltages are target only A variable voltage source should exist on systems in the event that a different voltage is required See Ararat Voltage Regulator Module Design Guide for more information 3 Uncore Core and Cache voltage and Current Rating are at the Package Pad 4 The voltage specification requirements are measured across the VCCCORESENSE and VSSCORESENSE pins using an oscilloscope set to a 100 MHz bandwidth and probes that are 1 5 pF maximum capacitance and 1 MOhm minimum impedance at the processor Socket The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the scope probe 5 The voltage specification requirements are measured across the VCCCACHESENSE and VSSCACHESENSE pins using oscilloscope set to a 100 MHz bandwidth and probes that are 1 5 pF maximum
120. DP Thermal Max Operating T C T C Minimum Design Power Temperature TcoNTROL Notes W DT Readout DT Readout 185 0 5 88 5 1 2 3 4 5 155 0 5 88 5 1 2 3 4 5 130 0 5 88 5 1 2 3 4 5 Notes 1 processor maximum temperature is reached at That is when DT readout is equal to zero 2 Intel recommends that the thermal solution designs target the processor Thermal Design Power instead of its spontaneous maximum power consumption 3 Processor is determined at the equal to TcAsE GTDP 4 Tcase is provided for the purpose of designing a processor compatible thermal solution 5 The THERMALERT and TCONTROL values are temperature offsets below Tcase cannot be used as proxy for power dissipation due to the variation in work load imbalances between cores TDPmax is 185 W or 155 W or 130 W depending on the SKU The combined max short term 250 ms power for the Ararat supplies VCC CORE VCC UNCORE and VCC CACHE is limited to 230 W and the total of all supplies is limited to 250 W for the 185 W SKUs Thermal Specification for the Intel Itanium Processor 9500 Series Processor TDP Thermal Max Operating T C T C Minimum Design Power Temperature e Notes W DT Readout DT Readout 170 0 5 78 3 1 130 0 5 78 3 1 2 3 4 5 Notes 1 The processor maximum temperature is reached
121. Development and Optimization Intel Itanium Processor Family System Abstraction Layer Specification Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series Platform Design Guide System Management Bus SMBus Specification Contact your Intel representative or check http developer intel com for the latest revision of the reference documents Intel Itanium Processor 9300 Series and 9500 Series Datasheet 21 22 Introduction Intel Itanium Processor 9300 Series and 9500 Series Datasheet Electrical Specifications n tel 2 2 1 Electrical Specifications This chapter describes the electrical specifications of the Intel Itanium Processor 9300 Series and 9500 Series processors Intel QuickPath nterconnect and Intel Scalable Memory I nterconnect Differential Signaling The links for Intel QuickPath Interconnect Intel and Intel Scalable Memory Interconnect Intel SMI signals use differential signaling The Intel SMI bus pins are referred to as FB DIMM pins on the package The termination voltage level for the processor for uni directional serial differential links each link consisting of a pair of opposite polarity D D signals is Termination resistors are provided on the processor silicon and are terminated to Vss thus eliminating the need to terminate the links on the system board for the Intel QuickPath Interconnect a
122. Differential 27 Power Other V11 SYSUTST_REFCLK Differential 1 Power Other 011 SYSUTST_REFCLK_N Differential 17 Power Other 11 AK23 Power Other P12 TDI AL15 VCCIO Power Other N12 TDO 0 AL25 Power Other Y28 TESTHI 1 AL35 VCCIO Power Other W29 TESTHI 2 14 Power Other V28 TESTHI 4 19 Power Other A5 THERMALERT N 0 AM29 Power Other A6 THERMTRIP_N 0 AM33 Power Other R12 TMS 12 Power Other AL11 TRIGGER 0 1 0 AP20 Power Other AP11 TRIGGER 1 _N 1 0 AP24 Power Other 11 TRST_N 4 Power Other AV6 VCC33 SM Power Other AR12 VCCIO Power Other 7 VCC33_SM Power Other AR23 Power Other A27 VCCA Power Other AR28 Power Other A28 VCCA Power Other AR30 Power Other A31 VCCA Power Other AR35 Power Other A32 VCCA Power Other AT25 Power Other AV21 VCCA Power Other AU20 Power Other AV22 VCCA Power Other 14 Power Other AV26 VCCA Power Other C24 Power Other AV27 VCCA Power Other C29 Power Other AA37 Power Other D32 Power Other AB28 Power Other E14 Power Other AB30 Power Other E27 Power Other AB36 Power Other E34 Power Other AD11 Power Other 16 Pow
123. FB DIMM 1 and Bits 7 3 MSBs reserved 1 supported 1 supported 0 not supported 0x04 2 only 0 06 2 1 support Intel Itanium Processor 9500 Series 57 39h Maximum Memory 6 bcd digits Maximum Memory Transfer rate 800 MT s 000800 GT Transfer Rate for this part in GT s 5 58 39h 00 59 3Bh 3Ah 08 3Bh 00 60 3Ch Minimum Memory 6 bcd digits Minimum Memory Transfer rate 800 MT s 000800 GT Transfer Rate for this part in 5 5 61 3Dh 3Ch 00 62 3Eh 3Dh 08 3Eh 00 63 3Fh Uncore Voltage ID 4 bcd digits Voltage in four 4 bit Hex digits in 1200 mV 1200 mV 64 40h 00 40 12 65 41h Uncore Voltage 2 Hex digits Edge finger tolerance in mV 20 mV 0x14 Tolerance High 66 42h Uncore Voltage 2 Hex digits Edge finger tolerance in mV 20 mV 0 14 Tolerance Low 67 43h RESERVED Hex Reserved for future use 42h 0x00 68 44h 43h 0x00 69 45h Checksum Hex Add up by byte and take 2 s complement Cache 70 46h L3 LLC Cache Size 4 bcd digits Size of the Cache in MB 24MB 0024 71 47h 46h 24 47h 00 72 48h Cache Voltage ID 4 bcd digits Voltage in four 4 bit bcd digits in 1163 mV 1163 Intel Itanium Intel Itanium mV Intel Itanium Processor 48h 63 73 49h Processor 9300 Series Processor 9300 Series 49 11 5 s Intel Itanium 2 Hex digits Intel Itanium amp Processor 9300 Series Processor 9500 RESERVED Intel Series 48h 0x00 Itaniu
124. FLASHROM CFG 1 0 setup to 0 ns PWRGOOD deasserted T8 SKTID 2 0 as socket id LRGSCLSYS hold 0 s after RESET deasserted SKTID 1 0 as rst modifier setup to RESET N T9 asserted 200 ns T10 SKTID 1 0 as rst modifier hold after RESET_N 200 ns 70 Intel Processor 9300 Series 9500 Series Datasheet Electrical Specifications Table 2 40 RESET_N and SKTID Timing Sheet 2 of 2 Parameter Description MIN MAX UNIT RESET_N deasserted delay to SKTID 2 deasserted as error 100 nS SKTID 2 as error in asserted pulse width SYSCLK T12 3 cycles BOOTMODE 2 0 FLASHROM CFG 1 0 hold 1 after 5 deasserted T14 BOOTMODE 2 FLASHROM_CFG 1 0 setup to 0 Hs RESET asserted 2 14 Test Access Port TAP Connection The recommended connectivity is detailed in the Intel Itanium Platform Debug Port Design Guide DPDG Intel Itanium Processor 9300 Series 9500 Series Datasheet 71 72 Electrical Specifications Intel Itanium Processor 9300 Series 9500 Series Datasheet Pin Listing 3 Pin Listing Processor Package Bottom Pin Assignments This section provides a sorted package bottom pin list in Table 3 1 and Table 3 2 Table 3 1 is a listing of all processor package bottom side pins ordered alphabetically by pin name Table 3 2 is a listing of all processor package bottom side pins ordered by pin number
125. IMMs FB DIMM 1 SB CLK C D P N Interface Branch South Output Clock Channel Differential Name Number Bound Pair Polarity Positive Negative Example FBD1SBICLKDPO represents FB DIMM branch 1 southbound clock output signal of channel D and positive bit of the differential pair FBD 0 1 REFSYSCLK P N These signals no longer used by the Intel Itanium Processor 9300 Series and Intel Itanium 9500 Series FBDONBI A B P N 12 0 FBDONBI A B P N 13 Intel Itanium Processor 9300 Series and 9500 Series Datasheet These differential pair data signals generated from the branch zero channel A and B of FB DIMMs are input to the processor FB DIMM 12 0 Interface Branch North Input Channel Differential Lane Name Number Bound Pair Number Polarity Positive Negative Example FBDONBIAP 0 represent FB DIMM branch 0 northbound data input lane 0 signal of channel A and positive bit of the differential pair These signals are spare lanes and are intended for Reliability Availability and Serviceability RAS coverage on the Intel Itanium 9500 Processor Series These signals are not used by Intel Itanium 9300 Processor Series 161 intel Signal Definitions
126. IXING Processor Senenin DER RUND data REX S 64 2 11 Supported Power up Voltage Sequence 64 2 11 1 Supported Power up Voltage Sequence for the Intel Itanium Processor 9300 66 2 11 2 Supported Power up Voltage Sequence for the Intel Itanium Processor 9500 Series esee 67 2 11 3 Power up Voltage Sequence Timing 4 68 2 12 Supported Power down Voltage Sequence 68 2 13 Timing Relationship Between RESET and 5 69 2 14 Test Access Port meses esee een 71 3 Pin Liston EET 73 3 1 Processor Package Bottom Pin 73 Intel Itanium Processor 9300 Series and 9500 Series Datasheet 167 intel 3 1 1 Package Bottom Pin Listing by Pin mes 73 3 1 2 Pin Listing by Pin ettet pen na RR 89 3 2 Processor Package Top Pin 105 3 2 1 Top Side 1 Connector Two Dimensional Table 105 3 2 2 5 2 Connector Two Dimensional Table 108 3 2 3 Top Side 3 Connector Two Di
127. Itanium Processor 9300 Series and 9500 Series Datasheet 101 intel Pin Listing Table 3 2 Pin List by Pin Number Sheet Table 3 2 Pin List by Pin Number Sheet 27 of 32 28 of 32 SN Pin Name eras Direction m Li m Direction M7 VSS Power Other N9 FBD1NBICP 5 Differential 8 FBD1NBI CLKCPO Differential 10 VSS Power Other M9 FBD1NBICN 13 Differential 11 TRST_N 10 FBD1NBICP 13 Differential 12 0 M11 LRGSCLSYS 27 FLASHROM_CLK 0 M12 VSS Power Other N28 FLASHROM CFG 0 M13 RSVD N29 FLASHROM_CS 3 _N 14 514 01 Differential N30 VSS Power Other M15 CSIATPDAT O Differential N31 CSI 2TPDAT 13 Differential 16 VSS Power Other N32 CSIOTNDAT 12 Differential 17 VSS Power Other N33 CSIOTPDAT 12 Differential 18 Power Other N34 CSIOTNDAT 13 Differential 19 VSS Power Other N35 VSS Power Other M20 RSVD N36 Power Other M21 RSVD N37 CSIORNDAT 12 Differential M22 VSS Power Other N38 CSIORPDAT 12 Differential 23 Other FBDOSBOAN 9 Differential M24 VSS Power Other P2 FBDOSBOAP 9 Differential M25 VSS Power Other P3 VSS Power Other M26 Other vss Power Other M27 VSS Power Other P5 FBDINBIDN 12 Differential 28 FLASHROM_CFG 1 1
128. Itanium Processor 9500 Series Package Thermocouple Location 140 6 1 Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series 151 Intel Itanium Processor 9300 Series and 9500 Series Datasheet 169 170 Intel Itanium Processor 9300 Series and 9500 Series Datasheet 1 1 Intel Itanium Processor 9300 Series and Intel tanium Processor 9500 Series Feature Comparison 19 2 1 Signals With rec Dese tr E debated bero DEED DR 24 2 2 Signal GroUpSe dhe nea aei ER ed Ee 24 2 3 Intel QuickPath Interconnect Intel Scalable Memory Interconnect Reference Clock 5 26 2 4 Intel Itanium Processor 9300 Series Clock Frequency 29 2 5 Intel Itanium Processor 9300 Series Transmitter Parameter Values for Intel QuickPath Interconnect and Intel SMI Channels 4 8 5 29 2 6 Intel Itanium Processor 9300 Series Receiver Parameter Values for Intel QuickPath Interconnect and Intel SMI Channels 4 8 GT 30 2 7 Intel Itanium Processor 9500 Series Clock Frequency 33 2 8 Intel Itanium Processor 9500 Series Link Speed Independent Specifications 33 2 9 Intel Itani
129. LLC 4MBLLC 4MB LLC 4MB LLC 4MB LLC 4MB LLC 4MB LLC 4MBLLC Intel 1 Intel su lt gt gt smi PFO Zbox0 BboxO lt Rbox Bbox1 Zbox1 lt rr Intel Intel sui gt gt Ubox 4 4 1 1 4 gt f Pai PQ2 5 Intel Intel Intel Intel Intel Intel OPI 4 QPI O 1 2 3 5 Intel Itanium Processor 9300 Series and 9500 Series Datasheet The Intel QPI viral and poison fields are used to flag corrupted system state and bad data accordingly Once it has gone viral an Intel QPI agent will set the viral field within all packet headers Viral mode is entered in three ways receiving a viral packet upon a detecting fatal panic error or when a global viral signal from Cboxes is asserted Viral is cleared on Reset Poisoning is used to indicate bad data on a per flit basis Poison does not indicate corrupted system coherency but rather that a particular block of data is not reliable Intel Itanium Processor 9500 Series PAL s Demand Based Switching DBS support includes implementations of Power Performance states P states and Halt states C states For the PAL Halt state interface and architected specifications of the PAL P state interface see the Intel Itanium Architecture Software Developer s Manual Volume 2 Section 11 6 PAL controls the Intel Itanium Processor 9500 Series processor power through a special built
130. MI 1 54 V signals VMAX US DIFF Undershoot for Intel and Intel SMI 0 337 V signals VABSMAX OS DIFF Absolute Max for Intel and Intel 1 7 V SMI signals VABSMAX US DIFF Absolute Min for Intel and Intel SMI 0 525 V signals 05 SYSCLK Sysclk single ended maximum voltage 1 54 VMIN US SYSCLK Sysclk single ended minimum voltage 0 337 Overshoot and Undershoot Specifications for the Intel Itanium Processor 9500 Series Overshoot and Undershoot Specifications For Differential Intel QuickPath I nterconnect and Intel SMI and Single Ended Signals for the Intel Itanium Processor 9500 Series Symbol Parameter Min Max Unit VMAX OS SE Overshoot for single ended signals 1 36 V VMIN US SE Undershoot for single ended signals 0 22 V VABSMAX OS SE Absolute Max for single ended signals 1 46 V VABSMIN US SE Absolute Min for single ended signals 0 32 V VMAX OS DIFF Overshoot for Intel and Intel SMI 1 3 V signals VMAX US DIFF Undershoot Intel and Intel 0 3 V SMI signals VABSMAX OS DIFF Absolute for Intel and Intel 1 4 V SMI signals VABSMAX US DIFF Absolute Min for Intel and Intel 0 4 V SMI signals VMAX OS SYSCLK Sysclk single ended maximum voltage 1 3 VMIN 95 SYSCLK Sysclk single ended minimum voltage 0 3 Signal DC Specifications Table 2 27 through Table 2 35 state the DC spec
131. MTRIP_N 7 FBD1SBOCLKCPO Differentia 8 FBD1SBOCLKCNO Differentia 9 VSS Power Other A10 FBD1SBOCP 5 Differentia 11 FBD1SBOCP 7 Differentia 12 FBD1SBOCN 7 Differentia 1 FBD1SBOCP 10 Differentia 14 VSS Power Other 15 CSIARPDAT O Differentia 16 VSS Power Other A17 CSI4RNDAT 3 Differentia 18 CSIARPDAT 3 Differentia 19 VSS Power Other A20 CSI2RPDAT 8 Differentia 21 CSI2RNCLK Differentia 22 512 Differentia 23 5128 10 Differentia 24 VSS Power Other A25 CSI2RNDAT 13 Differentia 26 5128 13 Differentia 27 Power Other A28 VCCA Power Other A29 VSS Power Other A30 CSI2RPDAT 17 Differential 1 Power Other A32 VCCA Power Other A33 5 0 Differential Intel Itanium Processor 9300 Series 9500 Series Datasheet Table 3 2 Pin List by Pin Number Sheet 2 of 32 Direction A34 VSS Power Other A35 RSVD A36 VSS Power Other A37 RSVD A38 RSVD 1 VCCIO FBD Power Other AA2 FBDOSBOBN 8 Differential AA3 FBDOSBOBP 8 Differential VSS Power Other AA5 VSS Power Other AA6 FBD1NBIDN 1 Differential 7 FBD1NBIDP 1 Differential 8 VCCIO FBD Power Other AA9 VSS Power Other AA10 VSS Power Other AA11 RSVD AA12 SYSCLK N Differential 27 RSVD AA28 VSS Power Other AA29 VSS Power Other AA30 VSS Power Oth
132. Materials its E 130 1248 FCLGA Package Marking Zones sss menm mene 130 Thermal Sensor Accuracy Distribution for the Intel Itanium Processor 9300 ERO CU Ep Pu Re 134 Thermal Sensor Accuracy Distribution for the Intel Itanium Processor 9500 5 135 Thermal Specification for the Intel Itanium Processor 9300 Series 139 Thermal Specification for the Intel Itanium Processor 9500 Series Processor 139 Storage Condition Ratings xci RU 141 Processor Information ROM 6 66 6 nnns 144 Read Byte SMBus Patcket ise rrr bake E HERE A 150 Write Byte SMBus Packet 150 Offset 78h 79h 2 440 4 mene mnn nnn nnn 156 128 Byte Checksum Values 2 1 eene 157 Signal Definitions for the Intel Itanium Processor 9300 Series and Intel Itanium 9500 enne 159 Intel Itanium Processor 9300 Series and 9500 Series Datasheet 7 intel Revision History Document Revision RP Number Number Description Date 322821 002 Initial release of the 9300 9500 document November 2012 322821 001 Initial release
133. Min and Max range is spec at the die for VCCIO This range includes 35 mV p p AC noise It also includes any DC and AC tolerances at package pin Intel Itanium Processor 9300 Series 9500 Series Datasheet 43 intel Electrical Specifications 7 The FMB remote sense tolerance is 2 5 for DC to 20 MHz at the package where 1 5 is allotted for a DC to 1 MHz range and an additional 1 0 for 1 MHz to 20 MHz Similarly 6 4 is allotted for DC to 20 MHz at the die It is expected that VCCIO regulators meet 1 5 at the remote sense location based on the general remote sense termination point location as described in Figure 2 16 VR Sense Point Representation For future processor compatibility it is strongly recommended that the platform query the PIROM to assure VCCIO is set to the appropriate level prior to powering up the VCCIO supply All voltage regulation measurements taken at remote sense termination points For peak to peak Ripple and Noise R amp N measured with full bandwidth BW of the scope Min 1 GHz BW scope is required set scope diff probe and the scope at full BW capture waveform A channel 1 10 For peak to peak Ripple and Noise R amp N measured above 1 MHz Step 1 set both scope diff probe and or the scope at 1 MHz BW limit capture waveform B channel 2 Step 2 calculate A B use scope Math function subtract channel 1 channel 2 to Table 2 19 170W 130W Current Specificatio
134. N Power Supplies Core Veccore Uncore Cache Intel Itanium VeccacHe Processor 9300 Series Analog VccA 1 0 Vecio Stand by Vcc33 5 Vcc33_sm Pins Input PIR_SCL 1 0 PIR_SDA PIROM Input PIR_AO Input 1 Input SM_WP Notes 1 CMOS signals have a reference voltage Vref equal to VCCIO 2 2 signals have a reference voltage Vref equal to VCCIO 2 3 3 All single ended buffer types including inputs outputs and input outputs include an on die pull up resistor between 4 kOhms and 8 7 kOhms Recommended values for external pull downs on the inputs and input output signals must meet the Vj specification for that buffer Reference Clocking Specifications The processor has one input reference clock SYSCLK SYSCLK for the Intel interface The processor timing specified in this section is defined at the processor pins unless otherwise noted Table 2 3 Intel QuickPath I nterconnect Intel Scalable Memory Interconnect Reference Clock Specifications Sheet 1 of 2 Symbol Parameter Min Nom Max Units Notes fsysclk ssc off System clock frequency 133 31 133 33 133 34 MHz Fsyclk scc on System clock frequency 132 62 132 99 133 37 MHz ERcysclk diff Rise Differential Rising and Falling Edge 1 0 4 0 Vins 3 4 ERcysclk diff Fall Rates Tsysclk_dutycycle Duty cycle of Reference clock 40 60 pe
135. N Dat 9 0 one uni directional transfer link Out The links Tx are terminally ground referenced The ports 3 0 with 19 0 bit lanes can be configured as a full width link with 20 active lanes a half width link with 10 active lanes or as a quarter width link with five active lanes Intel QuickPath 5 0 DAT 19 0 Interconnect Interface Name Port Transmitter Differential Lane Number Pair Number Polarity Positive Negative Example 514 0 represents port 5 Data lane 0 transmit signal and positive bit of the differential pair ERROR O _N Side band signaling for system management Refer to the Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series Platform Design Guide for pin considerations ERROR 1 _N Side band signaling for system management Assertion on this pin indicates that error reset response is required from the platform Refer to the Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series Platform Design Guide for pin considerations FBDONBICLK A B P N O These differential pair clock signals generated from the branch zero channel A and B of FB DIMMs are input to the processor FB DIMM 0 CLK Interface Branch North Input Clock Channel Differential Name Number Bound Pair Polarity Positive Negative Example FBDONBICLKAPO represents FB DIMM branch 0 no
136. Notes Transmitter output AC common mode defined as Vp4 Vp 2 0 0375 0 0375 Fraction of Vtx diff pp pin TXauty pin Average of absolute UI UI jitter 0 06 0 06 UI TXjitui Ut 1E 7 pin UI UI jitter measured at Tx output pins with 1E 7 probability 0 085 0 085 UI TXjitui Ut 1E 9 pin UI UI jitter measured at Tx output pins with 1E 9 probability 0 09 0 09 UI TXetk acc jit N_UI 1E 7 p p accumulated jitter out of transmitter over 0 lt n lt N UI where N 12 measured with 1 7 probability UI TXetk acc jit N_UI 1E 9 TTx data clk skew pin p p accumulated jitter out of transmitter over 0 lt lt N UI where N 12 measured with 1 9 probability Delay of any data lane relative to clock lane as measured at Tx output 0 5 0 17 0 5 UI UI Vnx diff pp pin Voltage eye opening at the end of channel for any data or clock channel measured with a cumulative probability of 1E 9 UI 1400 mV TRx diff pp pin Timing eye opening at the end of Tx channel for any data or clock channel measured with a cumulative probability of 1E 9 UI 0 61 UI Trx data clk skew pin Delay of any data lane relative to the clock lane as measured at the end of Tx channel This parameter is a collective sum of effects of data clock mismatches in Tx and on the mediu
137. OQOO QOO O0 O0 000000000000 OO 00000 Ot e 000000000000 000000000000 000000000000 XY 92899996985 ag EH E QQ 00 OO 0000 0000 Q 123 Intel Itanium Processor 9300 Series and 9500 Series Datasheet exea 32 1 Mechanical Specifications
138. Power Other AM7 VSS Power Other AU27 VSS Power Other AN10 VSS Power Other AU32 VSS Power Other AN15 VSS Power Other AU38 VSS Power Other AN20 VSS Power Other AU7 VSS Power Other AN25 VSS Power Other AV10 VSS Power Other AN30 VSS Power Other AV13 VSS Power Other AN35 VSS Power Other AV15 VSS Power Other AN5 VSS Power Other AV18 VSS Power Other AN8 VSS Power Other AV20 VSS Power Other AP12 VSS Power Other AV25 VSS Power Other AP13 VSS Power Other AV3 VSS Power Other apis vss ___ AV30 VSS Power Other AP22 VSS Power Other AV36 VSS Power Other AP23 VSS Power Other 5 VSS Power Other AP28 VSS Power Other B1 VSS Power Other AP3 VSS Power Other B12 VSS Power Other AP33 VSS Power Other B14 VSS Power Other AP38 VSS Power Other B17 VSS Power Other VSS Power Other B22 VSS Power Other AR11 VSS Power Other B27 VSS Power Other AR16 VSS Power Other B32 VSS Power Other AR21 VSS Power Other B7 VSS Power Other AR24 VSS Power Other C10 VSS Power Other AR26 VSS Power Other C15 VSS Power Other AR29 VSS Power Other C20 VSS Power Other AR31 VSS Power Other C25 VSS Power Other AR36 vsS C30 vss Power Other 86 Intel Itanium Processor 9300 Series and 9500 Series Datasheet intel Pin Listing Table3 1 PinList by Pin Name Sh
139. Processor 9300 Series and 9500 Series Datasheet intel Pin Listing Table 3 2 Pin List by Pin Number Sheet 5 Table 3 2 Pin List by Pin Number Sheet 6 of 32 of 32 m m Pin Name ba ek Direction ae Pin Name Direction AE27 RSVD AG5 vss Power Other AE28 SM_WP 6 FBDOSBOBP 4 Differential 29 Power Other AG7 vss Power Other AE30 RSVD AG8 XDPOCPD 1 _N 1 0 AE31 vss Power Other 9 XDPOCPD 3 _N 1 0 AE32 CSI3TPDAT 15 Differentia 10 XDPOCPD 5 _N 1 0 AE33 511 14 Differentia 0 AG11 XDPOCPFRAME_N 1 0 AE34 511 151 Differentia 12 vss Power Other AE35 CSI1TPDAT 15 Differentia AG13 CSI5TNDAT O Differential 6 VSS Power Other AG14 Power Other AE37 CSI IRNDAT 15 Differentia 15 VSS Power Other AE38 511 151 Differentia 16 515 31 Differential 1 FBDONBIBP 8 Differentia 17 VSS Power Other AF2 FBDONBIBN 8 Differentia 18 Power Other AF3 FBDONBIBN 7 Differentia 19 CSI5TNDAT 7 Differential AF4 VSS Power Other AG20 CSI5TPDAT 7 Differential 5 FBDOSBOCLKBPO Differentia 0 AG21 RSVD AF6 FBDOSBOBN 4 Differentia 22 VSS Power Other AF7 FBDOSBOBN 3 Differentia AG23 VSS Power Other AF8 FBDOSBOBP 3 Differentia 2
140. RSVD AL31 RSVD M13 RSVD AL8 amp RSVD M20 RSVD 11 RSVD M21 RSVD AM38 RSVD M36 RSVD 11 RSVD M4 RSVD AN38 RSVD P10 RSVD Intel Itanium RSVD Processor 9300 Series SVID CLK2 Intel RSVD Itanium Processor 9500 Series AR38 RSVD P27 RSVD AT2 RSVD R10 RSVD Intel Itanium AT37 RSVD Processor 9300 Series AT38 RSVD SVI D DATIO Intel Itanium Processor AU1 RSVD 9500 Series AU2 RSVD R27 RSVD AU3 RSVD T11 RSVD Intel tanium Processor 9300 Series AU36 RSVD SVID_ALERT_N2 Intel Itanium Processor AUS Reve 9500 Series 1 RSVD U4 RSVD Reve V27 RSVD AV35 RSVD V29 RSVD AV37 RSVD W10 RSVD AV38 RSVD W12 RSVD AVA W27 RSVD BS ROV Y10 RSVD B3 iud 29 SKTID O B36 gt 28 SKTID 1 RSVD 28 SKTID 2 RSVD 28 SM WP RSVD AT32 SMBCLK SMBus 1 0 Reve AR32 SMBDAT SMBus 1 0 82 Intel Itanium Processor 9300 Series 9500 Series Datasheet intel Pin Listing Table 3 1 Pin List by Pin Name Sheet 21 Table 3 1 Pin List by Pin Name Sheet 22 of 33 of 33 M Pin Name M Direction LUN Pin Name dem Direction AT30 SPDCLK 1 0 AG35 Power Other AT31 SPDDAT 1 0 AH12 Power Other Y12 SYSCLK Differential 22 Power Other 12 SYSCLK_N
141. Series Datasheet intel Pin Listing Table 3 1 Pin List by Pin Name Sheet 25 Table 3 1 Pin List by Pin Name Sheet 26 of 33 of 33 ae Direction SLM Pin Name Direction AB37 VSS Power Other AG7 VSS Power Other AB7 VSS Power Other AH10 VSS Power Other AC10 VSS Power Other AH15 VSS Power Other 11 VSS Power Other AH18 VSS Power Other AC30 VSS Power Other AH20 VSS Power Other AC35 VSS Power Other AH23 VSS Power Other AC36 VSS Power Other AH25 VSS Power Other AC5 VSS Power Other AH26 VSS Power Other AC7 VSS Power Other AH30 VSS Power Other AD10 VSS Power Other AH35 VSS Power Other AD28 VSS Power Other AH5 vss Power Other AD3 VSS Power Other AJ12 VSS Power Other AD33 VSS Power Other AJ13 VSS Power Other AD35 VSS Power Other AJ16 VSS Power Other AD38 VSS Power Other AJ18 VSS Power Other AD8 VSS Power Other AJ 23 vss Power Other 1 VSS Power Other 26 VSS Power Other AE10 VSS Power Other AJ 28 vss Power Other AE11 VSS Power Other AJ3 VSS Power Other AE31 VSS Power Other AJ33 VSS Power Other AE36 VSS Power Other AJ35 VSS Power Other AE6 VSS Power Other AJ38 VSS Power Other AE9 VSS Power Other AJ6 VSS Power Other AF28 VSS Power Other AJ8 VSS Power Other AF29 VSS Power Other AK1 VSS Power Other AF34 VSS Power Other AK11 VSS Power Other AF35 VSS Power Other AK14 VSS Power Ot
142. T 7 Differentia 133 CSIOTNDAT 10 Differentia AM36 CSI1IRNDAT 8 Differentia M34 CSIOTNDAT 11 Differentia AL37 CSI1RNDAT 9 Differentia 32 CSIOTNDAT 12 Differentia AJ37 511 10 Differentia l N34 CSI OTNDATT 13 Differentia 8 511 11 Differentia 834 CSIOTNDAT 14 Differentia AG36 511 12 Differentia 833 CSIOTNDAT 15 Differentia AF38 511 131 Differentia 033 CSI OTNDATT 16 Differentia 6 CSI1RNDAT 14 Differentia V32 CSIOTNDAT 17 Differentia 7 511 151 Differentia V34 CSI OTNDATT 18 Differentia 511 16 Differentia W32 CSIOTNDAT 19 Differentia 7 511 17 Differentia K34 CSIOTPCLK Differentia AA38 CSI 1RNDAT 18 Differentia 130 CSIOTPDAT O Differentia 8 511 191 Differentia H31 CSIOTPDAT 1 Differentia 7 CSI1RPCLK Differentia G30 CSIOTPDAT 2 Differentia 5118 0 Differentia E30 CSIOTPDAT 3 Differentia AV32 CSI IRPDAT 1 Differentia 132 CSIOTPDAT 4 Differentia AU34 CSI1RPDAT 2 Differentia 2 CSIOTPDAT 5 Differentia 511 31 Differentia CSIOTPDAT 6 Differentia AU35 CSI1RPDAT 4 Differentia G33 CSIOTPDAT 7 Differentia 5 511 5 Differentia H34 CSIOTPDAT 8 Differentia 7 511 6 Differentia 132
143. This is computed as absolute difference between average value of all UI with that of average of odd UI which in magnitude would equal absolute difference between average of all Ul and average of all even Ul 0 018 UI TX1UI Rj NoXtalk pin Rj value of 1 UI jitter With X talk off but on die system like noise present This extraction is to be done after software correction of DCD 0 008 UI TX1UI Dj NoXtalk pin pp Dj value of 1 01 jitter With X talk off but on die system like noise present 0 01 0 01 UI TXN UI Rj NoXtalkpin Rj value of N UI jitter With X talk off but on die system like noise present Here 1 N 9 This extraction is to be done after software correction of DCD 0 012 UI TXN UI Dj NoXtalkpin pp Dj value of N UI jitter With X talk off but on die system like noise present Here 1 N 9 Dj here indicated Djdd of dual dirac fitting after software correction of DCD 0 04 0 04 0 2 UI data clk skew pin Delay of any data lane relative to clock lane as measured at Tx output 0 5 0 5 UI T Rx data clk skew pin Delay of any data lane relative to the clock lane as measured at the end of Tx channel This parameter is a collective sum of effects of data clock mismatches in Tx and on the medium connecting Tx and Rx Forward CLK Rx input voltage sensitivity differential pp 3 5 150
144. V 41 29h 28h 00 29h 12 42 2Ah Core Voltage Tolerance 2 Hex digits Edge finger tolerance in mV 20 mV 0x14 High 43 2Bh Core Voltage Tolerance 2 Hex digits Edge finger tolerance in 20 mV 0x14 Low 44 2Ch RESERVED Hex Reserved for future use 0x00 45 2Dh Checksum Hex Add up by byte and take 2 s complement Uncore 46 2Eh Maximum Intel 6 bcd digits Maximum Intel QuickPath 4 8 GT s 004800 QuickPath Interconnect Interconnect Link Transfer rate 2Eh 00 47 2Fh Link Transfer Rate for this part 5 _ 2Fh 48 48 30h 30h 00 Intel Itanium Processor 9300 Series and 9500 Series Datasheet 145 intel System Management Bus I nterface Table 6 1 Processor I nformation ROM Data Sheet 3 of 6 Sec Offset Field Name Data Type Description Example 49 31h Minimum Intel 6 bcd digits Minimum Intel QuickPath 4 8 GT s 004800 QuickPath Interconnect Interconnect Link Transfer rate 31h 00 50 32h Link Transfer Rate for this part in MT s 32h 48 51 33h 33h 00 52 34h Intel QuickPath 4 8 bit ASCII Hex Intel QuickPath Interconnect 01 0 HER Interconnect version characters version number supported by 34h 0x30 Number processor 35h Ox2E 54 36h 36h 0x31 55 37h 37h 0x30 56 38h Memory Support flags Hex Bit 0 FBD1 Support LSB 0x01 FB DIMM 1 only Bit 1 MB1 Support 0x02 1 only Bit 2 MB2 Support 0x03
145. VROUTPUT_ENABLEO 7 CSI1RPCLK Differentia 1 VRPWRGD Intel Itanium Processor AK38 5 1 9300 Series VR_READY ALL FBDONBIAN 10 Differentia Bcc Pon 89 AL2 FBDONBIAP 10 Differentia 2 VSS Power Other A FEDONBIANIS Differentia l AM3 FBDONBIAP 9 Differentia AM4 VCCIO_FBD Power Other AUS 5 Differentia 5 FBDONBIBNIA Differentia 16 5 5 Differentia 6 FBDONBIBP 4 Differentia AL7 FBDOREFSYSCLKP Differentia 7 VSS Power Other AR REND AM8 FBDONBIBP 1 Differentia Ale Power FBDONBIBN 1 Differentia AL10 FBDONBIBP 14 Differential 10 141 Differentia 11 TRIGGER O _N 1 0 11 RSVD AL12 CSI5RNDAT O Differential 12 vss Power Other Intel Itanium Processor 9300 Series and 9500 Series Datasheet 93 intel Pin Listing Table 3 2 Pin List by Pin Number Sheet Table 3 2 Pin List by Pin Number Sheet 11 of 32 12 of 32 MN Pin Name Direction Bae Pin Name A Direction AM13 CSI5RNDAT 1 Differentia 15 VSS Power Other AM14 Power Other AN16 CSI 31 Differentia 15 CSI3RPDAT 2 Differentia 17 CSI 3RNDAT 3 Differentia 16 CSI 3RNDAT 2 Differentia 18 CSI 3RNDAT O Differentia 17
146. VSS K L VSS L M VCCUNCORE M N VCCUNCORE N P VCCUNCORE P R VCCUNCORE R T VSS T U VSS U vss V VCCUNCORE Ww Y VCCUNCORE Y AA VCCUNCORE AA AB VCCUNCORE AB AC vss AC AD vss AD AE vss AE AF VCCUNCORE AF AG VCCUNCORE AG AH VCCUNCORE AH AJ VCCUNCORE vss AK AL VSS AL AM VCCCORE AM AN VCCCORE AN AP vss AR AT vss AT 1 Intel Itanium Processor 9300 Series 9500 Series Datasheet 107 intel Table 3 4 Top Side J1 Connector Two Dimensional Table Intel Itanium Processor 9500 Series Sheet 3 of 3 1 2 3 4 AU VSS VSS AU AV CPU PRESA N NO CONNECT AV NO CONNECT NO CONNECT aw YROUTPUT_ENABLEO VCCUNCORE P AY PROCTYPE 0 VR PROCTYPE 1 AY 1 2 3 4 3 2 2 Top Side J2 Connector Two Dimensional Table 3 2 2 1 Top Side J2 Connector Two Dimensional Table for the Intel Itanium Processor 9300 Series Table 3 5 is a two dimensional table of the Intel Itanium Processor 9300 Series Processor package top side J2 connector Table 3 5 Top Side J2 Connector Two Dimensional Table Intel Itanium Processor 9300 Series Sheet 1 of 2 1 2 3 4 VID VCCUNCORE 1 VID VCCUNCORE 3 A B VID VCCUNCORE 2 NO CONNECT VID VCCUNCORE 5 B NO CONNECT C VID VCCUNCORE 4 VID 6
147. WRGOOD and cold reset period The BOOTMODE 2 0 and FLASHROM CFG 1 0 pins are sampled during the assertion of all resets except warm logic resets Intel Itanium Processor 9300 Series 9500 Series Datasheet 69 intel Electrical Specifications Figure 2 20 RESET_N and SKITID Timing for Warm and Cold Resets COLD RESET PWR CYCLE OR PWRGOOD WARM STATE OR WARM LOGIC RESETS SYSCLK SKTID 1 0 SKTID 2 FLASHROM CFG 1 0 BOOTMODE 2 0 XOXO IER 3399993 9A Error Reset Warm Logic if SKTID 0 1 0000000000000000 T12 strap values Table 2 40 RESET_N and SKTID Timing Sheet 1 of 2 asserted Parameter Description MIN MAX UNIT Tl PWRGOOD deasserted delay to RESET_N 0 200 ns asserted PWRGOOD asserted delay to RESET N T2 deasserted Intel Itanium Processor 9300 10 ms Series PWRGOOD asserted delay to RESET N T2 deasserted Intel Itanium Processor 9500 15 ms Series RESET_N setup and hold relative to SYSCLK asserted 500 ps T4 RESET_N deasserted pulse width 8 SYSCLK cycles RESET_N asserted pulse width Intel Itanium 5 Processor 9300 Series 10 ma RESET_N asserted pulse width Intel Itanium 5 Processor 9500 Series 15 ms T6 SKTID 2 0 as rst modifier error hold after 0 ns PWRGOOD deasserted SKTID 2 0 as socket id LRGSCLSYS T7 BOOTMODE 2 0
148. a 2 VSS Power Other AD10 VSS Power Other AB33 CSI 3TNDAT 17 Differential AD11 VCCIO Power Other AB34 CSI TTNDAT 17 Differential AD12 RSVD AB35 CSI TTPDAT 17 Differential AD27 RSVD AB36 VCCIO Power Other AD28 VSS Power Other AB37 VSS Power Other AD29 RSVD AB38 CSI 1RPDAT 18 Differential AD30 RSVD 1 11 Differential AD31 Power Other AC2 VCCIO FBD Power Other AD32 CSI3TNDAT 15 Differentia FBDOSBOBP 6 Differential AD33 VSS Power Other AC4 FBDOSBOBN 5 Differential AD34 CSI1TPDAT 16 Differentia 5 VSS Power Other AD35 VSS Power Other AC6 VCCIO_FBD Power Other AD36 CSI1RNDAT 16 Differentia VSS Power Other AD37 CSI1RPDAT 16 Differentia AC8 FBD1NBIDN 14 Differential AD38 VSS Power Other AC9 FBDIREFSYSCLKP Differential 1 vss Power Other AC10 VSS Power Other AE2 FBDONBI BP 9 Differentia 11 VSS Power Other AE3 FBDONBI BN 9 Differentia 12 RSVD AE4 VCCIO_FBD Power Other AC27 RSVD AE5 FBDOSBOCLKBNO Differentia 28 RSVD AE6 vss Power Other AC29 RSVD AE7 FBDOSBOBP 9 Differentia VSS Power Other AE8 VCCIO_FBD Power Other AC31 CSI 3TNDAT 16 Differential 9 VSS Power Other AC32 CSI 3TPDAT 16 Differential 10 VSS Power Other AC33 CSI 3TPDAT 17 Differential 11 VSS Power Other AC34 CSI1TNDAT 16 Differential 12 RSVD 90 Intel Itanium
149. a 21 CSI 2RNCLK Differentia B31 CSI2RPDAT 18 Differentia 122 5128 0 Differentia C32 CSI2RPDAT 19 Differentia Intel Itanium Processor 9300 Series and 9500 Series Datasheet 75 intel Pin Listing Table 3 1 Pin List by Pin Name Sheet 7 Table 3 1 Pin List by Pin Name Sheet 8 of 33 of 33 Direction Direction H29 CSI2TNCLK Differentia V31 CSI2TPDAT 18 Differentia 23 CSI2TNDAT 0 Differentia W31 CSI 2TPDAT 19 Differentia G24 CSI2TNDAT 1 Differentia AU21 CSI3RNCLK Differentia 25 CSI2TNDAT 2 Differentia 18 5138 0 Differentia 024 CSI2TNDAT 3 Differentia AL17 CSI 3RNDAT 1 Differentia 26 512 41 Differentia 16 CSI3RNDAT 2 Differentia l F26 512 51 Differentia 17 CSI 3RNDAT 3 Differentia 29 CSI2TNDAT 6 Differentia 19 CSI3RNDAT 4 Differentia 26 512 71 Differentia 19 CSI 3RNDAT 5 Differentia 28 512 81 Differentia 17 CSI3RNDAT 6 Differentia 27 512 91 Differentia AU18 CSI3RNDAT 7 Differentia 28 512 101 Differentia 19 CSI3RNDAT 8 Differentia 29 512 11 Differentia 20 CSI3RNDAT 9 Differentia 512 121 Diffe
150. ad FBD1NBICN 7 Differentia 7 FBD1NBIDP 2 Differentia 611 FBDINBICN 8 Differentia V6 FBD1NBI DP 3 Differentia G8 FBDINBICN 9 Differentia 06 FBD1NBIDP 4 Differentia 9 FBD1NBICN 10 Differentia T6 FBD1NBI DP 5 Differentia F11 FBD1NBICN 11 Differentia 6 FBD1NBIDP 6 Differentia 112 FBD1NBI CN 12 Differentia 15 FBD1NBIDP 7 Differentia 9 FBD1NBICN 13 Differentia 7 FBD1NBI DP 8 Differentia Y8 FBD1NBI CN 14 Differentia 5 FBD1NBIDP 9 Differentia w9 FBDINBICP 0 Differentia 16 FBD1NBI DP 10 Differentia V8 FBDINBICP 1 Differentia 7 FBD1NBIDP 11 Differentia FBDINBICP 2 Differentia 6 FBD1NBI DP 12 Differentia 09 FBDINBICP 3 Differentia T5 FBD1NBI DP 13 Differentia R8 FBDINBICP 4 Differentia 8 FBD1NBIDP 14 Differentia 9 FBDINBICP 5 Differentia AD9 FBDIREFSYSCLKN Differentia K8 FBD1NBICP 6 Differentia 9 FBD1REFSYSCLKP Differentia J10 FBD1NBICP 7 Differentia 8 FBD1ISBOCLKCNO Differentia 11 FBDINBICP 8 Differentia 7 FBD1SBOCLKCPO Differentia FBDINBICP 9 Differentia 4 FBD1SBOCLKDNO Differentia 19 FBD1NBICP 10 Differentia FBDISBOCLKDPO Differentia 80 Intel Itanium Processor 9300 Series 9500 Series Datasheet intel
151. annel 2 Step 2 calculate A B use scope Math function subtract channel 1 channel 2 Table 2 16 FMB 130W Current Specifications for the Intel Itanium Processor 9300 Series Symbol Parameter Max Units Notes cc for core 151 A TDC Thermal Design Current for Core 100 A 1 sTEP Load step for 95 A 2 dicc CORE dt Slew rate for core at Ararat output 154 A us I cc UNCORE for uncore 50 A UNCORE Thermal Design Current for Uncore 43 A 3 UNCORE STEP Max Load step for uncore 22 A 4 dl CC UNCORE dt Slew rate for uncore at Ararat output 75 A us ICC for processor 1 0 22 A 5 Analog ICC for processor Analog 4 A 1 _5 for supply 200 mA Notes 1 CORE TDC is the sustained DC equivalent current that the processor core is capable of drawing indefinitely and should be used for the Ararat voltage regulator temperature assessment The Ararat voltage regulator is responsible for monitoring its temperature and asserting the VR_FAN_N VR THERMALERT N VR THERMTRIP N signals sequentially to inform the processor and platform of a thermal excursion Of the three signals only VR THERMALTERT N is monitored by the processor Please see the Ararat Voltage Regulator Module Design Guide for further details The processor is capable of drawing CORE indefin
152. as 130A peak to peak ICC UNCORE TDC is the sustained DC equivalent current that the processor uncore is capable of drawing indefinitely and should be used for the Ararat voltage regulator temperature assessment The Ararat voltage regulator is responsible for monitoring its temperature and asserting the VR FAN VR THERMALERT THERMTRIP signals sequentially to inform the processor and platform of a thermal excursion Of the three signals only VR THERMALTERT is monitored by the processor Please see the Ararat Voltage Regulator Module Design Guide for further details The processor is capable of drawing ICC UNCORE TDC indefinitely This parameter is based on design characterization and is not tested Figure 2 9 Processor cc core Load Current versus Time 42 IMax ITDC Sustained Current A 0 01 0 1 1 10 Time Duration us 100 During system power on the pulse inrush ICC UNCORE STEP can be as high as 40A peak to peak The ICC 10 current specification applies to the total current from VCCIO pins 1000 Intel Itanium Processor 9300 Series and 9500 Series Datasheet Electrical Specifications tel 2 6 2 Flexible Motherboard Guidelines for the Intel I tanium Processor 9500 Series The Flexible Motherboard FMB guidelines are estimates of the maximum ratings that the processor will have over certain time periods The ratings are only estimates as actual specifications for future
153. ation 1 1 1 1 nnn 144 6 2 2 ERRi 149 6 2 3 Scratch EEPROM Supported SMBus Transactions 150 6 3 Memory Component 2 150 6 4 PIROM Field 2 eem nennen nnn 152 6 41 152 6 4 2 Processor 152 6 4 3 Processor Core 152 6 4 4 Processor Uncore Data eerie har erri E 153 6 45 CACHE eden E aiit pe Ra RR RR UAR 154 6 4 6 Package exerce 155 6 4 7 Part Number Data ico nana lama RE E EE 155 6 4 8 Thermal Reference Data 155 6 4 9 Feature Data tale Rd 156 6 4 10 Other Data 1 12 4 2 4 4 1 6100 aenean nnne nnn nnn 157 6 4 11 tad AG
154. capacitance and 1 mOhms minimum impedance at the processor socket The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the scope probe 6 Warm boot reset only in downward direction 7 Min and Max range is spec at the die for both VCCIO This range includes 50 mV p p AC noise It also includes any DC and AC tolerances at package pin 8 The FMB remote sense tolerance is 2 5 for DC to 20 MHz at the package where 1 5 is allotted for a DC to 1 MHz range and an additional 1 for 1 MHz to 20 MHz Similarly 6 4 is allotted for DC to 20 MHz at the die It is expected that VCCIO regulators meet 1 5 at the remote sense location based on the general remote sense termination point location as described in Figure 2 16 VR Sense Point Representation For future processor compatibility it is strongly recommended that the platform query the PIROM to assure VCCIO is set to the appropriate level prior to powering up the VCCIO supply 9 All voltage regulation measurements taken at remote sense termination points 10 For peak to peak Ripple and Noise R amp N measured with full bandwidth BW of the scope Min 1 GHz BW scope is required set scope diff probe and the scope at full BW capture waveform A channel 1 11 For peak to peak Ripple and Noise R amp N measured above 1 MHz Step 1 set both scope diff probe and or the scope at 1 MHz BW limit capture waveform B ch
155. cessor 9500 Series 0 02 0 01 0 0 02 0 03 0 04 0 05 0 06 0 07 0 08 0 09 0 1 0 11 Normalized 0 01 lt VccCore 1 4 Tolerance Band 10 15 e V 8R DOVex V amp Norrralized V V AOMn V 25 30 35 40 45 A Intel Itanium Processor 9300 Series 9500 Series Datasheet 51 intel 2 6 5 1 2 6 5 2 2 6 5 2 1 Table 2 25 52 Electrical Specifications Overshoot and Undershoot Guidelines Overshoot or undershoot is the value of the maximum voltage above or below VSS The overshoot and undershoot specifications limit transitions beyond VCCIO or VSS due to the fast signal edge rates The processor can be damaged by single and or repeated overshoot or undershoot events any input output or 1 0 buffer if the charge is large enough that is if the overshoot or undershoot is great enough Determining the impact of an overshoot or undershoot condition requires knowledge of the magnitude the pulse duration and the activity factor AF Permanent damage to the processor is the likely result of excessive overshoot or undershoot Overshoot Undershoot Magnitude Pulse Duration and Activity Factor Magnitude describes the maximum potential difference between a signal and its voltage reference
156. common mode level 125 350 mV 2 VRx data cm ripple Receiver data common mode ripple 0 100 Vnx clk cm pin Receiver clock common mode level 175 350 mV Vnx clk cm ripple pin Receiver clock common mode ripple 0 100 MVp p VRX eye data pin Minimum eye height at pin for data 200 mV 4 VRX eye clk pin Minimum eye height at pin for 225 mV 5 30 Intel Itanium Processor 9300 Series and 9500 Series Datasheet Electrical Specifications intel Table 2 6 Intel Itanium Processor 9300 Series Receiver Parameter Values for Intel QuickPath I nterconnect and ntel SMI Channels 4 8 GT Sheet 2 of 2 Symbol Parameter Min Nom Max Units Notes Minimum eye width at pin for clk data 0 6 Ul 4 BER ane Bit Error Rate per lane valid for 4 8 and 6 4 GT s 1 0E 14 Events SMI Bit Error Rate per lane valid for 4 8 6 4 GT s 1 0E 12 Events Notes Li Parameter value at 1 4 Intel Refclk 2 Parameter value at full Intel Refclk 3 termination small signal resistance tolerance over the entire signalling voltage range sha 4 HVM guaranteed error free value for stressed PRBS signaling across PVT Link BER is the dominant spec of which eye dimensions are only one factor and improving another factor could compensate for eye height or width not exceed 5 ohms with regard to the average of the values measured in the high
157. cur if the Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series go into thermal trip The part that shuts down may still have pending snoops or memory reads that the other sockets in the partition may have requested Once THERMTRIP_N is asserted the Intel Itanium9 Processor 9300 Series and Intel Itanium Processor 9500 Series remain stopped until RESET_N is asserted If the die temperature has dropped below the trip level a RESET N pulse can be used to reset the processor If the temperature has not dropped below the trip level the processor Intel Itanium Processor 9300 Series and 9500 Series Datasheet 137 m tel Thermal Specifications Note 5 1 7 5 1 8 5 1 9 138 will continue to drive THERMTRIP_N and remain stopped It is recommended to allow the processor case temperature to drop below the specified design target before issuing a reset to the processor Please see Section 5 2 and Table 5 3 for details on the case temperature In a partitioned system sockets in the same partition are in the same coherency domain so they cannot continue to operate if even one of the processors asserts THERMTRIP_N and shuts down Moreover a cold reset is required to get the part back up after a THERMTRIP event Because cold reset will reset all the sockets in the partition the other sockets cannot continue running without a reset event PROCHOT The temperature at PROCHOT represents the maximu
158. e DC AC in mV 61 3Dh Low 27 1Bh VCCIO Voltage 6 bcd digits Voltage in six 4 bit Hex digits in 1 11250V 001125 mV 2 28 1 1 25 1 11 29 1Dh 1Dh 00 30 1Eh Voltage Tolerance 2 Hex digits Total tolerance DC AC in mV 28 mV Ox1C High 31 1Fh Voltage Tolerance 2 Hex digits Total tolerance DC AC in mV 28 mV Ox1C Low 32 20h RESERVED Hex Reserved for future use 0x00 33 21h Checksum Hex Add up by byte and take 2 s complement Core 34 22h Architecture Revision 2 Hex Digits From CPUID Taken from CPUI D 3 archrev 35 23h Processor Core Family 2 Hex Digits From CPUID Taken from CPUID 3 family 36 24h Processor Core Model 2 Hex Digits From CPUID Taken from CPUID 3 model 37 25h Processor Core Stepping 2 Hex Digits From CPUID Taken from CPUID 3 revision 38 26h Boost Core Frequency 4 bcd digits Maximum Specified operating 1733 MHz 1733 39 27h Intel Itanium Intel Itanium amp frequency of this part in MHz 26h 33 Processor 9300 Series Processor 9300 Intel Itanium Processor 9300 27h 17 Series Series Intel Itanium amp Processor 9300 Series Core Count 0x26 2 bcd digits 0x26 RESERVED 0x27 2 Hex digits Number of available cores in the 26h 08 Intel Itanium amp 2 27h 0x00 Processor 9500 Series Intel Itanium Intel Itanium Processor 9500 Processor 9500 Series Series 40 28h Core Voltage ID 4 bcd digits Voltage in four 4 bit Hex digits in 1200 mV 1200h m
159. e DT readout will have a positive value The DT has a limited range It will report out the value of its upper or lower limits when it has reached the limits and set QR CSR IPF THERM STATUS valid 170 Thermal Sensor Accuracy Distribution for the Intel Itanium Processor 9300 Series Table 5 1 shows the processor thermal sensor accuracy with respect to the DT readout for the an Intel tanium Processor 9300 Series The margin of error is relative to PROCHOT and represents the typical 3 sigma range This data is for a large sample of parts It should be noted that a particular part should be consistent across the entire operating range Thermal Sensor Accuracy Distribution for the ntel Itanium Processor 9300 Series Sheet 1 of 2 DT Readout RM 0x83 0x80 0x00 0x07 1 0x08 OxOE 2 0 14 3 0 15 0 1 4 0 1 0 22 5 0 23 0 29 6 Intel Itanium Processor 9300 Series 9500 Series Datasheet Thermal Specifications intel Table 5 1 Thermal Sensor Accuracy Distribution for the Intel Itanium Processor 9300 Series Sheet 2 of 2 DT Readout 4 4 0x2A 0x30 7 0 31 0 37 8 0 38 9 0 45 10 5 1 1 2 Thermal Sensor Accuracy Distribution for the Intel tanium Processor 9500 Series Table 5 2 shows the processor thermal sensor accuracy with respect to the DT read
160. e Select TMS is a J TAG specification support signal used by debug tools TRI GGER 1 0 TRST N TRIGGER 1 0 pins are needed for XDP connectivity Test Reset TRST resets the TAP logic TRST must be driven electrically low during power on Reset VCC33 SM VCC33 SM is a 3 3 V supply to the processor package required for the PIROM interface on the processor package and also Flash device This pin must be routed to a 3 3 V supply 164 Intel Itanium Processor 9300 Series 9500 Series Datasheet Signal Definitions Table 7 1 intel Signal Definitions for the Intel Itanium Processor 9300 Series and Intel Itanium 9500 Series Sheet 7 of 8 Name Type Description VCCA VCCA provides 41 8 V isolated power supply to the analog portion of the internal PLL s Refer to the Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series Platform Design Guide for routing decoupling recommendations for VCCA VCCCACHE This provides power to the Cache on the Intel Itanium 9300 Processor Series This is on the top of the package and is driven by the Ararat Voltage Regulator Actual value of the voltage is determined by the settings of VID VCCCACHE 5 0 VCCCACHESENSE VSSCACHESENSE Remote sense lines used by the Ararat Voltage Regulator to sense VCCCACHE die voltage The Voltage Regulator should not draw more than 0 1 from these pads
161. e either 1 below all applicable substrate thresholds as proposed by the EU or 2 an approved pending exemption applies RoHS implementation details are not fully defined and may change Package Materials Component Material Integrated Heat Spreader IHS Nickel Plating over Copper Substrate Fiber Reinforced Resin Package Lands Gold Plating over Nickel Package Markings Bottom side marks on the package substrate provide the necessary processor identification and tracking information This information is captured in Table 4 5 and their locations are illustrated in Figure 4 10 1248 FCLGA Package Marking Zones Zone Engineering Samples Production Units Zone A 2D Matrix Mark VID Zone B Visual I dentification VID Mark Zone C Line 1 INTEL CONFI DENTIAL Line 1 Product Name Line 2 Mask and Copy Right Date Codes Line 2 Mask and Copy Right Date Codes Lead Free product designator Zone E Intel Zone F Finish Process Order FPO and Serial Zone Processor Zone H 2D Matrix Mark Finish Process Order FPO and Serial Notes 1 VID Visual Identification Is a unique number which can be used for the purpose of tracking the processor It is used by Intel to retrieve processor related information 2 FPO Finish Process Order Is a unique number It can be used for tracking purposes It is used by Intel to retrieve processor and shipping order information
162. e for the Intel Itanium Processor 9300 Series The VID VCCCACHE specification for the processor is supported by the Ararat Regulator Module Design Guide The voltage set by the VID VCCCACHE value is the maximum VCCCACHE voltage allowed by the processor Individual processor CVID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID VCCCACHE settings Intel Itanium Processor 9300 Series 9500 Series Datasheet Electrical Specifications tel The processor uses the value to support automatic selection of the power supply voltages Table 2 38 specifies the voltage level corresponding to the state of VID VCCCACHE A 1 in this table refers to a high voltage level and a refers to a low voltage level See the Ararat Regulator Module Design Guide for more details Table 2 38 Cache VID_VCCCACHE Voltage dentification Definition for Ararat eae bea TER ae Ww Hex VID5 VID3 VID2 VIDO wv oo o 0 0 0 0 0 OFF 20 1 0 0 0 0 12125 01 0 0 0 0 0 1 1 6000 a 4 0 0 0 0 1 1 2000 02 0 0 0 0 1 15875 22 1 0 0 0 1 1 1875 03 0 0 0 0 1 1 1 5750 23 1 0 0 0 1 1 1 1750 04 o 0 0 1 0 0 1 5625 24 1 0 0 1
163. e full bandwidth VCCA Processor analog supply voltage AC 1 8 15 mV 9 10 tolerance for noise 1MHz VCCA Processor analog supply voltage Total 1 739 1 8 1 861 V DC spec AC tolerance VCCA Ramp Min time allowed to ramp VCCA from 1096 1 10 ms to 90 typical value VCC33 SM 3 3 V supply voltage 3 135 3 3 3 465 V Notes 1 The voltage specification requirements are measured across the VCCUNCORESENSE and VSSUNCORESENSE pins using oscilloscope set to a 100 MHz bandwidth and probes that are 1 5 pF maximum capacitance and 1 mOhms minimum impedance at the processor socket The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the scope probe 2 These voltages are target only A variable voltage source should exist on systems in th e event that a different voltage is required See the Ararat 11 Voltage Regulator Module Design Guide for more information 3 Uncore and Core voltage and Current Rating are at the Package Pad 4 The voltage specification requirements are measured across the VCCCORESENSE and VSSCORESENSE pins using an oscilloscope set to a 100 MHz bandwidth and probes that are 1 5 pF maximum capacitance and 1 mOhms minimum impedance at the processor socket The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the scope probe 5 Warm boot reset only in downward direction 6
164. e m Pin Name BEC Direction AK11 VSS Power Other AL13 CSI5RPDAT O Differential 12 RSVD AL14 VSS Power Other AK13 VCCIO Power Other AL15 VCCIO Power Other AK14 VSS Power Other AL16 CSI3RPDAT 1 Differential 15 CSI5TPDAT 2 Differential 17 CSI 3RNDAT 1 Differential 16 VSS Power Other AL18 VSS Power Other AK17 Power Other AL19 VSS Power Other AK18 CSI5TNDAT 6 Differential 120 CSI3TNDAT O Differential 19 CSI5TPDAT 6 Differential AL21 CSI5TNDAT 9 Differential 20 51 0 Differential 122 CSI5TPDAT 9 Differential 21 VSS Power Other AL23 CSI3TPDAT 2 Differential 22 CSI5TPCLK Differential 0 AL24 VSS Power Other AK23 Power Other AL25 Power Other AK24 VSS Power Other AL26 511 0 Differentia AK25 VSS Power Other AL27 CSI1TNDAT O Differentia AK26 VSS Power Other AL28 CSI1TNDAT 2 Differentia 27 CSI3TPDAT 9 Differential 129 VSS Power Other AK28 CSI3TPCLK Differential AL30 511 51 Differentia 29 CSI 3TNCLK Differential 1 RSVD AK30 VSS Power Other AL32 CSI1TPDAT 9 Differentia AK31 VSS Power Other AL33 511 91 Differentia 2 CSI1TPCLK Differential AL34 VSS Power Other AK33 CSI1TNDAT 10 Differential AL35 VCCIO Power Other AK34 CSI1TPDAT 10 Differential AL36 CSI1RPDAT 9 Differential 5 VSS Power Other AL37 CSI IRNDAT 9 Differential 6 VSS Power Other AL38
165. ection key cache Before a memory access including A 32 is permitted the processor compares a translation s key value against all keys contained in the PKRs If a matching key is not found the processor raises a Key Miss fault If a matching Key is found access to the page is qualified by additional read write and execute protection checks specified by the matching protection key register If these checks fail a Key Permission fault is raised Upon receipt of a Key Miss or Key Permission fault software can implement the desired security policy for the protection domain Some processor models may implement additional protection key registers and protection key bits Unimplemented bits and registers are reserved Please see the processor specific documentation for further information on the number of protection key registers and protection key bits implemented on the processor I ntel Itanium Processor 9500 Series Firmware Diagram Operating System Software Bon mgmt NT A A ot plug runtime ransfers a M Services Handoff to OS Instruction entrypoints P na Unified Extensible Firmware Interface UEFI N SAL S _ procedure gt OS Bog Interrupts Advanced Selection traps E Configuration faults and Power System Abstraction Layer Interface SAL PAL calls Transfe
166. ectively identifying both the single ended and the differential signalling pins The overshoot and undershoot values assume an activity factor of 10096 and a pulse width of 2596 over the signal pulse width The tables also include the absolute maximum and minimum values beyond which the processor is not guaranteed to operate properly These values assume a pulse width of 196 and an activity factor of 10096 Overshoot and Undershoot Specifications for the Intel Itanium Processor 9300 Series Overshoot and Undershoot Specifications For Differential I ntel QuickPath I nterconnect and Intel SMI and Single Ended Signals for the Intel tanium Processor 9300 Series Sheet 1 of 2 Symbol Parameter Min Max Unit VMAX OS SE Overshoot for single ended signals 1 45 VMIN US SE Undershoot for single ended signals 0 247 V VABSMAX OS SE Absolute Max for single ended signals 1 6 V VABSMIN US SE Absolute Min for single ended signals 0 425 V Intel Itanium Processor 9300 Series 9500 Series Datasheet Electrical Specifications Table 2 25 Overshoot and Undershoot Specifications For Differential Intel QuickPath Interconnect and Intel SMI and Single Ended Signals for the Intel Itanium Processor 9300 Series Sheet 2 of 2 2 6 5 2 2 Table 2 26 2 6 6 Table 2 27 intel Symbol Parameter Min Max Unit VMAX OS DIFF Overshoot for Intel and Intel S
167. eet 29 Table 3 1 Pin List by Pin Name Sheet 30 of 33 of 33 MU LE Pin Name me o a Direction 5 VSS Power Other G17 VSS Power Other C38 VSS Power Other G2 VSS Power Other C5 VSS Power Other G22 VSS Power Other D10 VSS Power Other G27 VSS Power Other D13 VSS Power Other G32 VSS Power Other D14 VSS Power Other G37 VSS Power Other D18 VSS Power Other G7 VSS Power Other D23 VSS Power Other H10 VSS Power Other D25 VSS Power Other H15 VSS Power Other D28 VSS Power Other H20 VSS Power Other D3 VSS Power Other H25 VSS Power Other D30 VSS Power Other H30 VSS Power Other D31 VSS Power Other H35 VSS Power Other D33 VSS Power Other H4 VSS Power Other D8 VSS Power Other H5 vss Power Other El VSS Power Other 113 VSS Power Other E11 VSS Power Other J18 VSS Power Other E13 VSS Power Other 123 VSS Power Other E15 VSS Power Other 124 VSS Power Other E16 VSS Power Other J25 VSS Power Other E21 VSS Power Other J28 VSS Power Other E26 VSS Power Other J3 VSS Power Other E28 VSS Power Other J33 VSS Power Other E31 VSS Power Other 138 VSS Power Other E36 VSS Power Other VSS Power Other E6 VSS Power Other 6 VSS Power Other 212 VSS Power Other 8 VSS Power Other F13 VSS Power Other K1 VSS Power Other 14 VSS Power Other K11 VSS Power Other F15 VSS Power Other K16 VSS Power Other F19 VSS Power Other K21 VSS Power Other F22 VSS Power Other K22 VSS Power Other F24 VSS Power Other K23 VSS Power Other
168. el QuickPath Interconnect and Intel SMI Specifications for 4 8 tenu rta 28 2 4 2 Intel Processor 9500 Series Requirements for Intel QuickPath Interconnect for 4 8 and 6 4 5 32 2 4 3 Intel Itanium Processor 9500 Series Processor Requirements for Intel SMI Specifications for 6 4 5 2 220004 2 37 2 5 Processor Absolute Maximum 05 0 38 2 5 1 Intel Itanium Processor 9300 Series Absolute Maximum Ratings 39 2 5 2 Intel Itanium Processor 9500 Series Absolute Maximum Ratings 39 2 6 Processor DC Specifications 1 eem sese eese 39 2 6 1 Flexible Motherboard Guidelines for the Intel Itanium Processor 9300 1 nnns 40 2 6 2 Flexible Motherboard Guidelines for the Intel Itanium Processor 9500 5 EE ERR esse KORR ERAT 43 2 6 3 Intel Itanium Processor 9300 Series Uncore Core and Cache Tolerances 44 2 6 4 Intel Itanium Processor 9500 Series Uncore and Core Tolerances 49 2 6 5 Overshoot and Undershoot Guidelines esse 52 2 6 6 Signal DC Specificatlohs kuris iroi ceder eene PE ED 53 2 6 7 Motherboard Socket Specification for VR S
169. election of VCCCORE VCCUNCORE and VCCCACHE by the Intel Itanium 9300 Processor Series The VCCCORE VCCUNCORE and VCCCACHE Voltage Regulator Ararat outputs must be disabled prior to these pins becoming invalid The VID pins are needed to support processor voltage specification variations The VCCCORE VCCUNCORE and VCCCACHE Voltage Regulator Ararat outputs must supply the voltage that is requested by these pins or disable itself VR FAN N 1 0 This signal is open drain collector driven by Ararat Voltage Regulator into a pad at the top of the processor package and out through a pin at the bottom of the processor package When asserted it indicates that the temperature on the Ararat solution is approximately 10 below the VR_THERMTRIP_N limit The Processor cores do not monitor or respond to this signal The Platform could monitor this pin to implement thermal management such as controlling fan speed airflow See Ararat 170W Voltage Regulator Module Design Guide and or Ararat 11 Voltage Regulator Module Design Guidefor platform specific requirements VR_PROCTYPE 1 0 VR_PROCTYPE output informs the Ararat Voltage Regulator the processor type These pins are 00 Intel Itanium 9300 Processor Series and 01 for the Intel Itanium 9500 Processor Series These pads are located at the top of the package Future processors may use different bit configurations for this bus VR THERMALERT N 1 0 This
170. emory latency 160 general and 128 floating point registers supporting register rotation Register stack engine for effective management of processor resources Support for predication and speculation Extensive RAS features for business critical applications for example Machine check architecture with extensive ECC and parity protection with firmware first error handling End to end error detection On chip thermal management and power management Built in processor information ROM PIROM Built in programmable EEPROM Hot Plug Socket Hot add and hot removal support Double Device Data Correction DDDC for x4 DRAMs plus correction support of a single bit error Single Device Data Correction SDDC for x8 m x4 DRAMs plus correction of a single bit error Intel QuickPath Interconnect Dynamic Link Width Reduction Intel QuickPath Interconnect Clock Fail Safe Feature Intel QuickPath Interconnect Hot Add and Removal Memory DIMM and Rank Sparing Memory Scrubbing Memory Mirroring and Memory Migration Intel Itanium Processor 9300 Series and 9500 Series Datasheet Intel Turbo Boost Technology featuring sustained boost Architected firmware stack including PAL and SAL support Directory based and source based coherency protocol Intel poisoning viral containment and cleanup Two On die Memory Controllers Each mem
171. ense 57 2 7 Core and Uncore Voltage 57 2 7 1 Core and Uncore Voltage Identification for the Intel Itanium Processor 9300 2 2020 002 58 2 7 2 Core and Uncore Voltage Identification for the Intel Itanium Processor 9500 Series 59 2 8 Cache Voltage Identification Intel Itanium Processor 9300 Series only 62 2 9 RSVD Unused and DEBUG 4 4 04 4 4414 nnn nnn 63 2 10 Mixing 50 ee EDI 64 2 11 Supported Power up Voltage Sequence 00 nemen 64 2 11 1 Supported Power up Voltage Sequence for the Intel Itanium Processor 9300 Series 0 66 2 11 2 Supported Power up Voltage Sequence for the Intel Itanium Processor 9500 Series 67 2 11 3 Power up Voltage Sequence Timing 68 2 12 Supported Power down Voltage Sequence 68 2 13 Timing Relationship Between RESET and 5 69 Intel Itanium Processor 9300 Series and 9500 Series Datasheet 3 2 14 Test Access Port Connection 71 3 Listing ji ee i ies Casts ian 73 3 1 Proc
172. entia 22 CSI5TPCLK Differentia G16 CSI4TPDAT 4 Differentia AH13 515 0 Differentia 16 CSI4TPDAT 5 Differentia 14 515 1 Differentia 117 CSI4TPDAT 6 Differentia 15 CSI5TPDAT 2 Differentia 18 CSIATPDAT 7 Differentia 16 515 3 Differentia 119 514 81 Differentia 17 515 4 Differentia 20 CSIATPDAT 9 Differentia 19 515 51 Differentia 17 CSISRNCLK Differentia 19 CSI5TPDAT 6 Differentia 112 CSI5RNDAT O Differentia 20 CSI5TPDAT 7 Differentia AM13 CSI5RNDAT 1 Differentia AJ21 CSI5TPDAT 8 Differentia 14 CSI5RNDAT 2 Differentia AL22 CSI5TPDAT 9 Differentia 15 CSI5RNDAT 3 Differentia 12 ERROR 0 N AR13 CSI5RNDAT 4 Differentia 12 ERROR 1 _N 1 CSI5RNDAT 5 Differentia 11 FBDONBIAN 0 Differentia AU14 CSI5RNDAT 6 Differentia AU9 FBDONBIAN 1 Differentia 15 CSI5RNDAT 7 Differentia AV8 FBDONBIAN 2 Differentia AU15 CSI5RNDAT 8 Differentia 10 FBDONBIAN 3 Differentia 16 CSI5RNDAT 9 Differentia AT8 FBDONBIAN 4 Differentia 17 CSI5RPCLK Differentia 6 5 Differentia AL13 5158 0 Differentia 4 FBDONBIAN 6 Differentia 13 5158 1 Differentia 2 FBDONBIAN 7 Differentia 14 CSI5RPDAT 2 Differentia 8 Differentia
173. er AA31 CSI3TNDAT 18 Differentia 2 CSI3TNDAT 19 Differentia AA33 CSI3TPDAT 19 Differentia 4 VSS Power Other AA35 511 181 Differentia 6 CSI1TPDAT 18 Differentia AA37 Power Other AA38 CSI IRNDAT 18 Differentia 1 FBDONBIBN 11 Differentia 2 VSS Power Other AB3 FBDOSBOBN 6 Differentia 4 VCCIO FBD Power Other 89 intel Pin Listing Table 3 2 Pin List by Pin Number Sheet 3 Table 3 2 Pin List by Pin Number Sheet 4 of 32 of 32 NN Pin Name M LN Direction 5 FBD1NBI DP 0 Differential 5 VSS Power Other AB6 FBD1NBIDN 0 Differential 6 VSS Power Other AB7 VSS Power Other AC37 CSIIRNDAT 17 Differentia 8 FBD1NBIDP 14 Differential 8 CSI1RPDAT 17 Differentia 9 VCCIO FBD Power Other AD1 FBDONBI BN 10 Differentia 10 VSS Power Other AD2 FBDONBI BP 10 Differentia 11 VSS Power Other AD3 VSS Power Other AB12 VSS Power Other AD4 FBDOSBOBP 5 Differentia 27 VSS Power Other AD5 FBDOSBOBP 7 Differentia 28 VCCIO Power Other AD6 FBDOSBOBN 7 Differentia 29 VSS Power Other AD7 FBDOSBOBN 9 Differentia Power Other AD8 VSS Power Other 1 CSI 3TPDAT 18 Differential AD9 FBDIREFSYSCLKN Differenti
174. er Other AD31 Power Other F23 Power Other AE29 Power Other F35 Power Other AF10 Power Other G13 Power Other AF27 Power Other G29 Power Other AG14 Power Other G34 Power Other AG18 Power Other H17 Power Other AG25 Power Other H19 Power Other Intel Itanium Processor 9300 Series and 9500 Series Datasheet 83 intel Table 3 1 Pin List by Pin Name Sheet 23 Table 3 1 Pin List by Pin Name Sheet 24 of 33 of 33 NL Pin Name pane TUE Direction Direction H22 ___ H7 VCCIO FBD Power Other H24 VCCIO Power Other VCCIO_FBD Power Other H32 Power Other 14 FBD Power Other 134 Power Other N4 VCCIO_FBD Power Other K24 Power Other T10 VCCIO_FBD Power Other K27 Power Other T3 VCCIO FBD Power Other K35 VCCIO Power Other w5 VCCIO FBD Power Other L15 VCCIO Power Other Y2 VCCIO FBD Power Other M18 VCCIO Power Other T12 VFUSERM 3 ___ ___ 1 M26 Power Other K38 VR_THERMALERT_N 36 VCCIO Power Other H38
175. erface 6 2 SMBus Memory Component 6 2 1 Processor nformation ROM PI ROM Table 6 1 maps the PI ROM offsets to the field definitions which are described in Section 6 4 Table 6 1 Processor nformation ROM Data Sheet 1 of 6 Sec Offset Field Name Data Type Description Example General 0 00h Data Format Revision Hex Incremented with PI ROM Table Rev 1 6 0x10 revisions 1 01h EEPROM Size Hex Size in Bytes 128 bytes 00801 that is 2 02h 02h 7 0 0x00 01h 7 0 0x80 3 03h Processor Data Address Hex Byte pointer Pointer to the section of PIROM OxOF 0x00 if not containing Processor Production present Data 4 04h Processor Core Address Hex Byte pointer Pointer to the section of PIROM 0x22 0x00 if not containing Processor Core Data present 5 05 Processor Uncore Hex Byte pointer Pointer to the section 0 2 0x00 if not Address containing Processor Uncore Data present 6 06h Processor Cache Hex Byte pointer Pointer to the section of PIROM 0x46 0x00 if not Address containing Processor Cache Data present 7 07h Package Data Address Hex Byte pointer Pointer to the section of PIROM Ox4F 0 00 if not containing Processor Package present Data 8 08h Part Number Data Hex Byte pointer Pointer to the section of PIROM 0x56 0x00 if not Address containing Processor Part Number present Data 9 09h Thermal Reference Data Hex Byte pointer Pointer to the section
176. es processor and 90 for the Intel Intel Itanium Processor 9300 Series 9500 Series Datasheet System Management Bus 1 tel 6 4 10 6 4 11 Table 6 5 Itanium Processor 9500 Series Note that even reduced core count Itanium products for example 2 core Intel Itanium Processor 9300 Series will still have all devices on the TAP chain Other Data Addresses 7Dh 7Fh are listed as reserved Checksums The Processor Information section of the ROM includes multiple checksums Table 6 5 includes the checksum values for each section defined in the 128 byte PIROM section except the Other Data section 128 Byte PIROM Checksum Values Section Checksum Address General OEh Processor Data 21h Processor Core Data 2Dh Processor Uncore Data 45h Cache Data 4Eh Package Data 55h Part Number Data 6Ah Thermal Reference Data 71h Feature Data 7Ch Other Data None Defined Checksums are automatically calculated and programmed The first step in calculating the checksum is to add each byte from the field to the next subsequent byte The second step is to take the 2 s complement of the first step This value is the checksum Example For a byte string of AA445Ch the resulting checksum will be B6h AA 10101010 44 01000100 5C 0101100 First step add the bytes AA 44 5 01001010 Second step take 2 s complement 10110101 1 10110110 C
177. essor Package Bottom Pin 73 3 1 1 Package Bottom Pin Listing by Pin 0 1 2 73 3 1 2 Listing by Pin Number 1 1 memes enemies ees 89 3 2 Processor Package Top Pin 5 5 105 3 2 1 Top Side 1 Connector Two Dimensional Table 105 3 2 2 5 2 Connector Two Dimensional Table 108 3 2 3 Top Side 3 Connector Two Dimensional Table 111 3 2 4 Top Side 4 Connector Two Dimensional Table 114 4 Mechanical Specifications 119 4 1 Package Mechanical 120 4 2 Intel Itanium Processor 9300 121 4 3 Processor Component Keepout 2 129 4 4 Package Loading 5 00 129 4 5 Package Handling 129 4 6 Processor Mass 500 130 4 7 Processor 5 eq DURER Lade 130 4 8 Package Markings
178. ferentia 12 FBDONBIAP 10 Differentia AL7 FBDOREFSYSCLKP Differentia 11 Differentia V4 FBDOSBOAN 0 Differentia 12 Differentia W1 FBDOSBOAN 1 Differentia 05 FBDONBIAP 13 Differentia V2 FBDOSBOAN 2 Differentia AV12 FBDONBIAP 14 Differentia U1 FBDOSBOAN 3 Differentia FBDONBIBN 0 Differentia T1 FBDOSBOAN 4 Differentia 9 FBDONBIBN 1 Differentia FBDOSBOAN 5 Differentia 7 FBDONBIBN 2 Differentia 1 FBDOSBOAN 6 Differentia FBDONBIBN 3 Differentia 13 FBDOSBOAN 7 Differentia 5 FBDONBIBN 4 Differentia L1 FBDOSBOAN 8 Differentia 5 FBDONBIBN 5 Differentia 1 FBDOSBOAN 9 Differentia 1 FBDONBIBN 6 Differentia 2 FBDOSBOAN 10 Differentia FBDONBIBN 7 Differentia WA FBDOSBOAP 0 Differentia FBDONBIBN 8 Differentia 2 FBDOSBOAP 1 Differentia FBDONBIBN 9 Differentia V3 FBDOSBOAP 2 Differentia AD1 FBDONBIBN 10 Differentia V1 FBDOSBOAP 3 Differentia 1 FBDONBIBN 11 Differentia T2 FBDOSBOAP 4 Differentia 2 FBDONBIBN 12 Differentia 2 FBDOSBOAP 5 Differentia 4 FBDONBIBN 13 Differentia 1 FBDOSBOAP 6 Differentia 10 FBDONBIBN 14 Differentia M3 FBDOSBOAP 71 Differentia 9 FBDONBIBP 0 Differentia 12 FBDOSBOAP 8 Differentia 8 FBDONBIBP 1 Differentia 2 FBDOSBOAP 9 Differe
179. ff Rise E Rrefcik diff Fall 00 150 MV Vretcik diff in 150 MV 1 1 1 REFCLK girs Figure 2 5 Vgg and Tstabie Definitions 2 4 2 4 1 28 Intel QuickPath I nterconnect and Intel SMI Signaling Specifications Intel Itanium Processor 9300 Series Intel QuickPath Interconnect and Intel SMI Specifications for 4 8 GT 5 The applicability of this section applies to Intel for the Intel Itanium9 Processor 9300 Series This section contains information for Intel slow boot up speed 1 4 frequency of the reference clock and processor s normal operating frequency 4 8 GT s for Intel and Intel SMI For Intel slow boot up speed the signaling rate is defined as 1 4 the rate of the system reference clock For example a 133 MHz system reference clock would have a forwarded clock frequency of 33 33 MHz and the signaling rate would be 66 67 MT s The transfer rates available for the processor are shown in Table 2 4 Transmitter and receiver parameters for Intel QPI slow mode Intel QPI and Intel SMI are shown in Table 2 5 and Table 2 6 respectively Intel Itanium Processor 9300 Series 9500 Series Datasheet Electrical Specifications Table 2 4 Intel Itanium Processor 9300 Series C
180. fied for each processor SKU separately in Table 2 16 through Table 2 17 Table 2 18 defines the FMB voltage specification values applied to the 130 W and 170 W SKUs for the Intel Itanium9 Processor 9500 Series Current specifications are identified for each processor SKU separately in Table 2 19 Table 2 15 FMB Voltage Specifications for the Intel Itanium Processor 9300 Series Symbol Parameter Min Typ Max Units Notes VI Dnange VCCCORE VID Range 0 8 11 1 35 V UVI Drange VCCUNCORE VID Range 0 8 11 1 35 V VCCUNCORE Processor uncore supply voltage See Table 2 20 and Figure 2 10 V 2 1 Processor core supply voltage See Table 2 21 and Figure 2 11 V 2 3 4 VCCCACHE Processor cache supply voltage See Table 2 22 and Figure 2 12 V 5 VID Transition VID step size during transition 12 5 mV VID_DCshift Total allowable DC load line shift from VID 450 mV 6 steps VCCI O Processor 1 supply voltage at die 1 08 1 15 1 22 V 7 including all AC and DC VCCIO Processor 1 supply voltage high 0 50 mV frequency AC p p noise at die VCCIO Processor 1 supply voltage at package 1 147 1 175 1 203 V 8 pin including all AC and DC VCCA Processor analog supply voltage DC spec 1 764 1 8 1 836 V VCCA Processor analog supply voltage AC 1 8 25 9 10 tolerance for noise at scope full bandwidth VCCA Processor analog supply voltage AC 1 8 15 mV 9 11 tolerance for noise gt 1 2 VCCA Processor analog supply voltage Total 1 739 1 8 1 861 V
181. for this part f 1600 Mhz 102 66h Gahi 90 66h 16 103 67h RESERVED Intel 4 bcd digits Reserved for future use Intel 67h 0x00 Itanium Processor Itanium processor 9300 series 68h 0x00 Intel 104 68h 9300 Series Itanium Processor 9300 Series Uncore Frequency Nominal operating uncore frequency in MHz 2 4 GHz Processor 95 eries Intel Itanium Processor 9500 67h 0x00 Series 68h 0x24 Intel Itanium amp Processor 9500 Series 105 69h RESERVED Hex Reserved for future use 69h 0x00 106 6Ah Checksum Hex Add up by byte and take 2 s complement Thermal Reference 107 6Bh THERMALERT_N hot 2 Hex digits Recommended THERMALERT_N 10C below PROCHOT_N assertion assertion threshold value 0x0A 108 6Ch THERMALERT_N hot 2 Hex digits Recommended THERMALERT_N 2C deassert 0x02 deassertion hysteresis deassertion threshold value This indicates a THERMALERT_N deassert of 10C 2C 12C below PROCHOT_N 109 6Dh Maximum TDP 2 Hex digits Thermal Design Power Max 185 W 9 110 6Eh TCONTROL 2 Hex digits Default processor thermal 5C below PROCHOT_N monitoring setpoint in C 0 5 111 6Fh 6Fh 0x00 RESERVED Hex Reserved for future use 112 70h 70h 0x00 113 71h Checksum Hex Add up by byte and take 2 s complement 148 Intel Itanium Processor 9300 Series 9500 Series Datasheet System Management Bus 1 tel Table 6
182. full 2 half width at up to 6 4 GT s Intel Hot plug Supported Supported Intel QPI Link self healing Supported Supported Intel QPI Clock fail safe Supported Supported Intel Data scrambling Supported Required Intel QPI Periodic retraining Not Supported Required Integrated memory controllers 2 2 Intel SMI Interface Intel 7500 Scalable Memory Buffer Intel 7500 Scalable Memory Buffer 4 8 GT s 4 8 GT s Intel 7510 Scalable Memory Buffer 6 4 GT s Intel SMI Hot plug Supported Supported Physical address space virtual address space 50 physical 64 virtual 50 physical 64 virtual Caching agent architecture four caching agents per socket where each agent is responsible for all of the address space and dedicated to a core two caching agents per socket are responsible for half the address space and shared among the cores DIMM memory interface Home agents per socket 2 2 Directory Cache Supported Supported Intel Virtualization Technology Intel VT Intel Vt i 2 Intel Vt i 3 Hot add hot removal at Intel QPI link and Supported Supported Hot add CPU Supported 3 Supported 3 Hot add memory Supported 3 Supported 3 Hot remove hot replace memory Supported 3 Supported 3 Memory sparing technique DIMM DIMM and Rank Memory scrubbing Supported Supported Memory mirroring Supported Supported Intel Itanium Processor 9300 Series and 9500 Series Datasheet 19
183. hanism for transferring data between SMBus devices This is an open drain signal Intel Itanium Processor 9300 Series and Intel Itanium 9500 Series are Slave only Intel Itanium Processor 9300 Series and 9500 Series Datasheet 163 intel Signal Definitions Table 7 1 Signal Definitions for the Intel Itanium Processor 9300 Series and Intel Itanium 9500 Series Sheet 6 of 8 Name Type Description SPDCLK 1 0 This is a bi directional clock signal between the processor DRAM SPD registers and external components on the board This is an open drain signal The Intel Itanium Processor 9300 Series and 9500 Series Processors are Master only refer to the Intel Itanium Processor 9300 Series External Design Specification or Intel Itanium Processor 9500 Series External Design Specification for limitations SPDDAT 1 0 This is a bi directional data signal between the processor DRAM SPD registers and external components on the board This is an open drain signal Intel Itanium Processor 9300 Series and 9500 Series Processors are Master only refer to the Intel Itanium Processor 9300 Series External Design Specification or Intel Itanium Processor 9500 Series External Design Specification for limitations SVID_CLK This a source synchronous clock used by the processor to transmit voltage ID data to the Ararat voltage regulator This is an open drain signal See Ararat
184. hecksum is OxB6 Intel Itanium Processor 9300 Series and 9500 Series Datasheet 157 n tel System Management Bus I nterface 158 Intel Itanium Processor 9300 Series and 9500 Series Datasheet Signal Definitions 7 Signal Definitions This Chapter provides an alphabetical listing of all Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series signals The tables list the signal directions Input Output 1 0 and signal descriptions For a complete pinout listing including processor specific pins please refer to Chapter 3 Pin Listing Table 7 1 Signal Definitions for the Intel Itanium Processor 9300 Series and Intel Itanium 9500 Series Sheet 1 of 8 Name Type Description BOOTMODE 1 0 The BOOTMODE 1 0 inputs specify which way the Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series will boot For details on the modes refer to the Intel Itanium Processor 9300 Series External Design Specification or the Intel Itanium Processor 9500 Series External Design Specification To pull any of these inputs high they should be strapped to VCCIO through a pull up resistor and to pull these low they should be strapped to GND These pins are sampled during all resets except warm logic reset CPU 1 0 CPU Present pads These pins at the top of the package are part of a daisy chain that indicates to the platform that
185. her AF4 VSS Power Other AK16 vss Power Other AF9 VSS Power Other AK21 VSS Power Other AG12 VSS Power Other AK24 VSS Power Other AG15 VSS Power Other AK25 VSS Power Other AG17 VSS Power Other AK26 VSS Power Other AG2 VSS Power Other AK30 vss Power Other AG22 VSS Power Other AK31 VSS Power Other AG23 VSS Power Other AK35 vss Power Other AG26 VSS Power Other AK36 vss Power Other AG27 VSS Power Other AK6 VSS Power Other AG32 VSS Power Other AL14 VSS Power Other AG37 VSS Power Other AL18 vss Power Other 5 VSS Power Other AL19 VSS Power Other Intel Itanium Processor 9300 Series and 9500 Series Datasheet 85 intel Table 3 1 Pin List by Pin Name Sheet 27 Table 3 1 Pin List by Pin Name Sheet 28 of 33 of 33 NL UR Pin Name pone TUE Direction LAM Pin Name mL Direction aa vss AR6 VSS Power Other AL29 VSS Power Other 1 VSS Power Other AL34 VSS Power Other AT12 VSS Power Other AL4 VSS Power Other AT14 VSS Power Other AL9 VSS Power Other AT19 VSS Power Other AM12 VSS Power Other AT24 VSS Power Other AM17 VSS Power Other AT29 VSS Power Other AM2 VSS Power Other AT34 VSS Power Other AM22 VSS Power Other AT4 VSS Power Other vss jPowejOter AT9 VSS Power Other AM32 VSS Power Other AU12 VSS Power Other AM34 VSS Power Other AU17 VSS Power Other am37 vss jPowejOter ___ AU22 VSS
186. hich failure of the Intel Product could result directly or indirectly in personal injury or death SHOULD YOU PURCHASE OR USE INTEL S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES SUBCONTRACTORS AND AFFILIATES AND THE DIRECTORS OFFICERS AND EMPLOYEES OF EACH HARMLESS AGAINST ALL CLAIMS COSTS DAMAGES AND EXPENSES AND REASONABLE ATTORNEYS FEES ARISING OUT OF DIRECTLY OR INDIRECTLY ANY CLAIM OF PRODUCT LIABILITY PERSONAL I OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN MANUFACTURE OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to ob
187. ia AL23 CSI3TPDAT 2 Differentia 121 514 Differentia 21 CSI 3TPDAT 3 Differentia 14 514 0 Differentia 22 CSI3TPDAT 4 Differentia K13 CSI4TNDAT 1 Differentia 24 CSI3TPDAT 5 Differentia 15 CSI4TNDAT 2 Differentia 25 5 61 Differentia 14 CSI4TNDAT 3 Differentia 26 CSI 3TPDAT 7 Differentia G15 CSI4TNDAT 4 Differentia 25 CSI 3TPDAT 8 Differentia 16 CSI4TNDAT 5 Differentia 27 CSI3TPDAT 9 Differentia 17 CSI4TNDAT 6 Differentia 29 CSI3TPDAT 10 Differentia 118 CSI4TNDAT 7 Differentia 31 CSI3TPDAT 11 Differentia 19 CSI4TNDAT 8 Differentia 1 CSI3TPDAT 12 Differentia 120 CSI4TNDAT 9 Differentia CSI3TPDAT 13 Differentia 122 CSI ATPCLK Differentia Intel Itanium Processor 9300 Series and 9500 Series Datasheet 77 intel Pin Listing Table 3 1 Pin List by Pin Name Sheet 11 Table 3 1 Pin List by Pin Name Sheet 12 of 33 of 33 Nom Pin Name Baier Direction E LAN Pin Name Direction M15 CSI4TPDAT O Differentia 19 CSI5TNDAT 7 Differentia K14 CSI4TPDAT 1 Differentia 20 CSI5TNDAT 8 Differentia 115 514 21 Differentia 121 CSI5TNDAT 9 Differentia 14 CSI4TPDAT 3 Differ
188. ia 117 VSS Power Other K16 VSS Power Other L18 CSI4TNDAT 7 Differential 17 CSI4TNDAT 6 Differentia 119 VSS Power Other K18 CSI4TPDAT 7 Differentia 120 CSI4TNDAT 9 Differential K19 CSI4TNDAT 8 Differentia 121 CSI4TNCLK Differential 20 CSI4TPDAT 9 Differentia 122 CSI4TPCLK Differential K21 VSS Power Other L23 VSS Power Other K22 VSS Power Other 124 VSS Power Other K23 VSS Power Other L25 VSS Power Other K24 VCCIO Power Other L26 VSS Power Other K25 VSS Power Other L27 FLASHROM WP N 26 VSS Power Other L28 FLASHROM CFG 2 K27 Power Other L29 VSS Power Other K28 512 10 Differentia 130 FLASHROM CS 0 N 29 512 10 Differentia L31 CSIOTNDAT 9 Differential K30 CSIOTNDAT O Differentia 132 CSIOTPDAT 9 Differential K31 VSS Power Other L33 CSIOTNDAT 10 Differential K32 CSIOTNDAT 4 Differentia 134 VSS Power Other K33 CSIOTNCLK Differentia 135 VSS Power Other K34 CSI OTPCLK Differentia 136 CSIORNDAT 10 Differentia K35 VCCIO Power Other L37 CSI ORPDAT 10 Differentia K36 VSS Power Other L38 CSIORNDAT 11 Differentia K37 CSIORPCLK Differential 1 FBDOSBOAN 6 Differentia K38 VR_THERMALERT_N 2 vss Power Other L1 FBDOSBOAN 8 Differential M3 FBDOSBOAP 7 Differentia 12 FBDOSBOAP 8 Differential 4 RSVD L3 FBDOSBOAN 7 Differential 5 FBDINBIDN 7 Differentia 14 VSS Power Other 6 1 1 6 Differentia Intel
189. icating which section of the EEPROM is to be addressed the PIROM MSB 0 or the Scratch EEPROM MSB 1 Table 6 2 Read Byte SMBus Packet Slave 5 Slave 5 Address Eno A 5 Address Read 111 1 7 65 1 1 8 bits 1 7 bits 8 bits 1 Table 6 3 Write Byte SMBus Packet Slave 5 Address Write A Code A Data P 1 7 bits 1 1 8 bits il 8 bits 1 6 3 150 Memory Component Addressing The Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series PIR_A 1 0 pins are used as the memory address selection signals The processor does not specify the value on these pins It is left to the system architect to set the SMBus memory map If the processor is the only device on the bus these pins may be tied to VSS PIR_A 2 is tied to VSS internal to the processor Figure 6 1 shows the address connections within the processor package Intel Itanium Processor 9300 Series 9500 Series Datasheet m e System Management Bus I nterface n tel Figure 6 1 Intel Itanium Processor 9300 Series and Intel I tanium Processor 9500 Series Package PIR_SDA gt 2 VSS 1 0 AU VCC33 SM ee 5 9 SMBDAT 4 SMBDAT SMBCLK 44 SMBCLK 5 SPDDAT
190. ich may be used for other data at the system vendor s discretion The data in this EEPROM once programmed can be write protected by asserting the active high SM_WP signal This signal has a weak pull down 10 kQ to allow the EEPROM to be programmed in systems with no implementation of this signal The Scratch EEPROM resides in the upper half of the memory component addresses 80 FFh The lower half comprises the Processor Information ROM addresses 00 7Fh which is permanently write protected Intel Itanium Processor 9300 Series and 9500 Series Datasheet 149 intel PI ROM and Scratch EEPROM Supported SMBus Transactions System Management Bus I nterface The PIROM responds to two SMBus packet types Read Byte and Write Byte However since the PIROM is write protected it will acknowledge a Write Byte command but ignores the data The Scratch EEPROM responds to Read Byte and Write Byte commands Table 6 2 illustrates the Read Byte command Table 6 3 illustrates the Write Byte command In the tables S represents the SMBus start bit P represents a stop bit A represents an acknowledge and 7 represents a negative acknowledge NACK shaded bits are transmitted by the PIROM or Scratch EEPROM and the bits that aren t shaded are transmitted by the SMBus host controller In the tables the data addresses indicate 8 bits The SMBus host controller should transmit 8 bits with the most significant bit ind
191. ies package includes a system management bus SMBus interface This chapter describes the features of the SMBus and its components Introduction The Intel Itanium Processor 9300 Series Intel Itanium Processor 9500 Series package includes an SMBus interface which allows access to a memory component subdivided into two sections referred to as the and the Scratch EEPROM sideband access to the processor s control amp status registers CSRs This chapter is devoted to the PIROM field definitions of the memory component For details of SMBus transactions used to access processor Control and Status Registers CSRs refer to the RS Intel Itanium 9300 Processor External Design Specification or the RS Intel Itanium Processor 9500 Series External Design Specification The PIROM consists of the following sections General Processor Processor Core Processor Uncore Cache Package Part Number Thermal Reference Feature Other Details on each of these sections are described in Section 6 4 The processor SMBus implementation uses the clock and data signals of the System Management Bus SMBus Specification Layout and routing guidelines are available in the Intel 9300 Series and Intel Itanium amp 9500 Series Platform Design Guide Intel Itanium Processor 9300 Series and 9500 Series Datasheet 143 intel System Management Bus I nt
192. ifferentia AV23 CSI3RPDAT 12 Differential 022 VSS Power Other AV24 CSI3RNDAT 12 Differential 96 Intel Itanium Processor 9300 Series and 9500 Series Datasheet intel Pin Listing Table 3 2 Pin List by Pin Number Sheet Table 3 2 Pin List by Pin Number Sheet 17 of 32 18 of 32 0 Direction 8 Direction AV25 VSS Power Other B27 VSS Power Other AV26 VCCA Power Other B28 CSI2RNDAT 16 Differentia 27 Power Other B29 CSI 2RPDAT 16 Differentia 28 CSI3RPDAT 17 Differentia 0 CSI2RNDAT 17 Differentia 29 CSI3RNDAT 17 Differentia B31 CSI 2RPDAT 18 Differentia AV30 VSS Power Other B32 VSS Power Other AV31 CSI3RNDAT 19 Differentia B33 CSI ORNDAT O Differentia AV32 CSI1RPDAT 1 Differentia B34 CSIORNDAT 2 Differentia CSI1RNDAT 1 Differentia 835 CSIORPDAT 2 Differentia 4 CSI1RNDAT 2 Differentia B36 RSVD AV35 RSVD B37 RSVD AV36 vss Power Other B38 RSVD AV37 RSVD Cl RSVD AV38 RSVD C2 RSVD 1 55 Power Other CPU_PRES1_N 1 0 B2 RSVD C4 FBD1SBODN 5 Differentia 0 B3 RSVD C5 VSS Power Other B4 FBD1SBODN 9 Differentia FBD1SBODP 6 Differentia 5 FBD1SBODP 9 Differentia C7 FBD1SBOCP 4 Differentia B6 FBD1SBODN
193. ifications for the single ended signal groups defined in Table 2 2 Voltage Regulator Signal Group DC Specifications Symbol Parameter Min Max Unit Notes Input Low Voltage 0 0 4 Vin Input High Voltage 0 8 3 6 V Output High Voltage 0 8 3 6 1 2 3 4 5 VoL Output Low Voltage 0 0 4 V 1 2 3 4 5 Notes 1 Open collector and drain outputs need pull up resistors on the motherboard Intel Itanium Processor 9300 Series 9500 Series Datasheet 53 Table 2 28 Table 2 29 Electrical Specifications These outputs can be pulled up to VCCIO or VCC_STDBY on the platform Pull up resistance should limit current to 2 mA Actual Voy and Vo levels are determined by pull up resistance and supply voltage values These values are based on 2 2 KQ pull up to 3 3 V supply Voltage Regulator Control Group DC Specification Symbol Parameter Min Max Unit Notes Input Low Voltage 0 VCCIO 0 67 0 2 V Input High Voltage VCCIO 0 67 0 2 VCCIO V Output High Voltage V 1 2 3 4 VoL Output Low Voltage 1 2 3 4 Notes 1 Open collector and drain outputs need pull up resistors on the motherboard 2 Actual Voy and levels determined by pull up resistance and supply voltage value Refer to the Ararat Voltage Regulator Module Design Guide or the Ararat Voltage Regulator Module Design Guide for Io max 3 See I
194. in microcontroller that manipulates voltage and frequency PAL communicates requested P states to this controller through internal registers As shown in Figure 1 3 Itanium architecture based firmware consists of several major components Processor Abstraction Layer PAL System Abstraction Layer SAL Unified Extensible Firmware Interface UEFI and Advanced Configuration and Power Interface ACPI PAL SAL UEFI and ACPI together provide processor and system initialization for an operating system boot PAL and SAL provide machine check abort handling PAL SAL UEFI and ACPI provide various run time services for system functions which may vary across implementations The interactions of the various services that PAL SAL UEFI and ACPI provide are illustrated in Figure 1 3 In the context of this model and throughout the rest of this chapter the System Abstraction Layer SAL is a firmware layer which isolates operating system and other higher level software from implementation differences in the platform while PAL is the firmware layer that abstracts the processor implementation 17 Figure 1 3 intel Introduction Protection Keys provide a method to restrict permission by tagging each virtual page with a unique protection domain identifier The Protection Key Registers PKR represent a register cache of all protection keys required by a process The operating system is responsible for management and replacement polices of the prot
195. ing Residue protection on Floating Point unit along with the adoption of radiation hardened RAD sequential latching elements for vulnerable architectural and state The Intel Itanium Processor 9500 Series processor interfaces exclusively with the Ararat Voltage Regulator Module The Intel Itanium Processor 9500 Series consists of up to 8 core processors and a system interface unit Each processor core provides a 12 wide 11 stage deep execution pipeline The resources consist of six integer units one integer multiply unit four multimedia units two load store units three branch units and two floating point units each capable of extended double and single precision arithmetic The hardware employs dynamic prefetch branch prediction a register scoreboard and non blocking caches to optimize for compile time non determinism 32 additional stacked general registers are provided over the Intel Itanium Processor 9300 Series and hardware support is provided for denormal unnormal and pseudo normal operands for floating point software assist offloading New instructions on the Intel Itanium Processor 9500 Series simplify common tasks They include clz count leading zeros mpy4 and mpyshl4 unsigned integer multiply shift and multiply mov to DAHR mv from DAHR for improved MLD FLD prefetcher hinting and performance hint priority used by the processor to temporarily allocate more resources to a thread Advanced Explicit
196. intel Intel Itanium Processor 9300 Series and 9500 Series Intel I tanium Processor Quad Core 1 86 1 73 GHz with 24 MB L3 Cache 9350 Intel I tanium Processor Quad Core 1 73 1 60 GHz with 20 MB L3 Cache 9340 Intel I tanium Processor Quad Core 1 60 1 46 GHz with 20 MB Cache 9330 Intel I tanium Processor Quad Core 1 46 1 33 GHz with 16 MB Cache 9320 Intel I tanium Processor Dual Core 1 60 GHz Fixed Frequency with 10 MB Cache 9310 Intel Itanium Processor Eight Core 2 53 GHz with 32 MB LLC Cache 9560 Intel I tanium Processor Four Core 2 40 GHz with 32 MB LLC Cache 9550 Intel Itanium Processor Eight Core 2 13 GHz with 24 MB LLC Cache 9540 Intel I tanium Processor Four Core 1 73 GHz with 20 MB LLC Cache 9520 Datasheet November 2012 Reference Number 322821 002 INFORMATION IN THIS DOCUMENT IS PROVIDED CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT A Mission Critical Application is any application in w
197. itely Refer to Figure 2 9 for further details on the average processor current draw over various time durations This parameter is based on design characterization and is not tested 2 During system power on the pulse inrush ICC CORE STEP can be as high as 130A peak to peak 3 UNCORE TDC is the sustained DC equivalent current that the processor uncore is capable of drawing indefinitely and should be used for the Ararat voltage regulator temperature assessment The Ararat voltage regulator is responsible for monitoring its temperature and asserting the VR THERMALERT VR THERMTRIP signals sequentially to inform the processor and platform of a thermal excursion Of the three signals only VR THERMALTERT is monitored by the processor Please see the Ararat Voltage Regulator Module Design Guide for further details The processor is capable of drawing ICC UNCORE TDC indefinitely This parameter is based on design characterization and is not tested 4 During system power on the pulse inrush UNCORE STEP be as high as 40A peak to peak 5 The ICC 1O current specification applies to the total current from VCCIO pins Intel Itanium Processor 9300 Series 9500 Series Datasheet 41 intel Electrical Specifications Table 2 17 155W 185W Current Specifications for the I ntel Itanium Processor 9300 Series Symbol Parameter Max Un
198. its Notes for core 180 l CC_CORE_TDC Thermal Design Current for Core 131 A 1 _ 5 Load step for core 95 A 2 dicc coRE dt Slew rate for core at Ararat output 154 A us UNCORE cc for uncore 50 A I cc UNCORE TDC Thermal Design Current for Uncore 43 A 3 UNCORE STEP Max Load step for uncore 22 A 4 dlcc uNcoRE dt Slew rate for uncore at Ararat output 75 A us for processor 1 0 22 5 Analog for processor Analog 4 A 5 for main supply 200 mA Notes 1 is the sustained DC equivalent current that the processor core is capable of drawing indefinitely and should be used for the Ararat voltage regulator temperature assessment The Ararat voltage regulator is responsible for monitoring its temperature and asserting the VR_FAN_N VR THERMALERT N VR THERMTRIP signals sequentially to inform the processor and platform of a thermal excursion Of the three signals only THERMALTERT is monitored by the processor Please see the Ararat Voltage Regulator Module Design Guide for further details The processor is capable of drawing CORE indefinitely Refer to Figure 2 9 for further details on the average processor current draw over various time durations This parameter is based on design characterization and is not tested During system power the pulse inrush ICC CORE STEP can be as high
199. ium Processor 9500 Series package allows the Ararat Voltage Regulator to signal to the platform when it approaches its own thermal limits The specific signals for this purpose FAN VR THERMALERT and THERMTRIP The processor does not monitor or respond to the FAN and VR THERMTRIP pins The response to VR THERMALERT is to force the processor into the same state as PROCHOT The processor will go into SIM and also transition to the voltage and frequency of the lowest supported P state Time limits and CMCI generation are active This response may be disabled via R CSR IPF THERM CONFIG vr thermalert disable Intel Itanium Processor 9300 Series 9500 Series Datasheet Thermal Specifications 5 2 Table 5 3 Table 5 4 Package Thermal Specifications and Considerations intel This section lists the thermal parameters of the Intel Itanium9 Processor 9300 Series and Intel Itanium Processor 9500 Series package See Table 5 3 and Table 5 4 for the Tcase design target at Thermal Design Power and the minimum Tcontrol specification for the Intel Itanium Processor 9300 Series and the Intel Itanium Processor 9500 Series respectively The case temperature is defined as the temperature measured at the center of the processor substrate on the top surface of the IHS Thermal Specification for the Intel Itanium Processor 9300 Series T
200. kPath Interconnect Clock Fail Safe Feature Intel QuickPath Interconnect Intel Hot Add and Removal DIMM Sparing Memory Scrubbing Memory Mirroring and Memory Migration Architected firmware stack including PAL and SAL support Directory based and source based coherency protocol Intel QPI poisoning viral containment and cleanup Intel Itanium Processor 9300 Series and 9500 Series Datasheet On die Memory Controller Each memory controller supports two Intel Scalable Memory Interconnects Support for one Scalable Memory Buffer per Intel Scalable Memory Interconnect four Scalable Memory Buffers per processor High memory bandwidth thus improved performance 4 8 GT s for the Intel 7500 Scalable Memory Buffer Intel Virtualization Technology for virtualization for data intensive applications Reduce virtualization complexity Improve virtualization performance Increase operating system compatibility Intel Cache Safe Technology ensures mainframe caliber availability Minimize L3 cache errors Disable cache entries that have become hard errors Improve availability High bandwidth Intel QuickPath Interconnect for multiprocessor scalability 4 full and 2 half width Intel QPI Links 4 8GT s transfer rate Systems are easily scaled without sacrificing performance Features to support flexible platform environment
201. keepout zones and Figure 4 8 for Intel Itanium 9500 Series Processor keepout zones Package Loading Specifications Table 4 1 provides dynamic and static load specifications for the processor package These mechanical load limits should not be exceeded during heatsink assembly shipping conditions or standard use condition Also any mechanical system or component testing should not exceed the maximum limits The processor package substrate should not be used as a mechanical reference or load bearing surface for thermal and mechanical solutions Processor Loading Specifications Parameter Maximum Unit Notes Static Compressive Load 1000 N 1 2 3 Dynamic Compressive Load 1793 N 1 3 t lt 30 5 Transient 1090 N 1 3 5 lt 15 Notes 1 These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top surface 2 This is the allowable static force that can be applied by the heatsink and retention solution to maintain the heatsink and processor interface 3 These parameters are based on limited testing for design characterization Loading limits are for the package only and do not include the limits of the processor socket Package Handling Guidelines Table 4 2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal
202. le 6Dh OxB9 indicates a 185 W part TControl Offset 6Eh contains the recommended TControl spec in degrees C below PROCHOT N temperature in Hex format Feature Data This section provides information on key features that the platform may need to understand without powering on the processor Processor Core Feature Flags For the Intel Itanium Processor 9300 Series offset 72h 75h contains a copy of results in EDX 31 0 from Function 1 of the CPUID instruction These details provide instruction and feature support by product family These fields are RESERVED for the Intel tanium Processor 9500 Series processor Package Feature Flags Offset 78h 79h provides additional feature information from the processor This field is defined as follows Offset 78h 79h Definitions Bit Definition 4 32 Reserved 3 Thermal calibration offset byte present 2 Scratch OEM EEPROM present set if there is a scratch ROM at offset 80 FFh 1 Core VID present set if there is VID provided by the processor 0 Reserved Number of Devices in TAP Chain At offset 7Bh a 4 bit Hex digit is used to tell how many devices are in the TAP Chain The four bits are the most significant bits at this offset Since Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series processors have TAP per core plus sysint TAP this field would be set to 50h for the Intel Itanium Processor 9300 Seri
203. level For the Intel Itanium Processor 9300 Series Intel Itanium Processor 9500 Series both are referenced to VSS It is important to note that overshoot and undershoot conditions are separate and their impact must be determined independently Pulse duration describes the total amount of time that an overshoot or undershoot event exceeds the overshoot or undershoot reference voltage Activity factor AF describes the frequency of overshoot or undershoot occurrence relative to a clock Since the highest frequency of assertion of a single ended signal is every other clock an AF 1 indicates that the specific overshoot or undershoot waveform occurs every other clock cycle Thus an AF 0 01 indicates that the specific overshoot or undershoot waveform occurs one time in every 200 clock cycles The highest frequency of assertion of any differential signal is every active edge of its associated clock not the reference clock So an AF 1 indicates that the specific overshoot or undershoot waveform occurs every cycle Overshoot Undershoot Specifications The overshoot and undershoot specifications listed in the following table specify the allowable overshoot or undershoot for a single overshoot or undershoot event Table 2 25 specifies the maximum overshoot and undershoot for the Intel Itanium Processor 9300 Series while Table 2 26 specifies the maximum overshoot and under shoot for the Intel Itanium Processor 9500 Series resp
204. ling link for Intel SMI for the Intel Itanium Processor 9500 Series The link consists of a transmitter and a receiver and the interconnect between them The specifications described in this section covers 6 4 Gb s operation The parameters for Intel SMI at 6 4 GT s and lower are captured in Table 2 11 and the PLL specification for transmit and receive are captured in Table 2 12 Table 2 11 Values for Intel SMI at 6 4 and lower Sheet 1 of 2 Intel Itanium Processor 9500 Series Transmitter and Receiver Parameter Symbol Parameter Min Nom Max Unit Notes Transmitter differential swing 800 1200 mV LOW CM DC DC resistance of Tx terminations at half the single ended swing which is usually 0 25 VTx_ditf pp pin bias point 37 4 50 ZRX LOW CM DC DC resistance of Rx terminations at half the single ended swing which is usually 0 25 VTx_ditf pp pin bias point 37 4 50 V Tx diff pp CLK pin Transmitter differential swing using a CLK like pattern 0 9 min VTx diff pp pin max VTxdiff pp pin mV Vtx cm de pin Transmitter output DC common mode defined as average of Vp and Vp 0 23 0 27 Fraction of VTx diff pp pin Transmitter output common mode defined as Vp4 Vp 2 Vtx cm de pin 0 0375 0 0375 Fraction of VTx diff pp pin TXduty Ul pin
205. ll RSVD RESERVED pins must be left unconnected Connection of these pins to power VSS or to any other signal including each other can result in component malfunction or incompatibility with future processors Intel Itanium Processor 9300 Series 9500 Series Datasheet 63 tel Electrical Specifications For reliable operation always terminate unused inputs or bi directional signals to their respective deasserted states A resistor must be used when tying bi directional signals to power or ground also allowing for system testability Unused pins of Intel QuickPath Interconnect and FB DIMM ports may be left as no connects since termination is provided on the processor silicon Unused outputs may be terminated on the system board or left connected Note that leaving unused outputs unterminated may interfere with some Test Access Port TAP functions complicate debug probing and prevent boundary scan testing Signal termination for these signal types is discussed in latest revisions of Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series Platform Design Guide Debug pins have ODT and can be left as no connects Their routing guidelines are provided in the Intel Itanium Processor 9300 Series and Intel Itanium9 Processor 9500 Series Platform Design Guide 2 10 Mixing Processors Intel will support mixing CPUs in the same system or hard partition as defined below A hard partition is a s
206. ll have a value of 8 Intel Itanium Processor 9300 Series 9500 Series Datasheet System Management Bus 1 tel 6 4 3 3 6 4 3 4 6 4 4 6 4 4 1 6 4 4 2 6 4 4 3 6 4 4 4 Core Voltage Offset 28h 29h is the nominal core voltage for this part rounded to the next thousandth is in mV and is reflected in bcd Example 1500 mV is represented as 1500 Core Voltage Tolerance Offsets 2Ah and 2Bh contain the core voltage tolerances high and low respectively These use a decimal to Hexadecimal conversion Example 19 mV tolerance would be saved as 13h Processor Uncore Data This section contains silicon related data relevant to the processor Uncore Maximum Intel QuickPath Interconnect Link Transfer Rate Offset 2Eh 30h provides maximum operating link transfer rate for the Intel QuickPath Interconnect A link rate of 4 8 GT s is expressed as 6 bcd digits in MT s Example 4 8 GT s 004800 Minimum Operating I ntel QuickPath nterconnect Link Transfer Rate Offset 31h 33h provides minimum operating link transfer rate for the Intel QuickPath Interconnect Systems may need to read this offset to decide if all installed processors support the same link transfer rate This does not relate to the link power up transfer rate of 1 4th Ref Clk This value is represented by 6 bcd digits Intel QuickPath Interconnect Version Number Offset 34h 37h provides the In
207. lock Frequency Table Intel QuickPath I nterconnect Intel QuickPath I nterconnect Data Forwarded Clock Frequency Transfer Rate 33 33 MHz 66 66 MT s see note 1 2 40 GHz 4 8 GT s Notes 1 This speed is the 1 4 SysCIk Frequency Table 2 5 Intel Itanium Processor 9300 Series Transmitter Parameter Values for Intel QuickPath I nterconnect and Intel SMI Channels 4 8 GT s Sheet 1 of 2 Symbol Parameter Min Nom Max Units Notes Ulayg Average UI size at 4 8 GT s 208 33 ps NwiN UI Validation of UI over which the eye mask voltage 1 6 timing spec needs to be validated Tslew rise fall pin Defined as the slope of the rising or falling 6 12 V ns waveform as measured between 100 mV of the differential transmitter output data or clock VTx diff pp pin Transmitter differential swing 900 1300 mV Transmitter termination resistance 37 4 47 6 4 ZTX LINK DETECT Link Detection Resistor 500 2000 LINK DETECT Link Detection Resistor Pull up Voltage max VCCIO TpATA TERM SKEW Skew between first to last data termination 600 UI 2 Intel meeting 2 iow cM pc TERM SKEW Skew between first to last data termination 780 UI 2 Intel SMI meeting 2 cM Dc TiNBAND RESET sense Time taken by inband reset detector to sense 8k 256k UI 7 7 Reset Time taken by clock detector to observe clock 8k 256k UI 7 stability TsySCLK TX VARIABILITY Phase variability between reference Clk at Tx 500 ps inpu
208. ly Parallel Instruction Computing EPIC is enhanced on the Intel Itanium Processor 9500 Series by increasing the capacity of retiring instructions per cycle from 6 to a maximum of 12 instructions per cycle per core Intel Hyper threading Technology is enhanced in the Intel Itanium Processor 9500 Series with dual domain multithreading which enables independent front end and back end pipeline execution to improve multi thread efficiency and performance for both new and legacy applications It provides hardware support for two threads per core with a threaded 96 entry per thread Instruction Buffer and threaded MLDTLB and FLDTLB and a dedicated load return path from the MLD to the integer register file Three levels of on die cache minimize overall memory latency with 16 KB instruction cache FLI 16 KB write through data cache FLD that comprise the FLC and 512 KB MLI 256 KB writeback data cache MLD that comprise the MLC The Intel Itanium Processor 9500 Series offers a new RAS feature Intel Instruction Replay Technology Pipeline replay resolves stall conditions that occur when the microprocessor pipeline encounters a resource hazard that prevents immediate execution In a replay the instruction that encountered the resource hazard is removed from the pipeline along with all the instructions that come after it The instruction is then read again out of the instruction buffer for replay and re executed To ensure Intel Itanium Process
209. m connecting Tx and Rx UI VRx CLK Forward CLK Rx input voltage sensitivity differential pp 150 mV VRx cm dc pin DC common mode ranges at the Rx input for any data or clock channel 90 350 mV VRx cm ac pin AC common mode ranges at the Rx input for any data or clock channel defined as Vp4 2 7 VRX cm dc pin 50 50 mV Notes 1 1300 mVpp swing is recommended when CPU to CPU or CPU to length is within 2 of max trace length Note that default value is 1200 mVpp 2 Measure AC CM noise at the TX and decimate to its spectral components For all spectral components above 3 2 GHz apply the attenuation of the channel at the appropriate frequency If the resultant AC CM at the receiver is met after taking out the appropriate spectral components meets the RX AC CM spec then we can allow the transmitter AC CM noise to pass Measured with neighboring lines being quiet and the remaining lines toggling PRBS patterns DC CM can be relaxed to 0 20 and 0 30 Vdiffp p swing if RX has wide DC common mode range Based on transmitting a PRBS pattern Intel Itanium Processor 9300 Series 9500 Series Datasheet Electrical Specifications 2 4 3 intel Intel I tanium Processor 9500 Series Processor Requirements for ntel SMI Specifications for 6 4 GT 5 This section defines the high speed differential point to point signa
210. m amp Processor Reserved for future use 49h 0x00 9500 Series Intel Itanium amp Processor 9500 Intel Itanium amp Series Processor 9500 Series 146 Intel Itanium Processor 9300 Series 9500 Series Datasheet System Management Bus 1 intel Table 6 1 Processor Information ROM Data Sheet 4 of 6 Sec Offset Field Name Data Type Description Example 74 4Ah Cache Voltage 2 Hex digits Edge finger tolerance in mV 20 mV 0 14 Tolerance High Intel amp Intel Itanium Processor 9300 Intel Itanium Series Processor 9300 Series 5 0 00 RESERVED Intel Reserved for future use Intel Itanium 2 t Intel Itanium Processor 9500 Processor 9500 Series Series 75 4Bh Cache Voltage 2 Hex digits Edge finger tolerance in 20 mV 0x14 Tolerance Low Intel Intel Itanium Processor 9300 Intel Itanium Series Processor 9300 Series 5 Reserved for future use 0x00 RESERVED Intel Intel Itanium Processor 9500 Intel Itanium Itanium Processor Series 9500 9500 Series rocessor eries 76 4Ch RESERVED Hex Reserved for future use 4Ch 0x00 77 ADh 4Dh 0x00 78 4Eh Checksum Hex Add up by byte and take 2 s complement Package 79 4Fh Package Revision Five 8 bit ASCII Package Revision Tracking Revision OINT3
211. m normal operating temperature of the processor PROCHOT_N is asserted when the processor temperature is greater or equal to PROCHOT_N is a signal from the processor to the platform indicating that the processor has detected an over temperature condition and it is taking corrective measures This pin is not asserted when FORCEPR_N or VR_THERMALERT_N is asserted unless the thermal system has detected a PROCHOT condition independent of those input signals The condition may occur due to any of the following conditions The thermal environment 15 outside of the limits defined for full performance operation The processor power consumption is unbalanced due to very high activity factors in some cores coupled with very low activity factors in others FORCEPR_N Signal Pin FORCEPR_N is an input pin that will force the processor into one of two modes The default mode is the same state as PROCHOT_N The processor will go into Single Issue Mode SIM and also transition to the voltage and frequency of the lowest supported P state Time limits and CMCI generation are the same as PROCHOT_N The second mode selectable QR CSR IPF THERM CONFIG forcepr mode disables SIM and timer functions while maintaining core frequency and voltage throttling Both modes can be disabled via QR CSR IPF THERM CONFIG forcepr disable Ararat Voltage Regulator Thermal Signals The Intel Itanium Processor 9300 Series and Intel Itan
212. maller system capable of booting an OS consisting of one or more processors memory and 1 0 controller hubs that are formed by domain partitioning 1 CPUs from adjacent steppings For example if one cpu is from stepping and another cpu is from the next stepping N 1 then CPUy are compatible Similarly is not compatible with CPU 2 2 CPUs in the system or hard partition must have the same core clock speed speed range and the same cache size 3 All Intel links must have the same data rate except for Intel links which are disabled or in slow mode Additionally for the Intel Itanium9 Processor 9300 Series 4 If variable frequency mode VFM is enabled one CPU it must be enabled in all CPUs If VFM mode is disabled in one CPU it must be disabled in all CPUs 5 Mixing an enabled VFM part with an fixed frequency mode FFM part within the same system or hard partition 2 11 Supported Power up Voltage Sequence The supported order of voltage sequencing for the processor detailed in Figure 2 17 and Figure 2 18 and Table 2 39 is VCC33 5 VccArarat 12V VCCIO VCCUNCORE and VCCCORE for the Intel Itanium Processor 9500 Series processor and followed by VCCCACHE for the Intel Itanium Processor 9300 Series processor If customers need to apply VccArarat 12V before SM the processor will not sustain damage The application of VCC33 SM before VccArarat 1
213. mensional Table 111 3 2 4 Top Side 4 Connector Two Dimensional Table 114 4 Mechanical Specifications 119 4 1 Package Mechanical 0 0 2 2 0 nnns 120 4 2 Intel Itanium Processor 9300 2 2 4 8 121 4 3 Processor Component Keepout 0 5 129 4 4 Package Loading 5 5 129 4 5 Package Handling eee ee ee enn 129 4 6 X Processor Mass 5 eee eene enn 130 4 7 Processor 15 nice cn n s dots d nn i CD LR e ta 130 4 8 Package Markings ier VERRE TERM RERBA DRE 130 5 Thermal Specifications core rro ine ae va E i t i Pin 133 5 Thermal Features xi eate ago tn EA ERE OR PARES 133 5 1 1 Digital ceeds ioe dea vedi Poe 134 5 1 2 Thermal mene ener 135 5 1 3 Thermal asco cemere e eame Re etn rera ara dade i daa 136 5 1 4 TCONTROHLE EI
214. mination is connected Table 2 9 Intel Itanium Processor 9500 Series Transmitter and Receiver Parameter 34 Values for Intel QPI Channel at 4 8 s Sheet 1 of 2 Symbol Parameter Min Nom Max Unit Notes Vix diff pp pin Transmitter differential swing 900 1400 1 LOW CM DC DC resistance of Tx terminations 37 4 50 Q zn at half the single ended swing which is usually 0 25 Vr gir pp pin bias point ZRX LOW CM DC DC resistance of Rx terminations 37 4 50 Q at half the single ended swing which is usually 0 25 Vr ditf pp pin bias point Transmitter output DC common 0 23 0 27 Fraction of mode defined as average of Vp Vix diff pp pin and Vp Transmitter output AC common 0 0375 0 0375 Fraction of 2 mode defined as Vp4 2 TXauty pin Average of UI UI jitter 0 055 0 055 UI TXjitui Ut 1E 7 pin UI UI jitter measured at Tx output 0 075 0 075 UI pins with 1E 7 probability TXjitul UI 1E 9 pin UI UI jitter measured at Tx output 0 085 0 085 Ul pins with 1 9 probability Intel Itanium Processor 9300 Series 9500 Series Datasheet Electrical Specifications tel Table 2 9 Table 2 10 Intel Itanium Processor 9500 Series Transmitter and Receiver Parameter Values for Intel QPI Channel at 4 8 GT s Sheet 2 of 2
215. mponent once installed onto the application board are not specified Intel does not conduct component level certification assessments post subsequent applications such as components sub assembly FRU Field Replaceable Unit or installation onto a board given the multitude of attach methods and board types used by customers Provided as general guidance only Intel board products are specified and certified to meet the following temperature and humidity limits Non Operating Temperature Limit 40 C to 70 C and Humidity 50 to 90 non condensing with a maximum wet bulb of 28 C Table specifies absolute maximum and minimum storage temperature limits which represent the maximum or minimum device condition beyond which damage latent or otherwise may occur The table also specifies sustained storage temperature relative humidity and time duration limits These limits specify the maximum or minimum device storage conditions for a sustained period of time At conditions outside sustained limits but within absolute maximum and minimum ratings quality and reliability may be affected Intel Itanium Processor 9300 Series 9500 Series Datasheet Thermal Specifications tel Table 5 5 Storage Condition Ratings Symbol Parameter Min Max Notes Tabs storage The minimum maximum device storage 55 C 125 C 1 2 3 4 temperature beyond which damage latent or otherwise may occur when subjected to for any length of time
216. n Guide for further details The processor is capable of drawing ICC CORE indefinitely 3 During system power on the pulse inrush ICC CORE STEP can be as high as 35A peak to peak 4 UNCORE TDC is the sustained DC equivalent current that the processor uncore is capable of drawing indefinitely and should be used for the Ararat voltage regulator temperature assessment The Ararat voltage regulator is responsible for monitoring its temperature and asserting the VR THERMALERT VR THERMTRIP signals sequentially to inform the processor and platform of a thermal excursion Of the three signals only VR THERMALTERT is monitored by the processor Please see the Ararat Voltage Regulator Module Design Guide for further details The processor is capable of drawing ICC UNCORE TDC indefinitely This parameter is based on design characterization and is not tested 5 During system power on the pulse inrush ICC UNCORE STEP can be as high as 40A peak to peak 6 The CC 10 current specification applies to the total current from VCCIO pins 7 The max load step represents the maximum current required during Intel QPI and Intel9 SMI port initialization The min time 2 6 3 2 44 between steps represents the time between Intel and Intel SMI initialization Intel Itanium Processor 9300 Series Uncore Core and Cache Tolerances 6 3 1 Uncore Static and Transient Tolerances Table 2 20 and Figure
217. n absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within operational maximum and minimum ratings after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits Intel Itanium Processor 9300 Series 9500 Series Datasheet intel Electrical Specifications At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Intel Itanium Processor 9300 Series Absolute Maximum Ratings 2 5 1 Table 2 13 Intel Itanium Processor 9300 Series Absolute Maximum Ratings Symbol Parameter Min Max Units Notes VcccoRE Processor core supply voltage with respect to 55 0 3 1 55 1 2 VCcCUNCORE Processor uncore supply voltage with respect
218. nd FB DIMM signals When designing a system Intel strongly recommends that design teams perform analog simulations of the Intel QuickPath Interconnect and FB DIMM pins Please refer to the latest available revision of the Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series Platform Design Guide Figure 2 1 illustrates the active on die termination ODT of these differential signals All the differential signals listed in Table 2 1 have ODT resistors Also included in the table are the debug signals Figure 2 1 Active ODT for a Differential Link Example Signal Rx Signal Intel Itanium Processor 9300 Series and 9500 Series Datasheet 23 intel Table 2 1 2 2 Table 2 2 24 Signals with RTT Signal CSI 3 0 R P N Dat 19 0 CSI 5 4 R P N Dat 9 0 CSI 3 0 T P N Dat 19 0 CSI 5 4 T P N Dat 9 0 5115 0 CSI 5 0 T P N CIK vss Termination FBDONBICLK A B P N O FBD1NBICLK C D P N O FBDOSBOCLK A B P N O FBD1SBOCLK C D P N O FBDONBI A B P N 13 0 FBDINBI C D P N 13 0 FBDOSBO A B P N 10 0 FBD1SBO C D P N 10 0 VSS XDPOCPD_N 7 0 TRIGGER_N 1 0 XDPOCPFRAME_N XDPOCP_STRB_IN_N PRBMODE_REQST_N XDPOCP_STRB_OUT_N PRBMODE_RDY_N Signal Groups Electrical Specifications The signals are grouped by buffer type and similar characteristics as listed in Table 2 2 The
219. ngle ended DC 4k 1 impedance to GND for either D or D of any data bit at Rx ZRx_HIGH_CM_DC Intel Itanium Processor 9300 Series 9500 Series Datasheet 33 intel Electrical Specifications Table 2 8 Intel Itanium Processor 9500 Series Link Speed Independent Specifications Sheet 2 of 2 Symbol Parameter Min Nom Max Unit Notes ZTX LINK DETECT Link Detection Resistor 500 2000 LINK DETECT Link Detection Resistor max VCCIO 7 07 Pull up Voltage TERM SKEW Skew between first to last 128 UI 7 data termination meeting ZRX LOW CM DC TINBAND RESET Time taken by inband 1 5 SENSE reset detector to sense Inband Reset pet Time taken by clock 20K Ul 7 detector to observe clock stability TCLK_FREQ_DET Time taken by clock 32 Reference frequency detector to Clock Cycles decide slow vs operational clock after stable clock TRefclk Tx Variability Phase variability between 500 psec reference Clk at Tx input and Tx output TRefclk Rx Variability Phase variability between 1000 psec reference Clk at Rx input and Rx output LD D RX Skew Phase skew between D 0 03 UI and D lines for any data bit at Rx BERLane Bit Error Rate per lane 1 0E 14 Events valid for 4 8 and 6 4 GT s Notes 1 Used during initialization It is the state of OFF condition for the receiver when only the minimum ter
220. ns for the ntel Itanium Processor 9500 Series Symbol Parameter Max Min Units Notes lec for core 35 0 A 1 TDC Thermal Design Current for Core 30 0 A 1 2 Icc 5 Load step for core 14 62 A 1 3 dicc CORE dt Slew rate for core at Ararat output 34 4 A us 1 I cC UNCORE lec for uncore 80 0 A UNCORE Thermal Design Current Uncore 75 0 A 4 UNCORE STEP Max Load step for uncore 30 4 A 5 dl CC UNCORE dt Slew rate for uncore at Ararat output 168 0 A us Icc 10 for processor 1 0 17 2 6 dicc 1o dt Slew rate for 10 at the package pin 54 0 A us 10 5 Load step max slew 5 1 A 10 STEP Time between steps 4 7 us 7 Analog processor Analog 4 5 main supply 200 Notes 1 Values per core pair 2 CORE TDC is the sustained DC equivalent current that the processor core is capable of drawing indefinitely and should be used for the Ararat voltage regulator temperature assessment The Ararat voltage regulator is responsible for monitoring its temperature and asserting the VR_FAN_N VR_THERMALERT_N VR_THERMTRIP_N signals sequentially to inform the processor and platform of a thermal excursion Of the three signals only VR THERMALTERT N is monitored by the processor Please see the Ararat 11 Voltage Regulator Module Desig
221. ntel Itanium 9300 Series and Intel Itanium 9500 Series Platform Design Guide for recommended resistor values 4 VR THERMALERT is an input to the top of the package and an output from the bottom of the package and Vj levels are for the input at the top of the package sensed by the processor and Vo are for the output levels on the package pins at the bottom of the package TAP and System Management Group DC Specifications Symbol Parameter Min Max Unit Notes Vu Input Low Voltage 0 VCCIO 0 5 0 2 V Input High Voltage VCCIO 0 5 0 2 VCCIO V Output High Voltage VCCIO 0 2 V VoL Output Low Voltage 0 0 25 V 1 Output Low Current 16 23 mA 1 li Leak Input Leakage Current 200 200 2 3 4 Output Leakage Current 1000 200 Notes 1 With 50 W termination to VCCIO at the far end 2 With V at the pin at 1 1 V and 0 V System designers are advised to check the tolerance of their voltage regulator solutions to ensure V at the pin is 1 1 V 3 Internal weak pull up included for TCLK 4 Internal weak pull up included for TRST_N TMS and TDI Table 2 30 Error FLASHROM Power Up Setup and Thermal Group DC Specifications 54 Symbol Parameter Min Max Unit Notes ViL Input Low Voltage 0 VCCI O 0 67 0 2 V Vin Input High Voltage VCCIO 0 67 0 2 V
222. ntel Itanium Processor 9500 2 0 110 Top Side J3 Connector Two Dimensional Table Intel Itanium Processor 9300 2 111 Top Side 3 Connector Two Dimensional Table Intel Itanium Processor 9500 Series 113 Top Side 4 Connector Two Dimensional Table Intel Itanium Processor 9300 0 44 114 Top Side 4 Connector Two Dimensional Table Intel Itanium Processor 9500 0 4 116 Processor Loading 5 129 Package Handling 129 Processor Package Insertion Specification mme 130 Package Material ipi ap MAI 130 1248 FCLGA Package Marking ZONES 130 Thermal Sensor Accuracy Distribution for the Intel Itanium Processor 9300 134 Thermal Sensor Accuracy Distribution for the Intel Itanium Processor 9500 Series 135 Thermal Specification for the Intel Itanium Processor 9300 139 Thermal Specification for the Intel Itanium Processor 9500 Series Processor 139 Storage Condition 6
223. ntel Itanium Processor 9300 Series VccUNCORE Tolerance Bands s AC V 0 00 5 DC max 0 02 Typical Vcc V x DC min V 0 04 AC min V 0 06 5 0 08 9 5 012 5 0 14 046 0 18 0 20 0 22 0 24 0 5 10 15 20 25 30 35 40 45 50 1 Intel Itanium Processor 9300 Series and 9500 Series Datasheet 45 m e n tel Electrical Specifications 2 6 3 2 Core Static and Transient Tolerances Table 2 21 and Figure 2 11 specify static and transient tolerances for the core outputs Table 2 21 Static and Transient Tolerance for Intel Itanium Processor 9300 Series Sheet 1 of 2 Core Current A Voltage Deviation from VID Setting V 1 2 3 4 Vcc Max Vcc Typ Vcc Min 0 VID 0 VID 0 02 VID 0 04 5 VID 0 004 VID 0 024 VID 0 044 10 VID 0 009 VID 0 029 VID 0 049 15 VID 0 013 VID 0 033 VID 0 053 20 VID 0 017 VID 0 037 VID 0 057 25 VID 0 021 VID 0 041 VID 0 061 30 VID 0 026 VID 0 046 VID 0 066 35 VID 0 03 VID 0 05 VID 0 07 40 VID 0 034 VID 0 054 VID 0 074 45 VID 0 038 VID 0 058 VID 0 078 50 VID 0 043 VID 0 063 VID 0 083 55 VID 0 047 VID 0 067 VID 0 087 60 VID 0 051 VID 0 071 VID 0 091 65 VID 0
224. ntia 7 FBDONBIBP 2 Differentia K2 FBDOSBOAP 10 Differentia 6 FBDONBIBP 3 Differentia 8 FBDOSBOBN 0 Differentia 6 FBDONBIBP 4 Differentia 7 FBDOSBOBN 1 Differentia AL5 FBDONBIBP 5 Differentia FBDOSBOBN 2 Differentia 1 FBDONBIBP 6 Differentia AF7 FBDOSBOBN 3 Differentia FBDONBIBP 7 Differentia 6 FBDOSBOBN 4 Differentia 1 FBDONBIBP 8 Differentia 4 FBDOSBOBN 5 Differentia 2 FBDONBIBP 9 Differentia FBDOSBOBN 6 Differentia 2 FBDONBIBP 10 Differentia FBDOSBOBN 7 Differentia 1 FBDONBIBP 11 Differentia FBDOSBOBN 8 Differentia 2 FBDONBIBP 12 Differentia 7 5 9 Differentia 4 FBDONBIBP 13 Differentia FBDOSBOBN 10 Differentia AL10 FBDONBIBP 14 Differentia 9 FBDOSBOBP 0 Differentia 5 FBDONBICLKANO Differentia 7 FBDOSBOBP 1 Differentia 5 FBDONBICLKAPO Differentia 7 FBDOSBOBP 2 Differentia FBDONBICLKBNO Differentia AF8 FBDOSBOBP 3 Differentia 4 FBDONBI CLKBPO Differentia 6 FBDOSBOBP 4 Differentia Intel Itanium Processor 9300 Series 9500 Series Datasheet 79 intel Pin Listing Table 3 1 Pin List by Pin Name Sheet 15 Table 3 1
225. onding to the state of VID VCCCORE and VID VCCUNCORE for the Intel Itanium Processor 9300 Series and Intel tanium Processor 9500 Series respectively 1 in this table refers to high voltage level and a 0 refers to a low voltage level The Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series provide the ability to operate while transitioning to an adjacent VID and its associated processor core voltage VCCCORE This will represent a DC shift in the load line It should be noted that a low to high or high to low voltage state change may result in many VID transitions as necessary to reach the target core voltage Transitions above the specified VID are not permitted The Ararat voltage regulator must be capable of regulating its output to the value defined by the new VID Please refer to the Ararat 170 Watt Voltage Regulator Module Design Guide for the Intel Itanium Processor 9300 Series processor or the Ararat 11 Voltage Regulator Module Design Guide for the Intel Itanium Processor 9500 Series Intel Itanium Processor 9300 Series 9500 Series Datasheet 57 m e n tel Electrical Specifications 2 7 1 Core and Uncore Voltage Identification for the Intel Itanium Processor 9300 Series Table 2 36 Intel Itanium Processor 9300 Series VCCCORE VID VCCCORE and VCCUNCORE and VID VCCUNCORE Voltage Identification Definition for Ararat Sheet 1 of 2
226. one processor ncludes Dynamic Domain Partitioning Advanced EPIC Explicitly Parallel Instruction Computing Architecture for current and future requirements of high end enterprise and technical workloads Provide a variety of advanced implementations of parallelism predication and speculation resulting in superior I nstruction Level Parallelism ILP Intel Hyper Threading Technology Two times the number of OS threads per core Wide parallel hardware based on Intel Itanium architecture for high performance ntegrated on die L3 cache of up to 24 MB cache hints for L1 L2 and L3 caches for reduced memory latency 128 general and 128 floating point registers supporting register rotation Register stack engine for effective management of processor resources Support for predication and speculation m Extensive RAS features for business critical applications for example Machine check architecture with extensive ECC and parity protection On chip thermal management Built in processor information ROM PIROM Built in programmable EEPROM Hot Plug Socket Hot add and hot removal Double Device Data Correction DDDC for x4 DRAMs plus correction of a single bit error Single Device Data Correction SDDC for x8 DRAMs plus correction of a single bit error Intel QuickPath Interconnect Dynamic Link Width Reduction Intel Quic
227. onnects enables each processor to directly connect to other system components thus can be used as an effective building block for very large systems The balanced core and memory subsystem provide high performance for a wide range of applications ranging from commercial workloads to high performance technical computing The Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series are pin compatible and support a range of computing needs and configurations from a 2 way to large SMP servers although OEM field upgrade methodologies vary This document provides the electrical mechanical and thermal specifications that must be met when using the Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series in your systems Intel Itanium Processor 9300 Series and 9500 Series Datasheet 9 10 Introduction Intel Itanium Processor 9300 Series and 9500 Series Datasheet Introduction intel Intel Itanium Processor 9300 Series Intel Itanium Processor Quad Core 1 86 1 73 GHz with 24 L3 Cache 9350 Intel Itanium Processor Quad Core 1 73 1 60 GHz with 20 MB L3 Cache 9340 Intel Itanium Processor Quad Core 1 60 1 46 GHz with 20 MB L3 Cache 9330 Intel Itanium Processor Quad Core 1 46 1 33 GHz with 16 MB L3 Cache 9320 I ntel Itanium Processor Dual Core 1 60 GHz Fixed Frequency with 10 MB L3 Cache 9310 Product Features Quad Core Four complete 64 bit processing cores on
228. oot to an operating system and provide runtime functionality Further information about SAL is available in the Intel Itanium Processor Family System Abstraction Layer Specification Mixing Processors of Different Frequencies and Cache Sizes All Intel Itanium Processor 9300 Series processors and Intel Itanium Processor 9500 Series in the same system partition are required to have the same last level cache size and identical core frequency Mixing processors of different core frequencies cache sizes and mixing Intel Itanium Processor 9300 Series with Intel Itanium Processor 9500 Series is not supported and has not been validated by Intel Operating system support for multiprocessing with mixed components should also be considered Terminology In this document the processor refers to the Intel Itanium Processor 9300 Series and or Intel Itanium Processor 9500 Series unless otherwise indicated An N notation after a signal name refers to an active low signal This means that a signal is in the active state based on the name of the signal when driven to a low level For example when RESET N is low a processor reset has been requested When NMI is high a non maskable interrupt has occurred In the case of lines where the name does not imply an active state but describes part of a binary sequence such as Intel Itanium Processor 9300 Series and 9500 Series Datasheet Introduction 1 7 1 8 Note intel
229. operating conditions It provides several hooks to the OS and system management to monitor and change the processor performance and thermal status With the power and thermal management system on the Intel Itanium Processor 9300 Series and Intel Itanium9 Processor 9500 Series typical applications see a higher core frequency resulting in higher performance the Intel Itanium9 Processor 9300 Series and Intel Itanium Processor 9500 Series base frequency is based on an activity factor determined by the highest known activity factor in benchmark suites Boost frequency is available when the processor is not power limited The Intel Itanium9 Processor 9500 Series enables Intel Turbo Boost Technology featuring sustained boost Processor performance is optimized for a given power envelope and is integrated into the processor core Power management optimizes the processor performance for a given TDP Thermal Design Power The core activity levels are monitored in real time and each core enforces its own AFT Activity Factor Throttling to keep the processor at TDP for high activity applications Instruction dispersal is lowered in a core to keep the activity of the core within TDP when an over TDP condition is detected AFT is transparent to software running on the processor Thermal Features The Intel Processor 9300 Series and Intel Itanium Processor 9500 Series have internal thermal sensors which sense when a ce
230. or 9300 Series and 9500 Series Datasheet Introduction 1 2 1 2 1 intel replay can be initiated for any instruction in the pipeline that encounters a resource hazard a copy of each instruction is maintained in the instruction buffer until the instruction has successfully traversed the pipeline and is no longer needed If necessary an instruction can replay multiple times As a result Intel Instruction Replay Technology automatically detects and many corrects soft errors in the instruction pipeline With this technology soft errors can be identified and corrected in as few as seven clock cycles which is fast enough to be invisible to the software running on the platform Architectural Overview The sections below give an overview of the Intel Itanium Processor 9300 Series Intel Itanium Processor 9500 Series Intel Itanium Processor 9300 Series Overview The Intel Itanium Processor 9300 Series processor is a quad core architecture It supports up to four processor cores each with its own L3 L2 and L1 level cache Also supported are the following page sizes for purges or inserts 4K 8K 16K 64K 256 1M 4M 16M 64M 256M 1 4G The architecture interfacing the cores to the system is referred to as the System Interface Each processor core has it own Caching Agent CPE The CPE interfaces between the processor core and the Intel QuickPath Interconnect The Intel Itanium Processor 9300 Series processo
231. ory controller supports two Intel9 Scalable Memory Interconnects that operate in lockstep Support for one Scalable Memory Buffer per Intel Scalable Memory Interconnect four Scalable Memory Buffers per processor High memory bandwidth thus improved performance 4 8 GT s for the Intel 7500 Scalable Memory Buffer 6 4 GT s for the Intel 7510 Scalable Memory Buffer Intel Instruction Replay Technology to replay core pipeline for pipeline management and core RAS Intel virtualization Technology Intel VT for Intel 64 or Itanium Sarchitecture Intel 9 vt i Virtualization Support Extensions for Intel Virtualization Technology Reduce virtualization complexity Improve virtualization performance via hardware optimization Increase operating system compatibility Intel Cache Safe Technology ensure mainframe caliber availability Minimize LLC cache errors Disable cache entries that have become hard errors Directory Cache covers 33 more cache lines Improve availability High bandwidth Intel QuickPath Interconnect for multiprocessor scalability 4 full and 2 half width Intel QPI Links 6 4GT s transfer rate with aggregate data bandwidth of 28 8 GB s Systems are easily scaled without sacrificing performance Features to support flexible platform environments Fully compatible with binaries for the Intel Itanium processor family with Instruction level ad
232. out for the Intel Itanium Processor 9500 Series The margin of error is relative to PROCHOT and represents the typical 3 sigma range For the Intel Itanium amp Processor 9500 Series it is based on presilicon simulation data It should be noted that a particular part should be consistent across the entire operating range Table 5 2 Thermal Sensor Accuracy Distribution for the Intel tanium Processor 9500 Series DT Readout Expected Margin of Error Relative to PROCHOT 0x83 0x80 0x00 0x03 1 0 04 0 32 3 0 33 0 49 5 5 1 2 Thermal Management 5 1 2 1 Overview The Thermal Management controller on the processor will measure the die temperature using thermal sensors placed in several key locations on the die Each sensor is fed into a central thermometer logic block For the Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series the central thermometer logic block will report the highest temperature of all sensors Referring to Figure 5 1 the sequence of steps taken by the processor thermal management system are presented in steps a to d a gt and the Intel Itanium Processor 9300 Series is operating at boost frequency then the thermal management system will instruct the processor to go to base voltage and frequency After a delay if the processor temperature is below the threshold normal operation
233. ower Other AR25 CSI3TPDAT 6 Differential 24 VCCIO Power Other AR26 vss Power Other AP25 CSI3TNDAT 6 Differential AR27 CSI3RPDAT 15 Differential 26 CSI3TPDAT 7 Differential AR28 VCCIO Power Other AP27 RSVD AR29 vss Power Other AP28 VSS Power Other AR30 VCCIO Power Other AP29 511 31 Differential 1 VSS Power Other AP30 CSI1TPDAT 4 Differential AR32 SMBDAT SMBus 1 0 AP31 CSI1TNDAT 4 Differential CSI1RPDAT 3 Differential 2 511 61 Differential 4 CSI IRNDAT 3 Differential VSS Power Other AR35 VCCIO Power Other AP34 VCCIO Power Other AR36 VSS Power Other AP35 CSI 1RPDAT 5 Differential 7 511 61 Differential 6 CSI1RNDAT 5 Differential AR38 RSVD AP37 CSI1RNDAT 6 Differential 1 VSS Power Other AP38 VSS Power Other AT2 RSVD 1 RSVD AT3 CPU_PRES4_N 1 0 AR2 FBDONBIAN 12 Differentia VSS Power Other AR3 FBDONBIAP 12 Differentia 5 FBDONBICLKAPO Differentia 4 FBDONBIAP 6 Differentia 6 FBDONBIAN 5 Differentia 5 FBDONBICLKANO Differentia 7 VCCIO_FBD Power Other AR6 VSS Power Other AT8 FBDONBIAN 4 Differentia 7 FBDONBIBP 2 Differentia 9 VSS Power Other AR8 VCCIO FBD Power Other AT10 FBDONBIAP 3 Differentia ARQ PWRGOOD 11 FBDONBIAN 0 Differentia 10 FBDONBIAN 3 Differential 12 VSS Power Other AR11 VSS Power Other AT13 CSI5RNDAT 5 Differentia
234. processors may differ The processor may or may not have specifications equal to the FMB value in the foreseeable future Table 2 18 defines the FMB voltage specification values applied to the 130 W and 170 W SKUs for the Intel Itanium Processor 9500 Series Current specifications are identified for each processor SKU separately in Table 2 19 Table 2 18 FMB Voltage Specifications for the Intel tanium Processor 9500 Series Symbol Parameter Min Typ Max Units Notes CVI Drange VCCCORE VID Range 0 800 1 105 1 22 V 1 CVI DBoot VCCCORE VID default value 0 1 UVI Dnange VCCUNCORE VID Range 0 800 0 975 1 19 V 1 UVI VCCUNCORE VID default value 1 0 V 1 VCCUNCORE Processor uncore supply voltage See Table 2 23 and Figure 2 15 V 2 1 VCCCORE Processor core supply voltage See Table 2 24 and Figure 2 14 V 2 3 4 VID Transition VID step size during transition 25 mV VID DCshift Total allowable DC load line shift from VID 420 5 steps Processor I O supply voltage at die 1 011 1 050 1 094 V 6 including all AC and DC VCCIO Processor 1 supply voltage high 35 mV frequency AC p p noise at die VCCIO Processor 1 supply voltage at package 1 026 1 075 1 088 V 7 pin including all AC and DC VCCA Processor analog supply voltage DC spec 1 764 1 8 1 836 V 8 VCCA Processor analog supply voltage AC 1 8 x25 mV 8 9 tolerance for noise at scop
235. ps below TPROCHOT THYSTERESIS The processor will be in this low power mode for a minimum of 1 second and after 1 second will resume normal operation as soon as the temperature has decreased sufficiently If T2 TruERMwARN then the processor will issue fatal MCA and PROCHOT N will remain asserted the thermal management controller becomes non functional The processor cannot recover except via cold reset The processor will continue to throttle if gt when it comes out of reset Data integrity is not guaranteed beyond TryeRmwarn d If T gt Tryermtrip then the thermal management system will assert THERMTRIP and halt processor clocks 15 enforced to prevent physical damage to the processor Cold reset is required to recover Implementation The Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series thermal management features are designed to operate independently of software including the operating system The thermal sensors are on the die of the processor and the frequency and voltage control resides completely on the processor In order to reduce the processor power while throttling some execution units on the processor are shut down limiting the processor to executing only one instruction per cycle When the PROCHOT threshold is crossed and the processor enters low power mode a CMCI is sent to the OS and to the System Abstraction Layer SAL This in
236. r Other AT31 SPDDAT 1 0 AU33 CSI1RNDAT O Differentia 2 5 SMBus 1 0 AU34 CSI1RPDAT 2 Differentia 5118 0 Differential AU35 CSI1RPDAT 4 Differentia 4 VSS Power Other AU36 RSVD AT35 CSI 1RNDAT 4 Differential AU37 RSVD AT36 CPU_PRES3_N 1 0 AU38 vss Power Other AT37 RSVD AV1 RSVD AT38 RSVD AV2 RSVD AU1 RSVD AV3 VSS Power Other AU2 RSVD AV4 RSVD AU3 RSVD 5 VSS Power Other AUA FBDONBIANI 13 Differentia 6 VCC33_SM Power Other AU5 FBDONBIAP 13 Differentia 7 VCC33_SM Power Other AU6 FBDONBIAP 5 Differentia AV8 FBDONBIAN 2 Differentia 07 VSS Power Other FBDONBIAP 2 Differentia 08 FBDONBIAP 4 Differentia 10 VSS Power Other AU9 FBDONBIAN 1 Differentia 11 FBDONBI AN 14 Differentia AU10 FBDONBIAP 1 Differentia AV12 FBDONBIAP 14 Differentia 011 FBDONBIAP 0 Differentia AV13 VSS Power Other AU12 VSS Power Other 14 CSI5RPDAT 6 Differentia AU13 CSI5RPDAT 5 Differentia 15 VSS Power Other 014 CSI5RNDAT 6 Differentia 16 CSI 3RPDAT 6 Differentia AU15 CSI5RNDAT 8 Differentia 17 CSI 3RNDAT 6 Differentia AU16 CSI5RPDAT 8 Differentia 18 VSS Power Other AU17 VSS Power Other AV19 CSI 3RNDAT S8 Differentia 018 CSI 3RNDAT 7 Differentia 20 VSS Power Other 019 CSI3RPDAT 8 Differentia AV21 VCCA Power Other AU20 Power Other AV22 VCCA Power Other AU21 CSI3RNCLK D
237. r 9500 Series Intel Itanium Processor 9300 Series 9500 Series Datasheet System Management Bus 1 tel 6 4 6 6 4 6 1 6 4 6 2 6 4 7 6 4 7 1 6 4 7 2 6 4 7 3 6 4 7 4 6 4 8 6 4 8 1 Package Data Package Revision This section describes the package revision location at offset 4Fh 53h used to capture package technology This field tracks the highest level revision It is provided in ASCII Hex format of five characters This field is at offset 4Fh through 53h for the substrate layout design Substrate Revision Software This field is at offset 54h for the substrate layout design for the Intel Itanium Processor 9300 Series The field at offset 54h is reserved for the Intel Itanium Processor 9500 Series Part Number Data This section between 56h and 6Ah provides part tracing ability It also includes the processor s base frequency at 65h 66h Processor Part Number Offset 56h 5Ch contains seven ASCII characters reflecting the Intel part number for the processor This information is typically marked on the outside of the processor If the part number is less than 7 characters a leading space is inserted into the value Example A processor with a part number of 80546KF will have data as 46h 4bh 36h 34h 35h 30h 38h starting at offset 56h Processor Electronic Signature Offset 5Dh 64h contains a unique 64 bit identification number Base Frequency
238. r CPU to I OH length is within 2 of max trace length Note that default value is 1100 mVpp 2 Measure AC CM noise at the TX and decimate to its spectral components For all spectral components above 3 2 GHz apply the attenuation of the channel at the appropriate frequency If the resultant AC CM at the receiver is met after taking out the appropriate spectral components meets the RX AC CM spec then we can allow the transmitter AC CM noise to pass Intel I tanium Processor 9500 Series Transmitter and Receiver Parameter Values for Intel QPI at 6 4 GT s Sheet 1 of 2 Symbol Parameter Min Nom Max Unit Notes Transmitter differential swing 900 1400 1 ZTX LOW CM DC DC resistance of Tx terminations 37 4 50 Q at half the single ended swing which is usually 0 25 Vr pp pin bias point ZRx Low CM DC DC resistance of Rx terminations 37 4 50 Q at half the single ended swing which is usually 0 25 Vr pp pin bias point cm dc pin Transmitter output DC common 0 23 0 27 Fraction of 4 mode defined as average of Vp VTx diff pp pin and Vp Intel Itanium Processor 9300 Series 9500 Series Datasheet 35 Table 2 10 intel Electrical Specifications I ntel Itanium Processor 9500 Series Transmitter and Receiver Parameter Values for Intel at 6 4 GT s Sheet 2 of 2 Symbol Parameter Min Nom Max Unit
239. r has two Home Agents Bbox The Bbox interfaces between the memory controller and the Intel QuickPath Interconnect and supports a directory cache Each Bbox interfaces with a memory controllers Zbox Each memory controller supports two Intel SMI in lockstep The Intel SMI are the interconnects to Intel 7500 Scalable Memory Buffer The processor supports six Intel QuickPath Interconnects at the socket four full width and two half width The Caching Agent Home Agent and Intel QuickPath Interconnects are connected via a 12 port Crossbar Router each port supporting the Intel QuickPath Interconnect protocol Figure 1 1 shows the Intel Itanium Processor 9300 Series block diagram The Intel viral and poison fields are used to corrupted system state and bad data accordingly Once it has gone viral an Intel agent will set the viral field within all packet headers Viral mode is entered in three ways receiving a viral packet upon a detecting fatal panic error or when a global viral signal from Cboxes is asserted Viral is cleared on Reset Poisoning is used to indicate bad data on a per flit basis Poison does not indicate corrupted system coherency but rather that a particular block of data is not reliable Intel Itanium Processor 9300 Series and 9500 Series Datasheet 15 intel Figure 1 1 Intel Itanium Processor 9300 Series Processor Block Diagram
240. r lanes sending patterns Therefore for all Tx measurements use of a socket should be avoided The contribution of cross talk may be significant and should be done using the same setup at Tx and compared against the expectations of full link signaling Note that there may be cases when one of Dj and Rj specs is met and another violated in which case the signaling analysis should be ran to determine link feasibility 3 DC CM can be relaxed to 0 20 and 0 30 Vdiffp p swing if RX has wide DC common mode range Table 2 12 2 5 38 PLL Specification for TX and RX Symbol Parameter Min Max Units Notes Fpii Bw 3dB bandwidth 4 16 MHz JitPkrx Jitter Peaking 3 dB Processor Absolute Maximum Ratings Table 2 13 specifies absolute maximum and minimum ratings for the Intel Itanium Processor 9300 Series Within operational maximum and minimum limits the processor functionality and long term reliability can be expected The processor maximum ratings listed in Table 2 13 are applicable for the 130 W 155 W and 185 W parts Table 2 14 specifies absolute maximum and minimum ratings for the Intel Itanium9 Processor 9500 Series Within operational maximum and minimum limits the processor functionality and long term reliability can be expected The processor maximum ratings listed in Table 2 14 are applicable for the 130 W and 170 W parts At conditions outside operational maximum ratings but withi
241. re 4 6 Intel Itanium Processor 9300 Series and 9500 Series Datasheet m n tel Mechanical Specifications Figure 4 7 Intel Itanium Processor 9500 Series Package Drawing Sheet 2 of 4 9 24 ii L7 SIDA 5 ES E E E b 0000 1000 ziii d E 1 ya Lx 126 Intel Itanium Processor 9300 Series 9500 Series Datasheet Mechanical Specifications Figure 4 8 Intel Itanium Processor 9500 Series Package Drawing Sheet 3 of 4
242. re VROUTPUT ENABLEO high for Intel 21 us Itanium Processor 9300 Series 1 VCCIO stable before VROUTPUT ENABLEO high for Intel 21 ms Itanium Processor 9500 Series VROUTPUT ENABLEO high to VRPWRGOOD high for Intel 200 ms Itanium Processor 9300 Series 1 VROUTPUT ENABLEO high to VR READY for Intel Itanium 200 ms Processor 9500 Series VCCUNCORE time to stabilize 1 1 5 ms Delay from VCCUNCORE at programmed VID value to VCCCORE 1 0 05 8 ms VCCCORE steady at safe VID value 1 0 05 3 ms VCCCORE transition time from safe VID to programmed VID 1 2 5 Delay from VCCCORE VCCUNCORE VCCCACHE at programmed 0 05 3 values to VRPWRGOOD high for Intel Itanium Processor 9300 Series 1 VRPWRGD high to PWRGOOD high for Intel Intel Itanium gt 0 ms Processor 9300 Series VR READY high to PWRGOOD high for Intel Itanium Processor gt 0 ms 9500 Series PWRGOOD high to RESET N high Intel Itanium 10 ms Processor 9300 Series PWRGOOD high to RESET high tagser Intel Itanium 15 ms Supported Power down Voltage Sequence The supported power down sequence of voltage for the processor is detailed in Figure 2 19 It should be noted that when the processor is required to be physically removed from its socket power rails VCC33 SM and Vcc 12V must also be powered down before removal of the processor Intel Itanium Processor 9300 Series 9500 Series Datasheet Electrical Specifications
243. rentia 22 CSI 3RNDAT 10 Differentia M31 CSI 2TNDATT 13 Differentia AU23 CSI 3RNDAT 11 Differentia 830 512 14 Differentia 24 CSI 3RNDAT 12 Differentia 2 512 151 Differentia AU25 CSI 131 Differentia T31 CSI 2TNDATT 16 Differentia AU26 CSI 141 Differentia 029 512 171 Differentia 27 CSI 3RNDAT 15 Differentia 031 512 181 Differentia 028 CSI 3RNDAT 16 Differentia w30 512 19 Differentia 29 CSI 3RNDAT 17 Differentia 129 CSI2TPCLK Differentia AU30 CSI 181 Differentia 623 512 0 Differentia 1 CSI 3RNDAT 19 Differentia G25 CSI2TPDAT 1 Differentia 21 CSI3RPCLK Differentia 25 CSI2TPDAT 2 Differentia 18 CSI3RPDAT O Differentia 24 CSI2TPDAT 3 Differentia AL16 CSI 3RPDAT 1 Differentia 626 512 41 Differentia 15 CSI3RPDAT 2 Differentia 27 512 51 Differentia 16 CSI 3RPDAT 3 Differentia 029 512 6 Differentia 19 CSI 3RPDAT 4 Differentia 127 CSI2TPDAT 7 Differentia 18 CSI 3RPDAT 5 Differentia 628 512 81 Differentia 16 CSI3RPDAT 6 Differentia 28 CSI2TPDAT 9 Differentia 18 CSI3RPDAT 7 Differentia K29 512 101 Differentia 019 CSI 3RPDAT 8 Differentia 30 512 11
244. riod 3 Ci ck Clock Input Capacitance 0 5 2 0 pf VH Differential High Input Voltage 0 15 3 VL Differential Low Input Voltage 0 15 V 3 Vcross Absolute crossing point 0 25 0 35 0 55 1 5 6 Vcross delta Peak peak variation 140 mv 1 5 7 VnB piff Differential Ringback voltage 100 100 3 10 threshold 26 Intel Itanium Processor 9300 Series 9500 Series Datasheet Electrical Specifications tel Table 2 3 Intel QuickPath nterconnect Intel Scalable Memory Interconnect Reference Clock Specifications Sheet 2 of 2 TREFCLK JITTER RMS PLL output is generated by convolving ONEPLL the measured reference clock phase Symbol Parameter Min Nom Max Units Notes Tstable Allowed time before ringback 500 ps 3 10 Accumulated rms jitter over UI of a 0 5 ps 2 given PLL model output in response to the jittery reference clock input The jitter with a given PLL transfer function Here n 12 Note 1 Measurement taken from single ended waveform 2 given PLL parameters are Underdamping z 0 8 and natural frequency fn 7 86E6 Hz wn 2 fn minUI 12 for Intel QuickPath Interconnect 4 8 Gt s channel 3 Measurement taken from differential waveform 4 Measured from 150 mV to 150 mV on the differential waveform derived from SYSCLK minus SYSCLK N The signal must be monotonic through the measurement region for rise and fall time The 30
245. rs to 0 SAL entrypoints platform ow eas Processor Abstraction Layer PAL VN gt A ae 2 Processor hardware mag 7 x Performance critical hard ware events e g inter rupts LU Non performance criti gt cal hardware events e g reset machine Y Y Y checks Platform 18 Intel Itanium Processor 9300 Series and 9500 Series Datasheet Introduction 1 3 Processor Feature Comparison intel The Intel Itanium Processor 9300 Series processor and Intel Itanium Processor 9500 Series processor features are compared below in Table 1 1 Table 1 1 Intel Itanium Processor 9300 Series and Intel I tanium Processor 9500 Series Feature Comparison Description Intel tanium Processor 9300 Intel I tanium Processor 9500 Series Series Socket LG1248 LG1248 Transistors 2 billion 3 1 billion Cores Threads up to 4 8 up to 8 16 Clock speeds up to 1 86 GHz via Intel Turbo Boost with sustained boost 1 73 2 53 GHz Integrated on die cache L1 111 16K L1D 16K 12 121 512K L2D 256K inclusive L3 6 MB per core FLC FLI 16K FLD 16K 512K MLD 256K LLC shared up to 32 MB up to 24 MB Ararat Voltage Regulator Module Support Ararat 1 Ararat Supported speeds DDR3 800 DDR3 800 and DDR3 1067 Intel QPI links 6 6 4 full 2 half width at up to 4 8 GT s 4
246. rtain temperature is reached on the processor core These sensors are used to control various thermal states Figure 5 1 shows an approximate relationship between temperature time and the THERMALERT TCONTROL PROCHOT THERMWARN and THERMTRIP points Figure 5 1 is not intended to show an exact relationship in time or temperature as a processor s thermal state advances from one state to the next state Cooling solution performance degradation and processor workload variations will affect the processor thermal state Intel Itanium Processor 9300 Series and 9500 Series Datasheet 133 intel Figure 5 1 5 1 1 5 1 1 1 Table 5 1 134 Intel Itanium Processor 9300 Series and Intel I tanium Processor 9500 Series Thermal States THERMTRIP THERMWARN PROCHOT Max Operating Temperature RELATIVE TEMP THERMALERT Time Diagram not to scale Digital Thermometer The Intel Itanium9 Processor 9300 Series and Intel Itanium Processor 9500 Series uses a thermal sensing device called Digital Thermometer DT to read the values from the thermal sensors available on the processor die The DT also compares these values to a thermal trip point that is hard wired Calibration information is used to translate the DT output to processor temperature in degrees Celsius relative to the PROCHOT setpoint DT readout is available in CSR or via SMBus When it is below the PROCHOT setpoint th
247. rthbound clock input signal of channel A and positive bit of the differential pair 160 Intel Itanium Processor 9300 Series 9500 Series Datasheet Signal Definitions intel Table 7 1 Signal Definitions for the Intel Itanium Processor 9300 Series and Intel Itanium 9500 Series Sheet 3 of 8 Name Type Description FBD1NBICLK C D P N 0 These differential pair clock signals generated from the branch one channel and D of FB DIMMs are input to the processor FB DIMM 1 NB 1 CLK C D P N Interface Branch North Input Clock Channel Differential Name Number Bound Pair Polarity Positive Negative Example FBD1NBICLKDPO represent FB DIMM branch 1 northbound clock input signal of channel D and positive bit of the differential pair FBDOSBOCLK A B P N O o These differential pair output clock signals generated from the processor are inputs to the branch zero channel A and B of FB DIMMs SB DIMM Interface Branch South Output Clock Channel Differential Name Number Bound Pair Polarity Positive Negative Example FBDOSBICLKAPO represent FB DIMM branch 0 southbound clock output signal of channel A and positive bit of the differential pair FBDISBOCLK C D P N O These differential pair output clock signals generated from the processor inputs to the branch one channel C and D of FB D
248. rviceability RAS coverage on the Intel Itanium 9500 Processor Series These signals are not used by Intel Itanium 9300 Processor Series FBD1SBO C D P N 9 0 These differential pair output data signals generated from the processor to the branch one channel C and D of FB DIMMs FB 1 NB o C D P N 9 0 DI MM Interface Branch North Output Channel Differential Lane Name Number Bound Pair Number Polarity Positive Negative Example FBD1SBOCP 0 represents FB DIMM branch 1 southbound data output lane 0 signal of channel and positive bit of the differential pair FBD1SBO C D P N 10 These signals are spare lanes and intended for Reliability Availability and Serviceability RAS coverage on the Intel Itanium 9500 Processor Series These signals are not used by Intel Itanium 9300 Processor Series FLASHROM CFG 2 0 These input signals to the processor that would initialize map the Flash ROM upon reset After reset is deasserted this input would be ignored by the processor logic These pins are sampled during all resets except warm logic reset FLASHROM CLK 0 The Flash ROM clock FLASHROM_CS 3 0 _N Flash ROM chip selects Up to four separate flash ROM parts may be used FLASHROM_DATI Serial Data 1 from ROM s to processor FLASHROM_DATO Serial Data Output from processor to ROM s FLASHROM_WP_N 0 Flash ROM write protect 162 Intel Itanium
249. s 32 Execution Layer supports 32 application binaries Bi endian support Processor abstraction layer eliminates processor dependencies 11 12 ntel The Intel Itanium Processor 9300 Series delivers new levels of flexibility reliability performance and cost effective scalability for your most data intensive business and technical applications It provides 24 megabytes L3 cache accessed at core speed Hyper Threading Technology for increased performance Intel virtualization Technology for improved virtualization Intel Cache Safe Technology for increased availability The Intel Itanium Processor 9300 Series consists of up to 4 core processors and a system interface unit Each processor core provides a 6 wide 8 stage deep execution pipeline The resources consist of six integer units six multimedia units two load and two store units three branch units and two floating point units each capable of extended double and single precision arithmetic The hardware employs dynamic prefetch branch prediction a register scoreboard and non blocking caches to optimize for compile time non determinism Each core provides duplication of all architectural state to support hardware multithreading thus enabling greater throughput Three levels of on die cache minimize overall memory latency It interfaces with the Ararat 1 Voltage Regulator Module which used exclusively with the Intel Itanium Processor 9300
250. sed of the PIROM and the OEM Scratch PAD PIR_AO PIR_A1 Processor Information ROM Address 0 1 The 11 pins are used as the PIROM memory address selection signals This bus applies to the EEPROM which is composed of the PIROM and the OEM Scratch PAD SM_WP WP Write Protect can be used to write protect the Scratch EEPROM The Scratch EEPROM is write protected when this input is pulled high to VCC33_SM PRBMODE_REQ_N Input from Extended Debug Port XDP to make a probe mode request PRBMODE_RDY_N Output to XDP to acknowledge probe mode request PROCHOT_N The assertion of PROCHOT_N processor hot indicates that the processor die temperature has reached its thermal limit PROCTYPE PROCTYPE output informs the platform the processor type PROCTYPE is tied to VSS internally to indicate the Intel Itanium 9300 Processor Series and VCC33 SM internally to indicate the Intel Itanium 9500 Processor Series This pin does not require a platform pull up or pull down PWRGOOD The processor requires this signal to be a clean indication that all the processor clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD
251. signal the Ararat Voltage Regulator is permitted to shutdown but should latch VR_THERMTRIP_N low which be reset by a power cycle or de assertion of VROUTPUT ENABLEO VR THERMTRIP N trip point is determined by the Ararat Voltage Regulator Module Design and it should be set such that VR THERMTRIP N is asserted prior to permanent damage to the Ararat voltage regulator See Ararat 170W Voltage Regulator Module Design Guide and or Ararat Voltage Regulator Module Design Guide for platform requirements on driving this signal VROUTPUT ENABLEO 1 0 This signal is an input to the processor package bottom and drives into the Ararat voltage regulator from the top of the package When this signal is asserted the VIDs become active and the voltage regulator s startup sequence begins When this signal is pulled down the Ararat Voltage regulator should shut down VCCCORE VCCUNCORE and VCCCACHE Intel Itanium 9300 Processor Series only See Ararat 170W Voltage Regulator Module Design Guide and or Ararat 11 Voltage Regulator Module Design Guide for platform requirements on driving this signal VRPWRGD Ararat VR_READY Ararat 1 1 0 This signal is open drain collector driven by Ararat Voltage Regulator into a pad at the top of the processor package and out through a pin at the bottom of the processor package When pulled up active high state it indicates that the supply voltages to VCCCORE VCCUNCORE and VCCCACHE are s
252. signal is open drain collector driven by Ararat Voltage Regulator into pad at the top of the processor package and out through a pin at the bottom of the processor package When asserted it indicates that the temperature on the Ararat solution is about to exceed the VR_THERMTRIP_N limit When enabled the processor this signal causes the processor to enter a throttling state to reduce the power consumption level The Platform could monitor this pin to implement thermal management See Ararat 170W Voltage Regulator Module Design Guide and or Ararat 11 Voltage Regulator Module Design Guide for platform requirements on driving this signal Intel Itanium Processor 9300 Series and 9500 Series Datasheet 165 intel Signal Definitions Table 7 1 Signal Definitions for the Intel Itanium Processor 9300 Series and Intel Itanium 9500 Series Sheet 8 of 8 Name Type Description VR 1 0 This signal is open drain collector driven by Ararat Voltage Regulator into a pad at the top of the processor package and out through a pin at the bottom of the processor package When asserted it indicates that the temperature on the Ararat solution has exceeded a critical threshold and it is required to shut down the Ararat solution immediately The Processor cores do not monitor or respond to this signal The Platform should immediately de assert VROUTPUT_ENABLEO If the Platform does not respond to this
253. sor has two Home Agents Bbox The Bbox interfaces between the memory controller and the Intel QuickPath Interconnect and supports a directory cache Each memory controller supports two Intel Scalable Memory Interconnects Intel SMI in lockstep The Intel SMI are the interconnects to Scalable Memory Buffer The Intel Itanium Processor 9500 Series processor supports six Intel QuickPath Interconnects at the socket four full width and two half width The Caching Agent Home Agent and Intel QuickPath Interconnects are connected via a 10 port Crossbar Router each port supporting the Intel QuickPath Interconnect protocol Figure 1 2 shows the processor block diagram 16 Intel Itanium Processor 9300 Series and 9500 Series Datasheet Introduction intel Figure 1 2 Intel Itanium Processor 9500 Series Processor Block Diagram Poulson MC Poulson MC Poulson MC Poulson MC Poulson MC Poulson MC Poulson MC Poulson MC Cored 1 2 4 5 7 Ring Interface Ring Interface Ring Interface Ring Interface Ring Interface Ring Interface Ring Interface Ring Interface Ring Ring Ring Ring k Ring F TRing TRing T Ring Stop Stop Stop Stop 1 4 Stop Stop Chox1 2 Cbox3 Cbox4 Cbox5 Sbox0 f Sbox1 4MB
254. ss Power Other W33 VSS Power Other M32 VSS Power Other W38 vss Power Other M37 VSS Power Other w8 VSS Power Other M7 VSS Power Other 1 VSS Power Other N10 vss Power Other 11 VSS Power Other N30 VSS Power Other Y29 VSS Power Other N35 vss Power Other Y31 VSS Power Other N5 VSS Power Other Y36 VSS Power Other P28 vss Power Other 5 vss Power Other P3 VSS Power Other Y6 vss Power Other P33 vss Power Other 11 XDPOCP_STRB_IN_N 5 55 Power Other AH11 XDPOCP_STRB_OUT_N P38 vss Power Other AH8 XDPOCPD 0 _N 1 0 P4 VSS Power Other AG8 XDPOCPD 1 _N 1 0 P8 vss Power Other AJ9 XDPOCPD 2 N 1 0 R1 vss Power Other 9 XDPOCPD 3 _N 1 0 R11 VSS Power Other AH9 XDPOCPD 4 N 1 0 R31 VSS Power Other AG10 XDPOCPD 5 _N 1 0 R36 vss Power Other AJ10 XDPOCPD 6 N 1 0 R4 VSS Power Other AK10 XDPOCPD 7 N 1 0 88 Intel Itanium Processor 9300 Series and 9500 Series Datasheet Pin Listing Table 3 1 Pin List by Pin Name Sheet 33 of 33 Moo Pin Name m Direction 11 1 0 3 1 2 Pin Listing by Pin Number Table 3 2 Pin List by Pin Number Sheet 1 of 32 Direction Al RSVD A2 RSVD A3 VSS Power Other A4 RSVD A5 THERMALERT_N 0 A6 THER
255. ssor 9300 Series 41 FMB 155W 185W Current Specifications for the Intel Itanium Processor 9300 42 FMB Voltage Specifications for the Intel Itanium Processor 9500 Series 43 FMB 170W and 130W Current Specifications for the Intel Itanium Processor 9500 Series rec e EXER E RR EE E kx 44 VCCUNCORE Static and Transient Tolerance for Intel itanium Processor 9300 Series 45 VCCCORE Static and Transient Tolerance for Intel Itanium Processor 9300 Series isses erret ge Du RR RR 46 VCCCACHE Static and Transient Tolerance for Intel Itanium Processor 9300 48 VCCUNCORE Static and Transient Tolerance for the Intel Itanium Processor 9500 Series rer ree re rn o i i e FR E ce 49 VCCCORE Static and Transient Tolerance for the Intel Itanium Processor 9500 Series ce oer a E Rh HL a E PRG 51 Overshoot and Undershoot Specifications For Differential Intel QuickPath Interconnect and Intel SMI and Single Ended Signals for the Intel Itanium Processor 9300 Series 52 Overshoot and Undershoot Specifications For Differential Intel QuickPath Interconnect and Intel SMI and Single Ended Signals for the Intel Itanium Processor 9500 Series 53 Voltage Regulator Signal Group DC 53 Voltage Regulator Control Gro
256. ssor 9500 Series The Intel Itanium Processor 9500 Series implements a Serial VID BUS that is used to transfer power management information between the microprocessor and the five output voltages Voltage levels are compliant to the VR12 0 1V TTL signaling requirements and are shown in Table 2 32 SVID Group DC Specifications for the Intel Itanium Processor 9500 Series Symbol Parameter Min Max Unit Notes ViL Input Low Voltage 0 VCCIO 0 5 0 2 V Input High Voltage VCCIO 0 5 0 2 V Output High Voltage VCCI O 0 2 VCCIO V VoL Output Low Voltage 0 0 25 1 Output Low Current 16 23 mA 1 liLeak Input Leakage Current 200 200 2 oLeak Output Leakage Current 200 200 Notes 1 With 50W termination to VCCIO at the far end 2 With input leakage current measured at the pin with OV and with 1 075V supplied to the pin System designers are advised to check the tolerance of their voltage regulator solutions to ensure Vpin of 1 1 V Table 2 33 SMBus and Serial Presence Detect SPD Bus Signal Group DC Specifications Symbol Parameter Min Max Unit Notes Input Low Voltage 0 VCCIO 0 67 0 2 V 1 Input High Voltage VCCIO 0 67 0 2 VCCIO V 1 VoL Output Low Voltage 0 0 25 V 1 lo Output Low Current 16 23 mA 1 2 Input Leakage Current 1000 200 1 lio Output Leakage Current 1000 200
257. t Sheet 2 of 2 Hex VD VIP VID VID VID vip v Hex VID6 VIDS VID2 VID1 VID V 25 0 1 0 0 1 0 1 1 1500 53 1 0 0 0 0 1 1 0 5750 26 0 1 0 0 1 1 0 1 1375 54 1 0 1 0 1 0 0 0 5625 27 0 1 0 0 1 1 1 1 1250 55 1 0 1 0 1 0 1 0 5500 28 0 1 0 1 0 0 0 1 1125 56 1 0 1 0 1 1 0 0 5375 29 0 1 0 1 0 0 1 1 1000 57 1 0 1 0 1 1 1 0 5250 2 0 1 0 1 0 1 0 1 0875 58 1 0 1 1 0 0 0 0 5125 28 0 1 0 1 0 1 1 1 0750 59 1 0 1 1 0 0 1 0 5000 2 0 1 0 1 1 0 0 1 0625 7 1 1 1 1 1 1 1 2 0 1 0 1 1 0 1 1 0500 2 7 2 Core and Uncore Voltage dentification for the I ntel Itanium Processor 9500 Series Table 2 37 Intel Itanium Processor 9500 Series VCCCORE VID VCCCORE VCCUNCORE and VID VCCUNCORE Voltage Identification Definition for Ararat Sheet 1 of 4 VID VIDE VID VID VID VID VID Hex VID VID VID VID VID vip 00 0 0 or 27 0 1 1 1 1 0 440 01 0 0 11 0 250 28 0 1 0 1 o 0 445 02 0 0 0 1 0 0 255 29 1 1 1 0 450 03 0 0 1 1 0 260 2 1 0 1 0 1 0 0 455 04 0 0 1 0 0 265 28 1 0 1 0 1 1 0 460 05 0 0 1 1 0 270 2c 1 0 1 1 o 0 465 06 0 0 1 1 0275 2 1 1 1 1 0 470 07 0 0
258. t and Tx output TXEQ BOOST Voltage ratio between the cursor and the 0 25 dB 3 post cursor when transmitting successive ones Transmitter data or clock common mode level 23 27 VTx CM RIPPLE PIN Transmitter data or clock common mode 0 14 8 9 ripple Intel Itanium Processor 9300 Series and 9500 Series Datasheet 29 intel Electrical Specifications Table 2 5 Intel Itanium Processor 9300 Series Transmitter Parameter Values for Intel QuickPath nterconnect and Intel SMI Channels 4 8 GT s Sheet 2 of 2 Symbol Parameter Min Nom Max Units Notes TXpurv cvciE PIN Transmitter clock or data duty cycle at the 0 076 0 076 UI UI 6 pin Transmit duty cycle at the pin defined as UI to UI jitter as specified by the Intel Electrical Specification Rev 1 0 TTx DATA CLK SKEW PIN Delay of any data lane relative to clock lane 0 5 0 5 Ul 1 2 as measured at Tx output TXace jiT N_UI 1E 9 Peak to peak accumulated jitter out of any TX 0 0 18 Ul 5 data or clock over 0 lt n lt UI where N 12 measured with 1E 9 probability TXji7U Ul 1E 9PIN Transmitter clock or data UI UI jitter at 1E 9 0 0 17 Ul 5 probability RLtx DIFF Transmitter Differential return loss from 10 dB 7 50MHz to 2GHz RLtx DIFF Transmitter Differential return loss from 6 dB 7 2GHz to 4GHz Notes T Parameter value at full Intel Refclk 2 Stagger offset OxF 3
259. t FLASHROM_CFG 2 0 FLASHROM_DATI GTL open Drain Output FLASHROM_CS 3 0 _N FLASHROM_CLK FLASHROM_DATO FLASHROM_WP_N ERROR Bus Single ended GTL Open Drain Output ERROR 0 _N ERROR 1 _N GTL Input MEM_THROTTLE_L Power up Single ended GTL Input PWRGOOD RESET_N Thermal Single ended GTL Open Drain Output PROCHOT_N THERMTRIP_N THERMALERT_N GTL Input VID Port4 Intel Itanium Processor 9300 Seri FORCEPR N ies Single ended CMOS Output VID VCCCORE 6 0 VID VCCCACHE 5 0 VID VCCUNCORE 6 0 SVID Port4 Intel Itanium Processor 9500 Series Single ended GTL Output SVID CLK GTL I O SVD_DATIO GTL Input SVID_ALERT_N Voltage Regulator 4 Single ended Open Collector Drain Output VR_THERMTRIP_N VRPWRGD Intel Itanium Processor 9300 Series processor VR_READY Intel Itanium Processor 9500 Series processor VR_FAN_N Voltage Regulat or Control 4 Single ended CMOS Input GTL Input Open Collector Drain Output VROUTPUT ENABLEO VR THERMALERT N VR THERMTRIP VRPWRGD VR FAN Intel Itanium Processor 9300 Series 9500 Series Datasheet 25 intel Table 2 2 2 3 Signal Groups Sheet 3 of 3 Electrical Specifications Signal Group Buffer Type Signals 1 2 3 Debug GTLI O XDPOCPD N 7 0 TRIGGER N 1 0 XDPOCPFRAME N single ended eer input XDPOCP_STRB_IN_N PRBMODE_REQST_N GTL Output XDPOCP_STRB_OUT_N PRBMODE_RDY_
260. table within their voltage specification and indicates that the Ararat VR start up sequence is completed This signal will transition to a logic low for power off sequencing and or any Ararat VR fault condition See Ararat 170W Voltage Regulator Module Design Guide and or Ararat 11 Voltage Regulator Module Design Guide for platform requirements on pull up resistors and filtering VSS VSS is the ground plane for the processor XDPOCPD 7 0 1 0 Bidirectional XDP data XDPOCP_STRB_IN_N Input clock center aligned with XDPOCP_FRAME_N and XDPOCPD 7 0 XDPOCP_STRB_OUT_N Output clock edge aligned with XDPOCP_FRAME_N and XDPOCPD 7 0 XDPOCP_FRAME_N 1 0 Bidirectional signal indicating valid data on XDPOCPD 7 0 166 Intel Itanium Processor 9300 Series and 9500 Series Datasheet 1 9 MEO UJ Ner 9 1 2 Architectural OVGrVIgW terere rae e rmi xD 15 1 2 1 Intel Itanium Processor 9300 Series Overview 15 1 2 2 Intel Itanium Processor 9500 Series Overview 16 1 3 Processor Feature Comparison 1 19 1 4 Processor Abstraction 1 2 1 1 R EDE S 20
261. tain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 go to http www intel com design literature htm96 20 12 is a two wire communication bus protocol developed by Phillips SMBus is a subset of the I C bus protocol developed by Intel Implementation of the 12 bus protocol or the SMBus bus protocol may require licenses from various entities including Phillips Electronics N V and North American Phillips Corporation Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain computer system software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Intel Itanium and the Intel logo are trademarks of Intel Corporation in the S and or other countries Other names and brands may be claimed as the property of others Copyright 2012 Intel Corporation Rights Reserved 2 Intel Itanium Processor 9300 Series and 9500 Series Datasheet Contents 1 9 1 1 9 1 2 Architectural
262. ted 2 Applicable over recommended operating range T 40 C to 88 C Vcc 1 7 V to 3 6 V 56 Intel Itanium Processor 9300 Series and 9500 Series Datasheet m Electrical Specifications tel 2 6 7 Motherboard Socket Specification for VR Sense Point Figure 2 16 VR Sense Point Representation Note 2 7 1 5 DC DC to 1 MHz 1 AC 1 MHz to 20 MHz specified at MB socket Core and Uncore Voltage Identification The VID VCCCORE 6 0 and VID VCCUNCORE 6 0 lands supply the encoding that determine the voltage to be supplied by the VCCCORE and VCCUNCORE voltage regulators The VID VCCCORE and VID VCCUNCORE specifications for the Intel Itanium9 Processor 9300 Series and 9500 Series are defined the Ararat 170 Watt Voltage Regulator Module Design Guide and Ararat 11 Voltage Regulator Module Design Guide respectively The voltage set by the VID VCCCORE and VID VCCUNCORE lands are the maximum VCCCORE and VCCUNCORE voltage allowed by the processor Individual processor VID VCCCORE and VID VCCUNCORE values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID VCCCORE and VID VCCUNCORE settings Furthermore any Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series can drive different VID VCCCORE and VID VCCUNCORE settings during normal operation Table 2 36 and Table 2 37 specify the voltage levels corresp
263. tel QuickPath Interconnect Version Number as four 8 bit ASCII characters Example The Intel Itanium Processor 9300 Series processor supports Intel QuickPath Interconnect Version Number 1 0 Therefore offset 34h 37h has an ASCII value 01 0 in reverse order 34h 30h 35h 2E 36h 31h 37h 30h Memory Type Support Offset 38h signifies the type of memory support for this processor and platform A 011 signifies FBD1 support only for Intel Itanium Processor 9300 Series 02h is Intel 7500 Scalable Memory Buffer support only and 04h represents support for Intel 7510 7520 Scalable Memory Buffers Intel Itanium Processor 9500 Series only A 06h represents support for both Intel 7500 Scalable Memory Buffer and Intel 7510 7520 Scalable Memory Buffers Intel Itanium Processor 9300 Series and 9500 Series Datasheet 153 m e n te System Management Bus I nterface 6 4 4 5 6 4 4 6 6 4 4 7 6 4 4 8 6 4 5 6 4 5 1 6 4 5 2 6 4 5 3 154 Maximum Memory Transfer Rate Offset 39h 3Bh provides maximum memory transfer rate on the Intel Scalable Memory Interconnect Intel SMI Systems may need to read this offset to decide if processors and Intel 75xx Scalable Memory Buffers support the same Intel SMI transfer rate Six 4 bit BCD digits are used to provide the maximum transfer rate in MT s Example A speed of 4 8 GT s is shown as 004800h Minimum Memory Transfer Rate Offset 3Ch
264. terrupt is sent out when entering throttling CMCI entry and also when the processor is exiting the SIM phase CMCI exit to inform the system of the performance status Note that the temperature could cool below the throttle trip point but exiting SIM is still subject to the minimum time of 1 second Information on the CMCI interrupt can be found in the Intel Itanium Processor Family Interrupt Architecture Guide There is a mechanism to bypass the PROCHOT setpoint When it is bypassed both the THERMALERT_N and THERMTRIP_N signals as well as THERMWARN threshold still operate as normal There is also a mode that emulates PROCHOT setpoint for testing The processor can be placed in this mode by a Processor Abstraction Layer PAL call Another PAL call will return the processor to normal operation These special modes are intended for debug purposes only Thermal Alert THERMALERT_N is a programmable thermal alert signal which is part of the Intel Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500 Series thermal management system THERMALERT N is asserted when the measured temperature from the processor s digital thermometer DT is equal to or exceeds QR CSR IPF THERM CONFIG thermalert assert hot thresh below PROCHOT THERMALERT will deassert after the DT readout is below PROCHOT by the sum of the values in QR CSR IPF THERM CONFIG thermalert assert hot thresh and Intel Itanium Processor 9300 Series 95
265. the processor and Ararat are properly installed into the socket CPU_PRES 1 4 _N 1 0 CPU Present Pads These pads at the bottom of the package are part of a daisy chain that indicates to the platform that the processor and Ararat are properly installed into the socket Motherboard routing guidelines for these pins are documented in the Intel Itanium 9300 Series Processor and Intel Itanium Processor 9500 Series Platform Design Guide CSI 5 0 R P N CLK The receive clock signals are inputs to the Intel Itanium Processor 9300 Series and Intel Itanium 9500 Series and are required to be the same frequency at both ends but may differ by a fixed phase An Intel QuickPath Interconnect local receiver port receives a forwarded clock from the transmitter side of the remote port and vice versa to maintain timing reference at either end of the link Intel QuickPath 5 0 R P N CLKO Interconnect Interface Name Port Receiver Differential Pair ClockO Number Polarity Positive Negative Example CSI4RPCLK represents port 5 clock receive signal and positive bit of the differential pair CSI 5 O T P N CLK These transmit clock signals are driven by the processor and are required to be the same frequency at both ends but may differ by a fixed phase An Intel QuickPath Interconnect local port transmit side sends a forwarded clock to the receive side of the remote port and vice versa
266. to 55 0 3 1 55 V 1 2 VccA Processor Analog Supply Voltage with respect to 55 0 3 1 89 V 1 2 Vccio Processor 1 Supply Voltage with respect to 55 0 3 1 55 V 1 2 Vcc33 5 Processor 3 3 Supply Voltage with respect to 55 0 3 3 465 V 1 2 Notes 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Overshoot and undershoot voltage guidelines for input output 1 0 signals are outlined in Section 2 6 3 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 2 5 2 Table 2 14 Intel Itanium Processor 9500 Series Processor Absolute Maximum Ratings Intel Itanium Processor 9500 Series Absolute Maximum Ratings Symbol Parameter Min Max Units Notes VccconE Processor core supply voltage with respect to 55 0 3 1 42 V 1 2 VCcCUNCORE Processor uncore supply voltage with respect to 55 0 3 1 42 V 1 2 VccA Processor Analog Supply Voltage with respect to Vss 0 3 1 89 V 1 2 Vccio Processor 1 Supply Voltage with respect to Vss 0 3 1 55 V 1 2 Vcc33 SM Processor 3 3 V Supply Voltage with respect to VSS 0 3 3 465 V 1 2 Notes 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Overshoot and undershoot voltage guidelines for input output and 1 signals are outlined in Section 2 6 4
267. um Processor 9500 Series Transmitter and Receiver Parameter Values for Intel Channel at 4 8 5 34 2 10 Intel Itanium Processor 9500 Series Transmitter and Receiver Parameter Values for Intel at 6 4 5 35 2 11 Intel Itanium Processor 9500 Series Transmitter and Receiver Parameter Values for Intel SMI at 6 4 GT s and lower 37 2 12 PLL Specification for TX and 11111 senseri nns 38 2 13 Intel Itanium Processor 9300 Series Absolute Maximum 06 39 2 14 Intel Itanium Processor 9500 Series Processor Absolute Maximum Ratings 39 2 15 FMB Voltage Specifications for the Intel Itanium Processor 9300 Series 40 2 16 130W Current Specifications for the Intel Itanium Processor 9300 Series 41 2 17 FMB 155W 185W Current Specifications for the Intel tanium Processor 9300 Series eene 42 2 18 FMB Voltage Specifications for the Intel Itanium Processor 9500 Series 43 2 19 FMB 170W 130W Current Specifications for the Intel Itanium Processor 9500 Series nns 44 2 20 VCCUNCORE Static and Transient Tolerance for Intel Itanium Processor 9300 Series 0 1 45 2 21 VCCCORE Static and Transient Tolerance for Intel Itanium Processor 93
268. up DC Specification ene 54 and System Management Group DC Specifications 54 Error FLASHROM Power Up Setup and Thermal Group DC Specifications 54 VID VCCCORE 6 0 VID VCCUNCORE 6 0 and VID VCCCACHE 5 0 DC Specifications for the Intel Itanium Processor 9300 55 SVID Group DC Specifications for the Intel Itanium Processor 9500 Series 55 Intel Itanium Processor 9300 Series and 9500 Series Datasheet 3 6 3 7 3 8 3 9 4 1 4 2 4 3 4 4 4 5 5 1 5 2 5 3 5 4 5 5 6 2 6 3 6 4 6 5 7 1 SMBus Serial Presence Detect SPD Bus Signal Group DC Specifications 55 Debug Signal Group DC 5 56 Signal Group DC Specifications 56 Intel Itanium Processor 9300 Series VCCCORE VID VCCCORE and VCCUNCORE and VID VCCUNCORE Voltage Identification Definition for Ararat 58 Intel Itanium Processor 9500 Series VCCCORE VID VCCCORE and VCCUNCORE and VID VCCUNCORE Voltage Identification Definition for Ararat rennen nnn 59 Cache VID VCCCACHE Voltage Identification Definition for 63 Power up Voltage Sequence Timing Requirements 68 RESET N and
269. us Signal Group DC Specifications 55 Intel Itanium Processor 9300 Series and 9500 Series Datasheet 171 172 ntel 3 6 3 7 3 8 3 9 3 10 4 1 4 2 4 3 4 4 4 5 5 1 y N ooooouvug UD WwW Debug Signal Group DC 5 56 Signal Group DC 5 56 Intel Itanium Processor 9300 Series VCCCORE VID_VCCCORE and VCCUNCORE and VID VCCUNCORE Voltage Identification Definition for Ararat 58 Intel Itanium Processor 9500 Series VCCCORE VID VCCCORE and VCCUNCORE and VID VCCUNCORE Voltage Identification Definition for Ararat 11 59 Cache VID VCCCACHE Voltage Identification Definition for 63 Power up Voltage Sequence Timing Requirements sss 68 RESET and SKTID TIMING Hmmm mene 70 Pini List by Pin Name oor eren pest her Pu PER Dor 73 bist DY 89 Top Side J1 Connector Two Dimensional Table Intel Itanium Processor 9300 Series 105 Top Side J1 Connector Two Dimensional Table Intel Itanium Processor 9500 0 106 Top Side J2 Connector Two Dimensional Table Intel Itanium Processor 9300 Series 108 Top Side J2 Connector Two Dimensional Table I
270. vancements LGA1248 Socket Level compatible with the Intel Itanium Processor 9300 Series Bi endian support Processor abstraction layer eliminates processor dependencies 13 14 ntel The Intel Itanium Processor 9500 Series delivers increased levels of flexibility reliability performance and cost effective scalability for your most data intensive business and technical applications The Intel Itanium Processor 9500 Series processor provides up to 32 megabytes LLC cache Hyper Threading Technology for increased performance Intel Virtualization Technology for improved virtualization Intel Cache Safe Technology for increased availability Intel Turbo Boost Technology featuring sustained boost The Intel Itanium Processor 9500 Series employs advanced power monitoring and control to deliver a higher processor frequency at all times for maximum performance on all workloads The result is a higher thermal envelope utilization for more overall performance The Intel Itanium Processor 9500 Series offers large cache arrays covered by ECC including the large LLC utilizing double correct triple detect DECTED and protecting the MLI MLD with in line single correct double detect SECDED In addition the processor provides extensive parity protection and parity interleaving on nearly all RFs end to end parity protection with recovery support on all critical internal buses and data paths including the r

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