Kingston Technology ValueRAM KVR16LR11S4/4I memory module
Contents
1. 180 30 00mm double sided component kingston com kingston TECHINOLOGY Value SPECIFICATIONS CL IDD 11 cycles Row Cycle Time tRCmin 48 125ns min Refresh to Active Refresh 160ns min Command Time tRFCmin Row Active Time tRASmin 35ns min Maximum Operating Power 1 35V 5 478 W 1 50V 3 947 W 94V 0 0 C to 85 C 55 C to 100 C UL Rating Operating Temperature Storage Temperature Power will vary depending on the SDRAM and Register PLL used Continued gt gt Document No VALUERAM1346 001 A00 05 02 13 Page 1 continued ValueRAM MODULE DIMENSIONS units millimeters D 9 o co sa ve oo N ee E e eS DI Th 30 00 ii ria 29 60x4 24 80x2 21 80x2 mK 18 80x2 15 80x2 J a R 0 65 MAX TYPICAL 11 00x2 L 8 00x2 3 80 Loa i O 0 000 x 150 4 0 10 sila CHAMFER 0 50 X 45 DEG 4 PLAC OOO D LO LO m C M kingston com Document No VALUERAM1346 001 A00 Page 22. Memory Module Specifications KVR16LR115S4 41 4GB 1Rx4 512M x 72 Bit PC3L 12800 CL11 Registered w Parity 240 Pin DIMM DESCRIPTION This document describes ValueRAM s 512M x 72 bit 4GB DDR3L 1600 CL11 SDRAM Synchronous DRAM low voltage registered w parity 1Rx4 ECC Intel Compatibility Tested memory module based on eighteen 512M x 4 bit FBGA compo nents The SPD is programmed to JEDEC standard latency DDR3 1600 timing of 11 11 11 at 1 35V and 1 5V This 240 pin DIMM uses gold contact fingers The electrical and mechanical specifications are as follows FEATURES e JEDEC standard 1 35V 1 28V 1 45V and 1 5V 1 425V 1 575V Power Supply VDDQ 1 35V 1 28V 1 45V and 1 5V 1 425V 1 575V e 800MHz fCK for 1600Mb sec pin e 8 independent internal bank e Programmable CAS Latency 11 10 9 8 7 6 e Programmable Additive Latency 0 CL 2 or CL 1 clock e 8 bit pre fetch e Burst Length 8 Interleave without any limit sequential with starting address 000 only 4 with tCCD 4 which does not allow seamless read or write either on the fly using A12 or MRS e Bi directional Differential Data Strobe e Internal self calibration Internal self calibration through ZQ pin RZQ 240 ohm 1 On Die Termination using ODT pin e On DIMM thermal sensor Grade B Average Refresh Period 7 8us at lower than TCASE 85 3 9us at 85 C lt TCASE lt 95 C e Asynchronous Reset e PCB Height 1
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