Home

Hynix 8GB DDR3 PC3-12800

Contents

1. B lt lt 0 ER lt FE oz 3 4 8 36 2 O lt s 883052 lt E sb RIESE L Es A g 8 25 LSR 2 E d iR ETT i v l L 1 1 ZW bas S W os vss w ids Mien A B4 g E g GR g E g DO 3 0 D9 DQ 3 0 D8 DQ 3 0 D45 DQ 3 0 D44 5 S o 128 vis 5 wie w 8 5 281261888 12812 618882 re W Das W Sas VS WY as VSS pp s Dos S DOS 5 DOS S DOs S 1080 z DM z DM z W DO 3 0 D7 DQ 3 0 D6 DQ 3 0 D47 EN D46 5 g 8 w 18182 is 5 wesw 5 DEIER 12181 618852 E gt La La La La e e DOs W Dos VSS WY Os VSS pa a EN a ES g GR E 3 W 0 3 0 D5 DQ 3 0 D4 3 DQ 3 0 D49 DQ 3 0 Dag 3 3
2. Front lt 133 35 gt Detail B 128 95 lt gt 2 10 0 15 p A Detail A d DDP g DDP g DDP DDP g DDP g C 4x3 00 0 10 g A eg SIE g g g s g g Bd D x Ki Ki mim P DDP be DDP bd gt 8 DDP DDP KIN ZO qd n 120 oi 2X3 00x0 I ma y p 71 00 Back g DDP g DDP DDP g DDP g DDP C v v v v B g g g g g S S S S S 5 DDP w DDP DDP DDP 240 121 a f Lermmmrmmmmmmmmmmimmm 2x R0 75 Max Side Detail of Contacts A Detail of Contacts B Detail of Contacts C Detail of Contacts D 3 46mm max 1 204 0 15 010 05 m S T N 4 13 60 N 2 S N 3 01 8 N n E n 9 Y d A mre 4 gt 1 00 e is A 5 00 27 010mm gt max Note 1 0 13tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 0 Jul 2012 75 SK nix 2Gx72 HMT42GR7CMRAC Heat Spreader 22 00 30 20 46 46 lt gt e 80 54 gt e 119 64 gt Back k 57 2 gt 2
3. Sig gis vB TESS HISAR 86 593 HSS 98 593 Biggs 86 593 DQ53 DOS 33 Dos 33 Das 33 DOS 33 D053 Wy DOS DOS DQS DQS DM3 TDQS12 W TDQS TDQS TDQS TDOS 100512 WU TDQS U10 H U19 Ts U28 ane U37 DQ 31 24 WW DQ 7 0 DQ 7 0 DQ 7 0 DO 7 0 po r re re Vtt N Plan to use SPD with Integrated TS of Class B and VDDSPD VDDSPD SAO SA0 might be changed on customer s requests For more EVENT EVENT SPD with SA1 SA1 details of SPD and Thermal sensor please contact local SK hynix sales representative ert SCL Wang SA2 L SA2 y j SDA SDA VSS VSS Vppspp T Serial PD VDD T U1 U37 Notes EF 1 DQ to 1 O wiring may be changed within a byte Vor 2 See wiring diagrams for resistor values VREFCA a U1 U37 3 ZQ pins of each SDRAM are connected to individual RZQ resistors 240 1 ohms VREFDQ U1 U37 Vss U1 U37 Rev 1 0 Jul 2012 18 SK yi 8GB 1Gx72 Module 4Rank of x8 page3 S0 W 51 OA 12 32 S3 R BAIN 0 E A N 0 RAS S T CAS E WE P CKEO P CKEl n Dm AA ODT1 AA CK0 s CK0 sa SE CKI 5 PAR_IN W
4. ZOE gE E woo go N GER m RIS 0 9 N Yo 2 m 9230 PHH e IL EIER NEIER w u Ex w 1013318 s0 8533 61281886 593 HIS gis S b 33 HSS PESOS DOS MN DOS 33 DOS SS DOS z g os SS DQ50 M DOS DOS DOS Ds DMO TDQS9 WH TDQS TDQS TDQS Tos 15058 M TDOS U2 1005 U11 TDQS U20 ETS U29 DQ 7 0 MW DQ 7 0 DQ 7 0 DQ 7 0 DQ 7 0 PU i ida D e e U asss wjgrsegggo oggs spco eggs tgBco DQS1 Wy DOS lt lt DOS 3 DOS zz mam lt 2 DOS1 W DOS DOS DOS Ls DM1 TDOS10 WW TDOS U3 m TDQS10 W TDOS E DQ 15 8 2A DQ 7 0 de 4 La IgE asss ejersuygos eggsse gpco Iognggoentzs D0S2 W DOS 23 DOS 23 DOS 23 005 23 D052 W DOS DOS DOS Ls DM2 TDQS11 A TDOS TDQS TDQS Tos ME U4 TE U13 T0 U22 Kees U31 DQ 32 16 WW DQ 7 0 DQ 7 0 00 7 0 00 7 0 2 DE 3 L B e La YY u k SS Yuk oo 55 SS ggk SIE BR OS 031812968533 0121812316 533 626363533 DQS3 44 DOS 23 Dos 2 DOS EA 2 nam we TbQs ac Ge m CRW U5 ns U14 D U23 zs U32 DQ 31 24 WW DQ 7 0 E 3 E IN i e WEBER REST PEREUUEESS URRESRYSSE Beers sss DQS8 Wy DOS S DOS 33 DOS z pos amp 3 Be 7005 1005 mos eu U6 ET u15 a U24 m U33 CB 7 0 AA DQ 7 0 Lt DQ 7 0 00 7 0 DQ 7 0 oo e in de Vtt
5. DQS4 DOS Dos DQ54 w DOS DQS E VSS DM DM D0135 321 4W DQ 3 0 D4 DQ 3 0 D22 121818 5 wie sis 8 L T DOS16 Ww DOS oos DQS16 A DOS E Dos E VSS DM DM 9 DQ 63 60 A DQ 3 0 D16 5 DQ 3 0 D34 oe 3 1818 amp 916882 1 1818 ss 8 DQS7 ww DOS s DOS7 W DOS i DQS x VSS DM DM DQI 59 56 A DQ 3 0 D7 DQ 3 0 D25 10 1818 8 s 8 i Be 8 AM e Vtt WwW Vppspp SPD VDD T DO D35 Vu i D0 D35 VREFCA A DO D35 VREFDQ D0 D35 Vss s s D0 D35 Note 1 DQ to I O wiring may be changed within a nibble 2 See wiring diagrams for all resistors values 3 ZQ pins of each SDRAM are connected to individual RZQ resistors 240 1 ohms Rev 1 0 Jul 2012 m a im n 0108 8 52 oo da aU O JO 5 22 o gig 5 SNE 3 JEg 1 1 1 1 1 ji DQ513 w DOS DOS DQS13 W DQS n DQs VSS DM 2 DM E DQ 39 36 dd DO 3 0 D13 DQ 3 0 D31 3 12818 swe 5
6. m o 02 d i TE J 4 i 9 30 Add E g lt gt 1 1 Mi bas Ze AM 3 E g DO 3 0 D27 DQ 3 0 D26 5 o 128 s 5 2812 w 8 5 gt re 0 bas Das w Dos 3 DOS 3 W re D25 Doan D24 5 w 18182 s is 5 wesw 5 gt La La 0 bas Sie S 3 53 g W DQ 3 0 D23 DQ 3 0 D22 3 w 18182 x 5 w 1818 a w 5 E Weg 0 bas Sie ME 3 BM El W DQ 3 0 D21 DQ 3 0 D20 8 w 2188 168 3 2 w 1818 w 5 E all 0 bos as ia g ERE g W pq 3 0 D19 DQ 3 0 Pis w 2184 168 5 wesw 5 La lt lt o Dt TTE ATH TEES db 5 8 515858565 mo gt J j j J uj u P qp I I zQ ZQ DOS Dos S E DQ 3 0 D63 Beech D62 w 1818 8 w 3 w 1818 18 188 8 gt zQ ZQ DOS DOS S 5 S DQ 3 0 D65 DQ 3 0 D64 E 8 w ie w 5 1218 12 618882 E La e zQ ZQ ESS Dos 5 z DQ 3 0 D67 DQ 3 0 D66 z 3 2 21815188582 121818 61888 gt Le Le zQ ZQ DOS DOS a DQ 3 0 D69 3 DQ 3 0 D68 ES 3 8 121818318852 6121818 s EET EE e ZQ zQ DOS DOS Gg g om D Geen 2A DQ 3 0 D E w 1818 w 5 121818 s EET e J
7. pagel lt lt lt 22 95 o lt lt SO 52 lt n mn nibo pl 22 RESETE SE np SREE el k RSS E lee 220 lt 8 2 ale ze DEIR Z YRZ Z za KIN Z 9 DQS8 DoS Dos4 DUS Dos wDas a Dos Dos wDos E DM8 DOS17 WH TDQS TDQS o DM4 DQS13 W TDQS o TDOS o DOS WATDOS D8 1005 D17 Z DS vDo D4 1005 D13 Ei CB 0 M DQ 7 0 B DQ 7 0 DQ 39 32 MDQ 7 0 m DQ 7 0 20 g e 20 e opgeet MEOE Meee MULITITIE i a i I DQS3 WwiDas DQS DOSS wrjDas Dos use w ae 2 o SEN E Des 2 o S 2 GS MTS D3 E TE D12 2 DOH vT D5 Toe D14 E DQ 31 24 MM DO 7 0 DQ 7 0 DQ 47 40 M DQ 7 0
8. Speed Bin DDR3 1600K CL nRCD NRP 11 11 11 SE Note Parameter Symbol min max 13 75 e ea faa 13 125 10 d ACT to internal read or tco 13 75 _ write delay time 13 125 510 PRE command period tap a 10 ns 13 125 ACT to ACT or REF hc 48 75 _ command period 48 125 5 10 CWL 25 CK AVG 2 5 3 3 ns 1 2 3 8 CL 6 CWL 6 xv Reserved ns 1 2 3 4 8 CWL 7 amp xave Reserved ns 4 CWL 5 awe Reserved ns 4 CWL 6 favo ae ns 1 2 3 4 8 CL 7 Optional gt 10 CWL 7 tek avo Reserved ns 1 2 3 4 8 CWL 8 awe Reserved ns 4 CWL 5 awe Reserved ns 4 CL 8 CWL 6 IcK AVG 1 875 lt 2 5 ns 1 2 3 8 CWL 7 CK AVG Reserved ns 1 2 3 4 8 CWL 8 tekave Reserved ns 1 2 3 4 CWL 5 6 KK AVG Reserved ns 4 CL 9 CWL 7 tek avo ns 1 2 3 4 8 Optional 10 CWL 8 aver Reserved ns 1 2 3 4 CWL 5 6 KK AVG Reserved ns 4 CL 10 CWL 7 CK AVG 1 5 lt 1 875 ns 1 2 3 8 CWL 8 ck avG Reserved ns 1 2 3 4 cL 11 ENL 7 5 67 kene Reserved ns 4 CWL 8 Ck AvG 1 25 1 5 ns 1 2 3 Supported CL Settings 5 6 7 8 9 10 11 Mk Supported CWL Settings 5 6 7 8 Mk Rev 1 0 Jul 2012 49 SK nix DDR3 1866 Speed Bins For specific Notes See Speed Bin Table Notes on page 51 Speed Bin DDR3 1866M CL nRCD NRP 13 13 13 Unit Note Pa
9. 1 DQ to 1 O wiring may be changed within a nibble 2 Unless otherwise noted resistor values are 15 Ohms 5 3 See the wiring diagrams for all resistors associated with the command address and control bus might be changed on customer s requests For more details of SPD and Thermal sensor please contact local SK hynix sales representative 4 ZQ resistors are 240 Ohms 1 For all other resistor values refer to the appropriate wiring diagram Rev 1 0 Jul 2012 22 3 8 55555 ee a n METETE a Y TETTERE 8 HIHTHE i d KIT N il ET i db l L l l W Das VS W os VS Wis VSS pa SCH Mm DQS s DQS s DQS g DQS g Ea 3 0 D29 s D28 See D61 Bere D60 EI o 92 616882 28121688 lo 1818 ss YET 12814 618852 La Las La W Das VSS Wi Das VSS W Das VSS pp sa w Dos S8 Dos s Dos S8 DQS s TH z DM z DM Z z DO 3 0 D31 DQ 3 0 D30 DQ 3 0 D59 EG D58 w 18182 168 3 w 1818 a w 5 w 1818 vs 8ET io 1818 618852 gt Das VSS W Das VSS W Das VSS pa a 7 5 z 2 W DQ 3 0 D33 DQ 3 0 D32 A DQ 3 0 D57 ES DQ 3 0 250 z w 18182 168 8 wiki sw 8 wikis 8 12181 8 5 1 1 Le Das VSS W Das VSS W Das VSS pa SC ES W DQ 3 0 D35 amp DQ 3 0 D34 DQ 3 0 D55 ERG D54 EI
10. Rev 1 0 Jul 2012 17 SK nix 8GB 1Gx72 Module 4Rank of x8 page2 geseit E PE E egyvyoge 9 9 x 9 9 x 0 0 x ER 9222 Ir 3808 n 0 n 8 Ei i a BREE s PEE l La Aa u u u ig igs S PESOS Big igs 8168533 Sig igs S ZR SS Sig igs ve L 52 2 DQS4 Wy DUS x 3 DOS z z DQS x E DQS x z D054 WY DOS DOS DOS DOS DM4 TDQS13 WY TDOS TDQS TDS TDQS 100513 2 U7 E U16 U25 mr U34 DQ 39 32 WW DQ 7 0 DQ 7 0 DQ 7 0 DQ 7 0 15 1s i4 it a DSS ER FRETTI egigs spoc PkkESR 555 jggss5 bnpco DQS5 44 DOS 3 Dos lt 2 DQS 9 2 DOS 23 DOSS 4 DOS DOS Dos Dos DM5 TDQS14 WW TDOS TDQS TDQS TDQS 10051 RS U8 E U17 TE U26 TE U35 DQ 47 40 WW DQ 7 0 i5 5 e La x LES LE v Y Y LES Sig igs S SESS 8 gigs 8168533 Sig igs 5B SESS Bgg ss 858 Dies 4 DOS SS DoS 23 DOS 23 DOS 23 D056 W DOS DOS DOS DOS DM6 TDOS15 WY TDOS 1005 TDQS TDQS 100515 W TDQ5 U9 m U18 m U27 mr U36 DQ 55 48 WW DQ 7 0 DQ 7 0 DQ 7 0 DQ 7 0
11. w 2188 168 8 181188582 21813188582 6121818 s EET x x e Le e V SPD DDSPD X VDDSPD VDDSPD SAO SAO VDD DO D71 x EVENT EVENT SPD with SA1 SA1 Vrr Integrated VS T SCL SCL SA2 SA2 VREFDQ DO D71 SDA SDA VSS VSS Vss e DO D71 Plan to use SPD with Integrated TS of Class B and 26 SK yi 16GB 2Gx72 Module 4Rank of x4 page5 50 H ARSOA gt CS1 SDRAMs D1 D3 D5 D7 D9 52 J I BRS2A gt CS1 SDRAMs D45 D47 D49 D51 D53 1 2 D19 D21 D23 D25 D27 1 2 D63 D65 D67 D69 D71 ARSOB CS1 SDRAMs D11 D13 D15 D17 BRS2B CS1 SDRAMs D37 D39 D41 D43 R D29 D31 D33 D35 R D55 D57 D59 D61 51 E L ARS1A gt CS0 SDRAMs DO D2 D4 D6 D8 53 My E BRS3A CS0 SDRAMs D44 D46 D48 D50 D52 G _ DI8 D20 D22 D24 D26 G D62 D64 D66 D68 D70 ARS1B CS0 SDRAMs D10 D12 D14 D16 BRS3B CS0 SDRAMs D36 D38 D40 D42 S D28 D30 D32 D34 S D54 D56 D58 D60 BA N 0 A L ARBA N 0 A gt BA N 0 SDRAMs D 9 0 D 27 18 _ BA N 0 yv L BRBA N 0 A BA N 0 SDRAMs D 53 44 D 71 62 T ARBAIN 0 B BAIN SDRAMa DIT TU D35281 T BRBAIN 018 RAIN 0 SDRAMs Die EE A N 0 WN ARA N 0 A gt A N 0 SDRAMs D 9 0 D 27 A N 0 A ram OJA gt A N 0 SDRAMs D 55 44 D 71 62 N 0 S ARAIN 0 B gt AIN 0 SDRAMs D 17 o EE L N 0 P RAIN 018 gt A Nl SDRAMs p GERS RA
12. 8 w 18182 x s 85 w 1818 a w 5 2181188582 12181 s EET e e La e e Das SW Bs VS WY Bas VSS pa SC SZ g E g EN g pas 3 W D013 0 D3 DQ 3 0 D2 DQ 3 0 D51 Zare D50 EI 8 8 8 8 w 2188 168 8 we w 5 w 1818 8 6121818 EET L 0 La La e e W Gs Tag ds WE VSS A SE q g Bu g eu E pos 3 W DQ 3 0 D1 3 DQ 3 0 DO 3 DQ 3 0 D53 GEN D32 z 8 8 8 8 io 218 168 52 w 1818 vis EET we s 8 121818 s 8 5 J x x Ly e e e e Rev 1 0 Jul 2012 23 S de 16GB 2Gx72 Module 4Rank of x4 page2 vss DQS17 DQS17 vss CB 7 4 vss DQs12 DQS12 VSS DQ 31 28 vss DQS11 DQS11 VSS DQ 23 20 vss DQS10 DQS10 vss DQ 15 12 vss DQS9 DQS9 DQ 7 4 vit
13. I KL La e e e pose ADOS 20 posis wloos 2 209 A DOS z DQS15 wWfjDos DM VSS DM DO 51 48W DO 3 0 D6 E Miss aad Do 13 01 D15 2 z 2 y 121818 x 5 6121818 BIg I e e L e e e DQS7 W DOS zQ DQS16 w Dos za D I pG 09516 wjoos S DM vss DM DQ 59 56F We DO 3 0 D7 E H Mies el DA 13 01 D16 2 2 y 121818 516888 62818 5168518 I e e La e e e Vtt 3 See the wiring diagrams for all resistors associated with the com mand address and control bus 4 ZQ resistors are 240 Rdr all other resistor values refer to the appro priate wiring diagram Rev 1 0 Jul 2012 Plan to use SPD with Integrated TS of Class B and might be changed on customer s requests For more details of SPD and Thermal sensor please contact local SK hynix sales representative Vppsep 34 SPD VDD EH D0 D17 Ver D0 D17 VREFCA A DO D17 VREFDQ D0 D17 Vss D0 D17 15 SK yi 4GB 512Mx72 Module 1Rank of x4 page2 50 W m St ege BA N 0 R AN E b G RAS N L WE N E CKE0 w ODTO CK0 CKO PAR IN GERR RESET RST RSOA gt CS0 SDRAMs D 3 0 D 12 8 D17 RSOB CS0 SDRAMs D 7 4 D 16 13 RSIA CSI SDRAMs D 12 9 D17 RS1B CSI SDRAMs D 16 13 Ed gt BAIN 0 SDRAMs D 3 0
14. Operating Burst Write Current CKE High External clock On tCK CL see Table 1 BL 88 AL 0 CS High between WR Command Address Bank Address Inputs partially toggling according to Table 8 Data IO seamless read data burst with different data between one burst and the next one according to Table 8 DM stable at 0 Bank Activity all banks open WR commands cycling through banks 0 0 1 1 2 2 see Table 8 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at HIGH Pattern Details see Table 8 pp5B Burst Refresh Current CKE High External clock On tCK CL nRFC see Table 1 BL 82 AL 0 CS High between REF Command Address Bank Address Inputs partially toggling according to Table 9 Data IO MID LEVEL DM stable at 0 Bank Activity REF command every nREF see Table 9 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 9 bD6 Self Refresh Current Normal Temperature Range Tease 0 85 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Normal CKE Low External clock Off CK and CK LOW CL see Table 1 BL 89 AL 0 CS Command Address Bank Address Inputs Data 10 MID_LEVEL DM stable at 0 Bank Activity Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID_LEVEL IppeET Self Refresh Current Extended Temperature Range optional Tease
15. 0 175 Note2 V 1 2 7 VIL DQ AC175 AC input logic low Note2 Vref 0 175 E V 1 2 8 VIH DQ AC150 AC Input logic high Vref 0 150 Notez Vref 0 150 Notez Vref 0 150 Note2 V 1 2 7 VIL DQ AC150 AC input logic low Note Vref 0 150 Notez Vref 0 150 Note2 Vref 0 150 V 1 2 8 VIH CA AC135 AC input logic high S S Vref 0 135 Note2 mV 1 2 7 VIL CA AC135 AC input logic low N Notez Vref 0 135 mV 1 2 8 VRefDQ DC EE 0 49 VDD 0 51 VDD 0 49 VDD 0 51 VDD 0 49 VDD 0 51 VDD V 3 4 Notes 1 Vref VrefDQ DC 2 Refer to Overshoot and Undershoot Specifications on page 43 3 The ac peak noise on Vger may not allow Vrer to deviate from Vgerpo pc by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV 5 VIH dc is used as a simplified symbol for VIH DQ DC100 6 VIL dc is used as a simplified symbol for VIL DQ DC100 7 VIH ac is used as simplified symbol for VIH DQ AC175 VIH DQ AC150 and VIH DQ AC135 VIH DQ AC175 value is used when Vref 0 175V is referenced VIH DQ AC150 value is used when Vref 0 150V is referenced and VIH DQ AC135 value is used when Vref 0 135V is referenced 8 VIL ac is used as simplified symbol for VIL DQ AC175 VIL DQ AC150 and VIL DQ AC135 VIL DQ AC175 value is used when Vref 0 175V is referenced VIL DQ AC150 value is used when Vref 0 150V is referenced and VIL DQ AC135 value is used
16. 12818 x m 8 agg DOS pos DQS5 W DOS a Dos vsS DM 9 DM e DQ43 40 MW DO 3 0 D5 DQ 3 0 D23 E 8 3 1218 12 916882 I 1818 amp 51888 DOS15 WwW DOS Dos DQS15 W Dos DOS VSS DM DM 2 DQ 55 52 MM DQ 3 0 DIS DQ 3 0 D33 3 3 1218 12 91685 218 5 DQS6 A DQS DOS DQs6 wy DOS DOS VSS DM e DM 9 DQ 51 48 MM DQ 3 0 D6 DQ 3 0 D24 3 3 12812 sa 8 Be Bk KEET Vtt VW VDDSPD VDDSPD SA0 SAO EVENT EVENT SPD with SA1 SA1 SCL SCL biam SA2 SA2 SDA SDA VSS VSS Plan to use SPD with Integrated TS of Class B and might be changed on customer s requests For more details of SPD and Thermal sensor please contact local SK hynix sales representative 21 SK yi 8GB 1Gx72 Module 2Rank of x4 page3 S0 L RS0A gt CS0 SDRAMs D 3 0 D 12 8 D17 sa 1 2 RS0B CS0 SDRAMs D 7 4 D 16 13 S1 g RSIA gt CST SDRAMs D 21 18 D 3026 D35 RS1B gt CST SDRAMs D 25 22 D 34 31 BA N 0 A E L RBA N O A BA N 0 SDRAMs D 3 0 D 12 8 D 21 17 D 30 20 D35 G Lu BAINO SDRAMs D 7 4 DI16 19 25 22 bt 34 31 AIN 0 RA N Q A A N 0 SE 21 17 Diode D35 RUE A N 0 B A N 0 SDRAMs D 7 4 D 16 1 JEE RS s F MN RAS SDRAMs D 3 0 D 12 8 D 21 17 D 30 26 D35 E T RRASB RAS SDRAMs D 7 4 D 16 13 D 25 22 D 34 31 CAS WA RCASA gt CAS S
17. 17 20 repeat cycles 1 4 but BA 2 0 4 21 24 repeat cycles 1 4 but BA 2 0 5 25 28 repeat cycles 1 4 but BA 2 0 6 29 32 repeat cycles 1 4 but BA 2 0 7 2 33 nRFC 1 repeat Sub Loop 1 until nRFC 1 Truncate if necessary a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 0 Jul 2012 63 SK nix Table 10 IDD7 Measurement Loop Pattern ATTENTION Sub Loops 10 19 have inverse A 6 3 Pattern and Data Pattern than Sub Loops 0 9 o v 8 8 og S wit d Sg RMS 5 28 2 38 Elel3l8lE 8S 3 8588 5 ou 0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 1 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000 2 D 1 0 0 0 0 0 00 0 0 0 Sas repeat above D Command until nRRD 1 nRRD ACT 0 0 1 1 0 1 00 0 0 F 0 1 nRRD 1 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011 nRRD 2 D 1 0 0 0 0 1 00 0 0 F 0 ai repeat above D Command until 2 nRRD 1 2 2 nRRD repeat Sub Loop 0 but BA 2 0 2 3 3 nRRD repeat Sub Loop 1 but BA 2 0 3 4 4 nRRD D 1 0 0 0 0 3 00 0 0 F 0 Assert and repeat above D Command until nFAW 1 if necessary 5 nFAW repeat Sub Loop 0 but BA 2 0 4 6 nFAW nRRD repeat Sub Loop 1 but BA 2
18. 22 00 30 20 46 46 lt gt e 80 54 gt e 119 64 gt Back k 57 2 gt 2 7 gt LJ Cc C D Cc mu 15 36 22 00 Side 7 19mm max HH q M 27 010mm max Note 1 0 13 tolerance on all dimensions unless otherwise stated ninstall FDHS pl ntact sal ministrator 2 In order to uninsta S please contact sales administrato Units millimeters Rev 1 0 Jul 2012 72 SK nix 1Gx72 HMT31GR7CFR4C Front lt 133 35 N Detail B 128 95 i N gt 2 10 0 15 p lt a a Detail A d C 4X3 00 0 10 z a U S Z als E o m m L d E JJ N i S p co o N N uo DEE oi Toon y 71 00 gt gt Detail C 5 0 Detail D Back 240 4
19. 0 95 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Extended CKE Low External clock Off CK and CK LOW CL see Table 1 BL 82 AL 0 CS Command Address Bank Address Inputs Data IO MID LEVEL DM stable at 0 Bank Activity Extended Temperature Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID_LEVEL Rev 1 0 Jul 2012 57 SK yi Symbol Description Operating Bank Interleave Read Current CKE High External clock On tCK nRC nRAS nRCD NRRD nFAW CL see Table 1 BL 8 AL CL 1 CS High between ACT and RDA Command Address Bank Address Inputs partially toggling according to Table pp7 10 Data IO read data burst with different data between one burst and the next one according to Table 10 DM stable at 0 Bank Activity two times interleaved cycling through banks 0 1 7 with different address ing wee Table 10 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 10 a Burst Length BL8 fixed by MRS set MRO A 1 0 00B b Output Buffer Enable set MR1 A 12 0B set MR1 A 5 1 01B RTT Nom enable set MR1 A 9 6 2 0118 RTT_Wr enable set MR2 A 10 9 10B c Precharge Power Down Mode set MRO A12 0B for Slow Exit or MRO A12 1B for Fast Exit d Auto Self Refresh ASR set MR2 A6 OB to disable or 1B to enable feature e Self Refresh Tem
20. 1 10 11 The CL setting and CWL setting result in tCK AVG MIN and tCK AVG MAX requirements When mak ing a selection of tCK AVG both need to be fulfilled Requirements from CL setting as well as require ments from CWL setting tCK AVG MIN limits Since CAS Latency is not purely analog data and strobe output are synchro nized by the DLL all possible intermediate frequencies may not be guaranteed An application should use the next smaller J EDEC standard tCK AVG value 3 0 2 5 1 875 1 5 or 1 25 ns when calculat ing CL nCK tAA ns tCK AVG ns rounding up to the next Supported CL where tCK AVG 3 0 ns should only be used for CL 5 calculation tCK AVG MAX limits Calculate tCK AVG tAA MAX CL SELECTED and round the resulting tCK AVG down to the next valid speed bin i e 3 3ns or 2 5ns or 1 875 ns or 1 25 ns This result is tCK AVG MAX corresponding to CL SELECTED Reserved settings are not allowed User must program a different value Optional settings allow certain devices in the industry to support this setting however it is not a man datory feature Refer to DIMM data sheet and or the DIMM SPD information if and how this setting is supported Any DDR3 1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1333 speed bin also supports
21. RBA N 0 B gt BA N 0 SDRAMs D 7 4 BANS A gt A E SDRAMs EI L D RA N 0 B A N 0 SDRAMs D 7 4 D RRASA gt RAS SDRAMs D 3 0 D 12 RRASB RAS SDRAMs D 7 4 D 16 8 1 RCASA gt CAS SDRAMs D 0 D I2 8 D17 1 i i RWEA WE SDRAMs Dan DI12 8 pu RWEB gt WE SDRAMs DU AL D 16 1 RCKEOA CKE0 SDRAMs D 3 0 D RCKEOB CKE0 SDRAMs D 7 4 D RODTOA ODTO SDRAMs D 3 0 D 12 8 RODTOB ODTO SDRAMs D 7 4 D 16 1 PCKOA gt CK SDRAMs D 3 PCKOB CK SDRAMs D 7 0 DS 4 PCKOA CK SDRAMs D 3 0 D8 PCKOB CK SDRAMs D 7 4 Err_Out RST SDRAMs D 17 0 S 3 2 CKE1 ODT1 CK1 and CK1 are NC Unused register inputs ODT1 and CKE1 have a 3300 resistor to ground Rev 1 0 Jul 2012 16 SK nix 8GB 1Gx72 Module 4Rank of x8 pagel
22. RST Rev 1 0 Jul 2012 CS0 CS0 SDRAMs U 10 2 CS1 CS1 SDRAMs U 19 11 CS2 CS2 SDRAMs U 28 20 CS3 CS3 SDRAMs U 37 29 WBA N 0 BA N 0 SDRAMs U 6 2 U 15 11 U 24 20 U 33 29 EBA N 0 BA N 0 SDRAMs U 10 7 U 19 16 U 28 25 U 37 34 WA N 0 A N 0 SDRAMs U 6 2 U 15 11 U 24 20 U 33 29 EA N 0 A N 0 SDRAMs U 10 7 U 19 16 U 28 25 U 37 34 WRAS RAS SDRAMs U 6 2 U 15 11 U 24 20 U 33 29 ERAS gt RAS SDRAMs U 10 7 U 19 16 U 28 25 U 37 34 WCAS gt CAS SDRAMs U 6 2 U 15 11 U 24 20 U 33 29 ECAS CAS SDRAMs U 10 7 U 19 16 U 28 25 U 37 34 WWE gt WE SDRAMs U 6 2 U 15 11 U 24 20 U 33 29 EWE WE SDRAMs U 10 7 U 19 16 U 28 25 U 37 34 WCKEO CKE0 SDRAMs U 6 2 U 24 20 ECKE0 CKE0 SDRAMs U 10 7 U 28 25 WCKE1 CKE1 SDRAMs U 15 11 U 33 29 ECKE1 CKE1 SDRAMs U 19 16 U 37 34 WODT0 gt ODTO SDRAMs U 6 2 EODTO ODTO SDRAMs U 10 7 WODTO gt ODTI SDRAMs U 24 20 EODTO gt ODTI SDRAMs U 28 25 PCKO CK SDRAMs U 6 2 U 15 11 PCK1 CK SDRAMs U 10 7 U 28 25 PCK2 CK SDRAMs U 24 20 U 33 29 PCK3 CK SDRAMs U 19 16 U 37 34 PCKO gt CK SDRAMs U 6 2 U 15 11 PCK1 CK SDRAMs U 10 7 U 28 25 PCK2 CK SDRAMs U 24 20 U 33 29 PCK3 CK SDRAMs U 19 16 U 37 34 Err_Out RST SDRAMs U 37 2 19 SK nix 8GB 1G
23. 0 5 7 nFAW 2 nRRD repeat Sub Loop 0 but BA 2 0 6 8 nFAW 3 nRRD repeat Sub Loop 1 but BA 2 0 7 T 5 9 nFAW 4 nRRD D 1 0 0 0 0 7 00 0 0 F 0 X Assert and repeat above D Command until 2 nFAW 1 if necessary S E 2 nFAW 0 ACT 0 0 1 1 0 0 00 0 0 F 0 x a 10 2 nFAW 1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011 D 1 0 0 0 0 0 00 0 0 F 0 EE Repeat above D Command until 2 nFAW nRRD 1 2 nFAW nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 11 2 nFAW nRRD 1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000 D 1 0 0 0 0 1 00 0 0 0 0 ees Repeat above D Command until 2 nFAW 2 nRRD 1 12 2 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 2 13 2 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 3 D 1 0 0 0 0 3 00 0 0 0 0 lanai as Assert and repeat above D Command until 3 nFAW 1 if necessary 15 3 nFAW repeat Sub Loop 10 but BA 2 0 4 16 3 nFAW nRRD repeat Sub Loop 11 but BA 2 0 5 17 3 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 6 18 3 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 7 D 1 0 0 0 0 7 00 0 0 0 0 AMIA Assert and repeat above D Command until 4 nFAW 1 if necessary a DM must be driven LOW all the time DOS DOS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Rev 1 0 Jul 2012 64 SK nix IDD Specifications Tcase 0 to 95 C Module IDD values in the datasheet are only a calculation based on the co
24. 1 27 010mm max gt Note 1 0 13tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 0 Jul 2012 70 SK nix 1Gx72 HMT31GR7CFR8C Front lt 133 35 N Detail B 128 95 i N gt 2 10 0 15 p lt a a Detail A d C 4X3 00 0 10 z a U S Z als E o m m L d E JJ N i S p co o N N uo DEE oi Toon y 71 00 gt gt Detail C 5 0 Detail D Back 240 4 2 f Lemma 2x R0 75 Max Side Detail of Contacts A Detail of Contacts B Detail of Contacts C Detail of Contacts D 3 46mm max 1 20 0 15 80 0 05 2 50 gt 14 90 gt lt 0 4 13 60 e 5 3 0 1 Y n 8 8 8 2 2 3 n v n N N poo Wi lt 50 0 5 00 27 010mm max Note 1 0 13tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 0 Jul 2012 71 SK nix 1Gx72 HMT31GR7CFRSC Heat Spreader
25. 2 f Lemma 2x R0 75 Max Side Detail of Contacts A Detail of Contacts B Detail of Contacts C Detail of Contacts D 3 46mm max 1 20 0 15 80 0 05 2 50 gt lt 14 90 gt lt 0 4 13 60 e 5 3 0 1 Y n 8 8 8 2 2 3 n v n N N poo Wi lt 50 0 5 00 27 010mm max Note 1 0 13tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 0 Jul 2012 73 SK nix 1Gx72 HMT31GR7CFR4C Heat Spreader 22 00 30 20 46 46 lt gt e 80 54 gt e 119 64 gt Back k 57 2 gt 2 7 gt LJ Cc C D Cc mu 15 36 22 00 Side 7 19mm max Hi q M 27 010mm max Note 1 0 13 tolerance on all dimensions unless otherwise stated ninstall FDHS pl ntact sal ministrator ar 2 In order to uninsta S please contact sales administrato Units millimeters Rev 1 0 Jul 2012 74 SK nix 2Gx72 HMT42GR7CMR4C
26. 3 0 D8 DQ 3 0 D26 S 8 121818 ves 5 2818516855 DQsS3 W DOS DOS3 W DOS vss DM D0 27 24 WW DQ 3 0 D3 81251688 Dos 5 H DQ 3 0 D21 H 9 8 121818 s EET DQS2 A DOS DQS2 W DOS VSS DM DQ 19 16 DQ 3 0 D2 8151688 Dos e 2 DQ 3 0 D20 121818 91888 DQS1 A DQS DQS1 W DQS VSS DM DQ 11 8 DQ 3 0 D1 w 1818 w 5 DOS DQS DQ 3 0 D19 A N O BA N O A N O BA N O 612812 518688 DQS9 A DOS DQS9 W DOS VSS DM DQI 7 4 A DO 3 0 D9 a 1818 g s w 85 DOS DQS DQ 13 01 D27 A N O BALN O A N O BALN O 12818 91885 Vtt 34 20 SK nix 8GB 1Gx72 Module 2Rank of x4 page2 a o 9 2o m jo m 05 IT elt le d PP g E PSE J E SEI E p DOS14 7 DOS DOS14 W DOS VSS DM o DQ 47 44 A DQ 3 0 D14 25 u io 1818 s 8 m mn n gg Y E PE 1 1 1 1 1 DOS DOS S D32 1281 9158 5 A N O BA N O L
27. 44 1209 APCKOB CK SDRAMs D 17 10 1209 BPCKOB CK SDRAMs D 43 36 z 459 APCKIA gt CK SDRAMs D 27 18 459 BPCK1A gt CK SDRAMs D 71 62 m CET APCK1B gt CK SDRAMs D 35 28 a BPCK1B CK SDRAMs D 61 54 CKO APCKOA CK SDRAMs D 9 0 CKO BPCK0A CK SDRAMs D 53 44 APCKOB CK SDRAMs D 17 10 BPCKOB CK SDRAMs D 43 36 APCKIA CK SDRAMs D 27 18 BPCK1A CK SDRAMs D 71 62 APCK1B CK SDRAMs D 35 28 BPCK1B CK SDRAMs D 61 54 PAR IN w Err Out PAR IN W Err Out RESET RST RESET RST RST SDRAMs D 35 0 CK1 1202 5 1 CKO and CKO are differentially terminated with a single 120 Ohms 5 resistor 2 CK1 and CKI are differentially terminated with a single 120 Ohms 3 Unused register inputs ODT1 for Register A and ODTO for Register B are tied to ground 4 The module drawing on this page is not drawn to scale Rev 1 0 Jul 2012 E5 resistor but is not used 27 SK nix Absolute Maximum Ratings Absolute Maximum DC Ratings Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes VDD Voltage on VDD pin relative to Vss 0 4 V 1 80 V V 1 3 VDDQ Voltage on VDDQ pin relative to Vss 0 4 V 1 80 V V 1 3 Vin Vout Voltage on any pin relative to Vss 0 4 V 1 80 V V 1 Tstg Storage Temperature 55 to 100 K 1 2 Notes 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage t
28. 45 sd Standard Speed Bins DDR3 SDRAM Standard Speed Bins include tCK tRCD tRP tRAS and tRC for each corresponding bin DDR3 800 Speed Bins For specific Notes See Speed Bin Table Notes on page 51 Speed Bin DDR3 800E Unit Notes CL nRCD nRP 6 6 6 Parameter Symbol min max Internal read command to first data tna 15 20 ns ACT to internal read or write delay time trcp 15 ns PRE command period tp 15 ns ACT to ACT or REF command period ikc 52 5 ns ACT to PRE command period as 37 5 9 tREFI ns CL 6 CWL 5 ck AvG 25 3 3 ns 1 2 3 Supported CL Settings 6 nck Supported CWL Settings 5 lick Rev 1 0 Jul 2012 46 SK nix DDR3 1066 Speed Bins For specific Notes See Speed Bin Table Notes on page 51 Speed Bin DDR3 1066F it Not CL nRCD NRP 7 7 7 CN jet Parameter Symbol min max Internal read command to ACT to internal read or write delay time bc E ix PRE command period lap 13 125 ns ACT to ACT or REF L i command period Be 30 022 de ACT to PRE command Bi 37 5 9 tREFI ns period mu CWL 5 LK AVG 2 5 3 3 ns 1 2 3 6 N CWL 6 ECK AVG Reserved ns 1 2 3 4 mE CWL 5 IcK AVG Reserved ns 4 N CWL 6 tck avG 1 875 lt 2 5 ns 1 2 3 4 EE CWL 5 cK AVG Reserved ns 4 N CWL 6 tck avG 1 875 lt 2 5 ns 1 2 3 Supported CL Settings 6 7 8 Mk Supported CWL
29. 7 gt LJ Cc C D Cc mu 15 36 22 00 Side 7 19mm max Hi q M 27 010mm max Note 1 0 13 tolerance on all dimensions unless otherwise stated ninstall FDHS pl ntact sal ministrator ar 2 In order to uninsta S please contact sales administrato Units millimeters Rev 1 0 Jul 2012 76
30. BA 2 0 2 1 D v 2 18 11 repeat Sub Loop 0 but ODT 1 and BA 2 0 2 8 3 12 15 repeat Sub Loop 0 but ODT 1 and BA 2 0 3 4 16 19 repeat Sub Loop 0 but ODT 0 and BA 2 0 4 5 20 23 repeat Sub Loop 0 but ODT 0 and BA 2 0 5 6 24 17 repeat Sub Loop 0 but ODT 1 and BA 2 0 6 7 28 31 repeat Sub Loop 0 but ODT 1 and BA 2 0 7 a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 0 Jul 2012 61 SK nix Table 7 IDD4R and IDDQ4R Measurement Loop Pattern Y e E silagial clicla v8 i EE 161818585833 33 5 vun 3 03 lt lt Z lt lt 0 0 RD 0 1 0 1 0 0 00 O 0 0 0 00000000 I D 1 0 0 0 0 0 0 0 0 0 0 2 3 DD 1 1 1 1 0 0 0 1 0 0 01 01 4 RD 0 1 0 1 0 0 000 0 F 0 00110011 5 D 1 0 0 0 0 0 0 0 0 F 0 2 3 6 7 DD 11 1 11 1 0 0 0 0 0 F o 2 1 8 15 repeat Sub Loop 0 but BA 2 0 1 8 L 2 16 23 repeat Sub Loop 0 but BA 2 0 2 3 24 31 repeat Sub Loop 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 but BA 2 0 4 5 40 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DOS DOS are used according to RD Commands otherwise MI D LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signal
31. CMD signals in every half cycle DQS DQSL DQSU DQS DQSL have to reach VSEHmin VSELmax approximately the ac levels VIH ac VIL ac for DQ signals in every half cycle preceding and following a valid transition Note that the applicable ac levels for ADD CMD and DO s might be different per speed bin etc E g if VIH CA AC150 VIL CA AC150 is used for ADD CMD signals then these ac levels apply also for the single ended signals CK and CK Or E VDO e erm Ee Se 9er Ree RUE uS VSEHmina m9 mc K Dee roban dara a e Es VDD 2 0r NDDOI2 ee EE CK or DOS VSELmax Single ended reguirements for differential signals Note that while ADD CMD and DO signal reguirements are with respect to Vref the single ended compo nents of differential signals have a reguirement with respect to VDD 2 this is nominally the same the transition of single ended signals through the ac levels is used to measure setup time For single ended components of differential signals the reguirement to reach VSELmax VSEHmin has no bearing on timing but adds a restriction on the common mode characteristics of these signals Rev 1 0 Jul 2012 35 SK nix Single ended levels for CK DQS DQSL DQSU CK DQS DQSL or DQSU DDR3 800 1066 1333 1600 Symbol Parameter Unit Notes Min Max VSEH Single ended high level for strobes VDD 2 0 175 Note 3 V 1 2 Single ended high level for Ck C
32. DQ 7 0 20 Q 20 20 0 20 o u Ege eet T geet Tobe ve bs wHBEsubb T ll T DQS2 N DUS DQS DQS6 MN DOS DOS TIIA EXE g Ge t o pas F O F e DOSTI y TD0S D2 ES D11 Z basis W TDQS D6 ee D15 gt DQ 23 16 MM DO 7 0 m DQ 7 0 DQ55 48 M DQ 7 0 g DO 7 0 9 o 9 o Toke set MA TEE Togpsseppzl T Zp eeett I I e La DOSI WwiDas Dos DOS7 DOS Dos ee 3 Es s De 5 5 O 9 2 DQSIO MTS D1 Ta D10 Z Di was D7 E m D16 DQ 15 8 M DQ 7 0 m DQ 7 0 2 DQ 63 56 M DQ 7 0 B DQ 7 0 2 2 2 ARS S585851 CE R SIR est Teese yw ees t i t Doso was DOS vt DOS RA 5 DOS DMO DQS9 TDQS S TDQS Xs M lt POLL 5 DQ 7 0 a DQ 7 0 a 20 M 5 g MOETE MULT vi I VDDSPD VDDSPD SAO H SAO 1 EVENT EVENT SPD with SA1 n SA1 lt SAS SCL SCL Gees SA2 SA2 SDA SDA VSS VSS Plan to use SPD with Integrated TS of Class B and Note might be changed on customer s requests For more 1 DQ to 1 O wiring may be changed within a byte 2 Unless otherwise noted resistor values are 152 5 3 ZQ resistors are 2402 1 For all other resistor values refer to the appropriate wiring diagram 4 See the wiring diagrams for all resistors associated with the command address and control bus Rev 1 0 Jul 2012 details of SPD and Thermal sensor please contact local SK hynix sales re
33. Le Rev 1 0 Jul 2012 24 S CP ix K 16GB 2Gx72 Module 4Rank of x4 page3 vss DQS4 DQS4 DQ 35 32 vss DQS5 DQS5 DQ 43 40 vss DQS6 DQS6 DQ 51 48 vss DQS7 DQS7 vss DQ 59 56 Vtt n a 20 20 5555 Si a n eG RIESE ii a S a N Y m HHE E 28 BER E d n i ET i d l l l L W Das VS W os VS Ws VSS pa SCH AE 3 E g GR S 3 DO 3 0 D11 DQ 3 0 D10 DQ 3 0 D13 DQ 3 0 D42 5 o 82 281216838 wile w 8 amp 12814 618852 gt gt e W Das W Sas VSS WY Os VSS pp s Dos S DOS S DOS S DOs S 108 z DM z DM z DO 3 0 D13 DQ 3 0 D12 DQ 3 0 D41 Boel D40 5 g 8 w 18182 s
34. ZQ DQS8 W Dos E DQS4 m DOS ja DM8 DQS17 TDOS 9 J DM4 DQS13 A TDQS z L D0S17 W TDQS D8 Z DQ w rDos D4 EB CB 0 WHDO 7 0 DQ 39 32 W DQ 7 0 o 2 2 a 1818 18 si 83 ja 1818 18 s 5 LIIILLLLI Seana IN DQS3 WDQS ZQ DQS5 W DQS ZQ DQS3 wW DOS N DQS5 N DOS DM3 DQS12 TDQS 9 J DM5 DOS14 W TDOS o L DOSIZ wTDOS D3 DOSIA w TDQS D5 5 gt DQ 31 24 WHDO 7 0 amp DO 47 40 DQ 7 0 E 5 o o 18188 s1988 61281896882 LIIILILLLLI Lp p EES DQS2 w Dos ZQ DQS6 MM DOS ZQ DQS2 DOS eo DQS6 NN DOS s DM2 DQS11 A 4 TDQS 9 DM6 DQS15 A TDQS 9 SR DQSll W TDQS D2 Dosis w 1D05 D6 DQ 23 16 WHDO 7 0 g DQ 55 48 WHDO 7 0 El z 2 w 6 u ko 181818 916882 o 21818 168 8 LILIILLLLI ERE EE ERE ERR ET EE REIS DQS1 W Dos zQ DQS7 gt DOS S DQS1 WNMDQS Ze DQS7 N DOS DM1 DQS10 WY TDQS 9 DM7 DOS16 W TDOS 9 Vppsrp SPD DQS 10 W TDQS D1 g D0516 TOS D7 T Vo p tp po p8 B DQ 15 8 W4 DQ 7 0 DQ 63 56 WH DO 7 0 k 2 rg Vrr z z 6121818 sis EE 61281851688 Z vrerca 00 08 TII ITI LI TTT TT L I 1 VREFDO D0 D8 Doso w Dos m Kamm S Vss T L 00 08 DQSO NA DOS DM0 DQS9 W TDQS 9 L DOSI TDS DO DO 7 0 n DQ 7 0 a Note o 1 DQ to I O wiring may be changed within byte y 218 ja v 15 25 18 E u 6 o lt 2 ZQ resistors are 240 Q 1 For all other resistor value
35. differential signals as shown in table and figure below Differential Output Slew Rate Definition Measured Description Defined by From To Differential output slew rate for rising edge VoLaiff AC Vonaitt ac Vouaitt ac Voaitt Ac DeltaTRditf Differential output slew rate for falling edge Vouditt AC Voraitt ac Vonait AC Voraitt acy Delta TFdiff Notes 1 Output slew rate is verified by design and characterization and may not be subject to production test Differential Output Voltage i e DQS DQS M vOHdiff AC DN vOLdiff AC Differential Output Slew Rate Definition Differential Output slew Rate Definition Differential Output Slew Rate DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Parameter Symbol Min Max Min Max Min Max Min Max Min Max Differential Output Slew Rate SRQdiff 5 12 5 12 5 12 5 12 5 12 V ns Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Units Rev 1 0 Jul 2012 41 SK yi Reference Load for AC Timing and Output Slew Rate Figure below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements It is not intended as a precise
36. mA IDD2N 2204 2204 2564 mA IDD2NT 2564 2564 2924 mA IDD2PO 1092 1092 1092 mA IDD2P1 1308 1308 1308 mA IDD2Q 2204 2420 2420 mA IDD3N 2564 2708 2924 mA IDD3P 1308 1308 1452 MA IDD4R 3194 3464 4274 MA IDDAW 3194 3374 4094 mA IDD5B 3824 3914 4544 mA IDD6 1092 1092 1092 mA IDD6ET 1236 1236 1236 mA IDD7 4454 5084 5714 mA Rev 1 0 Jul 2012 67 SK nix Module Dimensions 256Mx72 HMT325R7CFR8C Front 133 35 gt 128 95 lt gt SPDUIS A p lt 2 10 0 15 pid 4X3 00 0 10 EZ 005010 SE D Y p 28 8 Detail A Q Detail B Detail C 2X3 00 0 101 v Back 240 121 O N OJ 2x R0 75 Max Side 3 43mm max Detail of Contacts A Detail of Contacts B Detail of Contacts C H te 1 20 0 15 EE 2 50 T gt lt n i fats 3 0 1 P 3 ri a e P 6 2 u Y d A CT A gt 1 00 e is lt 5o gt 1 27 010mm max gt te Note 1 0 13 tolerance on all dimensions unless otherwise stated Rev 1 0 Jul 2012 Units millimeters 68 SK nix 512Mx72 HMT351R7CFR8C Front e 133 35 128 95 lt gt jl 2
37. representation of any particular system environment or a depiction of the actual load presented by a production tester System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment Manufacturers correlate to their production test conditions generally one or more coaxial transmission lines terminated at the tester electronics VDDQ VTT VDDQ 2 Reference Load for AC Timing and Output Slew Rate Rev 1 0 Jul 2012 42 SK nix Overshoot and Undershoot Specifications Address and Control Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Address and Control Pins DDR3 DDR3 DDR3 DDR3 DDR3 Parameter Units 800 1066 1333 1600 1866 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 0 4 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 0 4 V Maximum overshoot area above VDD See Figure below 0 67 0 5 0 4 0 33 0 28 V ns Maximum undershoot area below VSS See Figure below 0 67 0 5 0 4 0 33 0 28 V ns A0 A15 BAO BA3 CS RAS CAS WE CKE ODT See figure below for each parameter definition Maximum Amplitude Overshoot Area VDD Volts WE ygs Undershoot Area Maximum Amplitude Time ns Address and Control Overshoot and Undershoot Definition Address and Control Overshoot and Under
38. when Vref 0 135V is referenced Rev 1 0 Jul 2012 31 SK yi Vref Tolerances The dc tolerance limits and ac noise limits for the reference voltages vrerca and Vrerpo are illustrated in figure below It shows a valid reference voltage Ves t as a function of time Vrer stands for Vrefca and Vrerpo likewise Vref DC is the linear average of Vrer t over a very long period of time e g 1 sec This average has to meet the min max requirements in the table Differential Input Slew Rate Definition on page 38 Further more Veer t may temporarily deviate from Vref pc by no more than 1 VDD voltage VDD Vner t Ver ac noise Ret VRef DC max VDD 2 VRef DC min VRef DC Illustration of Vref pc tolerance and Vref ac noise limits The voltage levels for setup and hold time measurements Viu ac Vinto Vit ac and Vii pc are depen dent on Vger Vner shall be understood as Vger pc as defined in figure above This clarifies that dc variations of Vref affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured System timing and voltage budgets need to account for Vger pc deviations from the optimum position within the data eye of the input signals This also clarifies that the DRAM setup hold specification and derating values need to include time and voltage associated with Vrerac noise Timing and voltage effe
39. 10 0 15 uu A Detail A O a E k c asa SS i E 9 8 m m i Detail B Detail C v Back U U L o 240 f 121 d M 2x R0 75 Max Side 3 43mm max Detail of Contacts A Detail of Contacts B Detail of Contacts C 1 204 0 15 moons 2 50 gt lt t a n S 8 8 3 0 1 8 3 A S S 3 P E N v R Mi 1 00 lt is E lt o gt 1 27 010mm max gt Note 1 0 13tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 0 Jul 2012 69 SK nix 512Mx72 HMT351R7CFR4C Front P 133 35 128 95 lt gt jl 2 10 0 15 uu A Detail A O a E k c asa SS i E 9 8 m m i Detail B Detail C v Back U U L o 240 f 121 d M 2x R0 75 Max Side 3 43mm max Detail of Contacts A Detail of Contacts B Detail of Contacts C 1 204 0 15 moons 2 50 gt lt t a n S 8 8 3 0 1 8 3 A S S 3 P E N v R Mi 1 00 lt is E lt o gt
40. 20 Ohm in MR2 TDQS Feature disabled in MR1 Attention The IDD and IDDQ Measurement Loop Patterns need to be executed at least one time before actual IDD or IDDO measurement is started Define D CS RAS CAS WE HIGH LOW LOW LOW Define D CS RAS CAS WE HIGH HIGH HIGH HIGH Rev 1 0 Jul 2012 53 Y Jop Y DDA optional o DDR3 SDRAM CKE bas Das Att 25 Ohm CS Ha DQ DM kl Vppo 2 RAS CAS WE TDOS TDOS A BA ODT ZQ Vss Figure 1 Measurement Setup and Test Load for IDD and IDDQ optional Measurements Note DIMM level Output test load condition may be different from above Application specific IDDQ memory channel Test Load Ul Channel IDDQ IDDQ lO Power Simulation Simulation Simulation a gt Correction Channel IO Power Number Figure 2 Correlation from simulated Channel IO Power to actual Channel 1O Power supported by IDDQ Measurement Rev 1 0 Jul 2012 54 SK nix Table 1 Timings used for I DD and I DDO Measurement Loop Patterns DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Symbol Unit 7 7 7 9 9 9 11 11 11 13 13 13 tex 1 875 1 5 1 25 1 25 ns CL 7 9 11 11 nCK PRCD 7 9 11 11 nCK Nac 27 33 39 39 nCK IRAS 20 24 28 28 nCK Map 7 9 11 11 nCK 1KB page size 20 20 24 24 nCK FAW KB page size 27 30 32 32 nCK 1KB page si
41. 6 223 Vss 44 Vss 164 CB6 NC 104 Vss 224 DQ54 45 CB2 NC 165 CB7 NC 105 DQ50 225 DQ55 46 CB3 NC 166 Vss 106 DQ51 226 Vss 47 Vss 167 NC TEST 107 Vss 227 DQ60 48 VTT NC 168 RESET 108 DQ56 228 DQ61 KEY KEY 109 DQ57 229 Vss 49 VTT NC 169 CKE1 NC 110 Vss 230 I 50 CKEO 170 VoD 111 DQS7 231 ai 51 VoD 171 A15 112 DQS7 232 Vss 52 BA2 172 A14 113 Vss 233 DQ62 53 Err_Out NC 173 VDD 114 DQ58 234 DQ63 54 VoD 174 A12 BC 115 DQ59 235 Vss 55 All 175 19 116 Vss 236 VDDSPD 56 A7 176 VoD 117 SAO 237 SA1 57 Von 177 A8 118 SCL 238 SDA 58 A5 178 A6 119 SA2 239 Vss 59 A4 179 VDD 120 VTT 240 VTT 60 VDD 180 A3 NC No Connect RFU Reserved Future Use Rev 1 0 Jul 2012 sd Registering Clock Driver Specifications Capacitance Values Symbol Parameter Conditions Min Typ Max Unit Input capacitance Data inputs 1 5 2 5 pF a Input capacitance CK CK FBIN FBIN 15 25 F up to DDR3 1600 i i p CIR GE RESET MIRROR V Vpp or GND Vpp 1 5v _ 3 oF Input amp Output Timing Requirements eege DDR3 1600 DDR3 1866 Symbol Parameter Conditions Unit Min Max Min Max Min Max fia Input clock fre Application fre 300 670 300 810 300 945 Mhz quency quency Input clock fre frEST EE Test frequency 70 300 70 300 70 300 Mhz Input valid before _ tsu Setup time CK CK 100 50 40 ps Input to remain N N ty Hold time valid after CK
42. 8GB 2Rx4 16GB 4Rx4 Refresh Method 8K 64ms 8K 64ms 8K 64ms 8K 64ms 8K 64ms 8K 64ms Row Address A0 A14 A0 A14 A0 A14 A0 A14 A0 A14 A0 A14 Column A0 A9 A0 A9 A0 A9 A11 A0 A9 A0 A9 A11 A0 A9 A11 Address Bank Address BA0 BA2 BA0 BA2 BA0 BA2 BA0 BA2 BA0 BA2 BA0 BA2 Page Size 1KB 1KB 1KB 1KB 1KB 1KB Rev 1 0 Jul 2012 Ds SK hynix Pin Descriptions Num ee Num Pin Name Description ber Pin Name Description ber CKO Clock Input positive line 1 ODT 1 0 On Die Termination Inputs 2 CKO Clock Input negative line 1 DQ 63 0 Data Input Output 64 CK1 Clock Input positive line 1 CB 7 0 Data check bits Input Output 8 CK1 Clock Input negative line 1 DQS 8 0 Data strobes 9 CKE 1 0 Clock Enables 2 DQS 8 0 Data strobes negative line 9 DM 8 0 Data Masks Data strobes RAS Row Address Strobe 1 DQS 17 9 TE 3 ee 9 TDQS 17 9 ermination data strobes PE DQS 17 9 Data strobes negative line CAS Column Address Strobe 1 9 TDQS 17 9 Termination data strobes Reserved for optional hardware WE Write Enable 1 EVENT 1 temperature sensing I Memory bus test tool Not Con SIS Chip Selects i TEST nected and Not Usable on DIMMs 1 A 9 0 A11 a N A 15 13 Address Inputs 14 RESET Register and SDRAM control pin 1 A10 AP Address Input Autoprecharge 1 Vpp Power Supply 22 A12 BC Address Input Burs
43. CK 175 125 75 ps Propagation MN tppu delay single bit CK CK to output 0 65 1 0 0 65 1 0 0 65 1 0 ns switching E dn eL Yn Yn to output 0 54 N 0 5 N 0 5 N prelaunch float tQSK1 min tQSK1 min tQSK1 min tan a ee Output driving to 0 5 I 0 5 I 0 5 I D prelaunch Yn Yn tQSK1 max tQSK1 max tQSK1 max Rev 1 0 Jul 2012 10 SK nix On DIMM Thermal Sensor The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor The integrated thermal sensor comply with J EDEC TSE2002av Serial Presence Detect with Temperature Sensor Connection of Thermal Sensor SAO SPD with sA1 SCL Integrated c SDA TS Temperature to Digital Conversion Performance Parameter Condition Min Typ Max Unit Active Range 75 C lt Ty lt 95 C Temperature Sensor Accuracy Grade B Monitor Range I 40 C lt Ty lt 125 C siad 8 20 C lt T4 lt 125 C 2 0 3 0 C Resolution 0 25 RS Rev 1 0 Jul 2012 11 S d Functional Block Diagram 2GB 256Mx72 Module 1Rank of x8 a gg lt o 28 29 HENE TEHE Bele lee 8 28 FAHER i l l i l l l l DQS8 wW DOS ZQ DQS4 V DDS
44. D10 161218 12 x 16 8 5 vss y IK vss peso oel pos ZO h poss pas 20 vs ier z vs om S DQ 3 0 dvl DO 3 0 DO E DQI7 4 WW DO 3 0 D9 S 121818 x x se 21812 91568 512 Vtt wv VDDSPD VDDSPD SAO DAD EVENT EVENT SPD with SAL SA1 sc scL Integrated s42 L 542 SDA SDA TS VSS VSS Note 1 DQ to 1 O wiring may be changed within a nibble 2 Unless otherwise noted resistor values are 15 5 vss vss vss W1 vss w m n 07 D Es HUL Die z Z ER s Ll 1 I II DQS4 N DOS ZO DQS13 N pas 2 past w DOS DQS13 W DQS i n vss DM a DOL35 324 WW DQ 3 0 D4 H Misa amd DQ 3 0 D13 z 2 121818 8 5 1 BB 5168512 I Le poss DOS 70 A posu w 09s N DQS5 d DOS M DOS w DOS cc vss DM g vss DM E DQ 43 4044M DO 3 0 D5 Z DOl47 44 W D0o 3 0 D14 z 2 wes 8 5 2818 5168518
45. D2NT 1214 1304 1304 mA IDD2P0 444 444 444 mA IDD2P1 498 498 534 mA IDD2Q 1178 1178 1214 mA IDD3N 1250 1304 1304 mA IDD3P 498 534 552 mA IDD4R 2384 2654 3014 mA IDD4W 2294 2474 2924 mA IDD5B 2834 2924 2924 MA IDD6 444 444 444 mA IDD6ET 480 480 480 MA IDD7 4004 4094 4364 mA 8GB 1G x 72 R DIMM HMT31GR7CFR8C Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit note IDDO 1664 1664 1979 mA IDD1 1754 1754 2069 mA IDD2N 1484 1484 1664 mA IDD2NT 1664 1664 1844 mA IDD2P0 660 660 660 mA IDD2P1 768 768 768 mA IDD2Q 1484 1592 1592 mA IDD3N 1664 1736 1844 mA IDD3P 768 768 840 mA IDD4R 1979 2114 2519 mA IDD4W 1979 2069 2429 mA IDD5B 2294 2339 2654 MA IDD6 660 660 660 MA IDD6ET 732 732 732 MA IDD7 2609 2924 3239 MA Rev 1 0 Jul 2012 66 sd 8GB 1G x 72 R DI MM HMT31GR7CFR4C Symbol DDR3 1333 DDR3 1600 DDR3 1866 Unit note IDDO 1844 2114 2114 mA IDD1 2024 2294 2384 mA IDD2N 1484 1664 1664 mA IDD2NT 1664 1844 1844 mA IDD2PO 660 660 660 mA IDD2P1 768 768 840 mA IDD2Q 1592 1592 1664 mA IDD3N 1736 1844 1844 mA IDD3P 768 840 879 MA IDD4R 2744 3194 3554 MA IDDAW 2654 3014 3464 mA IDD5B 3194 3464 3464 mA IDD6 660 660 660 mA IDD6ET 732 732 732 mA IDD7 4364 4634 4904 mA 16GB 2G x 72 R DI MM HMT42GR7CMR4C Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit note IDDO 2564 2564 3194 mA IDD1 2744 2744 3374
46. DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to Overshoot and Undershoot Specifications on page 43 Allowed time before ringback tDVAC for CK CK and DQS DQS DDR3 800 1066 1333 1600 DDR3 1866 tDVAC ps tDVAC ps tDVAC ps O VIH Ldiff ac tDVAC ps Slew Rate VIH Ldiff ac VIH Ldiff ac 270mV O VIH Ldiff ac V ns 350mV 300mV DQS DQS only 270mV Optional min max min max min max min max gt 4 0 75 175 214 134 4 0 57 170 214 134 3 0 50 167 191 112 2 0 38 119 146 67 1 8 34 102 131 52 1 6 29 81 113 33 1 4 22 54 88 9 1 2 note 19 56 note 1 0 note note 11 note lt 1 0 note note S note note note Rising input differential signal shall become equal to or greater than VIHdiff ac level and Falling input differential signal shall become equal to or less than VIL ac level Rev 1 0 Jul 2012 34 SK yi Single ended requirements for differential signals Each individual component of a differential signal CK DQS DQSL DQSU CK DQS DQSL of DQSU has also to comply with certain requirements for single ended signals CK and CK have to approximately reach VSEHmin VSELmax approximately equal to the ac levels VIH ac VIL ac for ADD
47. DRAMs D 3 0 D 12 8 D 21 17 D 30 26 D35 E E RCASB CAS SDRAMs DI AL D 16 13 D 25 22 D 34 31 WE JN R RWEA gt WE SDRAMs D 3 0 D 12 8 D 21 17 D 30 26 D35 RWEB WE SDRAMs D 7 4 D 16 13 D 25 22 D 34 31 CKE0 i RCKE0A gt CKE0 SDRAMs D 3 0 D 12 8 D17 P RCKEOB CKE0 SDRAMs D 7 4 D 16 13 DR I L F RCKEIA gt CKEI SDRAMs D 21 18 D 30 26 D35 L RCKE1B CKE1 SDRAMs D 25 22 D 34 31 ODTO I RODTOA_ gt ODTO SDRAMs D 3 0 D 12 8 D17 RODTOB ODTO SDRAMs D 7 4 D 16 13 O0DTI J RODTIA ODTI SDRAMs D 21 18 D 30 26 D35 RODTIA gt ODTI SDRAMs D 25 22 D 34 31 CKO PCKOA CK SDRAMs D 3 0 D 12 8 D17 PCKOB CK SDRAMs D 7 4 D 16 13 PCK1A gt CK SDRAMs D 21 18 D 30 26 D35 uc PCK1B CK SDRAMs D 25 22 E 31 CKO PCKOA CK SDRAMs D 3 0 D 12 8 D17 PCKOB gt CK SDRAMs D 7 4 D 16 13 PCKIA gt CK SDRAMs D 21 18 D 30 26 D35 CK1 PCK1B CK SDRAMs D 25 22 D 34 31 CK1 2 PAR IN Err Out RESET RST RST SDRAMs D 35 0 S 3 2 CK1 and CK1 are NC Rev 1 0 Jul 2012 S CP ix K 16GB 2Gx72 Module 4Rank of x4 pagel vss DQS8 DQS8 VSS CB 3 0 vss DQS3 DQS3 vss DQ 27 24 vss DQS2 DQS2 DQ 19 16 vss DQS1 DQS1 DQ 11 8 vss DQS0 DQS0 DQ 3 0 Vtt
48. H CA AC125 VIH CA AC175 value is used when Vref 0 175V is referenced VIH CA AC150 value is used when Vref 0 150V is referenced VIH CA AC135 value is used when Vref 0 135V is referenced and VIH CA AC125 value is used when Vref 0 125V is referenced 8 VIL ac is used as simplified symbol for VIL CA AC175 VIL CA AC150 VIL CA AC135 and VIL CA AC125 VIL CA AC175 value is used when Vref 0 175V is referenced VIL CA AC150 value is used when Vref 0 150V is referenced VIL CA AC135 value is used when Vref 0 135V is referenced and VIL CA AC125 value is used when Vref 0 125V is referenced Rev 1 0 Jul 2012 30 SK nix AC and DC I nput Levels for Single Ended Signals DDR3 SDRAM will support two Vih Vil AC levels for DDR3 800 and DDR3 1066 as specified in the table below DDR3 SDRAM will also support corresponding tDS values Table 41 and Table 47 in DDR3 Device Operation as well as derating tables in Table 44 of DDR3 Device Operation depending on Vih Vil AC lev els Single Ended AC and DC I nput Levels for DQ and DM DDR3 800 1066 DDR3 1333 1600 DDR3 1866 Symbol Parameter Unit Notes Min Max Min Max Min Max VIH DQ DC100 DC input logic high Vref 0 100 VDD Vref 0 100 VDD Vref 0 100 VDD V 1 5 VIL DQ DC100 DC input logic low VSS Vref 0 100 VSS Vref 0 100 VSS Vref 0 100 V 1 6 VIH DQ AC175 AC input logic high Vref
49. IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET and IDD7 are measured as time averaged currents with all VDD balls of the DDR3 SDRAM under test tied together Any IDDO current is not included in IDD currents DDQ currents such as IDDQ2NT and IDDO4R are measured as time averaged currents with all VDDO balls of the DDR3 SDRAM under test tied together Any IDD current is not included in IDDO cur rents Attention IDDO values cannot be directly used to calculate IO power of the DDR3 SDRAM They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2 In DRAM module application IDDQ cannot be measured separately since VDD and VDDQ are using one merged power layer in Module PCB Fo IDD and IDDO measurements the following definitions apply 0 and LOW is defined as VIN lt V LAC max e 1 and HIGH is defined as VIN gt Vinac may MID LEVEL is defined as inputs are VREF VDD 2 Timing used for IDD and IDDQ Measurement Loop Patterns are provided in Table 1 Basic IDD and IDDQ Measurement Conditions are described in Table 2 Detailed IDD and IDDO Measurement Loop Patterns are described in Table 3 through Table 10 IDD Measurements are done after properly initializing the DDR3 SDRAM This includes but is not lim ited to setting RON RZQ 7 34 Ohm in MR1 Qoff Og Output Buffer enabled in MR1 RTT_Nom RZQ 6 40 Ohm in MR1 RTT_Wr RZQ 2 1
50. K SDRAMs D 12 9 D17 PCK1B CK SDRAMs D 16 13 12 8 D17 16 13 Sg Es 290 16 EA 8 D17 Err_Out RST SDRAMs D 17 0 S 3 2 CK1 and CK1 are NC Rev 1 0 Jul 2012 14 SK nix 4GB 512Mx72 Module 1Rank of x4 pagel vss WI vss vss WwW as 2 lt i si E 20 Sle 81589 23 UE e z CIK L s LI 1111101 Doss w Dos ZO DQS17 w Dos za DQS8 DOS D DOSU ABC vss pM 2 vss DM z CB 3 0 A DQ 3 0 D8 H Al AADQ 13 01 D17 5 2 2 o o 81315882 18 218 s 8 5 DQS3 d DOS za DQS12 dd DOS zQ Doss DOS D Dos wypas a vss pm z vss DM z DOI27 2444W DQ 3 0 D3 H DQ 31 28FA DQ 3 0 D12 2 2 o o 618183168882 121818 5 4 e e e DQS2 wiDos 70 posi w pas Dasz POS D Dos wypos 3 DM Z vss DM z DQ 19 16M DQ 3 0 D2 H Dpo23 20 A DO 13 01 D11 z 2 u 21818 RIRE Big 21818 51568512 Ls e 1 e DQS1 dd DOS za DQS10 DOS zQ DOSI DOS Dos10 7w DOS DM DQL11 8 W DQ 3 0 D1 A O N BALO N 812515688 I VSS DM DQ 15 Lal DQ 3 0
51. K VDD 2 0 175 Note 3 V 1 2 VSEL Single ended low level for strobes Note 3 VDD 2 0 175 V 1 2 Single ended low level for CK CK Note 3 VDD 2 0 175 V 1 2 Notes 1 For CK CK use VIH VIL ac of ADD CMD for strobes DQS DOS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs 2 VIH ac VIL ac for DQs is based on VREFDQ VIH ac VIL ac for ADD CMD is based on VREFCA if a reduced ac high or ac low level is used for a signal group then the reduced level applies also here 3 These values are not defined however the single ended signals Ck CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to Overshoot and Undershoot Specifications on page 43 Rev 1 0 Jul 2012 36 SK yi Differential nput Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe each cross point voltage of differential input signals CK CK and DQS DQS must meet the requirements in table below The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS VDD m a CK DQS N Vix iaai sp ate aN tt VDDI2 Vix N N CK DQS VSEH VSEL VSS Vix Definition Cross point voltage for differential i
52. Par_In NC 188 A0 9 DQ2 129 DQ7 69 VDD 189 VDD 10 DQ3 130 Vss 70 A10 AP 190 BA1 11 Vss 131 DQ12 71 BA0 191 VDD 12 DQ8 132 DQ13 72 VDD 192 RAS 13 DQ9 133 Vss 73 WE 193 50 14 Vss 134 EOS 74 CAS 194 VoD 15 DOST 135 E 75 Von 195 ODTO 16 DQS1 136 Vss 76 51 NC 196 A13 17 Vss 137 DQ14 77 ODT1 NC 197 VDD 18 DQ10 138 DQ15 78 VDD 198 53 NC 19 DQ11 139 Vss 79 52 NC 199 Vss 20 Vss 140 DQ20 80 Vss 200 D036 21 DQ16 141 DQ21 81 DQ32 201 DQ37 22 DQ17 142 Vss 82 DQ33 202 Vss 23 Vss 143 E 83 Vss 203 x e u 988 a ma wo WEE 25 DQS2 145 Vss 85 DQS4 205 Vss 26 Vss 146 DQ22 86 Vss 206 DQ38 27 DQ18 147 DQ23 87 DQ34 207 DQ39 28 DQ19 148 Vss 88 DQ35 208 Vss 29 Vss 149 DQ28 89 Vss 209 DQ44 30 DQ24 150 DQ29 90 DQ40 210 DQ45 31 DQ25 151 Vss 91 DQ41 211 Vss NC No Connect RFU Reserved Future Use Rev 1 0 Jul 2012 SK CP ix pa s dr zy S Litt Juuti ete Gi Ex s isi o 32 Vss 152 ri 92 Vss 212 EN 33 DQS3 153 E 93 DQS5 213 kri 34 DQS3 154 Vss 94 DQS5 214 Vss 35 Vss 155 DQ30 95 Vss 215 DQ46 36 DQ26 156 DQ31 96 DQ42 216 DQ47 37 DQ27 157 Vss 97 D043 217 Vss 38 Vss 158 CB4 NC 98 Vss 218 DQ52 39 CB0 NC 159 CB5 NC 99 DQ48 219 DQ53 40 CB1 NC 160 Vss 100 DQ49 220 Vss 41 Vss 161 ir d 101 Ver 221 RE 42 DQS8 162 aoe 102 DQS6 222 ots 43 DQS8 163 Vss 103 DQS
53. S d L ARRASA gt RAS SDRAMs D 9 0 D 27 18 RAS Ad L BRRASA gt RAS SDRAMs D 53 44 D 71 62 ARRASB RAS SDRAMs D 17 10 D 35 28 BRRASB gt RAS SDRAMs D 43 36 D 61 54 CAS wr P L ARCASA GAS SDRAMs D 9 0 D 27 18 CAS wr P L BRCASA gt GAS SDRAMs D 53 44 D 71 62 L ARCASB CAS SDRAMs D 17 10 D 35 28 L BRCASB CAS SDRAMs D 43 36 D 61 54 WE L ARWEA WE SDRAMs D 9 0 D 27 18 WE FBRWEA WE SDRAMs D 53 44 D 71 62 ARWEB WE SDRAMs D 17 10 D 35 28 BRWEB WE SDRAMs D 43 36 D 61 54 CKE0 y A ARCKEOA gt CKE1 SDRAMs D1 D3 D5 D7 D9 CKEO w d B L BRCKEQA gt CKEI SDRAMs D45 D47 D49 D51 D53 D19 D21 D23 D25 D27 D63 D65 D67 D69 D71 ARCKEOB gt CKE1 SDRAMs D11 D13 D15 D17 BRCKEOB CKE1 SDRAMs D37 D39 D41 D43 D29 D31 D33 D35 D55 D57 D59 D61 CKE1 H ARCKE1A gt CKE0 SDRAMs D0 D2 D4 D6 D8 CKEL H BRCKE1A CKE0 SDRAMs D44 D46 D48 D50 D52 D18 D20 D22 D24 D26 D62 D64 D66 D68 D70 ARCKE1B CKE0 SDRAMs D10 D12 D14 D16 BRCKE1B CKE0 SDRAMs D36 D38 D40 D42 D28 D30 D32 D34 D54 D56 D58 D60 ODTO A ARODTOA gt ODTI SDRAMs D1 D3 D5 D7 D9 ODT1 WU L BRODT1A ODTI SDRAMs D45 D47 D49 D51 D53 _ D19 D21 D23 D25 D27 D63 D65 D67 D69 D71 ARODTOB ODTO SDRAMs D11 D13 D15 D17 BRODT1B ODTO SDRAMs D37 D39 D41 D43 D29 D31 D33 D35 D55 D57 D59 D61 CKO APCKOA CK SDRAMs D 9 0 CKO BPCKOA CK SDRAMs D 53
54. SKE yi red DIMM DDR3 SDRAM Registered DIMM Based on 2Gb C die HMT325R7CFR8C HMT351R7CFR8C HMT351R7CFR4C HMT31GR7CFR8C HMT31GR7CFR4C HMT42GR7CMR4C SK hynix reserves the right to change products or specifications without notice Rev 1 0 Jul 2012 1 SK nix Revision History Revision No History Draft Date Remark 0 1 Initial Release Aug 2011 0 2 Typo Collected 1866 Speed bin table update Sep 2011 1 0 Latest J EDEC Spec and Product Line up Updated Jul 2012 Rev 1 0 Jul 2012 SK nix Description Registered DDR3 SDRAM DIMMs Registered Double Data Rate Synchronous DRAM Dual In Line Memory Modules are low power high speed operation memory modules that use DDR3 SDRAM devices These Registered SDRAM DIMMs are intended for use as main memory when installed in systems such as servers and workstations Features Power Supply VDD 1 5V 1 425V to 1 575V VDDQ 1 5V 1 425V to 1 575V VDDSPD 3 0V to 3 6V Functionality and operations comply with the DDR3 SDRAM datasheet 8 internal banks Data transfer rates PC3 14900 PC3 12800 PC3 10600 PC3 8500 Bi Directional Differential Data Strobe 8 bit pre fetch Burst Length BL switch on the fly BL8 or BC4 Burst Chop Supports ECC error correction and detection On Die Termination ODT Temperature sensor with integrated SPD This product is in compliance with the RoHS directive Ordering I nformation Pa
55. Settings 5 6 MK Rev 1 0 Jul 2012 47 SK nix DDR3 1333 Speed Bins For specific Notes See Speed Bin Table Notes on page 51 Speed Bin DDR3 1333H Unit Note CL nRCD nRP 9 9 9 Parameter Symbol min max Internal read 13 5 t command to first data 13 125 510 E ACT to internal read or 13 5 _ oe write delay time RED 13 125 510 13 5 PRE command period Ir ns p RP 13 125 gt 10 ACT to ACT or REF n 49 5 _ a command period RC 49 125 5 10 ACT to PRE command N Ir period RAS 36 9 tREFI ns CWL 25 lCK AVG 2 5 3 3 ns 1 2 3 7 CL 6 CWL 6 amp xave Reserved ns 1 2 3 4 7 CWL 7 ICK AVG Reserved ns 4 CWL 5 CK AVG Reserved ns 4 1 875 lt 2 5 CL 7 CWL 6 IcK AVG ns 1 2 3 4 7 Optional 5 10 CWL 7 aver Reserved ns 1 2 3 4 CWL 5 awe Reserved ns 4 CL 8 CWL 6 CK AVG 1 875 2 5 ns 1 2 3 7 CWL 7 lck AVG Reserved ns 1 2 3 4 CWL 5 6 KK AVG Reserved ns 4 CWL 7 fave 1 5 lt 1 875 ns 1 2 3 4 CWL 5 6 amp kave Reserved ns 4 CL 10 1 5 lt 1 875 ns 1 2 3 k SES EKIAVG Optional ns 5 Supported CL Settings 6 7 8 9 10 Mk Supported CWL Settings 5 6 7 MK Rev 1 0 Jul 2012 48 SK nix DDR3 1600 Speed Bins For specific Notes See Speed Bin Table Notes on page 51
56. als perform Low unique functions including disabling all outputs except CKE and ODT of the register s on the DIMM or accessing internal control words in the register device s For modules with two registers S 3 2 operate similarly to S 1 0 for the second set of register out puts or register control words ODT 1 0 IN du On Die Termination control signals RAS CAS WE IN Active When sampled at the positive rising edge of the clock CAS RAS and WE define the i I Low operation to be executed by the SDRAM VREFDO Supply Reference voltage for DQ0 DQ63 and CBO CB7 V Suppl Reference voltage for A0 A15 BA0 BA2 RAS CAS WE S0 S1 CKE0 CKE1 Par_In REFCA pp y ODTO and ODT1 Selects which SDRAM bank of eight is activated BA 2 0 IN N BAO BA2 define to which bank an Active Read Write or Precharge command is being applied Bank address also determines mode register is to be accessed during an MRS cycle Provided the row address for Active commands and the column address and Auto Precharge bit for Read Write commands to select one location out of the mem A 15 13 ory array in the respective bank A10 is sampled during a Precharge command to deter 12 BC 11 IN mine whether the Precharge applies to one bank A10 LOW or all banks A10 HIGH If 10 AP 9 0 only one bank is to be precharged the bank is selected by BA A12 is also utilized for BL 4 8 identification for BL on the fly during CAS command The address inputs also pro vid
57. and DC I nput Levels for Command and ADDress DDR3 800 1066 1333 1600 DDR3 1866 Symbol Parameter Unit Notes Min Max Min Max VIH CA DC100 DC input logic high Vref 0 100 VDD Vref 0 100 VDD V 1 5 VIL CA DC100 DC input logic low VSS Vref 0 100 VSS Vref 0 100 V 1 6 VIH CA AC175 AC input logic high Vref 0 175 Note2 V 1 2 7 VIL CA AC175 AC input logic low Note2 Vref 0 175 S V 1 2 8 VIH CA AC150 AC Input logic high Vref 0 150 Note2 V 1 2 7 VIL CA AC150 AC input logic low Note2 Vref 0 150 V 1 2 8 VIH CA AC135 AC input logic high Vref 0 135 Note2 V 1 2 7 VIL CA AC135 AC input logic low Note2 Vref 0 135 V 1 2 8 VIH CA AC125 AC Input logic high Vref 0 125 Note2 V 1 2 7 VIL CA AC125 AC input logic low Note2 Vref 0 125 V 1 2 8 VRefCA DC m 0 49 VDD 0 51 VDD 0 49 VDD 0 51 VDD V 3 4 Notes 1 For input only pins except RESET Vref VrefCA DC 2 Refer to Overshoot and Undershoot Specifications on page 43 3 The ac peak noise on Veer may not allow Veer to deviate from Vrercaipcy by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV 5 VIH dc is used as a simplified symbol for VIH CA DC100 6 VIL dc is used as a simplified symbol for VIL CA DC100 7 VIH ac is used as simplified symbol for VIH CA AC175 VIH CA AC150 VIH CA AC135 and VI
58. binning to DDR3 1600 or DDR3 1333 or 1066 should program 13 125ns in SPD bytes for tAAmin byte 16 tRCDmin byte 18 and tRPmin byte 20 is programmed to 13 125ns tRCmin byte 21 23 also should be programmed accordingly For example 47 125ns tRASmin tRPmin 34ns 13 125ns Rev 1 0 Jul 2012 51 SK yi Environmental Parameters Symbol Parameter Rating Units Notes Topr Operating temperature See Note 3 Hopr Operating humidity relative 10 to 90 1 TsrG Storage temperature 50 to 100 oc 1 Hera Storage humidity without condensation 5 to 95 K 1 PBAR Barometric Pressure operating amp storage 105 to 69 K Pascal 4 2 Note 1 Stress greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied Expousure to absolute maximum rating conditions for extended periods may affect reliablility 2 Up to 9850 ft 3 The designer must meet the case temperature specifications for individual module components Rev 1 0 Jul 2012 52 SK yi IDD and I DDO Specification Parameters and Test Conditions IDD and I DDO Measurement Conditions In this chapter IDD and IDDO measurement conditions such as test load and patterns are defined Figure 1 shows the setup and test load for IDD and IDDO measurements IDD currents such as IDDO IDD1 IDD2N IDD2NT IDD2P0 IDD2P1
59. ccording to Table 5 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 Precharge Standby ODT Current CKE High External clock On tCK CL see Table 1 BL 88 AL 0 CS stable at 1 Command Address Bank ppant Address Inputs partially toggling according to Table 6 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal toggling according to Table 6 Pattern Details see Table 6 Precharge Power Down Current Slow Exit fios CKE Low External clock On tCK CL see Table 1 BL 88 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data 10 MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Slow Exit Precharge Power Down Current Fast Exit fum CKE Low External clock On tCK CL see Table 1 BL 88 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Fast Exit Precharge Quiet Standby Current CKE High External clock On tCK CL see Table 1 BL 89 AL 0 CS stable at 1 Command Address Bank Addre
60. cts due to ac noise on Vp up to the speci fied limit 1 of VDD are included in DRAM timings and their associated deratings Rev 1 0 Jul 2012 32 SK nix AC and DC Logic I nput Levels for Differential Signals Differential signal definition VILDIFFACMIN o fee e ea O oe Stee ss A 222 EAS E CU CAM Bl 1 ce at bala half cycle mr Saa astas tel Differential Input Voltage i e DQS DQS CK CK VILDIRRACMAN eee eee N Foe ers e I Definition of differential ac swing and time above ac level tpvac Rev 1 0 Jul 2012 33 SK nix Differential swing requirements for clock CK CK and strobe DQS DQS Differential AC and DC I nput Levels DDR3 800 1066 1333 1600 Symbol Parameter Unit Notes Min Max VIHdiff Differential input high 0 180 Note 3 V 1 VILdiff Differential input logic low Note 3 0 180 V 1 VIHdiff ac Differential input high ac 2 x VIH ac Vref Note 3 V 2 VILdiff ac Differential input low ac Note 3 2 x VIL ac Vref V 2 Notes 1 Used to define a differential signal slew rate 2 For CK CK use VIH VIL ac of AADD CMD and VREFCA for DQS DQS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs and VREFDQ if a reduced ac high or ac low levels is used for a signal group then the reduced level applies also here 3 These values are not defined however the single ended signals Ck CK DQS DQS DQSL
61. e the op code during Mode Register Set commands DQ 63 0 CBI7 0 1 0 Data and Check Bit Input Output pins Active c vd T DM 8 0 IN High Masks write data when high issued concurrently with input data Vpp Vss Supply Power and ground for the DDR SDRAM input buffers and core logic Vit Supply Termination Voltage for Address Command Control Clock nets Rev 1 0 Jul 2012 sd Symbol Type Polarity Function Positive TT DQS 17 0 1 0 Edge Positive line of the differential data strobe for input and output data OP EE Negative poc DQS 17 0 1 0 Edge Negative line of the differential data strobe for input and output data TDQS TDQS is applicable for X8 DRAMs only When enabled via Mode Register A11 1 in TDQS 17 9 MR1 DRAM will enable the same termination resistance function on TDQS TDQS that is TDQS 17 9 OUT applied to DQS DQS When disabled via mode register A11 0 in MR1 DM TDQS will provide the data mask function and TDQS is not used X4 X16 DRAMs must disable the TDQS function via mode register A11 0 in MR1 SA 2 0 IN These signals are tied at the system planar to either Vss or Vppspp to configure the serial SPD EEPROM address range This bidirectional pin is used to transfer data into or out of the SPD EEPROM A resistor SDA 1 0 must be connected from the SDA bus line to Vppspp on the system planar to act as a pullup SCL IN This signal is u
62. f VIHdiffmin ViLdiffmax VIHdiffmin VILdiffmax Delta T Fdiff Differential Input Voltage i e DOS DOS CK CK I l I I I I I u lt T 2 3 3 par vILdiffmax Differential Input Slew Rate Definition for DOS DQS and CK CK Differential Input Slew Rate Definition for DQS DQS and CK CK Rev 1 0 Jul 2012 38 SK nix AC amp DC Output Measurement Levels Single Ended AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Single ended AC and DC Output Levels DDR3 800 1066 Symbol Parameter Unit Notes 1333 and 1600 VoH DC DC output high measurement level for IV curve linearity 0 8 x VDDQ V Vom Dc DC output mid measurement level for IV curve linearity 0 5 x Vppq V VoL DO DC output low measurement level for IV curve linearity 0 2 x Vppq V VoH AC AC output high measurement level for output SR Vrr 0 1 x Vppo V 1 VoL AC AC output low measurement level for output SR Vrr 0 1 x Vppo V 1 Notes 1 The swing of 0 1 x Vppo is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to Vrr Vppg 2 Differential AC and DC Output Levels Table below shows the output levels used for measurements of single ended s
63. functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization DDR3 SDRAM devices supporting optional down binning to CL 7 and CL 9 and tAA tRCD tRP must be 13 125 ns or lower SPD settings must be programmed to match For example DDR3 1333H devices supporting down binning to DDR3 1066F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 DDR3 1600K devices supporting down binning to DDR3 1333H or DDR3 1600F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 Once tRP Byte 20 is programmed to 13 125ns tRCmin Byte 21 23 also should be programmed accordingly For example 49 125ns tRASmin tRPmin 36 ns 13 125 ns for DDR3 1333H and 48 125ns tRASmin tRPmin 35 ns 13 125 ns for DDR3 1600K DDR3 SDRAM devices supporting optional down binning to CL 11 CL 9 and CL 7 tAA tRCD tRPmin must be 13 125ns SPD setting must be programed to match For example DDR3 1866 devices sup porting down
64. he time DOS DOS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DO signal by Read Command Outside burst operation DQ signals are MID LEVEL Rev 1 0 Jul 2012 60 Ds SK hynix Table 5 IDD2N and I DD3N Measurement Loop Pattern S amp o E Ss aloin s Pegg ble Bigs E B 3 E 528 vuo Q E M 3 8 GB x lt lt lt 0 0 D 1 0 0 0 0 0 0 0 0 0 0 1 D 1 0 0 0 0 0 0 0 0 0 0 2 D 1 1 1 11 0 0 01 D 0 F 0 3 D 1 1 1 1 0 0 01 0 1 0 F 0 2 5 1 4 7 repeat Sub Loop 0 use BA 2 0 1 instead D 2 8 11 repeat Sub Loop 0 use BA 2 0 2 instead E 5 3 12 15 repeat Sub Loop 0 use BA 2 0 3 instead 4 16 19 repeat Sub Loop 0 use BA 2 0 4 instead 5 20 23 repeat Sub Loop 0 use BA 2 0 5 instead 6 24 17 repeat Sub Loop 0 use BA 2 0 6 instead 7 28 31 repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DOS DOS are MID LEVEL b DO signals are MID LEVEL Table 6 IDD2NT and I DDO2NT Measurement Loop Pattern Y o D E o G lt v8 12 SE 1121815855833 363 o Q E M 3 8 ao z lt lt lt 0 0 D 1 0 0 0 0 0 0 0 0 0 0 1 D 110 0 0 0 0 0 0 0 0 0 2 D 1l1 1 1 0 0 0 0 0 FIJO 3 D 1 1 1 1 0 0 0 0 0 F J 0 2 5 1 4 7 repeat Sub Loop 0 but ODT 2 0 and
65. ignals Differential AC and DC Output Levels DDR3 800 1066 Symbol Parameter Unit Notes 1333 and 1600 Voudift ac AC differential output high measurement level for output SR 0 2 x VDDQ V 1 VoLaiff AC AC differential output low measurement level for output SR 0 2 x Vppq V 1 Notes 1 The swing of 0 2 x Vppq is based on approximately 50 of the static differential output high or low swing with a driver impedance of 40 9 and an effective test load of 25 to Vtr Vppg 2 at each of the differential outputs Rev 1 0 Jul 2012 39 SK nix Single Ended Output Slew Rate When the Reference load for timing measurements output slew rate for falling and rising edges is defined and measured between Vo ac and Voy ac for single ended signals are shown in table and figure below Single ended Output slew Rate Definition Measured Description Defined by From To Single ended output slew rate for rising edge VOL AC VOH AC Voun acy Voro DeltaTRse Single ended output slew rate for falling edge VoH AC VoL AC Voro VoL Ac l DeltaTFse Notes 1 Output slew rate is verified by design and characterisation and may not be subject to production test D g p vOH AC Y 8 S 4 3 v TT g o 5 9 2 K EE g vOI AC Single Ended Output Slew Rate Definition Single Ended Outp
66. is 8 w 1818 a w 5 2181188582 12181 618852 E gt La La La DOs YM Dos imi VSS M a EN 3 BD g GR 3 E 3 W DQ 3 0 D15 DQ 3 0 D14 i DQ 3 0 D39 3 DQ 3 0 D38 z 3 8 w 18182 168 8 21815188582 wile 8 12181 s 8 5 La t La T e Ze YM Bs VSS WY Das VSS pa SC SZ 3 E El EN 3 pas g W 00 3 0 D17 EI DQ 3 0 D16 DQ 3 0 D37 Zare D36 EI 3 8 8 8 w 2188 168 3 21813188582 21813188582 6121818 s EET e e e N Rev 1 0 Jul 2012 25 S CP ix K 16GB 2Gx72 Module 4Rank of x4 page4 vss DQS13 DQS13 VSS DQ 39 36 vss DQS14 DQS14 VSS DQ 47 44 vss DQS15 DQS15 VSS DQ 55 52 vss DOS16 DOS16 vss DQ 63 60 vt Note
67. mponent IDD spec and register power The actual measurements may vary according to DQ loading cap 2GB 256M x 72 R DIMM HMT325R7CFR8C Symbol DDR3 1333 DDR3 1600 DDR3 1866 Unit note IDDO 1124 1169 1169 mA IDD1 1214 1259 1304 mA IDD2N 944 989 989 mA IDD2NT 989 1034 1034 mA IDD2PO 336 336 336 mA IDD2P1 363 363 381 mA IDD2Q 971 971 989 mA IDD3N 1007 1034 1034 mA IDD3P 363 384 390 MA IDD4R 1574 1709 1889 MA IDDAW 1529 1619 1844 mA IDD5B 1799 1844 1844 mA IDD6 336 336 336 mA IDD6ET 354 354 354 mA IDD7 2384 2429 2564 mA 4GB 512M x 72 R DI MM HMT351R7CFR8C Symbol DDR3 1333 DDR3 1600 DDR3 1866 Unit note IDDO 1304 1439 1439 mA IDD1 1394 1529 1574 mA IDD2N 1124 1214 1214 mA IDD2NT 1214 1304 1304 mA IDD2PO 444 444 444 mA IDD2P1 498 498 534 mA IDD2Q 1178 1178 1214 mA IDD3N 1250 1304 1304 mA IDD3P 498 534 552 MA IDD4R 1754 1979 2159 MA IDDAW 1709 1889 2114 mA IDD5B 1979 2114 2114 mA IDD6 444 444 444 mA IDD6ET 480 480 480 mA IDD7 2564 2699 2834 mA Rev 1 0 Jul 2012 65 SK uix 4GB 512M x 72 R DI MM HMT351R7CFR4C Symbol DDR3 1333 DDR3 1600 DDR3 1866 Unit note IDDO 1484 1574 1574 mA IDD1 1664 1754 1844 mA IDD2N 1124 1214 1214 mA ID
68. nix Table 4 IDD1 Measurement Loop Pattern y g z o GZ a e U eli 3 Pilg 8 i 8 S 3 5 8 vat 2 03 5 lt lt lt lt lt 0 0 ACT 0 0 1 1 0 0 0 0 0 0 1 2 DD 1 O 0 0 0 0 0 0 O 0 3 4 DD 1 1 11 4 0 0 0 0 0 0 v repeat pattern 1 4 until nRCD 1 truncate if necessary nRCD RD 0 110 1 0 0 0 0 0 0 0 00000000 WM repeat pattern 1 4 until nRAS 1 truncate if necessary nRAS PRE 0 0 1 0 0 0 0 0 0 0 0 ja repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 0 0 1 1 0 0 0 0 0 F 0 1 nRC 1 2 DD 1 O 0 0 0 0 0 0 O F 0 2 1 nRC 3 4 DD 1 1 1 1 0 0 0 0 0 F o a v ai repeat pattern nRC 1 4 until nRC nRCE 1 truncate if necessary B 1 nRC nRCD RD 0 1 0 1 0 0 0 0 0 F o 00110011 s repeat pattern nRC 1 4 until nRC nRAS 1 truncate if necessary 1 nRC nRAS PRE 0 0 1 0 0 0 0 0 0 F 0 T repeat pattern nRC 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all t
69. nput signals CK DOS DDR3 800 1066 1333 1600 amp 1866 Symbol Parameter Unit Notes Min Max Differential Input Cross Point Voltage I Vix relative to VDD 2 for CK CK 199 190 O N Differential Input Cross Point Voltage Vix relative to VDD 2 for DOS DOS met Notes 1 The relation between Vix Min Max and VSEL VSEH should satisfy following VDD 2 Vix Min VSEL gt 25mV VSEH VDD 2 Vix Max gt 25mV Rev 1 0 Jul 2012 37 SK nix Slew Rate Definitions for Single Ended I nput Signals See 7 5 Address Command Setup Hold and Derating on page 134 in DDR3 Device Operation for sin gle ended slew rate definitions for address and command signals See 7 6 Data Setup Hold and Slew Rate Derating on page 142 in DDR3 Device Operation for single ended slew rate definition for data signals Slew Rate Definitions for Differential nput Signals Input slew rate for differential signals CK CK and DQS DQS are defined and measured as shown in table and figure below Differential I nput Slew Rate Definition Measured N Description Defined by Min Max Differential input slew rate for rising edge CK CK and DOS DOS Differential input slew rate for falling edge CK CK and DOS DOS Notes The differential signal i e CK CK and DOS DOS must be linear between these thresholds VILdiffmax VIHdiffmin VIHdiffmin VlLdiffmax Delta T Rdif
70. o the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rat ing conditions for extended periods may affect reliability Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard VDD and VDDQ must be within 300mV of each other at all times and VREF must not be greater than 0 6XVDDQ When VDD and VDDQ are less than 500mV VREF may be equal to or less than 300mV DRAM Component Operating Temperature Range Temperature Range Symbol Parameter Rating Units Notes T Normal Operating Temperature Range 0 to 85 C 1 2 OPER Extended Temperature Range 85 to 95 C 1 3 Notes 1 Operating Temperature TOPER is the case surface temperature on the center top side of the DRAM For mea surement conditions please refer to the JEDEC document J ESD51 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported Dur ing operation the DRAM case temperature must be maintained between 0 85 C under all operating conditions Some applications require operation of the DRAM in the Extended Temperature Range between 85 C and 95 C case temperature Full specifications are guaranteed in this range bu
71. perature Range SRT set MR2 A7 OB for normal or 1B for extended temperature range f Read Burst Type Nibble Sequential set MRO A 3 0B Rev 1 0 Jul 2012 58 SK nix Table 3 IDD0 Measurement Loop Pattern L 8 9 E E n e K mS v BZ BE EIE BS 3 3 ba 0 0 ACT 0 O 1 1 0 0 00 0 0 1 2 DD 1 O 0 0 0 0 00 0 0 3 4 DD 1 1 1 1 0 0 00 0 0 a repeat pattern 1 4 until nRAS 1 truncate if necessary nRAS PRE 0 O 1 0 0 0 00 0 0 0 0 m repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 0 O 1 1 0 0 00 0 0 F 0 1 nRC 1 2 DD 1 0 0 0 0 0 0 O 0 F 0 9 3 1 nRC 3 4 IDD 1 1 1 1 0 0 0 0 0 F o0o D v 5i repeat pattern 1 4 until 1 nRC nRAS 1 truncate if necessary 988 1 nRC nRAS PRE 0 0 1 0 0 0 0 0 0 Flo sis repeat pattern 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DOS DOS are MID LEVEL b DO signals are MID LEVEL 59 Rev 1 0 Jul 2012 De SK hy
72. presentative Vppspp EE Serial PD VDD n D0 D17 Vir n D0 D17 VREFCA A D0 D17 VREFDQ D0 D17 Vss D0 D17 13 SK yi 4GB 512Mx72 Module 2Rank of x8 page2 S0 W L 1 2 S1 S 3 2 NC R BAIN 0 yy E L AN 0 GE GE RAS s F WE RF CKE0 w L CKEL dd LL L ODTO dV e ODTI E CKO 1202 L o 15 CKO Kl 1202 CK1 2 PAR IN wW OERR RESET RST RSOA gt CS0 SDRAMs D 3 0 D8 RSOB CS0 SDRAMs D 7 4 RSIA gt CSI SDRAMs D 12 9 D17 RS1B gt CSI SDRAMs D 16 13 RBA N 0 A BA N 0 SDRAMs D 3 S N 0 B BA N 0 SDRAMs D 7 A N 0 ANO SDRAMs D 3 0 A N 0 B_ A N 0 SDRAMs D 7 4 MN RAS SDRAMs D 3 0 D 12 RRASB RAS SDRAMs D 7 4 D 16 13 RCASA gt CAS SDRAMs D 3 0 D 12 8 D17 RCASB CAS SDRAMs D 7 4 D 16 13 RWEA gt WE SDRAMs D 3 0 D 12 8 D17 RWEB WE SDRAMs D 7 4 D 16 13 RCKEOA gt CKEO SDRAMs D 3 0 D8 RCKEOB CKE0 SDRAMs D 7 4 RCKE1A CKEI SDRAMs D 12 9 D17 RCKE1B gt CKEI SDRAMs D 16 13 RODTOA ODTO SDRAMs D 3 0 D8 RODTOB ODTO SDRAMs D 7 4 RODTIA_ gt ODTI SDRAMs D 12 9 D17 RODT1A gt ODTI SDRAMs D 16 13 PCKOA CK SDRAMs D 3 0 D8 PCKOB CK SDRAMs D 7 4 PCKIA gt CK SDRAMs D 12 9 D17 PCK1B CK SDRAMs D 16 13 PCKOA CK SDRAMs D 3 0 D8 PCKOB CK SDRAMs D 7 4 PCKIA C
73. rameter Symbol min max Internal read command ba 13 91 20 E to first data 13 125 511 ACT to internal read or en 13 91 n write delay time 13 125 gt 1 PRE command period tap id ns 13 125 ACT to PRE command fans 34 9 tREFI T period ACT to ACT or PRE 47 91 command period RC 47 125 5 11 I i CWL 5 CK AVG 2 5 3 3 ns 1 2 3 9 CL 6 CWL 6 CK AVG Reserved ns 1 2 3 4 9 CWL 7 8 9 aver Reserved ns 4 CWL 5 fcK AVG Reserved ns 4 CL 7 CWL 6 CK AVG 1 875 lt 2 5 ns 1 2 3 4 9 CWL 7 8 9 tekave Reserved ns 4 CWL 5 ck AVG Reserved ns 4 CL 8 CWL 6 ck AVG 1 875 2 5 ns 1 2 3 9 CWL 7 CK AVG Reserved ns 1 2 3 4 9 CWL 8 9 aver Reserved ns 4 CWL 5 6 KK AVG Reserved ns 4 crag L ENL ZT xavo 1 5 1 875 ns 1 2 3 4 9 CWL 8 CK AVG Reserved ns 1 2 3 4 9 CWL 9 ck AVG Reserved ns 4 CWL lt 5 6 ck AvG Reserved ns 4 CL 10 CWL 7 LK AVG 1 5 lt 1 875 ns 1 2 3 9 CWL 8 fcK AVG Reserved ns 1 2 3 4 9 CWL 5 6 7 fck ave Reserved ns 4 CL 11 CWL 8 fcK AVG 1 25 1 5 ns 1 2 3 4 9 CWL 9 CK AVG Reserved ns 1 2 3 4 CL 12 CWL 5 6 7 8 fck ave Reserved 4 CWL 9 ck AVG Reserved ns 1 2 3 4 CL 13 CWL 5 6 7 8 Ick AvG Reserved HE 4 CWL 9 ck AVG 1 07 1 25 ns 1 2 3 Supported CL Settings 6 7 8 9 10 11 13 Mk Supported CWL Settings 5 6 7 8 9 Mk Rev 1 0 Jul 2012 50 w SK hynix Speed Bin Table Notes Absolute Specification ToPER VDDQ Vpp 1 5V 0 075 V
74. rt Number Density Organization Component Composition aoe FDHS HMT325R7CFR8C H9 PB RD 2GB 256Mx72 256Mx8 H5TQG83CFR 9 1 X HMT351R7CFR8C H9 PB RD 4GB 512Mx72 256Mx8 H5TQ2G83CFR 18 2 X HMT351R7CFRAC H9 PB RD 4GB 512Mx72 512Mx4 H5TQ2G43CFR 18 1 X HMT31GR7CFR8C G7 H9 PB 8GB 1Gx72 256Mx8 H5TQ2G83CFR 36 4 O HMT31GR7CFR4C H9 PB RD 8GB 1Gx72 512Mx4 H5TQ2G43CFR 36 2 0 HMT42GR7CMR4C G7 H9 PB 16GB 2Gx72 DDP 1Gx4 H5TQ4G43CMR 36 4 0 In order to uninstall FDHS please contact sales administrator Rev 1 0 Jul 2012 3 SK nix Key Parameters CAS RAS MT s Grade SEK Latency ice oan ERE CL tRCD tRP ns ns ns ns ns tCK DDR3 1066 G7 1 875 7 13 125 13 125 37 5 50 625 7 7 7 13 5 13 5 49 5 DDR3 1333 H9 1 5 9 13 125 13 125 36 49 125 9 9 9 13 75 13 75 48 75 DDR3 1600 PB 1 25 11 13 125 13 125 35 48 125 11 11 11 13 91 13 91 47 91 DDR3 1866 RD 1 07 13 13 125 13 125 34 48 125 13 13 13 SK hynix DRAM devices support optional downbinning to CL11 CL9 and CL7 SPD setting is programmed to match Speed Grade Frequency MHz Grade Remark CL6 CL7 CL8 CL9 CL10 CL11 CL12 CL13 G7 800 1066 1066 H9 800 1066 1066 1333 1333 PB 800 1066 1066 1333 1333 1600 RD 800 1066 1066 1333 1333 1600 1866 Address Table 2GB 1Rx8 4GB 2Rx8 4GB 1Rx4 8GB 4Rx8
75. s are MID LEVEL Table 8 IDD4W Measurement Loop Pattern o v eS Y o lt m Bg i 8 lekkkSS3S5 om S ERR z lt lt lt I 0 10 WR 0 1 0 0 1 0 0 0 0 0 0 00000000 1 D 1 0 0 0 1 0 00 0 0 0 0 2 3 DD 1 1 1 1 1 oloo 0 0190 4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011 5 D 1 0 0 0 1 0 00 0 0 F 0 2 2 6 7 D D 1 1 1 1 1 0 00 0 0 F 0 9 1 8 15 repeat Sub Loop 0 but BA 2 0 1 8 8 2 16 23 repeat Sub Loop 0 but BA 2 0 2 3 24 31 repeat Sub Loop 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 but BA 2 0 4 5 40 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DQS DQS are used according to WR Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Write Command Outside burst operation DQ signals are MID LEVEL Rev 1 0 Jul 2012 62 Ds SK hynix Table 9 IDD5B Measurement Loop Pattern Y o H E o imimimiz soa BE po BEBSIIiii 0 0 REF 0 0 0 0 0 0 0 1 1 2 DD 1 0 0 0 0 00 0 3 4 DD 1 1 1 1 0 0 00 0 5 8 repeat cycles 1 4 but BA 2 0 1 2 5 9 12 repeat cycles 1 4 but BA 2 0 2 2 D 13 16 repeat cycles 1 4 but BA 2 0 3 8
76. s refer to the 1 TITTI appropriate wiring diagram Vtt 34 N 50 P L RSOA CS0 SDRAMs D 3 0 DS SI i RSOB gt CS0 SDRAMs D 7 4 BA N 0 WY F RBA N 0 A BA N 0 SDRAMs D 3 0 D8 2 RBA N OJA BA N 0 SDRAMs D 7 4 AIN 0 R F RAIN 0JA gt A N 0 SDRAMs D 3 0 D8 m E RA N 0 A A Nook SDRAMs pp RAS H RRASA RAS N G RRASA RAS unm D8 VDDSPD VDDSPD SAO SAO QS RCASA gt CAS SDRAMs D 3 0 DS EVENT EVENT SPD with SA1 SA1 MP S RCASA gt CAS SDRAMs D 7 4 WE ir RWEA WE SDRAMs D 3 0 DS sc sc Integrated sa saz RWEA WE SDRAMs D 7 4 TS CKE0 Mw E L RCKE0A gt CKEO SDRAMs D 3 0 DS SDA SDA VSS VSS R RCKEOB gt CKE0 SDRAMs D 7 4 ODTO VV RODTOA gt ODTO SDRAMs D 3 0 D8 Plan to use SPD with Integrated TS of Class B and RODTOB ODTO SDRAMs D 7 4 S CKO P L PCK0A gt CK SDRAMs DD might be changed on customer s requests For more E CK s D 3 0 D8 details of S d Th I a Ss L PCKOB CK SDRAMs D 7 4 etails o PD and Therma sensor please contact CKO L PCKOA CK SDRAMs D 3 0 DS local SK hynix sales representative CKO 2100 PCKOB CK SDRAMs D 7 4 CKO 1 PAR IN OERRF Err Out RESET RST m RST SDRAMs D 8 0 S 3 2 CKE1 ODT1 are NC Unused register inputs ODT1 and CKE1 have a 3302 resistor to ground Rev 1 0 Jul 2012 12 SK nix 4GB 512Mx72 Module 2Rank of x8
77. sed to clock data into and out of the SPD EEPROM A resistor may be con B nected from the SCL bus time to Vppspp on the system planar to act as a pullup OUT This signal indicates that a thermal event has been detected in the thermal sensing EVENT Active L device The system should guarantee the electrical level requirement is met for the Uem CuVe LOW EVENT pin on TS SPD part No pull up resister is provided on DI MM V Suppl Serial EEPROM positive power supply wired to a separate power pin at the connector DDSPD HDN which supports from 3 0 Volt to 3 6 Volt nominal 3 3V operation The RESET pin is connected to the RESET pin on the register and to the RESET pin on RESET IN the DRAM Par In IN Parity bit for the Address and Control bus 1 Odd 0 Even Er Out OUT Parity error detected on the Address and Control bus A resistor may be connected from in ezer Err Out bus line to Vpp on the system planar to act as a pull up TEST Used by memory bus analysis tools unused NC on memory DIMMs Rev 1 0 Jul 2012 SK nix Pin Assignments EE eae 50 doce EE SE left A E EE EE 1 VREFDQ 121 Vss 61 A2 181 Al 2 Vss 122 DQ4 62 VDD 182 VDD 3 DQO 123 DQ5 63 NC CK1 183 VDD 4 DQ1 124 Vss 64 NC CK1 184 CKO 5 Vss 125 k 65 Von 185 TKO 6 DQSO 126 66 Von 186 VoD 7 DQS0 127 Vss 67 VREFCA 187 EVENT NC 8 Vss 128 DQ6 68
78. shoot Definition Rev 1 0 Jul 2012 43 SK uix Clock Data Strobe and Mask Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Clock Data Strobe and Mask DDR3 DDR3 DDR3 DDR3 DDR3 Parameter Units 800 1066 1333 1600 1866 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 04 04 04 04 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 04 04 V Maximum overshoot area above VDD See Figure below 0 25 0 19 0 15 0 13 0 11 V ns Maximum undershoot area below VSS See Figure below 0 25 0 19 0 15 0 13 0 11 V ns CK CK DO DOS DOS DM See figure below for each parameter definition Maximum Amplitude Overshoot Area DQ Volts V VSSQ Undershoot Area Maximum Amplitude Time ns Clock Data Strobe and Mask Overshoot and Undershoot Definition Clock Data Strobe and Mask Overshoot and Undershoot Definition Rev 1 0 Jul 2012 44 SK nix Refresh parameters by device density Refresh parameters by device density Rev 1 0 Jul 2012 Parameter RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units Notes REF command AG T r tRFC 90 110 160 260 350 ns REF command time Average periodic IREFI 0 C lt TcASE lt 85 C 7 8 7 8 7 8 7 8 7 8 us refresh interval 85 C lt Tease lt 95 0 3 9 3 9 3 9 3 9 3 9 us 1
79. ss Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Active Standby Current CKE High External clock On tCK CL see Table 1 BL 88 AL 0 CS stable at 1 Command Address Bank lppsN Address Inputs partially toggling according to Table 5 Data IO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 Active Power Down Current T CKE Low External clock On tCK CL see Table 1 BL 88 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data lO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Rev 1 0 Jul 2012 56 SK nix Symbol Description ppar Operating Burst Read Current CKE High External clock On tCK CL see Table 1 BL 89 AL 0 CS High between RD Command Address Bank Address Inputs partially toggling according to Table 7 Data IO seamless read data burst with different data between one burst and the next one according to Table 7 DM stable at 0 Bank Activity all banks open RD commands cycling through banks 0 0 1 1 2 2 see Table 7 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 7 ppaw
80. t chop 1 Vos Ground 59 BA 2 0 SDRAM Bank Addresses 3 VREFDO Reference Voltage for DQ 1 Serial Presence Detect SPD V SCL Clock Input 1 REFCA Reference Voltage for CA 1 SDA SPD Data Input Output 1 ViT Termination Voltage 4 SA 2 0 SPD Address Inputs 3 Vppspp SPD Power 1 Parity bit for the Address and Par_In 1 Control bus Parity error found on the Err Out Address and Control bus Rev 1 0 Jul 2012 5 SK nix I nput Output Functional Descriptions Symbol Type Polarity Function CKO IN Positive Positive line of the differential pair of system clock inputs that drives input to the on Line DIMM Clock Driver CKO IN Negative Negative line of the differential pair of system clock inputs that drives the input to the Line on DIMM Clock Driver CK1 IN id Terminated but not used on RDIMMs CK1 IN a G Terminated but not used on RDIMMs CKE HIGH activates and CKE LOW deactivates internal clock signals and device input CKE 1 0 IN Active buffers and output drivers of the SDRAMs Taking CKE LOW provides PRECHARGE i High POWER DOWN and SELF REFRESH operation all banks idle or ACTIVE POWER DOWN row ACTIVE in any bank Enables the command decoders for the associated rank of SDRAM when low and dis ables decoders when high When decoders are disabled new commands are ignored ST3 0 IN Active and previous operations continue Other combinations of these input sign
81. t the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the Refresh interval tREFI to 3 9 us It is also possible to specify a component with 1X refresh tREFI to 7 8us in the Extended Temperature Range Please refer to the DIMM SPD for option availability b If Self Refresh operation is required in the Extended Temperature Range then it is mandatory to either use the Manual Self Refresh mode with Extended Temperature Range capability MR2 A6 Ob and MR2 A7 1b or enable the optional Auto Self Refresh mode MR2 A6 1b and MR2 A7 0b DDR3 SDRAMs support Auto Self Refresh and in Extended Temperature Range and please refer to component datasheet and or the DIMM SPD for tREFI requirements in the Extended Temperature Range Rev 1 0 Jul 2012 28 SK nix AC amp DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions Rating Symbol Parameter Units Notes Min Typ Max VDDQ supply Voltage for Output 1 425 1 500 1 575 1 2 Notes 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together Rev 1 0 Jul 2012 29 SK nix AC amp DC Input Measurement Levels AC and DC Logic I nput Levels for Single Ended Signals AC and DC I nput Levels for Single Ended Command and Address Signals Single Ended AC
82. ut slew Rate Definition Output Slew Rate single ended DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Unit nits Parameter Symbol Min Max Min Max Min Max Min Max Min Max Single ended Output Slew Rate SRQse 2 5 5 2 5 5 2 5 5 2 5 5 25 5 Wns Description SR Slew Rate O Query Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Note 1 In two cases a maximum slew rate of 6V ns applies for a single DO signal within a byte lane Case 1 is a defined for a single DO signal within a byte lane which is switching into a certain direction either from high to low or low to high while all remaining DO signals in the same byte lane are static i e they stay at either high or low Case 2 is a defined for a single DO signal within a byte lane which is switching into a certain direction either from high to low or low to high while all remaining DO signals in the same byte lane switching into the opposite direction i e from low to high of high to low respectively For the remaining DO signal switching in to the opposite direction the regular maximum limite of 5 V ns applies Rev 1 0 Jul 2012 40 SK nix Differential Output Slew Rate With the reference load for timing measurements output slew rate for falling and rising edges is defined and measured between VOLdiff AC and VOHdiff AC for
83. x72 Module 2Rank of x4 pagel lt lt SZ lt 9 2 44 JIE BREE ela e E agg lt H VIS a E 1 Lig p 1 1 1 1 1 DQS17 WY DOS DOS DQS17 v DOS a DOS vss DM M s CB 7 4 DQ 3 0 D17 DQ 3 0 D35 3 3 12818 8 5 peBESssBB DOS12 w Dos DQ512 W DOS VSS DM DQ 31 28 A DQ 3 0 D12 w 1818 sess t DOS DQS DQ 13 01 D30 101218 12 188 5 A N O BA N 0 A N O BA N O DQS11 A DOS DQSII W DOS VSS DM DQI23 20 A DQ 3 0 D11 81251688 Dos DOS DM DQ 3 0 D29 A N O BALN O A N O BALN O 61218 12 x 16 8 5 DQS10 DOS DQS10 DOS VSS DM DQL15 12 A9 DQ 3 0 D10 wesw 5 DOS DQS DQ 3 0 D28 A N O BALN O A N O BALN O 101218 12 188 B DQS0 A DQS DOS0 w Dos VSS pm DQ 3 0 A9 DQ 3 0 DO 1181315838 DOS DQS DQ 3 0 D18 12181 6188 5 A N OJ BA N 0 A N O BALN O vt 34 Rev 1 0 Jul 2012 lt g 8 z sii itii 52222952 t 12 10 2 1 d L L 1 I DQS8 W DOS Dos DQS8 wH DOS pes DOS vss DM DM 9 CB 3 0 AM DO
84. ze 4 4 5 5 nCK DS 2KB page size 5 6 nCK Mac 512Mb 48 60 72 72 nCK Dgrc 1 Gb 59 74 88 88 nCK Marc 2 Gb 86 107 128 128 nCK Marc 4 Gb 139 174 208 208 nCK Marc 8 Gb 187 234 280 280 nCK Table 2 Basic I DD and I DDQ Measurement Conditions Symbol Description Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS CL see Table 1 BL 89 AL 0 CS High between ACT and bpo PRE Command Address Bank Address Inputs partially toggling according to Table 3 Data 10 MID LEVEL DM stable at 0 Bank Activity Cycling with one bank active at a time 0 0 1 1 2 2 see Table 3 Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 3 Operating One Bank Active Precharge Current CKE High External clock On CK nRC nRAS nRCD CL see Table 1 BL 82 AL 0 CS High between ACT bb1 RD and PRE Command Address Bank Address Inputs Data IO partially toggling according to Table 4 DM stable at 0 Bank Activity Cycling with on bank active at a time 0 0 1 1 2 2 see Table 4 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 4 Rev 1 0 J ul 2012 55 SK nix Symbol Description Precharge Standby Current CKE High External clock On tCK CL see Table 1 BL 88 AL 0 CS stable at 1 Command Address Bank bp2N Address Inputs partially toggling a

Download Pdf Manuals

Related Search

Related Contents

  Mode d`emploi  製品安全データシート（MSDS）  70 141 FR  - Eletronika  sts elettronica s.ri.  ConeCtor MPo  

Copyright © All rights reserved. Failed to retrieve file