Elpida 1GB DDR3 1600MHz
Contents
1. Function Active low asynchronous reset Supply voltage for internal circuit Ground for internal circuit Supply voltage for DQ circuit Ground for DQ circuit Reference voltage for DQ Reference voltage for CA Reference pin for ZQ calibration No connection Not usable 78 ball FBGA 1 2 3 7 8 O O O VSS VDD NU TDQS VSS O O O O VSS VSSQ DM TDQS VSSQ VDDQ O O O O VDDQ DQ2 DQ1 DQ3 O O C Q VSSQ DQ6 VDD VSS O O O O VREFDQ VDDQ DQ7 DQ5 O O e O NC VSS CK VSS O e O ODT VDD CK VDD O O NC CS A10 AP ZQ e O O VSS BAO NC VREFCA VSS OC O VDD A3 A12 BC BA1 O O O VSS A5 A1 A4 O O O VDD A7 A6 O O O VSS RESET A8 Top view Pin name Function Pin name Address inputs AO to A13 A10 AP Auto precharge RESET A12 BC Burst chop BAO to BA2 3 Bank select VDD DQ0 to DQ7 Data input output VSS DQS DQS Differential data strobe VDDQ TDQS TDQS Termination data strobe VSSQ ics Chip select VREFDQ IRAS CAS WE Command input VREFCA CKE 3 Clock enable ZQ CK CK Differential clock input Nc DM Write data mask NU ODT ODT control Notes 1 Not internally connected with die 2 Don t connect Internally connected 3 Input only pins address command CKE ODT and RESET do not supply termination Preliminary Data Sheet E1949E11 Ver 1 1 ELPIDA Pin Configurations x 16 configuration xxx indicates active low signal Pin name AO to A12 BAO to BA2 DQUO to DQU7 DQLO t2. 4to7 8 to 11 12 to 15 16 to 19 20 to 23 24 to 27 28 to 31 Com mand CS RAS CAS WE ODT BA D 1 0 0 0 0 D 1 0 0 0 0 ID 1 1 1 1 0 ID 1 1 1 1 0 Ojojo 0 0 0 0 Repeat Sub Loop 0 but ODT 0 and BA 1 Repeat Sub Loop 0 but ODT 0 and BA 4 Repeat Sub Loop 0 but ODT 0 and BA 5 Notes 1 DM must be driven low all the time DQS DQS are MID LEVEL por Iu Preliminary Data Sheet E1949E11 Ver 1 1 DQ signals are MID LEVEL BA BAO to BA2 Am m means Most Significant Bit MSB of Row address 15 A11 Am A10 0 0 0 0 0 0 0 0 A11 Am A10 0 0 0 0 0 0 0 0 A7 A9 Ojojoj jo A7 A9 Oj ojo o 0 D 1 1 1 Repeat Sub Loop 0 use BA 1 instead Repeat Sub Loop 0 use BA 3 instead Repeat Sub Loop 0 use BA 5 instead Repeat Sub Loop 0 use BA 7 instead A3 A0 A6 A2 Data 0 0 0 0 F 0 F 0 A3 A0 A6 A2 Data 0 0 0 0 F 0 F 0 Repeat Sub Loop 0 but ODT 1 and BA 2 Repeat Sub Loop 0 but ODT 1 and BA 3 Repeat Sub Loop 0 but ODT 1 and BA 6 Repeat Sub Loop 0 but ODT 1 and BA 7 ELPIDA Table 11 IDD4R and IDDQ4R Measurement Loop Pattern CK Sub CK CKE Loop 0 Toggling StaticH 1 2 3 4 5 6 7 E ado Preliminary Data Sheet E1949E11 Ver 1 1 Cycle number 6 7 8 to 15 16 to 23 24 to 31 32 to 39 40 to 47 48 to 55 56 to 63 Com mand CS RD 0 D 1 D D 1 RD 0 D 1 D D 1 RAS 1 0 1 1 0
3. stable at 0 bank activity Extended temperature self refresh operation output buffer and RTT enabled in MR ODT signal MID LEVEL TC 0 to 95 C ASR Enabled SRT Normal CKE L External clock off CK and CK L CL Table 5 BL 8 AL 0 CS command address bank address data I O MID LEVEL DM stable at 0 bank activity Auto self refresh operation output buffer and RTT enabled in MR ODT signal MID LEVEL CKE H External clock on tCK nRC nRAS nRCD nRRD nFAW CL see Table 5 BL 8 6 AL CL 1 CS H between ACT and RDA Command address bank address Inputs partially toggling according to Table 14 data I O read data bursts with different data between one burst and the next one according to Table 14 DM stable at 0 bank activity two times interleaved cycling through banks 0 1 7 with different addressing see Table 14 output buffer and RTT enabled in MR ODT signal stable at 0 pattern details see Table 14 RESET low External clock off CK and CK low CKE FLOATING CS command address bank address Data IO FLOATING ODT signal FLOATING RESET low current reading is valid once power is stable and RESET has been low for at least 1ms Burst Length BL8 fixed by MRS MRO bits 1 0 7 0 0 MR Mode Register Output buffer enable set MR1 bit A12 1 and MR1 bits 5 1 0 1 RTT Nom enable set MR1 bits 9 6 2 0 1 1 RTT WR enable set MR2 bits 10 9 1 0
4. 0 4 to 1 975 V 1 3 Power supply voltage for output VDDQ 0 4 to 1 975 V 15 33 Input voltage VIN 0 4 to 1 975 V 1 Output voltage VOUT 0 4 to 1 975 V 1 Reference voltage VREFCA 0 4 to 0 6 x VDD V 3 Reference voltage for DQ VREFDQ 0 4 to 0 6 x VDDQ V 3 Storage temperature Tstg 55 to 100 C 1 2 Power dissipation PD 1 0 W 1 Short circuit output current IOUT 50 mA 1 Notes 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage temperature is the case surface temperature on the center top side of the DRAM 3 VDD and VDDQ must be within 300mV of each other at all times and VREF must be no greater than 0 6 x VDDQ When VDD and VDDQ are less than 500mV VREF may be equal to or less than 300mV Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability 1 2 Operating Temperature Condition Table 2 Operating
5. 1 Command address bank address Inputs partially toggling according to Table 9 data I O MID LEVEL DM stable at 0 bank activity all banks open output buffer and RTT enabled in MR ODT signal stable at 0 pattern details see Table 9 CKE L External clock on tCK CL see Table 5 BL 8 AL 0 CS stable at 1 Command address bank address inputs stable at 0 data I O MID LEVEL DM stable at 0 bank activity all banks open output buffer and RTT enabled in MR ODT signal stable at 0 CKE H External clock on tCK CL see Table 5 BL 8 AL 0 CS H between RD Command address bank address Inputs partially toggling according to Table 11 data I O seamless read data burst with different data between one burst and the next one according to Table 11 DM stable at 0 bank activity all banks open RD commands cycling through banks 0 0 1 1 2 2 see Table 11 Output buffer and RTT enabled in MR ODT signal stable at O pattern details see Table 11 Same definition like for IDDAR however measuring IDDQ current instead of IDD current ELPIDA 11 EDJ1108EJBG EDJ1116EJBG Table 6 Basic IDD and IDDQ Measurement Conditions cont d Parameter Symbol Operating burst write current IDD4W Burst refresh current IDD5B Self refresh current normal IDD6 temperature range Self refresh current extended IDDGET temperature range Auto self refresh current IDD6TC Optional Operating b
6. Maximum DC value may not be greater than 1 425V The DC value is the linear average of VDD VDDQ t over a very long period of time e g 1 sec If maximum limit is exceeded input levels shall be governed by DDR3 specifications Under these supply voltages the device operates to this DDR3L specifcation Once initialized for DDR3L operation DDR3 operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3 operation shown as following timing wave form ARB Ie Table 4 Recommended DC Operating Conditions TC 0 C to 85 C DDR3 Operation Parameter Symbol min typ max Unit Notes Supply voltage VDD 1 425 1 5 1 575 V 1 2 3 Supply voltage for DQ VDDQ 1 425 1 5 1 575 V 1 2 3 Notes 1 If minimum limit is exceeded input levels shall be governed by DDR3L specifications 2 Under 1 5V operation this DDR3L device operates to the DDR3 specifcations under the same speedtimings as defined for this device 3 Once initialized for DDR3 operation DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3L operation shown as below VDD VDDQ DDR3 VDD VDDQ DDR3L RESET T min 10ns v y er L 7 QU UZ YW BW IN QU Nata X2 tDLLK EN CKE as us tXPR tMRD tMRD tMRD tMOD tZQinit Command ZOCO AMD cese XC XD GC BA a B dp ye 9 ED A 2222 722220 9 DA tIS tIS lt gt ODT SMA su low in case RTT_Nore is enabled at time Tg otherwise stati
7. Precharge power down mode set MRO bit A12 0 for Slow Exit or MRO bit A12 1 for fast exit Auto self refresh ASR set MR2 bit A6 0 to disable or 1 to enable feature Self refresh temperature range SRT set MRO bit A7 0 for normal or 1 for extended temperature range Read burst type nibble sequential set MRO bit A3 0 Preliminary Data Sheet E1949E11 Ver 1 1 ELPIDA 12 EDJ1108EJBG EDJ1116EJBG Table 7 IDDO Measurement Loop Pattern CK ICK Sub CKE Loop Toggling Static H Notes 1 Pm p I Preliminary Data Sheet E1949E11 Ver 1 1 Cycle number 0 1 2 3 4 nRAS 1 x nRC 0 1 x nRC 11 2 3 4 1 x nRC nRAS A11 Am A10 A7 A9 Com mand CS RAS CAS WE ODT BA D D 1 0 0 0 0 0 0 0 Repeat pattern 1 4 until nRAS 1 truncate if necessary Repeat pattern 1 4 until nRC 1 truncate if necessary ACT 0 0 1 1 0 0 0 0 0 D D 1 0 0 0 0 0 0 0 0 D D 1 1 1 1 0 0 0 0 0 ACT 0 0 1 1 0 0 0 0 0 0 D D 1 1 1 1 0 0 0 0 0 0 PRE 0 0 1 0 0 0 0 0 0 1 x nRC Repeat pattern nRC 1 4 until 1 x nRC nRAS 1 truncate if necessary PRE 0 0 1 0 0 0 0 0 0 A3 AO A6 A2 Data 0 0 0 0 0 F 0 F 0 F 0 F 0 Repeat nRC 1 4 until 2 x nRC 1 truncate if necessary oO on AJOJN gt 7 2 x nRC 4 x nRC 6 x nRC 8 x nRC 10 x nRC 12 x nRC 14 x nRC Repeat Sub Loop 0 use BA 1 instead DM must be driven low all the time D
8. Temperature Condition Parameter Symbol Rating Unit Notes Operating case temperature TC 0 to 95 C 1 2 3 Notes 1 Operating temperature is the case surface temperature on the center top side of the DRAM 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported During operation the DRAM case temperature must be maintained between 0 C to 85 C under all operating conditions 3 Some applications require operation of the DRAM in the Extended Temperature Range between 85 C and 95 C case temperature Full specifications are guaranteed in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the refresh interval tREFI to 3 9us This double refresh requirement may not apply for some devices b If Self refresh operation is required in the Extended Temperature Range then it is mandatory to either use the Manual Self Refresh mode with Extended Temperature Range capability MR2 bit A6 A7 0 1 or enable the optional Auto Self Refresh mode MR2 bit A6 A7 1 0 Preliminary Data Sheet E1949E11 Ver 1 1 ELPIDA EDJ1108EJBG EDJ1116EJBG 13 Recommended DC Operating Conditions Table 3 Recommended DC Operating Conditions TC 0 C to 85 C DDR3L Operation Parameter Symbol min typ max Unit Notes Supply voltage VDD 1 283 1 35 1 45 V 1 2 3 4 Supply voltage for DQ VDDQ 1 283 1 35 1 45 V 1 2 3 4 Notes 1
9. current 1866 TBD TBD brach WS 1333 30 30 recnarge quiet standby SDDOO 1600 30 30 mA current 1866 TBD TBD Acti d i 1333 25 25 ctive power own curren IDD3P 1600 25 26 MA Always fast exit 1866 TBD TBD 1333 40 40 Active standby current IDD3N 1600 45 45 mA 1866 TBD TBD O ii i 1333 90 105 O IDD4R 1600 105 120 mA Burst read operating 1866 TBD TBD O i i 1333 100 135 iain DM IDD4W 1600 115 155 mA Burst write operating 1866 TBD TBD 1333 135 135 Burst refresh current IDD5B 1600 140 140 mA 1866 TBD TBD Albanke d 1333 160 165 M d AS IDD7 1600 160 190 mA current 1866 TBD TBD RESET low current IDD8 10 10 mA Preliminary Data Sheet E1949E11 Ver 1 1 ELPIDA 19 EDJ1108EJBG EDJ1116EJBG Table 16 Self Refresh Current TC 0 C to 85 C VDD VDDQ 1 283V to 1 45V Parameter Symbol Self refresh current IDD6 normal temperature range Self refresh current IDDGET extended temperature range Auto self refresh current IDD6TC Optional Preliminary Data Sheet E1949E11 Ver 1 1 max 10 12 20 Unit Notes mA mA mA ELPIDA EDJ1108EJBG EDJ1116EJBG 2 2 Pin Capacitance Table 17 Pin Capacitance DDR3 800 to 1600 TC 25 C VDD VDDQ 1 283V to 1 45V DDR3L 800 DDR3L 1066 DDR3L 1333 DDR3L 1600 Parameter Symbol Min Max Min Max Min Max Min Max Units Notes Input outputcapacitance CIO 1 4 2 5 1 4 2 5 1 4 2 3 1 4 2 2 pF 1 2 Input capacitance CK and CK CCK 0 8 1 6 0 8 1 6 0 8 1 4 0 8 1 4 pF 2 Input cap
10. driven low all the time DQS DQS are MID LEVEL DQ signals are MID LEVEL BA BAO to BA2 Am m means Most Significant Bit MSB of Row address Com mand CS REF 0 0 Repeat cycles 1 Repeat cycles 1 Repeat cycles 1 Repeat cycles 1 Repeat Sub Loop 1 until nRFC 1 Truncate if necessary 0 1 0 0 1 1 4 but BA 1 4 but BA 2 4 but BA 3 4 but BA 4 4 but BA 5 4 but BA 6 4 but BA 7 17 EDJ1108EJBG EDJ1116EJBG ODT BA 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 A11 Am A10 OcO ojoj o joi o A11 RAS CAS WE ODT BA Am A10 0 D 1 0 0 D D 1 1 0 Ojojojoj jo 0 0 0 A9 O ojojo joi o ID D 00110011 A3 A0 A6 A2 Data O 0 00000000 0 0 0 0 F 0 F 0 F 0 Repeat Sub Loop 0 but BA 1 Repeat Sub Loop 0 but BA 3 Repeat Sub Loop 0 but BA 4 Repeat Sub Loop 0 but BA 5 Repeat Sub Loop 0 but BA 6 Repeat Sub Loop 0 but BA 7 DM must be driven low all the time DQS DQS are used according to write commands otherwise MID LEVEL Burst sequence driven on each DQ signal by write command Outside burst operation DQ signals are MID LEVEL BA BAO to BA2 Am m means Most Significant Bit MSB of Row address A7 A3 AO A9 A6 A2 Data 0 0 0 0 0 0 0 F 0 Repeat cycles 1 Repeat cycles 1 Repeat cycles 1 ELPIDA EDJ1108EJBG EDJ1116EJBG Table 14 IDD7 Measurement Loop Patter
11. if necessary Oo BR ws NM gt 7 2xnRC 4xnRC 6xnRC 8 x NRC 10 x nRC 12 x nRC 14 x nRC Repeat Sub Loop 0 use BA 1 instead Repeat Sub Loop 0 use BA 2 instead Repeat Sub Loop 0 use BA 3 instead Repeat Sub Loop 0 use BA 4 instead Repeat Sub Loop 0 use BA 5 instead Repeat Sub Loop 0 use BA 6 instead Repeat Sub Loop 0 use BA instead DM must be driven low all the time DQS DQS are used according to read commands otherwise MID LEVEL Burst sequence driven on each DQ signal by read command Outside burst operation DQ signals are MID LEVEL BA BAO to BA2 Am m means Most Significant Bit MSB of Row address ELPIDA 14 EDJ1108EJBG EDJ1116EJBG Table 9 IDD2N and IDD3N Measurement Loop Pattern CK Sub CK CKE Loop Toggling Static H OO BR wy NON gt 7 Cycle number 0 1 2 3 4to7 8 to 11 12 to 15 16 to 19 20 to 23 24 to 27 28 to 31 Com mand CS RAS CAS WE ODT BA D 1 0 0 0 0 D 1 0 0 0 1 1 0 D 1 1 1 0 Repeat Sub Loop 0 use BA 2 instead Repeat Sub Loop 0 use BA 4 instead Repeat Sub Loop 0 use BA 6 instead Notes 1 DM must be driven low all the time DQS DQS are MID LEVEL a DQ signals are MID LEVEL BA BAO to BA2 Am m means Most Significant Bit MSB of Row address Table 10 IDD2NT and IDDQ2NT Measurement Loop Pattern CK Sub CK CKE Loop Toggling Static H Oo oo BR W NM gt 7 Cycle number 0 1 2 3
12. lower SPD settings must be programmed to match DDR3 800 AC timing apply if DRAM operates at lower than 800 MT s data rate Preliminary Data Sheet E1949E11 Ver 1 1 ELPIDA 2 EDJ1108EJBG EDJ1116EJBG 3 Package Drawing 3 1 78 ball FBGA Solder ball Lead free Sn Ag Cu Unit mm 7 50 0 10 ds INDEX MARK O S I E NEN O 0 10 S 0 35 0 05 BH 78 0 45 0 05 4 0 15 M S A B OOO OOO 0100 OOO OOO A OOO 0 6 0 OOO OOO 000 OOO OQ oO Qoo A INDEX MARK ECA TS2 0383 01 Preliminary Data Sheet E1949E11 Ver 1 1 ELPIDA 28 EDJ1108EJBG EDJ1116EJBG 3 2 96 ball FBGA Solder ball Lead free Sn Ag Cu Unit mm 50 0 1 oes 0 20 S B INDEX MARK 13 50 0 10 0 20 S INDEX MARK ECA TS2 0384 01 Preliminary Data Sheet E1949E11 Ver 1 1 ELPIDA 29 EDJ1108EJBG EDJ1116EJBG 4 Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the 1G bits DDR3 SDRAM Type of Surface Mount Device EDJ1108EJBG 78 ball FBGA lt Lead free Sn Ag Cu gt EDJ1116EJBG 96 ball FBGA lt Lead free Sn Ag Cu gt Preliminary Data Sheet E1949E11 Ver 1 1 ELPIDA 30 EDJ1108EJBG EDJ1116EJBG NOTES FOR CMOS DEVICES D PRECAUTION AGAINST ESD FOR MO
13. nFAW 2 x nRRD 1 Repeat Sub Loop 10 but BA 2 Repeat Sub Loop 11 but BA 3 D 1 0 0 0 0 3 0 0 0 0 0 Assert and repeat above D Command until 3 x nFAW 1 if necessary Repeat Sub Loop 10 but BA 4 Repeat Sub Loop 11 but BA 5 Repeat Sub Loop 10 but BA 6 Repeat Sub Loop 11 but BA 7 D 1 0 0 0 0 7 0 0 0 0 0 Assert and repeat above D Command until 4 x nFAW 1 if necessary A9 A6 A2 Data 00000000 00110011 00110011 00000000 DM must be driven low all the time DQS DQS are used according to read commands otherwise MID LEVEL Burst sequence driven on each DQ signal by read command Outside burst operation DQ signals are MID LEVEL BA BAO to BA2 Am m means Most Significant Bit MSB of Row address Preliminary Data Sheet E1949E11 Ver 1 1 ELPIDA 18 EDJ1108EJBG EDJ1116EJBG 2 Electrical Specifications 2 1 DC Characteristics Table 15 DC Characteristics 1 TC 0 C to 85 C VDD VDDQ 1 283V to 1 45V Data rate x8 x 16 Parameter Symbol Mbps max max Unit Notes Operating current ids iis ACT PRE IDDO 1600 52 60 mA 1866 TBD TBD Operating current e jn n ACT RD PRE IDD1 1600 65 15 mA 1866 TBD TBD 1333 20 20 IDD2P1 1600 20 20 mA Fast PD Exit Precharge power down 1866 TBD TBD standby current 1333 10 10 IDD2PO 1600 10 10 mA Slow PD Exit 1866 TBD TBD 1333 30 30 Precharge standby current IDD2N 1600 30 30 mA 1866 TBD TBD Prech 1333 30 30 M eee IDD2NT 1600 32 32 mA ODT
14. 1 CAS 0 Oo ol o ANE O a O 1 Repeat Sub Loop 0 but BA 1 Repeat Sub Loop 0 but BA 2 Repeat Sub Loop 0 but BA 3 Repeat Sub Loop 0 but BA 4 Repeat Sub Loop 0 but BA 5 Repeat Sub Loop 0 but BA 6 Repeat Sub Loop 0 but BA 7 Notes 1 DM must be driven low all the time DQS DQS are used according to read commands otherwise MID LEVEL 16 EDJ1108EJBG EDJ1116EJBG ODT BA 0 0 0 0 0 0 0 0 0 0 0 0 A11 Am A10 OcO ojoj o joi o Ojojojoj jo A9 O ojojo joi o A3 A0 A6 A2 Data O 0 00000000 0 0 0 0 F 0 00110011 F 0 F 0 x Burst sequence driven on each DQ signal by read command Outside burst operation DQ signals are MID LEVEL BA BAO to BA2 Am m means Most Significant Bit MSB of Row address ELPIDA Table 12 IDD4W Measurement Loop Pattern CK Sub CK CKE Loop 0 Toggling StaticH 1 2 3 4 5 6 7 Notes 1 oie Cycle number 6 7 8 to 15 16 to 23 24 to 31 32 to 39 40 to 47 48 to 55 56 to 63 Com mand CS RAS CAS WE WR 0 1 0 0 D 1 0 0 0 1 1 1 1 WR 0 1 0 0 D 1 0 0 0 D D 1 1 1 1 Repeat Sub Loop 0 but BA 2 Table 13 IDD5B Measurement Loop Pattern CK ICK CKE Toggling Static H Notes 1 PPT Preliminary Data Sheet E1949E11 Ver 1 1 Sub Loop 1 2 Cycle number 0 1 2 3 4 5 to 8 9 to 12 13 to 16 17 to 20 21 to 24 25 to 28 29 to 32 33 to nRFC 1 DM must be
15. 1116EJBG Speed Bin DDR3 1600K CL tRCD tRP 11 11 11 Symbol CAS write latency min max Unit Notes tAA dd 5 20 ns 10 tRCD ee 5 ns 10 tRP i s 5 ns 10 tRC ae 5 ns 10 tRAS 35 9 x tREFI ns 9 tCK avg CL 5 CWL 5 3 0 3 3 ns 1 2 3 4 7 11 CWL 6 7 8 Reserved Reserved ns 4 tCK avg CL 6 CWL 5 2 5 3 3 ns 12 37 CWL 6 Reserved Reserved ns 4 CWL 7 8 Reserved Reserved ns 4 tCK avg CL 7 CWL 5 Reserved Reserved ns 4 CWL 6 1 875 lt 2 5 ns 1 2 3 4 7 CWL 7 Reserved Reserved ns 4 CWL 8 Reserved Reserved ns 4 tCK avg CL 8 CWL 5 Reserved Reserved ns 4 CWL 6 1 875 lt 2 5 ns 1 2 3 7 CWL 7 Reserved Reserved ns 4 CWL 8 Reserved Reserved ns 4 tCK avg CL 9 CWL 5 6 Reserved Reserved ns 4 CWL 7 1 5 1 875 ns 1 2 3 4 7 CWL 8 Reserved Reserved ns 4 tCK avg CL 10 CWL 5 6 Reserved Reserved ns 4 CWL 7 1 5 lt 1 875 ns 1 2 3 7 CWL 8 Reserved Reserved ns 4 tCK avg CL 11 CWL 5 6 7 Reserved Reserved ns 4 CWL 8 1 25 lt 1 5 ns 1 2 3 Supported CL settings 5 6 7 8 9 10 11 nCK Supported CWL settings 5 6 7 8 nCK ELPIDA Preliminary Data Sheet E1949E11 Ver 1 1 25 Table 23 DDR3 1866 Speed Bins Speed Bin CL tRCD tRP Symbol CAS write latency tAA tRCD tRP tRC tRAS tCK avg CL 5 CWL 5 CWL 6 7 8 9 tCK avg CL 6 CWL 5 CWL 6 CWL 7 8 9 tCK avg CL 7 CWL 5 CWL 6 CWL 7 8 9 tCK avg CL 8 CWL 5 CWL 6 CWL 7 CWL 8 9 tCK avg CL 9 CWL 5 6 CWL 7 CWL 8 CWL 9 tCK avg C
16. 3 13 96 ball FBGA EDJ1116EJBG GN F J 64M x 16 8 DDR3L 1600K 11 11 11 EDJ1116EJBG DJ F DDR3L 1333H 9 9 9 Note 1 Please refer to the EDJ1108DJBG EDJ1116DJBG datasheet E1729E when using this device at 1 5V operation unless stated otherwise Part Number EDJ1108EJBG JS F Elpida Memory Type D Packaged Device Environment code F Lead Free RoHS compliant and Halogen Free Product Family J DDR3 Density Bank 11 1Gb 8 bank TTT Speed JS DDR3 1866M 13 13 13 GN DDR3 1600K 11 11 11 DJ DDR3 1333H 9 9 9 Organization 08 x8 16 x16 Package BG FBGA Power Supply Die Rev E 1 35V Operating Frequency Frequency Mbps Speed speed bin Grade CL5 CL6 CL7 CL8 CL9 CL10 CL11 CL13 CL tRCD tRP DDR3L 1866 1 JS 667 800 1066 1066 1333 1333 1600 866 13 13 13 GN 667 800 1066 1066 1333 1333 1600 podio 11 11 11 DJ 667 800 1066 1066 1333 1333 P pm Detailed Information For detailed electrical specification and further information please refer to the DDR3L SDRAM General Functionality and Electrical Condition data sheet E1927E and Addendum data sheet E1928E Preliminary Data Sheet E1949E11 Ver 1 1 ELPIDA Pin Configurations Pin Configurations x8 configuration xxx indicates active low signal EDJ1108EJBG EDJ1116EJBG 9 O VDD O O VSSQ O VSSQ O VDDQ O NC O CKE O NC O VDD O VSS O VDD O VSS
17. 50 625 ns 10 tRAS 37 5 9 x tREFI ns 9 tCK avg CL 5 CWL 5 3 0 33 ns 1 2 3 4 5 11 CWL 6 Reserved Reserved ns 4 tCK avg CL 6 CWL 5 2 5 3 3 ns 1 2 3 5 CWL 6 Reserved Reserved ns 4 tCK avg CL 7 CWL 5 Reserved Reserved ns 4 CWL 6 1 875 2 5 ns 1 2 3 4 tCK avg CL 8 CWL 5 Reserved Reserved ns 4 CWL 6 1 875 lt 2 5 ns 1 2 3 Supported CL settings 5 6 7 8 nCK Supported CWL settings 5 6 nCK Preliminary Data Sheet E1949E11 Ver 1 1 23 ELPIDA Table 21 DDR3 1333 Speed Bins EDJ1108EJBG EDJ1116EJBG Speed Bin DDR3 1333H CL tRCD tRP 9 9 9 Symbol CASwrritelatency min max Unit Notes tAA nom 20 ns 10 tRCD en ns 10 tRP 25 ns 10 tRC VM ns 10 tRAS 36 9 x tREFI ns 9 tCK avg CL 5 CWL 5 3 0 3 0 ns 1 2 3 4 6 11 CWL 6 7 Reserved Reserved ns 4 tCK avg CL 6 CWL 5 2 5 3 3 ns 1 2 3 6 CWL 6 Reserved Reserved ns 4 CWL 7 Reserved Reserved ns 4 tCK avg CL 7 CWL 5 Reserved Reserved ns 4 CWL 6 1 875 lt 2 5 ns 1 2 3 4 6 CWL 7 Reserved Reserved ns 4 tCK avg CL 8 CWL 5 Reserved Reserved ns 4 CWL 6 1 875 2 5 ns 1 2 3 6 CWL 7 Reserved Reserved ns 4 tCK avg CL 9 CWL 5 6 Reserved Reserved ns 4 CWL 7 1 5 lt 1 875 ns 1 2 3 4 tCK avg CL 10 CWL 5 6 Reserved Reserved ns 4 CWL 7 1 5 lt 1 875 ns 1 2 3 Supported CL settings 5 6 7 8 9 10 nCK Supported CWL settings 5 6 7 nCK ELPIDA Preliminary Data Sheet E1949E11 Ver 1 1 24 Table 22 DDR3 1600 Speed Bins EDJ1108EJBG EDJ
18. ELPIDA PRELIMINARY DATA SHEET 1G bits DDR3L SDRAM EDJ1108EJBG 128M words x 8 bits EDJ1116EJBG 64M words x 16 bits Features Specifications Density 1G bits Organization 16M words x 8 bits x 8 banks EDJ1108EJBG 8M words x 16 bits x 8 banks EDJ1116EJBG e Package 78 ball FBGA EDJ1108EJBG 96 ball FBGA EDJ1116EJBG Lead free RoHS compliant and Halogen free Power supply 1 35V typ VDD 1 283V to 1 45V Backward compatible for VDD VDDQ 1 5V 0 075V e Data rate 1866Mbps 1600Mbps 1333Mbps max 1KB page size EDJ1108EJBG Row address AO to A13 Column address AO to A9 e 2KB page size EDJ1116EJBG Row address AO to A12 Column address AO to A9 e Eight internal banks for concurrent operation Burst length BL 8 and 4 with Burst Chop BC Burst type BT Sequential 8 4 with BC Interleave 8 4 with BC CAS Latency CL 5 6 7 8 9 10 11 13 CAS Write Latency CWL 5 6 7 8 9 Precharge auto precharge option for each burst access Driver strength RZQ 7 RZQ 6 RZQ 24012 Refresh auto refresh self refresh Refresh cycles Average refresh period 7 8us at 0 C lt TC lt 85 C 3 9us at 85 C lt TC lt 95 C Operating case temperature range TC 0 C to 95 C Document No E1949E11 Ver 1 1 Date Published September 2012 K Japan Printed in Japan URL http www elpida com Do
19. L 10 CWL 5 6 CWL 7 CWL 8 tCK avg CL 11 CWL 5 6 7 CWL 8 CWL 9 tCK avg CL 12 CWL 5 6 7 8 CWL 9 tCK avg CL 13 CWL 5 6 7 8 CWL 9 Supported CL settings Supported CWL settings Preliminary Data Sheet E1949E11 Ver 1 1 DDR3 1866M 13 13 13 min 13 91 13 91 13 91 47 91 34 0 3 0 Reserved 2 5 Reserved Reserved Reserved 1 875 Reserved Reserved 1 875 Reserved Reserved Reserved 1 5 Reserved Reserved Reserved 1 5 Reserved Reserved 1 25 Reserved Reserved Reserved Reserved 1 07 26 max 20 0 9 x tREFI 3 3 Reserved 9 9 Reserved Reserved Reserved 2 5 Reserved Reserved 2 5 Reserved Reserved Reserved 1 875 Reserved Reserved Reserved 1 875 Reserved Reserved 1 5 Reserved Reserved Reserved Reserved 1 25 5 6 7 8 9 10 11 13 5 6 7 8 9 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK EDJ1108EJBG EDJ1116EJBG Notes ELPIDA Notes 1 2 11 EDJ1108EJBG EDJ1116EJBG The CL setting and CWL setting result in tCK avg min and tCK avg max requirements When making a selection of tCK avg both need to be fulfilled Requirements from CL setting as well as requirements from CWL setting tCK avg min limits Since CAS latency is not purely analog data and strobe output are synchronized by the DLL all possible intermediate frequencies may not be guaranteed An appli
20. QS DQS are MID LEVEL DQ signals are MID LEVEL BA BAO to BA2 Am m means Most Significant Bit MSB of Row address 13 Repeat Sub Loop 0 use BA 2 instead Repeat Sub Loop 0 use BA 3 instead Repeat Sub Loop 0 use BA 4 instead Repeat Sub Loop 0 use BA 5 instead Repeat Sub Loop 0 use BA 6 instead Repeat Sub Loop 0 use BA instead ELPIDA EDJ1108EJBG EDJ1116EJBG Table 8 IDD1 Measurement Loop Pattern CK ICK Sub CKE Loop Toggling Static H Notes 1 E TS Preliminary Data Sheet E1949E11 Ver 1 1 Cycle number 0 1 2 3 4 nRCD nRAS 1 x nRC 0 1 2 3 4 1 xnRC nRCD 1 xnRC nRAS A11 A7 AO CS RAS CAS WE ODT BA Am A10 A9 A2 Data ACT 0 0 1 1 0 0 0 0 0 0 0 D D 1 0 0 0 0 0 0 0 0 Com A3 mand D D 1 1 1 1 0 0 0 0 0 0 0 Repeat pattern 1 4 until nRCD 1 truncate if necessary RD 0 1 0 1 0 0 0 0 0 0 0 00000000 Repeat pattern 1 4 until nRAS 1 truncate if necessary PRE 0 0 1 0 0 0 0 0 0 0 O Repeat pattern 1 4 until nRC 1 truncate if necessary ACT 0 0 1 1 0 0 0 0 0 F O CI Bg 4 o o o 38 oo amp 9 o F 0 MRC DjiD4 1 1 1 0 0 0 0 0 F 0 Repeat pattern nRC 1 4 until nRC nRCD 1 truncate if necessary RD 0 1 0 1 0 0 0 0 0 F O 00110011 7 Repeat pattern nRC 1 4 until nRC nRAS 1 truncate if necessary PRE 0 0 1 0 0 0 0 0 0 F 0 i Repeat pattern nRC 1 4 until 2 x nRC 1 truncate
21. S DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when once it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity MOS devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap MOS devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor MOS devices on it 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to Vo or GND with a resistor if it is considered to have a possibility of being an output pin The unused pins must be handled in accordance with the related s
22. Ver 1 1 ELPIDA EDJ1108EJBG EDJ1116EJBG CONTENTS ve lef Te 672 USAS torta 1 BS Sse seed 1 o A 2 A 2 Operating Frequentes 2 Detailed Informatio ur es 2 PIO II AN UNS te SEE 3 le Elecmical Condos ac ic 6 1 1 Absolute Maxim m Ratings seis diodes ibid 6 1 2 Operating Temperature Condition oooccccccccncccncnconnnncccncnnonocononannnononnnnnnnnnnonanononnnnnnnnnnnnnnnnnnnnnnos 6 1 3 Recommended DC Operating Conditions occcccoocccnccnnnnnnccnnncnnnononccnnnnnncnnnonnnrnnnonnnnnnnonnnrnnnonnanennss 7 1 4 IDD and IDDQ Measurement Conditions ooocccccccnnccconnncconcncnoncnononccnnnnnonononnnonnnnnnonnenonnnenenoneness 8 2 Electrical Specifications errata ccoo Idee Rain 19 2 1 SA AC Ce ISS TN EU 19 2 2 qe o AP A 21 29 Standard Speed BINS NT m 23 3 Fackage DIAWING ER m m m 28 3 1 TODO PDA oracion 28 3 2 LGA nn 29 4 Recommended Soldering Conditions c occcocccconcconccccnononononcnononnnnonanonononanonanonarnnannnnnnnnanenaninos 30 Preliminary Data Sheet E1949E11 Ver 1 1 ELPIDA EDJ1108EJBG EDJ1116EJBG 1 Electrical Conditions All voltages are referenced to VSS GND Execute power up and Initialization sequence before proper device operation is achieved 1 1 Absolute Maximum Ratings Table 1 Absolute Maximum Ratings Parameter Symbol Rating Unit Notes Power supply voltage VDD
23. acitance delta CK and CK CDCK 0 0 15 0 0 15 0 0 15 0 0 15 pF 2 3 Input output capacitance delta CDDQS 0 0 2 0 0 2 0 0 15 0 0 15 pF 2 4 DQS and DQS Input capacitance coniro address Cl 0 75 1 3 0 75 13 075 13 0 75 12 pF 2 5 command input only pins Input capacitance delta All control input only CDI CTRL 0 5 0 3 0 5 0 3 0 4 0 2 0 4 0 2 pF 2 6 7 pins Input capacitance delta CDI ADD All addres command CMD 0 5 0 5 0 5 0 5 0 4 0 4 0 4 0 4 pF 2 8 9 input only pins Input output capacitance delta DQ DM DQS CDIO 0 5 0 3 0 5 0 3 0 5 0 3 0 5 0 3 pF 2 10 DQS TDQS TDQS Input output capacitance o of ZQ pin CZQ 3 3 3 3 pF 2 11 Table 18 Pin Capacitance DDR3 1866 to 2133 TC 25 C VDD VDDQ 1 283V to 1 45V DDR3L 1866 Parameter Symbol Min Max Units Notes Input output capacitance CIO 1 4 2 1 pF 1 2 Input capacitance CK and CK CCK 0 8 1 3 pF 2 Input capacitance delta CK and CK CDCK 0 0 15 pF 2 3 Input output capacitance delta DQS and DQS CDDQS 0 0 15 pF 2 4 Input capacitance control address command input CI 0 75 1 2 pF 2 5 only pins Input capacitance celle CDI CTRL 0 4 0 2 pF 2 6 7 All control input only pins Input capacitance delta All CDI ADD CMD 0 4 04 pF 2 8 9 addres command input only pins Input output capacitance delta E DQ DM DOS DQS TDas rbas P O ve i pF erm Input output capacitance of ZQ pin CZQ 3 pF 2 11 Notes 1 Although t
24. ank interleave IDD7 read current RESET low current IDD8 Notes 1 2 27 91 to Description CKE H External clock on tCK CL see Table 5 BL 8 1 AL 0 CS H between WR command address bank address inputs partially toggling according to Table 12 data I O seamless write data burst with different data between one burst and the next one according to IDD4W Measurement Loop Pattern table DM stable at 0 bank activity all banks open WR commands cycling through banks 0 0 1 1 2 2 see Table 12 Output buffer and RTT enabled in MR ODT signal stable at H pattern details see Table 12 CKE H External clock on tCK CL nRFC see Table 5 BL 8 1 AL 0 CS H between REF Command address bank address Inputs partially toggling according to Table 13 data I O MID LEVEL DM stable at 0 bank activity REF command every nRFC Table 13 output buffer and RTT enabled in MR ODT signal stable at 0 pattern details see Table 13 TC 0 to 85 C ASR disabled SRT Normal CKE L External clock off CK and CK L CL see Table 5 BL 8 AL 0 CS command address bank address data I O MID LEVEL DM stable at 0 bank activity Self refresh operation output buffer and RTT enabled in MR ODT signal MID LEVEL TC 0 to 95 C ASR Disabled SRT Extended CKE L External clock off CK and CK L CL Table 5 BL 8 AL 0 CS command address bank address data I O MID LEVEL DM
25. c high or low VIH or VIL Note 1 From time point Td until Tk NOP or DES commands must be applied between MRS and ZQCL commands Figure 1 VDD VDDQ Voltage Switch between DDR3L and DDR3 Preliminary Data Sheet E1949E11 Ver 1 1 ELPIDA EDJ1108EJBG EDJ1116EJBG 1 4 IDD and IDDQ Measurement Conditions In this chapter IDD and IDDQ measurement conditions such as test load and patterns are defined The figure Measurement Setup and Test Load for IDD and IDDQ Measurements shows the setup and test load for IDD and IDDQ measurements IDD currents such as IDDO IDD1 IDD2N IDD2NT IDD2PO IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDDAW IDD5B IDD6 IDD6ET IDD6TC and IDD7 are measured as time averaged currents with all VDD balls of the DDR3 SDRAM under test tied together Any IDDQ current is not included in IDD currents IDDQ currents such as IDDQ2NT and IDDQ4R are measured as time averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together Any IDD current is not included in IDDQ currents Note IDDQ values cannot be directly used to calculate I O power of the DDR3 SDRAM They can be used to support correlation of simulated I O power to actual I O power as outlined in correlation from simulated channel I O power to actual channel I O power supported by IDDQ measurement For IDD and IDDQ measurements the following definitions apply e Land 0 VIN lt VIL AC max e Hand 1 VIN gt VIH AC min MID LEVEL defin
26. cation should use the next smaller JEDEC standard tCK avg value 3 0 2 5 1 875 1 5 or 1 25ns when calculating CL nCK tAA ns tCK avg ns rounding up to the next Supported CL tCK avg max limits Calculate tCK avg tAA max CL selected and round the resulting tCK avg down to the next valid speed bin i e 3 3ns or 2 5ns or 1 875ns or 1 25ns This result is tCK avg max corresponding to CL selected Reserved settings are not allowed User must program a different value Any DDR3 1066 speed bin also supports functional operation at lower frequencies as shown in the table DDR3 1066 Speed Bins which are not subject to production tests but verified by design characterization Any DDR3 1333 speed bin also supports functional operation at lower frequencies as shown in the table DDR3 1333 Speed Bins which is not subject to production tests but verified by design characterization Any DDR3 1600 speed bin also supports functional operation at lower frequencies as shown in the table DDR3 1600 Speed Bins which is not subject to production tests but verified by design characterization Any DDR3 1866 speed bin also supports functional operation at lower frequencies as shown in the table DDR3 1866 Speed Bins which is not subject to production tests but verified by design characterization tREFI depends on operating case temperature TC For devices supporting optional down binning to CL 7 and CL 9 tAA tRCD tRP min must be 13 125 ns or
27. de registers ODT signal stable at 0 pattern details see Table 9 CKE H External clock on tCK CL see Table 5 BL 8 AL 0 CS stable at 1 Command address bank address Inputs partially toggling according to Table 10 data I O MID LEVEL DM stable at 0 bank activity all banks closed output buffer and RTT enabled in MR ODT signal toggling according to Table 10 pattern details see Table 10 Same definition like for IDD2NT however measuring IDDQ current instead of IDD current CKE L External clock on tCK CL see Table 5 BL 8 AL 0 CS stable at 1 Command address bank address inputs stable at 0 data I O MID LEVEL DM stable at 0 bank activity all banks closed output buffer and RTT EMR ODT signal stable at 0 precharge power down mode slow exit CKE L External clock on tCK CL see Table 6 BL 8 AL 0 CS stable at 1 Command address bank address Inputs stable at 0 data I O MID LEVEL DM stable at 0 bank activity all banks closed output buffer and RTT enabled in MR 2 ODT signal stable at 0 precharge power down mode fast exit CKE H External clock On tCK CL see Table 5 BL 8 AL 0 CS stable at 1 Command address bank address Inputs stable at 0 data I O MID LEVEL DM stable at 0 bank activity all banks closed output buffer and RTT enabled in MR ODT signal stable at 0 CKE H External clock on tCK CL see Table 5 BL 8 AL 0 CS stable at
28. ed as inputs are VREF VDDQ 2 FLOATING don t care or floating around VREF Timings used for IDD and IDDQ measurement loop patterns are provided in Timings used for IDD and IDDQ Measurement Loop Patterns table Basic IDD and IDDQ measurement conditions are described in Basic IDD and IDDQ Measurement Conditions table Note The IDD and IDDQ measurement loop patterns need to be executed at least one time before actual IDD or IDDQ measurement is started Detailed IDD and IDDQ measurement loop patterns are described in IDDO Measurement Loop Pattern table through IDD7 Measurement Loop Pattern table IDD Measurements are done after properly initializing the DDR3 SDRAM This includes but is not limited to setting RON RZQ 7 34Q in MR1 Qoff OB Output Buffer enabled in MR1 RTT Nom RZQ 6 402 in MR1 RIT WR RZQ 2 120Q in MR2 TDQS Feature disabled in MR Define D CS RAS CAS WE H L L L Define D CS RAS CAS WE H H H H Preliminary Data Sheet E1949E11 Ver 1 1 ELPIDA EDJ1108EJBG EDJ1116EJBG o RESET o CK CK DDR3 SDRAM DQS DQS RTT 250 A DQ DM ke VDDQ OT CS O RAS CAS WE o 4 Address BA o ODT o ZQ TDQS TDQS VSS Figure 2 Measurement Setup and Test Load for IDD and IDDQ Measurements Application specific memory channel IDDQ environment Test load Channel I O power simulation Correlation Correction Channel I O power nu
29. ed characteristics Elpida Memory Inc bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions Even within the guaranteed ranges and conditions consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail safes so that the equipment incorporating Elpida Memory Inc products does not cause bodily injury fire or other consequential damage due to the operation of the Elpida Memory Inc product Usage environment Usage in environments with special characteristics as listed below was not considered in the design Accordingly our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below Example 1 Usage in liquids including water oils chemicals and organic solvents 2 Usage in exposure to direct sunlight or the outdoors or in dusty places 3 Usage involving exposure to significant amounts of corrosive gas including sea air CLs H2S NH3 SO and NOx 4 Usage in environments with static electricity or strong electromagnetic waves or radiation 5 Usage in places where dew forms 6 Usage in environments with mechanical vibration impact or stress 7 Usage near heating elements igniters or flammable items If you export the products or technology described in this document that are controlled by the Foreign Excha
30. exit Precharge power down current fast exit Precharge quiet standby current Active standby current Active power down current Operating burst read current Operating burst read IDDQ current Symbol IDDO IDD1 IDD2N IDD2NT IDDQ2NT IDD2PO IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDDQ4R Preliminary Data Sheet E1949E11 Ver 1 1 Description CKE H External clock on tCK nRC nRAS CL see Table 5 BL 8 AL 0 CS H between ACT and PRE Command address bank address inputs partially toggling according to Table 7 Data I O MID LEVEL DM stable at 0 Bank activity cycling with one bank active at a time 0 0 1 1 2 2 see Table 7 Output buffer and RTT enabled in MR ODT signal stable at 0 Pattern details see Table 7 CKE H External clock On tCK nRC nRAS nRCD CL see Table 5 BL 8 amp AL 0 CS H between ACT RD and PRE Command address bank address inputs data I O partially toggling according to Table 8 DM stable at 0 Bank activity cycling with one bank active at a time 0 0 1 1 2 2 see Table 8 Output buffer and RTT enabled in MR ODT Signal stable at 0 Pattern details see Table 8 CKE H External clock on tCK CL see Table 5 BL 8 1 AL 0 CS stable at 1 Command address bank address Inputs partially toggling according to Table 9 data I O MID LEVEL DM stable at 0 bank activity all banks closed output buffer and RTT enabled in mo
31. he DM TDQS and TDQS pins have different functions the loading matches DQ and DQS 2 VDD VDDQ VSS VSSQ applied and all other pins floating except the pin under test CKE RESET and ODT as necessary VDD VDDQ 1 35V VBIAS VDD 2 and ondie termination off Preliminary Data Sheet E1949E11 Ver 1 1 ELPIDA 21 EDJ1108EJBG EDJ1116EJBG Absolute value of CCK C CK Absolute value of CIO DQS CIO DQS Cl applies to ODT CS CKE A0 A15 BAO BA2 RAS CAS and WE CDI CTRL applies to ODT CS and CKE CDI CTRL CI CTRL 0 5 x CI CK CI CK CDI ADD CMD applies to A0 A15 BAO BA2 RAS CAS and WE CDI ADD CMD CI ADD_CMD 0 5 x CI CK CI CK CDIO CIO DQ DM 0 5 x ClIO DQS ClO DQS Maximum external load capacitance on ZQ pin 5pF ee RoER 2 TM Preliminary Data Sheet E1949E11 Ver 1 1 ELPIDA 22 EDJ1108EJBG EDJ1116EJBG 2 3 Standard Speed Bins Table 19 DDR3 800 Speed Bins Speed Bin DDR3 800E CL tRCD tRP 6 6 6 Symbol CAS write latency min max Unit Notes tAA 15 20 ns 10 tRCD 15 ns 10 tRP 15 ns 10 tRC 52 5 ns 10 tRAS 37 5 9 x tREFI ns 9 tCK avg CL 5 CWL 5 3 0 3 0 ns 1 2 9 11 tCK avg CL 6 CWL 5 25 33 ns 15 259 11 Supported CL settings 5 6 nCK Supported CWL settings 5 nCK Table 20 DDR3 1066 Speed Bins Speed Bin DDR3 1066F CL tRCD tRP 7 7 7 Symbol CASwritelatency min max Unit Notes tAA 13 125 20 ns 10 tRCD 13 125 ns 10 tRP 13 125 ns 10 tRC
32. her related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of the customer s equipment shall be done under the full responsibility of the customer Elpida Memory Inc assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information Product applications Be aware that this product is for use in typical electronic equipment for general purpose applications Elpida Memory Inc makes every attempt to ensure that its products are of high quality and reliability However this product is not intended for use in the product in aerospace aeronautics nuclear power combustion control transportation traffic safety equipment medical equipment for life Support or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury Customers are instructed to contact Elpida Memory s sales office before using this product for such applications Product usage Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory Inc including the maximum ratings operating supply voltage range heat radiation characteristics installation conditions and other relat
33. mber Figure 3 Correlation from Simulated Channel I O Power to Actual Channel I O Power Supported by IDDQ Measurement Preliminary Data Sheet E1949E11 Ver 1 1 ELPIDA EDJ1108EJBG EDJ1116EJBG 1 4 1 Timings Used for IDD and IDDQ Measurement Loop Patterns Table 5 Timings Used for IDD and IDDQ Measurement Loop Patterns DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 Parameter 6 6 6 7 7 7 9 9 9 11 11 11 Unit CL 6 7 9 11 nCK tCK min 2 5 1 875 1 5 1 25 ns nRCD min 6 7 9 11 nCK nRC min 21 27 33 39 nCK nRAS min 15 20 24 28 nCK nRP min 6 7 9 11 nCK nFAW 1KB 16 20 20 24 nCK nFAW 2KB 4KB 20 27 30 32 nCK nRRD 1KB 4 4 4 5 nCK nRRD 2KB 4KB 4 6 5 6 nCK nRFC 1Gb 44 59 74 88 nCK nRFC 2Gb 64 86 107 128 nCK nRFC 4Gb 104 139 174 208 nCK DDR3 1866 Parameter 13 13 13 Unit CL 13 nCK tCK min 1 07 ns nRCD min 13 nCK nRC min 45 nCK nRAS min 32 nCK nRP min 13 nCK nFAW 1KB 26 nCK nFAW 2KB 4KB 33 nCK nRRD 1KB 5 nCK nRRD 2KB 4KB 6 nCK nRFC 1Gb 103 nCK nRFC 2Gb 150 nCK nRFC 4Gb 243 nCK Preliminary Data Sheet E1949E11 Ver 1 1 ELPIDA 10 EDJ1108EJBG EDJ1116EJBG 1 4 2 Basic IDD and IDDQ Measurement Conditions Table 6 Basic IDD and IDDQ Measurement Conditions Parameter Operating one bank active precharge current Operating one bank active read precharge current Precharge standby current Precharge standby ODT current Precharge standby ODT IDDQ current Precharge power down current slow
34. n CK ICK CKE Sub Loop Toggling StaticH 49 Notes 1 ak cuc 11 12 13 14 15 16 17 18 19 Cycle number 0 1 2 nRRD nRRD 1 nRRD 2 2 xnRRD 3 x nRRD 4 x nRRD nFAW nFAW nRRD nFAW 2xnRRD nFAW 3 x nRRD nFAW 4 x nRRD 2 x nFAW 0 2 x nFAW 1 2 xnFAW 2 2 x nFAW nRRD 2 xnFAW nRRD 1 2 xnFAW nRRD 2 2x nFAW 2xnRRD 2 xnFAW 3 x nRRD 2 xnFAW 4 x nRRD 3 x nFAW 3 x nFAW nRRD 3 x nFAW 2xnRRD 3 x nFAW 3xnRRD 3 x nFAW 4xnRRD Com A11 A7 A3 A0 mand CS RAS CAS WE ODT BA Am A10 ACT 0 0 1 1 0 0 0 0 0 0 0 RDA 0 1 0 1 0 0 0 1 0 0 0 D 1 0 0 0 0 0 0 0 0 0 0 Repeat above D Command until nRRD 1 ACT 0 0 1 1 0 1 0 0 0 F 0 RDA 0 1 0 1 0 1 0 1 0 F 0 D 1 0 0 0 0 1 0 0 0 F 0 Repeat above D Command until 2 x nRRD 1 Repeat Sub Loop 0 but BA 2 Repeat Sub Loop 1 but BA 3 D 1 0 0 0 0 3 0 0 0 F 0 Assert and repeat above D Command until nFAW 1 if necessary Repeat Sub Loop 0 but BA 4 Repeat Sub Loop 1 but BA 5 Repeat Sub Loop 0 but BA 6 Repeat Sub Loop 1 but BA 7 D 1 0 0 0 0 7 0 0 0 F 0 Assert and repeat above D Command until 2 x nFAW 1 if necessary ACT 0 0 1 1 0 0 0 0 0 F 0 RDA 0 1 0 1 0 0 0 1 0 F 0 D 1 0 0 0 0 0 0 0 0 F 0 Repeat above D Command until 2 x nFAW nRRD 1 ACT 0 0 1 1 0 1 0 0 0 0 0 RDA 0 1 0 1 0 1 0 1 0 0 0 D 1 0 0 0 0 1 0 0 0 0 0 Repeat above D Command until 2 x
35. nge and Foreign Trade Law of Japan you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan Also if you export products technology controlled by U S export control regulations or another country s export control laws or regulations you must follow the necessary procedures in accordance with such laws or regulations If these products technology are sold leased or transferred to a third party or a third party is granted license to use these products that third party must be made aware that they are responsible for compliance with the relevant laws and regulations M01E1007 Preliminary Data Sheet E1949E11 Ver 1 1 ELPIDA 32
36. o DQL7 DQSU DQSU DQSL DQSL iGo RAS CAS WE CKE CK CK DMU DML ODT Notes 1 O VDDQ Bl O VSSQ CI O VDDQ DIO VSSQ E O VSS FI O VDDQ G O VSSQ H J O NC K O ODT L O NC M O VSS N O VDD PE VSS RIO VDD 1 Function Address inputs O DQU5 O VDD O DQU3 O VDDQ O VSSQ O DQL2 EDJ1108EJBG EDJ1116EJBG 96 ball FBGA O DQLO O DQSL O O DQL6 DQSL Omer VREFDQ VDDQ O VSS O VDD O ICS BAO O A3 O A5 O A7 O O VSS RESET A10 AP Auto precharge A12 BC Burst chop Bank select Data input output Differential data strobe Chip select Command input Clock enable Differential clock input Write data mask ODT control Not internally connected with die O DQL4 O O RAS NC O O O CAS ICK VDD CKE O O O O ANE A10 AP ZQ NC O O O BA2 NC VREFCA VSS O O O O AO A12 BC BA1 VDD O O O O A2 A1 A4 VSS O O O O A9 A11 A6 VDD O O O NC NC A8 VSS Top view Pin name RESET VDD VSS VDDQ VSSQ VREFDQ VREFCA ZQ NC Function Active low asynchronous reset Supply voltage for internal circuit Ground for internal circuit Supply voltage for DQ circuit Ground for DQ circuit Reference voltage for DQ Reference voltage for CA Reference pin for ZQ calibration No connection 2 Input only pins address command CKE ODT and RESET do not supply termination Preliminary Data Sheet E1949E11
37. pecifications 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power on does not necessarily define initial status of MOS devices Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the MOS devices with reset function have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers MOS devices are not initialized until the reset signal is received Reset operation must be executed immediately after power on for MOS devices having reset function CME0107 Preliminary Data Sheet E1949E11 Ver 1 1 ELPIDA 31 EDJ1108EJBG EDJ1116EJBG The information in this document is subject to change without notice Before using this document confirm that this is the latest version No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory Inc Elpida Memory Inc does not assume any liability for infringement of any intellectual property rights including but not limited to patents copyrights and circuit layout licenses of Elpida Memory Inc or third parties by or arising from the use of the products or information listed in this document No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of Elpida Memory Inc or others Descriptions of circuits software and ot
38. uble data rate architecture two data transfers per clock cycle The high speed data transfer is realized by the 8 bits prefetch pipelined architecture Bi directional differential data strobe DQS and DQS is transmitted received with data for capturing data at the receiver DQS is edge aligned with data for READs center aligned with data for WRITEs Differential clock inputs CK and CK DLL aligns DQ and DAS transitions with CK transitions Commands entered on each positive CK edge data and data mask referenced to both edges of DQS Data mask DM for write data Posted CAS by programmable additive latency for better command and data bus efficiency On Die Termination ODT for better signal quality Synchronous ODT Dynamic ODT Asynchronous ODT Multi Purpose Register MPR for pre defined pattern read out ZQ calibration for DQ drive and ODT RESET pin for Power up sequence and reset function SRT range Normal extended Programmable Output driver impedance control Seamless BL4 access with bank grouping Applied only for DDR3 1333 and 1600 Elpida Memory Inc 2012 EDJ1108EJBG EDJ1116EJBG Ordering Information Die Organization Internal JEDEC speed bin Part number revision words x bits banks CL tRCD tRP Package EDJ1108EJBG JS F DDR3L 1866M 13 13 13 78 ball FBGA EDJ1108EJBG GN F J 128M x 8 8 DDR3L 1600K 11 11 11 EDJ1108EJBG DJ F DDR3L 1333H 9 9 9 EDJ1116EJBG JS F DDR3L 1866M 13 1
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