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Intel Core i3-3210

1. 77 Datasheet Volume 1 Electrical Specifications intel Sheet 2 of 3 VID VID VID VID VID VID VID VID inition VR 12 0 Voltage Identification Def Table 7 1 HEX Vcc_max 1 1 13000 A E 1 11500 A F 1 12000 B O 1 12500 B B 2 1 13500 B 3 1 14000 B 4 1 14500 B 5 1 15000 B 6 1 15500 B 7 1 16000 B 8 1 16500 B 9 1 17000 B A 1 17500 B B 1 18000 B C 1 18500 B D 1 19000 B E 1 19500 B F 1 20000 C O 1 20500 C 1 11 21000 C 2 1 21500 C 3 1 22000 C 4 1 22500 C 51 23000 C 6 1 23500 C 7 1 24000 C 8 1 24500 C 9 1 25000 C A 1 25500 C B 1 26000 C C 1 26500 C D 1 27000 C E 1 27500 C F 1 28000 D 0 1 28500 D 1 1 29000 D 2 1 29500 D 3 1 30000 D 4 1 30500 D 5 1 31000 D 6 1 31500 D 7 1 32000 D 8 1 32500 D 9 1 33000 D A 1 33500 D B 1 34000 D C 1 34500 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HEX Vcc_max 0 0 1 0 1 0 1 0 1 0 1 0 1 0
2. 82 7 9 Storage Conditions 5 cages chee cds ka daa daa RR RR ERR REY 83 7 10 DE Specifications di Eruca dE RE EAD IUE 84 7 10 1 Voltage and Current Specifications 0 nena 84 7 11 Platform Environmental Control Interface PECI DC 59 90 7 11 1 PECI B s Architecture 5 cet oed terat enn Inda ee ce aenea Fade 90 7 11 2 DC Characteristics sareni satius esp ree temas ME 91 7 11 3 Input Device AYSUEFESIS teneret nhe nra xe ne dixe nuage no nee ORE aun e ERR a 91 8 Processor Land and Signal tees 93 8 1 Processor Land Assignments Sec dada adeeb ed ga d ERRARE RARE RR RR 93 9 DDR Data Swizzling enie nenne niger aan nn dee te tg anced LER E RINR S REA AY REA UAR 109 Figures 1 1 Desktop Processor ius ere rne aka ore e d ae ena CR d SERI AERA 10 1 2 Desktop Processor Compatibility Diagram
3. ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND Dir 103 104 Table 8 1 Processor Land List by Land Name Processor Land and Signal Information Table 8 1 Processor Land List by Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land Name Land AK28 AK31 AK32 AK33 AK34 AK35 AK36 AK37 AK4 AK40 AK5 AK6 AK7 AK8 AK9 L11 L14 L17 L19 L24 L27 L30 gt gt ZIEL e uj AM11 AM14 AM17 AM2 AM21 AM23 AM25 AM27 AM3 AM30 AM36 AM37 AM38 AM39 AM4 AM40 5 AN10 AN11 AN14 AN17 AN19 Buffer Type GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Dir Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
4. 44 3 6 1 Intel Advanced Encryption Standard New Instructions Intel AES NI 44 3 6 2 PCLMULQDO n Sr men err nier ew n aids 44 3 6 3 JRDRAND InStrUCEIOT S tla Gi tese dn D 45 3 7 Intel 64 Architecture X2APIC scans ee ttti ede ti Stt gestita 45 3 8 Supervisor Mode Execution Protection SMEP ssssssssseemmem meme 46 3 9 Power Aware Interrupt Routing emen 46 Power Management 20 0 nnn enne nennen 47 4 1 Advanced Configuration and Power Interface ACPI States cece eee eds 48 4 1 1 System States iets 48 4 1 2 Processor Core Package Idle 5 5 48 4 1 3 Integrated Memory Controller 5 48 4 1 4 PCIExpress Link States nbl a inn C a AR EA RE TR ME 49 4 1 5 Direct Media Interface DMI States cee cece cece nnne 49 4 1 6 Processor Graphics Controller States
5. enna 18 2 1 Intel Flex Memory Technology Operation ccccccccccsccccseseeeeecensncncccesesenecesseseneneaees 26 2 2 PCI Express Layering Diagram recti reet eer Ink senate ahead ceeds ca SANE EATER 28 2 3 Packet Flow Through the Layers seen tesa csi ae nnn Dne nne duh naga a dg AX CREER ENS 29 2 4 PCI Express Related Register Structures in 30 2 5 PCI Express Typical Operation 16 Lanes Mapping 31 2 6 Processor Graphics Controller Unit Block Diagram 33 2 7 Processor Display Block Diagram eect eee eee eee eee nena eee ea a 36 4 1 Processor Power States ies ern Rr traen Catia rr ran Rea XR Rar ade dean i FERREA 47 4 2 Idle Power Management Breakdown of the Processor 0 66 51 4 3 Thread and Core C State Entry and inanan iana 51 4 4 Package C State Entry and Exit iocos ed deta da RR Y RR ERR 55 7 1 Example for P
6. i iii iiia SO IA fala la gt a BO 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 5 5 5 5 79 Datasheet Volume 1 m L 8 Electrical Specifications 7 7 80 System Agent SA Vcc VID The Vecsa is configured by the processor output land VCCSA VID VCCSA VID output default logic state is low for 2nd generation and 3rd generation Desktop Core processors and configures Vccsa to 0 925 V Reserved or Unused Signals The following are the general types of reserved RSVD signals and connection guidelines RSVD these signals should not be connected RSVD TP these signals must be routed to a test point Failure to route these signal to test points will restrict Intel s ability to assist in platform debug RSVD NCTF these signals are non critical to function and may be left un connected Arbitrary connection of these signals to Vcc Vecio VDDQ VAXG Vss or to any other signal including each other may result in component malfunction or incompatibility with future processors See Chapter 8 for a land listing of the processor and the location of a
7. eene 49 4 1 7 Interface State inini nana nana nu nun d 49 4 2 Processor Core Power Management nner eee tena anes 50 4 2 1 Enhanced Intel SpeedStep Technology eene 50 4 2 2 Low Power Idle States oce rater ennn tune DnE cau sc ken 50 4 2 3 Requesting Low Power Idle States 52 Datasheet Volume 1 2 NN NEGO ES 52 4 2 4 1 Core CO State o ntes eee nex due RR d RR 52 4 2 4 2 Core Ct CIE State cies dias chien hen dene 53 4 2 4 3 Core C3 SUALC rennen rti ecg pee coated eve ra ERFR Ma aaia eed es 53 4 2 4 4 Core CG Slate iid 53 4 2 4 5 C State Henn 53 4 2 5 Package t a 54 4 2 5 1 Package Desa a 55 4 2 5 2 Package Cl C1E ecccieieiscanascadatireareteatanenaien sacs datas en E RA GR 55 4 2 5 3 Package C3 State duce ecce a eer E E O nina 56 4 2 5 4 Package C6 State i uii erba O AREE OER VER Aa n ib 56 4 3 iE Memory Controller IMC Power Management sssses
8. 26 2 1 5 Technology Enhancements of Intel Fast Memory Access Intel 27 2 1 5 1 Just in Time Command 5 27 2 1 5 2 Command Overlap nce crt tta cata ener n da n ek koi na n RO e RR 27 2 1 5 3 Out of Order Scheduling iine etre terne anth arn erre ed 27 2 1 60 Data Scramiblinig enitn xin nne OCC Xn RR CORE we Qe die XR RR e UR RR 27 2 1 7 DDR3 Reference Voltage Generation n 27 2 2 PGLExpress Interface rentrer a rises xir ail nervus ge t ied 28 2 2 4 PCI Expr ss Architecture uie ie esent testet canis aa RARE ARA MED MEE 28 2 2 1 1 Transaction eques ken Cina 29 2 2 1 2 Data Link Layer clas ax RA AR E RR 29 2 2 1 3 Physical Laye uices eden e uses du 29 2 2 2 PCI Express Configuration Mechanism eens mmn 30 2 2 3 PCI EXpress ERREUR DEN SERV DRE eK MM 31 2 2 3 1 PCI Express Lanes Connection e 31 2 3 Direct Media Interface DMI koreino reprend penna asiacidaesed besa KE ONERE 32 pcm DMI Error
9. F Buffer Type PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express CMOS Async GTL Async GTL N A Async GTL CMOS O O CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO OF O Eu E o Datasheet Volume 1 Processor Land and Signal Information Table 8 1 Processor Land List by Land Name Table 8 1 intel Processor Land List by Land Name Land Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD NCTF RSVD NCTF RSVD NCTF RSVD NCTF SA 5 0 SA BS 1 SA BS 2 SA_CAS SA_CK 0 SA CK 1 SA CK 2 SA CK 3 SA CK 0 SA CK 1 SA CK 2 SA CK 3 SA CKE 0 SA CKE 1 SA CKE 2 SA CKE 3 SA CS 0 Datasheet Volume 1 Land D38 H7 H8 133 134 19 K34 K9 L31 L33 L34 L9 M34 N33 N34 35 37 39 R34 R36 R38 R40 131 AD34 AD35 K31 AV1 AW2 AY3 B39 AY29 AW28 AV20 AV30 AY25 AU24 AW27 AV26 AW25 AU25 AY27 AW26 AV19 AT19 AU18 AV18 AU29 Buffer Type DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 Dir O O CO CO CO CO
10. Table 7 8 Control Sideband and TAP Signal Group DC Specifications Symbol Parameter Min Max Units Notes Vit Input Low Voltage Vecio 0 3 V 2 Vin Input High Voltage Vecio 0 7 V 2 4 VoL Output Low Voltage Vecio 0 1 V 2 VoH Output High Voltage 0 9 V 2 4 Ron Buffer on Resistance 23 73 Q Ii Input Leakage Current 200 pA 3 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The Vccio referred to in these specifications refers to instantaneous 3 For Vjy between 0 V and Vccro Measured when the driver is tri stated 4 Vg and Voy may experience excursions above However input signal drivers must comply with the signal quality specifications Table 7 9 PCI Express DC Specifications Symbol Parameter Min Typ Max Units Notes DC Differential Tx Impedance Gen 1 ZpcbIFF DC Only P 80 120 2 DC Differential Tx Impedance Gen 2 ZTX DIF DC and Gen 3 k X 120 Q 2 ZRX DC DC Common Mode Rx Impedance 40 60 Q 3 4 DC Differential Rx Impedance Gen 1 ZRX DIFF DC Only p 80 120 Q PEG_ICOMPO Comp Resistance 24 75 25 25 25 Q 5 6 PEG_ICOMPI Comp Resistance 24 75 25 25 25 Q 5 6 PEG_RCOMPO Comp Resistance 24 75 25 25 25 Q 5 6 Notes 1 Refer to the PCI Express Base Specification for more details 2 Low impedance defined during signaling Parameter is captured for 5 0 GHz by RLTX DIFF 3 DC impedance limits are
11. LP 32 2 3 2 Processor PCH Compatibility Assumptions cesssseeee e 32 2 3 3 DMI LINK DOWN rm 32 2 4 Processor Graphics Controller GT iiie dad cageedeneet tease ERR RR 33 Datasheet Volume 1 3 2 4 1 3D and Video Engines for Graphics Processing 33 2 4 1 1 3D Engine Execution 5 ines 33 2 4 1 2 3D Pipeline eie naaa er pne td aa ete RR RR A E ERR EXE 34 2 4 1 3 Video ENGINE asiriarren anoni n EETA ane r E AYER 34 2 4 1 4 29 iae ede tes eterne ete ex beer eve tetur vinee etu Ed 35 2 4 2 Processor Graphics Display ies tienen unen kir eeee d xe pibe nn a Reim mn a RR RR RE 36 2 4 2 1 Display Pl n6esS drinnen Ferr dina exea endi a DER RE PI GR cx 36 2 4 2 2 Display iei 37 2 4 2 3 Display 37 2 4 3 Intel Flexible Display Interface Intel FDI s ssseseseeseeeeeeeeeeeeeeneaeanees 37 2 4 4 Multi Graphics Controllers Multi Monitor Support c cece eect ee ee ee eee eaees 37 2 5 Platform Environment Control Interface 38 2 6 Interface Clocking sirarsa pecan neal eae pense E a ER lace aces inpEra ETNE EA EEA 38 2 6 1 Internal Clocking Requirements s
12. DirectX Video Acceleration DXVA support for accelerating video processing Full AVC VC1 MPEG2 HW Decode Advanced Scheduler 2 0 1 0 XPDM support Windows 7 Windows XP OSX Linux OS Support DirectX 11 DirectX 10 1 DirectX 10 DirectX 9 support OpenGL 3 0 support Switchable Graphics support on Desktop AIO platforms with MxM solutions only Intel Flexible Display I nterface Intel FDI For SKUs with graphics carries display traffic from the Processor Graphics in the processor to the legacy display connectors in the PCH Based on DisplayPort standard The two Intel FDI links are capable of being configured to support three independent channels one for each display pipeline There are two Intel FDI channels each one consists of four unidirectional downstream differential transmitter pairs Scalable down to 3X 2X or 1X based on actual display bandwidth requirements Fixed frequency 2 7 GT s data rate Two sideband signals for display synchronization FDI FSYNC and FDI LSYNC Frame and Line Synchronization One Interrupt signal used for various interrupts from the PCH FDI INT signal shared by both Intel FDI Links PCH supports end to end lane reversal across both links Common 100 MHz reference clock Power Management Support Processor Core Full support of ACPI C states as implemented by the following processor C states CO Cl CIE C3 C6 Enhanced Intel SpeedStep Technology System
13. Disabling Unused System Memory Outputs Any System Memory SM interface signal that goes to a memory module connector in which it is not connected to any actual memory devices such as SO DIMM connector is unpopulated or is single sided is tri stated The benefits of disabling unused SM signals are e Reduced power consumption Reduced possible overshoot undershoot signal quality issues seen by the processor 1 0 buffer receivers caused by reflections from potentially un terminated transmission lines When a given rank is not populated the corresponding chip select and CKE signals are not driven At reset all rows must be assumed to be populated until it can be proven that they are not populated This is due to the fact that when CKE is tri stated with a SO DIMM present the SO DIMM is not ensured to maintain data integrity SCKE tri state should be enabled by BIOS where appropriate since at reset all rows must be assumed to be populated Datasheet Volume 1 Power Management intel 4 3 2 DRAM Power Management and Initialization The processor implements extensive support for power management on the SDRAM interface There are four SDRAM operations associated with the Clock Enable CKE signals that the SDRAM controller supports The processor drives four CKE pins to perform these operations The CKE is one means of power saving When CKE is off the internal DDR clock is disabled and the DDR power is reduced The power s
14. FDI FDI FDI FDI FDI FDI FDI FDI FDI FDI FDI FDI FDI FDI FDI PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express y O O O CO Of Of Of CO CO OF Of Of Of OF HP 1 1 11 Of BI A Rt 95 96 intel Table 8 1 Processor Land List by Land Name Processor Land and Signal Information Table 8 1 Processor Land List by Land Name Land Name PECI PEG COMPI PEG ICOMPO PEG RCOMPO PEG RX O PEG RX 1 PEG RX 2 PEG RX 3 PEG RX 4 PEG RX 5 6 7 8 9 PEG RX PEG RX PEG RX PEG RX PEG RX 10 PEG RX 11 PEG RX 12 PEG RX 13 PEG RX 14 PEG RX 15 PEG RX 0 PEG RX 1 PEG RX 2 PEG RX 3 PEG RX 4 PEG RX 5 PEG RX 6 PEG RX 7 PEG RX 8 PEG RX 9 PEG RX 10 PEG RX 11 PEG RX 12 PEG RX 13 PEG RX 14 PEG RX 15 PEG TX 0 PEG TX 1 PEG TX 2 PEG TX 3 PEG TX 4 PEG TX 5 PEG TX 6 PEG TX 7 PEG TX 8 PEG TX 9 PEG TX 10 Land 135 B4 B5 C4 B11 D12 C10 E10 B8 C6 A5 E2 F4 G2 H3 J1 K3 L1 M3 Ni B12 D11 C9 E9 B7 C5 A6 E1 F3 G1 H4 12 K4 L2 M4 N2 C13 E14 G14 F12 J14 D8 D3 E6 F8 G10 G5 Buffer Type Async
15. S0 S3 S4 S5 Memory Controller Datasheet Volume 1 Conditional self refresh Intel Rapid Memory Power Management Intel RMPM Dynamic power down 15 1 3 5 1 3 6 1 3 7 1 4 Table 1 1 Introduction PCI Express LOs and L1 ASPM power management capability Direct Media nterface DMI LOs and L1 ASPM power management capability Processor Graphics Controller GT Intel Rapid Memory Power Management Intel RMPM CxSR Intel Graphics Performance Modulation Technology Intel GPMT Intel Smart 2D Display Technology Intel S2DDT Graphics Render C State RC6 Thermal Management Support Digital Thermal Sensor ntel Adaptive Thermal Monitor THERMTRI P and PROCHOT support On Demand Mode Memory Thermal Throttling External Thermal Sensor TS on DI MM and TS on Board Render Thermal Throttling Fan speed control with DTS Processor SKU Definitions Desktop 3rd Generation Intel Core Processor Family Desktop I ntel Pentium Processor Family and Desktop Intel Celeron Processor Family SKUs Sheet 1 of 2 Processor TDP IA LFM Number W Frequency IA Frequency range GT Frequency range i7 3770T 45 1600 MHz 2 5 GHz up to 3 7 GHz 650 MHz up to 1150 MHz 94 i7 3770S 1600 MHz 3 1 GHz up to 3 9 GHz 650 MHz up to 1150 MHz 103 i7 3770K 1600 MHz 3 5 GHzup to 3 9 GHz 650 MHz up to 1150 MHz 105 i7 3770 77 1600 MHz 3
16. SB DQS 1 SB DQS 2 SB DQS 3 SB DQS 4 SB DQS 5 SB DQS 6 SB DQS 7 SB DQS 8 SB_DQS 0 SB_DQS 1 SB_DQS 2 SB_DQS 3 SB_DQS 4 5 6 7 8 SB_DQS SB_DQS SB_DQS SB_DQS SB ECC CB SB ECC CB SB ECC CB SB ECC CB SB ECC CB SB ECC CB SB ECC CB SB ECC CB SB SB MA 1 SB MA 2 SB MA 3 SB MA 4 SB MA 5 SB MA 6 SB MA 7 SB MA 8 SB MA 9 Ol nN Elo Land AL31 AM35 AL34 AH35 AH34 AE34 AE35 AJ35 AJ34 AF33 AF35 AH7 AM8 AR8 AN13 AN29 AP33 AL33 AG35 AN16 AH6 AL8 AP8 AN12 AN28 AR33 AM33 AG34 AN15 AL16 AM16 AP16 AR16 AL15 AM15 AR15 AP15 AK24 AM20 AM19 AK18 AP19 AP18 AM18 AL18 AN18 AY17 Buffer Type DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 Dir I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O 1 I O I O I O I O 1 0 I O I O I O I O I O I O I O I O I O I O I O I O I O o O O O CO CO OJ CO O OF O 99 intel 100 Table 8 1 Land Name Processor Land List by Processor Land and Signal Information Table 8 1 Processor Land List by Land Name Land Name SB MA 10 SB MA 11 SB MA 12 SB MA
17. e Support for two modes of operation to provide backward compatibility and extensibility for future platform innovations In xAPIC compatibility mode APIC registers are accessed through memory mapped interface to a 4 KB page identical to the xAPIC architecture In x2APIC mode APIC registers are accessed through Model Specific Register MSR interfaces In this mode the x2APIC architecture provides significantly increased processor addressability and some enhancements on interrupt delivery e Increased range of processor addressability in x2APIC mode Physical xAPIC ID field increases from 8 bits to 32 bits allowing for interrupt processor addressability up to 4 GB 1 processors in physical destination mode A processor implementation of x2APIC architecture can support fewer than 32 bits in a software transparent fashion Logical xAPIC ID field increases from 8 bits to 32 bits The 32 bit logical x2APIC ID is partitioned into two sub fields a 16 bit cluster ID and a 16 bit logical ID within the cluster Consequently 2 20 16 processors can be addressed in logical destination mode Processor implementations can support fewer than 16 bits in the cluster ID sub field and logical ID sub field in a software agnostic fashion Datasheet Volume 1 45 L 8 Technologies Note 3 8 3 9 46 More efficient MSR interface to access APIC registers To enhance inter processor and self directed interrupt
18. te 86 ns t ote te st ol o o o ojo o ojo o lojo o loj o ojlo o o jo o olo olo lo olo o olo o o lo o Zz O n O n O o O i O 19 15 n O 15 O 19 O io O io O ro O i O i O 10 O 19 O in O in O I jalia e o MITT TIM t0 i9 IR o o0 0 O JO 2 HAIN ex e o sr 00 Lo JO vo KR Jo Nix x TATE TR S S TRIN TS S x S TS f TS 99 1 o 100 00 60 jo jo jo jo 60 oo jo oo gt ojo o o o o o o Jo o o o Jo o o o Jo o o o Jo o o o Jo o o o Jo o o o o o o x O u r O ev o sr o 9 o o m JO sO uu JL v IM s 10 i 06 o a em JO pw ju ul TO uo 1 10 vo xo vo vo xo vo vo xo vo vo vo vo vo v o 8 In NIN IR IRIN IR RIN 89 89 89 9 NIN a SOS PS YS Te ste spe st ye pepe dye pape days faye pays ya ye pe ye ya ye pa yey BEE YO Pt pt 1 YO Pt pt 1 0 Pt Pt 1 0 Pt Pt 1 0 Jt Pt 10 0 J ft 10 0 J rt 10 JO J ft JO JO J a Bw PPS PO YO PO Pr tt a OO IO 2 72 e e 2 2 2 e P e 10 2 f a SM IA AIA JOJO JO IO JO 0 A JA A AJA td gt a 1D YS 2 1S 9 19 YO IO YO a 5 N
19. GND GND GND GND GND GND GND GND GND GND GND GND GND GND Dir Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land AY8 B10 B13 B14 B17 B23 B26 B29 B32 B35 B38 B6 C11 C12 C17 C20 C23 C26 C29 C32 C35 C7 C8 D17 D2 D20 D23 D26 D29 D32 D37 D39 D4 D5 D9 E11 E12 E17 E20 E23 E26 E29 E32 E36 E7 E8 Fi Buffer Type ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND ND QO OF OF O OF OF OF O OF Dir 105 106 ntel Processor Land and Signal Information Table 8 1 Processor Land List by Table 8 1 Processor Land List by Land Name Land Name Land Name Land Buffer Type Dir Land Name Land Buffer Type Dir VSS F10 GND VSS K12 GND VSS F13 GND VSS K13 GND VSS F14 GND VSS K14 GND VSS F17 GND VSS K17 GND VSS F2 G
20. I O I O I O I O Land Name SA_MA 1 SA_MA 2 SA_MA 3 SA_MA 4 SA_MA 5 SA_MA 6 SA_MA 7 SA_MA 8 SA_MA 9 SA_MA 10 SA_MA 11 SA_MA 12 SA MA 13 SA MA 14 SA MA 15 SA ODT 0 SA ODT 1 SA ODT 2 SA ODT 3 SA_RAS SA_WE SB_BS 0 SB_BS 1 SB_BS 2 SB_CAS SB_CK 0 SB CK 1 SB CK 2 SB CK 3 SB_CK 0 SB_CK 1 SB_CK 2 SB_CK 3 SB CKE 0 SB CKE 1 SB CKE 2 SB CKE 3 SB_CS 0 SB_CS 1 SB_CS 2 SB_CS 3 SB_DQ 0 SB_DQ 1 SB_DQ 2 SB_DQ 3 SB_DQ 4 SB_DQ 5 Land AY24 AW24 AW23 AV23 AT24 AT23 AU22 AV22 AT22 AV28 AU21 AT21 AW32 AU20 AT20 AV31 AU32 AU30 AW33 AU28 AW29 AP23 AM24 AW17 AK25 AL21 AL20 AL23 AP21 AL22 AK20 AM22 AN21 AU16 AY15 AW15 AV15 AN25 AN26 AL25 AT26 AG7 AG8 AJ9 AJ8 AG5 AG6 Buffer Type DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 OjOjOj O OlO O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O CO O Datasheet Volume 1 Processor Land and Signal Information Table 8 1 Processor Land List by Land Name Table 8 1 intel Processor Land List by Land Name Land Name SB DQI 6 SB DQ 7 SB DQ 8 SB DQ
21. Y3 AA4 W4 V4 Y4 AA5 V7 W7 Y6 AA7 V6 w8 Y7 Buffer Type Diff Clk Diff Clk Diff Clk Diff Clk GTL GTL GTL GTL GTL GTL GTL GTL GTL Q o MOS MOS MOS MOS o MOS MOS MOS MOS MOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Async CMOS DMI DMI DMI DMI DMI DMI DMI DMI DMI DMI DMI DMI DMI DMI DMI OoOlojojojoljoJjojojoijo Dir j ee ZISIS Erud ER Ed Erud O OC O O CO O OF O ol ol ol oO oO Of BI 5 5l Bl a ap ap Bp BP 5 Bp BP a Bp 5o Land Name DMI_TX 3 SB_DIMM_VREFDQ SA_DIMM_VREFDQ FDI_COMPIO FDI FSYNC 0 FDI FSYNC 1 FDI ICOMPO FDI INT FDI LSYNC 0 FDI LSYNC 1 FDI TX O FDI TX 1 FDI TX 2 FDI TX 3 FDI TX 4 FDI TX 5 FDI TX 6 FDI TX 7 FDI_TX 0 FDI_TX 1 FDI_TX 2 FDI_TX 3 FDI_TX 4 FDI_TX 5 FDI_TX 6 FDI_TX 7 NCTF NCTF NCTF NCTF NCTF PE RX 0 PE RX 1 PE RX 2 PE RX 3 RX 0 PE RX 1 PE_RX 2 PE_RX 3 PE TX 0 PE TX 1 PE TX 2 PE TX 3 PE_TX 0 PE_TX 1 PE_TX 2 PE_TX 3 Land AAB AH1 AH4 AE2 AC5 AE5 AG3 AC4 AE4 AC8 AC2 AD2 AD4 AD7 AE7 AF3 AG2 AC7 AC3 AD1 AD3 AD6 8 AF2 AG1 A38 AU40 AW38 C2 Di P3 R2 T4 U2 P4 R1 T3 U1 P8 T7 R6 U5 P7 T8 R5 U6 Buffer Type DMI Analog Analog Analog CMOS CMOS Analog CMOS CMOS CMOS FDI
22. eee eee 48 424 PCL Express Link States c itin n nth de a xn DR d m RR a a ROCA A RR RE 49 4 5 Direct Media Interface DMI States sssssssssssssssssssees semen 49 4 6 Processor Graphics Controller States ssssssssssssssssssssse nemen 49 4 7 G S and C State Combinationsi iiis cecinere a caa ed x ag aene VR De dd EY 49 4 8 Coordination of Thread Power States at the Core Level s s ssssssssssrsssrssrusrnnsurnnnnrernnners 51 4 9 LVLx to MWAIT ConVersiOTr c tare eran Dac mE ripe D va axe ina Dv icr i a DO chiens RR CEA TR EVE 52 4 10 Coordination of Core Power States at the Package Level sss 54 6 1 Signal Description Buffer Types cece eee senem nnns 65 6 Datasheet Volume 1 6 2 Memory Channel A Signals irae ere x a danas xe e n ARE ETEEN OARDE 66 6 3 Memory Channel B Signals 4 eee Fs 67 6 4 Memory Reference and Compensation sssssssssssssssssese emen eee eene 67 6 5 Reset and Miscellaneous 9 6 85 eee eee nee 68 6 6 PCI Express Graphics Interface Signals nens 69 6 7 Intel Flexible Display Intel FDI Interface ccccccccccecceceecucueeeueesececeeeeceueueueueatanaas 69 6 8 Direct Media Interface DMI Sign
23. processor core Virtual Legacy Wires VLWs Resetwarn or MSIs only Processor core gt DMI APIC and MSI interrupt messaging support Message Signaled Interrupt MSI and MSI X messages Downstream SMI SCI and SERR error indication Legacy support for ISA regime protocol PHOLD PHOLDA required for parallel port DMA floppy drive and LPC bus masters DC coupling no capacitors between the processor and the PCH Polarity inversion PCH end to end lane reversal across the link Supports Half Swing low power low voltage 1 2 4 Platform Environment Control I nterface PECI The PECI is a one wire interface that provides a communication channel between a PECI client the processor and a PECI master The processor supports the PECI 3 0 Specification 1 2 5 Processor Graphics 14 The Processor Graphics contains a refresh of the seventh generation graphics core enabling substantial gains in performance and lower power consumption Up to 16 EU support Next Generation Intel Clear Video Technology HD Support is a collection of video playback and enhancement features that improve the end user s viewing experience Encode transcode HD content Playback of high definition content including Blu ray Disc Superior image quality with sharper more colorful images Datasheet Volume 1 Introduction 1 2 6 1 3 1 3 1 1 3 2 1 3 3 Playback of Blu ray disc S3D content using HDMI V 1 4 with 3D
24. tins 73 6 12 SENSE E 73 6 13 Ground and Non Critical to Function NCTF 5 8 5 eaten 74 6 14 Processor Internal Pull Up Pull Down 74 7 Electrical Specifications oci nanenane REESE I e aane adu RD CURRERE DES RR Nx nna 75 7 1 Power and Ground Lands sssssssssssssssesese eese esee nenne sensns 75 7 2 Decoupling Guidelines ieri ties se e iR ae onde SERE RM Dec Rd DRla EE 75 7 2 1 Voltage Rail Decoupling eseeesseseseese nnne nnn 75 7 3 Processor Clocking BCLK 0 BCLK 0 mH 76 7 3 1 Phase Lock Loop PLL 5 76 7 4 VCC Voltage Identification seen terna hen nnns nana da an RA nu naa 76 7 5 System Agent SA Vcc VID sranna nae ore degenas ge anagaedaxenes dealnews 80 7 60 Reserved or Un sed Signals ecce ore ge tenta tet yoke Cab ad a RE nena ERR RE 80 Datasheet Volume 1 5 Fad _ TDCi 80 7 8 Test Access Port TAP Connection
25. 0 differential pair DMI Phase Lock Loop PLL Signals Phase Lock Loop PLL Signals Direction Signal Name Description Buffer Type BCLK Differential bus clock input to the processor I BCLK Diff Clk Test Access Points TAP Signals TAP Signals Signal Name Description b Breakpoint and Performance Monitor Signals These signals BPM 7 0 are outputs from the processor that indicate the status of I O breakpoints and programmable counters used for monitoring CMOS processor performance BCLK_ITP These signals are connected in parallel to the top side debug 1 BCLK_ITP probe to enable debug capacities DBR is used only in systems where no debug port is DBR implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive system reset PRDY is a processor output used by debug tools to determine PRDY processor debug readiness Asynchronous CMOS PREQ is used by debug tools to request debug operation of the I PREQ processor Asynchronous CMOS Test Clock This signal provides the clock input for the I TCK processor Test Bus also known as the Test Access Port TCK CMOS must be driven low or allowed to float during power on Reset Test Data In This signal transfers serial test data into the I TDI processor TDI provides the serial input needed for JTAG CMOS specification support Test Data Out This signal transfers serial test data out
26. 13 SB MA 14 SB MA 15 SB ODT 0 SB ODT 1 SB ODT 2 SB ODT 3 SB RAS SB WE SKTOCC SM_DRAMPWROK SM_DRAMRST SM_VREF TCK TDI TDO THERMTRIP TMS TRST UNCOREPWRGOOD VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Land AN23 AU17 AT18 AR26 AY16 AV16 AL26 AP26 AM26 AK26 AP24 AR25 AJ33 AJ19 AW18 AJ22 M40 L40 L39 G35 L38 139 140 A12 A13 A14 A15 A16 A18 A24 A25 A27 A28 B15 B16 B18 B24 B25 B27 B28 B30 B31 B33 B34 C15 C16 C18 Buffer Type DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 Analog Async CMOS DDR3 Analog TAP TAP TAP Asynch CMOS TAP TAP Async CMOS PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR g ete O FH A O 1 CO CO CO CO CO OF O Land Name Land C19 C21 C22 C24 C25 C27 C28 C30 C31 C33 C34 C36 D13 D14 D15 D16 D18 D19 D21 D22
27. 2 Desktop Processor Compatibility Diagram VAXG 2 ph required for some of the SKUs 2 x 330 pF 2 x 330 pF 1 placeholder PEG AC Decoupling PEG Gen 1 2 100 nF PEG Gen 1 2 3 220 nF G2_Core 1 5V G3 Core 1 5V G2 Core 1 05 V G3 Core 1 05 V G2 Core 0 925 V G3 Core 0 925 V Processor VCCSA VID G2 Core 0 G3 Core 0 VCCIO_SEL G2_Core 1 PROC_SELECT G3 Core 1 G2 Core 1 G3 Core 0 Controls DMI And FDI termination DF TVS Notes 1 G2 Core 2nd Generation Intel Core processor family Desktop Intel Pentium processor family Desktop Intel Celeron processor family Desktop 2 G3 Core Desktop 3rd Generation Intel Core processor family Desktop Intel Pentium processor Desktop Intel Celeron processor family e 18 Datasheet Volume 1 Introduction 1 7 Table 1 2 Terminology Terminology Sheet 1 of 3 Execute Disable Bit Term Description ACPI Advanced Configuration and Power Interface ADB Automatic Display Brightness APD Active Power Down ASPM Active State Power Management BGA Ball Grid Array BLT Block Level Transfer CLIT Closed Loop Thermal Throttling CRI Cathode Ray Tube cTDP Configurable Thermal Design Power DDDR3L RS DDR3L Reduced Standby Power DDR3 Third generation Double Data Rate SDRAM memory technology DDR3L DDR3 Low Voltage DMA Direct Memory Access DMI Di
28. 2D Display Technology Intel 525 61 4 6 5 Intel Graphics Dynamic Frequency nnn nnne 61 4 7 Graphics Thermal Power 61 5 Thermal Managerment ornate en aE RE dete enedeacedaeecnadanannanecens 63 Signal Description eroi idees eco euer et A Rl Er el kae A 65 6 1 System Memory Interface Signals ssssssssssssssssssssse eene 66 6 2 Memory Reference and Compensation 5 5 67 6 Reset and Miscellaneous SignalS c ccecececeecseeeseeaecceeeeeeeececeeseeeeaenaeaearsanaeeeeeeeeenes 68 6 4 PCI Express based Interface Signals scrini iiaiai aa iaat re ai 69 6 5 Intel Flexible Display Intel FDI Interface Signals eee 69 6 6 Direct Media Interface DMI Signals sss nemen emen emen 70 6 7 Phase Lock Loop PLL Signals 2 xe rebns nix a eaa adea ta En ia 70 6 8 Test Access Points TAP Signals cccccee ee ee eee eee eee ensem eem 70 6 9 Error and Thermal Protection Signals sse eene 71 6 10 Power Sequencing Signals eee inanis esee emm nnns 72 6 11 Processor end ie
29. 4 GHz up to 3 9 GHz 650 MHz up to 1150 MHz 105 i5 3570T 45 1600 MHz 2 3 GHz up to 3 3 GHz 650 MHz up to 1150 MHz 94 i5 3570S 65 1600 MHz 3 1 GHz up to 3 8 GHz 650 MHz up to 1150 MHz 103 i5 3570K 77 1600 MHz 3 4 GHz up to 3 8 GHz 650 MHz up to 1150 MHz 105 i5 3570 1600 MHz 3 4 GHz up to 3 8 GHz 650 MHz up to 1150 MHz 105 i5 3550S 1600 MHz 3 GHz up to 3 7 GHz 650 MHz up to 1150 MHz 103 i5 3550 77 1600 MHz 3 3 GHz up to 3 7 GHz 650 MHz up to 1150 MHz 105 ib 3475S 65 1600 MHz 2 9 GHz up to 3 6 GHz 650 MHz up to 1100 MHz 103 i5 3470S 65 1600 MHz 2 9 GHz up to 3 6 GHz 650 MHz up to 1100 MHz 103 i5 3470T 35 1600 MHz 2 9 GHz up to 3 6 GHz 650 MHz up to 1100 MHz 91 i5 3470 1600 MHz 3 2 GHz upto 3 6 GHz 650 MHz up to 1100 MHz 105 i5 3450S 1600 MHz 2 8 GHz upto 3 5 GHz 650 MHz up to 1100 MHz 103 16 Datasheet Volume 1 Introduction Table 1 1 Desktop 3rd Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family SKUs Sheet 2 of 2 W re ena Frequency range GT Frequency range cS i5 3450 77 1600 MHz 3 1 GHz up to 3 5 GHz 650 MHz up to 1100 MHz 105 i5 3350P 69 1600 MHz 3 1 GHZ up to 3 3 GHZ N A 105 i5 3330 77 1600 MHz 3 GHz up to 3 2 GHz 650 MHz up to 1050 MHz 105 i3 3240T 35 1600 MHz Up to 3 0 GHz 650 MHz up to 1050 MHz 91 i3 3240 55 1600 MHz Up to 3 4 GHz 650 MHz up to 1050 MHz 105 i3 3225 55 1600 MHz Up to 3 3 GHz
30. 650 MHz up to 1050 MHz 105 i3 3210 55 1600 MHz Up to 3 2 GHz 650 MHz up to 1050 MHz 105 G2130 55 1600 MHz Up to 3 2 GHz 650 MHz up to 1050 MHz 105 G2120 55 1600 MHz 3 1 GHz 650 MHZ up to 1 05 GHZ 105 G2100T 35 1600 MHz 2 6 GHz 650 MHZ up to 1 05 GHZ 91 G2020T 2 5 GHz 650 MHZ up to 1050 MHz 91 G2010 55 1600 MHz 650 MHZ up to 1050 MHz 105 G1620 55 1600 MHz 650 MHZ up to 1050 MHz 105 G1610 55 1600 MHz 650 MHZ up to 1050 MHz 105 G1610T 35 1600 MHz 650 MHZ up to 1050 MHz 91 1 5 Package The processor socket type is noted as LGA 1155 The package is a 37 5 x 37 5 mm Flip Chip Land Grid Array FCLGA 1155 See the Desktop 3rd Generation Intel Core Processor Family Desktop Intel Pentium Processor Family Desktop Intel Celeron Processor Family and LGA1155 Socket Thermal Mechanical Specifications and Design Guidelines for complete details on the package Datasheet Volume 1 17 Introduction 1 6 Processor Compatibility The Desktop 3rd Generation Intel Core processor family Desktop Intel Pentium processor family Desktop Intel Celeron processor Family has specific platform requirements that differentiate it from a 2nd Generation Intel Core processor family Desktop Intel Pentium processor family Desktop Intel Celeron processor Family Desktop processor Platforms intending to support both processor families need to address the platform compatibility requirements detailed in Figure 1 2 Figure 1
31. Analog Analog Analog PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express PCI Express Dir pu o Ololjlolijolijolioliolioioiolioi 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 5 5 5 5 5 5 5 5 5 9 5 5 5 Land Name PEG TX 11 PEG TX 12 PEG TX 13 PEG TX 14 PEG TX 15 PEG 4 0 PEG TX 1 PEG 4 2 PEG TX 3 PEG 4 4 PEG 4 5 PEG TX 6 PEG TX 7 PEG TX 8 PEG 4 9 PEG TX 10 PEG TX 11 PEG TX 12 PEG TX 13 PEG TX 14 PEG 4 15 PM SYNC PRDY PREQ PROC_SEL PROCHOT RESET RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD Land K7 J5 M8 L6 N5 C14 E13 G13 F11 J13 D7 C3 E5 F7 G9 G6 K8 J6 M7 L5 N6 E38 K38 K40 K32 H34 F36 AB6 AB7 AD37 AE6 AF4 AG4 AJ11 AJ29 AJ30 AJ31 AN20 AP20 AT11 AT14 AU10 AV34 AW34 AY10 C38 C39
32. CO CO CO CO CO CO CO OF OC OF O Land Name SA_CS 1 SA_CS 2 SA_CS 3 SA DQ O SA DQ 1 SA DQ 2 SA DQ 3 SA DQ 4 SA DQ 5 6 7 8 9 SA DQ SA DQ SA DQ SA DQ SA DQ 10 SA DQ 11 SA DQ 12 SA DQ 13 SA DQ 14 SA DQ 15 SA DQ 16 SA DQ 17 SA DQ 18 SA DQ 19 SA DQI 20 SA DQI 21 SA DQI 22 SA DQI 23 SA 24 SA 25 SA DQI 26 SA DQI 27 SA DQI 28 SA DQI 29 SA DQI 30 SA DQI 31 SA 32 SA DQI 33 SA 34 SA DQ 35 SA DQI 36 SA DQI 37 SA DQI 38 SA DQI 39 SA DQ 40 SA DQ 41 SA 42 SA 43 Land AV32 AW30 AU33 AJ3 AJ4 AL3 AL4 AJ2 AJ1 AL2 AL1 AN1 AN4 AR3 AR4 AN2 AN3 AR2 AR1 AV2 AW3 5 AWS AU2 AU3 AUS AY5 AY7 AU7 AV9 AU9 AV7 AW7 AW9 9 AU35 AW37 AU39 AU36 AW35 AY36 AU38 AU37 AR40 AR37 AN38 AN37 Buffer Type DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 ojojo 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 97 98 intel Table 8 1 Processor Land List by Land Name Processor Land
33. D24 D25 D27 D28 D30 D31 D33 D34 D35 D36 E15 E16 E18 E19 E21 E22 E24 E25 E27 E28 E30 E31 E33 E34 E35 F15 F16 Buffer Type PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Dir Datasheet Volume 1 Processor Land and Signal Information Table 8 1 Processor Land List by Land Name Table 8 1 intel Processor Land List by Land Name Datasheet Volume 1 Land Name Land F18 F19 F21 F22 F24 F25 F27 F28 F30 F31 F32 F33 F34 G15 G16 G18 G19 G21 G22 G24 G25 G27 G28 G30 G31 G32 G33 H13 H14 H15 H16 H18 H19 H21 H22 H24 H25 H27 H28 H30 H31 H32 112 115 116 118 119 Buffer Type PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR P
34. DQ47 SA DQ 6 AL2 DQ02 SA DQ 46 AN39 DQ40 SA DQ 7 AL1 DQ03 SA DQ 47 AN40 DQ41 SA DQ 8 AN1 DQ15 SA DQ 48 AL40 DQ52 SA DQ 9 AN4 DQ12 SA DQ 49 AL37 DQ55 SA DQ 10 AR3 DQ08 SA DQ 50 138 DQ51 SA_DQ 11 AR4 DQ09 SA DQ 51 137 DQ50 SA_DQ 12 AN2 DQ14 SA_DQ 52 AL39 DQ54 SA_DQ 13 AN3 DQ13 SA 53 AL38 DQ53 SA DQ 14 AR2 DQ10 SA DQ 54 AJ39 DQ48 SA DQ 15 AR1 DQ11 SA DQ 55 AJ40 DQ49 SA_DQ 16 AV2 DQ21 SA_DQ 56 AG40 DQ61 SA DQ 17 AW3 DQ20 SA DQ 57 AG37 DQ63 SA_DQ 18 5 DQ16 SA_DQ 58 AE38 DQ59 SA DQ 19 AW5 DQ19 SA DQ 59 AE37 DQ58 SA DQ 20 AU2 DQ23 SA DQ 60 AG39 DQ62 SA DQ 21 AU3 DQ22 SA DQ 61 AG38 DQ60 SA DQ 22 AUS DQ18 SA DQ 62 AE39 DQ57 SA DQ 23 5 DQ17 SA DQ 63 AE40 DQ56 SA DQ 24 AY7 DQ28 SA DQ 64 AU12 DQ71 SA DQ 25 AU7 DQ30 SA DQ 65 AU14 DQ66 SA DQ 26 9 27 SA_DQ 66 AW13 DQ67 SA_DQ 27 9 DQ26 SA_DQ 67 AY13 DQ65 SA_DQ 28 AV7 DQ31 SA_DQ 68 AU13 DQ70 SA DQ 29 AW7 DQ29 SA DQ 69 AU11 DQ69 SA_DQ 30 AW9 DQ24 SA_DQ 70 AY12 DQ64 SA DQ 31 AY9 DQ25 SA DQ 71 AW12 DQ68 SA DQ 32 AU35 DQ36 SA DQ 33 AW37 DQ37 SA DQ 34 AU39 DQ32 SA DQ 35 AU36 DQ33 SA DQ 36 AW35 DQ38 SA DQ 37 AY36 DQ39 SA DQ 38 AU38 DQ35 SA DQ 39 AU37 DQ34 Datasheet Volume 1 m 8 DDR Data Swizzling tel Table 9 2 DDR Data Swizzling Table 9 2 DDR Data Swizzling table Channel B table Cha
35. ES 5 Tsustained storage media for a sustained period of time 40 C 5 6 The ambient storage temperature in shipping on Tshort term storage media for a short period of time 20 C 85 C The maximum device storage relative humidity RHsustained storage for a sustained period of time 60 at 24 C 6 7 A prolonged or extended period of time typically Timesustained storage associated with customer shelf life OMonthsi i 3O Months 7 Timesnortterm storage A short period of time 0 hours 72 hours Notes 1 Refers to a component device that is not assembled in a board or socket and is not electrically connected to a voltage reference or I O signal 2 Specified temperatures are not to exceed values based on data collected Exceptions for surface mount reflow are specified by the applicable JEDEC standard Non adherence may affect processor reliability 3 Tabsolute storage PPlies to the unassembled component only and does not apply to the shipping media moisture barrier bags or desiccant 4 Component product device storage temperature qualification methods may follow JESD22 A119 low temp and JESD22 A103 high temp standards when applicable for volatile memory 5 Intel branded products are specified and certified to meet the following temperature and humidity limits that are given as an example only Non Operating Temperature Limit 40 C to 70 C and Humidity 50 to 90 non condensing with a maximum wet bu
36. H o i O 05 o jn 10 vo vo IR 90 60 0 O O O 3 ex eoo 0 itin 10 v0 vo r9 IN 90 o0 0 O O JO HIN g m m m m m m v se c c EHE E E E E SE E E SE SE IE IE SE SE E 00 pin in fin fin gt iM M iM iMT 2 2 M M9 M9 9 9 M M9 M 9 m m m9 m 9 9 x o u O n ev s to r9 o o im JO WIL O ex eo st t0 r9 oo o j lt jajo JO Jw JL ul I jojojo u w w w w ud w w w w w w us jw w w u u uc ju u u u u u ju ju ju u u u u a SOS PS tS pS pth Pye pt ye pat pe pat ye pat ye pat ye pt yo pat Opt po pat fo prt pO pt po yt a SPS PPS SO Pt tO 0 baa SN PY YS S SO OO S O10 e 2 n pt OO e e P ps is a E w J 2 2 o ololjojo jojoljo 2 25 29 29 2 25 9 29 o o lOO lO o o o 9 9 9 gt a ST PPPS YO YO PO FO YO JO PO FO fo yo po fo yo yo po pt pet pet pt pet bad bad bad et baa bad bad pt baa tt Bnjo ommmmmmmnmmT mm mm T nmnmv 4T mpmmmmiiinT a 5119 gt a at d nde is arsit d s te ste 6 nis ns fe ns ne est rte f ns sts fe
37. Intel VT d read prefetching snarfing that is translations within a cacheline are not stored in an internal buffer for reuse for subsequent translations No support for advance fault reporting No support for super pages No support for Intel VT d translation bypass address range such usage models need to be resolved with VMM help in setting up the page tables correctly 41 8 Technologies 3 3 42 Intel Trusted Execution Technology Intel TXT Intel Trusted Execution Technology Intel TXT defines platform level enhancements that provide the building blocks for creating trusted platforms The Intel TXT platform helps to provide the authenticity of the controlling environment such that those wishing to rely on the platform can make an appropriate trust decision The Intel TXT platform determines the identity of the controlling environment by accurately measuring and verifying the controlling software Another aspect of the trust decision is the ability of the platform to resist attempts to change the controlling environment The Intel TXT platform will resist attempts by software processes to change the controlling environment or bypass the bounds set by the controlling environment Intel TXT is a set of extensions designed to provide a measured and controlled launch of system software that will then establish a protected environment for itself and any additional software that it may execute These extensions enhanc
38. MLE could consist of a virtual machine monitor an OS or an application In addition Intel TXT requires the system to contain a TPM v1 2 as defined by the Trusted Computing Group and specific software for some uses For more information see http www intel com technology security Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain computer system software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Intel Active Management Technology requires the computer system to have an Intel R AMT enabled chipset network hardware and software as well as connection with a power source and a corporate network connection Setup requires configuration by the purchaser and may require scripting with the management console or further integration into existing security frameworks to enable certain functionality It may also require modifications of implementation of new business processes With regard to notebooks Intel AMT may not be available or certain capabilities may be limited over a host OS based VPN or when connecting wirelessly on battery power sleeping hibernating or powered off For more information see http www intel com tech
39. Primary Planes A B and C Planes A B and C are the main display planes and are associated with Pipes A B and C respectively Sprite A B and C Sprite A and Sprite B are planes optimized for video decode and are associated with Planes A and B respectively Sprite A and B are also double buffered Cursors A B and C Cursors A and B are small fixed sized planes dedicated for mouse cursor acceleration and are associated with Planes A and B respectively These planes support resolutions up to 256 x 256 each Video Graphics Array VGA VGA is used for boot safe mode legacy games and so on It can be changed by an application without operating system driver notification due to legacy requirements Datasheet Volume 1 Interfaces 2 4 2 2 2 4 2 3 2 4 3 2 4 4 Note Display Pipes The display pipe blends and synchronizes pixel data received from one or more display planes and adds the timing of the display output device upon which the image is displayed The display pipes A B and C operate independently of each other at the rate of 1 pixel per clock They can attach to any of the display ports Each pipe sends display data to eDP or to the PCH over the Intel Flexible Display Interface Intel FDI Display Ports The display ports consist of output logic and pins that transmit the display data to the associated encoding logic and send the data to the display device that is LVDS HDMI DVI SDVO and so o
40. RAS RAS Control Signal This signal is used with SB_CAS and SB_WE O along with SB_CS to define the SRAM Commands DDR3 SB CAS CAS Control Signal This signal is used with SB_RAS and SB_WE Oo along with SB_CS to define the SRAM Commands DDR3 Data Strobes SB_DQS 8 0 and its complement signal group make SB_DQS 8 0 up a differential strobe pair The data is captured at the crossing point I O SB_DQS 8 0 of SB_DQS 8 0 and its SB_DQS 8 0 during read and write DDR3 transactions SB_DQ 63 0 Data Bus Channel B data signal interface to the SDRAM data bus 1 0 DDR3 SB MAT15 0 Memory Address These signals are used to provide the multiplexed MA 15 0 row and column address to the SDRAM DDR3 SDRAM Differential Clock Channel B SDRAM Differential clock SB CK 3 0 signal pair The crossing of the positive edge of SB CK and the SB_CK 3 0 negative edge of its complement SB_CK are used to sample the DDR3 command and control signals on the SDRAM Clock Enable 1 per rank These signals are used to Initialize the SDRAMs during power up Oo SB CKE 3 0 B 3 0 e Power down SDRAM ranks DDR3 e Place all SDRAM ranks into and out of self refresh during STR Chip Select 1 per rank These signals are used to select particular o SB_CS 3 0 SDRAM components during the active state There is one Chip Select DDR3 for each SDRAM rank SB ODT 3 0 On Die Termination Active Termination Control DDR3 Memory Reference and Compensation
41. Standard New Instructions Intel AES NI that are a set of Single Instruction Multiple Data SIMD instructions that enable fast and secure data encryption and decryption based on the Advanced Encryption Standard AES Intel AES NI are valuable for a wide range of cryptographic applications for example applications that perform bulk encryption decryption authentication random number generation and authenticated encryption AES is broadly accepted as the standard for both government and industry applications and is widely deployed in various protocols AES NI consists of six Intel SSE instructions Four instructions namely AESENC AESENCLAST AESDEC and AESDELAST facilitate high performance AES encryption and decryption The other two AESIMC and AESKEYGENASSIST support the AES key expansion procedure Together these instructions provide a full hardware for support AES offering security high performance and a great deal of flexibility PCLMULQDQ Instruction The processor supports the carry less multiplication instruction PCLMULQDQ PCLMULQDO is a Single Instruction Multiple Data SIMD instruction that computes the 128 bit carry less multiplication of two 64 bit operands without generating and propagating carries Carry less multiplication is an essential processing component of several cryptographic systems and standards Hence accelerating carry less multiplication can significantly contribute to achieving high speed secure comput
42. VSS VSS Land AN22 AN24 AN27 AN30 AN31 AN32 AN33 AN34 AN35 AN36 5 6 AN7 AN8 AP1 AP11 AP14 AP17 AP22 AP25 AP27 AP30 AP36 AP37 AP4 AP40 5 AR11 AR14 AR17 AR18 AR19 AR27 AR30 AR36 AR5 AT1 AT10 AT12 AT13 5 AT16 AT17 AT2 AT25 AT27 Buffer Type GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Dir Datasheet Volume 1 Processor Land and Signal Information Table 8 1 Processor Land List by Land Name Table 8 1 intel Processor Land List by Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Datasheet Volume 1 Land Name Land AT28 AT29 AT3 AT30 AT31 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AT39 AT4 AT40 AT5 AT6 AT7 AT8 AT9 AU1 AU15 AU26 AU34 AUA AUG AU8 AV10 AV11 AV14 AV17 AV3 AV35 AV38 AV6 AW10 AW11 AW14 AW16 AW36 AW6 AY11 AY14 AY18 AY35 AY4 AY6 Buffer Type GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
43. a C1E sub state hint All cores are in a power state lower that C1 C1E but the package low power state is limited to C1 C1E using the PMG CST CONFIG CONTROL MSR All cores have requested C1 using HLT or MWAIT C1 and C1E auto promotion is enabled in IA32 MISC ENABLES No notification to the system occurs upon entry to C1 C1E Datasheet Volume 1 55 4 2 5 3 4 2 5 4 4 3 4 3 1 56 Power Management Package C3 State A processor enters the package C3 low power state when e At least one core is in the C3 state e The other cores are in a C3 or lower power state and the processor has been granted permission by the platform The platform has not granted a request to a package C6 state but has allowed a package C6 state In package C3 state the L3 shared cache is valid Package C6 State A processor enters the package C6 low power state when e At least one core is in the C6 state e The other cores are in a C6 or lower power state and the processor has been granted permission by the platform In package C6 state all cores have saved their architectural state and have had their core voltages reduced to zero volts The L3 shared cache is still powered and snoopable in this state The processor remains in package C6 state as long as any part of the L3 cache is active Integrated Memory Controller IMC Power Management The main memory is power managed during normal operation and in low power ACPI Cx states
44. acceleration features that go beyond the original VGA standard Logical 128 Bit Fixed BLT and 256 Fill Engine This BLT engine accelerates the GUI of Microsoft Windows operating systems The 128 bit BLT engine provides hardware acceleration of block transfers of pixel data for many common Windows operations The BLT engine can be used for the following Move rectangular blocks of data between memory locations Data alignment To perform logical operations raster ops The rectangular block of data does not change as it is transferred between memory locations The allowable memory transfers are between cacheable system memory and frame buffer memory frame buffer memory and frame buffer memory and within system memory Data to be transferred can consist of regions of memory patterns or solid color fills A pattern is always 8 x 8 pixels wide and may be 8 16 or 32 bits per pixel The BLT engine expands monochrome data into a color depth of 8 16 or 32 bits BLTs can be either opaque or transparent Opaque transfers move the data specified to the destination Transparent transfers compare destination color to source color and write according to the mode of transparency selected Data is horizontally and vertically aligned at the destination If the destination for the BLT overlaps with the source memory location the BLT engine specifies which area in memory to begin the BLT transfer Hardware is included for all 256 raster operati
45. be dropped Re issues Configuration cycles that have been previously completed with the Configuration Retry status PCI Express reference clock is 100 MHz differential clock Power Management Event PME functions Dynamic width capability Message Signaled Interrupt MSI and MSI X messages Polarity inversion Note The processor does not support PCI Express Hot Plug Datasheet Volume 1 13 Introduction 1 2 3 Direct Media I nterface DMI DMI 2 0 support Four lanes in each direction 5 GT s point to point DMI interface to PCH is supported Raw bit rate on the data pins of 5 0 Gb s resulting in a real bandwidth per pair of 500 MB s given the 8b 10b encoding used to transmit data across this interface Does not account for packet overhead and link maintenance Maximum theoretical bandwidth on interface of 2 GB s in each direction simultaneously for an aggregate of 4 GB s when DMI x4 Shares 100 MHz PCI Express reference clock 64 bit downstream address format however the processor never generates an address above 64 GB Bits 63 36 will always be zeros 64 bit upstream address format but the processor responds to upstream read transactions to addresses above 64 GB addresses where any of Bits 63 36 are nonzero with an Unsupported Request response Upstream write transactions to addresses above 64 GB will be dropped Supports the following traffic types to or from the PCH DMI gt DRAM DMI gt
46. buffers are not 3 3 V tolerant Refer to the PCIe specification Direct Media Interface signals These signals are compatible with PCI Express 2 0 DMI Signaling Environment AC Specifications but are DC coupled The buffers are not 3 3 V tolerant CMOS CMOS buffers DDR3 DDR3 buffers 1 5 V tolerant A Analog reference or output May be used as a threshold voltage or for buffer compensation Ref Voltage reference signal Asynchronous Signal has no timing relationship with any reference clock Note 1 Qualifier for a buffer type Datasheet Volume 1 Signal Description intel 6 1 System Memory Interface Signals Table 6 2 Memory Channel A Signals Signal Name Description Bue Tue SA BSI2 0 Bank Select These signals define which banks are selected within 0 BS 2 0 each SDRAM rank DDR3 SA WE Write Enable Control Signal This signal is used with SA_RAS and SA_CAS along with SA_CS to define the SDRAM Commands DDR3 SA RAS RAS Control Signal This signal is used with SA CAS and SA WE O along with SA_CS to define the SRAM Commands DDR3 SA CAS CAS Control Signal This signal is used with SA_RAS and SA_WE O along with SA_CS to define the SRAM Commands DDR3 Data Strobes SA_DQS 8 0 and its complement signal group make SA_DQS 8 0 up a differential strobe pair The data is captured at the crossing point I O SA_DQS 8 0 of SA_DQS 8 0 and its SA
47. cores is selected Software requested transitions are accepted at any time If a previous transition is in progress the new transition is deferred until the previous transition is completed The processor controls voltage ramp rates internally to ensure glitch free transitions Because there is low transition latency between P states a significant number of transitions per second are possible Low Power Idle States When the processor is idle low power idle states C states are used to save power More power savings actions are taken for numerically higher C states However higher C states have longer exit and entry latencies Resolution of C states occur at the thread processor core and processor package level Thread level C states are available if Intel HT Technology is enabled Long term reliability cannot be assured unless all the Low Power Idle States are enabled Datasheet Volume 1 Power Management Figure 4 2 Figure 4 3 Table 4 8 Idle Power Management Breakdown of the Processor Cores Thread O Thread 1 Thread O Thread 1 Core 0 State Core 1 State Processor Package State Entry and exit of the C States at the thread and core level are shown in Figure 4 3 Thread and Core C State Entry and Exit we MWAIT C6 Peaster Paneg P SVO Read C1E Enabled P LV2 1 0 Read amp i While individual threads can request l
48. current at 0 25 Vccro 0 4 mA Ileak050 leakage current at 0 50 Vccio 0 2 mA Ileak075 leakage current at 0 75 Vccro 0 13 mA Ileak100 leakage current at Vccro 0 10 mA Notes 1 supplies the PECI interface PECI behavior does not affect Vccro min max specifications 2 The leakage specification applies to powered devices on the PECI bus 3 The PECI buffer internal pull up resistance measured at 0 75 V cjo 7 11 3 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt triggered input design for improved noise immunity Use Figure 7 2 as a guide for input buffer design Figure 7 2 Input Device Hysteresis YM Vitp 7 wy Maximum Ve High Range Wyss P Minimum i Valid Input Hysteresis Signal Range Maximum Vy AC A Mini LW Minimum Vy NN Low Range SS PECI Ground NK GAMMA 88 Datasheet Volume 1 91 92 Electrical Specifications Datasheet Volume 1 Processor Land and Signal Information L D 8 8 1 Note Note Processor Land and Signal Information Processor Land Assignments The processor land map is shown in Figure 8 1 Table 8 1 provides a listing of all processor lands ordered alphabetically by land name SA ECC CB 7 0 and SB ECC CB 7 0 Lands are RSVD on Desktop 3rd Generation Intel Core i7 i5 processors PE TX 3 0 PE TX
49. delivery as well as the ability to virtualize the local APIC the APIC register set can be accessed only through MSR based interfaces in the x2APIC mode The Memory Mapped IO MMIO interface used by xAPIC is not supported in the x2APIC mode e The semantics for accessing APIC registers have been revised to simplify the programming of frequently used APIC registers by system software Specifically the software semantics for using the Interrupt Command Register ICR and End Of Interrupt EOI registers have been modified to allow for more efficient delivery and dispatching of interrupts The x2APIC extensions are made available to system software by enabling the local x2APIC unit in the x2APIC mode To benefit from x2APIC capabilities a new operating system and a new BIOS are both needed with special support for the x2APIC mode The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendibility for future Intel platform innovations Intel x2APIC technology may not be available on all SKUs For more information refer to the Intel 64 Architecture x2APIC specification at http www intel com products processor manuals Supervisor Mode Execution Protection SMEP The processor introduces a new mechanism that provides next level of system protection by blocking malicious software attacks from user mode code when the system is running in the highest privilege level This technology helps to prot
50. family Desktop Intel Celeron processor family the usage of this pin was changed as follows The pin is configured on the package to be same as 2nd Generation Intel Core processor family desktop Intel Pentium processor family desktop Intel Celeron processor family desktop This pin must be pulled high on the motherboard when using a dual rail voltage regulator Datasheet Volume 1 Signal Description 6 11 Processor Power Signals Table 6 13 Processor Power Signals 6 12 Signal Name Description Direction Buffer Type Table 6 14 Sense Signals VCC Processor core power rail Ref VCCIO Processor power for I O Ref VDDQ Processor I O supply voltage for DDR3 Ref VCCAXG Graphics core power supply Ref VCCPLL VCCPLL provides isolated power for internal processor PLLs Ref VCCSA System Agent power supply Ref VIDALERT VIDSCLK and VIDSCLK comprise a three signal VIDSOUT serial synchronous interface used to transfer power CMOS I OD O VIDSCLK management information between the processor and the ODO VIDALERT voltage regulator controllers This serial VID interface replaces CMOS I the parallel VID interface on previous processors Voltage selection for VCCSA 0 1 VCCSA_VID CMOS Note 1 The VCCSA VID can toggle at most once in 500 uS The slew rate of VCCSA VID is 1 V nS Sense Signals Direction Signal Name Description Buffer Type VCC S
51. memory into self refresh mode during C3 C6 to allow the system to remain in the lower power states longer Processors routinely save power during runtime conditions by entering the C3 C6 state Intel RMPM is an indirect method of power saving that can have a significant effect on the system as a whole Intel Graphics Performance Modulation Technology Intel GPMT Intel Graphics Power Modulation Technology Intel GPMT is a method for saving power in the graphics adapter while continuing to display and process data in the adapter This method will switch the render frequency and or render voltage dynamically between higher and lower power states supported on the platform based on render engine workload In products where Intel Graphics Dynamic Frequency also known as Turbo Boost Technology is supported and enabled the functionality of Intel GPMT will be maintained by Intel Graphics Dynamic Frequency also known as Turbo Boost Technology Graphics Render C State Render C State RC6 is a technique designed to optimize the average power to the graphics render engine during times of idleness of the render engine Render C state is entered when the graphics render engine blitter engine and the video engine have no workload being currently worked on and no outstanding graphics memory transactions When the idleness condition is met then the Processor Graphics will program the VR into a low voltage state 90 V through the SVID bus Lon
52. of the processor TDO provides the serial output needed for JTAG Drai specification support TMS Test Mode Select A JTAG specification support signal used by I debug tools CMOS TRST Test Reset This signal resets the Test Access Port TAP logic I TRST must be driven low during power on Reset CMOS Datasheet Volume 1 Signal Description 6 9 Error and Thermal Protection Signals Table 6 11 Error and Thermal Protection Signals Signal Name Description Direction Buffer Type Catastrophic Error This signal indicates that the system has experienced a catastrophic error and cannot continue to operate The processor will set this for non recoverable machine check errors or other unrecoverable internal errors Datasheet Volume 1 CATERR On the processor CATERR is used for signaling the following o types of errors CMOS Legacy MCERRs CATERR is asserted for 16 BCLKs Legacy IERRs CATERR remains asserted until warm or cold reset PECI Platform Environment Control Interface A serial 1 0 PECI sideband interface to the processor it is used primarily for A h thermal power and error management eynenronous Processor Hot PROCHOT goes active when the processor temperature monitoring sensor s detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been CMO
53. the Processor 30 PCI PCI Bridge PCI representing PCI Compatible Express PEGO root PCI Host Bridge Da Express ports Device Device 1 and Device O Device 6 DMI PCI Express extends the configuration space to 4096 bytes per device function as compared to 256 bytes allowed by the Conventional PCI Specification PCI Express configuration space is divided into a PCI compatible region that consists of the first 256 bytes of a logical device s configuration space and an extended PCI Express region that consists of the remaining configuration space The PCI compatible region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express configuration access mechanism described in the PCI Express Enhanced Configuration Mechanism section The PCI Express Host Bridge is required to translate the memory mapped PCI Express configuration space accesses from the host processor to PCI Express configuration cycles To maintain compatibility with PCI configuration addressing mechanisms it is recommended that system software access the enhanced configuration space using 32 bit operations 32 bit aligned only See the PCI Express Base Specification for details of both the PCI compatible and PCI Express Enhanced configuration mechanisms and transaction rules Datasheet Volume 1 Interfaces 2 2 3 PCI Express Port intel The PCI Express i
54. use of the Processor Graphics Controller GT and a x16 PCI Express Graphics PEG device The processor supports a maximum of 2 displays connected to the PEG card in parallel with up to 2 displays connected to the processor and PCH When supporting Multi Graphics Multi Monitors drag and drop between monitors and the 2x8 PEG is not supported Datasheet Volume 1 37 intel Interfaces 2 6 2 6 1 Table 2 5 38 Platform Environment Control Interface PECI The PECI is a one wire interface that provides a communication channel between a PECI client processor and a PECI master The processor implements a PECI interface to Allow communication of processor thermal and other information to the PECI master Read averaged Digital Thermal Sensor DTS values for fan speed control Interface Clocking Internal Clocking Requirements Reference Clock Reference Input Clock Input Frequency Associated PLL BCLK 0 BCLK 2 0 100 MHz Processor Memory Graphics PCIe DMI FDI 58 Datasheet Volume 1 Technologies 3 3 1 3 1 1 intel Technologies This chapter provides a high level description of Intel technologies implemented in the processor The implementation of the features may vary between the processor SKUs Details on the different technologies of Intel processors and other relevant external notes are located at the Intel technology web site http www intel com technology I
55. voltage level The processor supports Boundary Scan JTAG IEEE 1149 1 2001 and IEEE 1149 6 2003 standards A small portion of the I O lands may support only one of those standards 82 Datasheet Volume 1 Electrical Specifications 7 9 Table 7 3 intel Storage Conditions Specifications Environmental storage condition limits define the temperature and relative humidity to which the device is exposed to while being stored in a moisture barrier bag The specified storage conditions are for component level prior to board attach Table 7 3 specifies absolute maximum and minimum storage temperature limits that represent the maximum or minimum device condition beyond which damage latent or otherwise may occur The table also specifies sustained storage temperature relative humidity and time duration limits These limits specify the maximum or minimum device storage conditions for a sustained period of time Failure to adhere to the following specifications can affect long term reliability of the processors conditions outside sustained limits but within absolute maximum and minimum ratings quality and reliability may be affected Storage Condition Ratings Symbol Parameter Min Max Notes The non operating device storage temperature Tabsolute storage Damage latent or otherwise may occur when 25 C 125 C 1 2 3 4 exceeded for any length of time The ambient storage temperature in shipping
56. while the processor is at package C3 or deeper power state During EPG the Vccjo internal voltage rail will be powered down while Vppg and the un gated Vccig will stay powered on The processor will transition in and out of DDR EPG mode on an as needed basis without any external pins or signals There is no change to the signals driven by the processor to the DIMMs during DDR IO EPG mode During EPG mode all the DDR IO logic will be powered down except for the Physical Control registers that are powered by the un gated Vccro power supply Unlike S3 exit at DDR EPG exit the DDR will not go through training mode Rather it will use the previous training information retained in the physical control registers and will immediately resume normal operation Datasheet Volume 1 59 4 4 Note Note 4 5 4 6 4 6 1 4 6 2 4 6 3 Caution 60 Power Management PCI Express Power Management e Active power management support using LOs and L1 states e All inputs and outputs disabled in L2 L3 Ready state PCIe interface does not support Hot Plug An increase in power consumption may be observed when PCIe Active State Power Management ASPM capabilities are disabled DMI Power Management Active power management support using LOs L1 state Graphics Power Management Intel Rapid Memory Power Management Intel RMPM also known as CxSR The Intel Rapid Memory Power Management Intel RMPM puts rows of
57. 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 2 E 0 47500 2 F 0 48000 3 0 0 48500 3 1 0 49000 3 2 0 49500 3 3 0 50000 3 4 0 50500 3 5 0 51000 3 6 0 51500 3 7 0 52000 3 8 0 52500 3 9 0 53000 3 A 0 53500 3 B 0 54000 3 C 0 54500 3 D 0 55000 3 E 0 55500 3 F 0 56000 4 0 0 56500 4 1 0 57000 4 2 0 57500 4 3 0 58000 4 4 0 58500 4 5 0 59000 4 6 0 59500 4 7 0 60000 4 8 0 60500 4 9 0 61000 4 A 0 61500 4 B 0 62000 4 C 0 62500 4 D 0 63000 4 0 63500 4 0 64000 5 0 0 64500 5 1 0 65000 5 2 0 65500 5 3 0 66000 5 4 0 66500 5 5 0 67000 5 6 0 67500 5 7 0 68000 5 8 0 68500 5 9 0 69000 5 A 0 69500 5 B 0 70000 5 C 0 70500 1 2 3 4 5 6 VID VID VID VID VID VID VID VID 7 Datasheet Volume 1 78 intel Electrical Specifications ion Sheet 3 of 3 ini VR 12 0 Voltage Identification Def Table 7 1 x ololjo o ojo o jojo ololo lolojo olo jo olo ololo ololo lolo o olo o olo o z o mn o n o 0 o i O i O i o i O i o i O i o i O i O o 15 O
58. 1 07500 A 7 1 08000 A 8 1 08500 A 9 1 09000 A A 1 09500 A B 1 10000 A C 1 10500 A D 1 11000 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HEX Vcc_max 1 0 33000 E 0 39500 F 0 40000 0 0 0 00000 O 1 0 25000 0 2 0 25500 0 3 0 26000 0 4 0 26500 0 5 0 27000 0 6 0 27500 0 7 0 28000 0 8 0 28500 0 9 0 29000 0 A 0 29500 0 B 0 30000 0 C 0 30500 0 D 0 31000 0 E 0 31500 0 F 0 32000 110 0 32500 1 1 2 0 33500 1 3 0 34000 1 4 0 34500 1 5 0 35000 1 6 0 35500 1 7 0 36000 1 8 0 36500 1 9 0 37000 1 A 0 37500 1 B 0 38000 1 C 0 38500 1 D 0 39000 1 1 2 0 0 40500 2 1 0 41000 2 2 0 41500 2 3 0 42000 2 4 0 42500 2 5 0 43000 2 6 0 43500 2 7 0 44000 2 8 0 44500 2 9 0 45000 2 A 0 45500 2 B 0 46000 2 C 0 46500 2 D 0 47000 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 2 3 4 5 6 7
59. 3 0 PE TX4 3 0 Single Ended Analog Input PEG ICOMPO PEG COMPI PEG RCOMPO DMI Differential DMI Input DMI RX 3 0 DMI RX 3 0 Differential DMI Output DMI TX 3 0 DMI TX2 3 0 Intel FDI Single Ended FDI Input FDI FSYNC 1 0 FDI LSYNC 1 0 FDI INT Differential FDI Output FDI TX 7 0 FDI_TX 7 0 Single Ended Analog Input FDI COMPIO FDI ICOMPO Notes 1 Refer to Chapter 8 for signal description details 2 SAand SB refer to DDR3 Channel A and DDR3 Channel B 3 The maximum rise fall time of UNCOREPWRGOOD is 20 ns 4 TX 3 0 PE TX 3 0 and PE RX 3 0 PE RX2 3 0 signals are only used for platforms that support 20 PCIe lanes These signals are reserved on Desktop 3rd Generation Intel Core i7 i5 processors Note All Control Sideband Asynchronous signals are required to be asserted de asserted for at least 10 BCLKs with maximum T ise Tfa of 6 ns in order for the processor to recognize the proper signal state See Section 7 10 for the DC specifications 7 8 Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic Intel recommends the processor be first in the TAP chain followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Two copies of each signal may be required with each driving a different
60. 3 0 and PE RX 3 0 PE RX 3 0 Lands are RSVD on Desktop 3rd Generation Intel Core i7 i5 processors Desktop Intel Pentium processors and Desktop Intel Celeron processors Datasheet Volume 1 93 intel Figure 8 1 LGA Socket Land Map Processor Land and Signal Information 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 gt AHE PpBaomnozruxrzEzvaic lt s lt PFRRERHRSEB 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 94 Datasheet Volume 1 Table 8 1 Processor Land and Signal Information Processor Land List by Land Name Table 8 1 intel Processor Land List by Land Name Land Name BCLK ITP BCLK ITP BCLK 0 BCLK 0 BPM O BPM 1 BPM 2 BPM 3 BPM 4 5 6 BPM BPM BPM 7 CATERR CFG 0 CFG 1 CFG 2 CFG 3 CFG 4 CFG 5 CFG 6 CFG 7 CFG 8 CFG 9 CFG 10 CFG 11 CFG 12 CFG 13 CFG 14 CFG 15 CFG 16 CFG 17 DBR MI RX 0 MI RX 1 MI RX 2 MI RX 3 MI RX 0 MI RX 1 MI RX 2 MI RX 3 MI TX 0 MI TX 1 MI TX 2 TX 3 MI TX 0 MI TX 1 MI_TX 2 oj g g g gj g g g gj g olgj gojoj Datasheet Volume 1 Land C40 D40 w2 H40 H38 G38 G40 G39 F38 E40 F40 E37 H36 136 137 K36 L36 N35 L37 M36 138 35 M38 N36 N38 N39 N37 N40 G37 G36 E39 w5 v3
61. 32 A11 A7 AA3 AB8 AF8 Buffer Type PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Analog PWR PWR PWR PWR PWR Dir Land Name VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO_SEL VCCIO_SENSE VCCPLL VCCPLL VCCSA VCCSA VCCSA Land AG33 AJ16 AJ17 AJ26 AJ28 AJ32 AK15 AK17 AK19 AK21 AK23 AK27 AK29 AK30 B9 D10 D6 E3 E4 G3 G4 13 14 17 18 L3 L4 L7 M13 3 N4 N7 R3 R4 R7 U3 U4 U7 V8 w3 P33 AB4 AK11 AK12 H10 H11 H12 Buffer Type PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR N A Analog PWR PWR PWR PWR PWR Dir Datasheet Volume 1 Processor Land and Signal Information Table 8 1 Processor Land List by Land Name Table 8 1 intel Processor Land List by Land Name Land Name VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA SENSE VCCSA VID VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VD
62. 36 V37 V38 v39 V40 V5 W6 Y5 Y8 A4 AV39 AY37 B3 B36 M32 AB3 Buffer Type GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Analog Analog Analog Dir 88 107 Processor Land and Signal Information 108 Datasheet Volume 1 DDR Data Swizzling inte 9 DDR Data Swizzling To achieve better memory performance and timing Intel Design performed DDR Data pin swizzling that allows a better use of the product across different platforms Swizzling has no effect on functional operation and is invisible to the operating system software However during debug swizzling needs to be taken into consideration Therefore swizzling information is presented in this chapter When placing a DIMM logic analyzer the design engineer must pay attention to the swizzling table in order to be able to debug memory efficiently Datasheet Volume 1 109 intel 110 DDR Data Swizzling Table 9 1 DDR Data Swizzling Table 9 1 DDR Data Swizzling Table Channel A Table Channel A Land Name Land MC Land Name Land Name Land MC Land Name SA DQ 0 A23 DQ06 SA DQ 40 AR40 DQ44 SA DQ 1 AJA 5 SA_DQ 41 AR37 DQ45 SA_DQ 2 AL3 DQO1 SA DQ 42 AN38 DQ43 SA DQ 3 ALA DQOO SA DQ 43 AN37 DQ42 SA DQ 4 12 DQ04 SA DQ 44 AR39 DQ46 SA DQ 5 All DQ07 SA DQ 45 AR38
63. 40 i3 3240T i5 3330 i5 3330S i5 3335S i5 3350P processors Added Desktop 3rd Generation Intel Core i3 3210 processor 005 Added Desktop Intel Pentium G2130 G2020 G2020T G2010 processor January 2013 Added Desktop Intel Celeron 1620 G1610 G1610T processor 88 Datasheet Volume 1 Introduction 1 Note Note Note Note Note intel Introduction The Desktop 3rd Generation Intel Core processor family Desktop Intel Pentium processor family and Desktop Intel Celeron processor family are the next generation of 64 bit multi core processors built on 22 nanometer process technology The processors are designed for a two chip platform The two chip platform consists of a processor and a Platform Controller Hub PCH and enables higher performance lower cost easier validation and improved x y footprint The processor includes an Integrated Display Engine Processor Graphics PCI Express ports and an Integrated Memory Controller The processor is designed for desktop platforms The processor offers either 6 or 16 graphic execution units EUs The number of EU engines supported may vary between processor SKUs The processor is offered in an 1155 land LGA package H2 Figure 1 1 shows an example desktop platform block diagram The Datasheet provides DC specifications pinout and signal definitions interface functional descriptions and additional feature information pertinent to t
64. AM28 DQ35 SB DQ 39 AM29 DQ32 Datasheet Volume 1 111 112 DDR Data Swizzling Datasheet Volume 1
65. Buffer RON DN CMD pull down Resistance 15 DDR3 Control Buffer Row pull up Resistance a DDR3 Control Buffer Ron_DN CTL pull down Resistance Input Leakage Current DQ CK i ov 0 75 u 0 2 Vppo 40 55 0 8 Vppo 4 0 9 VDDQ 31 4 Input Leakage Current CMD CTL i ov 0 85 gun u 0 2 Vppo 0 65 0 8 Vppo 1 10 VDDQ 1 65 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vy is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value Vip is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 and Voy may experience excursions above Vppg However input signal drivers must comply with the signal quality specifications 5 This is the pull up pull down driver resistance 6 Rrerm is the termination on the DIMM and in not controlled by the processor 7 The minimum and maximum values for these signals are programmable by BIOS to one of the two sets 8 SM DRAMPWROK must have a maximum of 15 ns rise or fall time over Vppo 0 55 200 mV and the edge must be monotonic 9 5 VREF is defined as Vppo 2 10 Ron tolerance is preliminary and might be subject to change 88 Datasheet Volume 1 Electrical Specifications intel
66. C implements aggressive CKE control to dynamically put the DRAM devices in a power down state The processor core controller can be configured to put the devices in active power down CKE de assertion with open pages or precharge power down CKE de assertion with all pages closed Precharge power down provides greater power savings but has a bigger performance impact since all pages will first be closed before putting the devices in power down mode If dynamic power down is enabled all ranks are powered up before doing a refresh cycle and all ranks are powered down at the end of refresh DRAM I O Power Management Unused signals should be disabled to save power and reduce electromagnetic interference This includes all signals associated with an unused memory channel Clocks can be controlled on a per SO DIMM basis Exceptions are made for per SO DIMM control signals such as CS CKE and ODT for unpopulated SO DIMM slots The I O buffer for an unused signal should be tri stated output driver disabled the input receiver differential sense amp should be disabled and any DLL circuitry related ONLY to unused signals should be disabled The input path must be gated to prevent spurious results due to noise on the unused signals typically handled automatically when input receiver is disabled DDR Electrical Power Gating EPG The DDR I O of the processor supports on die Electrical Power Gating DDR EPG during normal operation SO mode
67. CC Raw Card B Dual Ranked x8 unbuffered non ECC Raw Card C Single Ranked x16 unbuffered non ECC The processor supports memory configurations that mix DDR3 DIMMs DRAMs with DDR3L DIMMs DRAMs running at 1 5 V Volume 1 23 intel Interfaces Table 2 2 Supported UDIMM Module Configurations Dum Dave DRAM nin Physica T4 m Banks Page Version apacity Technology Organization Devices RE E m Size Desktop Platforms Unbuffered Non ECC Supported DIMM Module Configurations 1 GB 1 Gb 128MX8 8 1 14 10 8 8K A 2 GB 2 Gb 128 M X 16 8 1 1510 8 8K 4 GB 4 Gb 512MX8 8 1 15 10 8 8K 2 GB 1 Gb 128MX8 16 2 14 10 8 8K B 4 GB 2 Gb 256M X8 16 2 15 10 8 8K 8 GB 4 Gb 512MX8 16 2 16 10 8 8K C 1GB 2 Gb 128M X 16 4 1 14 10 8 16K Note 1 DIMM module support is based on availability and is subject to change Table 2 3 Supported SO DIMM Module Configurations AIO Only pl DIMM DRAM 2 Physical ion col Banks Page Version Capacity Technology Organization Devices Device Address Inside Size Ranks Bits DRAM 2 GB 2 Gb 128 Mx 16 8 14 10 8 8K a 4 GB 4 Gb 256 Mx 16 8 2 15 10 8 8K 1 GB 1 Gb 128M x8 8 1 14 10 8 8K B 2 GB 2 Gb 256Mx8 8 1 15 10 8 8K 4 GB 4 Gb 512Mx8 8 1 16 10 8 8K 1 GB 2 Gb 128 M x 16 4 1 14 10 8 8K 2 GB 4 Gb 256M x 16 4 1 15 10 8 8K 2 GB 1 Gb 128Mx8 16 2 14 10 8 8K F 4 GB 2 Gb 256Mx8 16 2 15 10 8 8
68. Caution 50 Processor Core Power Management While executing code Enhanced Intel SpeedStep Technology optimizes the processor s frequency and core voltage based on workload Each frequency and voltage operating point is defined by ACPI as a P state When the processor is not executing code it is idle A low power idle state is defined by ACPI as a C state In general lower power C states have longer entry and exit latencies Enhanced Intel SpeedStep Technology The following are the key features of Enhanced Intel SpeedStep Technology Multiple frequency and voltage points for optimal performance and power efficiency These operating points are known as P states e Frequency selection is software controlled by writing to processor MSRs The voltage is optimized based on the selected frequency and the number of active processor cores If the target frequency is higher than the current frequency Vcc is ramped up in steps to an optimized voltage This voltage is signaled by the SVID bus to the voltage regulator Once the voltage is established the PLL locks on to the target frequency If the target frequency is lower than the current frequency the PLL locks to the target frequency then transitions to a lower voltage by signaling the target voltage on SVID bus All active processor cores share the same frequency and voltage In a multi core processor the highest frequency P state requested amongst all active
69. DQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VIDALERT VIDSCLK VIDSOUT VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Datasheet Volume 1 Land 110 K10 K11 L11 L12 M10 M11 M12 T2 34 AJ13 AJ14 AJ20 AJ23 AJ24 AR20 AR21 AR22 AR23 AR24 AU19 AU23 AU27 AU31 AV21 AV24 AV25 AV29 AV33 AW31 AY23 AY26 AY28 A37 C37 B37 A17 A23 A26 A29 A35 AA33 AA34 AA35 AA36 AA37 AA38 Buffer Type PWR PWR PWR PWR PWR PWR PWR PWR Analog CMOS PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR CMOS CMOS CMOS GND GND GND GND GND GND GND GND GND GND GND Dir I O Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land AA6 AB5 AC1 AC6 AD33 AD36 AD38 AD39 AD40 AD5 AD8 AE3 AE33 AE36 AF1 AF34 AF36 AF37 AF40 AF5 AF6 AF7 AG36 AH2 AH3 AH33 AH36 AH37 AH38 AH39 AH40 AH5 AH8 AJ12 AJ15 AJ18 AJ21 AJ25 AJ27 AJ36 AJ5 AK1 AK10 AK13 AK14 AK16 AK22 Buffer Type o 0
70. Desktop 3rd Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 January 2013 Document Number 326764 005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT A Mission Critical Application is any application in which failure of the Intel Product could result directly or indirectly in personal injury or death SHOULD YOU PURCHASE OR USE INTEL S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES SUBCONTRACTORS AND AFFILIATES AND THE DIRECTORS OFFICERS AND EMPLOYEES OF EACH HARMLESS AGAINST ALL CLAIMS COSTS DAMAGES AND EXPENSES AND REASONABLE ATTORNEYS FEES ARISING OUT OF DIRECTLY OR INDIRECTLY ANY CLAIM OF PRODUCT LIABILITY PERSONAL INJURY OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION WHETHER OR NOT INTEL OR ITS SUBCONT
71. ECI Host Clients Connection sssssssssssssssenemen nemen emen 90 7 52 Input Device Eysteresiso a tenete eve diee 91 8 1 LGA Socket Land Map nen ra penna re exe RU CE DARF NRI REA TEEDE RM 94 Tables 1 1 Desktop 3rd Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family SKUS 16 122 Terminology CR 19 153 Related 5 22 2 1 Processor DIMM Support Summary by 23 2 2 Supported UDIMM Module Configurations ccecceeee eene 24 2 3 Supported SO DIMM Module Configurations AIO Only sss 24 2 4 System Memory Timing Support I IU nnne nnn nnns 25 2 5 Reference ClO CK evince VERE Rue Candia cies dang angie Fed Rin V glia UR R de 38 4 1 System States iis ke pce SYRIEN 48 4 2 Processor Core Package State Support nene 48 4 3 Integrated Memory Controller States ccc
72. ENSE and VSS SENSE provide an isolated low or measure voltage near the silicon VCC SENSE impedance connection to the processor core voltage and 0 VSS_SENSE ground They can be used to sense or measure voltage near the Analog silicon VAXG_SENSE VAXG_SENSE and VSSAXG_SENSE provide an isolated low VSSAXG SENSE impedance connection to the voltage and ground They Analog can be used to sense or measure voltage near the silicon VCCIO_SENSE and VSS_SENSE_VCCIO provide an isolated low VCCIO_SENSE impedance connection to the processor VCCIO voltage and 0 VSS_SENSE_VCCIO ground They can be used to sense or measure voltage near the Analog silicon VCCSA_SENSE provide an isolated low impedance connection o VCCSA_SENSE to the processor system agent voltage It can be used to sense Analog Datasheet Volume 1 73 Signal Description intel Ground and Non Critical to Function NCTF Signals 6 13 Table 6 15 Ground and Non Critical to Function NCTF Signals 6 14 Signal Name Description Direction Buffer Type VSS Processor ground node GND VSS_NCTF BGA Only Non Critical to Function These signals are for package mechanical reliability Processor Internal Pull Up Pull Down Resistors Table 6 16 Processor Internal Pull Up Pull Down Resistors 74 Signal Name Pull Up Pull Down Rail Value BPM 7 0 Pull Up VCC
73. I 9 SB DQ 10 SB DQ 11 SB DQ 12 SB DQ 13 SB DQ 14 SB DQ 15 SB DQ 16 SB DQ 17 SB DQ 18 SB DQ 19 SB DQ 20 SB DQ 21 SB DQ 22 SB 23 SB DQ 24 SB 25 SB DQ 26 SB DQ 27 SB DQ 28 SB DQ 29 SB DQ 30 SB 31 SB DQ 32 SB DQ 33 SB DQ 34 SB 35 SB 36 SB DQ 37 SB DQ 38 SB DQ 39 SB DQ 40 SB 41 SB 42 SB 43 SB_DQ 44 SB_DQ 45 SB_DQ 46 SB_DQ 47 SB_DQ 48 SB_DQ 49 SB_DQ 50 SB_DQ 51 SB_DQ 52 Datasheet Volume 1 Land AJ6 AJ7 AL7 AM7 AM10 AL10 AL6 AM6 9 AM9 AP7 AR7 AP10 AR10 AP6 AR6 AP9 AR9 AM12 AM13 AR13 AP13 AL12 AL13 AR12 AP12 AR28 AR29 AL28 AL29 AP28 AP29 AM28 AM29 AP32 AP31 AP35 AP34 AR32 AR31 AR35 AR34 AM32 AM31 AL35 AL32 AM34 Buffer Type DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 Dir I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O Land Name SB DQ 53 SB DQ 54 SB DQ 55 SB DQ 56 SB DQ 57 SB DQ 58 SB DQ 59 SB DQ 60 SB DQ 61 SB DQ 62 SB DQ 63 SB DQS 0
74. IO 65 165 Q PRDY Pull Up VCCIO 65 1650 PREQ Pull Up VCCIO 65 165 Q TCK Pull Down VSS 5 15 kQ TDI Pull Up VCCIO 5 15 kQ TMS Pull Up VCCIO 5 15 TRST Pull Up VCCIO 5 15 CFG 17 0 Pull Up VCCIO 5 15 88 Datasheet Volume 1 Electrical Specifications L 7 7 1 7 2 Caution 7 2 1 Electrical Specifications Power and Ground Lands The processor has VCC VDDQ VCCPLL VCCSA VCCAXG VCCIO and VSS ground inputs for on chip power distribution All power lands must be connected to their respective processor power planes while all VSS lands must be connected to the system ground plane Use of multiple power and ground planes is recommended to reduce I R drop The VCC and VCCAXG lands must be supplied with the voltage determined by the processor Serial Voltage IDentification SVID interface A new serial VID interface is implemented on the processor Table 7 1 specifies the voltage level for the various VIDs Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storage Cay such as electrolytic capacitors supply current during longer lasting changes in current demand for example coming out of an idle condition Similarly capacitors act as a s
75. K 8 GB 4 Gb 512Mx8 16 2 16 10 8 8K Note 1 System memory configurations are based on availability and are subject to change 2 1 2 System Memory Timing Support Th e IMC supports the following Speed Bins CAS Write Latency CWL and command signal mode timings on the main memory interface 24 tCL CAS Latency tRCD Activate Command to READ or WRITE Command delay tRP PRECHARGE Command Period CWL CAS Write Latency Command Signal modes 1N indicates a new command may be issued every clock and 2N indicates a new command may be issued every 2 clocks Command launch mode programming depends on the transfer rate and memory configuration Datasheet Volume 1 Interfaces Table 2 4 2 1 3 2 1 3 1 2 1 3 2 Note System Memory Timing Support Transfer tRCD tRP CWL CMD 1 Segment NE tCK tCK tck tck PPC Mode Notes 1 1N 2N 1333 9 9 9 7 Desktop 2 2N 1 1N 2N 1600 11 11 11 8 2 2 1 1N 2N 1333 9 9 9 7 AIO 2 2 1600 11 11 11 8 1 1N 2N Note 1 System memory timing support is based on availability and is subject to change System Memory Organization Modes The IMC supports two memory organization modes single channel and dual channel Depending upon how the DIMM Modules are populated in each memory channel a number of different configurations can exist Single Channel Mode In this mode all memory cycles are directed to a single c
76. ND VSS K2 GND VSS F20 GND VSS K20 GND VSS F23 GND VSS K23 GND VSS F26 GND VSS K26 GND VSS F29 GND VSS K29 GND VSS F35 GND VSS K33 GND VSS F37 GND VSS K35 GND VSS F39 GND VSS K37 GND VSS F5 GND VSS K39 GND VSS F6 GND VSS K5 GND VSS F9 GND VSS K6 GND VSS G11 GND VSS L10 GND VSS G12 GND VSS L17 GND VSS G17 GND VSS L20 GND VSS G20 GND VSS L23 GND VSS G23 GND VSS L26 GND VSS G26 GND VSS L29 GND VSS G29 GND VSS L8 GND VSS G34 GND VSS M1 GND VSS G7 GND VSS M17 GND VSS G8 GND VSS M2 GND VSS H1 GND VSS M20 GND VSS H17 GND VSS M23 GND VSS H2 GND VSS M26 GND VSS H20 GND VSS M29 GND VSS H23 GND VSS M33 GND VSS H26 GND VSS M35 GND VSS H29 GND VSS M37 GND VSS H33 GND VSS M39 GND VSS H35 GND VSS M5 GND VSS H37 GND VSS M6 GND VSS H39 GND VSS M9 GND VSS H5 GND VSS N8 GND VSS H6 GND VSS P1 GND VSS H9 GND VSS P2 GND VSS J11 GND VSS P36 GND VSS J17 GND VSS P38 GND VSS J20 GND VSS P40 GND VSS J23 GND VSS P5 GND VSS J26 GND VSS P6 GND VSS J29 GND VSS R33 GND VSS J32 GND VSS R35 GND VSS K1 GND VSS R37 GND Datasheet Volume 1 Table 8 1 Processor Land and Signal Information Processor Land List by Land Name Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_SENSE VSSAXG_SENSE VSSIO_SENSE Datasheet Volume 1 Land R39 R8 5 T6 U8 Vi v2 V33 V34 V35 V
77. RACTOR WAS NEGLIGENT IN THE DESIGN MANUFACTURE OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or go to http www intel com design literature htm No computer system can provide absolute security under all conditions Intel Trusted Execution Technology Intel TXT requires a computer system with Intel Virtualization Technology an Intel TXT enabled processor chipset BIOS Authenticated Code Modules and an Intel TXT compatible measured launched environment MLE The
78. S Input PROCHOT activated if enabled This signal can also be driven to the Open Drain processor to activate the TCC Output Note Toggling PROCHOT more than once in 1 5 ms period will result in constant Pn state of the processor Thermal Trip The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating temperature to ensure that there are no false trips The processor will stop all execution Asynchronous when the junction temperature exceeds approximately 130 C This is signaled to the system by the THERMTRIP signal 71 intel 6 10 Power Sequencing Signals Table 6 12 Power Sequencing Signals 72 Signal Description Signal Name Description Direction Buffer Type SM_DRAMPWROK SM_DRAMPWROK Processor Input Connects to PCH DRAMPWROK I Asynchronous CMOS UNCOREPWRGOOD The processor requires this input signal to be a clean indication that the Vccsa Vecio Vaxg and Vppo power supplies are stable and within specifications This requirement applies regardless of the S state of the processor Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state This is connected to the PCH PROCPWRGD signal I As
79. SB BS 2 0 SM_DRAMRST SA_CS 3 0 SB_CS 3 0 SA_ODT 3 0 SB_ODT 3 0 SA_CKE 3 0 SB_CKE 3 0 DDR3 Data Signals Single ended DDR3 Bi directional SA_DQ 63 0 SB_DQ 63 0 Differential DDR3 Bi directional SA_DQS 8 0 SA_DQS 8 0 SB_DQS 8 0 SB_DQS 8 0 TAP ITP XDP Single Ended CMOS Input TCK TDI TMS TRST Single Ended CMOS Output TDO Single Ended Asynchronous CMOS Output TAPPWRGOOD Control Sideband Single Ended CMOS Input CFG 17 0 Single Ended Draineldrecaonal Single Ended Asynchronous CMOS Output THERMTRIP CATERR Single Ended Asynchronous CMOS Input ST ee T MNGORERWRGOOBS Single Ended Asynchronous Bi directional PECI CMOS Input VIDALERT Single Ended Open Drain Output VIDSCLK Bi directional VIDSOUT Power Ground Other Power VCC VCC_NCTF VCCIO VCCPLL VDDQ VCCAXG Ground VSS No Connect and test point RSVD RSVD_NCTF RSVD_TP FC_x Sense Points VCC_SENSE VSS_SENSE VCCIO_SENSE VSS_SENSE_VCCIO VAXG_SENSE VSSAXG_SENSE Other SKTOCC DBR Datasheet Volume 1 81 Electrical Specifications intel Table 7 2 Signal Groups Sheet 2 of 2 Signal Group Type Signals PCI Express PEG RX 15 0 PEG RX 15 0 Diff tial PCI E Input eee press spy PE_RX 3 0 4 PE_RX 3 0 4 PEG TX 15 0 PEG TX 15 0 Diff tial PCI E Output PE TX
80. Signals Memory Reference and Compensation Direction Signal Name Description Buffer Type DDR3 Reference Voltage This signal is used as a reference I SM_VREF voltage to the DDR3 controller A Memory Channel A B DIMM DQ Voltage Reference These output pins are connected to the DIMMs and are programmed to SA_DIMM_VREFDQ have a reference voltage with optimized margin SB_DIMM_VREFDQ A The nominal source impedance for these pins is 150 Q The step size is 7 7 mV for DDR3 with no load Datasheet Volume 1 67 Table 6 5 68 Reset and Miscellaneous Signals Reset and Miscellaneous Signals Signal Description Signal Name Description Direction Buffer Type Configuration Signals The CFG signals have a default value of 1 if not terminated on the board CFG 1 0 Reserved configuration lane A test point may be placed on the board for this lane CFG 2 PCI Express Static x16 Lane Numbering Reversal 1 Normal operation 0 Lane numbers reversed CFG 3 PCI Express Static x4 Lane Numbering Reversal CFG 17 0 1 Normal operation 0 Lane numbers reversed CMOS CFG 4 Reserved configuration lane A test point may be placed on the board for this lane e CFG 6 5 PCI Express Bifurcation Note 1 00 1 x8 2 x4 PCI Express 01 reserved 10 2 x8 PCI Express 11 1 x16 PCI Express CFG 17 7 Re
81. TX 3 0 PE TX 3 0 and PE_RX 3 0 PE_RX 3 0 signals are only used for platforms that support 20 PCIe lanes These signals are reserved on Desktop 3rd Generation Intel Core i7 i5 processors Desktop Intel Pentium processors and Desktop Intel Celeron processors Intel Flexible Display Intel FDI Interface Signals Intel Flexible Display Intel FDI Interface Signal Name Description Bua Tile i Pi FSYNC O Intel Flexible Display Interface Frame Sync Pipe A MOS i i Pi FDIO LSYNC O Intel Flexible Display Interface Line Sync Pipe A m FDI TX 7 0 Intel Flexible Display Interface Transmit Differential FDI_TX 7 0 Pairs FDI i i Pi FDI1_FSYNC 1 Intel Flexible Display Interface Frame Sync Pipe B and C e i i x Pi FDI1_LSYNC 1 Intel Flexible Display Interface Line Sync Pipe B and C Gos Intel Flexible Display Interface Hot Plug Interrupt I FDI_INT Asynchronous CMOS 69 intel 6 6 Table 6 8 6 7 Table 6 9 6 8 Table 6 10 Test Access Points 70 Signal Description Direct Media Interface DMI Signals Direct Media Interface DMI Signals Processor to PCH Serial Interface Signal Name Description Direction Buffer Type DMI_RX 3 0 DMI Input from PCH Direct Media Interface receive I DMI_RX 3 0 differential pair DMI DMI_TX 3 0 DMI Output to PCH Direct Media Interface transmit DMI_TX 3
82. Table 4 4 4 1 5 Table 4 5 4 1 6 Table 4 6 4 1 7 Table 4 7 PCI Express Link States PCI Express Link States State Description LO Full on Active transfer state LOs First Active Power Management low power state Low exit latency L1 Lowest Active Power Management Longer exit latency L3 Lowest power state power off Longest exit latency Direct Media Interface DMI States Direct Media Interface DMI States State Description LO Full on Active transfer state LOs First Active Power Management low power state Low exit latency L1 Lowest Active Power Management Longer exit latency L3 Lowest power state power off Longest exit latency Processor Graphics Controller States Processor Graphics Controller States State Description DO Full on display active D3 Cold Power off Interface State Combinations G S and C State Combinations e 6 Sleep same Processor System Clocks Description tate S State C State State GO 50 CO Full On On Full On GO 50 C1 C1E Auto Halt On Auto Halt GO 50 C3 Deep Sleep On Deep Sleep GO 50 6 On Deep Power Down Gi S3 Power off Off except RTC Suspend to RAM Gi S4 Power off Off except RTC Suspend to Disk G2 S5 Power off Off except RTC Soft Off G3 NA Power off Power off Hard off Datasheet Volume 1 49 m L 5 Power Management 4 2 1 4 2 2
83. WR PWR Dir Land Name VCC_SENSE VCCAXG VCCAXG VCCAXG Land 121 122 124 125 127 128 130 K15 K16 K18 K19 K21 K22 K24 K25 K27 K28 K30 L13 L14 L15 L16 L18 L19 L21 L22 L24 L25 L27 L28 L30 M14 M15 M16 M18 M19 M21 M22 M24 M25 M27 M28 M30 A36 AB33 AB34 AB35 Buffer Type Dir 101 102 ntel Table 8 1 Processor Land List by Land Name Processor Land and Signal Information Table 8 1 Processor Land List by Land Name Land Name VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG_SENSE VCCIO VCCIO VCCIO VCCIO VCCIO Land AB36 AB37 AB38 AB39 AB40 AC33 AC34 AC35 AC36 AC37 AC38 AC39 AC40 33 T34 T35 T36 T37 T38 T39 T40 U33 U34 U35 U36 U37 U38 U39 U40 w33 W34 w35 W36 W37 W38 Y33 Y34 Y35 Y36 Y37 Y38 L
84. _DQS 8 0 during read and write DDR3 transactions Data Bus Channel A data signal interface to the SDRAM data bus 1 0 SA_DQ 63 0 9 DDR3 SA 15 0 Memory Address These signals are used to provide the multiplexed MA 15 0 row and column address to the SDRAM DDR3 SDRAM Differential Clock Channel A SDRAM Differential clock signal SA CK 3 0 pair The crossing of the positive edge of SA CK and the negative edge Oo SA CK 3 0 of its complement SA CK are used to sample the command and DDR3 control signals on the SDRAM Clock Enable 1 per rank These signals are used to e Initialize the SDRAMs during power up e Power down SDRAM ranks DDR3 Place all SDRAM ranks into and out of self refresh during STR Chip Select 1 per rank These signals are used to select particular SA_CS 3 0 SDRAM components during the active state There is one Chip Select DDR3 for each SDRAM rank SA_ODT 3 0 On Die Termination Active Termination Control 66 Datasheet Volume 1 Signal Description Table 6 3 6 2 Table 6 4 Memory Channel B Signals intel ET Direction Signal Name Description Buffer Type SB BSI2 0 Bank Select These signals define which banks are selected within 0 B5 2 0 each SDRAM rank DDR3 SB WE Write Enable Control Signal This signal is used with SB RAS and SB_CAS along with SB_CS to define the SDRAM Commands DDR3 SB
85. ackaging material Datasheet Volume 1 Introduction Table 1 2 Terminology Sheet 3 of 3 Term SVID Description Serial Voltage IDentification interface TAC Thermal Averaging Constant TAP TCC Test Access Point Thermal Control Circuit TDC Thermal Design Current TDP TLP Thermal Design Power Transaction Layer Packet VAXG Graphics core power supply Vccio Processor core power supply High Frequency I O logic power supply VccpiL PLL power supply Vecsa System Agent memory controller DMI PCle controllers and display engine power supply VDDQ DDR3 power supply VGA VID Video Graphics Array Voltage Identification VLD Variable Length Decoding VLW VR Virtual Legacy Wire Voltage Regulator Processor ground VTS x1 Virtual Temperature Sensor Refers to a Link or Port with one Physical Lane x16 Refers to a Link or Port with sixteen Physical Lanes x4 x8 Refers to a Link or Port with four Physical Lanes Refers to a Link or Port with eight Physical Lanes Datasheet Volume 1 21 Introduction intel 1 8 Related Documents Table 1 3 Related Documents Document Document Number Location Desktop 3rd Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family 326765 Datasheet Volume 2 Desktop 3rd Genera
86. ained I rocessors with 45 W TDP a 40 I 2011A Sustained Icc processors with 2 35 W TDP 7 B j Notes 1 Each processor is programmed with a maximum valid voltage identification value VID which is set at Datasheet Volume 1 manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range This differs from the VID employed by the processor during a power management event Adaptive Thermal Monitor Enhanced Intel SpeedStep Technology or Low Power States The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 20 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe ICC MAX specification is based on the V c loadline at worst case highest tolerance and ripple The Vcc specifications represent static and transient limits The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and VSS_SENSE lands PSx refers to the voltage regulator power state as set by the SVID protocol 2011A proces
87. ains in the higher power C state Table 4 10 shows package C state resolution for a dual core processor Figure 4 4 summarizes package C state transitions Table 4 10 Coordination of Core Power States at the Package Level Core 1 Package C State co C1 c3 C6 CO CO CO CO CO co cit Cii ci Core 0 03 CO ci C3 C3 C6 CO ci C3 C6 Note If enabled the package C state will be C1E if all cores have resolved a core C1 state or higher 54 Datasheet Volume 1 Power Management intel Figure 4 4 Package C State Entry and Exit 4 2 5 1 4 2 5 2 Package CO Package CO is the normal operating state for the processor The processor remains in the normal state when at least one of its cores is in the CO or C1 state or when the platform has not granted permission to the processor to go into a low power state Individual cores may be in lower power idle states while the package is in CO Package C1 C1E No additional power reduction actions are taken in the package C1 state However if the C1E sub state is enabled the processor automatically transitions to the lowest supported core clock frequency followed by a reduction in voltage The package enters the C1 low power state when e At least one core is in the C1 state The other cores are in a C1 or lower power state The package enters the C1E state when All cores have directly requested C1E using MWAIT C1 with
88. als Processor to PCH Serial Interface 70 6 9 Phase Lock Loop PLL Signals 5 errata cevancavavaearisnctigven dg dex CREER ER ERERRGAYR ERE dines 70 6 10 Test Access Points TAP Signals 2 2 teni eet And cue neni dd ee Ra des ena Da anand ra Y REA ER dane 70 6 11 Error and Thermal Protection Signals aaa 71 6 12 Power Sequencing Signals 2 onte entres eng tete etude basa oo ena ERA RR RA ARRA 72 6 13 Processor Power Signal Sensini nanmanna rei Fete DEROSE 73 6 14 Sense 4 8 5 aere tux t e ert eua ca prada da xa alge Rn ed eee a Dane eda e RA dn 73 6 15 Ground and Non Critical to Function NCTF Signals sss 74 6 16 Processor Internal Pull Up Pull Down 6 6 eee mene 74 7 1 VR 12 0 Voltage Identification 6 cece eee erent ennemi 77 722 Signal Gro psS Emm 81 7 3 Storage Condition Ratings meniran iere pter ERE ERR tuple CER ea CE CENE 83 7 4 Processor Core Active and Idle Mode DC Voltage and Current Specifications 84 7 5 Processor System Agent I O Buffer Supply DC Voltage and Current Specifications 86 7 6 Processor Graphics VID based Vaxc Supply DC Voltage and Curr
89. and Signal Information Table 8 1 Processor Land List by Land Name SA DQS SA DQS SA DQS SA DQS SA_DQS 0 SA_DQS 1 SA_DQS 2 SA_DQS 3 SA_DQS 4 SA_DQS 5 SA_DQS 6 SA_DQS 7 SA_DQS 8 SA_ECC_CB SA_ECC_CB SA ECC CB SA ECC CB SA ECC CB SA ECC CB SA ECC CB SA ECC CB SA 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Land Name SA DQ SA DQ SA DQ SA DQ SA DQ SA DQ SA DQ SA DQ SA DQ SA DQ SA DQ SA DQ SA DQ SA DQ SA DQ SA DQ SA DQ SA DQ SA DQ SA DQ SA DQS 0 SA DQS 1 SA DQS 2 SA DQS 3 SA DQS 4 5 6 7 8 Land AR39 AR38 AN39 AN40 AL40 AL37 AJ38 AJ37 AL39 AL38 AJ39 AJ40 AG40 AG37 AE38 AE37 AG39 AG38 AE39 AE40 AK3 AP3 AW4 AV8 AV37 AP38 AK38 AF38 AV13 AK2 AP2 AV4 AW8 AV36 AP39 AK39 AF39 12 AU12 AU14 AW13 AY13 AU13 AU11 AY12 AW12 AV27 Buffer Type DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 Dir I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O
90. aphics Processing The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive All the cores are fully programmable increasing the versatility of the 3D Engine The Gen 7 0 3D engine provides the following performance and power management enhancements Up to 16 Execution units EUs Hierarchal Z Video quality enhancements 3D Engine Execution Units e Supports up to 16 EUs The EUs perform 128 bit wide execution per clock e Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel processing Datasheet Volume 1 33 intel Interfaces 2 4 1 2 2 4 1 2 1 2 4 1 2 2 2 4 1 2 3 2 4 1 2 4 2 4 1 2 5 2 4 1 2 6 2 4 1 3 34 3D Pipeline Vertex Fetch VF Stage The VF stage executes 3DPRIMITIVE commands Some enhancements have been included to better support legacy D3D APIs as well 85 SGI OpenGL Vertex Shader VS Stage The VS stage performs shading of vertices output by the VF function The VS unit produces an output vertex reference for every input vertex reference received from the VF unit in the order received Geometry Shader GS Stage The GS stage receives inputs from the VS stage Compiled application provided GS programs specifying an algorithm to convert the vertices of an input object into some output primitives For example a GS shader may convert lines of a line strip into polygons representi
91. ated seer 16 1 3 5 Direct Media Interface DMI wii csciccccceersanseesctectedecessedeeae de ed 16 1 3 6 Processor Graphics Controller GT sss 16 1 3 7 Thermal 16 1 4 Processor SKU Definitions eir ennt e Enn nik de nenne dida dyes CU 16 S ccce 17 1 6 Processor Compatibility esses mnes sese 18 m RET 19 1 8 Related Documents icdccesacaessean ann enki RES 22 2 We m T 23 2 1 System Memory Interface ssssssssssssssssssseseseseseseene sisse senes ee seme sees nn nnn 23 2 1 1 System Memory Technology 5 23 2 1 2 System Memory Timing cect need 24 2 1 3 System Memory Organization 5 25 2 1 3 1 SinglesChannel Mode iiie ierat nnn nene ke ti nena 25 2 1 3 2 Dual Channel Mode Intel Flex Memory Technology Mode 25 2 1 4 Rules for Populating Memory 95 5
92. aving differs according to the selected mode and the DDR type used For more information refer to the IDD table in the DDR specificaiton The DDR defines 3 levels of power down that differ in power saving and in wakeup time 1 Active power down APD This mode is entered if there are open pages when de asserting CKE In this mode the open pages are retained Power saving in this mode is the lowest Power consumption of DDR is defined by IDD3P Exiting this mode is defined by tXP small number of cycles 2 Precharged power down PPD This mode is entered if all banks in DDR are precharged when de asserting CKE Power saving in this mode is intermediate better than APD but less than DLL off Power consumption is defined by IDD2P1 Exiting this mode is defined by tXP The difference relative to APD mode is that when waking up in PPD mode all page buffers are empty 3 DLL off In this mode the data in DLLs on DDR are off Power saving in this mode is the best among all power modes Power consumption is defined by IDD2P1 Exiting this mode is defined by tXP and tXPDLL 10 20 according to the DDR type until first data transfer is allowed The processor supports 6 different types of power down The different modes are the power down modes supported by DDR3 and combinations of these The type of CKE power down is defined by configuration The options are as follows 1 No power down 2 APD The rank enters power down as soon as the idle ti
93. ble 1 2 Terminology Sheet 2 of 3 20 Intel virtualization Technology I ntel VT for Directed I O Intel VT d is a hardware assist under system software Virtual Machine Manager or operating system control Intel VT d for enabling I O device virtualization Intel VT d also brings robust security by providing protection from errant DMAs by using DMA remapping a key feature of Intel VT d lov 1 O Virtualization ISA Industry Standard Architecture This is a legacy computer bus standard for IBM PC compatible computers Integrated Trusted Platform Module LCD Liquid Crystal Display LFM Low Frequency Mode LPC Low Pin Count LPM Low Power Mode LVDS Low Voltage Differential Signaling A high speed low power data transmission standard used for display connections to LCD panels MSI Message Signaled Interrupt Non Critical to Function NCTF locations are typically redundant ground or non critical NCTF reserved so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality ODT On Die Termination PAIR Power Aware Interrupt Routing Platform Controller Hub The chipset with centralized platform capabilities including the PCH main I O interfaces along with display connectivity audio features power management manageability security and storage features PECI Platform Environment Control Interface PCI Express Graph
94. ccepts TLPs assembled by the Transaction Layer calculates and applies data protection code and TLP sequence number and submits them to Physical Layer for transmission across the Link The receiving Data Link Layer is responsible for checking the integrity of received TLPs and for submitting them to the Transaction Layer for further processing On detection of TLP error s this layer is responsible for requesting retransmission of TLPs until information is correctly received or the Link is determined to have failed The Data Link Layer also generates and consumes packets which are used for Link management functions Physical Layer The Physical Layer includes all circuitry for interface operation including driver and input buffers parallel to serial and serial to parallel conversion PLL s clock recovery circuits and impedance matching circuitry It also includes logical functions related to interface initialization and maintenance The Physical Layer exchanges data with the Data Link Layer in an implementation specific format and is responsible for converting this to an appropriate serialized format and transmitting it across the PCI Express Link at a frequency and width compatible with the remote device Datasheet Volume 1 29 intel Interfaces 2 2 2 PCI Express Configuration Mechanism The PCI Express external graphics link is mapped through a PCI to PCI bridge structure Figure 2 4 PCI Express Related Register Structures in
95. cessor core control is maintained by an embedded controller The graphics driver dynamically adjusts between P States to maintain optimal performance power and thermals Graphics Thermal Power Management See Section 4 6 for all graphics thermal power management related features 88 Datasheet Volume 1 61 62 Power Management Datasheet Volume 1 Thermal Management m 5 Thermal Management For thermal specifications and design guidelines refer to the Desktop 3rd Generation Intel Core Processor Family Desktop Intel Pentium Processor Desktop Intel Celeron Processor and LGA1155 Socket Thermal and Mechanical Specifications and Design Guidelines 88 Datasheet Volume 1 63 64 Thermal Management Datasheet Volume 1 Signal Description 6 Signal Description This chapter describes the processor signals They are arranged in functional groups according to their associated interface or category The following notations are used to describe the signal type The signal description also includes the type of buffer used for the particular signal see Table 6 1 Notations Signal Type I Input Signal Output Signal 1 Bi directional Input Output Signal Table 6 1 Signal Description Buffer Types Signal Description PCI Express PCI Express interface signals These signals are compatible with PCI Express 3 0 Signalling Environment AC Specifications and are AC coupled The
96. cores A 32 KB instruction and 32 KB data first level cache L1 for each core A 256 KB shared instruction data second level cache L2 for each core Up to 8 MB shared instruction data third level cache L3 shared among all cores 1 1 1 Supported Technologies Intel virtualization Technology Intel VT for Directed I O Intel VT d Intel virtualization Technology Intel VT for 1A 32 Intel 64 and Intel Architecture Intel VT x Intel Active Management Technology Intel AMT 8 0 Intel Trusted Execution Technology Intel TXT Intel Streaming SIMD Extensions 4 1 Intel SSE4 1 Intel Streaming SIMD Extensions 4 2 Intel SSE4 2 Intel Hyper Threading Technology Intel HT Technology Intel 64 Architecture Execute Disable Bit Intel Turbo Boost Technology Intel Advanced Vector Extensions Intel AVX Intel Advanced Encryption Standard New Instructions Intel AES NI PCLMULQDQ Instruction RDRAND instruction for random number generation SMEP Supervisor Mode Execution Protection PAIR Power Aware Interrupt Routing 1 2 Interfaces 1 2 1 System Memory Support Datasheet Volume 1 Two channels of DDR3 Unbuffered Dual In Line Memory Modules UDIMM or DDR3 Unbuffered Small Outline Dual In Line Memory Modules SO DIMM with a maximum of two DIMMs per channel Single channel and dual channel memory organization modes Data burst length of eight for all memory organization modes Memory DDR3 data
97. d in the BIOS The P_LVLx I O Monitor address needs to be set up before using the P_LVLx I O read interface Each P LVLx is mapped to the supported MWAIT Cx instruction as shown in Table 4 9 P_LVLx to MWAIT Conversion P_LVLx MWAIT Cx Notes P_LVL2 MWAIT C3 P_LVL3 MWAIT C6 C6 No sub states allowed The BIOS can write to the C state range field of the PMG_IO_CAPTURE MSR to restrict the range of I O addresses that are trapped and emulate MWAIT like functionality Any P_LVLx reads outside of this range does not cause an I O redirection to an MWAIT Cx like request They fall through like a normal I O instruction When P_LVLx I O instructions are used MWAIT substates cannot be defined The MWAIT substate is always zero if I O MWAIT redirection is used By default P_LVLx I O redirections enable the MWAIT break on EFLAGS IF feature that triggers a wakeup on an interrupt even if interrupts are masked by EFLAGS IF Core C states The following are general rules for all core C states unless specified otherwise e Acore C State is determined by the lowest numerical thread state such as Thread 0 requests C1E while Thread 1 requests C3 resulting in a core C1E state See Table 4 7 e A core transitions to CO state when An interrupt occurs There is an access to the monitored address if the state was entered using an MWAIT instruction For core C1 C1E core C3 and core C6 an interrupt directed to
98. e 4 3 48 Power Management Advanced Configuration and Power Interface ACPI States Supported The ACPI states supported by the processor are described in this section System States System States State Description G0 S0 Full On G1 S3 Cold Scu ME STR Context saved to memory S3 Hot is not supported by the 61 54 Suspend to Disk STD All power lost except wakeup on PCH G2 S5 Soft off All power lost except wakeup on PCH Total reboot G3 Mechanical off All power removed from system Processor Core Package Idle States Processor Core Package State Support State Description CO Active mode processor executing code Ci AutoHALT state C1E AutoHALT state with lowest frequency and voltage operating point C3 Execution cores in C3 flush their L1 instruction cache L1 data cache and L2 cache to the L3 shared cache Clocks are shut off to each core C6 Execution cores in this state save their architectural state before removing core voltage Integrated Memory Controller States Integrated Memory Controller States State Power up Description CKE asserted Active mode Pre charge Power Down CKE de asserted not self refresh with all banks closed Active Power Down Self Refresh CKE de asserted not self refresh with minimum one bank active CKE de asserted using device self refresh Datasheet Volume 1 Power Management 4 1 4
99. e C6 state by initiating a P LVL3 I O read or an MWAIT C6 instruction Before entering core C6 the core will save its architectural state to a dedicated SRAM Once complete a core will have its voltage reduced to zero volts During exit the core is powered on and its architectural state is restored C State Auto Demotion In general deeper C states such as C6 have long latencies and have higher energy entry exit costs The resulting performance and energy penalties become significant when the entry exit frequency of a deeper C state is high Therefore incorrect or inefficient usage of deeper C states have a negative impact on idle power To increase residency and improve idle power in deeper C states the processor supports C state auto demotion There are two C State auto demotion options C6to C3 C6 C3 To C1 The decision to demote a core from C6 to C3 or C3 C6to C1 is based on each core s immediate residency history Upon each core C6 request the core C state is demoted to C3 or C1 until a sufficient amount of residency has been established At that point a core is allowed to go into C3 C6 Each option can be run concurrently or individually This feature is disabled by default BIOS must enable it in the PMG CST CONFIG CONTROL register The auto demotion policy is also configured by this register Datasheet Volume 1 53 m L Power Management 4 2 5 Package C States The processor supports CO C1 C1E C3 a
100. e two areas The launching of the Measured Launched Environment MLE The protection of the MLE from potential corruption The enhanced platform provides these launch and control interfaces using Safer Mode Extensions SMX The SMX interface includes the following functions Measured Verified launch of the MLE e Mechanisms to ensure the above measurement is protected and stored in a secure location e Protection mechanisms that allow the MLE to control attempts to modify itself For more information refer to the Intel TXT Measured Launched Environment Developer s Guide in http www intel com content www us en software developers intel txt software development guide html Intel Hyper Threading Technology Intel HT Technology The processor supports Intel Hyper Threading Technology Intel HT Technology that allows an execution core to function as two logical processors While some execution resources such as caches execution units and buses are shared each logical processor has its own architectural state with its own set of general purpose registers and control registers This feature must be enabled using the BIOS and requires operating system support Intel recommends enabling Intel HT Technology with Microsoft Windows 7 Microsoft Windows Vista Microsoft Windows XP Professional Windows XP Home and disabling Intel HT Technology using the BIOS for all previous versions of Windows operating systems For mo
101. e voltage source and not be connected to Vcc This specification is measured at VCCSA SENSE 2 5 total Minimum of 2 DC and 3 AC at the sense point di dt 50 A us with 150 ns step 86 Datasheet Volume 1 Electrical Specifications intel Table 7 6 Processor Graphics VID based Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note Vaxc GFX VID GFX VID Range for Vaxc _ Range 0 2500 1 5200 V 1 LLaxg Vaxgc Loadline Slope 4 1 mta 2 3 Vec Tolerance Band Vaxc TOB PSO PS1 19 mV 2 3 4 PS2 11 5 Ripple PSO 10 VaxcRipple PS1 10 mV 2 3 4 PS2 10 15 Current for Processor Graphics 1 Sustained current for Processor 25 Graphics core Notes 1 Vaxg is VID based rail 2 The Vaxc min and max loadlines represent static and transient limits 3 The loadlines specify voltage limits at the die measured at the VAXG_SENSE and VSSAXG_SENSE lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor VAXG_SENSE and VSSAXG_SENSE lands 4 PSx refers to the voltage regulator power state as set by the SVID protocol 5 Each processor is programmed with a maximum valid voltage identification value VID that is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have differ
102. ect from virus attacks and unwanted code to harm the system For more information please refer to the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A see Section 1 8 Related Documents on page 22 Power Aware Interrupt Routing PAIR The processor added enhanced power performance technology which routes interrupts to threads or cores based on their sleep states For example concerning energy savings it routes the interrupt to the active cores without waking the deep idle cores For Performance it routes the interrupt to the idle C1 cores without interrupting the already heavily loaded cores This enhancement is mostly beneficial for high interrupt scenarios like Gigabit LAN WLAN peripherals and so on S Datasheet Volume 1 Power Management intel 4 Power Management This chapter provides information on the following power management topics e Advanced Configuration and Power Interface ACPI States e Processor Core e Integrated Memory Controller IMC PCI Express e Direct Media Interface DMI e Processor Graphics Controller Figure 4 1 Processor Power States C0 Active mode C1 Auto halt C1E Auto halt low freq low voltage C3 L1 L2 caches flush clocks off C6 save core states before shutdown Note Power states availability may vary between the different SKUs Datasheet Volume 1 47 4 1 1 Table 4 1 4 1 2 Table 4 2 4 1 3 Tabl
103. ed Memory Controller IMC supports DDR3 DDR3L protocols with two independent 64 bit wide channels each accessing one or two DIMMs The type of memory supported by the processor is dependant on the PCH SKU in the target platform Refer to Chapter 1 for supported memory configuration details The processor supports only JEDEC approved memory modules and devices The IMC supports a maximum of two DIMMs per channel thus allowing up to four device ranks per channel The supported memory interface frequencies and number of DIMMs per channel are SKU dependent 1 Processor DIMM Support Summary by Product Processor DIMM per cores Package channel DIMM type DDR3 DDR3L at 1 5 V 1 DPC 1333 1600 1333 1600 Dual Core ulGA LL i so pimm SSS S Quad Core 2 DPC 1333 1600 1333 1600 1 DPC 1333 1600 1333 1600 Dual core uLGA UDIMM Quad Core 2 DPC 1333 1600 1333 1600 Note There is no support for DDR3L DIMMs DRAMS running at 1 35 V e DDR3 DDR3L at 1 5 V Data Transfer Rates 1333 MT s PC3 10600 1600 MT s PC3 12800 DDR3 DDR3L at 1 5 V SO DIMM Modules Raw Card A Dual Ranked x16 unbuffered non ECC Raw Card B Single Ranked x8 unbuffered non ECC Raw Card C Single Ranked x16 unbuffered non ECC Raw Card F Dual Ranked x8 planar unbuffered non ECC Desktop platform DDR3 DDR3L at 1 5 V UDIMM Modules Raw Card A Single Ranked x8 unbuffered non E
104. ent Specifications 87 7 7 DDR3 Signal Group DC Specifications icecis ies eta ertt hen hn RA n n Ra 87 7 8 Control Sideband and TAP Signal Group DC 5 89 7 9 PCI Express DC Specifications sssrin ii tenda rer aor aaa ERR E Rx TE EX Ra RR 89 7510 PECL DC Electrical Limits 5 respecte atn i Seeded xi E 91 8 1 Processor Land List by Land Name isssssssssssesess nenne esee emnes 95 9 1 DDR Data Swizzling Table Channel eee eene eene nen 110 9 2 DDR Data Swizzling table Channel B sss nemen nemen nen 111 Datasheet Volume 1 7 intel Revision History Revision Description Revision Date Number 001 Initial release April 2012 002 Added Desktop 3rd Generation Intel Core i5 3470T i5 3470 i5 3470S June 2012 i5 3475S i5 3570 i5 3570S processors Updated Section 1 2 2 PCI Express 003 Updated Section 2 1 1 System Memory Technology Supported June 2012 Updated Table 7 4 Processor Core Active and Idle Mode DC Voltage and Current Specifications Added 65 W to 2011C Minor edits throughout for clarity 004 Added Intel Pentium G2120 and G2100T processors September 2012 Added Desktop 3rd Generation Intel Core i3 3220 i3 3220T i3 3225 i3 32
105. ent settings within the VID range This differs from the VID employed by the processor during a power management event Adaptive Thermal Monitor Enhanced Intel SpeedStep Technology or Low Power States Table 7 7 DDR3 Signal Group DC Specifications Sheet 1 of 2 Datasheet Volume 1 Symbol Parameter Min Typ Max Units Notes Vi Input Low Voltage EE 2 4 9 Input High Voltage SM_VREF PONES 0 1 i y 33 Input Low Voltage ES Vppg 0 55 Vir SM DRAMPWROK 500 1 v 8 Input High Voltage V 0 55 V DDO V V IH SM_DRAMPWROK 0 1 3 Output Low Voltage Vppo 2 Ron VoL rene Output High Voltage Vppo 2 V Q DDO V 4 6 Dn Ron Ron Rterm DDR3 Data Buffer pull up Resistance 20 28 6 40 B 5 DDR3 Data Buffer pull Row DN DQ down Resistance 2 ANA 4n n 2 DDR3 On die termination equivalent RODT DQ resistance for data 40 20 5 n signals DDR3 On die termination DC working point driver set to 0 4 VppQ Wo Vp 9 6 Vnpq v receive mode 87 Electrical Specifications intel Table 7 7 DDR3 Signal Group DC Specifications Sheet 2 of 2 Symbol Parameter Min Units Notest R DDR3 Clock Buffer pull ON_UP CK up Resistance R DDR3 Clock Buffer pull ON DN CK down Resistance 20 5 10 20 10 DDR3 Command Buffer RON UP CMD pull up Resistance te 19 DDR3 Command
106. er each cache line 64 byte boundary If there are two requests and the second request is to an address on the opposite channel from the first that request can be sent before data from the first request has returned If two consecutive cache lines are requested both may be retrieved simultaneously since they are ensured to be on opposite channels Use Dual Channel Symmetric mode when both Channel A and Channel B DIMM connectors are populated in any order with the total amount of memory in each channel being the same When both channels are populated with the same memory capacity and the boundary between the dual channel zone and the single channel zone is the top of memory the IMC operates completely in Dual Channel Symmetric mode The DRAM device technology and width may vary from one channel to the other Rules for Populating Memory Slots In all System Memory Organization Modes the frequency and latency timings of the system memory is the lowest supported frequency and slowest supported latency timings of all memory DIMM modules placed in the system as determined through the SPD registers In a Two DIMM Per Channel 2DPC daisy chain layout memory configuration the furthest DIMM from the processor of any given channel must always be populated first Datasheet Volume 1 Interfaces 2 1 5 2 1 5 1 2 1 5 2 2 1 5 3 2 1 6 2 1 7 Technology Enhancements of Intel Fast Memory Access Intel FMA The following secti
107. er value before entering a guest The feature aids VMM developers in flexibility and Quality of Service QoS guarantees Descriptor Table Exiting Descriptor table exiting allows a VMM to protect a guest operating system from internal malicious software based attack by preventing relocation of key system data structures like IDT interrupt descriptor table GDT global descriptor table LDT local descriptor table and TSS task segment selector A VMM using this feature can intercept by a VM exit attempts to relocate these data structures and prevent them from being tampered by malicious software 3 1 3 Intel virtualization Technology Intel VT for Directed I O Intel VT d Objectives The key Intel VT d objectives are domain based isolation and hardware based virtualization A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated Virtualization allows for the creation of one or more partitions on a single system This could be multiple partitions in the same operating system or there can be multiple operating system instances running on the same system offering benefits such as system consolidation legacy migration activity partitioning or security 40 Datasheet Volume 1 Technologies 3 1 4 Intel Virtualization Technology Intel VT for Directed I O Intel VT d Features The processor supports the following Intel VT d fea
108. ese 56 4 3 1 Disabling Unused System Memory Outputs 56 4 3 2 DRAM Power Management and Initialization 57 4 3 2 1 Initialization Role of CKE sisina nna a a a 58 4 3 2 2 Conditional Self Refresh 2 iie eid tadni 58 4 3 2 3 Dynamic Power Down Operation eee eee ne 59 4 3 2 4 DRAM I O Power Management eee 59 4 3 3 DDR Electrical Power Gating eee ee eee e eee teeta eee ea ees 59 4 4 PCI Express Power Management sessi emen nnns 60 4 5 DMI Power Managemeht orden nannte horae nha echa tu ada RR VER RR EEARAR Fe n ua 60 4 6 Graphics Power Management ee eens eater tate eee sens 60 4 6 1 Intel Rapid Memory Power Management Intel RMPM also known as CXSR ii 60 4 6 2 Intel Graphics Performance Modulation Technology Intel 60 4 6 3 Graphics Render C State cicer nent rhe ert pened ensenmegeead Ea EEE aiai 60 4 6 4 Intel Smart
109. essor See the PCI Express Base Specification for details of PCI Express The number of PCI Express controllers is dependent on the platform Refer to Chapter 1 for details PCI Express Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers may operate unchanged The PCI Express configuration uses standard mechanisms as defined in the PCI Plug and Play specification The processor external graphics ports support Gen 3 speed as well At 8 GT s Gen 3 operation results in twice as much bandwidth per lane as compared to Gen 2 operation The 16 lane PCI Express graphics port can operate at either 2 5 GT s 5 GT s or 8 GT s PCI Express Gen 3 uses a 128 130b encoding scheme eliminating nearly all of the overhead of the 8b 10b encoding scheme used in Gen 1 and Gen 2 operation The PCI Express architecture is specified in three layers Transaction Layer Data Link Layer and Physical Layer The partitioning in the component is not necessarily along these same boundaries Refer to Figure 2 2 for the PCI Express layering diagram PCI Express Layering Diagram Transaction Transaction Data Link Data Link Physical Physical Logical Sub block Logical Sub block Electrical Sub block Electrical Sub block RX TX RX TX PCI Express uses packets to communicate information between components Packets are formed in the Transaction and Data Link Layers to carry the information f
110. g term reliability cannot be assured unless all the Low Power Idle States are enabled Datasheet Volume 1 Power Management 4 6 4 4 6 5 4 7 Intel Smart 2D Display Technology Intel S2DDT Intel S2DDT reduces display refresh memory traffic by reducing memory reads required for display refresh Power consumption is reduced by less accesses to the IMC S2DDT is only enabled in single pipe mode Intel S2DDT is most effective with e Display images well suited to compression such as text windows slide shows and so on Poor examples are 3D games e Static screens such as screens with significant portions of the background showing 2D applications processor benchmarks and so on or conditions when the processor is idle Poor examples are full screen 3D games and benchmarks that flip the display image at or near display refresh rates Intel Graphics Dynamic Frequency Intel Graphics Dynamic Frequency Technology is the ability of the processor and graphics cores to opportunistically increase frequency and or voltage above the ensured processor and graphics frequency for the given part Intel Graphics Dynamic Frequency Technology is a performance feature that makes use of unused package power and thermals to increase application performance The increase in frequency is determined by how much power and thermal budget is available in the package and the application demand for additional processor or graphics performance The pro
111. hannel Single channel mode is used when either Channel A or Channel B DIMM connectors are populated in any order but not both Dual Channel Mode Intel Flex Memory Technology Mode The IMC supports Intel Flex Memory Technology Mode Memory is divided into a symmetric and a asymmetric zone The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached In this mode the system runs with one zone of dual channel mode and one zone of single channel mode simultaneously across the whole memory array Channels A and B can be mapped for physical channel 0 and 1 respectively or vice versa however channel A size must be greater or equal to channel B size Datasheet Volume 1 25 intel Interfaces Figure 2 1 Intel Flex Memory Technology Operation 2 1 3 2 1 Note 2 1 4 Note 26 TOM Non interleaved access Dual channel interleaved access CHA CHB CH A and CH B can be configured to be physical channels O or 1 B The largest physical memory amount of the smaller size memory module C The remaining physical memory amount of the larger size memory module Dual Channel Symmetric Mode Dual Channel Symmetric mode also known as interleaved mode provides maximum performance on real world applications Addresses are ping ponged between the channels aft
112. he implementation and operation of the processor on its respective platform Throughout this document the Intel 6 7 Series Chipset Platform Controller Hub may be referred to as PCH Throughout this document the Desktop 3rd Generation Intel Core processor family Desktop Intel Pentium processor family and Desktop Intel Celeron processor family may be referred to simply as processor Throughout this document the Desktop 3rd Generation Intel Core processor family Desktop Intel Pentium processor family and Desktop Intel Celeron processor family refer to the processor SKUs listed in Table 1 1 Some processor features are not available on all platforms Refer to the processor specification update for details The term DT refers to desktop platforms Datasheet Volume 1 9 Introduction intel Figure 1 1 Desktop Processor Platform PCI Express 3 0 1 x16 or 2x8 DDR3 Discrete Intel Processor m PECI Intel Flexible Display Interface MORE Serial ATA Management Engine Intel 6 7 Series ISB 2 0 USB 3 0 Chipset Families SMBUS 2 0 SPI Controller Link 1 E 1 CES 8 PCI Express 2 0 Super I O x1 Ports 5 GTis GPIO Note 1 USB 3 0 is supported on the Inte 7 Series Chipset family only 10 Datasheet Volume 1 Introduction intel 1 1 Processor Feature Details Four or two execution
113. ications are consuming less than the TDP at the rated frequency To take advantage of the available thermal headroom the active cores can increase their operating frequency To determine the highest performance frequency amongst active cores the processor takes the following into consideration The number of cores operating in the CO state The estimated current consumption The estimated power consumption The temperature Any of these factors can affect the maximum frequency for a given workload If the power current or thermal limit is reached the processor will automatically reduce the frequency to stay with its TDP limit Intel Turbo Boost Technology processor frequencies are only active if the operating system is requesting the PO state For more information on P states and C states refer to Chapter 4 Intel Turbo Boost Technology Graphics Frequency Graphics render frequency is selected by the processor dynamically based on graphics workload demand The processor can optimize both processor and Processor Graphics performance by managing power for the overall package For the integrated graphics this allows an increase in the render core frequency and increased graphics performance for graphics intensive workloads In addition during processor intensive workloads when the graphics power is low the processor core can increase its frequency higher within the package power limit Enabling Intel Turbo Boost Technology will maxim
114. ics External Graphics using PCI Express Architecture A high PEG speed serial interface whose configuration is software compatible with the existing PCI specifications PGA Pin Grid Array PLL Phase Lock Loop PME Power Management Event PPD Precharged Power Down Processor The 64 bit single core or multi core component package The term processor core refers to Si die itself that can contain multiple execution Processor Core cores Each execution core has an instruction cache data cache and 256 KB L2 cache All execution cores share the L3 cache Processor Graphics Intel Processor Graphics Rank A unit of DRAM corresponding four to eight devices in parallel ignoring ECC These devices are usually but not always mounted on a single side of a SO DIMM SCI System Control Interrupt Used in ACPI protocol Intel SDRRS Intel Seamless Display Refresh Rate Switching Technology Technology SMEP Supervisor Mode Execution Protection A non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor landings should not be connected to any supply voltages have Storage Conditions any I Os biased or receive any clocks Upon exposure to free air that is unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the p
115. ides the ability to operate while transitioning to an adjacent VID and its associated voltage This will represent a DC shift in the loadline At condition outside functional operation condition limits neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded on exposure to conditions exceeding the functional operation condition limits Datasheet Volume 1 intel Electrical Specifications Sheet 1 of 3 VID VID VID VID VID VID VID VID ion ini VR 12 0 Voltage Identification Def VID VID VID VID VID VID VID VID Table 7 1 HEX Vcc 8 0 0 88500 8 1 0 89000 8 2 0 89500 8 3 0 90000 8 4 0 90500 8 5 0 91000 8 6 0 91500 8 7 0 92000 8 8 0 92500 8 9 0 93000 8 A 0 93500 8 B 0 94000 8 C 0 94500 8 D 0 95000 8 E 0 95500 8 F 0 96000 9 0 0 96500 9 1 0 97000 9 2 0 97500 9 3 0 98000 9 4 0 98500 9 5 0 99000 9 6 0 99500 9 7 1 00000 9 8 1 00500 9 9 1 01000 9 A 1 01500 9 B 1 02000 9 C 1 02500 9 D 1 03000 9 E 1 03500 9 F 1 04000 A O 1 04500 A 1 1 05000 A 2 1 05500 A 3 1 06000 A 4 1 06500 A 5 1 07000 A 6
116. ing and communication Datasheet Volume 1 Technologies 3 6 3 3 7 intel RDRAND Instruction The processor introduces a software visible random number generation mechanism supported by a high quality entropy source This capability will be made available to programmers through the new RDRAND instruction The resultant random number generation capability is designed to comply with existing industry standards in this regard ANSI X9 82 and NIST SP 800 90 Some possible usages of the new RDRAND instruction include cryptographic key generation as used in a variety of applications including communication digital signatures secure storage and so on Intel 64 Architecture x2APIC The Intel x2APIC architecture extends the xAPIC architecture that provides key mechanism for interrupt delivery This extension is intended primarily to increase processor addressability Specifically x2APIC Retains all key elements of compatibility to the xAPIC architecture delivery modes interrupt and processor priorities interrupt sources interrupt destination types e Provides extensions to scale processor addressability for both the logical and physical destination modes Adds new features to enhance performance of interrupt delivery Reduces complexity of logical destination mode interrupt delivery on link based architectures The key enhancements provided by the x2APIC architecture over xAPIC are the following
117. ing down is a fatal unrecoverable error If the DMI data link goes to data link down after the link was up then the DMI link hangs the system by not allowing the link to retrain to prevent data corruption This link behavior is controlled by the PCH Downstream transactions that had been successfully transmitted across the link prior to the link going down may be processed as normal No completions from downstream non posted transactions are returned upstream over the DMI link after a link down event Datasheet Volume 1 Interfaces 2 4 intel Processor Graphics Controller GT New Graphics Engine Architecture includes 3D compute elements Multi format hardware assisted decode encode pipeline and Mid Level Cache MLC for superior high definition playback video quality and improved 3D performance and Media The Display Engine handles delivering the pixels to the screen and is the primary channel interface for display memory accesses and PCI like traffic in and out Figure 2 6 Processor Graphics Controller Unit Block Diagram 2 4 1 2 4 1 1 VS GS Vertex Setup Rasterize Fetch Hierachical Z Hardware ro Unified L Unit Array Texture Mr Pixel Backend s Additional Post Processing Multi Format Decode Encode Full MPEG2 VC1 AVC Decode Fixed Function Post Processing Full AVC Encode Partial MPEG2 VC1 Encode 3D and Video Engines for Gr
118. is configured during power on reset by using its manufacturing default value This value is the highest non turbo core multiplier at which the processor can operate If lower maximum speeds are desired the appropriate ratio can be configured using the FLEX RATIO MSR Phase Lock Loop PLL Power Supply An on die PLL filter solution is implemented on the processor Refer to Table 7 5 for DC specifications Vcc Voltage Identification VID The processor uses three signals for the serial voltage identification interface to support automatic selection of voltages Table 7 1 specifies the voltage level corresponding to the eight bit VID value transmitted over serial VID A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the voltage regulation circuit cannot supply the voltage that is requested the voltage regulator must disable itself VID signals are CMOS push pull drivers Refer to Table 7 8 for the DC specifications for these signals The VID codes will change due to temperature and or current load changes to minimize the power of the part A voltage range is provided in Table 7 4 The specifications are set so that one voltage regulator can operate with all supported frequencies Individual processor VID values may be set during manufacturing so that two devices at the same core frequency may have different default VID settings This is shown in the VID range values in Table 7 4 The processor prov
119. ize the performance of the processor core and the graphics render frequency within the specified package power levels Datasheet Volume 1 43 m t 8 Technologies 3 6 3 6 1 3 6 2 44 Intel Advanced Vector Extensions Intel AVX Intel Advanced Vector Extensions Intel AVX is the latest expansion of the Intel instruction set It extends the Intel Streaming SIMD Extensions Intel SSE from 128 bit vectors to 256 bit vectors Intel AVX addresses the continued need for vector floating point performance in mainstream scientific and engineering numerical applications visual processing recognition data mining synthesis gaming physics cryptography and other application areas The enhancement in Intel AVX allows for improved performance due to wider vectors new extensible syntax and rich functionality including the ability to better manage rearrange and sort data In the processor new instructions were added to allow graphics media and imaging applications to speed up the processing of large amount of data by reducing the memory bandwidth and footprint The new instructions convert operands between single precision floating point values and half precision 16 bit floating point values For more information on Intel AVX see http www intel com software avx Security and Cryptography Technologies Intel Advanced Encryption Standard New Instructions Intel AES NI The processor supports Intel Advanced Encryption
120. lb of 28 C Post board attach storage temperature limits are not specified for non Intel branded boards 6 The JEDEC J JSTD 020 moisture level rating and associated handling practices apply to all moisture sensitive devices removed from the moisture barrier bag 7 Nominal temperature and humidity conditions and durations are given and tested within the constraints imposed by Tsustained storage and customer shelf life in applicable Intel boxes and bags Datasheet Volume 1 83 Electrical Specifications 7 10 DC Specifications The processor DC specifications in this section are defined at the processor pads unless noted otherwise See Chapter 8 for the processor land listings and Chapter 6 for signal definitions Voltage and current specifications are detailed in Table 7 4 Table 7 5 and Table 7 6 The DC specifications for the DDR3 signals are listed in Table 7 7 Control Sideband and Test Access Port TAP are listed in Table 7 8 Table 7 4 through Table 7 6 list the DC specifications for the processor and are valid only while meeting the thermal specifications as specified in the Thermal Mechanical Specifications and Guidelines clock frequency and input voltages Care should be taken to read all notes associated with each parameter 7 10 1 Voltage and Current Specifications Note Noise measurements on SENSE lands for all voltage supplies should be made with a 20 MHz bandwidth osci
121. ll reserved signals For reliable operation always connect unused inputs or bi directional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground Vss Unused outputs maybe left unconnected however this may interfere with some Test Access Port TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bi directional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability For details see Table 7 8 Signal Groups Signals are grouped by buffer type and similar characteristics as listed in Table 7 2 The buffer type indicates which signaling technology and specifications apply to the signals All the differential signals and selected DDR3 and Control Sideband signals have On Die Termination ODT resistors There are some signals that do not have ODT and need to be terminated on the board Datasheet Volume 1 Table 7 2 Electrical Specifications Signal Groups Sheet 1 of 2 Signal Group Type Signals System Reference Clock Differential CMOS Input BCLK 0 BCLK 0 DDR3 Reference Clocks Differential DDR3 Output SA CK 3 0 SA CK 3 0 SB CK 3 0 SB_CK 3 0 DDR3 Command Signals Single Ended DDR3 Output SA_RAS SB RAS SA_CAS SB CAS amp SA WE SB WE SA MA 15 0 SB MA 15 0 SA BS 2 0
122. lloscope Table 7 4 Processor Core Active and Idle Mode DC Voltage and Current Specifications Sheet 1 of 2 Symbol Parameter Min Typ Max Unit Note VID VID Range 0 2500 1 5200 V 1 Vcc Loadline Slope LLycc 2011D 2011C 2011B processors with 1 7 mo 2 4 5 77 W 65 W 55 W 45 W TDP Vcc Tolerance Band 2011D 2011C 2011B processors with 77 W 65 W 55 W 45 W TDP 245 VccTOB PSO FIT mV DL PS1 13 PS2 11 5 Ripple 2011D 2011C 2011B processors with 77 W 65 W 55 W 45 W TDP 2 4 5 VccRipple PSO 47 mV por PS1 10 PS2 10 25 Vcc Loadline Slope 2011A processors 214 5 with 35 W TDP 2 9 moa 7 Vcc Tolerance Band 2011A processors with 35 W TDP VccTOB PSO 419 2E PS1 19 PS2 11 5 Ripple 2011A processors with 35 W TDP VccRipple PSO 10 mv 2E PS1 10 PS2 10 25 Vcc Boor Default Vcc voltage for initial power up 0 Icc 2011D Icc processors with 77 W TDP 112 3 Icc 2011C Icc processors with 55 W TDP 75 3 84 Datasheet Volume 1 Electrical Specifications m L Table 7 4 Processor Core Active and Idle Mode DC Voltage and Current Specifications Sheet 2 of 2 Symbol Parameter Min Typ Max Unit Note Icc 2011B Icc processors with 45 W TDP 60 A 3 Icc 2011A Icc processors with 35 W TDP 35 3 I 2011D Sustained Icc processors with 85 CC TDC 77 W TDP i I 2011C Sustained Icc processors with 55 CCTDC 55 W TDP E E 2011B Sust
123. mer expires independent of the bank status 3 PPD When idle timer expires the MC sends PRE all to rank and then enters power down 4 DLL off Same as option 2 but DDR is configured to DLL off 5 APD change to PPD APD PPD Begins as option 1 and when all page close timers of the rank are expired it wakes the rank issues PRE all and returns to PPD 6 APD change to DLL off APD_DLLoff Begins as option 1 and when all page close timers of the rank are expired it wakes the rank issues PRE all and returns to DLL off power down The CKE is determined per rank when it is inactive Each rank has an idle counter The idle counter starts counting as soon as the rank has no accesses and if it expires the rank may enter power down while no new transactions to the rank arrive to queues The idle counter begins counting at the last incoming transaction arrival Datasheet Volume 1 57 m L Power Management Note 4 3 2 1 4 3 2 2 58 It is important to understand that since the power down decision is per rank the MC can find a lot of opportunities to power down ranks even while running memory intensive applications savings may be significant up to a few Watts depending on DDR configuration This becomes more significant when each channel is populated with more ranks Selection of power modes should be according to power performance or thermal trade offs of a given system e When trying to achieve maximum pe
124. n All display interfaces connecting external displays are now repartitioned and driven from the PCH Refer to the PCH datasheet for more details on display port support Intel Flexible Display Interface Intel FDI The Intel Flexible Display Interface Intel FDI is a proprietary link for carrying display traffic from the Processor Graphics controller to the PCH display I Os Intel FDI supports two or three independent channels one for pipe A one for pipe B and one for Pipe C Channels A and B have a maximum of four transmit Tx differential pairs used for transporting pixel and framing data from the display engine in two display configurations In three display configurations Channel A has 4 transmit Tx differential pairs while Channel B and C have two transmit Tx differential pairs e Each channel has four transmit Tx differential pairs used for transporting pixel and framing data from the display engine e Each channel has one single ended LineSync and one FrameSync input 1 V CMOS signaling One display interrupt line input 1 V CMOS signaling Intel FDI may dynamically scale down to 2X or 1X based on actual display bandwidth requirements Common 100 MHz reference clock Each channel transports at a rate of 2 7 Gbps e PCH supports end to end lane reversal across both channels no reversal support required in the processor Multi Graphics Controllers Multi Monitor Support The processor supports simultaneous
125. nd C6 power states The following is a summary of the general rules for package C state entry These apply to all package C states unless specified otherwise A package C state request is determined by the lowest numerical core C state amongst all cores e A package C state is automatically resolved by the processor depending on the core idle power states and the status of the platform components Each core can be at a lower idle power state than the package if the platform does not grant the processor permission to enter a requested package C state The platform may allow additional power savings to be realized in the processor For package C states the processor is not required to enter CO before entering any other C state The processor exits a package C state when a break event is detected Depending on the type of break event the processor does the following e If acore break event is received the target core is activated and the break event message is forwarded to the target core If the break event is not masked the target core enters the core CO state and the processor enters package CO e If the break event was due to a memory access or snoop request But the platform did not request to keep the processor in a higher package C state the package returns to its previous C state And the platform requests a higher power C state the memory access or snoop request is serviced and the package rem
126. needed to ensure Receiver detect 4 The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled to ensure that the Receiver Detect occurs properly Compensation of this impedance can start immediately and the 15 Rx Common Mode Impedance constrained by RLRX CM to 50 Q 20 must be within the specified range by the time Detect is entered 5 COMP resistance must be provided on the system board with 1 resistors 6 PEG ICOMPO PEG ICOMPI PEG RCOMPO are the same resistor Intel allows using 24 9 1 resistors Datasheet Volume 1 89 L L 8 Electrical Specifications 7 11 1 Figure 7 1 90 Platform Environmental Control Interface PECI DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices The processor contains a Digital Thermal Sensor DTS that reports a relative die temperature as an offset from Thermal Control Circuit TCC activation temperature Temperature sensors located throughout the die are implemented as analog to digital converters calibrated at the factory PECI provides an interface for external devices to read the DTS temperature for thermal management and fan speed control More detailed information may be found in the Platform Environment Control Interface PECI Specification PECI Bus Architecture The PECI architecture based on wired OR bus
127. ng a corresponding segment of a blade of grass centered on the line Or it could use adjacency information to detect silhouette edges of triangles and output polygons extruding out from the edges Clip Stage The Clip stage performs general processing on incoming 3D objects However it also includes specialized logic to perform a Clip Test function on incoming objects The Clip Test optimizes generalized 3D Clipping The Clip unit examines the position of incoming vertices and accepts rejects 3D objects based on its Clip algorithm Strips and Fans SF Stage The SF stage performs setup operations required to rasterize 3D objects The outputs from the SF stage to the Windower stage contain implementation specific information required for the rasterization of objects and also supports clipping of primitives to some extent Windower IZ WIZ Stage The WIZ unit performs an early depth test which removes failing pixels and eliminates unnecessary processing overhead The Windower uses the parameters provided by the SF unit in the object specific rasterization algorithms The WIZ unit rasterizes objects into the corresponding set of pixels The Windower is also capable of performing dithering whereby the illusion of a higher resolution when using low bpp channels in color buffers is possible Color dithering diffuses the sharp color bands seen on smooth shaded objects Video Engine The video engine is part of the Intel Processor Graphics fo
128. nnel B Land Name Land MC Land Name Land Name Land MC Land Name SB DQ 0 AG7 DQ04 SB_DQ 40 32 DQ43 SB_DQ 1 AG8 DQO5 SB_DQ 41 AP31 DQ44 SB_DQ 2 AJ9 2 SB_DQ 42 AP35 DQ42 SB DQ 3 AJ8 DQ03 SB DQ 43 AP34 DQ40 SB DQ 4 AG5 DQ07 SB DQ 44 AR32 DQ47 SB DQ 5 AG6 DQ06 SB_DQ 45 AR31 DQ45 SB DQ 6 AJ6 DQOO SB DQ 46 AR35 DQ41 SB DQ 7 17 DQO1 SB DQ 47 AR34 DQ46 SB_DQ 8 AL7 DQ12 SB_DQ 48 AM32 DQ52 SB_DQ 9 AM7 DQ13 SB DQ 49 AM31 DQ55 SB DQ 10 AM10 DQ08 SB DQ 50 AL35 DQ50 SB DQ 11 AL10 DQ10 SB DQ 51 AL32 DQ53 SB DQ 12 AL6 DQ15 SB DQ 52 AM34 DQ51 SB DQ 13 AM6 DQ14 SB_DQ 53 AL31 DQ54 SB DQ 14 AL9 DQ11 SB DQ 54 AM35 DQ48 SB DQ 15 AM9 DQ09 SB DQ 55 AL34 DQ49 SB_DQ 16 AP7 DQ20 SB_DQ 56 AH35 DQ60 SB_DQ 17 AR7 DQ21 SB_DQ 57 AH34 DQ61 SB_DQ 18 AP10 DQ18 SB DQ 58 AE34 DQ58 SB_DQ 19 AR10 DQ16 SB DQ 59 AE35 DQ56 SB DQ 20 AP6 DQ22 SB_DQ 60 135 DQ62 SB_DQ 21 AR6 DQ23 SB DQ 61 A334 DQ63 SB DQ 22 AP9 DQ19 SB DQ 62 AF33 DQ57 SB DQ 23 ARO DQ17 SB DQ 63 AF35 DQ59 SB DQ 24 AM12 DQ30 SB DQ 64 AL16 DQ66 SB DQ 25 AM13 DQ24 SB DQ 65 AM16 DQ64 SB DQ 26 AR13 DQ26 SB DQ 66 AP16 DQ68 SB DQ 27 AP13 DQ27 SB DQ 67 AR16 DQ69 SB DQ 28 AL12 DQ31 SB DQ 68 AL15 DQ67 SB DQ 29 AL13 DQ25 SB DQ 69 5 DQ65 SB_DQ 30 AR12 DQ28 SB_DQ 70 AR15 DQ70 SB DQ 31 AP12 DQ29 SB DQ 71 AP15 DQ71 SB DQ 32 AR28 DQ39 SB DQ 33 AR29 DQ37 88 SB DQ 34 AL28 DQ33 SB DQ 35 AL29 DQ34 SB DQ 36 AP28 DQ38 SB DQ 37 AP29 DQ36 SB DQ 38
129. nology platform technology intel amt Hyper Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology enabled chipset BIOS and operating system Performance will vary depending on the specific hardware and software you use For more information including details on which processors support HT Technology see htp www intel com info hyperthreading Intel Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability Intel Turbo Boost Technology performance varies depending on hardware software and overall system configuration Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology For more information see http www intel com technology turboboost Enhanced Intel SpeedStep Technology See the Processor Spec Finder or contact your Intel representative for more information Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See www intel com products processor_number for details 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 architecture Performance will vary depending on your hardware and software configurations Consult with your system vendor for more information Intel Pe
130. ntel Virtualization Technology Intel VT Intel Virtualization Technology Intel VT makes a single system appear as multiple independent systems to software This allows multiple independent operating systems to run simultaneously on a single system Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets Intel virtualization Technology for IA 32 Intel 64 and Intel Architecture Intel VT x added hardware support in the processor to improve the virtualization performance and robustness Intel Virtualization Technology for Directed I O Intel VT d adds chipset hardware implementation to support and improve I O virtualization performance and robustness Intel VT x specifications and functional descriptions are included in the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B and is available at http www intel com products processor manuals index htm Other Intel VT documents can be referenced at http www intel com technology virtualization index htm Intel virtualization Technology Intel VT for IA 32 Intel 64 and Intel Architecture Intel VT x Objectives Intel VT x provides hardware acceleration for virtualization of IA platforms Virtual Machine Monitor VMM can use Intel VT x features to provide improved reliable virtualized platform By using Intel VT x a VMM is Robust VMMs no longer need to use paravir
131. nterface on the processor is a single 16 lane x16 port that can also be configured at narrower widths The PCI Express port is being designed to be compliant with the PCI Express Base Specification Revision 3 0 2 2 3 1 PCI Express Lanes Connection Figure 2 5 demonstrates the PCIe lanes mapping Figure 2 5 PCI Express Typical Operation 16 Lanes Mapping 0 1 2 3 4 5 6 5 EM 7 is o 0 8 x Hg E 2 10 5 9 3 11 Z a 0 E 12 5 x 8 1 EE 5 13 be o o E 2 6 14 x 3 7 15 Lane 10 Lane 11 Lane 12 Lane 13 10 11 12 13 14 15 Datasheet Volume 1 31 intel Interfaces 2 3 Note 2 3 1 2 3 2 2 3 3 32 Direct Media Interface DMI Direct Media Interface DMI connects the processor and the PCH Next generation DMI 2 0 is supported Only DMI x4 configuration is supported DMI Error Flow DMI can only generate SERR in response to errors never SCI SMI MSI PCI INT or GPE Any DMI related SERR activity is associated with Device O Processor PCH Compatibility Assumptions The processor is compatible with the Intel 7 Series Chipset PCH products DMI Link Down The DMI link go
132. ntium Celeron Intel Core and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2013 Intel Corporation All rights reserved 2 Datasheet Volume 1 Contents 1 Hippie 9 1 1 Processor Feat re Details nicer tes cn die dauern nete x dR E cx Da castes adie 11 1 1 1 Supported Technologies ici inrer e ina aa Ee nel ae e E 11 1 2 Interfaces ettet cages d ERA E ERA RA MA Za ben PRA ERR RAE MR 11 1 2 1 System Memory Support siii neigt ie kae rg gen a aexapa du pr lupos renaR wanna 11 12 1 2 3 Direct Media Interface DMI sernir rieron enean sue A 14 1 2 4 Platform Environment Control Interface PECI 14 1 2 5 Processor Graphics ioci edd da tarea rae rex Md d oA Re SA a a RR eM 14 1 2 6 Intel Flexible Display Interface Intel FDI eee 15 1 3 Power Management Support 20 nennen hehehe en nnne nnns 15 1 32L PrOCeSSOI COFG i cues eoe tese nuance 15 1 9 2 e ae vaa Cou S 15 1 3 3 Memory Controller seen iint cn pha Fore kg iege Eia sx ER RD CR 15 1 3 4 PCL Express s
133. ons source pattern and destination defined by Microsoft including transparent BLT The BLT engine has instructions to invoke BLT and stretch BLT operations permitting software to set up instruction buffers and use batch processing The BLT engine can perform hardware clipping during BLTs Datasheet Volume 1 35 intel Interfaces Figure 2 7 2 4 2 1 2 4 2 1 1 2 4 2 1 2 2 4 2 1 3 2 4 2 1 4 36 Processor Graphics Display The Processor Graphics controller display pipe can be broken down into three components e Display Planes e Display Pipes DisplayPort and Intel FDI Processor Display Block Diagram VGA c PipeA Pane Transcoder Memory Plane Fitting A Host Du Interface Tx side Outside of Display 5 PipeB Pane Transcoder Cross Engine Plane Fitting B Point Mux FDI 1 I d4 I PipeC Panel Transcoder Tx side I Plane Fitting Display Planes A display plane is a single displayed surface in memory and contains one image desktop cursor overlay It is the portion of the display hardware logic that defines the format and location of a rectangular region of memory that can be displayed on display output device and delivers that data to a display pipe This is clocked by the Core Display Clock
134. ons describe the Just in Time Scheduling Command Overlap and Out of Order Scheduling Intel FMA technology enhancements Just in Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next The most efficient request is picked from all pending requests and issued to system memory Just in Time to make optimal use of Command Overlapping Thus instead of having all memory access requests go individually through an arbitration mechanism forcing requests to be executed one at a time they can be started without interfering with the current request allowing for concurrent issuing of requests This allows for optimized bandwidth and reduced latency while maintaining appropriate command spacing to meet system memory protocol Command Overlap Command Overlap allows the insertion of the DRAM commands between the Activate Precharge and Read Write commands normally used as long as the inserted commands do not affect the currently executing command Multiple commands can be issued in an overlapping manner increasing the efficiency of system memory protocol Out of Order Scheduling While leveraging the Just in Time Scheduling and Command Overlap enhancements the IMC continuously monitors pending requests to system memory for the best use of bandwidth and reduction of latency If there are multiple requests to the same o
135. ow power C states power saving actions only take place once the core C state is resolved Core C states are automatically resolved by the processor For thread and core C states a transition to and from CO is required before entering any other C state Coordination of Thread Power States at the Core Level Thread 1 Processor Core eae co ci c3 C6 CO CO CO CO CO CO ci Cii cit Thread 0 C3 CO cii C3 C3 C6 CO ci 03 C6 Note If enabled the core C state will be C1E if all enabled cores have also resolved a core C1 state or higher Datasheet Volume 1 51 m L 8 Power Management Note Table 4 9 Note 4 2 4 4 2 4 1 52 Requesting Low Power Idle States The primary software interfaces for requesting low power idle states are through the MWAIT instruction with sub state hints and the HLT instruction for C1 and C1E However software may make C state requests using the legacy method of I O reads from the ACPI defined processor clock control registers referred to as P_LVLx This method of requesting C states provides legacy support for operating systems that initiate C state transitions using I O reads To seamless support of legacy operating systems P_LVLx I O reads are converted within the processor to the equivalent MWAIT C state request Therefore P_LVLx reads do not directly result in I O reads to the system The feature known as I O MWAIT redirection must be enable
136. p CKE is the only input to the SDRAM that has its level recognized other than the DDR3 reset pin once power is applied The signal must be driven LOW by the DDR controller to make sure the SDRAM components float DQ and DQS during power up CKE signals remain LOW while any reset is active until the BIOS writes to a configuration register Using this method CKE is ensured to remain inactive for much longer than the specified 200 ys after power and clocks to SDRAM devices are stable Conditional Self Refresh Intel Rapid Memory Power Management Intel RMPM conditionally places memory into self refresh in the package C3 and C6 low power states Intel RMPM functionality depends on graphics display state relevant only when processor graphics is being used as well as memory traffic patterns generated by other connected I O devices When entering the S3 Suspend to RAM STR state or SO conditional self refresh the processor core flushes pending cycles and then enters all SDRAM ranks into self refresh the CKE signals remain LOW so the SDRAM devices perform self refresh Datasheet Volume 1 Power Management intel 4 3 2 3 4 3 2 4 4 3 3 The target behavior is to enter self refresh for the package C3 and C6 states as long as there are no memory requests to service Dynamic Power Down Operation Dynamic power down of memory is employed during normal operation Based on idle conditions a given memory rank may be powered down The IM
137. pen page these requests would be launched in a back to back manner to make optimum use of the open memory page This ability to reorder requests on the fly allows the IMC to further reduce latency and increase bandwidth efficiency Data Scrambling The memory controller incorporates a DDR3 Data Scrambling feature to minimize the impact of excessive di dt on the platform DDR3 VRs due to successive 1s and Os on the data bus Past experience has demonstrated that traffic on the data bus is not random Rather it can have energy concentrated at specific spectral harmonics creating high di dt that is generally limited by data patterns that excite resonance between the package inductance and on die capacitances As a result the memory controller uses a data scrambling feature to create pseudo random patterns on the DDR3 data bus to reduce the impact of any excessive di dt DDR3 Reference Voltage Generation The processor memory controller has the capability of generating the DDR3 Reference Voltage VREF internally for both read RDVREF and write VREFDQ operations The generated VREF can be changed in small steps and an optimum VREF value is determined for both during a cold boot through advanced DDR3 training procedures in order to provide the best voltage and signal margins Datasheet Volume 1 27 intel Interfaces 2 2 1 Figure 2 2 28 PCI Express Interface This section describes the PCI Express interface capabilities of the proc
138. r image processing play back and transcode of Video applications The Processor Graphics video engine has a dedicated fixed hardware pipe line for high quality decode and encode of media content This engine supports Full hardware acceleration for decode of AVC H 264 VC 1 and MPEG 2 contents along with encode of MPEG 2 and AVC H 264 apart from various video processing features The new Processor Graphics Video engine adds support for processing features such as frame rate conversion image stabilization and gamut conversion Datasheet Volume 1 Interfaces 2 4 1 4 2 4 1 4 1 2 4 1 4 2 intel The Display Engine fetches the raw data from the memory puts the data into a stream converts the data into raw pixels organizes pixels into images blends different planes into a single image encodes the data and sends the data out to the display device 2D Engine The Display Engine executes its functions with the help of three main functional blocks Planes Pipes and Ports except for eDP The Planes and Pipes are in the processor while the Ports reside in the PCH Intel FDI connects the display engine in the processor with the Ports in the PCH The 2D Engine adds a new display pipe C that enables support for three simultaneous and concurrent display configurations Processor Graphics Registers The 2D registers consists of original VGA registers and others to support graphics modes that have color depths resolutions and hardware
139. ranks of 8 bank devices Command launch modes of 1N 2N On Die Termination ODT Asynchronous ODT Intel Fast Memory Access Intel FMA Just in Time Command Scheduling Command Overlap Out of Order Scheduling 1 2 2 PCI Express 12 The PCI Express lanes PEG 15 0 TX and RX are fully compliant to the PCI Express Base Specification Revision 3 0 including support for 8 0 GT s transfer speeds Processor with Desktop PCH Supports may vary depending on PCH SKUs PCI Express supported configurations in desktop products Configuration Organization Desktop 1x8 1 Graphics 1 0 2x4 2 2x8 Graphics 1 0 3 1x16 Graphics 1 0 The port may negotiate down to narrower widths Support for x16 x8 x4 x2 x1 widths for a single PCI Express mode 2 5 GT s 5 0 GT s and 8 0 GT s PCI Express frequencies are supported Gen1 Raw bit rate on the data pins Gen 2 Raw bit rate on the data pins of 5 0 GT s resulting in a real bandwidth per pair of 500 MB s given the 8b 10b encoding used Datasheet Volume 1 Introduction intel to transmit data across this interface This also does not account for packet overhead and link maintenance Maximum theoretical bandwidth on the interface of 8 GB s in each direction simultaneously for an aggregate of 16 GB s when x16 Gen 2 Gen 3 raw bit rate on the data pins of 8 0 GT s resulting in a real bandwidth per pair of 984 MB s using 128b 130b encoding to transmit data acro
140. re information on Intel HT Technology see http www intel com technology platform technology hyper threading Datasheet Volume 1 Technologies 3 4 Note 3 4 1 Note 3 4 2 intel Intel Turbo Boost Technology Intel Turbo Boost Technology is a feature that allows the processor core to opportunistically and automatically run faster than its rated operating frequency render clock if it is operating below power temperature and current limits The Intel Turbo Boost Technology feature is designed to increase performance of both multi threaded and single threaded workloads Maximum frequency is dependant on the SKU and number of active cores No special hardware support is necessary for Intel Turbo Boost Technology BIOS and the operating system can enable or disable Intel Turbo Boost Technology Intel Turbo Boost Technology will increase the ratio of application power to TDP Thus thermal solutions and platform cooling that are designed to less than thermal design guidance might experience thermal and performance issues since more applications will tend to run at the maximum power limit for significant periods of time Intel Turbo Boost Technology may not be available on all SKUs Intel Turbo Boost Technology Frequency The processor s rated frequency assumes that all execution cores are running an application at the thermal design power TDP However under typical operation not all cores are active Therefore most appl
141. rect Media Interface DP DisplayPort DPST Display Power Savings Technology DTS Digital Thermal Sensor EC Embedded Controller ECC Error Correction Code eDP Embedded DisplayPort Enhanced Intel Technology that provides power management capabilities to laptops SpeedStep Technology EPG Electrical Power Gating EU Execution Unit The Execute Disable bit allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system See the Intel 64 and IA 32 Architectures Software Developer s Manuals for more detailed information HDMI HFM IMC High Definition Multimedia Interface High Frequency Mode Integrated Memory Controller Intel 64 Technology 64 bit memory extensions to the 32 architecture Intel Virtualization Technology Datasheet Volume 1 Intel DPST Intel Display Power Saving Technology Intel FDI Intel Flexible Display Interface Intel TXT Intel Trusted Execution Technology Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple robust independent software environments inside a single platform 19 Introduction intel Ta
142. rformance and power or thermal consideration is a non issue use no power down In a system that tries to minimize power consumption try to use the deepest power down mode possible DLL off or APD_DLLoff e In high performance systems with dense packaging that is tricky thermal design the power down mode should be considered in order to reduce the heating and avoid DDR throttling caused by the heating Control of the power mode through CRB BIOS BIOS selects by default no power down Another control is the idle timer expiration count This is set through PM_PDWN_config bits 7 0 MCHBAR 4CBO As this timer is set to a shorter time the IMC will have more opportunities to put DDR in power down The minimum recommended value for this register is 15 There is no BIOS hook to set this register Customers who choose to change the value of this register can do it by changing the BIOS For experiments this register can be modified in real time if BIOS did not lock the MC registers In APD APD PPD and APD DLLoff there is no point in setting the idle counter in the same range of page close idle timer Another option associated with CKE power down is the S_DLL off When this option is enabled the SBR I O slave DLLs go off when all channel ranks are in power down Do not confuse it with the DLL off mode in which the DDR DLLs are off This mode requires an I O slave DLL wakeup time be defined Initialization Role of CKE During power u
143. rom the transmitting component to the receiving component As the transmitted packets flow through the other layers they are extended with additional information necessary to handle packets at those layers At the receiving side the reverse process occurs and packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally for Transaction Layer Packets to the form that can be processed by the Transaction Layer of the receiving device Datasheet Volume 1 Interfaces intel Figure 2 3 Packet Flow Through the Layers 2 2 1 1 2 2 1 2 2 2 1 3 n i eme L I l L_ Transaction Layer Data Link Layer Physical Layer Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer The Transaction Layer s primary responsibility is the assembly and disassembly of Transaction Layer Packets TLPs TLPs are used to communicate transactions such as read and write as well as certain types of events The Transaction Layer also manages flow control of TLPs Data Link Layer The middle layer in the PCI Express stack the Data Link Layer serves as an intermediate stage between the Transaction Layer and the Physical Layer Responsibilities of Data Link Layer include link management error detection and error correction The transmission side of the Data Link Layer a
144. served configuration lanes A test point may be placed on the board for these pins FC x FC signals are signals that are available for compatibility with other processors A test point may be placed on the board for these pins PM SYNC Power Management Sync A sideband signal to communicate I power management status from the platform to the processor CMOS Platform Reset pin driven by the PCH I RESET CMOS RSVD Reserved All signals that are RSVD and RSVD_NCTF must be left No Connect RSVD NCTE unconnected on the board Non Critical to Function DDR3 DRAM Reset Reset signal from processor to DRAM devices SM_DRAMRST One common to all channels CMOS Note 1 PCIe bifurcation support varies with the processor and PCH SKUs used Datasheet Volume 1 Signal Description 6 4 Table 6 6 6 5 Table 6 7 Datasheet Volume 1 PCI Express based Interface Signals PCI Express Graphics Interface Signals Signal Name Description Direction Buffer Type x z PEG_ICOMPI PCI Express Input Current Compensation PCI Express Current Compensation PEG_ICOMPO I A PH PEG_RCOMPO PCI Express Resistance Compensation Dm PEG_RX 15 0 PEG_RX 15 0 PE RX 3 0 PE_RX 3 0 PCI Express Receive Differential Pair I PCI Express PEG_TX 15 0 PEG_TX 15 0 PE TX 3 0 PE 4 3 01 PCI Express Transmit Differential Pair PCI Express Note 1 PE
145. sors with 35 W TDP loadline slope TOB and ripple specifications allow for a cost reduced voltage regulator for boards supporting only the 2011A processors with 35 W TDP 2011A processors with 35 W TDP processors may also use the loadline slope TOB and ripple specifications for 2011D 2011C and 2011B 85 Electrical Specifications Table 7 5 Processor System Agent I O Buffer Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note VccsA Voltage for the system agent 0 879 0 925 0 971 V 1 Processor I O supply voltage for VDDQ DORS O supply g 1 5 DC 3 TOLppo Vppq Tolerance AC 2 AC DC 5 PLL supply voltage DC AC VecpLe specification Tt ks v Processor I O supply voltage for _9 20 a Vccio other than DDR3 2 3 1 05 2 3 V 2 Isa Current for the system agent 8 8 A Sustained current for the system Isa TDC agent 4 8 2 A Processor I O supply current for IppQ O supply 4 75 A 1 Processor I O supply sustained 4 75 A DDQ TDC current for DDR3 f I Processor I O supply standby 1 A DDQ STANDBY current for DDR3 PLL supply current 1 5 PLL sustained supply current 0 93 Icc vccio Processor I O supply current 8 5 A I Processor I O supply sustained 8 5 A CC VCCIO TDC current m Notes 1 VCCSA must be provided using a separat
146. ss menm 38 LEXSnpe IIn em 39 3 1 Intel Virtualization Technology Intel rad kil Ege 39 3 1 1 Intel virtualization Technology Intel VT for IA 32 Intel 64 and Intel Architecture Intel VT x Objectives bw la daa Eae eril 39 3 1 2 Intel virtualization Technology Intel VT for IA 32 Intel 64 and Intel Architecture Intel VT x Features ebd nw ed ail Gate ia Carat 40 3 1 3 Intel Virtualization Technology Intel VT for Directed I O Intel VT d Objectives E dba ba 40 3 1 4 Intel Virtualization Technology Intel VT for Directed I O Intel VT d 41 3 1 5 Intel Virtualization Technology Intel VT for Directed 1 0 Intel VT d Features Not Supported cceeee eene 41 3 2 Intel Trusted Execution Technology Intel TXT eeeseeesee nne 42 3 3 Intel Hyper Threading Technology Intel HT 42 3 4 Intel Turbo Boost Technology iii sisinissccegssvassecsuvanicts orbc rcc eG c c 43 3 4 1 Intel Turbo Boost Technology Frequency cceee nene 43 3 4 2 Intel Turbo Boost Technology Graphics 43 3 5 Intel Advanced Vector Extensions Intel 44 3 6 Security and Cryptography TechnoloGies ccccceeee eee eee ee eee ee
147. ss this interface This also does not account for packet overhead and link maintenance Maximum theoretical bandwidth on the interface of 16 GB s in each direction simultaneously for an aggregate of 32 GB s when x16 Gen 3 Hierarchical PCI compliant configuration mechanism for downstream devices Traditional PCI style traffic asynchronous snooped PCI ordering PCI Express extended configuration space The first 256 bytes of configuration space aliases directly to the PCI Compatibility configuration space The remaining portion of the fixed 4 KB block of memory mapped space above that starting at 100h is known as extended configuration space PCI Express Enhanced Access Mechanism Accessing the device configuration space in a flat memory mapped fashion Automatic discovery negotiation and training of link out of reset Traditional AGP style traffic asynchronous non snooped PCI X Relaxed ordering Peer segment destination posted write traffic no peer to peer read traffic in Virtual Channel 0 DMI gt PCI Express Port 0 64 bit downstream address format however the processor never generates an address above 64 GB Bits 63 36 will always be zeros 64 bit upstream address format however the processor responds to upstream read transactions to addresses above 64 GB addresses where any of Bits 63 36 are nonzero with an Unsupported Request response Upstream write transactions to addresses above 64 GB will
148. tion Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family 326766 Specification Update Desktop 3rd Generation Intel Core Processor Family Desktop Intel Pentium Processor Family Desktop Intel Celeron Processor Family and 326767 LGA1155 Socket Thermal Mechanical Specifications and Design Guidelines Advanced Configuration and Power Interface Specification 3 0 http www acpi info PCI Local Bus Specification 3 0 PCI Express Base Specification 2 0 http www pcisig com speci fications http www pcisig com DDR3 SDRAM Specification http www jedec org DisplayPort Specification Intel 64 and 32 Architectures Software Developer s Manuals http www vesa org http www intel com produ cts processor manuals inde h x htm Volume 1 Basic Architecture 253665 Volume 24A Instruction Set Reference A M 253666 Volume 2B Instruction Set Reference N Z 253667 Volume 3A System Programming Guide 253668 Volume 3B System Programming Guide 253669 Note Contact your Intel representative for the latest revision of this item 88 22 Datasheet Volume 1 Interfaces 2 2 1 2 1 1 Note Note Note Table 2 Note Datasheet Interfaces This chapter describes the interfaces supported by the processor System Memory Interface System Memory Technology Supported The Integrat
149. torage well for current when entering an idle condition from a running condition To keep voltages within specification output decoupling must be properly designed Design the board to ensure that the voltage provided to the processor remains within the specifications listed in Table 7 4 Failure to do so can result in timing violations or reduced lifetime of the processor Voltage Rail Decoupling The voltage regulator solution needs to provide bulk capacitance with low effective series resistance ESR a low interconnect resistance from the regulator to the socket e bulk decoupling to compensate for large current swings generated during poweron or low power idle state entry exit The power delivery solution must ensure that the voltage and current specifications are met as defined in Table 7 4 Datasheet Volume 1 75 a 8 Electrical Specifications 7 3 1 7 4 Note 76 Processor Clocking BCLK 0 BCLK 0 The processor uses a differential clock to generate the processor core operating frequency memory controller frequency system agent frequencies and other internal clocks The processor core frequency is determined by multiplying the processor core ratio by the BCLK frequency Clock multiplying within the processor is provided by an internal phase locked loop PLL that requires a constant frequency input with exceptions for Spread Spectrum Clocking SSC The processor s maximum non turbo core frequency
150. transfer rates of 1333 MT s and 1600 MT s The DDR3 data transfer rates supported by the processor is dependent on the PCH SKU in the target platform Desktop PCH platforms support 1333 MT s and 1600 MT s for One DIMM and Two DIMMs per channel All In One platforms AIO support 1333 MT s and 1600 MT s for One DIMM and Two DIMMs per channel 64 bit wide channels System Memory Interface I O Voltage of 1 5 V DDR3 and DDR3L DIMMs DRAMs running at 1 5 V No support for DDR3L DIMMs DRAMS running at 1 35 V 11 Introduction Support memory configurations that mix DDR3 DIMMs DRAMs with DDR3L DIMMs DRAMs running at 1 5 V The type of the DIMM modules supported by the processor is dependent on the PCH SKU in the target platform Desktop PCH platforms support non ECC UDIMMs only All In One platforms AIO support SO DIMMs Theoretical Maximum Memory Bandwidth 10 6 GB s in single channel mode or 21 3 GB s in dual channel mode assuming DDR3 1333 MT s 12 8 GB s in single channel mode or 25 6 GB s in dual channel mode assuming DDR3 1600 MT s Processor on die Reference Voltage VREF generation for both DDR3 Read RDVREF and Write VREFDQ 1Gb 2Gb and 4Gb DDR3 DRAM device technologies are supported Using 4Gb DRAM device technologies the largest memory capacity possible is 32 GB assuming Dual Channel Mode with four x8 dual ranked DIMM memory configuration Up to 64 simultaneous open pages 32 per channel assuming 8
151. tualization or binary translation This means that they will be able to run off the shelf operating systems and applications without any special steps Enhanced Intel VT enables VMMs to run 64 bit guest operating systems on IA x86 processors More reliable Due to the hardware support VMMs can now be smaller less complex and more efficient This improves reliability and availability and reduces the potential for software conflicts More secure The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system Datasheet Volume 1 39 Technologies 3 1 2 Intel Virtualization Technology Intel VT for IA 32 Intel 64 and Intel Architecture Intel VT x Features The processor core supports the following Intel VT x features e Extended Page Tables EPT EPT is hardware assisted page table virtualization It eliminates VM exits from guest operating system to the VMM for shadow page table maintenance e Virtual Processor IDs VPID Ability to assign a VM ID to tag processor core hardware structures such as TLBs This avoids flushes on VM transitions to give a lower cost VM transition time and an overall reduction in virtualization overhead e Guest Preemption Timer Mechanism for a VMM to preempt the execution of a guest operating system after an amount of time specified by the VMM The VMM sets a tim
152. tures Memory controller and processor graphics comply with Intel VT d 1 2 specification Two VT d DMA remap engines iGFX DMA remap engine DMI PEG Support for root entry context entry and default context 39 bit guest physical address and host physical address widths Support for 4K page sizes only Support for register based fault recording only for single entry only and support for MSI interrupts for faults Support for both leaf and non leaf caching Support for boot protection of default page table Support for non caching of invalid page table entries Support for hardware based flushing of translated but pending writes and pending reads on IOTLB invalidation Support for page selective IOTLB invalidation MSI cycles MemWr to address xxxxh not translated Translation faults result in cycle forwarding to VBIOS region byte enables masked for writes Returned data may be bogus for internal agents PEG DMI interfaces return unsupported request status Interrupt Remapping is supported Queued invalidation is supported VT d translation bypass address range is supported Pass Through Note Intel VT d Technology may not be available on all SKUs 3 1 5 Intel virtualization Technology Intel VT for Directed I O Intel VT d Features Not Supported The following features are not supported by the processor with Intel VT d Datasheet Volume 1 No support for PCIe endpoint caching ATS No support for
153. ward a single thread wakes only that thread However since both threads are no longer at the same core C state the core resolves to CO A system reset re initializes all processor cores Core CO State The normal operating state of a core where code is being executed Datasheet Volume 1 Power Management intel 4 2 4 2 4 2 4 3 4 2 4 4 4 2 4 5 Core C1 C1E State C1 C1E is a low power state entered when all threads within a core execute a HLT or MWAIT C1 C1E instruction A System Management Interrupt SMI handler returns execution to either Normal state or the C1 C1E state See the Intel 64 and IA 32 Architecture Software Developer s Manual Volume 3A 3B System Programmer s Guide for more information While a core is in C1 C1E state it processes bus snoops and snoops from other threads For more information on C1E see Package C1 C1E Core C3 State Individual threads of a core can enter the C3 state by initiating a P_LVL2 I O read to the P BLK or an MWAIT C3 instruction A core in C3 state flushes the contents of its L1 instruction cache L1 data cache and L2 cache to the shared L3 cache while maintaining its architectural state All core clocks are stopped at this point Because the core s caches are flushed the processor does not wake any core that is in the C3 state when either a snoop is detected or when another core accesses cacheable memory Core C6 State Individual threads of a core can enter th
154. which the clients as processor PECI can pull up high with strong drive The idle state on the bus is near zero Figure 7 1 demonstrates PECI design and connectivity while the host originator can be 3rd party PECI host and one of the PECI clients is the processor PECI device Example for PECI Host Clients Connection G lt T ay pees Host Originator Client Additional Clients Datasheet Volume 1 Electrical Specifications m L 7 11 2 DC Characteristics The PECI interface operates at a nominal voltage set by Vccro The DC electrical specifications shown in Table 7 10 are used with devices normally operating from a Vccro interface supply Vccro nominal levels will vary between processor families All PECI devices will operate at the Vccjg level determined by the processor installed in the system For specific nominal Vccro levels refer to Table 7 5 Table 7 10 PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Notes Rup Output resistance 15 45 3 Vin Input Voltage Range 0 15 Vccio Vnysteresis Hysteresis 0 1 Vccio N A V Vn Negative Edge Threshold Voltage 0 275 Vccro 0 500 V Vp Positive Edge Threshold Voltage 0 550 Vecig 0 725 Vecio V Cbus Bus Capacitance per Node N A 10 pF Cpad Pad Capacitance 0 7 1 8 pF Ileak000 leakage current at OV 0 6 mA Ileak025 leakage
155. ynchronous CMOS SKTOCC SKTOCC Socket Occupied This signal is pulled down directly 0 Ohms on the processor package to the ground There is no connection to the processor silicon for this signal System board designers may use this signal to determine if the processor is present PROC_SEL Processor Select This signal is an output that indicates if the processor used is 2nd Generation Intel Core processor family desktop Intel Pentium processor family desktop Intel Celeron processor family desktop or Desktop 3rd Generation Intel Core processor family Desktop Intel Pentium processor family Desktop Intel Celeron processor family For 2nd Generation Intel Core processor family desktop Intel Pentium processor family desktop Intel Celeron processor family desktop the output will be high For Desktop 3rd Generation Intel Core processor family Desktop Intel Pentium processor family Desktop Intel Celeron processor family the output will be low VCCIO_SEL Voltage selection for VCCIO This output signal was initially intended to select the I O voltage depending on the processor being used Since the Vccro voltage is the same for 2nd Generation Intel Core processor family desktop Intel Pentium processor family desktop Intel Celeron processor family desktop and Desktop 3rd Generation Intel Core processor family Desktop Intel Pentium processor

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