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Elixir 8GB DDR3 SO-DIMM

1. E VDD VDD Cterm Cterm F vit vit J vt sEREEZEBERS B eene oPeos osog 2 5658 gt 2400hm 2400hm 2400hm 2400hm pass pas edes pas Sd EIS pas RENE pas SEN 02954 0053 J Das Das 005 2m 005 zaw DM3 WM DM DM M DM4 DQ 24 31 M DQ 0 7 D11 DQ 0 7 D3 DQ 0 7 D4 DQ 0 7 D12 L N DQ 32 39 Il Il Ww E 5 5 5 a amp MAREE aegRESsSEBE Bi BERRESEEBRE P osoo oot P osoo ootf SECO Soe 5 www J NEL ES por pop 3 EN Pm 240ohm 240ohm 240ohm 240ohm DOS JN pas ES pas pas ESO pas SENS L N pase 0051 Das Das Zo eee 005 005 za DM1 M DM E DM DM DM E M DM6 DQ 8 15 DQ 0 7 D1 DQ 0 7 D9 DQ 0 7 D14 DQ 0 7 D6 2 8 55 x S 5 a amp 5 BEBESSS82 BERBSESBE BEBESESS2 eBB ESSSBS Of oszoo oscr O Posoo otr osoo ooE Oposoo ottr A A 240o0hm 2400hm 2400hm 2400hm paso JN pas edes pas Ee
2. 2500 330 WL 6 tCK AVG Reseved Reserved mns WL 7 tCK AVG Reserved ns WL 5 tCK AVG Reseved Reserved O Z o Q WL 6 tCK AVG 1 875 lt 25 __ WL 7 tCK AVG Reserved Reseved o o WL 5 tCK AVG Reserved Reserved _ ns o WL 6 tCK AVG 1 875 lt 25 jns t Q A tCK AVG Reserved Reserved O o WL 5 Reserved Reserved WL 6 Reserved 1 875 WL 5 Reserved Reserved WL 6 Reserved Reserved WL 7 1 500 1 875 WL 5 Reserved WL 6 Reserved WL 7 Reserved Reserved WL 8 1 25 lt 1 5 upported CL Settings 5 6 7 8 9 10 11 upported CWL Settings 6 7 8 Optional 1 i 5 i 5 Q 1 0 11 06 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2S4G64CB88B5N M288G64CB8HB5N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SO DIMM elixir AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1066MHz Glock Absolute Clock Period tCK abs Absolute clock HIGH pulse width tCH abs Absolute clock LOW pulse width tCL abs Cumulative error across i2cydes _ _ _ ERR 2pen DQ low impedance time from CK CK tLZ DQ DQ high impedance time from CK tHZ DQ AC150 tDH base P ative
3. 10ns Exit Self Refresh to commands not requiring a locked DLL tXS tXSmax tXSDLLmin tDLLK min Exit Self Refresh to commands requiring a locked DLL tXSDLL tXSDLLmax tCKESRmin tCKE min 1 nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR tCKESRmax Valid Clock Requirement after Self Refresh Entry SRE ICKSRE tCKSREmin max 5 nCK 10 ns or Power Down Entry PDE tCKSREmax Valid Clock Requirement before Self Refresh Exit SRX ICKSRX tCKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax Power Down Timings Exit Power Down with DLL on to valid command tXPmin max 3nCK 6ns Exit Precharge Power Down with DLL frozen to commands tXPmax not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands XPDLL tXPDLLmin max 10nCK 24ns requiring a locked DLL tXPDLLmax tCKEmin max 3nCK 5ns CKE minimum pulse width tCKE tCKEmax tCPDEDmin 1 Command pass disable delay tCPDED tCPDEDmin tPDmin tCKE min Power Down Entry to Exit Timing tPDmax 9 tREFI tACTPDENmin 1 Timing of ACT command to Power Down entry tACTPDEN tACTPDENmax tPRPDENmin 1 Timing of PRE or PREA command to Power Down entry tPRPDEN tPRPDENmax REV 1 0 19 06 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2S4G
4. tes S Cumulative erroracross4cycles ERRMpe __ 130 Cumulative eror across Scycles Cumulative eroracross6cycles RN amp pe Cumulative error across 7 oyoles HERAT tsps S Cumulative error across 8 cycles tERR 26 Cumulative error aoross 9 oyoles Cumulative error across 10 cycles _ Cumulative error across 11 cycles as S Cumulative error across 12 cycles _ o o ts S tERR nper min 1 0 68In n tJIT per min Cumulative error across 13 14 49 50 cycles tERR nper tERR nper max 1 0 68In n tJIT per max O DOS DAS to DA skew per group peraccess feasa DQoutputholdtimefromoas oas DOlowimpedane metomCK CKE DQhighimpedenetimetomCK CKF oo eps tDS Data setup time to DQS DQS referenced to Vih ac Vil ac levels 175 tDS base Data setup time to DQS DQS referenced to Vih ac Vil ac levels AC180 10 tDH base Data hold time from DQS DQS referenced to Vih dc Vil dc levels DC100 DQandDMipupusewidhforeachinput iw pg sss mee cte c een DQS DOS differential READ Preamble eere 09 Nee DOS DOSE differential READ Postamble os DOS DASE diffe
5. The system clock inputs All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK A Delay Locked Loop DLL circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high When the command decoder is disabled new commands are ignored but previous operations continue Rank 0 is selected by S0 Rank 1 is selected by S1 When sampled at the positive rising edge of CK and falling edge of CK signals RAS CAS WE define the operation to be executed by the SDRAM Asserts on die termination for DQ DM DQS and DQS signals if enabled via the DDR3 SDRAM mode register The data write masks associated with one data byte In Write mode DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high In Read mode DM lines have no effect The data strobes associated with one data byte sourced with data transfers In Write mode the data strobe is sourced by the controller and is centered in the data window In Read mode the data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window DQS
6. crossing Write leveling hold time from rising DQS DQS tWLH 165 crossing to rising CK crossing Write leveling output delay WLO L0 S vs fe T Write leveling output error po rs REV 1 0 20 06 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice 254664 88 5 M288G64CB8HB5N 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SO DIMM Package Dimensions 4GB 1 Rank 512Mx8 DDR3 SDRAMs 67 60 0 15 2 661 0 006 2 0 lt 63 60 gt 3 8 0 079 2 504 0 150 30 0 0 15 1 181 0 006 0 787 1 0 0 07 0 1 S Detail A 21 0 39 0 0 827 1 535 3 0 0 118 1 35 0 053 Detail A Units Millimeters Inches Note Device position and scale are only for reference REV 1 0 06 2012 2x 1 80 0 157 0 004 2x 4 0 0 1 0 6 0 024 Detail B 21 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice 254664 88 5 M288G64CB8HB5N 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SO DIMM Package Dimensions BGB 2 Ranks 512 8 DDR3 SDRAMs 67 60 0 15 2 661 0 006 2 0 63 60 gt 3 8 0 079 2 504 0 150
7. error across n 13 14 49 50 cycles tDSH REV 1 0 06 2012 DDR3 1066 2 Refer Standard Speed Bins 0 47 0 53 0 47 0 53 Min tCK avg min tJIT per min A avg 9 A Max tCK avg max tJIT per max 0 43 0 43 6 6 X X a ojo 132 157 175 188 200 209 217 224 231 237 242 tERR nper min 1 0 681 tJIT per min tERR nper max 1 0 68In n tJIT per max AJo 142 a wo wo e wo e EN a B o 19 11 CK avg CK avg CK avg avg A 9 A lt A 2 lt e avg avg wo e co 9 A co e A EN a mo a e o io a a 12 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2S4G64CB88B5N M2S8G64CB8HB5N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 e IXI r Unbuffered DDR3 SO DIMM tRTPmin max 4nCK 7 5ns Internal READ Command to PRECHARGE Command delay tRTP tRTPmax Delay from start of internal write WTR tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery time wR Pts Mode Register Set command cycle time Pk
8. not requiring a locked DLL XS tXSmax us tXSDLLmin tDLLK min Exit Self Refresh to commands requiring a locked DLL tXSDLL tXSDLLmax tCKESRmin tCKE min 1 nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR tCKESRmax Valid Clock Requirement after Self Refresh Entry SRE ICKSRE tCKSREmin max 5 nCK 10 ns or Power Down Entry PDE tCKSREmax Valid Clock Requirement before Self Refresh Exit SRX tCKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax tXPmin max 3nCK 7 5ns tXPmax O A n 2 Power Down Timings Exit Power Down with DLL on to any valid command X Uu Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL tXPDLLmin max 10nCK 24ns tXPDLLmax tCKEmin max 3nCK 5 625ns tCKEmax tCPDEDmin 1 nC tCPDEDmin tPDmin tCKE min tPDmax 9 tREFI tACTPDENmin 1 tACTPDENmax tPRPDENmin 1 CKE minimum pulse width Command pass disable delay Power Down Entry to Exit Timing K K Timing of ACT command to Power Down entry CK D T 4 o E m 2 2 Timing of or PREA command to Power Down entry REV 1 0 06 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice i gt M2S4G64CB
9. pas pas SER 0050 1 Das Be We Das zaw 005 005 29 1 4N DM 5 DM i DM DM 7 DM7 0 7 N 0 7 Do DQIO 7 D8 DQ 0 7 D15 DQ 0 7 D7 4V DQ 56 63 er er 5 5 5 5 T T lt e a m 5 5 YRS 5 5 BEBESBses BEBESBses BERESSESE KAA Rh A A 240 2400hm 2400hm 2400hm pas2 DOS 1 pas 1 pas 1 pas 1 pass 0052 Das Das ZQ W _ 005 eSI WF 005 29 01 pass DM2 N DM E DM E DM DM5 DQ 16 23 2 0 7 D2 DQ 0 7 D10 DQ 0 7 D13 DQ 0 7 D5 I N DQI40 47 er x S 5 5 5 5 Roh L 4 4 gg gg if LA RAAR eee wg T hoh d hhh hd AN vit SCL SCL Vobsep gt SPD sao Ao SPD Vacron y 00 015 SDA 1 gt A1 gt 00 015 A2 WP Vo 00 015 Eq Vss 44 00 015 SPD _____________ 00 07 Notes cki 08 015 1 DQ wiring may differ from that shown however DM CKO gt 00 07 DQS and DOS relationships are maintained as
10. rising DQS DQS crossing Write leveling hold time from rising DQS DQS crossing to rising CK CK crossing Write leveling output delay WLO T o wi Write leveling output error o 00 rs REV 1 0 17 06 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2S4G64CB88B5N M2S8G64CB8HB5N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 e IXI r Unbuffered DDR3 SO DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1600MHz C a 1 e O O Parameter Symbol Units P E Minimum Glock Cycle Time DLL off mode Average Clock Period Reter to Standard Speed Bin ps J o Average high pulse width oo 04 __ 05 Average low pulsewidth 0 oao Absolute Clock Period tCK abs Max tCK avg max tJIT per max Absolute clock HIGH pulsewidth os 0 Absolute clock LOW pulse width tabs 09 e o e Clock Period Jitter during DLL locking period Cycle to Cycle Period siter _______ to tos S Cycle to Cycle Period during DLL locking period nea S Duty Cyce ster ftir Ps Cumulative error across 2cycles as tps S Cumulative error aoross 3oyoles ae
11. shown gt 08 015 CKEO 00 07 CKE1 08 015 50 00 07 08 015 00 07 1 08 015 RESET 00 015 REV 1 0 6 06 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2S4G64CB88B5N M288G64CB8HB5N 4GB 512M 64 8GB 1024M x 64 PC3 10600 PC3 12800 e IXI r Unbuffered DDR3 SO DIMM Environmental Requirements ToPR Operating Temperature ambient 0 to 85 TsrG Storage Temperature 55 to 100 Note Stress greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability Absolute Maximum DC Ratings Vpp Voltage on VDD pins relative to Vss 0 4 V 1 975 V V VDDQ Voltage on VDDQ pins relative to Vss 0 4 V 1 975 V V 1 3 Vin Vout Voltage on I O pins relative to Vss 0 4 V 1 975 V V 1 TsrG Storage Temperature 55 to 100 C 1 2 Note 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or an
12. signals are complements and timing is relative to the cross point of respective DQS and DAQS If the module is to be operated in single ended strobe mode all DQS signals must be tied on the system board Vss and DDR3 SDRAM mode registers programmed appropriately Selects which DDR3 SDRAM internal bank of four or eight is activated During a Bank Activate command cycle defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK During a Read or Write command cycle defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK In addition to the column address AP is used to invoke autoprecharge operation at the end of the burst read or write cycle If AP is high autoprecharge is selected and BAO BAn defines the bank to be precharged If AP is low autoprecharge is disabled During a Precharge command cycle AP is used in conjunction with BAO BAn to control which bank s to precharge If AP is high all banks will be precharged regardless of the state of BAO BAn inputs If AP is low then BAO BAn are used to define which bank to precharge Data Input Output pins Power supplies for core I O Serial Presence Detect Temp sensor and ground for the module Reference voltage for SSTL15 inputs This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor A resistor must be connected from the SDA bus line to Vopsep on the sy
13. to first data 13 125 5 20 000 13 5 ACT to internal read or write delay time tRCD 13 125 Jom 13 125 ACT to ACT or REF command period t My P 49 125 5 Zu ACT to PRE command period RAS 36 000 9 tREFI ns CK AVG 3 me Q iL a CL 5 iL A 2 lt g 565 gt lt lt Qo iL A gt lt 25 0 E 1 500 lt 1875 ns i 55 A 2 lt gt gt lt lt 22 I N gt gt lt lt 9o rr an lt lt lt lt 9o 875 55 A 2 lt g I oa Q N 5 d i a o Bla I LALA LA gt lt I N REV 1 0 10 06 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2S4G64CB88B5N M2S8G64CB8HB5N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 e IXI r Unbuffered DDR3 SO DIMM DDR3 1600MHz DI 13 75 Internal read command to first data 13 1 255 ACT to internal read or write delay time tRCD 13 79 13 125 5 t t symbol 13 75 PRE command period 13 125 9 ACT to ACT or REF command period HN 48 125 ACT to PRE command period 35 000 WL 5 3 000 L 5 WL 6 WL 7 WL 5 tCK AVG
14. 1 DQ41 1 2010 N 02 2942 02 2911 103 D1 DQ43 103 D5 2912 04 2944 04 2013 105 2045 N 105 2914 6 2946 1 06 pais N 07 za rS 2047 N O7 za AL AL DQS2 NS Dase NS DQS2 0 Dase DM2 DM6 M DM CS Das 595 DM CS Das 595 pais N 1 00 DQ48 100 2917 N 1 2949 JN VO 1 pais 102 DQ50 1 02 DQi9 N O3 D2 DQ51 N j 103 D6 DQ20 N 1 04 DQ52 04 2921 5 2953 N 4 5 2922 1 06 2954 1 06 2923 1 07 za pass N 07 za m mu 56953 M 5 57 M 0983 DQS7 DM3 DM7 DM CS Das Das DM CS Das Das DQ24 1 00 pase 100 2025 N 1 DQ57 N 1 DQ26 N 2 pass O2 DQ27 N 1 03 D3 DQ59 N 103 D7 DQ28 1 04 N 1 04 DQ29 1 05 DQ61 105 DQ30 1 06 DQ62 N 1 06 107 za gt DQ63 N 107 za aL AL SCL ScL Vobsep gt SPD SAO gt AO SPD Vopb Vbpa zu 9 00 07 sai 1 gt SDA e 00 07 A2 Vss 00 7 gt TC Vrerca 9 gt 00 07 2 gt SDRAMs 00 07 15 1 1 SDRAMs 00 07 RAS gt RAS SDRAMs 00 07 DDR3 CAS W___
15. 21 0 30 0 0 15 1 181 0 006 0 787 0 827 1 35 0 053 Detail A Units Millimeters Inches Note Device position and scale are only for reference REV 1 0 06 2012 39 0 1 535 2x 21 80 0 071 0 157 0 004 2x 4 0 0 1 0 25 max 0 010 max 0 45 4 0 03 72 0 018 0 001 06 0 024 Detail B 22 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice 254664 88 5 M288G64CB8HB5N 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SO DIMM Revision Log Rev Date Modification 0 1 03 2012 Preliminary Release 1 0 06 2012 Official Release REV 1 0 23 06 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice
16. 34 DQi4 85 9 86 A7 137 0054 138 Vs 187 DM7 188 0057 35 DQ11 36 0015 87 88 139 Vas 140 0038 189 190 Vss 37 38 Va 89 A8 090 A6 141 0034 142 0039 191 0058 192 0062 39 0016 40 DQ20 91 AS 92 A4 143 0035 144 193 0059 194 0063 41 0017 42 DQ21 93 Vo 94 Vo 145 Vs 146 0044 195 Vs 196 Vss 43 44 Vs 95 9 2 147 0040 148 0045 197 SAO 198 EVENT 45 DOSZ 46 DM2 97 98 149 0041 150 199 Voose 200 SDA 47 0052 48 Vss 99 Vo 100 Vo 151 152 0055 201 SA 202 SCL 49 50 0022 101 CKO 102 153 5 154 0085 203 Vt 204 51 0018 52 0023 103 CKO 104 REV 1 0 06 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2S4G64CB88BS5N M2S8G64CB8HB5N 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SO DIMM Input Output Functional Description Symbol CKO CK1 CKO CK1 CKE1 0 51 RAS WE ODTO ODT1 DMO DM7 DQS0 DQS7 DQS0 DQS7 BAO BA1 BA2 A0 A9 A10 AP A11 A12 BC A13 A15 000 DQ63 Vss Vnerpa VREFCA SDA REV 1 0 06 2012 Type Polarity Cross Input point Active Input High Active Input Low Active Input Low Active Input High Active Input High Cross VO point Input Input Input Supply Supply Input Input Output Input x Supply Function
17. 600 PC3 12800 el IXI r Unbuffered DDR3 SO DIMM Ordering Information M2S4G64CB88B5N CG DDR3 1333 10600 667MHz 1 500ns CL 9 512Mx64 M2S8G64CB8HB5N CG DDR3 1333 PC3 10600 667MHz 1 500ns CL 9 1024Mx64 M2S4G64CB88B5N DI DDR3 1600 PC3 12800 800MHz 1 250ns CL 11 512 64 M288G64CB8HB5N DI DDR3 1600 PC3 12800 800MHz 1 250ns CL 11 1024Mx64 1 5V Gold Pin Description CKO CK1 Clock Inputs positive line 0090 0063 Data input output CKO CK1 Clock Inputs negative line DQS0 DQS7 Data strobes CKEO CKE1 Clock Enable DQS0 DQS7 Data strobes complement RAS Row Address Strobe DMO DM7 Data Masks CAS Column Address Strobe EVENT Temperature event pin WE Write Enable RESET Reset pin S0 51 Chip Selects Vnerba VnEFCA Input output Reference A0 A9 A11 A13 A15 Address Inputs Vopspp SPD and Temp sensor power A10 AP Address Input Auto Precharge SAO SA1 Serial Presence Detect Address Inputs A12 BC Address Input Burst Chop Vtt Termination voltage BAO BA2 SDRAM Bank Address Inputs Vss Ground ODTO ODT1 Active termination control lines Vop Core and I O power SCL Serial Presence Detect Clock Input NC No Connect SDA Serial Presence Detect Data input output REV 1 0 2 06 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2S4G64CB88BS5N M288G64CB8HB5N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SO DIMM D
18. 64CB88B5N M288G64CB8HB5N 4GB 512M x 64 8GB 1024M x 64 elixir PC3 10600 PC3 12800 Unbuffered DDR3 SO DIMM ree Timing of RD RDA command to Power Down entry tRDPDEN tRDPDENmax tWRPDEN BL8OTF BL8MRS 4 tWRPDENmax minno mmm e tWRAPDEN BL8MRS 4 tWRAPDENmax IWRPDENmin WL 2 WR 1 pem _ tWRAPDEN BC4MRS tWRAPDENmax GGG NUN Timing of REF command to Power Down entry tREFPDEN tREFPDENmax Timing of MRS command to Power Down entry tMRSPDEN ODT Timings high time without write command or ODTH4min 4 ODTH4 with write command and 4 ODTH4max ODTH8min 6 ODT high time with Write command and BL8 ODTH8 ODTH8max Asynchronous RTT turn on delay tAONPD 2 8 5 Power Down with DLL frozen Asynchronous RTT turn off delay tAOFPD 2 8 5 Power Down with DLL frozen RTT turn on tAON Ooo om zs e RTT_Nom and RTT_WR turn off time tAOF 0 3 0 7 tCK avg from ODTLoff reference RTT dynamic change skew Pos o7 oag Write Leveling Timings eee 14 eee First DQS DQS rising edge after tWLMRD nCK write leveling mode is programmed DQS DQS delay after write leveling mode is programmed nk Write leveling setup time from rising CK tWLS 165 crossing to rising DQS DQS
19. 88B5N M288G64CB8HB5N 4GB 512M x 64 8GB 1024M x 64 elixir PC3 10600 PC3 12800 Unbuffered DDR3 SO DIMM e BRI 90 RI Timing of RD RDA command to Power Down entry tRDPDEN tRDPDENmax Timing of WR command to Power Down entry IWRPDEN IWRPDENmin WL 4 tWR tCK avg BL8OTF BL8MRS 4 tWRPDENmax Lor NN RN CNN CN GN tWRAPDEN BL8OTF BL8MRS 4 tWRAPDENmax IWRPDENnin WL 2 WR tCK avg WRPDENmax vie p _ tWRAPDEN BC4MRS tWRAPDENmax e Timing of REF command to Power Down entry tREFPDEN tREFPDENmax Timing of MRS command to Power Down entry tMRSPDEN ODT Timings NENNEN NEN high time without write command or ODTH4min 4 ODTH4 with write command and 4 ODTH4max ODTH8min 6 ODT high time with Write command and BL8 ODTH8 ODTH8max Asynchronous RTT turn on delay tAONPD 2 8 5 Power Down with DLL frozen Asynchronous RTT turn off delay tAOFPD 2 8 5 Power Down with DLL frozen RTT turn on tAON __ w RTT Nom and RTT WR turn off time tAOF 0 3 0 7 tCK avg from ODTLoff reference RTT dynamic change skew tADC Pos oz oao Write Leveling Timings poene cvm xp ig ee p First DQS DQS rising edge after tWLMRD nCK write leveling mode is programmed DOS DOS delay after write leveling mode is programmed WLDOSEN fh nk S Write leveling setup time from risin
20. B 1024M x 64 elixir PC3 10600 PC3 12800 Unbuffered DDR3 SO DIMM e BRI 0 RI Timing of RD RDA command to Power Down entry tRDPDEN tRDPDENmax Timing of WR command to Power Down entry IWRPDEN tWRPDENmin WL 4 tCK avg BL8OTF BL8MRS 4 tWRPDENmax a NNNM CNN CN GN tWRAPDEN BL8MRS 4 tWRAPDENmax IWRPDENmin WL 2 WR 1 _ tWRAPDEN BC4MRS tWRAPDENmax E NN NUN Timing of REF command to Power Down entry tREFPDEN tREFPDENmax Timing of MRS command to Power Down entry tMRSPDEN ODT Timings NENNEN high time without write command or ODTH4min 4 ODTH4 with write command and 4 ODTH4max ODTH8min 6 ODT high time with Write command and BL8 ODTH8 ODTH8max Asynchronous RTT turn on delay tAONPD 2 8 5 Power Down with DLL frozen Asynchronous RTT turn off delay tAOFPD 2 8 5 Power Down with DLL frozen RTT turn on tAON e RTT Nom and RTT WR turn off time tAOF 0 3 0 7 tCK avg from ODTLoff reference RTT dynamic change skew tADC Poo O o7 Write Leveling Timings nn eee Se re First DQS DQS rising edge after tWLMRD write leveling mode is programmed DOS DOS delay after write leveling mode is programmed WLDOSEN fh nk S Write leveling setup time from rising CK WLS crossing to
21. DR3 SDRAM Pin Assignment Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 2 Vs 53 0019 54 Ves 105 Voo 106 155 156 Vss 3 4 004 55 Vs 56 DQ28 107 AI0 AP 108 157 0042 158 0046 5 6 DQ 57 0024 58 DQ29 109 BAO 110 RAS 159 0043 160 DQ47 7 pat 8 Va 59 0025 60 Va 111 Vos 112 161 Ves 162 Ves 9 10 DOSO 61 Vs 62 DOSS 13 WE 114 50 163 0048 164 0052 DMO 12 DQSO 63 DM3 64 DQS3 115 CAS 116 165 0049 166 DQ53 13 Vas i4 Ves 65 Va 66 Vae 117 Vo 118 Vw 167 Vs 168 15 DQ2 16 67 DQ26 68 0030 119 A13 NC 120 ODT 169 0055 170 DM6 17 18 69 0027 70 0031 121 ST 122 NC 171 pase 172 Ves 19 Ve 20 Ve 71 Va 72 Ves 123 Vo 124 173 Ves 174 0054 21 DQ8 22 0012 73 CKEO 74 1 125 126 Vac 175 0050 176 0055 23 pag 24 0013 75 V 76 127 Ves 128 Vas 177 0051 178 Ves 25 26 Va 77 78 15 129 DQ32 130 DQ36 179 Vas 180 DQ60 27 DOST 28 DMI 79 80 14 131 0033 132 0037 181 0056 182 0061 29 past 30 RESET 81 82 Vo 133 134 Vas 183 DQ57 184 Vss 31 Vs 32 Vs 83 12 8 84 135 054 136 DM4 185 Vs 186 0057 33 000
22. M2S4G64CB88B5N M288G64CB8HB5N 512 64 8 1024 64 10600 12800 Unbuffered DDR3 SO DIMM Based on DDR3 1333 1600 512Mx8 SDRAM B Die Features Performance PC3 10600 PC3 12800 Speed Sort CG DI DIMM CAS Latency 9 11 fck Clock Fregency 667 800 tck Clock Cycle 1 5 1 25 fDQ DQ Burst Freqency 1333 1600 204 Pin Small Outline Dual In Line Memory Module SO DIMM e 4GB 8GB 512Mx64 1024Mx64 Unbuffered DDR3 SO DIMM based on 512Mx8 DDR3 SDRAM B Die devices Intended for 667MHz 800MHz applications Inputs and outputs are SSTL 15 compatible VDD VDDQ 1 5V 0 075 SDRAMs have 8 internal banks for concurrent operation Differential clock inputs Data is read or written on both clock edges DRAM DLL aligns DQ and DGS transitions with clock transitions Auto Self Refresh option Nominal and Dynamic On Die Termination support Extended operating temperature rage Description Unit MHz ns Mbps Serial Presence Detect Programmable Operation DIMM CAS Latency 5 6 7 8 9 10 11 Burst Type Sequential or Interleave Burst Length BC4 BL8 Operation Burst Read and Write Address and control signals are fully synchronous to positive clock edge Two different termination values Rtt Nom amp Rtt WR 16 10 1 row column rank Addressing for 4GB 16 10 2 row column rank Addressing for 8GB Gold contacts SDRAMs are in 78 ball BGA Package
23. RoHS compliance and Halogen Free M2S4G64CB88B5N and M2S8G64CB8HBSN are unbuffered 204 Pin Double Data Rate DDR3 Synchronous DRAM Small Outline Dual In Line Memory Module SO DIMM organized as one rank of 512Mx64 4GB and two ranks of 1024Mx64 8GB high speed memory array Modules use eight 512Mx8 4GB and sixteen 512Mx8 8GB 78 ball BGA packaged devices These DIMMs are manufactured using raw cards developed for broad industry use as reference designs The use of these common design files minimizes electrical variation between suppliers All Elixir DDR3 SODIMMs provide a high performance flexible 8 byte interface in a space saving footprint The DIMM is intended for use in applications operating of 667MHz 800MHz clock speeds and achieves high speed data transfer rates of 10600Mbps 12800Mbps Prior to any access operation the device CAS latency and burst length operation type must be programmed into the DIMM by address inputs A0 A15 and I O inputs BAO BA2 using the mode register set cycle The DIMM uses serial presence detect implemented via a serial EEPROM using a standard IC protocol The first 128 bytes of SPD data are programmed and locked during module assembly The remaining 128 bytes are available for use by the customer REV 1 0 06 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2S4G64CB88B5N M2S8G64CB8HB5N 4GB 512M x 64 8GB 1024M x 64 PC3 10
24. ___1_1__ CAS SDRAMs 00 07 SDRAM CKEO SDRAMs 00 07 m Y gt WE SDRAMs 00 07 BA 2 0 80 T gt ODT SDRAMs 00 07 p CK SDRAMs 00 07 DBRS CK SDRAMs 00 07 SDRAM RESET RESET SDRAMs 00 07 Veo Notes 1 DQ to I O wiring is shown as recommended but may be changed 2 DQ DQS DQS ODT DM CKBE S relationships must be maintained as shown 3 For each DRAM a unique ZQ resistor is connected to ground The ZQ resistor is 2400 19 4 One SPD exists per module NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2S4G64CB88B5N M2S8G64CB8HB5N Cel 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 e IXI r Unbuffered DDR3 SO DIMM Functional Block Diagram BGB 2 Ranks 512Mx8 DDR3 SDRAMs
25. arge Current Precharge Power Down Current Slow Exit Precharge Power Down Current Fast Exit Precharge Quiet Standby Current Precharge Standby Current Active Power Down Current Active Standby Current Operating Burst Read Current Operating Burst Write Current Burst Refresh Current Self Refresh Current Normal Temperature Range Operating Bank Interleave Read Current NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2S4G64CB88B5N M2S8G64CB8HB5N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 e IXI r Unbuffered DDR3 SO DIMM Standard Speed Bins DDR3 1066MHz peed Bir 33 1066 IF nF 7 7 7 E Unit Parameter Symbol Mir Max Internal read command to first data 13 125 20 000 nS ACT to internal read or write delay time tRCD 13 125 Mo Ins OES PRE command period 13 125 Eo ms ACT to ACT or REF command period 50 625 ACT to command period tRAS 37 500 9 tREFI ns m CWL 5 tCK AVG 3 000 3 300 Ins CWL 6 tCK AVG Reserved mS CWL 5 2500 330 CWL 5 tCK AVG 2 500 3 300 CL 7 CWL 0 gCKAVG Reserved ms 0 cwL 5 QCKAVG Reserved ms CWL CKAVG 18 5 25 so m cwl 5 Reserved 1 mns 0 CWL 0 JCKAVGQ 18 5 25 0 ms DDR3 1333MHz 5 xc Unit M Ma 13 5 Internal read command
26. data sheet and or the DIMM SPD for option availability b If Self Refresh operation is required in the Extended Temperature Range then it is mandatory to either use the Manual Self Refresh mode with Extended Temperature Range capability MR2 0b and MR2 A7 1b or enable the optional Auto Self Refresh mode MR2 A6 1b and MR2 A7 Ob Please refer to the supplier data sheet and or the DIMM SPD for Auto Self Refresh option availability Extended Temperature Range support and tREFI requirements in the Extended Temperature Range DC Electrical Characteristics and Operating Conditions VDD Supply Voltage 1 425 1 575 VDDQ Output Supply Voltage 1 425 1 5 1 575 V Note 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together T REV 1 0 7 06 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2S4G64CB88B5N M2S8G64CB8HB5N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 e IXI r Unbuffered DDR3 SO DIMM Single Ended AC and DC Input Levels for Command and Address VIH CA DC DC Input Logic High Vref 0 100 VDD Vref 0 100 Vref 0 100 VD V VIL CA DC DC Input Logic Low VSS Vref 0 100 VSS Vref 0 100 VSS Vref 0 100 V VIH CA AC AC Input Logic High Vref 0 175 Note 2 Vref 0 175 Note 2 Vref 0 175 Note 2 V 1 2 VIL CA AC Input Logic Low Note 2 V
27. e delaytime 00 0 00 0 0 0 0 S command period ACT or REF command period RO to CASH command delay eeo a Auto precharge write recovery precharge time WRerowdupiRP Kavg eek Multi Purpose Register Recovery Time MPR ok to PRECHARGE command period RAS Standard Speed Bins tRRDmin max 4nCK 6ns ACTIVE to ACTIVE command period for 1KB page size tRRDmax tRRDmin max 4nCK 7 5ns ACTIVE to ACTIVE command period for 2KB page size tRRDmax Four activate window for 1KB page size posts f Four activate window for 2KB page size IFAW pt rs Command and Address setup time to CK CK tlS base referenced to Vih ac Vil ac levels Command and Address hold time from CK tlH base 120 referenced to Vih dc Vil dc levels Command and Address setup time to CK tlS base AC150 170 referenced to Vih ac Vil ac levels Control and Address Input pulse width for each input NENNEN Calibration Timing uuu Power up and RESET calibration time zai Normal operation Full calibration time Ope se ck ST Normal operation Short calibration time 1296 Reset Timing a eee MU aaa tXPRmin max 5nCK tRFC min 10ns Exit Reset from CKE HIGH to a valid command tXPR Nl fSetfRefresh Timings M tXSmin max 5nCK tRFC min
28. erence approx 15 mV 4 For reference approx VDD 2 15 mV 5 Single ended swing requirement for DQS DQS is 350 mV peak to peak Differential swing requirement for DQS DQS is 700 mV peak to peak REV 1 0 8 06 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2S4G64CB88B5N M288G64CB8HB5N 4GB 512M 64 8GB 1024M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SO DIMM Operating Standby and Refresh Currents Toase 0 85 Vona 1 5V 0 075V PC3 10600 CG 4GB 8GB IDDO IDD1 IDD2PO IDD2P1 IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 Operating One Bank Active Precharge Current Operating One Bank Active Read Precharge Current Precharge Power Down Current Slow Exit Precharge Power Down Current Fast Exit Precharge Quiet Standby Current Precharge Standby Current Active Power Down Current Active Standby Current Operating Burst Read Current Operating Burst Write Current Burst Refresh Current Self Refresh Current Normal Temperature Range Operating Bank Interleave Read Current Operating Standby and Refresh Currents Toase 0 85 Vona 1 5V 0 075V PC3 12800 DI 4GB 8GB IDDO IDD1 IDD2PO IDD2P1 IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 REV 1 0 06 2012 Operating One Bank Active Precharge Current Operating One Bank Active Read Prech
29. g CK tWLS 245 crossing to rising DQS DQS crossing Write leveling hold time from rising DQS DQS tWLH 245 crossing to rising CK CK crossing Write leveling output delay WLO ar T o w Write leveling output error __ 00 rs REV 1 0 14 06 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2S4G64CB88B5N M2S8G64CB8HB5N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 e IXI r Unbuffered DDR3 SO DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1333MHz C a 1 O Parameter Symbol Units p Minimum Glock Cycle Time DLL off mode Average Clock Period Reter to Standard Speed Average high pulsewidth ooo 04 Average low pulsewidth Absolute Clock Period tCK abs Max tCK avg max tJIT per max Absolute clock HIGH pulsewidth 04 Absolute clock LOW pulse width ces 09 Clock Period siter sitio o d 89 _ je S Clock Period Jitter during DLL locking period Cycle Period siter SS twos S Cycle to Cycle Period Jitter during DLL locking period Duty Cyce ster ftir Ps Cumulative error across 2 cycles Cumuatveemoraeoss3cydes HERS aw o tops S Cumulative eroracro
30. ing a locked DLL tXS tXSmax tXSDLLmin tDLLK min Exit Self Refresh to commands requiring a locked DLL tXSDLL tXSDLLmax tCKESRmin tCKE min 1 nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR tCKESRmax Valid Clock Requirement after Self Refresh Entry SRE ICKSRE tCKSREmin max 5 nCK 10 ns or Power Down Entry PDE tCKSREmax Valid Clock Requirement before Self Refresh Exit SRX ICKSRX tCKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax Power Down Timings Exit Power Down with DLL on to valid command tXPmin max 3nCK 6ns Exit Precharge Power Down with DLL frozen to commands tXPmax not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands XPDLL tXPDLLmin max 10nCK 24ns requiring a locked DLL tXPDLLmax tCKEmin max 3nCK 5 625ns CKE minimum pulse width tCKE tCKEmax tCPDEDmin 1 Command pass disable delay tCPDED tCPDEDmin tPDmin tCKE min Power Down Entry to Exit Timing tPDmax 9 tREFI tACTPDENmin 1 Timing of ACT command to Power Down entry tACTPDEN tACTPDENmax tPRPDENmin 1 Timing of PRE or PREA command to Power Down entry tPRPDEN tPRPDENmax REV 1 0 16 06 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2S4G64CB88B5N M288G64CB8HB5N 4GB 512M x 64 8G
31. or write delaytime command period JACTIO ACT or REF command period RO ICAS to CASH command delay too ok y Auto precharge write recovery precharge time WRerowdupiRP Kavg eek Multi Purpose Register Recovery Time MPR ok to PRECHARGE commandperiod eas Standard Speed Bins tRRDmin max 4nCK ens ACTIVE to ACTIVE command period for 1KB page size tRRDmax tRRDmin max 4nCK 7 5ns ACTIVE to ACTIVE command period for 2KB page size IRRD max Four activate window for 1KB page size bw Four activate window for 2KB page size IFAW Command and Address setup time to CK tlS base referenced to Vih ac Vil ac levels Command and Address hold time from CK tlH base 140 referenced to Vih dc Vil dc levels Command and Address setup time to CK tlS base AC150 65 125 referenced to Vih ac Vil ac levels Control and Address Input pulse width for each input Calibration Timing SS SSS SSS See Power up and RESET calibration time zai Normal operation Full calibration time ZQoer se Normal operation Short calibration time 1296 Reset Timing a eee MU aaa tXPRmin max 5nCK tRFC min 10ns Exit Reset from CKE HIGH to a valid command tXPR Nl tXSmin max 5nCK tRFC min 10ns Exit Self Refresh to commands not requir
32. ref 0 175 Note 2 Vref 0 175 Note 2 Vref 0 175 V 1 2 VIH CA AC150 AC Input Logic High Vref 0 15 Note 2 Vref 0 15 Note 2 Vref 0 15 Note 2 V 1 VIL CA AC150 AC Input Logic Low Note 2 Vref 0 15 Note 2 Vref 0 15 Note 2 Vref 0 15 V 1 Reference Voltage Vaecapo for ADD CMD 0 49xVDD 0 51xVDD 0 49xVDD 0 51xVDD 049xVDD 0 51 x VDD V 3 4 Inputs Note 1 For input only pins except RESET Vref VrefCA DC 2 See Overshoot and Undershoot Specifications in the device datasheet 3 The ac peak noise on VRef may not allow VRef to deviate from VRefDQ DC by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV Single Ended AC and DC Input Levels for VIH DQ DC DC Input Logic High 0 100 VDD Vref 0 100 VDD Vref 0 100 VDD VIL DQ DC DC Input Logic Low vss Vref 0 100 vss Vref 0 100 vss Vref 0 100 V 1 VIH DQ AC AC Input Logic High Vref 0 175 Note2 Vref 0 15 Note2 Vref 0 15 Note 2 V 1 2 5 VIL DQ AC AC Input Logic Low Note2 Vref 0 175 Note2 Vref 0 15 Note 2 Vref 0 15 V 1 2 5 Reference Voltage for DM 0 49x VDD 0 51 x VDD 0 49xVDD 0 51xVDD 049xVDD O 51xVDD V 3 4 Inputs Note 1 For input only pins except RESET Vref VrefDQ DC 2 See Overshoot and Undershoot Specifications in the device datasheet 3 The ac peak noise on VRef may not allow VRef to deviate from VRefDQ DC by more than 1 VDD for ref
33. rential output hightime jo DOS DASE differential outputiowtime pos o4 _ DOS DOSE differential WRITE Preamble were DOS DASE differential WRITE Postambe O DQS DQS low impedance time b i tLZ DQS 450 tCK avg Referenced from RL 1 DQS DQS high impedance time d tHZ DQS tCK avg Referenced from RL E _ cuu us DOS DOS amp difeemiainpuhghpusewidh 045 DOS DASE rising edge to CK risingedge Doass onr DOS DASE falling edge setup time to CK CK risigedge joss tae DOS DASE falling edge hold time CK CK rising edge SM _ QommadandAddess Timing o REV 1 0 18 06 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2S4G64CB88B5N M2S8G64CB8HB5N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 e IXI r Unbuffered DDR3 SO DIMM tRTPmin max 4nCK 7 5ns Internal READ Command to PRECHARGE Command delay tRTP tRTPmax Delay from start of internal write WTR tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery time Pts Register Set command cycle time tMODmin max 12nCK 15ns Mode Register Set command update delay to internal read or writ
34. ss4cycles Cumulative error across Scycles __ 8 ts S Cumulative eror across 6oyoles ts S Cumulative error across 7 oyoles ERRpe Cumulative error across 8 cycles tERR Pots s Cumulative error aoross 9 oyoles __ __ ts S Cumulative error across 10 cycles __ 205 25 S Cumulative error across 11 cycles aoo o o ets S Cumulative error across 12 as 25 tERR nper min 1 0 68In n tJIT per min Cumulative error across 13 14 49 50 cycles tERR nper tERR nper max 1 0 68In n tJIT per max pump m DOS DAS to DA skew per group peraccess feasa Hs S DQoutputholdtimefromoas oas DOlowimpedane meromCK CK so oo S DQhighimpedenetimetromCK CKF tDS Data setup time to DQS DQS referenced to Vih ac Vil ac levels C175 tDS base Data setup time to DQS DQS referenced to Vih ac Vil ac levels AC180 30 tDH base Data hold time from DQS DQS referenced to Vih dc Vil dc levels DC100 DQandDMipupusewidhforeachinut ow p sss mee cce c oen DQS DOS differential READ Preamble meE 09 Nee cK DOS DASE differential READ Postamble eest os DOS DASE differential outpu
35. stem planar to act as a pull up This signal is used to clock data into and out of the SPD EEPROM and Temp sensor Address pins used to select the Serial Presence Detect and Temp sensor base address The EVENT pin is reserved for use to flag critical module temperature This signal resets the DDR8 SDRAM Reference pin for ZQ calibration NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2S4G64CB88B5N M288G64CB8HB5N 4GB 512M 64 8GB 1024M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SO DIMM Functional Block Diagram 4GB 1 Rank 512Mx8 DDR3 SDRAMs REV 1 0 06 2012 eixir SO Daso 54 paso N gt DQS4 0 DMO DM CS Das Das DM CS Das Das N oo DQ32 N 100 pai N VO 1 DQ33 NA VO 1 Daz 2 N 02 JN vos DO DQ35 N 103 D4 DQ4 104 pase N 104 pas W 105 DQ37 N 105 N 106 pass N 106 DQ7 07 za DQ39 07 za DQS1 55 WM DQS1 0 Dass 0 DM DM5 DM CS Das 595 DM CS Das Das N 00 DQ40 100 pas N 1 0
36. t hightime OSH o4 DOS DASE differential outputiowtime pos tev DOS DOSE differential WRITE Preamble were 09 Ke DOS DOSE differential WRITE Postamble west os Kev Dre DQS DQS low impedance time i tLZ DQS 500 tCK avg Referenced from RL 1 DQS DQS high impedance time SUP tHZ DQS tCK avg Referenced from RL E Es cuu DOS DOS amp difeeniainpuhghpusewidh 045 DOS DASE rising edge to CK rising edge Doass os DOS DASE fang edge setup time to CK CK risngedoe jess o2 Ke DOS DOS falling edge hold time from CK CK rising edge 02 ice QommadandAddessTimng O o REV 1 0 15 06 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2S4G64CB88B5N M2S8G64CB8HB5N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 e IXI r Unbuffered DDR3 SO DIMM tRTPmin max 4nCK 7 5ns Internal READ Command to PRECHARGE Command delay tRTP tRTPmax Delay from start of internal write WTR tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery time Pts Register Set command cycle time tMODmin max 12nCK 15ns Mode Register Set command update delay to internal read
37. tMODmin max 12nCK 15ns tMODmax ACTtoACTor REF command period to CASH command delay eeo Auto precharge write recovery precharge time nck _ Multi Purpose Register Recovery Time merr ck ACTIVE to PRECHARGE commandperiod feas _ Standard Speed Bins ACTIVE to ACTIVE command period for 1KB size RRD max nK7Sn tRRDmin max 4nCK 10ns ACTIVE to ACTIVE command period for 2KB page size tRRDmax Four activate window for 1KB page size Ll x p o du T 1 Four activate window for 2KB page size IFAW posts Command and Address setup time to CK tlS base 125 referenced to Vih ac Vil ac levels Command and Address hold time from CK tlH base 200 referenced to Vih dc Vil dc levels Command and Address setup time to CK tlS base AC150 1254150 referenced to Vih ac Vil ac levels Control and Address Input pulse width for each input Calibration Timing NEN NEEESISENEM AREE X uS Power up and RESET calibration time Normal operation Full calibration time Ope se ck S Normal operation Short calibration time 1296 Reset Timing pro a ed ee tXPRmin max 5nCK tRFC min 10ns Exit Reset from CKE HIGH to a valid command tXPR ale o tXSmin 5 tRFC min 10ns Exit Self Refresh to commands
38. y other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 VDD and VDDQ must be within 300 mV of each other at all times and VREF must be not greater Operating temperature Conditions Normal Operating Temperature Range 0 to 85 1 Extended Temperature Range 85 to 95 C 7 3 Note 1 Operating Temperature TOPER is the case surface temperature on the center top side of the DRAM For measurement conditions please refer to the document JESD51 2 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported During operation the DRAM case temperature must be maintained between 0 to 85 under all operating conditions 3 Some applications require operation of the DRAM in the Extended Temperature Range between 85 and 95 case temperature Full specifications are supported in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the Refresh interval tREFI to 3 9 us It is also possible to specify a component with 1X refresh tREFI to 7 8us in the Extended Temperature Range Please refer to supplier

Elixir 8GB DDR3 SO-DIMM

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