Dataram 2GB DDR3-1600
Contents
1. PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High VIH DIFF 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low Vu pr DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage relative to VDD 2 Vix da eee y Capacitance Ta 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CRO Con 1 5 25 pF Input Capacitance Address BA 2 0 A 15 0 RAS CAS WE Ci 1 5 2 5 pF Input Capacitance Control SO CKEO ODTO Ci 1 5 2 5 pF DQ 63 0 CB 7 0 DQS 8 0 DQS 8 0 Input Output Capacitance DM 8 0 TDQS 17 9 Cio 1 5 2 3 pF DC Characteristics Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current lit 18 18 yA 1 2 Any input 0 V lt VIN lt VDD Output Leakage Current lot 10 10 yA 2 3 OV lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled Document 06100 Revision A 15 Mar 12 Dataram Corporation 2012 Page 5 DIPDATARAM DTM64369C tl 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Test Condition Max unit Value Operating One Bank Active Get Operating current One bank ACTIVATE to PRECHARGE 405 mA Precharge Current Operati2. ODTI1 0 On Die Termination Inputs 15 DQS1 45 CB2 75 Voo 105 DQ50 135 TDQS10 165 CB7 4950DTO 225DQ55 SAJ2 0 SPD Address 16 DQS1 46 CB3 76 S1 106 DQ51 136 Vss 166 Vss 196 A13 226 Vss SCL SPD Clock Input 17 Vss 47 Vss 770DT1 107Vss_ 137DQ14_ 1167 NC TEST 197 Voo 227 DQ60 SDA SPD Data Input Output 18 DQ10 48 ven 78 Voo 108 DQ56 138DQ15 1168 RESET 198 S3 NC 228DQ61 EVENT Temperature Sensing 19DQ11 49 Vrr 79 82 NC 109 DQ57 139 Vss 169 CHE 199 Vss 229 Vss IRESET Reset for register and DRAMs 20Vss 50 CKEO 80 Vss 110Vss 140DQ20 170 Voo 200DQ36 230 DM7 PAR IN Parity bit for Addr Ctrl 21 DQ16 51 Vos 81 DQ32 111 DQS7I141DQ21 1171 A15 201 DQ37 231 TDQS16 ERR OUT Error bit for Parity Error 22 DQ17 52 BA2 82 DQ33 112 DQS7 142 Vss 172A14 202 Vss 232 Vss A12 BC Combination input Addr12 Burst Chop 23Vss 53 ERR_Our B ss 113Vss 143DM2 173Voo 203 DM4 233DQ62 A10 AP Combination input Addr10 Auto precharge 24 IDQS2I54 Voo 84 DQS4 114 DQ58 144 TDQS11 174 A12 BC 204 TDQS13 234DQ63 Vss Ground 25 DQS2 55 A11 85 DQS4 115 DQ59 145 Vss 175 A9 205 Vss 235 Vss Von Power 26Vss_ 56 A7 86 Vss 116Vss 146DQ22 1176Vop 206 DQ38 236 Vbosro VppsPo SPD EEPROM Power 27 DQ18 57 Voo 87 DQ34 117SA0 147DQ23 177 A8 207 DQ39 237 SA1 VRErDa Reference Voltage for DQ s 28 DQ19 58 A5 88 DQ35 118SCL 148 Vss 178 A6 1208 Vss 238 SDA VREFCA Reference Voltage for CA 29Vss 59 Ad 89 Vss 119SA2 149DQ28 1179Vop 209 DQ44 239 Vss Vor Te
3. 21 Bit 3 Bit 0 tRAS Most Significant Nibble 1 0x11 Bit 7 Bit 4 tRC Most Significant Nibble 1 22 a Active to Precharge Delay Time tRASmin Least Significant 35 0ns 0x18 23 Minimum Active to Active Refresh Delay Time tRCmin Least 48 125ns_ 0x81 Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Least Significant 160 0ns 24 Byte 0x00 25 EE Refresh Recovery Delay Time tRFCmin Most Significant 160 Ons 0x05 26 Minimum Internal Write to Read Command Delay Time tWTRmin 7 5ns 0x3C 27 Minimum Internal Read to Precharge Command Delay Time tRTPmin 7 5ns 0x3C Upper Nibble for tFAW 28 Bit 3 Bit 0 FAW Most Significant Nibble 0 0x00 Bit 7 Bit 4 Reserved 0 EEC Zee Document 06100 Revision A 15 Mar 12 Dataram Corporation 2012 Page 9 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Oper Wue aed Pesta Minimum Four Activate Window Delay Time tFAWmin Least Significant Byte 30 0ns OxFO SDRAM Optional Features Bit 0 RZQ 6 x 30 Bit 1 RZQ 7 x 0x83 Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support SDRAM Drivers Supported Extended Temperature Range X Extended Temperature Refresh Rate Auto Self Refresh ASR 31 On die Thermal Sensor ODTS Readout 0x01 Reserved Reserved Reserved Partial Array Self Refresh PASR Module Thermal Sensor 32 Bit 6 Bit 0 Thermal Sensor Accuracy 0 0x80 Bit 7
4. Delay twTR Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min The maximum postamble is bound by tHZDQS max Document 06100 Revision A 15 Mar 12 Dataram Corporation 2012 Page 7 tel 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Byte Function Value Hex Number of Bytes Used Number of Bytes in SPD Device CRC Coverage 0 Bit 3 Bit 0 SPD Bytes Used 176 0x92 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 1 SPD Revision Rev 1 1 0x11 DDR3 2 Key Byte DRAM Device Type SDRAM 1998 Key Byte Module Type 3 Bit 3 Bit 0 Module Type RDIMM 0x01 Bit 7 Bit 4 Reserved 0 SDRAM Density and Banks 4 Bit 3 Bit O Total SDRAM capacity in megabits 2Gb 0x03 Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved 0 SDRAM Addressing 5 Bit 2 Bit 0 Column Address Bits 10 0x19 Bit 5 Bit 3 Row Address Bits 15 Bit 7 6 Reserved 0 Module Nominal Voltage VDD Bit 0 NOT 1 5 V operable Bit 1 1 35 V operable Bit 2 1 2X V operable 6 Bit 3 Reserved 0x00 Bit 4 Reserved Bit 5 Reserved Bit 6 Reserved Bit 7 Reserved Module Organization 7 Bit 2 Bit 0 SDRAM Device Width 8 Bits 0x01 Bit 5 Bit 3 Number of Ranks 1 Rank Bit 7 6 Reserved 0 Module Memory Bus Width 8 Bit 2 Bit O
5. Input Hold Time after DQS Strobe toH 45 ps DQ Input Pulse Width toipw 360 ps DQS Output Access Time from Clock tpascK 225 225 ps Write DQS High Level Width tbasH 0 45 0 55 tck avg Write DQS Low Level Width toast 0 45 0 55 tck avg DQS Out Edge to Data Out Edge Skew toasa 100 ps Data Input Setup Time Before DQS Strobe tos 10 ps DQS Falling Edge from Clock Hold Time tosH 0 18 tcK avg DQS Falling Edge to Clock Setup Time toss 0 18 toR avg Cloch Half Period tup minimum of ten or teL ns Address and Command Hold Time after Clock Dn 120 ps Address and Command Setup Time before Cloch tis 45 ps Load Mode Command Cycle Time turD 4 tck DQ to DQS Hold Lou 0 38 tor avg Active to Precharge Time tras 35 O tREFI ns Active to Active Auto Refresh Time tre 48 75 48 125 ns RAS to CAS Delay trep 13 75 13 125 ns Average Periodic Refresh Interval 0 C lt Tcase lt 85 C REFI 7 8 us Average Periodic Refresh Interval 0 C lt Tcase lt 95 C Iren 3 9 us Auto Refresh Row Cycle Time trFc 160 ns Row Precharge Time trp 13 75 13 125 ns Read DQS Preamble Time tRPRE 0 9 Note 1 tck avg Read DQS Postamble Time terest 0 3 Note 2 tck avg Row Active to Row Active Delay tRRD Max 4nCK 6ns ns Internal Read to Precharge Command Delay tRTP Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twPRE 0 9 tck avg Write DQS Postamble Time twest 0 3 tck avg Write Recovery Time twr 15 ns Internal Write to Read Command
6. Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Vop 1 425 1 5 1 575 V UO Reference Voltage VREFDQ 0 49 Mon 0 50 Mon 0 51 Von V 1 UO Reference Voltage VREFCA 0 49 Vpp 0 50 Vop 0 51 Voo V 1 Notes For Reference Vpp 2 15 mV The value of VREF is expected to equal one half VDD and to track variations in the VDD DC level Peak to peak noise on VREF may not exceed 1 of its DC value For Reference VREF VDD 2 15 mV DC Input Logic Levels Single Ended TA 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vue VREF 0 1 Vpop V Logical Low Logic 0 Vuupe Vss Veer 0 1 V AC Input Logic Levels Single Ended T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 VIH AC VREF 0 175 V Logical Low Logic 0 ViL ac VRer 0 175 V Document 06100 Revision A 15 Mar 12 Dataram Corporation 2012 Page 4 IU PDATARAM DIN ENT E E TE DTM64369C 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to Vss 0 V
7. Thermal Sensor With TS SDRAM Device Type Bit 6 Bit 0 Non Standard Device Description 0 33 Bit 7 SDRAM Device Type Std Mono 0x00 34 59 Reserved UNUSED 0x00 Module Nominal Height 60 Bit 4 Bit 0 Module Nominal Height max inmm 29 lt h lt 30 OXOF Bit 7 Bits Reserved 0 Module Maximum Thickness 61 Bit 3 Bit 0 Front in mm baseline thickness 1mm 414 lt th lt 2 0x11 Bit 7 Bit 4 Back in mm baseline thickness 1 mm 1 lt th lt 2 Reference Raw Card Used 62 Bit 4 Bit 0 Reference Raw Card RICA 0x00 Bit 6 Bit 5 Reference Raw Card Revision Rev 0 Bit 7 Reserved 0 Registered DIMM Module Attributes 63 Bit 1 Bit 0 of Registers used on RDIMM 1 Register _ 0x05 Bit 3 Bit 2 of Rows of DRAMs on RDIMM 1 Row Bit 7 Bit 4 Reserved 0 RDIMM Thermal Heat Spreader Solution 64 Bit 6 Bit 0 Heat Spreader Thermal Characteristics 0 0x00 Bit 7 Heat Spreader Solution No HS 65 Register Manufacturer ID Code Least Significant Byte Optional 0x80 66 Register Manufacturer ID Code Most Significant Byte Optional OxB3 b eNE l O Document 06100 Revision A 15 Mar 12 Dataram Corporation 2012 Page 10 Opener Wue aed Pesta 2GB 240 Pin 1Rx8 Registered ECC DD
8. DTM64369C 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Identification DTM64369C 256Mx72 2GB 1Rx8 PC3 12800R 11 11 A0 Performance range Clock Module Speed CL trep Zeg 800 MHz PC3 12800 11 11 11 667 MHz PC3 10600 10 10 10 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Features Description 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high DTM64369C is a registered 256Mx72 memory module g which conforms to JEDEC s DDR3 PC3 12800 standard Operating Voltage 1 5v 9959 The assembly is a Single Rank The Rank is comprised of I O Type SSTL 15 nine 256Mx8 DDR3 1600 Hynix SDRAMs On board DC temperature sensor with integrated serial presence One 2K bit EEPROM is used for Serial Presence Detect detect SPD EEPROM and a combination register PLL with Address and Data Transfer Rate 12 8 Gigabytes sec Command Parity is also used Both output driver strength and input termination Data Bursts 8 and burst chop 4 mode impedance are programmable to maintain signal integrity ZQ Calibration for Output Driver and On Die Termination ODT on the I O signals in a Fly by topology Programmable ODT Dynamic ODT during Writes A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating Programmable CAS Latency 6 7 8 9 10 and 11 temperature of 95C Bi Directional Differ
9. Least Significant Byte 0x80 118 Module Manufacturer ID Code Most Significant Byte OxCE 119 Module Manufacturing Location 0x01 120 Module Manufacturing Date 0x11 121 Module Manufacturing Date 0x20 122 Module Serial Number 0x44 123 Module Serial Number 0x22 124 Module Serial Number 0x80 125 Module Serial Number OXBE 126 Cyclical Redundancy Code CRC CRC 0x67 127 Cyclical Redundancy Code CRC CRC 0x38 128 131 Module Part Number Space 0x20 132 Module Part Number D 0x44 133 Module Part Number A 0x41 Document 06100 Revision A 15 Mar 12 Dataram Corporation 2012 Page 11 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Joerg Value aed Fraftemanuz 134 Module Part Number T 0x54 135 Module Part Number A 0x41 136 Module Part Number R 0x52 137 Module Part Number A 0x41 138 Module Part Number M 0x4D 139 Module Part Number Space 0x20 140 Module Part Number 6 0x36 141 Module Part Number 4 0x34 142 Module Part Number 3 0x33 143 Module Part Number 6 0x36 144 Module Part Number 9 0x39 145 Module Part Number Space 0x20 Kee Module Revision Code UNUSED 0x00 148 DRAM Manufacturer ID Code Least Significant Byte 0x80 149 DRAM Manufacturer ID Code Most Significant Byte OxCE 150 175 Manufacturers Specific Data UNUSED 0x00 176 255 Open for customer use UNUSED 0x00 A ea EI EE a a a p s E Document 06100 Revision A 15 Mar 12 Dataram Corporation 2012 Page 12 eu 2GB 240 Pin 1Rx8
10. NECTS All 47 OHMS BA 2 0 R A 15 0 R IRASR ICASR INER VTT All 47 OHMS CKEOR ODTOR RSO VIT TO SDRAMS Al 22 OHMS SO RSO IEN BA 2 0 BA 2 0 R A 15 0 A 14 0 R IRAS IRASR ICAS ICASR WE 4 IWER CKEO D CKEOR lt ODTO 9 ODTOR ba PAR IN ERR_OUT CKO L R CLK O 120 OHMS ICKO L R CLK O RESET SDRAMS All 240 OHMS Gal Vss DQSR4 DQSR4 O DMR4 TDQSR13 o O a VO 7 0 RANK 0 DQR 47 40 DQSR6 O DQSR6 DMR6 TDQSR15O q TDQS ICS DQS DQS TDQSR16 DQR 63 56 VDD Vop 100 A Al 36OHMS All 36 OHMS 100 nF LCLKO RCLKO 120 OHMS CR1 O VVV O CK1 DECOUPLING VDDSPD 4 Serial PD VDD a All Devices VREF_DQ All SDRAMs Vss All Devices VREF_CA All SDRAMs VTT F All SDRAMs EVENT TEMPERATURE MONITOR SOL Em SERIAL PD PS DA I I SA0 SA1 SA2 Document 06100 Revision A 15 Mar 12 Dataram Corporation 2012 Page 3 DIN ENT E E TE Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TSTORAGE 55 100 C Ambient Temperature Operating TA 0 70 C DRAM Case Temperature Operating TCASE 0 95 C Voltage on Vpp relative to Vss Vop 0 4 1 975 V Voltage on Any
11. Primary bus width in bits 64 Bits 0x0B Bit 4 Bit 3 Bus width extension in bits 8 Bits Bit 7 Bit 5 Reserved 0 Fine Timebase F TB Dividend Divisor 9 Bit 3 Bit 0 Fine Timebase FTB Divisor 1 0x11 Bit 7 Bit 4 Fine Timebase FTB Dividend 1 1 MTB de Medium Timebase MTB Dividend 0 125ns Hl Document 06100 Revision A 15 Mar 12 Dataram Corporation 2012 Page 8 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Oper Wue aed Pesta 8 MTB n Medium Timebase MTB Divisor 0 125ns 0208 12 SDRAM Minimum Cycle Time tCKmin 1 25ns Ox0A 13 Reserved UNUSED 0x00 CAS Latencies Supported Least Significant Byte Bit 0 CL 4 Bit 1 CL 5 Bit 2 CL 6 X 14 Bit 3 CL 7 X OxFC Bit 4 CL 8 X Bit 5 CL 9 X Bit 6 CL 10 X Bit 7 CL 11 X CAS Latencies Supported Most Significant Byte Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 15 Bit 3 CL 15 0x00 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved 16 Minimum CAS Latency Time tAAmin 13 125ns 0x69 17 Minimum Write Recovery Time tWRmin 15 0ns 0x78 18 Minimum RAS to CAS Delay Time tRCDmin 13 125ns 0x69 19 Minimum Row Active to Row Active Delay Time tRRDmin 6 Ons 0x30 20 Minimum Row Precharge Delay Time tRPmin 13 125ns 0x69 Upper Nibbles for tRAS and tRC
12. R3 DIMM 67 Register Revision Number Optional 0x63 Register Type 68 Bit 2 0 Support Device SSTE32882 0x00 Bit 7 3 Reserved 0 69 SSTE32882 RC1 MS Nibble RCO LS Nibble UNUSED 0x00 SSTE32882 RC3 MS Nibble RC2 LS Nibble Drive Strength Command Address 70 Bit 1 Bit 0 RC2 DA3 4 Value RESERVED 0x00 Bit 3 Bit 2 RC2 DBAO0 1 Value RESERVED Bit 5 Bit 4 RC3 DA4 3 value Command Address A Outputs Light Bit 7 Bit 6 RC3 DBAO0 1 value Command Address B Outputs Light SSTE32882 RC5 MS Nibble RC4 LS Nibble Drive Strength Control and Clock 71 Bit 1 Bit 0 RC4 DA3 4 Control Signals A Outputs Light 0x00 Bit 3 Bit 2 RC4 DBA0 1 Control Signals B Outputs Light Bit 5 Bit A RC5 DA4 3 value Y1 Y1 and Y3 Y3 Clock Outputs Light Bit 7 Bit 6 RC5 DBAO 1 value YO YO and Y2 Y2 Clock Outputs Light 72 SSTE32882 RC7 MS Nibble RC6 LS Nibble UNUSED 0x00 73 SSTE32882 RC9 MS Nibble RC8 LS Nibble UNUSED 0x00 74 SSTE32882 RC11 MS Nibble RC10 LS Nibble UNUSED 0x00 75 SSTE32882 RC13 MS Nibble RC12 LS Nibble UNUSED 0x00 76 SSTE32882 RC15 MS Nibble RC14 LS Nibble UNUSED 0x00 77 112 Module Specific Section UNUSED 0x00 113 Module Specific Section UNUSED 0x00 114 116 Module Specific Section UNUSED 0x00 117 Module Manufacturer ID Code
13. Registered ECC DDR3 DIMM DD DATARAM Ween DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06100 Revision A 15 Mar 12 Dataram Corporation 2012 Page 13
14. ential Data Strobe signals SDRAM Addressing Row Col Bank 15 10 3 Fully ROHS Compliant Pin Configuration Pin Description Front Side Back Side Name Function 1 VRerpal31 DQ25 61 A2 91 DQ41 121 Vss 151 Vss 181 A1 211 Vss CB 7 0 Data Check Bits 2 Vss 32 Vss 62 Vp 92 Vss 122DQ4 152DM3 182 Voo 212 DM5 DQ 63 0 Data Bits 3 DQO 33 DQS3 63 CK1 93 DQS5 123DQ5 153 TDQS12 183 Vop 213 TDQS14 DQSI8 0 DQS 8 0 Differential Data Strobes 4 DQ1 34 DQS3 64 CK1 oa DQS5 124 Vss 154 Vss 184 CKO 214 Vss DM 8 0 Data Mash 5 Vss 35 Vss 65 Voo 95 Vss 125DMO 1155DQ30 185 CRO 215DQ46 TDQS 17 9 Termination strobes 6 DQS0 36 DQ26 66 Voo 96 DQ42 126 TDQS9 156 DQ31 186 Vo 216DQ47 CHI1 0 CK 1 0 f Differential Clock Inputs 7 Dosen 37 DQ27 67 Vrerca 197 DQ43 127 Vss 157 Vss 187 EVENT 1217 Vss CKE 1 0 Clock Enables 8 Vss 38 Vss 68 PaR Ju 198 Vss 128DQ6 1158 CB4 188 AO 218DQ52 CAS Column Address Strobe 9 DQ2 39CB0 69 VDD 99 DQ48 j129DQ7 159 CB5 189 Vo 219DQ53 RAS Rovv Address Strobe 10DQ3 40 CB1 Go A10 AP Woo DQ49 130 Vss 160 Vss 190 BA1 220 Vss S 3 0 Chip Selects 11Vss Wi Vss 71 BAO 101 Ve 131DQ12 11461 DM8 191 Voo 221 DM6 INE Write Enable 12DQ8 42 DQS8 72 Voo 102 DQS6f132DQ13 162 TDQS17 192 RAS 222 TDQS15 A 15 0 Address Inputs 13DQ9 43 DQS8 73 WE 103 DQS6 133 Vss 163 Vss 193 S0 223 Vss BA 2 0 Bank Addresses 14Vss 44 Vss 74 CAS 104Vss H34DM1 164 CB6 194 Vop 224DQ54
15. ng One Operating current One bank ACTIVATE to READ to Bank Active Read Jon PRECHARGE 495 mA Precharge Current Precharge Povver lop2P Precharge power down current Slow exit 108 T Down Current Precharge Power L b Precharge power down current Fast exit 135 mA Down Current Precharge Quiet Precharge quiet standby current Standby Current oc EH mA Precharge Standby lop2N Precharge standby current 225 mA Current Active Power Down L b Active power down current 135 mA Current Active Standby lop3N Active standby current 270 M Current Operating Burst Burst write operating current Write Current Geht 999 Ae Operating Burst Burst read operating current Read Current loo4R 945 i mA Burst Refresh ae Refresh current 1080 m Current Self Refresh Luft Self refresh temperature current MAX Tc 85 C 108 mA Current Operating Bank g interleave Read ka All bank interleaved read current 1665 mA Current Document 06100 Revision A 15 Mar 12 Dataram Corporation 2012 Page 6 tel 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit Internal read command to first data taa 13 75 13 125 20 ns CAS to CAS Command Delay tecp 4 tck Clock High Level Width tcH avg 0 47 0 53 tck Clock Cycle Time tck 1 25 1 5 ns Clock Low Level Width tcL avg 0 47 0 53 tck Data
16. rmination Voltage 30 DQ24 60 Vos 90 DQ40 120 ven 150DQ29 180 A3 210DQ45 240 Vz NC No Connection Not used Document 06100 Revision A 15 Mar 12 Dataram Corporation 2012 Page 1 Lo Laia DTM64369C EN 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Front view le 133 35 gt 5 250 9 50 0 374 30 00 1 181 UC 17 30 0 681 0 197 0 008 5 175 a 47 00 gt La 71 00 gt 0 204 1 850 2 795 123 00 4 843 Back view Side view 3 94 Max 0 155 Max 4 00 Min 0 157 Min 1 27 2 10 gt 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches eS PEE EE TE EECHER Document 06100 Revision A 15 Mar 12 Dataram Corporation 2012 Page 2 Omar Value aed Pesta s DRDATARAM DTM64369C 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM RSO O DQSR0 O DQSR0 DMROO TDQSR9O VO 7 0 RANK 0 DQRI15 8 O DQSR2 O DQSR2 DMR2 ITDQSR11 O 50 SO DDH SO AGU GG al a an mi EE SE DQR 23 16 O 1 017 0 DQSR3 DQSR3 O DMR3 IMDOSR120 I DNA EUN NN SO AGOGG D a Ei E E dre Gi All 15 OHMS DA 63 0 O VVV O DQRI63 0J CB 7 0 O VVv O CBRI7 0 DQS 8 0 O VWA O DOSRI8 0 IDQSI8 0 O VV O DASRIB 0 DM 8 0 O VVV O DMRI8 0 TDQS 17 9 O VW O TDQSR 17 9 GLOBAL SDRAM CON
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