Silicon Power 1024MB DDR1 DIMM
Contents
1. standard 2 5 V SSTL_2 compatible I O e 66pin TSOP Il Leaded amp Pb Free ROHS compliant package This document is a general product description and is subject to change without notice SILICON POWER SP001GBLDU333002 Computer amp Communications Inc 184pin DDR1 333 Unbuffered DIMM 3 Module Specification Item Specification Capacity 1024MByte Physical Bank s 2 Module Organization 128M x 64bit Module Type Unbuffered NonECC Speed Grade PC 2700 CL 2 5 tRCD 3 tRP 3 DDR333 Voltage Interface SSTL 2 Power Supply Voltage 2 5V 0 1V Burst Lengths 2 4 8 DRAM Organization 64M x 8bit DDR SDRAM PCB Layer 6Layers Contact Tab 184pin GOLD Flash Plating Serial PD Support 4 Simplified Mechanical Drawing with Keying Positions 0 125 3 18 FRONT VIEW 5 256 133 50 52d 133 20 0 079 2 00 R dx 1 165 29 59 1 155 25 34 0 008 2 50 D 0 700 17 78 a TYF 0 097 2 30 TYP EA A 0 035 0 90 R 0 054 1 37 ar 7 0 046 1 17 0 250 6 35 TYP PIN 92 uM 0 091 2 30 0 050 1 27 0 040 1 02 TYF TYF TYF 4 750 120 65 TYF BACK VIEW a T LAG a Ls mn amn amn f f PIN 184 PIN G3 1 95 49 63 e SEAT TYP TYP 0 150 3 80 0 394 10 00 TYP TYP Notes 1 All dimensions are in millimeters inches MAX MIN or typical TYP where noted This document is a g2. SILICON POWER SP001GBLDU333002 O Computer amp Communications Ine 184pin DDR1 333 Unbuffered DIMM 1 Description The SP001GBLDU333002 is a 64M x 8bits Double Data Rate SDRAM high density for DDR1 333 The SP001GBLDU333002 consists of 16pcs CMOS 64x8 bits Double Data Rate SDRAMs in 66 pin TSOP package and a 2048 bits serial EEPROM on a 184 pin printed circuit board The SP001GBLDU333002 is a Dual In Line Memory Module and is intended for mounting into 184 pin connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications 2 Features e Double data rate architecture two data transfers per clock cycle e Bidirectional data strobe DQS is transmitted received with data to be used in capturing data at the receiver e DQS is edge aligned with data for READs center aligned with data for WRITEs e Differential clock inputs CK and CK e DLL aligns DQ and DQS transitions with CK transitions e Commands entered on each positive CK edge data and data mask referenced to both edges of DQS e Four internal banks for concurrent operation e Data mask DM for write data e Burst lengths 2 4 or 8 e AUTOPRECHARGE option for each burst access e Auto Refresh and Self Refresh Modes e JEDEC
3. eneral product description and is subject to change without notice
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