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Intel Xeon E5-1428L

1. Symbol Parameter Min Nom Max Units Notes Vn Input Low Voltage Signals SVIDDATA SVIDALERT N 0 4 Vccio in V 1 Vin Input High Voltage Signals SVIDDATA SVIDALERT_N 0 7 Vccro iN V 1 VoL Output Low Voltage Signals SVIDCLK SVIDDATA 0 2 V ccio iN V 1 5 Vuysteresis Hysteresis 0 05 Vccro iN V 1 Ron Buffer On Resistance Signals SVIDCLK SVIDDATA 4 14 Q 2 Ti Input Leakage Current 50 200 HA 3 Input Edge Rate 0 05 V ns 4 Signal SVIDALERT_N Output Edge Rate 0 20 1 5 V ns 4 5 Note 1 Vccro rw refers to instantaneous Vccro rw Measured at 0 31 Vccro rv Vin between OV and Vccro iN applies to SVIDDATA and SVIDALERT_N only These are measured between Vi and Vy Value obtained through test bench with 502 pull up to Vccro rw UV ec DA Ie Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical September 2014 Datasheet Order No 330783 001 41 intel 2 9 3 7 Processor Asynchronous Sideband DC Specifications Symbol Parameter Min Max Units Notes CMOS1 05v Signals ViL CMOS1 05V Input Low Voltage 0 4 V CCIO_IN V 1 2 ViH cMosi osv Input High Voltage 0 6 V ccio IN V 1 2 Iu cwosi sv Input Leakage Current 50 200 HA 1 2 Open Drain CMOS ODCMOS Signals ViL_opcmos Input Low Voltage 0 4 Vccio_IN V 1 2 Signals CATERR N MSMI N PM FAST WAKE N Vit opcvos Input Low Volta
2. Data Signals continued Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet September 2014 36 Order No 330783 001 Electrical Specifications Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families intel Symbol Parameter Min Nom Max Units Notes VoL Output Low Voltage Varies 10 Vou Output High Voltage Vccp Reference Clock Signal R on DDR4 Clock Buffer 27 33 ohm 6 On Resistance Command Signals R on DDR4 Command Buffer 16 20 ohm 6 On Resistance R on DDR4 Reset Buffer 78 ohm 6 On Resistance VoL cMOS1 2V Output Low 0 2 Vccp V 1 2 Voltage Signals DDR RESET C 01 23 _N V oH cMos1 2v Output High 0 9 Vccp V 1 2 Voltage Signals DDR RESET C 01 23 _N Control Signals R on DDR4 Control Buffer 27 33 ohm 6 On Resistance DDR4 Miscellaneous Signals ALERT_N On Die Termination 81 90 99 ohm for Parity Error Signals Vit Input Low Voltage 304 mV 2 3 DRAM PWR OK C 01 23 Vinh Input High Voltage 800 mV 2 4 5 DRAM PWR OK C 01 23 Note 1 Unless otherwise noted all specifications in this table apply to all processor frequencies an oe ee ODTs and series resistors on the DIMMs The voltage rail Vccp which will be set to 1 2V nominal depending on the voltage of all DIMMs connected to the processor Vi_ is the maximum voltage level at a receiving agent that will be interpreted a
3. PinName DDR2 MA DDR2 MAJS DDR2 MA 6 DDR2 MAJZ DDR2 MAB DDR2 MAS DDR2 MA DDR2 MAB DDR2 MA DDR2 MA DDR2 MABI DDR2 MAI DDR2_ODTIO DDR2 ODTHI DDR2_ODT 2 DDR2 ODTIS DDR2_ODTI4 DDR2 ODTIS DDR2 PAR DDR23 VREF DDR3 ACT N DDRS ALERTN DDR3 BAI DDR3 BAD DDR3 BG DDR3 BG DDR3 CID 2 DDR3 CKE DDR3 CKE DDR3 CKE 2 DDR3 CKE 3 DDR3CKE4 DDR3 CKE DDR3 CLK DNIO DDR3 CLK DN DDR3 CLK DN DDR3 CLK DN DDRS CLK DP 0 _ DDRS CLK DP DDRS CLK DP 2 DDR3 CLK DP S DDR3CS NO DDR3 CSND September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 70 Appendix A Pin List Pin Name Pin Number Buffer Type A15 SSTL F14 SSTL an SSTL A SSTL B14 SSTL B12 SSTL D38 SSTL B38 SSTL Gai SSTL SSTL Fad SSTL E35 SSTL Dao SSTL E33 SSTL Kad SSTL Tm SSTL Kao SSTL v30 SSTL L37 SSTL J35 SSTL L35 SSTL L31 SSTL N3 SSTL F28 SSTL E27 SSTL F24 SSTL E23 SSTL G29 SSTL E29 SSTL Vos SSTL C25 SSTL B24 SSTL m SSTL Ha SSTL Ji SSTL L SSTL Pa SSTL N3 SSTL K2 SSTL R3 SSTL Cao SSTL E9 SSTL Fe SSTL ES SSTL F SSTL EIIZ X l September 2014 Intel R Xeon R Processor E5 1600 and E5 26
4. Clock Enable Differential clocks to the DIMM All command and control signals are valid on the rising edge of clock DDR 0 1 2 3 _CS_N 9 0 Chip Select Each signal selects one rank as the target of the command and address CS_N 7 6 are MUXed with CID 4 3 respectively CS_N 3 2 are MUXed with CID 1 0 respectively DDR 0 1 2 3 _DQ 63 0 Data Bus DDR4 Data bits DDR 0 1 2 3 _DQS_DP 17 0 DDR 0 1 2 3 _DQS_DN 17 0 DDR 0 1 2 3 _ECC 7 0 Data strobes Differential pair Data ECC Strobe Differential strobes latch data ECC for each DRAM Different numbers of strobes are used depending on whether the connected DRAMs are x4 x8 Driven with edges in center of data receive edges are aligned with data edges Check bits An error correction code is driven along with data on these lines for DIMMs that support that capability DDR 0 1 2 3 _MA 17 0 Memory Address Selects the Row address for Reads and writes and the column address for activates Also used to set values for DRAM configuration registers MA 16 MA 15 and MA 14 are MUXed with RAS_N CAS_N and WE_N respectively DDR 0 1 2 3 _PAR Even parity across Address and Command continued Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Order No 330783 001 Datasheet 49 intel Table 20 4 2 Note Table 21 Table 22 Intel Xeon Processor E5 1600 and E5
5. 2 45 2 2 2 2 105W 136 0 1 0 001 1 4 1 4 64 0 02 0 001 0 8 0 8 208 210 2 4 A Gore 2 45 2 45 2 2 2 2 Advanc 135W 175 0 1 0 001 1 4 1 4 82 0 02 0 001 0 8 0 8 267 270 2 4 ed 12 2 45 2 45 2 2 2 2 Server Core 120W 156 0 1 0 001 1 4 1 4 73 0 02 0 001 0 8 0 8 238 240 2 4 12 2 45 2 45 2 2 2 2 Core 105W 136 0 1 0 001 1 4 1 4 64 0 02 0 001 0 8 0 8 208 210 2 4 10 2 45 2 45 2 2 2 2 Core Standa 90W 121 0 1 0 001 1 4 14 58 0 02 0 001 0 8 0 8 178 180 2 4 rd 8 Core 2 45 2 45 2 2 2 2 Server 85W 105 0 1 0 001 1 4 14 50 0 02 0 001 0 8 0 8 168 170 2 4 8 Core 2 45 2 45 2 2 2 2 continued Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 Datasheet 32 of 2 Electrical September 2014 Order No 330783 001 Electrical Specifications Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families intel 1 Unless otherwise noted al specifications in this table apply to all processors These specifications are based on final characterization 2 FMBis the flexible motherboard guidelines See Flexible Motherboard Guidelines FMB on page 29 for further details 3 ICCIN TDC Thermal Design Current is the sustained DC equivalent current that the processor is capable of drawing indefinitely and should b
6. DDR4 Command Signals Single ended SSTL Output DDR 0 1 2 3 _ACT_N DDR 0 1 2 3 _BA 1 0 DDR 0 1 2 3 _BG 1 0 DDR 0 1 2 3 _MA 17 DDR 0 1 2 3 _MA 16 _RAS_N DDR 0 1 2 3 _MA 15 _CAS_N DDR 0 1 2 3 _MA 14 _WE_N DDR 0 1 2 3 _MA 13 0 DDR 0 1 2 3 _PAR DDR4 Control Signals Single ended SSTL Output DDR 0 1 2 3 _CS_N 9 8 DDR 0 1 2 3 CS_N 7 CID 4 DDR 0 1 2 3 CS_N 6 CID 3 DDR 0 1 2 3 _CS_N 5 4 DDR 0 1 2 3 CS_N 3 CID 1 DDR 0 1 2 3 CS_N 2 CID 0 DDR 0 1 2 3 _CS_N 1 0 DDR 0 1 2 3 _CID 2 DDR 0 1 2 3 _ODT 5 0 DDR 0 1 2 3 _CKE 5 0 continued September 2014 Order No 330783 001 Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 23 intel Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Electrical Specifications Differential Single Ended Buffer Type Signal DDR4 Data Signals Differential SSTL Input Output DDR 0 1 2 3 _DQS_D N P 17 0 Single ended SSTL Input Output DDR 0 1 2 3 _DQ 63 0 DDR 0 1 2 3 _ECC 7 0 DDR4 Miscellaneous Signals Single ended SSTL Input DDR 0 1 2 3 _ALERT_N CMOS Input Note Input voltage from platform cannot exceed 1 08V max DRAM PWR OK CO1 DRAM PWR OK C23 CMOS 1 2V Output DDR RESET C 01 23 N Open Drain CMOS Input Output DDR SCL CO1 DDR SCL C23 DDR SDA CO1 DDR SDA C23 DC Output DDRO1 VREF DDR23 VREF
7. PE3B TX DP 7 4 PE3C TX DN 11 8 PE3C TX DP 11 8 PE3D TX DN 15 12 PE3D TX DP 15 12 PE HP SCL PE HP SDA DMI2 DMI TX DN 3 0 DMI TX DP 3 0 SMBus DDR SCL CO1 DDR SDA C01 DDR SCL C23 DDR SDA C23 Processor Sideband CATERR_N ERROR_N 2 0 BPM_N 7 0 PRDY_N THERMTRIP_N PROCHOT_N PECI MEM HOT CO1 N MEM HOT C23 N PM FAST WAKE N FIVR_FAULT SVID SVIDCLK SVIDDATA 2 6 Mixing Processors Intel supports and validates two configurations only in which all processors operate with the same Intel QuickPath Interconnect frequency core frequency power segment and have the same internal cache sizes Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel Combining processors from different power segments is also not supported Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet September 2014 28 Order No 330783 001 m Electrical Specifications Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families n tel Note 2 7 2 8 Table 11 September 2014 All processors within a system must run at a common maximum non Turbo ratio The system BIOS may be required to program the FLEX RATIO register if mixed frequency processors are populated Not all operating systems can support dual processors with mixed frequencies Mixing processors of different steppings but
8. sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit has been activated if enabled This signal can also be driven to the processor to activate the Thermal Control Circuit This signal is sampled after PWRGOOD assertion If PROCHOT N is asserted at the deassertion of RESET N the processor will tristate its outputs continued Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 54 September 2014 Order No 330783 001 m Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Signal Descriptions Intel n te Xeon Processor E5 1600 and E5 2600 v3 Product Families Signal Name Description PWRGOOD PWRGOOD is a processor input The processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD PWRGOOD transitions from inactive to active when all supplies except VCCIN are stable The si
9. 0 075 60 VID 0 041 VID 0 063 VID 0 085 70 VID 0 052 VID 0 074 VID 0 096 80 VID 0 062 VID 0 084 VID 0 106 90 VID 0 073 VID 0 095 VID 0 117 100 VID 0 083 VID 0 105 VID 0 127 110 VID 0 094 VID 0 116 VID 0 138 120 VID 0 104 VID 0 126 VID 0 148 130 VID 0 115 VID 0 137 VID 0 159 140 VID 0 125 VID 0 147 VID 0 169 150 VID 0 136 VID 0 158 VID 0 180 160 VID 0 146 VID 0 168 VID 0 190 170 VID 0 157 VID 0 179 VID 0 201 180 VID 0 167 VID 0 189 VID 0 211 190 VID 0 178 VID 0 200 VID 0 222 200 VID 0 188 VID 0 210 VID 0 232 210 VID 0 199 VID 0 221 VID 0 243 220 VID 0 209 VID 0 231 VID 0 253 Note 1 The Vccin_min and Veccin_max loadlines represent static and transient limits Please see Die Voltage Validation on page 35 for Vccin Overshoot specifications 2 This table is intended to aid in reading discrete points on graph in Figure 4 on page 35 3 The loadlines specify voltage limits at the die measured at the Vccin_sense and Vss vccin_sense lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor Vcctn_sense and Vss_vccin_sense lands 4 The Adaptive Loadline Positioning slope is 1 05 mQ mohm with 22mV TOB Tolerance of Band 5 Processor core current Icc ranges are valid up to Icciy wAx of the processor SKU as defined in the previous table above Intel Xeon Processor E5 1600 and E5 2600
10. A term used in conjunction with cache allocation policy MESIF Modified Exclusive Shared Invalid Forwarded States used in conjunction with cache coherency MLC Mid Level Cache NCTF Non Critical to Function NCTF locations are typically redundant ground or non critical reserved so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality continued September 2014 Order No 330783 001 Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 11 1 n te Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Introduction Term Description NID Node ID NID or NodeID NID The processor implements up to 4 bits of NodeID NID NodeID Node ID NID or NodeID NID pcode Pcode is microcode which is run on the dedicated microcontroller within the PCU PCH Platform Controller Hub A chipset with centralized platform capabilities including the main I O interfaces along with display connectivity audio features power management manageability security and storage features PCU Power Control Unit PCI Express 3 0 The third generation PCI Express specification that operates at twice the speed of PCI Express 2 0 8 Gb s PCI Express 3 0 is completely backward compatible with PCI Express 1 0 and 2 0 PCI Express 2 0 PCI Express Generation 2 0 PECI Pla
11. DOZ DD18 DD20 DG19 DEZ DEIS DF20 DETO DF22 DE23 CT26 CP26 DAS DD24 CY26 CV26 DF24 DF26 B B C C C C V4 U1 CL5 M4 E5 F6 K6 CL3 September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 63 Appendix A Pin List Pin Name Pin Number Buffer Type CRS SSTL ove SSTL CT6 SSTL CP SSTL CAS SSTL CR SSTL CP2 SSTL CUS SSTL CRS SSTL DA7 SSTL DBS SSTL DETI SSTL DOT SSTL DAS SSTL CYs SSTL B SSTL DES SSTL DFO SSTL CT28 SSTL OP28 SSTL CT32 SSTL CP32 SSTL CUe7 SSTL R27 SSTL cust SSTL ORS SSTL BTA SSTL DAS SSTL DB30 SSTL DO33 SSTL DF34 SSTL DB28 SSTL CY28 SSTL DA3S SSTL DE33 SSTL CUSS SSTL CRIS SSTL BT2 SSTL CUGS SSTL CR30 SSTL vad SSTL OT34 SSTL vse SSTL Tas SSTL DC97 SSTL IIXIXx I IXIXxXIXxIxIx September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 64 Appendix A Pin List Pin Name Pin Number Buffer Type DF36 SSTL DCaS SSTL DAIS Ser SSTL DC35 SSTL DB36 SSTL DF38 SSTL DE39 SSTL SSTL SSTL SSTL SSTL SSTL x SIS 5 IxX B DDR1 DQS DN 10 C SSTL DDR1_DQS_DN 11 SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL DDR1
12. PCI Express Port 1 2 amp 3 Signals Differential PCI Express Input PE1A_RX_D N P 3 0 PE1B_RX_D N P 7 4 PE2A_RX_D N P 3 0 PE2B_RX_D N P 7 4 PE2C_RX_D N P 11 8 PE2D_RX_D N P 15 12 PE3A_RX_D N P 3 0 PE3B_RX_D N P 7 4 PE3C_RX_D N P 11 8 PE3D_RX_D N P 15 12 Differential PCI Express Output PE1A TX D N P 3 0 PE1B TX D N P 7 4 PE2A TX D N P 3 0 PE2B TX D N P 7 4 PE2C TX D N P 11 8 PE2D TX DIN P 15 12 PE3A TX D N P 3 0 PE3B TX D N P 7 4 PE3C TX D N P 11 8 PE3D TX D N P 15 12 PCI Express Miscellaneous Signals Single ended Open Drain CMOS Input Output PE HP SCL PE HP SDA DMI2 PCI Express Signals Differential DMI2 Input DMI RX D N P 3 0 DMI2 Output DMI TX D N P 3 0 Intel QuickPath Interconnect Intel QPI Signals continued Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet September 2014 24 Order No 330783 001 Ici e Electrical Specifications Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families n tel Differential Single Ended Buffer Type Signal Differential Intel QPI Input QPI 0 1 DRX D N P 19 0 QPI 0 1 CLKRX D N P Intel QPI Output QPI40 1 DTX DIN P 19 0 QPI40 1 CLKTX D N P Platform Environmental Control Interface PECI Single ended PECI Input Output PECI System Re
13. PCI Express Signals The PCI Express Signal Group consists of PCI Express ports 1 2 and 3 and PCI Express miscellaneous signals Please refer to Table 7 on page 23 for further details Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 14 September 2014 Order No 330783 001 m Electrical Specifications Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families n tel 2 2 3 2 2 4 2 2 5 Figure 1 September 2014 DMI2 PCI Express Signals The Direct Media Interface Gen 2 DMI2 sends and receives packets and or commands to the PCH The DMI2 is an extension of the standard PCI Express Specification The DMI2 PCI Express Signals consist of DMI2 receive and transmit input output signals and a control signal to select DMI2 or PCIe 2 0 operation for port 0 Please refer to Table 7 on page 23 for further details Intel QuickPath Interconnect Intel QPI The processor provides two Intel QPI ports for high speed serial transfer between other processors Each port consists of two uni directional links for transmit and receive A differential signaling scheme is utilized which consists of opposite polarity DP DN signal pairs Platform Environmental Control Interface PECI PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external system management logic and thermal monitori
14. Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical September 2014 Order No 330783 001 Datasheet 5 m n tel Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Figures Figures 1 Input Device Hysteresis icri ertt T RE Reda eR rra Ud 15 2 VR Power State TransitlorS scisco see px u EE EE RE E E atenne d rct Pus De Re ds A a uae 20 3 Serial VID Interface SVID Signals Clock Timings esses 32 4 Vecin Static and Transient Tolerance Loadlines cccccee cece eects ee ects eee eee nn 35 5 Vecin Overshoot Example Waveform esses eene nennen 36 6 BCLK 0 1 Differential Clock Measurement Point for Ringback eese 39 7 BCLK 0 1 Differential Clock Crosspoint Specification sess 40 8 BCLK 0 1 Single Ended Clock Measurement Points for Absolute Cross Point and Swing 40 9 BCLK 0 1 Single Ended Clock Measure Points for Delta Cross Point eeessese 40 10 PWRGOOD SIgnal WaVvefotm rex eek cas nana sana nau sa Rana Rua CEAD ENR nE ERI iari 45 11 Maximum Acceptable Overshoot Undershoot WavefOrm ccceceeeceeeeeeeeeeeeeeeeeeeeeeeaeas 46 Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 6 September 2014 Order No 330783 001 m Tables Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families n tel Tables 1 Structure of the
15. SVIDCLK cpu pad Teo A SVIDDATA drive cpu pad ia e Toss Tis SVIDDATA recive cpu pad e E SVIDDATA combine di amp rcv cpu pad veia e Oo vale Table 14 CPU Power Rails Load Specification w a gt gt gt un In gt gt gt In In ma c ea E a z 9 3 2 g 3 g z ej E E z z et z 8 gt z z a 5 9 x x o s u 9 m Ez i z 9 o au lt lt Oo a a Q 5 a v gt o 5 z z S o v E a 9 8 s 9 9g S S x o 3 N m e m a Ei e 9 a a o a 5i 3 i 9 x 9 9 a 9 o g S a x x lt E S z n a n o E S z d z z EA P a E 5 z 1 S je I a 9 g g l g g n U El m 2 Segme 145W 189 0 1 0 001 1 4 1 4 88 0 02 0 001 0 8 0 8 288 290 2 4 nt 18 2 45 2 45 2 2 2 2 Optimiz Core ed 135W 175 0 1 0 001 1 4 14 82 0 02 0 001 0 8 0 8 267 270 2 4 16 2 45 2 45 2 2 2 2 Core 145W 189 0 1 0 001 1 4 14 88 0 02 0 001 0 8 0 8 288 290 2 4 14 2 45 2 45 2 2 2 2 Core 120W 156 0 1 0 001 1 4 1 4 73 0 02 0 001 0 8 0 8 238 240 2 4 14 2 45 2 45 2 2 2 2 Core Workst 160W 208 0 1 0 001 1 4 14 97 0 02 0 001 0 8 0 8 306 330 2 4 ation 10 2 45 2 45 2 2 2 2 Core Freque 135W 175 0 1 0 001 1 4 14 82 0 02 0 001 0 8 0 8 267 270 2 4 ncy 8 Core 2 45 2 45 2 2 2 2 Optimiz ed 135W 175 0 1 0 001 1 4 1 4 82 0 02 0 001 0 8 0 8 267 270 2 4 6 Core 2 45 2 45 2 2 2 2 135W 175 0 1 0 001 1 4 1 4 82 0 02 0 001 0 8 0 8 267 270 2 4 4 Core 2 45
16. So DD42 DB48 CUAS DE49 DB50 CUA7 DESI DB52 September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 81 Appendix A Pin List Pin Name Pin Number Buffer Type CT46 C746 CT Cus D049 DD44 CTA D045 DD46 cuas DC47 ORAS OF 40 CP40 RAT Mao AV46 n cust CWS B54 FS ES D56 A53 ALS BD46 AJ55 AY46 RS ET BN45 BHA6 BG43 BEA BJ45 BHA BJ43 BM44 BRAG BLAS BP44 BUA BRAG BD44 September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 82 Appendix A Pin List Pin Name Pin Number Buffer Type Brad BTA4 CaaS BV44 BYA DESS C53 F56 D56 K58 H58 RUSS ARES DESS DD54 CYS8 DAS BPa6 aus DCS CY56 RES U53 TSO DAT BL47 CASS AMSA APAB AE4S AM Y54 was IZ RAS P42 UT H56 Ga F46 EGO BFAS cH Brus AMAA September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 83 Appendix A Pin List Pin Name Pin Number Buffer Type CNAS OLAS BK56 BU49 CP52 CCSS ANAS UA ARAS CAS CF42 G4 D2 DB4 D2 C3 BASS B 47 BY46 CV50 AH52 CMOS Z gt CMOS CMOS CMOS ODCMOS ODCMOS CMOS CMOS ODCMOS ODCMOS CMOS CMOS CMOS AF52 CMOS CBi6 W cate PWR B20 PWR CB22 PWR CB24 PWR C826 PWR CG17 W G
17. however this may interfere with some Test Access Port TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bi directional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Resistor values should be within 20 of the impedance of the baseboard trace Reserved or Unused Signals All Reserved RSVD signals must not be connected Connection of these signals to Vecin Vccp Vss or to any other signal including each other can result in component malfunction or incompatibility with future processors For reliable operation always connect unused inputs or bi directional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground Vss Unused outputs maybe left unconnected however this may interfere with some Test Access Port TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bi directional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Resistor values should be within 20 of the impedance of the baseboard trace Signal Group Summary Signals are grouped by buffer type and similar characteristics as listed in the following table The buffer type indicates which signaling technology and specifications apply to the signals
18. 1 61 93 1 96 B6 2 31 D9 2 66 FC 3 01 4E 1 27 71 1 62 94 1 97 B7 2 32 DA 2 67 FD 3 02 4F 1 28 72 1 63 95 1 98 B8 2 33 DB 2 68 FE 3 03 50 1 29 73 1 64 96 1 99 B9 2 34 DC 2 69 FF 3 04 51 1 30 74 1 65 97 2 00 BA 2 35 DD 2 70 continued Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical September 2014 Datasheet Order No 330783 001 2i intel 2 2 10 2 3 Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Electrical Specifications HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN 52 1 31 75 1 66 98 2 01 BB 2 36 DE 2 71 53 1 320 76 1 67 99 2 02 BC 2 37 DF 2 72 54 1 33 77 1 68 9A 2 03 BD 2 38 EO 2 73 Note 1 00h Off State 2 VID Range HEX 01 32 are not used by the Intel Xeon processor E5 1600 and E5 2600 v3 product families 3 For VID Ranges supported see Table 13 on page 31 4 Vccp is a fixed voltage of 1 20V Reserved or Unused Signals All Reserved RSVD signals must not be connected Connection of these signals to Vecin Vccp Vss or to any other signal including each other can result in component malfunction or incompatibility with future processors For reliable operation always connect unused inputs or bi directional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground Vss Unused outputs maybe left unconnected
19. 2600 v3 Product Families Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Signal Descriptions Signal Name Description DDR 0 1 2 3 _ODT 5 0 On Die Termination Enables DRAM on die termination during Data Write or Data Read transactions DDR 0 1 2 3 _RAS_N Row Address Strobe MUXed with DDR 0 1 2 3 _MA 16 DDR 0 1 2 3 _WE_N Write Enable MUXed with DDR 0 1 2 3 _MA 14 Memory Channel Miscel laneous Signal Name Description DDR RESET CO1 N DDR RESET C23 N System memory reset Reset signal from processor to DRAM devices on the DIMMs DDR RESET CO1 N is used for memory channels 0 and 1 while DDR RESET C23 N is used for memory channels 2 and 3 DDR SCL CO1 SMBus clock for the dedicated interface to the serial presence detect SPD DDR SCL C23 and thermal sensors TSoD on the DIMMs DDR SCL CO1 is used for memory channels 0 and 1 while DDR_SCL_C23 is used for memory channels 2 and 3 DDR SDA C01 SMBus data for the dedicated interface to the serial presence detect SPD DDR SDA C23 and thermal sensors TSoD on the DIMMs DDR SDA CO1 is used for x memory channels 0 and 1 while DDR SDA C23 is used for memory channels 2 and 3 DDRO1 VREF Voltage reference for CMD ADD to the DIMMs DDRO1_VREF is used for DDR23 VREF memory channels 0 and 1 while DDR23_VREF is used for memory channels 2 and 3 DRAM PWR OK CO1 DRAM PWR OK C23 Power good for Vccp rail used b
20. 8 8 7 L W AJ9 5 H8 V38 U31 T3 V26 M V U25 N AJ7 ACES AB38 O27 DDR2 ECC 1 AA27 DDR2 ECC AC23 DDR2 ECC 3 AA23 DDR2 ECC 4 AD28 AB28 AD24 AB24 L15 v16 ARIS T20 wei P12 September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 69 Appendix A Pin List Pin Number Buffer Type Y14 SSTL R13 SSTL P14 SSTL T14 SSTL T18 SSTL L17 SSTL R19 SSTL P18 SSTL M18 SSTL U19 SSTL L19 SSTL P20 SSTL Y16 SSTL W15 SSTL R15 SSTL AB14 SSTL AE17 SSTL AD14 SSTL SSTL DDR2 MA 14 DDR2 MA 15 DDR2 MA 16 DDR2 MA 17 DDR2 MA 2 DDR2 MA 3 DDR2 MA 4 DDR2 MA 5 DDR2 MA 6 DDR2 MA 7 DDR2 MA 8 DDR2 MA 9 DDR2 ODT 0 DDR2 ODI 1 DDR2 ODT 2 DDR2_ODT 3 DDR2 ODT 4 DDR2 ODT 5 DDR2 PAR DDR23 VREF T40 DDR3 ACT N L21 SSTL DDR3 ALERT N 22 SSTL DDR3 BA 0 G13 SSTL DDR3 BA 1 K14 SSTL DDR3 BG 0 2 SSTL DDR3 BG 1 G 1 SSTL DDR3 CID 2 J11 SSTL DDR3 CKE 0 F22 SSTL DDR3 CKE 1 E21 SSTL DDR3_CKE 2 A2 SSTL DDR3_CKE 3 D22 SSTL DDR3 CKE 4 B2 SSTL DDR3 CKE 5 K2 SSTL DDR3 CLK DN O C17 SSTL DDR3 CLK DN 1 D20 SSTL DDR3 CLK DN 2 D18 SSTL DDR3 CLK DN 3 C19 SSTL DDR3 CLK DP 0 A17 SSTL DDR3 CLK DPT1 B2 SSTL DDR3 CLK DP 2 B18 SSTL DDR3 CLK DP 3 A19 SSTL DDR3 CS N 0 B16 SSTL DDR3 CS N 1 C15 SSTL DDR3 CS N 2JCID O F10 SSTL DDR3 CS N S3JCID 1 H10 SSTL N 2 N g O c peri NIN
21. DDR4 Fourth generation Double Data Rate SDRAM memory technology DMA Direct Memory Access DMI2 Direct Media Interface Gen2 operating at PCI Express 2 0 speed DSB Data Stream Buffer Part of the processor core architecture DTLB Data Translation Look aside Buffer Part of the processor core architecture DTS Digital Thermal Sensor ECC Error Correction Code Enhanced Intel SpeedStep Technology Allows the operating system to reduce power consumption when performance is not needed Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system See the Inte 64 and IA 32 Architectures Software Developer s Manuals for more detailed information FLIT Functional Operation Flow Control Unit The Intel QPI Link layer s unit of transfer 1 Flit 80 bits Refers to the normal operating conditions in which all processor specifications including DC system bus signal quality mechanical and thermal are satisfied GSSE Extension of the SSE SSE2 Streaming SIMD Extensions floating point instruction set to 256b operands HA A Home Agent HA orders read a
22. DP BCLK 0 1 DN eene 16 2 2 7 JTAG and Test Access Port TAP SigQnalsS cceceeeceeeeeee teeta eee ee eee eeeeeeaeeeas 16 2 2 8 Processor Sideband Signal Sisina eeedend adie serie na n tu tense ka nene n a RR RR regn 16 2 2 9 Power Ground and Sense Signals sssssssssssssssseeneennem nen 17 2 2 10 Reserved or Unused Signals eeeeeeeeeiees seen enhn eheu nana nana nu nn n n 22 2 3 Signal Group Summary peine penitentie x rasan neri RE REOR F ROLE EEE e RE NR RE 22 2 4 Power On Configuration POC Options c sss nemen 26 2 5 Fault Resilient Booting ERB 2 ierat a cae de addere sx rh aene R raga daa ena lA T Eri E Rea 27 2 6 une use uce EEUU 28 2 7 Flexible Motherboard Guidelines FMB ccceeeeee eee eect eee e esas eee e eases meme 29 2 8 Absolute Maximum and Minimum RatingS ccccecee eee ee eee ee eee eee ee eats eee emen 29 279 DC Specifications oerte eic ioiese O a E A qux EUN e NUR N TREND IRR Roe RN 31 2 9 1 Voltage and Current Specifications cssssssssessssssse nennen 31 2 9 2 Die Voltage Validation sssssssssssssesesssesene seen eee nen 35 2 9 3 Signal DC Specifications sicrie eret ertet a needed ada arua E HR a adaa 36 2 10 Package C State Power Specifications esssssssssssssssssseeenenennneme nene 42 2 LL SiG ial Quality MER 44 2 11 1 DDR Signal Quality Specifications sss 44 2 11 2 I O Signal Q
23. DQS DN 12 DDR1 DQS DN 14 CY32 DDR1_DQS DN 13 CR29 DDR1 DQS DN 17 CY14 DDR1 DQS DN 2 C C C C C D DDR1 DQS DN 15 CT36 D DDR1 DQS DNI4 CV30 DDR1 DQS DN 5 DB32 DDR1 DQS DN 6 CU37 DDR1 DQS DN 7 DA37 DDR1 DQS DN 8 DA13 DDR1 DQS DN 9 B bomi pos peo 6 Domi Das peu 3 DE37 3 A BY C W G C W BY C W DDR1 DQS DP 12 DC DDR1 DQS DP 13 CU29 DDR1_DQS_DP 14 DA31 DDR1 DQS DP 15 CV36 DDR1 DQS DP 16 DD36 DDR1 DQS DP 7 CW13 DDR1 DQS DP 2 CT DDR1 DQS DP 3 DB10 DDR1 DQS DP 4 CT30 DDR1 DQS DP 5 DD32 2 E3 F4 H6 3 U3 D8 V4 9 4 J5 H4 7 4 DDR DOS DN 3 DDR1 DQS DP 6 CR37 DDR1 DQS DP 7 DB38 September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 65 Appendix A Pin List PinName PinNumber BufferType DETA SSTL SSTL SSTL Ovid SSTL DDi4 SSTL DFTA SSTL CRIS SSTL V2 B CU13 IIXIXx DDR1 ECC 5 CT14 SSTL DDR1 ECC 6 DC13 SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL DETS CY22 DA CR23 CVi8 Owi7 Owes CNe3 ved CY24 CT24 CV20 owe CRI CY20 CWi9 OTIS DATS CYi8 DD22 DE25 DC23 DC25 DAS DD26 CT20 AED p22 v14 DDR2 BA 1 U17 DD
24. GND AB36 GND AB40 GND AB42 GND AC11 GND AC29 GND AC7 GND AC GND AD10 GND AD12 GN AD36 GND D GND AD40 GND AD42 GND AD44 GND AD46 GND AD48 GND AD50 GN AD52 GN D6 GN D8 GN AE13 GND AE15 GND AE19 GND AE23 GND AE27 GND AE29 GN AE33 GN AE35 GN AE39 GND AE41 GND AE43 GND AE47 GND AE49 GND AE51 GND AE53 GN AF10 GN AF16 GND AF18 GND AF2 GND AF20 GND AF22 GND AF24 GND co lt oO gt lt oO lt gt oO lt gt lt w lt 0 lt oO D p September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 90 Appendix A Pin List Pin Number Buffer Type GND GND GND GND GN GN GN GND GND GND GND GN GN GN GN GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ojojo ojojojo September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 91 Appendix A Pin List Pin Number Buffer Type AL53 GND AM10 GND AM12 GND AM14 GND AM16 GND AM2 GND M GND AM56 GND AM6 GND AM GND AN GND AN13 GN AN15 GND N3 GND AN5 GND AN55 GND AN57 GND AN7 GND AN9 GND AP42 GN AP44 GN AP58 GN AT44 GN AT46 GND AT48 GND AT50 GND AT52 GND AU45 GND AU47 GN AU49 GN AU51 GN AU53 GND AV42 GND AV54 GND AV
25. Order No 330783 001 Electrical Specifications Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Table 9 2 5 Table 10 September 2014 Power On Configuration Option Lands Configuration Option Land Name Notes Output tri state PROCHOT N 1 Execute BIST Built In Self Test BIST ENABLE 2 Enable Service Processor Boot Mode BMCINIT 3 Power up Sequence Halt EAR N 3 Enable Intel Trusted Execution Technology Intel TXT TXT PLTEN 3 Platform Enable Bootable Firmware Agent FRMAGENT 3 Enable Intel Trusted Execution Technology Intel TXT Agent TXT AGENT 3 Enable Safe Mode Boot SAFE MODE BOOT 3 Configure Socket ID SOCKET ID 1 0 3 Enables debug from cold boot DEBUG EN N 3 Note 2 BIST ENABLE is sampled at RESET N de assertion 3 This signal is sampled after PWRGOOD assertion 1 Output tri state option enables Fault Resilient Booting FRB for FRB details see the Fault Resilient Booting FRB Section The signal used to latch PROCHOT N for enabling FRB mode is RESET N Fault Resilient Booting FRB The Intel Xeon processor v3 product families supports both socket and core level Fault Resilient Booting FRB which provides the ability to boot the system as long as there is one processor functional in the system One limitation to socket level FRB is that the system cannot boot if the legacy socket that connects to an active PCH becomes unavailable since this is the pat
26. Processor Datasheet 0 ccccecceeeeeeeeeeeeseneaneeneeeeeeceeeeeeneneeeeaeaeereananeesanes 9 2 Public Publication ER 9 3 Power and Ground Landes cies iiie her bin enhn ln anra a RR ATA deans set ONDE REIR RE ES ENa 17 4 SVID Address Usage sii etes a e tek rn a a endaedt ie ecedbannesabibsadeat ea aie FER i RA RAS 20 5 VR12 5 Reference Code Voltage Identification VID Table sse 21 6 Signal Description Buffer Types sese onte nhi nien nuo tana a xke ATTE nini acs ORAE TEE RE RE KME 23 7 Signal GFOUpS iiec rn thi nn rd En OE NEG ROLE UC ERRARE CURA YER KT EATER AE E ERBEN EE A 23 8 Signals with On Die Weak PU PD 2 5 etre tere ena Du nna ax ud nn ees re xat ha nnda cu ane BERE RR 26 9 Power On Configuration Option Lands sssssssssssesee emen eem 27 10 Fault Resilient Booting Output Tri State Signals sessssesssseeememm 27 11 Processor Absolute Minimum and Maximum Ratings sese 29 12 Storage Condition Ratihgs iei eerte treten hein rex da la saa a aka eR ae ERR dad ERA APERTA E 30 13 Voltage SpecifiCcatiOn ie ciii eb ar E a EEO Xu aenea E IM DERE 31 14 CPU Power Rails Load Specification eeeeeieeee sese essen enne nennen nenkh nna nnn nana nna tad nk nnn 32 15 Veccin Static and Transient Tolerance Intel Xeon Processor E5 1600 and E5 2600 v3 Prod ct FamiliB amp s 2 rera oi rera a taam ena Ta sick dad RR ER D Ra a dada E ARR ER RA ERR EN bee 33 16
27. Resistance 6 00 mA Vou 0 75 Vecreci TLeak High impedance state 50 200 HA leakage to VccIo_IN Vieak VoL Ron High impedance 20 36 Q leakage to GND Vieak Von Caus Bus capacitance per N A 10 pF 4 5 node VNoise Signal noise immunity 0 100 N A Vp p above 300 MHz VccPEcI Output Edge Rate 50 1 5 4 V ns ohm to Vss between Vit and Vin Note 1 Vccpeci supplies the PECI interface PECI behavior does not affect Vccpgc min max specification 2 It is expected that the PECI driver will take into account the variance in the receiver input thresholds and consequently be able to drive its output within safe limits 0 150 V to 0 275 Vccpec for the low level and 0 725 Vccpgc to Vccpgcrt 0 150 V for the high level 3 The leakage specification applies to powered devices on the PECI bus 4 One node is counted for each client and one node for the system host Extended trace lengths might appear as additional nodes 5 Excessive capacitive loading on the PECI line may slow down the signal rise fall times and consequently limit the maximum bit rate at which the interface can operate 2 9 3 3 System Reference Clock BCLK 0 1 DC Specifications Symbol Parameter Signal Min Max Unit Figure Notes Vacik ditt in Differential Input Differential 0 150 N A V Figure 6 on page 9 High Voltage 39 Vacik ditt ii Differential Input Differential 0 150 V Figure 6 on page 9 Low Voltage 39 V
28. Vecin Overshoot Specifications esee nenne kenne nan hene EE Run R RM RR ERR AR AR RE d dada 35 17 Processor I O Overshoot Undershoot SpecificationS cccceceeceeeee eee eee nent ee ne eee enaees 45 18 Processor Sideband Signal Group Overshoot Undershoot Tolerance eeeese 47 19 Memory Channel DDRO DDR1 DDR2 DDR3 eccrine es 49 20 Memory Channel MiscellAnGOuS eceeee eee eee ee nemen sese eene eem nens 50 21 PCL Express Port 1 Signals reete tnn snag ene nes ec REE aide ge RI Y a ER RO E Rue 50 22 PCL Express Port 2 Signals ee nteger ten codbenvie xa n doe XAR wind d UR DR a PC IRR Y ASK EN BE RN RA 50 23 PCLExpress Port 3 Signals dir re a terna tts ada SR E dx a aa EA P aa DRY a da ERA Ea 51 24 PCI Express Miscellaneous Signals eese eese nennen nina nne hn nan nn ahhh eR la ARA Ran 51 25 DMI2 and PCI Express Port 0 Signals iiieeec eee setenta nnn kn unu rna EE Eaa 52 26 Intel QPI Port O and 1 Signals ccccccecseneneceeeeeeeeeceeseseaeaeesnaenneesaneeeeecneeeeeeeaaaersanneens 52 27 PECI Signal derininde iaa a a a a a Ana aa a aaaea 52 28 System Reference Clock BCLK 0 1 SignalS ssssssssrsssrsssrssrrrrrrssrnnrnnnsrnnsrnurnnnurnnrans 52 29 JTAG and TAP Signals iier tanen a E EE Ra EEEE Ea AE 53 BO SVID SINAIS asraon TED 53 31 Processor Asynchronous Sideband Signals ssssssssssssssss eene 53 32 Miscellaneous Signals rite spree puer repr
29. a legacy socket bootable firmware agent is present and DMI links are used in PCIe mode instead of DMI2 mode Each processor socket consumes one Node ID and there are 128 Home Agent tracker entries This signal is pulled down on the die Refer to Table 8 on page 26 for details TEST 3 0 Test 3 0 must be individually connected to an appropriate power source or ground through a resistor for proper processor operation TXT AGENT Intel Trusted Execution Technology Intel TXT Agent Strap 0 Default The socket is not the Intel TXT Agent 1 The socket is the Intel TXT Agent The legacy socket identified by SOCKET ID 1 0 00b with Intel TXT Agent should always set the TXT AGENT to 1b This signal is pulled down on the die refer to Table 8 on page 26 for details TXT PLTEN Intel Trusted Execution Technology Intel TXT Platform Enable Strap 0 The platform is not Intel TXT enabled All sockets should be set to zero Scalable DP sDP platforms should choose this setting if the Node Controller does not support Intel TXT Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet September 2014 56 Order No 330783 001 m Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Signal Descriptions Intel n te Xeon Processor E5 1600 and E5 2600 v3 Product Families Signal Name Description 1 Default The platform is I
30. and E5 2600 v3 Product Families Signal Descriptions Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families 4 0 4 1 Table 19 September 2014 intel Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Signal Descriptions This chapter describes the Intel Xeon processor E5 1600 and E5 2600 v3 product families signals They are arranged in functional groups according to their associated interface or category System Memory Interface Memory Channel DDRO DDR1 DDR2 DDR3 Signal Name Description DDR 0 1 2 3 _ACT_N Activate When asserted indicates MA 16 14 are command signals RAS_N CAS_N WE_N DDR 0 1 2 3 _ALERT_N Parity Error detected by the DIMM one for each channel DDR 0 1 2 3 _BA 1 0 Bank Address Defines which bank is the destination for the current Activate Read Write or Precharge command DDR 0 1 2 3 _BG 1 0 Bank Group Defines which bank group is the destination for the current Active Read Write or Precharge command BGO also determines which mode register is to be accessed during a MRS cycle DDR 0 1 2 3 _CAS_N Column Address Strobe MUXed with DDR 0 1 2 3 _MA 15 DDR 0 1 2 3 _CID 4 0 Chip ID Used to select a single die out of the stack of a 3DS device CID 4 3 are MUXed with CS_N 7 6 respectively CID 1 0 are MUXed with CS_N 3 2 respectively DDR 0 1 2 3 _CKE 5 0 DDR 0 1 2 3 _CLK_DN 3 0 DDR 0 1 2 3 _CLK_DP 3 0
31. enables the processor to run a faster frequency This results in increased performance of both single and multi threaded applications Intel TXT Intel Trusted Execution Technology Intel Virtualization Technology Intel VT Processor Virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple robust independent software environments inside a single platform Intel VT d Intel Virtualization Technology Intel VT for Directed I O Intel VT d is a hardware assist under system software Virtual Machine Manager or OS control for enabling I O device Virtualization Intel VT d also brings robust security by providing protection from errant DMAs by using DMA remapping a key feature of Intel VT d Integrated Heat Spreader IHS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface IOV I O Virtualization IVR Integrated Voltage Regulation IVR The processor supports several integrated voltage regulators Jitter Any timing variation of a transition edge or edges from the defined Unit Interval UI LGA 2011 3 Socket The 2011 3 land FC LGA package mates with the system board through this surface mount 2011 3 contact socket LLC Last Level Cache LRDIMM Load Reduced Dual In line Memory Module LRU Least Recently Used
32. light load 5A to 20A e PS2 02h Represents a very light load 5A The VR may change its configuration to meet the processor s power needs with greater efficiency For example it may reduce the number of active phases transition from CCM Continuous Conduction Mode to DCM Discontinuous Conduction Mode mode reduce the switching frequency or pulse skip or change to asynchronous regulation For example typical power states are 00h run in normal mode a command of Oih shed phases mode and an 02h pulse skip The VR may reduce the number of active phases from PS 00h to PS O1h or PS 00h to PS 02h for example There are multiple VR design schemes that can be used to maintain a greater efficiency in these different power states please work with your VR controller suppliers for optimizations If a power state is not supported by the controller the slave should acknowledge the SetPS command and enter the lowest power state that is supported If the VR is in a low power state and receives a SetVID command moving the VID up then the VR exits the low power state to normal mode PSO to move the voltage up as fast as possible The processor must re issue low power state PS1 or PS2 command if it is in a low current condition at the new higher voltage See the figure below for VR power state transitions Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical September 2014 Datasheet Order No 330783 0
33. shown with 1 not used Table 5 VR12 5 Reference Code Voltage Identification VID Table HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN 00 0 00 55 1 34 78 1 69 9B 2 04 BE 2 39 El 2 74 33 1 00 56 1 35 79 1 70 9C 2 05 BF 2 40 E2 2 75 34 1 01 57 1 36 7A 1 71 9D 2 06 CO 2 41 E3 2 76 35 1 02 58 1 37 7B 1 72 9E 2 07 Ci 2 42 E4 2 77 36 1 03 59 1 38 7C 1 73 9F 2 08 C2 2 43 E5 2 78 37 1 04 5A 1 39 7D 1 74 AO 2 09 C3 2 44 E6 2 79 38 1 05 5B 1 40 7E 1 75 A1 2 10 C4 2 45 E7 2 80 39 1 06 5C 1 41 7F 1 76 A2 2 11 C5 2 46 E8 2 81 3A 1 07 5D 1 42 80 1 77 A3 2 12 C6 2 47 E9 2 82 3B 1 08 5E 1 43 81 1 78 A4 2 13 C7 2 48 EA 2 83 3C 1 09 5F 1 44 82 1 79 A5 2 14 C8 2 49 EB 2 84 3D 1 10 60 1 45 83 1 80 A6 2 15 C9 2 50 EC 2 85 3E 1 11 61 1 46 84 1 81 A7 2 16 CA 2 51 ED 2 86 3F 1 12 62 1 47 85 1 82 A8 2 17 CB 2 52 EE 2 87 40 1 13 63 1 48 86 1 83 AQ 2 18 cc 2 53 EF 2 88 41 1 14 64 1 49 87 1 84 AA 2 19 CD 2 54 FO 2 89 42 1 15 65 1 50 88 1 85 AB 2 20 CE 2 55 F1 2 90 43 1 16 66 1 51 89 1 86 AC 2 21 CF 2 56 F2 2 91 44 1 17 67 1 52 8A 1 87 AD 2 22 DO 2 57 F3 2 92 45 1 18 68 1 53 8B 1 88 AE 2 23 D1 2 58 F4 2 93 46 1 19 69 1 54 8C 1 89 AF 2 24 D2 2 59 F5 2 94 47 1 20 6A 1 55 8D 1 90 BO 2 25 D3 2 60 F6 2 95 48 1 21 6B 1 56 8E 1 91 B1 2 26 D4 2 61 F7 2 96 49 1 22 6C 1 57 8F 1 92 B2 2 27 D5 2 62 F8 2 97 4A 1 23 6D 1 58 90 1 93 B3 2 28 D6 2 63 F9 2 98 4B 1 24 6E 1 59 91 1 94 B4 2 29 D7 2 64 FA 2 99 4C 1 25 6F 1 60 92 1 95 B5 2 30 D8 2 65 FB 3 00 4D 1 26 70
34. storage temperature qualification methods follow JEDEC High and Low Temperature Storage Life Standards JESD22 A119 low temperature and JESD22 A103 high temperature w Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 30 September 2014 Order No 330783 001 Electrical Specifications Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families 2 9 2 9 1 DC Specifications intel DC specifications are defined at the processor pads unless otherwise noted DC specifications are only valid while meeting specifications for case temperature TCASE specified in the Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Thermal Mechanical Specification and Design Guide TMSDG clock frequency and input voltages Care should be taken to read all notes associated with each specification Voltage and Current Specifications Table 13 Voltage Specification Symbols Parameter Voltage Min Nom Max Unit Notes Plane VccIN Input to VccIN 1 47 1 82 1 85 V 2 3 4 5 Integrated 8 10 13 Voltage Regulator Launch FMB VVID_STEP VID step size 10 0 mV 6 Vecin Veen during a transition V ccp V I O Voltage for Vccp 0 97 Vccp NoM 1 2 1 044 Vccp NoM V 7 9 10 CCD 01 V DDR4 11 12 CCD 23 Standard Voltage Note 1 Unless otherwise noted all specifications in this table apply to all processors These specifica
35. subtracted from the total overshoot undershoot pulse duration Figure 11 Maximum Acceptable Overshoot Undershoot Waveform Over Shoot I Duration gt Under Shoot k Duration Under Shoot PR Activity Factor Activity factor AF describes the frequency of overshoot or undershoot occurrence relative to a clock Since the highest frequency of assertion of any common clock signal is every other clock an AF 0 1 indicates that the specific overshoot or undershoot waveform occurs every other clock cycle The specification provided in the table shows the maximum pulse duration allowed for a given overshoot undershoot magnitude at a specific activity factor Each table entry is independent of all others meaning that the pulse duration reflects the existence of overshoot undershoot events of that magnitude ONLY A platform with an overshoot undershoot that just meets the pulse duration for a specific magnitude where the AF 0 1 means that there can be no other overshoot undershoot events even of lesser magnitude note that if AF 0 1 then the event occurs at all times and no other events can occur Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet September 2014 46 Order No 330783 001 m Electrical Specifications Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families n tel Table 18 September 2014 Read
36. the same model as per CPUID instruction is supported provided there is no more than one stepping delta between the processors for example S and S 1 S and S 1 is defined as mixing of two CPU steppings in the same platform where one CPU is S stepping CPUID EAX 01h EAX 3 0 and the other is S 1 CPUID EAX 01h EAX 3 0 1 The stepping ID is found in EAX 3 0 after executing the CPUID instruction with Function O1h Details regarding the CPUID instruction are provided in the Intel 64 and IA 32 Architectures Software Developer s Manuals Volume 2A Instruction Set Reference A M Flexible Motherboard Guidelines FMB The Flexible Motherboard FMB guidelines are estimates of the maximum values the Intel Xeon processor v3 product families will have over certain time periods The values are only estimates and actual specifications for future processors may differ Processors may or may not have specifications equal to the FMB value in the foreseeable future System designers should meet the FMB values to ensure their systems will be compatible with future processors Absolute Maximum and Minimum Ratings The table below specifies absolute maximum and minimum ratings At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subj
37. v3 Product Families Volume 1 of 2 Electrical Datasheet 34 September 2014 Order No 330783 001 Electrical Specifications Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families n te Figure 4 2 9 2 Table 16 September 2014 Vccin Static and Transient Tolerance Loadlines VccIN load A 0 040 0 020 0 000 0 020 0 040 0 060 0 080 0 100 0 120 0 140 VclN_Max V 0 160 VcclN Typ V 0 180 et nee 0 200 ccIN_Min 0 220 0 240 0 260 1 05 mQ Load Line 0 280 N normalized droop V set fom measured sVID Of Vc Die Voltage Validation Overshoot events at the processor must meet the specifications in Table 16 on page 35 when measured across the Vccin_sense and Vss vccin_sense lands Overshoot events that are 10 ns in duration may be ignored These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope Vccin Overshoot Specifications The Intel Xeon processor E5 1600 and E5 2600 v3 product families can tolerate short transient overshoot events where Vccin exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos max Vos wax is the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the Vccin_seENSE and Vss_vccin_sense lands Vccin Over
38. 00 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 71 Appendix A Pin List eurer aeterrue SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL TISI am m i im E a ian September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 72 Appendix A Pin List PinName PinNumber BufferType DDR3 DQS DP 10 SSTL DDR3 DQS DPT 1 SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL G19 SSTL F20 SSTL D16 SSTL INE SSTL D14 SSTL DDR3_DQS_DP 12 DDR3 DQS DP 13 DDR3_DQS_DP 14 DDR3_DQS_DP 15 DDR3_DQS_DP 16 DDR3_DQS_DP 17 DDR3 DQS DP DDR3_DQS_DP 3 DDR3_DQS_DP 4 DDR3_DQS_DP 5 DDR3 DQS DP 6 A A A DDR3 DQS DP 7 DDR3 DQS DP 8 Ix 3 F M B Y H E 2 F 2 2 2 2 M12 F12 3 Xr G15 K16 L13 35 3 26 4 8 H4 6 26 32 25 2 7 K2 B4 5 38 7 7 3 3 28 28 24 24 20 20 C J M M E L L J L J K M M K K M F
39. 01 19 intel Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Electrical Specifications Figure 2 VR Power State Transitions SVID Voltage Rail Addressing The processor addresses 3 different voltage rail control segments within VR12 5 Vccin Vccp o1 and Vccp 23 The SVID data packet contains a 4 bit addressing code Table 4 SVID Address Usage PWM Address HEX Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families 1 2 3 00 Vecin 01 NA 02 Vccp 01 03 1 not used 04 Vccp 23 05 1 not used Note Check with VR vendors for determining the physical address assignment method for their controllers VR addressing is assigned on a per voltage rail basis Dual VR controllers will have two addresses with the lowest order address always being the higher phase count continued Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 20 September 2014 Order No 330783 001 m e Electrical Specifications Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families n tel PWM Address HEX Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families 4 daba platform flexibility the VR controller should include an address offset as
40. 1 W CG2 W oG23 PWR CG25 PWR OMe PWR OMIS PWR MEO PWR M22 PWR OM24 W M26 W CU PWR CUI PWR Cue PWR cues PWR CUeS PWR DB16 PWR v D v v D v v D D l CBi6 P September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 84 Appendix A Pin List Pin Name Pin Number Buffer Type DETS PWR DB20 PWR D22 PWR DB24 PWR DB26 W DET W ACIS W ACIT PWR ACIS PWR AOR PWR c PWR PWR cei PWR E15 PWR E17 PWR E19 PWR Hie PWR PWR Hi6 PWR His PWR H20 PWR H22 PWR PWR v v pu Q M AB e pu v pu VCCD 23 N11 VCCD 23 N13 PWR NIS NT PWR vei PWR vid PWR Vi6 PWR Vie PWR v20 PWR V22 PWR CER PWR AF42 PWR G23 PWR AG27 PWR Ga PWR AGS PWR AG35 PWR AG39 PWR AGA PWR Ana PWR ALT PWR ANA PWR PWR PWR September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 85 Appendix A Pin List Pin Name Pin Number Buffer Type ANT PWR ANT PWR APTO PWR APT PWR APTA W Dur W W PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR v v pu pu v pu September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical D
41. 12 3 Processor 0 35 Vccio IN 1 35 VccIO IN 1 25 ns 0 5 ns 1 2 Asynchronous Sideband Signals System 0 3V 1 15V N A N A 1 2 Reference Clock BCLK 0 1 PWRGOOD 0 420V Vccio IN 0 28 1 25 ns 0 5 ns 3 Signal PWRGOOD SIgnal Waveform V t overshoo eoccccee Vu ndershoot Overshoot Undershoot Magnitude Magnitude describes the maximum potential difference between a signal and its voltage reference level For the processor both are referenced to VSS It is important to note that the overshoot and undershoot conditions are separate and their impact must be determined independently The pulse magnitude and duration must be used to determine if the overshoot undershoot pulse is within specifications Order No 330783 001 Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 45 m n te Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Electrical Specifications Overshoot Undershoot Pulse Duration Pulse duration describes the total amount of time that an overshoot undershoot event exceeds the overshoot undershoot reference voltage The total time could encompass several oscillations above the reference voltage Multiple overshoot undershoot pulses within a single overshoot undershoot event may need to be measured to determine the total pulse duration Note Oscillations below the reference voltage cannot be
42. 29 24 12 E5 2608L v3 52W 6 Core 26 22 12 Notes 1 Package C6 power specified at Tcase 50 C 2 Characterized but not tested Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical September 2014 Datasheet Order No 330783 001 43 m n tel Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Electrical Specifications 2 11 2 11 1 2 11 2 2 11 3 2 11 4 Signal Quality Data transfer requires the clean reception of data signals and clock signals Ringing below receiver thresholds non monotonic signal edges and excessive voltage swings will adversely affect system timings Ringback and signal non monotonicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines Excessive signal swings overshoot and undershoot are detrimental to silicon gate oxide integrity and can cause device failure if absolute voltage limits are exceeded Overshoot and undershoot can also cause timing degradation due to the build up of inter symbol interference ISI effects For these reasons it is crucial that the designer work towards a solution that provides acceptable signal quality across all systematic variations encountered in volume manufacturing This section documents signal quality metrics used to derive topology and routing guidelines through simulation All specifications are specified at the processor die pad measurements Specifica
43. 43 IX RES A T10 A U11 9 DDR2 DQ 49 AF12 AC39 DDR2 DQ 5O AK12 DDR2 DQ 51 AL13 DDR2 DQ 52 AG15 DDR2 DQ 53 AF14 DDR2 DQ 54 AK14 DDR2 DQ 55 AL15 AK10 por pog fu pore pog v oore po u R 4 4 9 8 7 9 9 6 6 9 8 8 A A A T A A A A 2 2 N K R J L K M U B A Y G G 3 K E E 3 8 9 7 7 9 8 7 7 DDR2 DQS DN O W DDR2 DQS DN 1 DDR2 DQS DN 10 L9 L7 3 4 33 3 V32 33 DDR2 DQS DN 11 AA33 DDR2 DQS DN 12 T26 September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 68 Appendix A Pin List Pin Number Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL DDR2 DQS DN 14 DDR2 DQS DN 15 AJ15 DDR2 DQS DN 16 DDR2 DQS DN 13 DDR2 DQS DN 17 AB26 DDR2_DQS_DN 2 AD32 DDR2 DQS DN 3 W A Ix DDR2 DQS DNI4 DDR2 DQS DN 5 Y10 DDR2 DQS DN 6 AJ13 DDR2 DQS DN 7 DDR2 DQS DNI 8 AE25 DDR2 DQS DN 9 AC37 DDR2 DQS DP 0 IxXIx DDR2 DQS DP 10 Ix DDR2 DQS DPH AC33 DDR2 DQS DP 2 DDR2_DQS_DP 13 AHIG AHO AD26 AB32 AB10 AHI DDR2 DOS DP i 7 9 2 4
44. 56 GND AW 11 GND AW13 GND AW15 GN AW17 GN AW3 GND AW GND AW55 GND AW57 GND AW7 GND AW9S GND gt rw 0 lt oO gt lt oO lt oO lt oO 0 lt o September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 92 Appendix A Pin List Pin Number Buffer Type AY10 GND AY12 GND AY14 GND AY16 GN Y2 GN Y4 GN AY44 GN AY6 GND AY8 GND B10 GND B36 GND B40 GN 2 GN GN GN lt oO lt gt oO lt gt 0 lt oO lt oO lt UJ oO UO lt oO lt BB42 BB46 GND BB50 GND BB58 GND BC45 GND BC47 GND BC49 GND BC51 GND BC53 GND BC55 GND BC57 GND BD52 GND BD54 GND BD56 GND BE49 GND BE51 GND BF10 GND BF12 GND BF14 GND BF16 GND BF2 GND BF4 GND BF42 GND BF6 GND F GND BG11 GND BG13 GND BG15 GND BG17 GND G GND BG45 GND 0 ies UJ wo September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 93 Appendix A Pin List Pin Number Buffer Type BG47 GND BG GND BG7 GND BG9 GND BH58 GND BJ55 GND BJ57 GND BK42 GND BK46 GND BK48 GND BK50 GND BK52 GN BK54 GND BL45 GND BL49 GND BL57 GND BN43 GND BN57 GND BP12 GND BP14 GN P GN BP58 GN P6 GN BP8 GND BR GND BR11 GND BR13 GND BR15 GND R GN R5 GN BR53 GN BR55 GND BR57 GND BR7 GND BR9 GND BT10 GND BT16
45. ACTORS AND AFFILIATES AND THE DIRECTORS OFFICERS AND EMPLOYEES OF EACH HARMLESS AGAINST ALL CLAIMS COSTS DAMAGES AND EXPENSES AND REASONABLE ATTORNEYS FEES ARISING OUT OF DIRECTLY OR INDIRECTLY ANY CLAIM OF PRODUCT LIABILITY PERSONAL INJURY OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN MANUFACTURE OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or go to http www intel com d
46. GND BT42 GN BT46 GN BT48 GND BT50 GND BT52 GND BT54 GND BT56 GND BUS GND lt oO lt oO lt oO qp lt UJ UJ w W W Co 0 lt oO D p September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 94 Appendix A Pin List Pin Number Buffer Type BU45 GND BU47 GND BU5 GND GN GN GN GN GND GND GND GND GN GN GN GN GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ojojoj ojojoj September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 95 Appendix A Pin List Pin Number Buffer Type CB40 GND CB42 GND CB44 GND CB46 GN CB48 GN CB50 GN CB52 GN CB54 GND CB56 GND CC11 GND CC GND CC33 GN CC43 GN CC45 GN CC47 GN CC49 GND CC GND CC7 GND CC GND CD12 GND CD GND CD40 GND CD GND CD8 GND CE15 GND CE33 GND CE43 GND CE45 GND CE7 GND CF10 GND CF12 GND CF28 GND CF32 GND CG27 GND CG29 GND CG31 GND CG33 GND CG35 GND CG37 GND CG39 GND CG43 GND CG45 GND CG5 GND CG53 GND CG7 GND lt oO E ojog lt 0 lt oO ojo lt O c1 c o vss cp co September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet
47. IG Gm n7 KIS F18 JO A Po September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 73 Appendix A Pin List Pin Name Pin Number Buffer Type D12 SSTL E13 SSTL En SSTL 15 SSTL CMOS PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX CMOS CMOS CMOS Open Drain Open Drain Open Drain CMOS CMOS Open Drain Open Drain CMOS ODCMOS ODCMOS PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 DMI_TX_DP 1 DMI_TX_DP 2 F40 B50 C49 B48 C47 D50 E49 D48 E47 C45 B44 C43 B42 E45 D44 E43 D42 29 Y48 P36 H52 B46 D46 51 D52 D54 E55 E51 F52 F54 G55 H42 J43 H44 DMI TX DP 3 DRAM PWR OK C01 CH16 DRAM PWR OK C23 W EAR_N CE53 ERROR_N 0 BD50 ERROR N 1 BB48 ERROR_N 2 BB52 FIVR_FAULT CY40 FRMAGENT MEM HOT C01 N CL33 MEM HOT C23 N MSMI N Ix PE HP SCL PE HP SDA C September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 74 Appendix A Pin List Pin Number Buffer Type PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3
48. Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families n te 1 1 1 Structure and Scope The following table summarizes the structure and scope of each volume of the processor Datasheet Table 1 Structure of the Processor Datasheet Volume One Electrical Datasheet e Introduction e Electrical Specifications e Processor Land Listing e Processor Signal Descriptions Volume Two Register Information e Configuration Process and Registers Overview e Configuration Space Registers CSR Model Specific Registers MSR 1 1 2 Related Publications Refer to the following documents for additional information Table 2 Public Publications Document Document Number Location Advanced Configuration and Power Interface Specification 4 0 http www acpi info PCI Local Bus Specification 3 0 http www pcisig com PCI Express Base Specification Revision 3 0 http www pcisig com PCI Express Base Specification Revision 2 1 PCI Express Base Specification Revision 1 1 PCIe Gen 3 Connector High Speed Electrical Test Procedure 325028 001 http www intel com content www us en io pci express pci express architecture devnet resources html Connector Model Quality Assessment Methodology 326123 002 http www intel com content www us en architecture and technology intel connector model paper html DDR4 SDRAM Specification and Register Specifica
49. Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 22 September 2014 Order No 330783 001 Electrical Specifications Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Table 6 intel Signal Description Buffer Types Signal Description Analog Asynchronous Analog reference or output May be used as a threshold voltage or for buffer compensation Signal has no timing relationship with any system reference clock CMOS CMOS buffers 1 05V DDR4 buffers 1 2V DMI2 Intel QPI Direct Media Interface Gen 2 signals These signals are compatible with PCI Express 2 0 and 1 0 Signaling Environment AC Specifications Current mode 9 6 GT s 8 0 GT s and 6 4 GT s forwarded clock Intel QuickPath Interconnect signaling Open Drain CMOS Open Drain CMOS ODCMOS buffers 1 05V tolerant PCI Express PCI Express interface signals These signals are compatible with PCI Express 3 0 Signaling Environment AC Specifications and are AC coupled The buffers are not 3 3 V tolerant Refer to the PCIe specification Reference SSTL Voltage reference signal Source Series Terminated Logic JEDEC SSTL_15 Note Table 7 Signal Groups 1 Qualifier for a buffer type Differential Single Ended Buffer Type Signal DDR4 Reference Clocks Differential SSTL Output DDR 0 1 2 3 _CLK_D N P 3 0
50. Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet September 2014 Order No 330783 001 intel By using this document in addition to any agreements you have with Intel you accept the terms set forth below You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein You agree to grant Intel a non exclusive royalty free license to any patent claim thereafter drafted which includes subject matter disclosed herein INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT A Mission Critical Application is any application in which failure of the Intel Product could result directly or indirectly in personal injury or death SHOULD YOU PURCHASE OR USE INTEL S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES SUBCONTR
51. J49 BP48 BRAT BG53 BGS5 BHS BHS4 BH50 BFS8 QPIO DRX DN O BG51 September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 78 Appendix A Pin List Pin Name Pin Number Buffer Type BG57 BP56 BJ51 BHS2 BLSS BM54 BLS BM52 BNS BM50 BNA BG4S BM4S BNA7 BESS BESS BFS6 BFS4 BFSO BDS BES BM56 BW49 BWS CF46 BY52 CAT CaaS OG47 OF 4s CF50 CF52 CG5 CG4 BWS BY54 BWS5 BV58 BWA7 BW57 BYS6 BAS BV50 BV52 CD46 September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 79 Appendix A Pin List Pin Name Pin Number Buffer Type CASI BY48 BYSO CE47 CDAS CD50 CD52 CE5 CE4 BUSS BV54 BUSS BTS8 BVAS BUS BV56 BVA6 CLsg C169 CY54 DB54 oMad CRSS CTS6 CRS7 CPS8 CK56 CLSS CF54 CF56 CESS CM46 CNa7 owas CNAS QPI1_DRX_DN 10 CT54 CMS CNS Cvs cuss CKaa CLas OPS CUSS QPI DRX DNI CN45 September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 80 Appendix A Pin List Pin Name Pin Number Buffer Type CV56 CUS CT58 CMS6 C55 CD54 CD56 COSS CK46 CL CKS CLaS CK50 OLS CTS2 R53 DE DB42 DD48 owas DCAS DD50 owa7 D051 D052 ova cvas ovas ows DEA DB44 ova DEAS DB46 owas DEA
52. K 0 1 DN The processor Core processor Uncore Intel QuickPath Interconnect link PCI Express and DDR4 memory interface frequencies are generated from BCLK 0 1 DP and BCLK 0 1 DN signals There is no direct link between core frequency and Intel QuickPath Interconnect link frequency e g no core frequency to Intel QuickPath Interconnect multiplier The processor maximum core frequency Intel QuickPath Interconnect link frequency and DDR memory frequency are set during manufacturing It is possible to override the processor core frequency setting using software see the Intel 64 and IA 32 Architectures Software Developer s Manuals This permits operation at lower core frequencies than the factory set maximum core frequency The processor core frequency is configured during reset by using values stored within the device during manufacturing The stored value sets the lowest core multiplier at which the particular processor can operate If higher speeds are desired the appropriate ratio can be configured via the IA32 PERF CTL MSR MSR 199h Bits 15 0 For details of operation at core frequencies lower than the maximum rated processor speed refer to the Intel 64 and IA 32 Architectures Software Developer s Manuals Clock multiplying within the processor is provided by the internal phase locked loop PLL which requires a constant frequency BCLK 0 1 _DP BCLK 0 1 DN input with exceptions for spread spectrum clocking DC specifi
53. O ol N lt on Qe Q O oe c lt op N d Q w lt 02 es o1 Q UO lt n Q oO NOBLES on lt lt P lt N Q iw n oO lt n N Oo e 0 lt no co UO C2 N lt io RB C2 o lt no qm oi o e UO September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 103
54. Order No 330783 001 59 Appendix A Pin List Pin Name Pin Number Buffer Type 0625 SSTL oK22 SSTL H24 SSTL H26 SSTL CD26 SSTL CK24 SSTL CK26 SSTL BU7 SSTL BT SSTL BWI SSTL Bia SSTL BTI SSTL BUIS SSTL OAT SSTL BY12 SSTL CES SSTL CF8 SSTL CKi0 SSTL can SSTL CAO SSTL CD10 SSTL CET SSTL cke SSTL CJ SSTL CES SSTL CGI5 SSTL CM SSTL CHi4 SSTL ccs SSTL CD14 SSTL CBS SSTL SE SSTL CLIS SSTL CKe8 SSTL che SSTL CK32 SSTL H32 SSTL VET Ser C127 SSTL cus SSTL cus SSTL BTS SSTL CD28 SSTL CB28 SSTL CD32 SSTL I XIXIXxIXx Ix September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 60 Appendix A Pin List Pin Name Pin Number Buffer Type B32 Ser CEe7 SSTL CCa7 SSTL OES SSTL CCS SSTL CESS SSTL C635 SSTL BUS SSTL CES SSTL 0030 SSTL CF34 SSTL D34 SSTL CF38 SSTL CD38 SSTL CLa5 SSTL 185 SSTL C39 SSTL C139 SSTL CAT SSTL C SSTL Kad SSTL CMe SSTL Ckoe SSTL CB6 SSTL BTI2 SSTL BUT SSTL BV SSTL BWI SSTL Bia SSTL Hs SSTL CF14 SSTL C9 SSTL CC29 SSTL CD36 SSTL CK36 SSTL ows SSTL cor SSTL NIE SSTL CM30 SSTL CF30 SSTL CES SSTL cus SSTL CTI SSTL BWO SSTL BYE SSTL TISI XIF IIIEIEIEI September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 61 Appendix A Pin List PinName P
55. Order No 330783 001 96 Appendix A Pin List Pin Number Buffer Type GND GND GND GN GN GN GN GND GND GND GND GN GN GN GN GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND O Uj UOJ UO U o O UO September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 97 Appendix A Pin List Pin Number Buffer Type GND GND GND GN GN GN GN GND GND GND GND GN GN GN GN GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND U o UO UO O U UOJ O September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 98 Appendix A Pin List Pin Number Buffer Type CW1 GND CW15 GND CW27 GND CW29 GN CW31 GN CW33 GN CW35 GN CW37 GND CW39 GND CW GND CW53 GND CW55 GN CW57 GN W GN CY10 GN CY12 GND CY2 GND CY30 GND CY34 GND CY36 GND CY38 GND CY4 GND CY42 GND CY44 GND CY46 GND CY48 GND CY50 GND CY52 GND CY8 GND D10 GND 24 GND D36 GND D4 GND D40 GND DA27 GND DAS GND DA35 GND DA41 GND DA43 GND DA45 GND DA47 GND DA49 GND DA51 GND DA53 GND DA55 GND lt oO lt oO lt 0 lt oO c1 lt oO oO lt O N 0 lt 0
56. PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 Fin name W ANAS AMEO ANS AME2 ARAS APSO ARS AP52 AB54 ABSG ACES AEST ADEA ADEE AESS AF58 J45 K42 L43 K44 L45 J53 K54 J57 K56 L53 M54 L57 M56 H46 J47 H48 J49 K46 L47 K48 L49 L55 T54 T56 U55 N55 V54 V56 55 PE2A RX DN I September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 75 Appendix A Pin List Pin Name Pin Number Buffer Type AGES PCIEXG AHA PCIEXG ANES PCIEXG AP54 PCIEXG AJ53 PCIEX3 AKA PCIEXG ARES PCIEXG AT54 PCIEXG AJ57 PCIEXG ARS PCIEXG AHSG PCIEXG AKSB PCIEXG ALS PCIEXS AUST PCIEXG AKS6 PCIEXS PE2C TX DN 10 AY54 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PE2C_RX_DP 9 AM58 PCIEX3 PE2C TX DN 11 AW51 PE2C TX DN 8 AV52 PE2C TX DN 9 AW53 BB54 BAS AYS2 BASS ATSG APSE AYSS AYS AVE ATS6 BAST BB56 AV50 AW49 AVA8 AWAT AYSO BAAS AY48 BAAT AF44 AGAS AF46 AAAS AAA September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 76 Appendix A Pin List Pin Name Pin N
57. R2 BG 0 AA21 AD20 TE Ra uei T22 2 2 2 September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 66 Appendix A Pin List PinName PinNumber BufferType DDR2 CKE 3 Y22 SSTL 20 AB22 SSTL AD22 SSTL wir SSTL Y SSTL vis SSTL wig SSTL AAT SSTL AB20 SSTL ABE AAI ABIG T16 Wi AALS P16 Uis SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL ACIS ADI6 ADIS T12 AD38 AAGT V T U T W DDR2 DQ 16 AD34 DDR2 DQ 17 AB34 DDR2 DQ 18 AD30 DDR2 DQ 19 AB30 DDR2 DQ 2 DDR2 DQ 20 AC35 DDR2 DQ 21 AA35 AESI ACSI T Y U U 3 R 3 R R R V 2 Set O O 30 0 35 35 2 31 37 27 27 23 23 28 8 38 September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 67 Appendix A Pin List Pin Number Buffer Type V SSTL T SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL QIZSIZ AEST DDR2 DQ 41 W11 DDR2 DQ 42 AA11 DDR2 DQ
58. Table 27 4 6 Table 28 Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Signal Descriptions DMI2 PCI Express Port 0 Signals DMI2 and PCI Express Port 0 Signals Signal Name Description DMI_RX_DN 3 0 DMI_RX_DP 3 0 DMI_TX_DP 3 0 DMI_TX_DN 3 0 DMI2 Receive Data Input DMI2 Transmit Data Output Intel QuickPath Interconnect Signals Intel QPI Port 0 and 1 Signals Signal Name Description QPI 0 1 _CLKRX_DN DP Reference Clock Differential Input These pins provide the PLL reference clock differential input 100 MHz typical QPI40 1 CLKTX DN DP Reference Clock Differential Output These pins provide the PLL reference clock differential input 100 MHz typical QPI 0 1 _DRX_DN DP 19 0 QPI Receive data input QPI 0 1 _DTX_DN DP 19 0 QPI Transmit data output PECI Signal PECI Signal Signal Name Description PECI PECI Platform Environment Control Interface is the serial sideband interface to the processor and is used primarily for thermal power and error management System Reference Clock Signals System Reference Clock BCLK 0 1 Signals Signal Name BCLK 0 1 _D N P Description Reference Clock Differential input These pins provide the required reference inputs to various PLLs inside the processor such as Inte
59. Tease shown in the Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Thermal Mechanical Specification and Design Guide TMSDG Icctn_max is specified at the relative Vcc wax point on the Vccry load line The processor is capable of drawing Iccry wax for up to 4 ms This specification represents the Vcciy reduction or Vcciy increase due to each VID transition For Voltage Identification VID see Voltage Identification VID on page 17 AC timing requirements for VID transitions are included in Figure 3 on page 32 Baseboard bandwidth is limited to 20 MHz FMB is the flexible motherboard guidelines See Flexible Motherboard Guidelines FMB on page 29 for details DC AC Ripple Total Tolerance vias close to the socket and measure with a DC to 100MHz bandwidth oscilloscope limit or DC to 20 MHz for older model oscilloscopes using 1 5 pF maximum probe capacitance and 1M ohm minimum impedance The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe September 2014 Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet Order No 330783 001 31 intel Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Electrical Specifications Figure 3 Serial VID Interface SVID Signals Clock Timings
60. aes ni Intel Active Management Technology Intel AMT requires activation and a system with a corporate network connection an Intel AMT enabled chipset network hardware and software For notebooks Intel AMT may be unavailable or limited over a host OS based VPN when connecting wirelessly on battery power sleeping hibernating or powered off Results dependent upon hardware setup and configuration For more information visit http www intel com content www us en architecture and technology intel active management technology html No computer system can provide absolute security under all conditions Intel Trusted Execution Technology Intel TXT requires a computer with Intel Virtualization Technology an Intel TXT enabled processor chipset BIOS Authenticated Code Modules and an Intel TXT compatible measured aunched environment MLE Intel TXT also requires the system to contain a TPM vi s For more information visit http www intel com technology security Requires a system with Intel Turbo Boost Technology Intel Turbo Boost Technology and Intel Turbo Boost Technology 2 0 are only available on select ntel processors Consult your PC manufacturer Performance varies depending on hardware software and system configuration For more information visit https www ssl intel com content www us en architecture and technology turbo boost turbo boost technology html Basis BlueMoon BunnyPeople Celeron Centrino Cilk Flexpipe In
61. ail will supply the integrated voltage regulators which in turn will regulate to the appropriate voltages for the cores cache and system agents This integration allows the processor to better control on die voltages to optimize for both performance and power savings The processor Vcc rail will remain a sVID based voltage with a loadline similar to the core voltage rail called Vcc in previous processors Processor Signaling The Intel Xeon processor E5 1600 and E5 2600 v3 product families includes 2011 lands which utilize various signaling technologies Signals are grouped by electrical characteristics and buffer type into various signal groups These include DDR4 Reference Clock Command Control and Data PCI Express DMI2 Intel QuickPath Interconnect Platform Environmental Control Interface PECI System Reference Clock SMBus JTAG and Test Access Port TAP SVID Interface Processor Asynchronous Sideband Miscellaneous and Power Other signals Refer to Table 7 on page 23 for details System Memory Interface Signal Groups The system memory interface utilizes DDR4 technology which consists of numerous signal groups These include Reference Clocks Command Signals Control Signals and Data Signals Each group consists of numerous signals which may utilize various signaling technologies Please refer to Table 7 on page 23 for further details Throughout this chapter the system memory interface may be referred to as DDR4
62. atasheet Order No 330783 001 86 Appendix A Pin List Finnie rin tober suerte PWR va PWR PWR BAT PWR BATS W BATS W BAIT W PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR v v pu pu v pu September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 87 Appendix A Pin List piaumber aeternae PWR PWR PWR PWR W W W PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR VCCIN v v pu pu v D September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 88 Appendix A Pin List tame a ser PWR a PWR SNE PWR BNIS PWR BNI7 W W W PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND v v pu pu v pu September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 89 Appendix A Pin List Pin Number Buffer Type AA55 GND AA7 GND AB12
63. ated THERMTRIP_N remains latched until RESET_N is asserted While the assertion of the RESET_N signal may de assert THERMTRIP_N if the processor s junction temperature remains at or above the trip level THERMTRIP_N will again be asserted after RESET_N is de asserted This signal can also be asserted if the system memory interface has exceeded a critical temperature limit set by BIOS Table 32 Miscellaneous Signals Signal Name Description BIST_ENABLE BIST Enable Strap Input which allows the platform to enable or disable built in self test BIST on the processor This signal is pulled up on the die Rrefer to Table 8 on page 26 for details BMCINIT BMC Initialization Strap Indicates whether Service Processor Boot Mode should be used Used in combination with FRMAGENT and SOCKET_ID inputs 0 Service Processor Boot Mode Disabled Example boot modes Local PCH this processor hosts a legacy PCH with firmware behind it Intel QPI Link Boot for processors one hop away from the FW agent or Intel QPI Link Init for processors more than one hop away from the firmware agent e 1 Service Processor Boot Mode Enabled In this mode of operation the processor performs the absolute minimum internal configuration and then waits for the Service Processor to complete its initialization The socket boots after receiving a GO handshake signal via a firmware scratchpad register continued Intel Xeon P
64. ator can operate with all supported frequencies Individual processor VID values may be calibrated during manufacturing such that two processor units with the same core frequency may have different default VID settings Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet Order No 330783 001 17 m 1 n tel Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Electrical Specifications The processor uses voltage identification signals to support automatic selection of Vccin power supply voltage If the processor socket is empty SKTOCC N high or a not supported response is received from the SVID bus then the voltage regulation circuit cannot supply the voltage that is requested the voltage regulator must disable itself or not power on Vout MAX register 30h is programmed by the processor to set the maximum supported VID code and if the programmed VID code is higher than the VID supported by the VR then VR will respond with a not supported acknowledgment SVID Commands The processor provides the ability to operate while transitioning to a new VID setting and its associated processor voltage rail Vccin This is represented by a DC shift It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target voltage Transitions above the maximum specified VID are not supported The processor s
65. cadere edges n NR RR WA ECEE FEN DEeE NEUE S 55 33 Power and Ground Signals enne xh bees puce enun dined ax aeta bec Drac Taser un Rr a DOR CK RN iE 57 Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical September 2014 Datasheet Order No 330783 001 7 m 1 n tel Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Introduction Note 1 1 Introduction The Datasheet provides descriptions of the Intel Xeon processor v3 product families registers and Electrical specifications including DC electrical specifications signal integrity and land and signal definitions This document is distributed as a part of the complete Datasheet consisting of two volumes Unless specified otherwise the term Intel Xeon processor v3 product families server processor or processor will represent the following processors throughout the rest of the document Features within this document may not be supported on all processor types and SKUs This document covers the following processors e Intel Xeon processor E5 1600 and E5 2600 v3 product families for Efficient Performance Server Workstation HPC Storage and Embedded The Intel Xeon processor v3 product families is the next generation of 64 bit multi core enterprise processor built on 22 nm process technology Based on the low power high performance processor microarchitecture the processor is designed for a platfo
66. cations Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families intel Segment Model Number TDP C1E W 2 c3 Ww C6 W Segment E5 2699 v3 145W 18 Core 56 36 14 Optimized E5 2698 v3 135W 16 Core 47 33 14 E5 2697 v3 145W 14 Core 45 34 14 E5 2695 v3 120W 14 Core 46 34 14 E5 2683 v3 120W 14 Core 55 38 20 Workstation E5 2687 v3 160W 10 Core 41 31 13 E5 1680 v3 140W 8 Core 34 25 12 E5 1660 v3 140W 8 Core 34 25 12 E5 1650 v3 140W 6 Core 30 22 12 E5 1630 v3 140W 4 Core 26 20 12 E5 1620 v3 140W 4 Core 26 20 12 Frequency E5 2667 v3 135W 8 Core 32 26 12 Optimized E5 2643 v3 135W 6 Core 32 26 12 E5 2637 v3 135W 4 Core 30 25 12 E5 2623 v3 105W 4 Core 33 26 12 Advanced E5 2690 v3 135W 12 Core 38 30 13 Server E5 2680 v3 120W 12 Core 44 33 13 E5 2670 v3 120W 12 Core 44 33 13 E5 2660 v3 105W 10 Core 38 30 13 E5 2650 v3 105W 10 Core 43 33 13 Standard E5 2640 v3 90W 8 Core 33 25 12 Server E5 2630 v3 85W 8 Core 34 26 12 E5 2620 v3 85W 6 Core 36 28 12 Basic E5 2609 v3 85W 6 Core 28 24 20 E5 2603 v3 85W 6 Core 28 24 13 Low Power E5 2650L v3 65W 12 Core 38 38 13 E5 2630L v3 55W 8 Core 27 23 13 Embedded E5 2663 v3 120W 10 Core 34 28 13 E5 2658 v3 105W 12 Core 39 30 13 E5 2628 v3 85W 8 Core 33 25 12 E5 2648L v3 75W 12 Core 36 28 13 E5 2628L v3 75W 10 Core 33 27 13 E5 2618L v3 75W 8 Core
67. cations for the BCLK 0 1 DP BCLK 0 1 DN inputs are provided in Processor Asynchronous Sideband DC Specifications on page 42 These specifications must be met while also meeting the associated signal quality specifications outlined in Signal Quality on page 44 JTAG and Test Access Port TAP Signals Due to the voltage levels supported by other components in the JTAG and Test Access Port TAP logic Intel recommends the processor be first in the TAP chain followed by any other components within the system Please refer to the Intel8Xeon9 Processor E5 1600 and E5 2600 v3 Product Family Boundary Scan Description Language BSDL file more details A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Two copies of each signal may be required with each driving a different voltage level Processor Sideband Signals The Intel Xeon processor E5 1600 and E5 2600 v3 product families includes asynchronous sideband signals that provide asynchronous input output or I O signals between the processor and the platform or Platform Controller Hub Details can be found in Table 7 on page 23 All Processor Asynchronous Sideband input signals are required to be asserted de asserted for a defined number of BCLKs in order for the processor to recognize the proper signal state these are outlined in Processor Asynchronous Sideband DC Specificati
68. ccp o1 and Vccp 23 will also be referred to as Vccp Note The processor must be provided Vccp o1 and Vccp 23 for proper operation even in configurations where no memory is populated A MBVR 12 0 or 12 5 controller is required Vss Processor ground return VcciOo IN IO voltage supply input Vecpect Power supply for PECI Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical September 2014 Order No 330783 001 Datasheet 57 Appendix A Pin List Appendix A Pin List September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 58 Appendix A Pin List Pin ame Pin Number Buffer Type ENT CMOS OLAT CMOS AWAS CMOS BAAS CMOS A3 CMOS AMAS CMOS BC43 ODCMOS BB44 ODCMOS BEAT ODCMOS BF46 ODCMOS BEAS ODCMOS BD46 ODCMOS BAG ODCMOS AWAS ODCMOS Cos ODCMOS D015 CMOS C23 CMOS OKA ODCMOS vad ODCMOS Y40 Ix ODCMOS ODCMOS SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL DDR SDA C23 DDRO ACT N CK16 CD16 cum CH20 CL CNI7 Cus CIT CET CF16 COT CNS CCI5 CE2 CF18 CF20 CETS A CD18 CD20 CCI9 CD23 H22 CF26 _ C23 N DDR_SDA_C01 CM42 September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet
69. cp is the generic term for Vccp 01 and Vccp 23 Vccio IN 1 IO voltage supply input Vccpeci 1 Power supply for PECI Vss 631 Ground Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the Intel Xeon processor E5 1600 and E5 2600 v3 product families is capable of generating large current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Large electrolytic bulk capacitors CBULK help maintain the output voltage during current transients for example coming out of an idle condition Care must be taken in the baseboard design to ensure that the voltages provided to the processor remain within the specifications listed in Table 13 on page 31 Failure to do so can result in timing violations or reduced lifetime of the processor Voltage Identification VID The reference voltage or the VID setting is set via the SVID communication bus between the processor and the voltage regulator controller chip The VID settings are the nominal voltages to be delivered to the processor s Vcciy lands Table 5 on page 21 specifies the reference voltage level corresponding to the VID value transmitted over serial VID The VID codes will change due to temperature and or current load changes in order to minimize the power and to maximize the performance of the part The specifications are set so that a voltage regul
70. d is preemptive the VR interrupts its current processes and moves to the new VID This is the instruction used for normal P state voltage change This command is used in the processor for the Intel Enhanced SpeedStep Technology transitions Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet September 2014 18 Order No 330783 001 m Electrical Specifications Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families n tel SetVID Decay The SetVID Decay command is the slowest of the DVID transitions It is normally used for VID down transitions The VR does not control the slew rate the output voltage declines with the output load current only The SetVID Decay command is preemptive the VR interrupts its current processes and moves to the new VID This command is used in the processor for package C6 entry allowing capacitor discharge by the leakage thus saving energy This command is normally used in VID down direction in the processor package C6 entry SVID Power State Functions SetPS The processor has three power state functions and these will be set seamlessly via the SVID bus using the SetPS command Based on the power state command the SetPS commands sends information to VR controller to configure the VR to improve efficiency especially at light loads For example typical power states are e PSO 00h Represents full power or active mode e PS1 01h Represents a
71. dershoot specifications limit transitions beyond VCCD or VSS due to the fast signal edge rates The processor can be damaged by single and or repeated overshoot or undershoot events on any input output or I O buffer if the charge is large enough i e if the over undershoot is great enough Baseboard designs which meet signal integrity and timing requirements and which do not exceed the maximum overshoot or undershoot limits listed in the following table will insure reliable IO performance for the lifetime of the processor Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 44 September 2014 Order No 330783 001 Electrical Specifications Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Table 17 Figure 10 September 2014 Processor I O Overshoot Undershoot Specifications Notes 1 These specifications are measured at the processor pad 2 Refer to Figure 11 on page 46 for description of allowable Overshoot Undershoot magnitude and duration 3 Tcp is the minimum high pulse width duration 4 For PWRGOOD DC specifications see Processor Asynchronous Sideband DC Specifications on page 42 and Figure 10 on page 45 Signal Group Maximum Maximum Overshoot Undershoot Notes Undershoot Overshoot Duration Duration Intel QuickPath 0 2 Vccio IN 1 2 Vccio IN 39 ps 15 ps 1 2 Interconnect DDR4 0 22 Vccp 1 22 Vccp 0 25 Tcy 0 1 TcH
72. dity 60 24 9C for a sustained period of time Timesustained storage A prolonged or extended period of time 0 30 months typically associated with sustained storage conditions Unopened bag includes 6 months storage time by customer Timeshort term storage A short period of time in shipping media 0 72 hours Note 1 Storage conditions are applicable to storage environments only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation please refer to the processor case temperature specifications 2 These ratings apply to the Intel component and do not include the tray or packaging Failure to adhere to this specification can affect the long term reliability of the processor 4 Non operating storage limits post board attach Storage condition limits for the component once attached to the application board are not specified Intel does not conduct component level certification assessments post board attach given the multitude of attach methods socket types and board types used by customers Provided as general guidance only Intel board products are specified and certified to meet the following temperature and humidity limits Non Operating Temperature Limit 40C to 70C amp Humidity 50 to 90 non condensing with a maximum wet bulb of 28 C 5 Device
73. e used for the voltage regulator thermal assessment The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion 4 Minimum VCCIN and maximum ICCIN are specified at the maximum processor case temperature TCASE ICCIN MAX is specified at the relative VCCIN MAX point on the VCCIN load line The processor is capable of drawing ICCIN MAX for up to 4 ms 5 The numbers in parentheses are due to a memory initialization load pulse occurring at system boot that may last up to 5s a gt gt gt In In gt gt gt In in c c E E e i i g e e i i g e lt E E E z z 4 z z 8 gt z 3 YF IE 3 B 5 g ie l A o 1 a lt lt 9 A a g o o s z z gt 2 9g t ET 2 E o g al a 9 i gt z 2 3 X S e N m gt F4 n a A 5 A 9 m o a x 9 x o o a v o g E x x g B B t n a o E S a 9 Fr a a E i k4 a a U z H ke S 9 Is 9 E J gt Jg Lj mM 85W 105 0 1 0 001 1 4 1 4 50 0 02 0 001 0 8 0 8 168 170 2 4 e Core 2 45 2 45 2 2 2 2 Basic 85W 105 0 1 0 001 1 4 1 4 50 0 02 0 001 0 8 0 8 168 170 2 4 e Core 2 45 2 45 2 2 2 2 Low 65W 83 0 1 0 001 1 4 1 4 40 0 02 0 001 0 8 0 8 127 130 2 4 Power 42 2 45 2 45 2 2 2 2 Core 55W 70 0 1 0 001 1 4 1 4 34 0 02 0 001 0 8 0 8 107 110 2 4 8 Core 2 45 2 45 2 2 2 2 Embed 120W 156 0 1 0 001 1 4 1 4 73 0 02 0 001 0 8 0 8 238 240 2 4 d
74. ected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits Although the processor contains protective circuitry to resist damage from Electro Static Discharge ESD precautions should always be taken to avoid high static voltages or electric fields Processor Absolute Minimum and Maximum Ratings Symbol Parameter Min Max Unit VccIN Processor input voltage with respect to Vss 0 3 1 98 V Vccp Processor IO supply voltage for DDR4 0 3 1 35 V standard voltage with respect to Vss VccIO IN IO voltage supply input with respect to Vss 0 3 1 35 V Vecpect Power supply for PECI with respect to Vss 0 3 1 35 V Note 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied continued Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet Order No 330783 001 29 intel Table 12 Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Electrical Specifications Symbol Parameter Min Max Unit 2 Overshoot and undershoot voltage guidelines for input output and I O signals are outlined in Overshoot Undershoot Tolerance on page 44 Excessive Overshoot or undershoot on any signa
75. ed 10 2 45 2 45 2 2 2 2 Core 105W 136 0 1 0 001 1 4 1 4 64 0 02 0 001 0 8 0 8 208 210 2 4 12 2 45 2 45 2 2 2 2 Core 85W 105 0 1 0 001 1 4 1 4 50 0 02 0 001 0 8 0 8 168 170 2 4 8 Cor 2 45 2 45 2 2 2 2 75W 97 0 1 0 001 1 4 1 4 46 0 02 0 001 0 8 0 8 149 150 2 4 12 2 45 2 45 2 2 2 2 Core 75W 97 0 1 0 001 1 4 1 4 46 0 02 0 001 0 8 0 8 149 150 2 4 10 2 45 2 45 2 2 2 2 Core 75W 97 0 1 0 001 1 4 1 4 46 0 02 0 001 0 8 0 8 149 150 2 4 e tore 2 45 2 45 2 2 2 2 52W 67 0 1 0 001 1 4 1 4 32 0 02 0 001 0 8 0 8 99 104 2 4 eCore 2 45 2 45 2 2 2 2 Note Table 15 Vcc n Static and Transient Tolerance Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Icciw A VcciN Max V VcciN Nom V VcciN Min V Notes 0 VID 0 022 VID 0 000 VID 0 022 10 VID 0 012 VID 0 011 VID 0 033 20 VID 0 001 VID 0 021 VID 0 043 30 VID 0 010 VID 0 032 VID 0 054 40 VID 0 020 VID 0 042 VID 0 064 continued September 2014 Order No 330783 001 Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 33 intel Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Electrical Specifications Icc n A Vcc n_max V VcciN Nom V VcciN Min V Notes 50 VID 0 031 VID 0 053 VID
76. el Xeon Processor E5 1600 and E5 2600 v3 Product Families Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Signal Descriptions Signal Name Description MEM HOT CO1 N MEM HOT C23 N e 0 Hardware correctable error no operating system or firmware action necessary e 1 Non fatal error operating system or firmware action required to contain and recover e 2 Fatal error system reset likely required to recover Memory throttle control Signals external BMC less controller that DIMM is exceeding temperature limit and needs to increase to max fan speed MEM HOT CO1 N and MEM HOT C23 N signals have two modes of operation input and output mode Input mode is externally asserted and is used to detect external events such as VR_HOT from the memory voltage regulator and causes the processor to throttle the appropriate memory channels Output mode is asserted by the processor known as level mode In level mode the output indicates that a particular branch of memory subsystem is hot MEM HOT CO1 N is used for memory channels 0 amp 1 while MEM HOT C23 N is used for memory channels 2 amp 3 MSMI N Machine Check Exception MCE is signaled via this pin when eMCA2 is enabled PMSYNC Power Management Sync A sideband signal to communicate power management status from the Platform Controller Hub PCH to the processor PROCHOT N PROCHOT N will go active when the processor temperature monitoring
77. eross abs Absolute Crossing Single Ended 0 250 0 550 V Figure 7 on page 2 4 7 9 Point 40 Figure 8 on page 40 continued Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 38 September 2014 Order No 330783 001 Electrical Specifications Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families intel 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 falling edge of BCLK 0 1 DP Vuavg is the statistical average of the VH measured by the oscilloscope The crossing point must meet the absolute and relative crossing point specifications simultaneously VHavg can be measured directly using Vtop on Agilent and High on Tektronix oscilloscopes Vcnoss is defined as the total variation of all crossing voltages as defined in Note 3 The rising edge of BCLK 0 1 DN is equal to the falling edge of BCLK 0 1 DP For Vin between 0 and Vih Specifications can be validated at the pin poo SEO Uo Ee CA Symbol Parameter Signal Min Max Unit Figure Notes Veross rel Relative Crossing Single Ended 0 250 0 5 VH 0 550 0 5 VH V Figure 7 on page 3 4 5 9 Point avg 0 700 avg 0 700 40 AVeross Range of Crossing Single Ended N A 0 140 V Figure 9 on page 6 9 Points 40 VTH Threshold Voltage Single Ended Vcross 0 1 Vcross 0 1 V 9 In Inpu
78. esign literature htm Any software source code reprinted in this document is furnished for informational purposes only and may only be used or copied and no license express or implied by estoppel or otherwise to any of the reprinted source code is granted by this document Any software source code reprinted in this document is furnished under a software license and may only be used or copied in accordance with the terms of that license Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families Go to http www intel com products processor number Intel Hyper Threading Technology Intel HT Technology is available on select Intel Core processors It requires an Intel HT Technology enabled system Consult your PC manufacturer Performance will vary depending on the specific hardware and software used Not available on Intel Core i5 750 For more information including details on which processors support Intel HT Technology visit http www intel com info hyperthreading Intel High Definition Audio Intel HD Audio requires an Intel HD Audio enabled system Consult your PC manufacturer for more information Sound quality will depend on equipment and actual implementation For more information about Intel HD Audio refer to http www intel com design chipsets hdaudio htm Intel 64 architecture requires a system with a 64 bit e
79. ference Clock BCLK 0 1 Differential CMOS 1 05V Input BCLK 0 1 _D N P JTAG amp TAP Signals Single ended CMOS 1 05V Input TCK TDI TMS TRST_N CMOS 1 05V Input Output PREQ_N CMOS1 05V Output PRDY_N Open Drain CMOS Input Output BPM_N 7 0 Open Drain CMOS Output TDO Serial VID Interface SVID Signals Single ended CMOS 1 05V Input SVIDALERT_N Open Drain CMOS Input Output SVIDDATA Open Drain CMOS Output SVIDCLK Processor Asynchronous Sideband Signals Single ended CMOS 1 05V Input BIST_ENABLE BMCINIT DEBUG_EN_N FRMAGENT PWRGOOD PMSYNC RESET_N SAFE_MODE_BOOT SOCKET_ID 1 0 TXT_AGENT TXT_PLTEN CMOS 1 05V Output FIVR_FAULT Open Drain CMOS Input Output CATERR_N MEM HOT CO1 N MEM HOT C23 N MSMI N PM FAST WAKE N PROCHOT N Open Drain CMOS Output ERROR N 2 0 THERMTRIP N Miscellaneous Signals continued Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical September 2014 Datasheet Order No 330783 001 25 intel Table 8 2 4 Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Electrical Specifications Differential Single Ended Buffer Type Signal CMOS 1 05V Input EAR N Output SKTOCC N Power Other Signals Power Ground Vecin Vccp 01 Vccp 23 Vccio IN Vecrect Vss Sense Points VCCIN_SENSE VSS_VCCIN_SENSE Note 1 Refer to Signa
80. ge 0 3 Vccro IN V 1 2 Signals MEM HOT CO01 23 N PROCHOT N Vin_opcmos Input High Voltage 0 7 Vccro TN V 1 2 VoL_opcmos Output Low Voltage 0 2 Vccio_IN V 1 2 Vuysteresis Hysteresis 0 1 Vccio_IN Signals MEM_HOT_C01 23_N PROCHOT_N Vuysteresis Hysteresis 0 05 Vccro iN Signal CATERR_N MSMI N PM FAST WAKE N IL Input Leakage Current 50 200 HA Ron Buffer On Resistance 4 14 Q 1 2 Output Edge Rate 0 05 0 60 V ns 3 Signal MEM_HOT_C 01 23 _ N ERROR N 2 0 THERMTRIP PROCHOT N Output Edge Rate 0 2 1 5 V ns 3 Signal CATERR_N MSMI_N PM_FAST_WAKE_N Note 1 This table applies to the processor sideband and miscellaneous signals specified in Table 7 on page 23 2 Unless otherwise noted all specifications in this table apply to all processor frequencies 3 These are measured between Vi and Vig 2 9 3 8 Miscellaneous Signals DC Specifications Symbol Parameter Min Nominal Max Units SKTOCC N Signal Vo ABS MAX Output Absolute Max Voltage 3 30 3 50 V Tomax Output Max Current 1 mA 2 10 Package C State Power Specifications Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Electrical Specifications The following table lists the processor package C state power specifications for the various processor SKUs Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 42 September 2014 Order No 330783 001 Electrical Specifi
81. gh Voltage 0 7 Vccio IN V Vuysteresis Hysteresis 0 1 Vccio_In V Vor Output Low Voltage 0 2 V cero iN V R on Buffer On Resistance 4 14 Q continued Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet September 2014 40 Order No 330783 001 Electrical Specifications Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families n te Symbol Parameter Min Max Units Notes IL Leakage Current Signals 50 200 HA Output Edge Rate 0 05 0 6 V ns 1 50 ohm to Vccro IN between Vit and Vin Note 1 Value obtained through test bench with 50Q pull up to Vecio_in 2 9 3 5 JTAG and TAP Signals DC Specifications Symbol Parameter Min Max Units Notes Vib Input Low Voltage 0 4 V cro iN V Vin Input High Voltage 0 8 V ccto_IN V Vit Input Low Voltage TCK 0 4 Vccro 1N V Vin Input High Voltage TCK 0 6 Vccro IN V VoL Output Low Voltage 0 2 V ccro IN V Vuysteresis Hysteresis O 1 Vccro IN RoN Buffer On Resistance Signals 4 14 Q BPM N 7 0 TDO In Input Leakage Current Signals 50 200 HA Output Edge Rate 0 2 1 5 V ns 1 50 ohm to Vccio_in Signal BPM N 7 0 PRDY N TDO Note 1 These are measured between Vj and Vi 2 The signal edge rate must be met or the signal must transition monotonically to the asserted state 2 9 3 6 Serial VID Interface SVID DC Specifications
82. gnal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation RESET_N Global reset signal Asserting the RESET_N signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents Note some PLL Intel QuickPath Interconnect and error states are not affected by reset and only PWRGOOD forces them to a known state THERMTRIP_N Assertion of THERMTRIP_N Thermal Trip indicates one of two possible critical over temperature conditions One the processor junction temperature has reached a level beyond which permanent silicon damage may occur and Two the system memory interface has exceeded a critical temperature limit set by BIOS Measurement of the processor junction temperature is accomplished through multiple internal thermal sensors that are monitored by the Digital Thermal Sensor DTS Simultaneously the Power Control Unit PCU monitors external memory temperatures via the dedicated SMBus interface to the DIMMs If any of the DIMMs exceed the BIOS defined limits the PCU will signal THERMTRIP_N to prevent damage to the DIMMs Once activated the processor will stop all execution and shut down all PLLs To further protect the processor its core voltage Vccin Vccp Vccrio 1N Vccpecr Supplies must be removed following the assertion of THERMTRIP_N Once activ
83. h to the system BIOS See the table below for a list of output tri state FRB signals Socket level FRB will tri state processor outputs via the PROCHOT_N signal Assertion of the PROCHOT_N signal through RESET N de assertion will tri state processor outputs Note that individual core disabling is also supported for those cases where disabling the entire package is not desired The Intel Xeon processor v3 product families extends the FRB capability to the core granularity by maintaining a register in the Uncore so that BIOS or another entity can disable one or more specific processor cores Fault Resilient Booting Output Tri State Signals Output Tri State Signal Groups Signals Intel QPI QPIO CLKTX DN 1 0 QPIO CLKTX DP 1 0 QPIO DTX DN 19 00 QPIO DTX DP 19 00 QPI1_CLKTX_DN 1 0 QPI1_CLKTX_DP 1 0 QPI1 DTX DN 19 00 continued Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Order No 330783 001 Datasheet 27 m 1 n te Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Electrical Specifications Output Tri State Signal Groups Signals QPI1_DTX_DP 19 00 PCI Express PE1A_TX_DN 3 0 PE1A_TX_DP 3 0 PE1B_TX_DN 7 4 PE1B_TX_DP 7 4 PE2A_TX_DN 3 0 PE2A_TX_DP 3 0 PE2B_TX_DN 7 4 PE2B_TX_DP 7 4 PE2C_TX_DN 11 8 PE2C_TX_DP 11 8 PE2D_TX_DN 15 12 PE2D TX DP 15 12 PE3A TX DN 3 0 PE3A TX DP 3 0 PE3B TX DN 7 4
84. inNumber BufferType DDRO DQS DP 1 BV12 SSTL DDRO DQS DP 10 BU13 SSTL DDRO DQS DP 11 SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL DDRO DQS DPT 12 CG13 DDRO DQS DPT 13 CL29 DDRO DQS DPT 14 CE29 DDRO DQS DPT 15 CF36 DDRO DQS DP 16 CM36 DDRO_DQS_DP 17 Ix DDRO DQS DP 2 CH10 DDRO DQS DP g CK14 DDRO DQGS DPI 4 CK30 DDRO DQS DP 5 CD30 DDRO DOGS DP 6 CC37 DDRO_DQS_DP 7 CJ37 DDRO_DQS_DP 8 CV10 Ix OW cun CP10 CR OP22 CG9 CU9 BV8 CT8 CV8 CP8 CN9 CRe CP24 CPi8 CRI CE23 Cue CE oL23 CD24 CT22 ONZ CP20 CLI9 CNI9 CHB Gu19 Cki8 CF22 CN25 September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 62 Appendix A Pin List Pin Name Pin Number Buffer Type Cue SSTL 0023 SSTL CF24 SSTL CEeS SSTL CK20 SSTL BY16 CTi6 CRIS CWa3 Vea Cvie CP16 CR25 DAT DC17 DD16 DFIG g O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL CYi6 DATS
85. ing Overshoot Undershoot Specification Tables The overshoot undershoot specification for the processor is not a simple single value Instead many factors are needed to determine the over undershoot specification In addition to the magnitude of the overshoot the following parameters must also be known the width of the overshoot and the activity factor AF To determine the allowed overshoot for a particular overshoot event the following must be done Determine the signal group a particular signal falls into 2 Determine the magnitude of the overshoot or the undershoot relative to VSS 3 Determine the activity factor How often does this overshoot occur 4 Next from the appropriate specification table determine the maximum pulse duration in nanoseconds allowed 5 Compare the specified maximum pulse duration to the signal being measured If the pulse duration measured is less than the pulse duration shown in the table then the signal meets the specifications Undershoot events must be analyzed separately from overshoot events as they are mutually exclusive Determining if a System Meets the Overshoot Undershoot Specifications The overshoot undershoot specifications listed in the table specify the allowable overshoot undershoot for a single overshoot undershoot event However most systems will have multiple overshoot and or undershoot events that each have their own set of parameters duration AF and magnitude While each o
86. l Descriptions for signal description details 2 DDR 0 1 2 3 refers to DDR4 Channel 0 DDR4 Channel 1 DDR4 Channel 2 and DDR4 Channel 3 Signals with On Die Weak PU PD Signal Name Pull Up Pull Down Rail Value Units BIST_ENABLE Pull Up VCCIO_IN 5K 15K Q BMCINIT Pull Down VSS 5K 15K Q DEBUG_EN_N Pull Up VCCIO_IN 5K 15K Q EAR_N Pull Up VCCIO_IN 5K 15K Q FRMAGENT Pull Down VSS 5K 15K Q PM FAST WAKE N Pull Up VCCIO IN 5K 15K Q PREQ N Pull Up VCCIO IN 5K 15K Q SAFE MODE BOOT Pull Down VSS 5K 15K Q SOCKET ID 1 0 Pull Down VSS 5K 15K Q TCK Pull Down VSS 5K 15K Q TDI Pull Up VCCIO_IN 5K 15K Q TMS Pull Up VCCIO IN 5K 15K Q TRST N Pull Up VCCIO IN 5K 15K Q TXT AGENT Pull Down VSS 5K 15K Q TXT PLTEN Pull Up VCCIO IN 5K 15K Q Power On Configuration POC Options Several configuration options can be configured by hardware The processor samples its hardware configuration at reset on the active to inactive transition of RESET N or upon assertion of PWRGOOD inactive to active transition For specifics on these options please refer to the table below The sampled information configures the processor for subsequent operation These configuration options cannot be changed except by another reset transition of the latching signal RESET N or PWRGOOD Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 26 September 2014
87. l QPI and PCIe BCLKO and BCLK1 run at 100MHz from the same clock source Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 52 September 2014 Order No 330783 001 Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Signal Descriptions Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families 4 7 Table 29 4 8 Table 30 4 9 Table 31 September 2014 intel JTAG and TAP Signals JTAG and TAP Signals Signal Name Description BPM N 7 0 Breakpoint and Performance Monitor Signals I O signals from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance These are 100 MHz signals PRDY N Probe Mode Ready is a processor output used by debug tools to determine processor debug readiness PREQ N Probe Mode Request is used by debug tools to request debug operation of the processor TCK TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for JTAG specification support TDO TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for JTAG specification support TMS TMS Test Mode Select is a JTAG specification support signal used by deb
88. l will likely result in permanent damage to the processor Storage Conditions Specifications Environmental storage condition limits define the temperature and relative humidity limits to which the device is exposed to while being stored in a Moisture Barrier Bag The specified storage conditions are for component level prior to board attach see notes in the table below for post board attach limits The table below specifies absolute maximum and minimum storage temperature limits which represent the maximum or minimum device condition beyond which damage latent or otherwise may occur The table also specifies sustained storage temperature relative humidity and time duration limits These limits specify the maximum or minimum device storage conditions for a sustained period of time At conditions outside sustained limits but within absolute maximum and minimum ratings quality and reliability may be affected Storage Condition Ratings Symbol Parameter Min Max Unit Tabsolute storage The minimum maximum device storage 25 125 9c temperature beyond which damage latent or otherwise may occur when subjected to for any length of time Tsustained storage The minimum maximum device storage 5 40 C temperature for a sustained period of time Tshort term storage The ambient storage temperature in shipping 20 85 ec media for a short period of time RHsustained storage The maximum device storage relative humi
89. lt ii September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 99 Appendix A Pin List September 2014 Order No 330783 001 Pin Number Buffer Type DA9 GND DB12 GND DB34 GND DB40 GN DB58 GN B6 GN C GN DC53 GND DC55 GND DD10 GND DD12 GND DD34 GN DD38 GN DD40 GN GN GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND OjO ojojo ol 0 U o O UO m n T m Ph Co Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet 100 Appendix A Pin List Buffer Type 101 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 September 2014 Appendix A Pin List Buffer Type Direction 102 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 September 2014 Appendix A Pin List Pin Number Buffer Type V12 N S V36 N S V44 N VSS V46 GND VSS V48 GND VSS V50 GND VSS GND VSS GND S N S N S N S N VSS GND VSS GND VSS GND VSS GND VSS GND VSS GND VSS GND S N S N S N S N VSS GND VSS GND VSS GND VSS GND VSS GND VSS GND VSS N VSS VCCIN SENSE lt n lt n Q oO S Q oO lt n Q o
90. nabled processor chipset BIOS and software Performance will vary depending on the specific hardware and software you use Consult your PC manufacturer for more information For more information visit http www intel com content www us en architecture and technology microarchitecture intel 64 architecture general html Intel Virtualization Technology Intel VT requires a computer system with an enabled Intel processor BIOS and virtual machine monitor VMM Functionality performance or other benefits will vary depending on hardware and software configurations Software applications may not be compatible with all operating systems Consult your PC manufacturer For more information visit http www intel com go virtualization The original equipment manufacturer must provide TPM functionality which requires a TPM supported BIOS TPM functionality must be initialized and may not be available in all countries For Enhanced Intel SpeedStep Technology see the Processor Spec Finder at http ark intel com or contact your Intel representative for more information Intel AES NI requires a computer system with an AES NI enabled processor as well as non Intel software to execute the instructions in the correct sequence AES NI is available on select Intel processors For availability consult your reseller or system manufacturer For more information see http software intel com en us articles intel advanced encryption standard instructions
91. nd write requests to a piece of coherent memory ICU Instruction Cache Unit Part of the processor core architecture IFU Instruction Fetch Unit Part of the processor core continued Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 10 September 2014 Order No 330783 001 Introduction Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families intel Term Description IIO The Integrated I O Controller An I O controller that is integrated in the processor die IMC The Integrated Memory Controller A Memory Controller that is integrated in the processor die IQ Instruction Queue Part of the core architecture Intel ME Intel Management Engine Intel QuickData Technology Intel QuickData Technology is a platform solution designed to maximize the throughput of server data traffic across a broader range of configurations and server environments to achieve faster scalable and more reliable I O Intel QuickPath Interconnect Intel QPI A cache coherent link based Interconnect specification for Intel processors chipsets and I O bridge components Intel 64 Technology 64 bit memory extensions to the IA 32 architecture Further details on Intel 64 architecture and programming model can be found at http developer intel com technology intel64 Intel Turbo Boost Technology A feature that opportunistically
92. ng devices The processor contains a Digital Thermal Sensor DTS that reports a relative die temperature as an offset from Thermal Control Circuit TCC activation temperature Temperature sensors located throughout the die are implemented as analog to digital converters calibrated at the factory PECI provides an interface for external devices to read processor temperature perform processor manageability functions and manage processor interface tuning and diagnostics The PECI interface operates at a nominal voltage set by Vccpecr The set of DC electrical specifications shown in PECI DC Specifications on page 38 is used with devices normally operating from a Vccpeci interface supply Input Device Hysteresis The PECI client and host input buffers must use a Schmitt triggered input design for improved noise immunity Please refer to the following image and PECI DC Specifications on page 38 Input Device Hysteresis Vccredi a Maximum Ve 7 PECI High Range Minimum Ve Minimum Valid Input Hysteresis Signal Range Maximum VN Minimum Wn SS PECI Low Range PECI Ground N Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet Order No 330783 001 15 m n tel Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Electrical Specifications 2 2 6 2 2 7 2 2 8 System Reference Clocks BCLK 0 1 DP BCL
93. nsmit Data Output PE2C TX DN 11 8 PE2C TX DP 11 8 PE2D TX DN 15 12 PE2D TX DP 15 12 PCIe Transmit Data Output PCIe Transmit Data Output PCI Express Port 3 Signals Signal Name Description PE3A_RX_DN 3 0 PE3A_RX_DP 3 0 PCIe Receive Data Input PE3B_RX_DN 7 4 PE3B_RX_DP 7 4 PCIe Receive Data Input PE3C_RX_DN 11 8 PE3C_RX_DP 11 8 PCIe Receive Data Input PE3D RX DN 15 12 PE3D RX DP 15 12 PCIe Receive Data Input PE3A TX DN 3 0 PE3A TX DP 3 0 PCIe Transmit Data Output PE3B TX DN 7 4 PE3B TX DP 7 4 PCIe Transmit Data Output PE3C TX DN 11 8 PE3C TX DP 11 8 PCIe Transmit Data Output PE3D TX DN 15 12 PE3D TX DP 15 12 PCIe Transmit Data Output PCI Express Miscellaneous Signals Signal Name Description PE HP SCL PCI Express Hot Plug SMBus Clock Provides PCI Express hot plug support via a dedicated SMBus interface Requires an external general purpose input output GPIO expansion device on the platform PE HP SDA PCI Express Hot Plug SMBus Data Provides PCI Express hot plug support via a dedicated SMBus interface Requires an external general purpose input output GPIO expansion device on the platform Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet Order No 330783 001 51 intel 4 3 Table 25 4 4 Table 26 4 5
94. nstalled in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor landings should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air that is unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material TAC Thermal Averaging Constant TDP Thermal Design Power continued Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 12 September 2014 Order No 330783 001 Introduction Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families n te Term Description TSOD Temperature Sensor On DIMM UDIMM Unbuffered Dual In line Memory Module Uncore The portion of the processor comprising the shared LLC cache Cbo IMC HA PCU Ubox IIO and Intel QPI link interface Unit Interval Signaling convention that is binary and unidirectional In this binary signaling one bit is sent for every edge of the forwarded clock whether it be a rising edge or a falling edge If a number of edges are collected at instancest 1 t2 t t then the UI at instance n is defined as UI n tn t n 1 VccIN Primary voltage input to the voltage regulato
95. ntel TXT enabled All sockets should be set to one In a non Scalable DP platform this is the default When this is set Intel TXT functionality requires user to explicitly enable Intel TXT via BIOS setup This signal is pulled up on the die refer to Table 8 on page 26 for details 4 10 Processor Power and Ground Supplies Table 33 Power and Ground Signals Signal Name Description VcciN VccIN SENSE Vss vcCCIN SENSE Input to the Integrated Voltage Regulator IVR for the processor cores lowest level caches LLC ring interface PLL IO and home agent It is provided by a VR 12 5 compliant motherboard voltage regulator MBVR for each CPU socket The output voltage of this MBVR is controlled by the processor using the serial voltage ID SVID bus VccIN SENSE and Vss vCCIN SENSE are remote sense signals for VcciN MBVR12 5 and are used by the voltage regulator to ensure accurate voltage regulation These signals must be connected to the voltage regulator feedback circuit which ensures the output voltage remains within specification Vccp 01 Fixed 1 2V power supply for the processor system memory interface Vccp 23 Provided by two MBVR 12 0 or 12 5 compliant regulators per CPU socket g Vccp 01 and Vccp 23 are used for memory channels 0 amp 1 and 2 amp 3 respectively The valid voltage of this supply 1 20V is configured by BIOS after determining the operating voltages of the installed memory V
96. ons on page 42 DC specifications Refer to Signal Quality on page 44 for applicable signal integrity specifications Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 16 September 2014 Order No 330783 001 m Electrical Specifications Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families n te 2 2 9 Table 3 September 2014 Power Ground and Sense Signals Processors also include various other signals including power ground and sense points Details can be found in Table 7 on page 23 Power and Ground Lands All Vccp Vecin and Vecio_in and Vccpgci lands must be connected to their respective processor power planes while all Vss lands must be connected to the system ground plane For clean on chip power distribution processors include lands for all required voltage supplies These are listed in the following table Power and Ground Lands Power and Number of Lands Comments Ground Lands VccIN 173 Each Vcciy land must be supplied with the voltage determined by the SVID Bus signals Table 5 on page 21 defines the voltage level associated with each core SVID pattern Table 15 on page 33 and Figure 4 on page 35 represent Vcciy static and transient limits Vccb 01 56 Each Vccp land is connected to a switchable 1 20 V supply Vccp 23 provide power to the processor DDRA interface i Vccp is also controlled by the SVID Bus Vc
97. rm consisting of a processor and the Platform Controller Hub PCH Note Some processor features are not available on all platform segments processor types and processor SKUs The processor supports up to 46 bits of physical address space and 48 bit of virtual address space e The Intel Xeon processor E5 1600 and E5 2600 v3 product families features per socket two Intel QuickPath Interconnect point to point links capable of up to 9 6 GT s up to 40 lanes of PCI Express 3 0 links capable of 8 0 GT s and 4 lanes of DMI2 PCI Express 2 0 It features 2 IMCs Integrated Memory Controller which support DDR4 DIMMs Included in this family of processors is an integrated memory controller IMC and an integrated I O IIO on a single silicon die This single die solution is known as a monolithic processor For supported processor configurations refer to e Intel 64 and IA 32 Architectures Software Developer s Manuals Electrical Datasheet Introduction This is volume one Vol 1 of the processor Datasheet which provides DC electrical specifications signal integrity differential signaling specifications and land and signal definitions of the processor Additionally this document may be used by system test engineers board designers and BIOS developers Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 8 September 2014 Order No 330783 001 m Introduction
98. rocessor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical September 2014 Order No 330783 001 Datasheet 55 intel Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Signal Descriptions Signal Name Description This signal is pulled down on the die refer to Table 8 on page 26 for details EAR N External Alignment of Reset used to bring the processor up into a deterministic state This signal is pulled up on the die refer to Table 8 on page 26 for details FIVR_FAULT Indicates an internal error has occurred with the integrated voltage regulator The FIVR_FAULT signal can be sampled any time after 1 5 ms after the assertion of PWRGOOD FIVR_FAULT must be qualified by THERMTRIP_N assertion FRMAGENT Bootable Firmware Agent Strap This input configuration strap used in combination with SOCKET_ID to determine whether the socket is a legacy socket bootable firmware agent is present and DMI links are used in PCIe mode instead of DMI2 mode The firmware flash ROM is located behind the local PCH attached to the processor via the DMI2 interface This signal is pulled down on the die refer to Table 8 on page 26 for details PM FAST WAKE N Power Management Fast Wake Enables quick package C3 C6 exits of all Sockets Asserted if any socket detects a break from package C3 C6 state requiring all socket
99. rs integrated into the processor VSS Processor ground VccIO IN IO voltage supply input Vccp DDR power rail xi Refers to a Link or Port with one Physical Lane x4 Refers to a Link or Port with four Physical Lanes x8 Refers to a Link or Port with eight Physical Lanes x16 Refers to a Link or Port with sixteen Physical Lanes 1 1 4 State of Data The data contained within this document is final It is the most accurate information available by the publication date of this document Electrical DC specifications are based on estimated I O buffer behavior September 2014 Order No 330783 001 Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 13 m 1 n tel Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Electrical Specifications 2 1 2 2 2 2 1 2 2 2 Electrical Specifications This chapter describes processor signaling DC specifications and signal quality References to various interfaces memory PCIe Intel QPI PECI etc are also described Integrated Voltage Regulation A new feature to the processor is the integration of platform voltage regulators into the processor Due to this integration the processor has one main voltage rail Vccrw and a voltage rail for the memory interface Vccpo1 Vccp23 one for each memory channel pair compared to five voltage rails Vcc Vita Vrrp Vsa and Vccpi on previous processors The Vecyy voltage r
100. s a logical low value Vin is the minimum voltage level at a receiving agent that will be interpreted as a logical high value Vi and Voy may experience excursions above Vccp However input signal drivers must comply with the signal quality specifications Refer to Signal Quality on page 44 This is the pull down driver resistance Reset drive does not have a termination Rytt_term is the termination on the DIMM and not controlled by the processor Refer to the applicable DIMM datasheet The minimum and maximum values for these signals are programmable by BIOS to one of the pairs Input leakage current is specified for all DDR4 signals 10 Vol Ron VCCD Ron Rtt_Eff where Rtt_Eff is the effective pull up resistance of all DIMMs in the system including September 2014 Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Order No 330783 001 Datasheet 37 intel Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Electrical Specifications 2 9 3 2 PECI DC Specifications Symbol Definition and Min Max Units Figure Notes Conditions Vin Input Voltage Range 0 150 Vccpeci V 0 150 Vuysteresis Hysteresis 0 100 V VccPEcI VN Negative edge 0 275 0 500 V Figure 1 on 2 threshold voltage Vccpeci Vccpeci page 15 Vp Positive edge 0 550 0 725 V Figure 1 on 2 threshold voltage Vccpeci Vccpeci page 15 I source Pullup
101. s to exit the low power state to service a snoop memory access or interrupt Expected to be wired OR among all processor sockets within the platform PROC ID This output can be used by the platform to determine if the installed processor is a Intel Xeon processor E5 1600 and E5 2600 v3 product families There is no connection to the processor silicon for this signal The processor package grounds or floats the pin to set 0 or 1 respectively 1 Intel Xeon processor E5 1600 and E5 2600 v3 product families 0 Reserved for future use RSVD RESERVED All signals that are RSVD must be left unconnected on the board Refer to Reserved or Unused Signals on page 22 for details SAFE MODE BOOT Safe Mode Boot Strap SAFE MODE BOOT allows the processor to wake up safely by disabling all clock gating This allows BIOS to load registers or patches if required This signal is sampled after PWRGOOD assertion The signal is pulled down on the die Refer to Table 8 on page 26 for details SKTOCC N SKTOCC N Socket Occupied is used to indicate that a processor is present This is pulled to ground on the processor package there is no connection to the processor silicon for this signal SOCKET ID 1 0 Socket ID Strap Socket identification configuration straps for establishing the PECI address Intel QPI Node ID and other settings This signal is used in combination with FRMAGENT to determine whether the socket is
102. shoot Specifications Symbol Parameter Min Max Units Figure Notes Vos wax Magnitude of Vccin overshoot above VID 50 mV Figure 5 on page 36 Tos Max Time duration of Vccry overshoot above 25 us Figure 5 on page 36 VcciN max Value at the new lighter load Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet Order No 330783 001 35 m l n tel Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Electrical Specifications Figure 5 Vccin Overshoot Example Waveform Vos wax Vecin_max Vos wax E d Vecin_Max E Tos wax 0 5 10 15 20 25 Time us Note 1 Vos max is the measured overshoot voltage above Vccin_max 2 Tos wax is the measured time duration above Vccin_max 3 VCCIN MAX VID TOB 2 9 3 Signal DC Specifications For additional specifications refer to Related Publications on page 9 2 9 3 1 DDR4 Signal DC Specifications Symbol Parameter Min Nom Max Units Notes In Input Leakage Current 1 4 1 4 mA 9 Data Signals R on DDR4 Data Buffer 27 33 ohm 6 On Resistance Data ODT On Die Termination 45 55 ohm 8 for Data Signals Reference Clock and Command Signals VoL Output Low Voltage V ccp 2 R V 2 7 on R on R VTT TERM Vou Output High Voltage V ccp V V 2 b 7 ccp 2 R on R on R VTT_TERM
103. sor E5 1600 and E5 2600 v3 Product Families Contents Contents Revision HIStOFY E 3 1 0 TNtrOGuctiOn cccceceeeee cece eee ee cece cece eee ee ee ee nena eee sanas a4 R4 RA RA GAS uS RR RR SR SR SAZASAZSR RR eee 8 1 1 Electrical Datasheet Introduction c sss 8 T 1 1 Str cture and SCOp6e do eiii rene etus petra a a PRO RN E 9 1 1 2 Related Publications eise ot rex erasa epar eps ER ARER ga Reda 9 1 1 3 Terminology eise ee irae obra ka Rl LER RR REIR TA TRO C CURRERE EAE ANTEE ERR EPI NE EAR 10 1 1 4 State of Data cen etre sauer n a Ea RR ERR YR RASA TERRE I ERRE DER RR Aaa a ia 13 2 0 Electrical Specifications seeeeeeesesesse ense nanenennn nana na nana uuu nhau sanas ann n uana enn 14 2 1 Integrated Voltage Regulation i eec eie a n nura nasa kan aha oa eR E RA Ra 14 2 2 Processor Signalilig cutis chen esae RUM ER XRPEK QUE USER RR UREN RI AURA E An DnPt a MER 14 2 2 1 System Memory Interface Signal Groups sess 14 2 2 2 PCI Express Signals rin dinner dieu a nk DER ARRA NER NEA RES Me EAE OEE EREA AAE iia 14 2 2 3 DMI2 PCI Express Signals 2 2 terere t eu cantat rua unt ERR ER Race Dude denned seataners 15 2 2 4 Intel QuickPath Interconnect Intel QPI csssesseseeeeenn nenne 15 2 2 5 Platform Environmental Control Interface PECI s s ssssssssssersrrrsrrurnnnerrrsrrrrrnns 15 2 2 6 System Reference Clocks BCLK 0 1
104. t Leakage N A 1 50 mA 8 9 Current Cpad Pad Capacitance N A 1 12 1 7 pF 9 Note Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK 0 1 _DN is equal to the Figure 6 BCLK 0 1 Differential Clock Measurement Point for Ringback T VRB Differential STABLE Vin 150 mV Vgg 100 mV Vaga 100 mV Vit 150 mV REFCLK T sraBLE VRB Differential Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical September 2014 Order No 330783 001 Datasheet 39 m l n te l Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Electrical Specifications Figure 7 BCLK1 0 1 Differential Clock Crosspoint Specification 650 600 550 0 5 VHavg 700 250 0 5 VHavg 700 350 Crossing Point mV 300 250 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg mV Figure 8 BCLK 0 1 Single Ended Clock Measurement Points for Absolute Cross Point and Swing Vmax 1 15V BCLK_DN Vcnoss max 550mV VcRoss min 250mV BCLK_DP Vin 0 30V Figure 9 BCLK 0 1 Single Ended Clock Measure Points for Delta Cross Point BCLK_DN BCLK DP 2 9 3 4 SMBus DC Specifications Symbol Parameter Min Max Units Notes Vit Input Low Voltage 0 3 V ccio iN V V iH Input Hi
105. tel the Intel logo the Intel Anti Theft technology logo Intel AppUp the Intel AppUp logo Intel Atom Intel CoFluent Intel Core Intel Inside the Intel Inside logo Intel Insider Intel NetMerge Intel NetStructure Intel RealSense ntel SingleDriver Intel SpeedStep Intel vPro Intel Xeon Phi Intel XScale InTru the InTru logo the InTru Inside logo InTru soundmark Iris tanium Kno Look Inside the Look Inside logo MCS MMX Pentium picoArray Picochip picoXcell Puma Quark SMARTi smartSignaling Sound Mark Stay With It the Engineering Stay With It logo The Creators Project The Journey Inside Thunderbolt the Thunderbolt logo Transcede Transrf Ultrabook VTune Xeon X GOLD and XMM are trademarks of Intel Corporation in the U S and or other countries Other names and brands may be claimed as the property of others Copyright 9 2014 Intel Corporation All rights reserved Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet September 2014 2 Order No 330783 001 Revision History Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families n tel Revision History Document Revision Description Date Number Number 330783 001 Initial release September 2014 Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical September 2014 Datasheet Order No 330783 001 3 m n tel Intel Xeon Proces
106. tform Environment Control Interface Phit An Intel QPI terminology defining bits at physical layer Processor Includes the 64 bit cores uncore I Os and package Processor Core The term processor core refers to Si die itself which can contain multiple execution cores Each execution core has an instruction cache data cache and 256 KB L2 cache All execution cores share the L3 cache R3QPI Intel QPI Agent An internal logic block providing interface between internal Ring and external Intel QPI Rank A unit of DRAM corresponding four to eight devices in parallel ignoring ECC These devices are usually but not always mounted on a single side of a DDR4 DIMM RDIMM Registered Dual In line Memory Module RTID Request Transaction IDs are credits issued by the Cbo to track outstanding transaction and the RTIDs allocated to a Cbo are topology dependent SCI System Control Interrupt Used in ACPI protocol SKU Stock Keeping Unit SKU is a subset of a processor type with specific features electrical power and thermal specifications Not all features are supported on all SKUs A SKU is based on specific use condition assumption SSE Intel Streaming SIMD Extensions Intel SSE SMBus System Management Bus A two wire interface through which simple system and power management related devices can communicate with the rest of the system Storage Conditions A non operational state The processor may be i
107. tion http www jedec org Intel 64 and IA 32 Architectures Software Developer s Manuals 325462 e Volume 1 Basic Architecture http www intel com products e Volume 2A Instruction Set Reference A M processor manuals index htm e Volume 2B Instruction Set Reference N Z e Volume 3A System Programming Guide e Volume 3B System Programming Guide continued Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical September 2014 Datasheet Order No 330783 001 9 1 1 3 Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Introduction Document Document Number Location Intel 64 and IA 32 Architectures Optimization Reference Manual Intel Virtualization Technology Specification for Directed I O http www intel com Architecture Specification content www us en intelligent systems intel technology vt directed io spec html Intel Trusted Execution Technology Software Development Guide http www intel com technology security Terminology Term Description ASPM Active State Power Management BMC Baseboard Management Controller Cbo Caching Agent also referred to as CA It is a term used for the internal logic providing ring interface to LLC and Core The Cbo is a functional unit in the processor A Caching Agent is defined per the RS Intel QuickPath Interconnect External Link Specification
108. tions are based on final 2 3 7 8 9 10 For SVID Power State Functions SetPS see SVID Power State Functions SetPS on page 19 11 Vccp tolerance at processor pins Required in order to meet 5 tolerance at processor die 12 The Vecpo1 Vccp2s voltage specification requirements are measured across vias on the platform Choose Vecpo1 Or Vecp23 13 Veccin has a Vboot setting of 0 0V and is not included in the PWRGOOD indication characterization These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required The Vccry voltage specification requirements are measured across the remote sense pin pairs Vccin_sense and Vss vccIN sENsE 0n the processor package Voltage measurement should be taken with a DC to 100 MHz bandwidth oscilloscope limit or DC to 20MHz for older model oscilloscopes using a 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe Refer to Table 15 on page 33 and corresponding Figure 4 on page 35 The processor should not be subjected to any static Vcciy level that exceeds the Vccin_max associated with any particular current Failure to adhere to this specification can shorten processor lifetime Minimum Vecin and maximum Iccry are specified at the maximum processor case temperature
109. tions for signal quality are for measurements at the processor core only and are only observable through simulation Therefore proper simulation is the only way to verify proper timing and signal quality DDR Signal Quality Specifications Overshoot or undershoot is the absolute value of the maximum voltage above or below VSS The overshoot undershoot specifications limit transitions beyond specified maximum voltages or VSS due to the fast signal edge rates The processor can be damaged by single and or repeated overshoot or undershoot events on any input output or I O buffer if the charge is large enough i e if the over undershoot is great enough Baseboard designs which meet signal integrity and timing requirements and which do not exceed the maximum overshoot or undershoot limits listed in Table 17 on page 45 will ensure reliable IO performance for the lifetime of the processor I O Signal Quality Specifications Signal Quality specifications for PCIe Signals are included as part of the PCIe DC specifications Input Reference Clock Signal Quality Specifications Overshoot Undershoot and Ringback specifications for BCLK 0 1 _D N P are found in Table 17 on page 45 Overshoot Undershoot and Ringback specifications for the DDR4 Reference Clocks are specified by the DIMM Overshoot Undershoot Tolerance Overshoot or undershoot is the absolute value of the maximum voltage above or below VSS see Figure 11 on page 46 The overshoot un
110. uality Specifications cessssssssssssss eene 44 2 11 3 Input Reference Clock Signal Quality Specifications sese 44 2 11 4 Overshoot Undershoot Tolerance scsssesseesseese nennen ness nnn 44 3 0 Processor Land Listing e esesseseseeeiessesa sa sa sa nenuuna ananas anu au auus u sanas annuas na 48 4 0 Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Signal DECPnHbPDIL M 49 4 1 System Memory Interface ieiseiesesgece aE ERR REV UURCERE DIRNE E FER denenaedenert 49 4 2 PCI Express Based Interface Signals ice ei detener ta nr ian reta da nah aaa Re kann 50 4 3 DMI2 PCI Express Port 0 Sigrials 2 irc eie ciet opea rm rae I eR dn kien au daa Re ERE NA 52 4 4 Intel QuickPath Interconnect Signals cccccccceccceeceeeeeeeeeeeeeeeseeeseeeesueeeseeesaeeesnees 52 A SPECI SIGMA Pe 52 Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet September 2014 4 Order No 330783 001 Contents Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families 4 6 System Reference Clock Signals sse 4 7 JTAG and TAP Signals nr petra tust a a ER ES 4 8 Serial VID Interface SVID Signals sseeseseeeeen 4 9 Processor Asynchronous Sideband and Miscellaneous Signals 4 10 Processor Power and Ground Supplies Intel Xeon
111. ug tools TRST N TRST_N Test Reset resets the Test Access Port TAP logic TRST N must be driven low during power on Reset Serial VID Interface SVID Signals SVID Signals Signal Name Description SVIDALERT N Serial VID alert SVIDCLK SVIDDATA Serial VID clock Serial VID data out Processor Asynchronous Sideband and Miscellaneous Signals Processor Asynchronous Sideband Signals Signal Name Description CATERR N Indicates that the system has experienced a fatal or catastrophic error and cannot continue to operate The processor will assert CATERR_N for unrecoverable machine check errors and other internal unrecoverable errors It is expected that every processor in the system will wire OR CATERR_N for all processors Since this is an I O land external agents are allowed to assert this land which will cause the processor to take a machine check exception This signal is sampled after PWRGOOD assertion On the Intel Xeon processor v3 product families CATERR_N is used for signaling the following types of errors e Legacy MCERR s CATERR N is asserted for 16 BCLKs e Legacy IERR s CATERR N remains asserted until warm or cold reset ERROR N 2 0 Error status signals for integrated I O IIO unit continued Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Order No 330783 001 Datasheet 53 Int
112. umber Buffer Type J45 PCIEX3 AHAB PCIEXG ACAD PCIEXG PCIEXS PCIEXG PCIEXS PCIEXG PCIEXG PCIEXS PCIEXG PCIEXG PCIEXG PCIEXG PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 U T M Y A Y ARES AAS PE3B_RX_DP 4 AB50 PE3B RX DP 5 AB52 PE3B RX DP 6 AC53 PE3B RX DP 7 AC51 PE3B TX DN 4 AF5O H T U T U PE3C RX DN 11 AG49 PE3C RX DNI8 AF48 PE3C RX DN 9 AG51 PE3C_RX_DP 10 AH50 PE3C_RX_DP 11 AJ49 E Ast ART Y R ACAT ABAG T U AGAT ANAT J5 R P K L5 4 P R P R P 50 1 47 48 50 1 47 8 50 52 52 51 50 49 52 51 50 49 46 46 45 46 45 PE3B TX DN 6 PE3B TX DN 5 September 2014 Intel R Xeon R Processor E5 1600 and E5 2600 v3 Product Families Vol 1 of 2 Electrical Datasheet Order No 330783 001 77 Appendix A Pin List Pin Name Pin Number Buffer Type AMAG PCIEXS ANAS PCIEXG AMT PCIEXG ARAT PCIEXS APAG PCIEXS ARAS PCIEXG AAAS PCIEXG Ya PCIEXS AGAS PCIEX3 144 PCIEXS AGAS PCIEX3 BAA PCIEXS ARAB PCIEXS Pad PCIEXG 5 G55 PECI AVAA K52 CU49 owas ABA BLS ACA BJSS BM58 BKB OF 44 CD44 CMOS CMOS CMOS CMOS z 2 ODCMOS CMOS CMOS QPIO DRX DN 1 BF52 QPIO DRX DN 10 BN55 BP54 BNS3 BP52 BASI BP50 BRA B
113. upports the following VR commands e SetVID Fast 20 mV us e SetVID Slow 5 mV us e Slew Rate Decay downward voltage only and it s a function of the output capacitance s time constant commands Table 5 on page 21 includes SVID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 13 on page 31 The VRM or EVRD utilized must be capable of regulating its output to the value defined by the new VID Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable SetVID Fast Command The SetVID Fast command contains the target VID in the payload byte The range of voltage is defined in the VID table The VR should ramp to the new VID setting with a fast slew rate as defined in the slew rate data register It is minimum of 20 mV us depending on the amount of decoupling capacitance The SetVID Fast command is preemptive The VR interrupts its current processes and moves to the new VID The SetVID Fast command operates on 1 VR address at a time This command is used in the processor for package C6 fast exit SetVID Slow The SetVID Slow command contains the target VID in the payload byte The range of voltage is defined in the VID table The VR should ramp to the new VID setting with a slow slew rate as defined in the slow slew rate data register The SetVID Slow is nominally 4x slower than the SetVID Fast slew rate The SetVID Slow comman
114. vershoot on its own may meet the overshoot specification when you add the total impact of all overshoot events the system may fail A guideline to ensure a system passes the overshoot and undershoot specifications is shown below 1 If only one overshoot undershoot event magnitude occurs ensure it meets the over undershoot specifications in the following tables OR 2 If multiple overshoots and or multiple undershoots occur measure the worst case pulse duration for each magnitude and compare the results against the AF 0 1 specifications If all of these worst case overshoot or undershoot events meet the specifications measured time specifications in the table where AF 0 1 then the system passes Processor Sideband Signal Group Overshoot Undershoot Tolerance Absolute Absolute Pulse Pulse Maximum Maximum Duration ns Duration ns Overshoot Undershoot AF 0 1 AF 0 01 V V 1 3335 V 0 2835 V 3ns 5ns 1 2600 V 0 210 V 5 ns 5 ns Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet Order No 330783 001 47 m l n te Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Processor Land Listing 3 0 Processor Land Listing Refer to Appendix A in this document Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet September 2014 48 Order No 330783 001 Intel Xeon Processor E5 1600
115. y the DRAM This is an input signal used to indicate the Vccp power supply is stable for memory channels 0 amp 1 and channels 2 amp 3 PCI Express Based Interface Signals PCI Express Ports 1 2 and 3 Signals are receive and transmit differential pairs PCI Express Port 1 Signals Signal Name Description PE1A RX DN 3 0 PE1A RX DP 3 0 PCIe Receive Data Input PE1B RX DN 7 4 PE1B RX DP 7 4 PCIe Receive Data Input PE1A TX DN 3 0 PE1A TX DP 3 0 PCIe Transmit Data Output PE1B TX DN 7 4 PE1B TX DP 7 4 PCIe Transmit Data Output PCI Express Port 2 Signals Signal Name Description PE2A RX DN 3 0 PE2A RX DP 3 0 PCIe Receive Data Input PE2B_RX_DN 7 4 PCIe Receive Data Input PE2B_RX_DP 7 4 continued Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Volume 1 of 2 Electrical Datasheet 50 September 2014 Order No 330783 001 Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Signal Descriptions Intel Xeon Processor E5 1600 and E5 2600 v3 Product Families Table 23 Table 24 September 2014 intel Signal Name Description PE2C RX DN 11 8 PE2C RX DP 11 8 PCIe Receive Data Input PE2D RX DN 15 12 PE2D RX DP 15 12 PCIe Receive Data Input PE2A TX DN 3 0 PE2A TX DP 3 0 PCIe Transmit Data Output PE2B TX DN 7 4 PE2B TX DP 7 4 PCIe Tra

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