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Elixir M2F2G64CB88DHN-CG memory module

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1. pasa t pas4 1 DM4 I DM CS DGS 005 DM CS Das 5005 DM CS DOS Das DM CS DAS DAS W4 VO 0 oo N o1 VO 1 pass 1 VO 1 N o2 Vo 2 DQ34 N 02 VO 2 N vos DO Vo 3 D8 pass N o3 04 012 04 VO 4 pass N 704 VO 4 N vos Vo 5 DQ37 05 yo 5 N voe VO 6 06 WM 7 zo 0039 107 zo x Vo 7 zo M 9 pass M Ed 0055 t DM5 t DM CS 0605 005 DM CS DOS 005 DM CS 005 5 DM CS DOS 005 NH roo 0 N oo 0 N 4 01 VO 1 DQ41 1 VO 1 N vo2 VO 2 0042 N 02 VO 2 N 4 vos D1 Vo 3 D9 DQ43 N o3 D5 W4 4 VO 4 0044 704 VO 4 N 05 VO 5 0045 05 yo 5 N voe VO 6 DQ46 06 N voz zo Ex VO 7 2947 N o7 zo x VO 7 za 7 pase D t pass M 1 DM6 t DM CS 505 005 DM CS 005 DOS DM CS 505 Das DM CS 6505 Das Ww roo VO 0 DQ48 N roo 1 VO 1 00949 VO1 VO 1 W4 2 2 DQ50 02 2 N vos D2 VOS DQ51 3 06 014 104 VO 4 DQ52 704 VO 4 N vos VO 5 0053 05 yo 5 N voe VO 6 DQ54 N 06 N voz za VO7 0955 07 Ke VO7 zal 0057 T gt DQS7 1 DM7 DM CS Das 905 DM CS bas pas DM CS DOS 505
2. 0010000 1 00 Pitch 1 50 0 10 Units Millimeters Note Device position and scale are only for reference REV 1 1 20 09 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2F4G64CB8HD5 9 N 2GB 256M x 64 AGB 512M x 64 _ PC3 8500 PC3 10600 el iIXir Unbuffered DDR3 SDRAM DIMM Package Dimensions 4GB 2 Ranks 256Mx8 DDR3 SDRAMs Heat Sink FRONT 13335 0 15 126 00 0 2 25 00 0 2 30 00 0 5 0 15 1 27 0 07 0 10 e Detail A Detail B 2 50 sala a 0 8 0 0 05 M DOCTI 000000 4 4 1 00 Pitch 1 50 4 0 10 Units Millimeters REV 1 1 21 09 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2FA4G64CB8HD5 9 N 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 Unbuffered DDR3 SDRAM DIMM Revision Log Rev Date Modification 0 1 02 2011 Preliminary Release 1 0 03 2011 Official Release 1 1 09 2011 Added Heat Sink Part Numbers REV 1 1 22 09 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice
3. 15 mV 4 For reference approx VDD 2 15 mV 5 Single ended swing requirement for DQS DQS is 350 mV peak to peak Differential swing requirement for DQS DQS is 700 mV peak to peak REV 1 1 8 09 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2F4G64CB8HD5 9 N 2GB 256M x 64 4GB 512M x 64 Wi PC3 8500 PC3 10600 e IXIr Unbuffered DDR3 SDRAM DIMM Operating Standby and Refresh Currents Toase 0 85 Voo 1 5V 0 075V 2GB 1 Rank 256Mx8 DDR3 SDRAMs IDDO Operating One Bank Active Precharge Current IDD1 Operating One Bank Active Read Precharge Current 704 748 mA IDD2PO Precharge Power Down Current Slow Exit 106 106 mA IDD2P1 Precharge Power Down Current Fast Exit 220 264 mA IDD2Q Precharge Quiet Standby Current 264 308 mA IDD2N Precharge Standby Current 290 334 mA IDD3P Active Power Down Current 334 352 mA IDD3N Active Standby Current 396 440 mA IDD4R Operating Burst Read Current 1056 1188 mA IDD4W Operating Burst Write Current 1012 1144 mA IDD5B Burst Refresh Current 1452 1496 mA IDD6 Self Refresh Current Normal Temperature Range 106 106 mA IDD7 Operating Bank Interleave Read Current 1848 1980 mA Operating Standby and Refresh Currents Toase 0 85 1 5V 0 075V 4GB 2 Ranks 256 8 DDR3 SDRAMs IDDO Operating One Bank Active Precharge Current 1012 I
4. DQ to I O wiring is shown as recommended but may be changed T DQ DQS DQS ODT DM CKE S relationships must be maintained as shown For each DRAM a unique ZQ resistor is connected to ground The ZQ resistor is 2400 1 One SPD exists module NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2F4G64CB8HD5 9 N 268 256M x 64 428 512M x 64 PC3 8500 PC3 10600 e Unbuffered DDR3 SDRAM DIMM Environmental Requirements Topr Module Operating Temperature Range ambient 0 to 55 C 3 Hopr Operating Humidity relative 10 to 90 1 Storage Temperature Plastic 55 to 100 C 1 Storage Humidity without condensation 5 to 95 1 Pressure operating amp storage 105 to 69 K Pascal 1 2 Note 1 Stresses greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Up to 9850 ft 3 The component maximum case temperature shall not exceed the value specified in the component spec Absolute Maximum DC Ratings Vpp Voltage on VDD pins relative to Vss 0 4 V 1 975 V V Voltage on pins relative to 55 0 4 V 1 975 V V 1 3 Vin Vout Voltage on I O pin
5. NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2F4G64CB8HD5 9 N 2GB 256M x 64 AGB 512M x 64 _ PC3 8500 PC3 10600 el IXIY Unbuffered DDR3 SDRAM DIMM Package Dimensions 2GB 1 Rank 256Mx8 DDR3 SDRAMs Heat Sink FRONT 13335 0 15 126 0 2 SIDE 4 30 Max 4 25 00 0 2 30 00 0 5 0 15 1 27 0 07 0 10 Detail A Detail B 2 250 8 3 9 MEE 0 8 0 0 05 4 78000 L4 00 0000 0110000 1 00Pitch 1 50 0 10 Units Millimeters REV 1 1 19 09 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2FAG64CB8HD5 9 N 2GB 256M x 64 428 512M x 64 _ PC3 8500 PC3 10600 el IXIY Unbuffered DDR3 SDRAM DIMM Package Dimensions 4GB 2 Ranks 256Mx8 DDR3 SDRAMs FRONT 133 35 0 15 4 00 Max 30 00 0 5 0 15 Detail A PN Detail B 5 175 47 00 71 00 1 27 0 07 0 10 5 00 Detail A Detail B 250 0 80 0 05 80 0
6. Parameter Symbol e 24 Units Minimum Clock Cycle Time DLL off mode _ Jckouor 8 ___ ns Average Clock Period Reter to Standard Speed Bin ps Average high pulse width 04 05 Average low pulsewidth 047 Absolute Clock Period tCK abs Max tCK avg max tJIT per max Absolute clock HIGH JCcHe 043 Absolute clock LOW pulse width _____ 049 Cock Period Jitter __ Clock Period Jitter during DLL locking period Cycle to Period siter tsps S Cycle to Period Jitter during DLL locking period Duty Cycle ster misty Pps Cumulative error across 2cycles ae _ Cumuaiveemorawoss3cydes __ JERRGpe ____ Cumulative error across 4 cycles Cumulative error across 5 cycles ___ ons Jes S Cumulative error across 6 cycles gt ______ Cumulative error across 7 oycles 9 Cumulative error across Boyles Cumuaiveemoramoss9cydes 24 24 e S Cumulative error across 10 cyoles ea S Cumulative error across 11 cyoles SS S Cumulative error across 12 cyoles __ S tERR
7. 07 Notes 1 DQ to I O wiring is shown as recommended but may be changed 2 DQ DQS DQS ODT DM CKBE S relationships must be maintained as shown 3 For each DRAM a unique ZQ resistor is connected to ground The ZQ resistor is 2400 19 4 One SPD exists per module NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2FA4G64CB8HD5 9 N 2GB 256M x 64 AGB 512M x 64 PC3 8500 PC3 10600 Unbuffered DDR3 SDRAM DIMM Functional Block Diagram 4GB 2 Ranks 256Mx8 DDR3 SDRAMs 51 50 0050 0050 DQO DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1 DM1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 0052 0052 DQ16 DQ17 DQ18 DQ19 DQ20 0021 0922 DQ23 5053 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 REV 1 09 2011 eixir
8. RTT dynamic change skew Poo o7 Write Leveling Timings nn eee ee First DQS DQS rising edge after tWLMRD write leveling mode is programmed DOS DOS delay after write leveling mode is programmed WLDOSEN fh nk S Write leveling setup time from rising CK CK WLS crossing to rising DQS DQS crossing Write leveling hold time from rising DQS DQS crossing to rising crossing Write leveling output delay WLO ___ T wi Write leveling output error hwy REV 1 1 17 09 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2FAG64CB8HD5 9 N 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 Unbuffered DDR3 SDRAM DIMM Package Dimensions 2GB 1 Rank 256Mx8 DDR3 SDRAMs elixir FRONT 133 35 0 15 le gt SIDE wo D 2 57 Max I e e e i __ Detail Pur Detail A 5 175 47 00 71 00 1 27 0 07 0 10 Detail A Detail B 2 50 o e E 0 80 0 05 pee NE 0110000 1 00 Pitch 1 50 0 10 Units Millimeters Note Device position and scale are only for reference REV 1 1 18 09 2011
9. __ P tXSmin max 5nCK tRFC min 10ns Exit Self Refresh to commands not requiring a locked DLL tXS tXSmax tXSDLLmin tDLLK min Exit Self Refresh to commands requiring a locked DLL CK tXSDLLmax tCKESRmin tCKE min 1 nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR tCKESRmax Valid Clock Requirement after Self Refresh Entry SRE ICKSRE tCKSREmin max 5 nCK 10 ns or Power Down Entry PDE tCKSREmax t in Valid Clock Requirement before Self Refresh Exit SRX CKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax Power Down Timings x ERA Exit Power Down with DLL on to any valid command tXPmin max 3nCK 6ns Exit Precharge Power Down with DLL frozen to commands tXPmax not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands XPDLL tXPDLLmin max 10nCK 24ns requiring a locked DLL tXPDLLmax tCKEmin max 3nCK 5 625ns CKE minimum pulse width tCKE tCKEmax tCPDEDmin 1 Command pass disable delay tCPDED tCPDEDmin tPDmin tCKE min Power Down Entry to Exit Timing tPDmax 9 tREFI tACTPDENmin 1 Timing of ACT command to Power Down entry tACTPDENmax tPRPDENmin 1 tPRPDENmax A n 2 2 o 4 U 2 U 20 U m z Timing of PRE or PREA command to Power Down entry REV 1 1 16 09 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves t
10. 268 256M x 64 428 512M x 64 PC3 8500 PC3 10600 e Unbuffered DDR3 SDRAM DIMM Ordering Information M2F2G64CB88D7N BE 0083 1066 PC3 8500 533MHz 1 875ns 9 CL 7 M2F2G64CB88D7N CG DDR3 1333 10600 667MHz 1 500ns CL 9 M2F2G64CB88DHN BE DDR3 1066 PC3 8500 533MHz 1 875ns CL 7 M2F2G64CB88DHN CG 0083 1333 PC3 10600 667MHz 1 500ns CL 9 n per M2F4G64CB8HD5N BE DDR3 1066 PC3 8500 533MHz 1 875ns CL 7 M2F4G64CB8HD5N CG 0093 1333 PC3 10600 667MHz 1 500ns CL 9 1 M2F4G64CB8HD9N BE DDR3 1066 PC3 8500 533MHz 1 875ns CL 7 ee M2F4G64CB8HD9N CG DDR3 1333 PC3 10600 667MHz 1 500ns CL 9 Pin Description CKO CK1 Clock Inputs positive line 0090 0063 Data input output CK1 Clock Inputs negative line DQS0 DQS8 Data strobes CKEO CKE1 Clock Enable DQSO0 DQS8 Data strobes complement RAS Row Address Strobe Data Masks CAS Column Address Strobe EVENT Temperature event pin WE Write Enable RESET Reset pin S0 S1 Chip Selects Vnerba Input Output Reference 9 A11 A13 A15 Address Inputs Vopspp SPD and Temp sensor power A10 AP Address Input Auto Precharge SAO SA1 Serial Presence Detect Address Inputs A12 BC Address Input Burst Chop Vtt Termination voltage BAO BA2 SDRAM Bank Address Inputs Vss Ground ODTO ODT1 Active termination control lines Voo Core and I O power SCL Serial Presence Detect Clock Input NC No Conne
11. 72 Vo 192 RAS 102 0056 222 00515 00517 00515 13 009 133 Vss 43 DQS8 163 Vss 73 WE 193 50 103 0056 223 Vss 14 134 uc 44 Vs 164 CB6NC 74 CAS 194 104 Vs 224 0054 15 DOSI 135 pun 45 CB2 NC 165 CB7ZNC 75 195 105 0050 225 0055 16 DQS1 136 Vss 46 CB3 NC 166 Vss 76 SINC 196 A13 106 0051 226 Vss 17 Vg 137 47 167 NC TEST 77 ODTINC 197 V 107 Vas 227 18 0010 138 0015 48 168 RESET 78 Vp 198 S3 NC 108 0056 228 0061 19 0011 139 Vss 49 Vm NC 169 79 S2NC 199 Veg 109 0057 229 Vss DM7 20 140 DQ20 50 CKEO 170 Voo 80 200 0036 110 Vss 230 00516 TDOSI6 NC 21 0016 141 51 171 A15NC 81 0032 201 00937 111 00557 231 DOSTS 150516 22 0017 142 52 2 172 14 82 DQ33 202 Vs 112 DQS7 232 Vss DM4 23 143 53 Our 173 Voo 83 203 00513 113 Vss 233 0062 NG TDQS13 NC DOS71 rias 24 DOSZ 144 174 A12 BC 84 DOS4 204 DOSS 114 0058 234 00513 150513 25 0052 145 Vss 55 AM 175 A9 85 DQS4 205 Vs 115 0059 235 Ves 26 Vss 146 0022 56 7 176 m 86 Vss 206 0038 116 Vss 236 27 0018 147 DQ23 57 177 A8 87 207 DQ39 117 SAO 237 SA 28 DQI9 148 Vss 58 A5 178 A6 88 DQ35 208 Vs 118 SCL 238 SDA 29 149 0028 59 4 179 ve 89 209 0044 119 SA2 239 Vss 0024 150 9 60 180 A3 90 0040 210 0045 120 Vm 240 Vn Note CK1 CKE1 S1 and ODT1 are for 4GB modules only RE
12. CK tWLS 245 crossing to rising 005 DQS crossing Write leveling hold time from rising DQS 0 ite leveling hold time from rising DQS DQS 245 crossing to rising CK CK crossing Write leveling output delay WLO ps Jj 4 Write leveling output error ts REV 1 1 14 09 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2F4G64CB8HD5 9 N 2GB 256M x 64 AGB 512M x 64 PC3 8500 PC3 10600 el IXIY Unbuffered DDR3 SDRAM DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1333MHz C w 1 oe O O Parameter Symbol Units Minimum Glock Cycle Time DLL off mode Average Clock Period Reter to Standard Speed Average high pulsewidth oo 04 05 oag Average low pulsewidth 04 05 Absolute Clock Period tCK abs Max tCK avg max tJIT per max Absolute clock HIGH pulse width 04 Absolute clock LOW pulse 09 Clock Period siter sitio ____ ____ 8 Clock Period Jitter during DLL locking period Cycle Cycle Period siter Cycle to Cycle Period Jitter during DLL locking period Duty Cyce ster ftir __ __ __ s Cumulative error across 2 cycle
13. DASE differential output hightime OSH o4 __ DOS DASE differential outputiowtime pos DOS DOSE differential WRITE Preamble were 09 ____ DOS DOSE differential WRITE Postamble west ____ Dre DQS DQS low impedance time i tLZ DQS 500 tCK avg Referenced from RL 1 DQS DQS high impedance time SUP tHZ DQS tCK avg Referenced from RL E Es cuu us E E 005 DOS amp difeeniainpuhghpusewidh 045 DOS DASE rising edge to CK rising edge Doass os 05 DASE fang edge setup time to pss Ke 05 DASE falling edge hold time from rising edge _ REV 1 1 15 09 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2F4G64CB8HD5 9 N 2GB 256M x 64 4GB 512M x 64 A PC3 8500 PC3 10600 e Unbuffered DDR3 SDRAM DIMM tRTPmin max 4nCK 7 5ns Internal READ Command to PRECHARGE Command delay tRTP tRTPmax Delay from start of internal write WTR tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery time s d o s Mode Register Set command cycle time ____ tMODmin max 12nCK 15ns Mode R
14. DD1 Operating One Bank Active Read Precharge Current 1100 1188 mA IDD2PO Precharge Power Down Current Slow Exit 211 211 mA IDD2P1 Precharge Power Down Current Fast Exit 440 528 mA IDD2Q Precharge Quiet Standby Current 528 616 mA IDD2N Precharge Standby Current 581 669 mA IDD3P Active Power Down Current 669 704 mA IDD3N Active Standby Current 792 880 mA IDD4R Operating Burst Read Current 1452 1628 mA IDD4W Operating Burst Write Current 1408 1584 mA IDD5B Burst Refresh Current 1848 1936 mA IDD6 Self Refresh Current Normal Temperature Range 211 211 mA IDD7 Operating Bank Interleave Read Current 2244 2420 mA REV 1 1 9 09 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2F4G64CB8HD5 9 N 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 el IXIr Unbuffered DDR3 SDRAM DIMM Speed Bins DDR3 1066MHz ACTIohenalveadorwiedeaytme RCD wm m AGTIOACTorREFconmandpered 98S m AGTIOPRE commana poroa m o oms Ree ows m E B mi oms wo Rem m REV 1 1 10 09 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2F4G64CB8HD5 9 N 2GB 256M x 64 4GB 512M x 64
15. DM CS 605 DOS W VO 0 0056 N j oo o w VO 1 DQ57 701 VO 1 N 2 Vo 2 pass N 02 2 vos D3 Di 959 N 03 D7 015 w 4 VO 4 704 VO 4 5 VO 5 05 yo 5 Ww voe VO 6 6 Ww 07 Ex VO7 2983 107 zo x Vo 7 zo VopsPp 9 SPD SDRAM 20 015 CKE 1 0 A 13 0 Vnerba 00 015 RAS CAS WE m Va Vs 00 015 ODT 1 0 BA 2 0 51 0 00 015 2 gt 2 SDRAMs 00 015 13 gt 13 SDRAMs 00 015 DDR3 RAS p RAS SDRAMs 00 015 SDRAM CAS p CAS SDRAMs 00 015 CK 1 WE SDRAMs 00 015 gt SDRAMs 00 07 CKE1 y SDRAMs 08 015 gt ODT SDRAMs 00 07 SDRAMs 08 015 SCL gt SCL SDRAMs 00 07 3 A0 4 gt 50 CKO CK SDRAMs 00 07 3 TS p CK SDRAMs 08 015 CK SDRAMs 08 015 ES RESET RESET SDRAMs 08 015 1 Notes
16. ECHARGE commandperiod eas Standard Speed Bins to ACTIVE command period for 18 page size RRD tRRDmin max 4nCK 10ns ACTIVE to ACTIVE command period for 2KB page size tRRDmax Four activate window for 1KB page size Four activate window for 2KB page size fs _ ____ Command and Address setup time to CK CK tlS base 125 referenced to Vih ac Vil ac levels Command and Address hold time from CK CK tIH base 200 referenced to Vih dc Vil dc levels Command and Address setup time to CK CK id tlS base AC150 1254150 referenced to Vih ac Vil ac levels Control and Address Input pulse width for each input O z Calibration Timing E eS LEER MIND Power up and RESET calibration time _____ __ Normal operation Full calibration time Zooper 29 Normal operation Short calibration time 12008 pwc Reset Timing ______ y tXPRmin max 5nCK tRFC min 10ns Exit Reset from CKE HIGH to a valid command tXPR Self Refresh Timings pae Racer Enc ees 2x tXSmin max 5nCK tRFC min 10ns Exit Self Refresh to commands not requiring a locked DLL XS tXSmax tXSDLLmin tDLLK min Exit Self Refresh to commands requiring a locked DLL tXSDLL tXSDLLmax tCKESRmin tCKE min 1 nCK Minimum CKE low width for Self Refresh entry to e
17. M2F2G64CB88D7 H N M2F4G64CB8HD5 9 N 2GB 256M x 64 AGB 512M x 64 PC3 8500 PC3 10600 Unbuffered DDR3 SDRAM DIMM Based on DDR3 1066 1333 256Mx8 SDRAM D Die Features Performance PC3 8500 PC3 10600 Spent BE DIMM CAS Latency 7 9 fck Clock Freqency 533 667 MHz tck Clock Cycle 1 875 1 5 ns fDQ DQ Burst Fregency 1066 1333 Mbps 240 Pin Dual In Line Memory Module UDIMM 256Mx64 2GB 512Mx64 4GB DDR3 Unbuffered DIMM based on 256Mx8 DDR3 SDRAM D Die devices Intended for 533MHz 667MHz applications Inputs and outputs are SSTL 15 compatible Voo 1 5V 0 075V elixir Programmable Operation DIMM CAS Latency 5 6 7 8 9 Burst Type Sequential or Interleave Burst Length BC4 BL8 Operation Burst Read and Write Two different termination values Rtt Nom amp Rtt WR 15 10 1 row column rank Addressing for 2GB 15 10 2 row column rank Addressing for 4GB Extended operating temperature rage Auto Self Refresh option Serial Presence Detect SDRAMs have 8 internal banks for concurrent operation Differential clock inputs Data is read or written on both clock edges DRAM DLL aligns DQ and 005 transitions with clock transitions Address and control signals are fully synchronous to positive clock edge Nominal and Dynamtic On Die Termination support Gold contacts SDRAMs are in 78 ball BGA Package RoHS compliance and Halogen fr
18. N 0 2 DQ35 N 4 103 D4 DQ36 N 4 DQ37 N 5 JN 4 DQ39 N 4 7 r3 9055 DQS5 DM5 DM cs Das 2940 oo 0041 N J 701 0042 1 02 0043 N 05 0044 0 4 09045 N 4 05 0046 106 2047 N 4 7 20 Dase DQS6 DM6 DM cs Das DO48 oo DQ49 VO 1 DQ50 N 4 02 DQ51 o3 D6 DQ52 104 DQ53 o5 0054 106 0055 VO7 Das7 DQS7 DM7 DM cs Das DQ56 M 100 DQ57 DQ58 N 4 02 0059 N 103 D7 DQ60 J 4 DQ61 5 DQ62 106 DQ63 J VO7 ZQ EJ Vooso 9 8 SPD o D0 D7 Vaga F gt 00 07 Vss gt DO D7 Vasea 00 07 2 BAO BA2 SDRAMs 00 07 0 13 A0 A13 SDRAMs 00 07 RAS y RAS SDRAMs 00 07 CAS yp CAS SDRAMs 00 07 p SDRAMs 00 07 WE p WE SDRAMs 00 07 gt ODT SDRAMs 00 07 p CK SDRAMs 00 07 CK SDRAMs 00 07 RESET RESET SDRAMs 00
19. PC3 8500 PC3 10600 el IXIr Unbuffered DDR3 SDRAM DIMM DDR3 1333MHz ct Internal read command to first data 2000 KM ess Reserved Reserved ns _ Reowd ne Reserved rs NN RN Reserves Reowd ne Reemi rs Reed Reseved ns EN NENNEN CNN Reemi Resend Reed Reseved ns okava CNN Optional D ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CWL A L 5 olo mu a 5 AA 619 AA A A oToTo o 0 A A A A A A A SIS gt gt gt gt gt gt gt gt gt gt gt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt A T o ain gt lt 1 1 11 09 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2F4G64CB8HD5 9 N 2GB 256M x 64 AGB 512M x 64 PC3 8500 PC3 10600 el IXIY Unbuffered DDR3 SDRAM DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1066MHz 1
20. V 1 1 09 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2F4G64CB8HD5 9 N 2GB 256M x 64 AGB 512M x 64 PC3 8500 PC3 10600 Unbuffered DDR3 SDRAM DIMM elixir Input Output Functional Description Symbol CKO CK1 CKO CK1 CKE1 0 51 RAS WE ODTO ODT1 DMO DM8 00950 0058 DQS0 DQS8 BAO BA1 BA2 A0 A9 A10 AP A11 A12 BC A13 A15 DQ63 Vss Vnerpa VREFCA SDA SCL SA2 EVENT RESET REV 1 1 09 2011 Type Polarity Cross Input point Active Input High Active Input Low Active Input Low Active Input High Active Input High Cross VO point Input Input Input Input Input Output Input Function The system clock inputs All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK A Delay Locked Loop DLL circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high When the command d
21. additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the Refresh interval tREFI to 3 9 us It is also possible to specify a component with 1X refresh to 7 8 5 in the Extended Temperature Range Please refer to supplier data sheet and or the DIMM SPD for option availability b If Self Refresh operation is required in the Extended Temperature Range then it is mandatory to either use the Manual Self Refresh mode with Extended Temperature Range capability MR2 Ob and MR2 A7 1b or enable the optional Auto Self Refresh mode MR2 A6 1b and MR2 A7 Ob Please refer to the supplier data sheet and or the DIMM SPD for Auto Self Refresh option availability Extended Temperature Range support and tREFI requirements in the Extended Temperature Range REV 1 1 7 09 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2F4G64CB8HD5 9 N 2GB 256M x 64 4GB 512M x 64 A PC3 8500 PC3 10600 e Unbuffered DDR3 SDRAM DIMM DC Electrical Characteristics and Operating Conditions VDD Supply Voltage 1 425 1 575 VDDQ Output Supply Voltage 1 425 1 5 1 575 V Note 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together Single Ended AC and DC Input Levels for Command and Address VIH CA DC DC Input Logic High Vr
22. ct SDA Serial Presence Detect Data input output REV 1 1 2 09 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2F4G64CB8HD5 9 N 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 Unbuffered DDR3 SDRAM DIMM DDR3 SDRAM Pin Assignment Pin Pin Front Pin Back Pin Front Pin Back Front Pin Back Pin Front Pin Back Vagos 121 Vss 31 0025 151 Vss 61 2 181 Ai 91 004 21 Vs DMS 2 Vs 122 DQ4 32 Va 152 di 62 182 Vo 92 212 00514 0514 NC DASZ E 000 123 DQ5 33 pass 153 0512 Q4 NC 183 V 93 DOSS 213 0051 150512 150514 4 001 124 Vss 34 DQS3 154 Vss 64 CKiNC 184 CKO 94 0055 214 Vss 5 125 35 155 X 0030 65 185 CKO 95 Vg 215 0046 6 0950 126 p 36 00926 156 0031 66 186 96 0042 216 0047 7 0050 127 Vss 37 DQ27 157 Vss 67 Vaerca 187 rd 97 DQ43 217 Vss 8 Va 128 DQ6 38 158 CBANC 68 Ea 188 AO 98 218 0052 DQ2 129 DQ7 39 CBO NC 159 CBS amp NC 69 189 Vp 99 DQ48 219 0053 10 003 130 Vss 40 CB1 NC 160 Vss 70 A10 AP 190 100 0049 220 Vss DM6 11 131 2012 44 161 DM amp DQS17 74 191 101 Vas 221 00515 TDQS17 NC TDOSIS NC DOS17 Mm NC 12 132 42 0058 162
23. d to Power Down enti tWRPDENmin WL 4 tCK av mE mr see IWRPDEN ab ava BL8MRS IWRPDENmax Timing of WRA command to Power Down entry IWRAPDENmin WL 4 WR 1 tWRAPDEN BL8MRS tWRAPDENmax Timing of WR command to Power Down entry BCAMRS tWRPDEN tWRPDENmin WL 2 tWR tCK avg tWRPDENmax nck Timing of WRA command to Power Down entry tWRAPDENmin WL 2 WR 1 tWRAPDEN BCAMRS tWRAPDENmax tREFPDENmin 1 Timing of REF command to Power Down entry tREFPDEN tREFPDENmax tMRSPDENmin tMOD min Timing of MRS command to Power Down entry tMRSPDEN tMRSPDENmax ODT Timings mr ODT high time without write command or ODTH4min 4 ODTH4 nCK with write command and BC4 ODTH4max ODTH8min 6 ODT high time with Write command and BL8 ODTH8 ODTH8max Asynchronous RTT turn on delay 2 tAONPD 2 8 5 Power Down with DLL frozen Asynchronous RTT turn off delay tAOFPD 2 8 5 Power Down with DLL frozen RTT turn on RTT Nom and RTT WR turn off time tAOF 0 3 0 7 tCK avg from ODTLoff reference RTT dynamic change skew Pos Wills Leveling Tinin LS TS First DQS DQS rising after tWLMRD write leveling mode is programmed 005 00058 delay after write leveling mode is programmed IWLDOSEN Sp ry T Write leveling setup time from rising CK
24. ecoder is disabled new commands are ignored but previous operations continue Rank 0 is selected by SO Rank 1 is selected by S1 When sampled at the positive rising edge of CK and falling edge of CK signals RAS CAS WE define the operation to be executed by the SDRAM Asserts on die termination for DQ DM DQS and DQS signals if enabled via the DDR3 SDRAM mode register The data write masks associated with one data byte In Write mode DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high In Read mode DM lines have no effect The data strobes associated with one data byte sourced with data transfers In Write mode the data strobe is sourced by the controller and is centered in the data window In Read mode the data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window DQS signals are complements and timing is relative to the cross point of respective DQS and DAQS If the module is to be operated in single ended strobe mode all DQS signals must be tied on the system board to Vss and DDR3 SDRAM mode registers programmed appropriately Selects which DDR3 SDRAM internal bank of four or eight is activated During a Bank Activate command cycle defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK During a Read or Write command cycle defines the column address when sampled at the cross p
25. ee product Description M2F2G64CB88D7N and M2F4G64CB8HDB5N are 240 Pin Double Data Rate DDR3 Synchronous DRAM Unbuffered Dual In Line Memory Module UDIMM organized as one rank of 256Mx64 2GB and two ranks of 512Mx64 4GB high speed memory array Modules use eight 256Mx8 2GB 78 ball BGA packaged devices and sixteen 256Mx8 4GB 78 ball BGA packaged devices These DIMMs are manufactured using raw cards developed for broad industry use as reference designs The use of these common design files minimizes electrical variation between suppliers All Elixir DDR3 SDRAM DIMMs provide a high performance flexible 8 byte interface in a 5 25 long space saving footprint The DIMM is intended for use in applications operating of 533MHz 667MHz clock speeds and achieves high speed data transfer rates of 1066Mbps 1333Mbps Prior to any access operation the device CAS latency and burst length operation type must be programmed into the DIMM by address inputs A0 A13 2GB 0 14 4GB and I O inputs BAO BA2 using the mode register set cycle The DIMM uses serial presence detect implemented via a serial EEPROM using a standard IIC protocol The first 128 bytes of SPD data are programmed and locked during module assembly The remaining 128 bytes are available for use by the customer REV 1 1 1 09 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2F4G64CB8HD5 9 N
26. ef 0 100 Vref 0 100 VIL CA DC DC Input Logic Low VSS Vref 0 100 VSS Vref 0 100 V 1 VIH CA AC Input Logic High Vref 0 175 Note 2 Vref 0 175 Note 2 V 1 VIL CA AC Input Logic Low Note 2 Vref 0 175 Note 2 Vref 0 175 V 1 VIH CA AC150 AC Input Logic High Vref 0 15 Note 2 Vref 0 15 Note 2 V 1 VIL CA AC150 Input Logic Low Note 2 Vref 0 15 Note 2 Vref 0 15 V 1 enn for 9 49 x VDD 0 51 x VDD 0 49 x VDD 0 51 x VDD v 3 4 Note 1 For input only pins except RESET Vref VrefCA DC 2 See Overshoot and Undershoot Specifications in the device datasheet 3 The ac peak noise on VRef may not allow VRef to deviate from VRefDQ DC by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV Single Ended AC and DC Input Levels for DQ and DM VIH DQ DC DC Input Logic High EN NM 0 100 Vref 0 100 VIL DQ DC Input Logic Low VSS Vref 0 100 VSS Vref 0 100 V 1 VIH DQ AC AC Input Logic High Vref 0 175 Note 2 Vref 0 15 Note 2 1 2 5 VIL DQ AC Input Logic Low Note 2 Vref 0 175 Note 2 Vref 0 15 1 2 5 Vneraipo Cine T Tor 0 49 x VDD 0 51 x VDD 0 49 x VDD 0 51 x VDD V Note 1 For input only pins except RESET Vref VrefDQ DC 2 See Overshoot and Undershoot Specifications in the device datasheet 3 The ac peak noise on VRef may not allow VRef to deviate from VRefDQ DC by more than 1 VDD for reference approx
27. egister Set command update delay to internal read or write delaytime command period JACTIO ACT or REF command period ee ICAS to CASH command delay eeo 4 ok Auto precharge write recovery precharge time _ WRerowdupiRP Kavg Multi Purpose Register Recovery Time MPR ok PRECHARGE commandperiod eas Standard Speed Bins tRRDmin max 4nCK ens ACTIVE to ACTIVE command period for 1KB page size tRRDmax tRRDmin max 4nCK 7 5ns ACTIVE to ACTIVE command period for 2KB page size IRRD max Four activate window for 1KB page size bw Four activate window for 2KB page size IFAW 5 Command and Address setup time to tlS base referenced to Vih ac Vil ac levels Command and Address hold time from CK CK tlH base 140 referenced to Vih dc Vil dc levels Command and Address setup time to CK CK tlS base AC150 65 125 referenced to Vih ac Vil ac levels Control and Address Input pulse width for each input _____ Timing SS SSS SSS See Power up and RESET calibration time zai Normal operation Full calibration time Normal operation Short calibration time 12008 Reset Timing a eee MU aaa tXPRmin max 5nCK tRFC min 10ns Exit Reset from CKE HIGH to a valid command tXPR Nl SetReesh Timings
28. gram 2GB 1 Rank 256Mx8 DDR3 SDRAMs eixir 50 5950 M paso DMO DM CS 005 595 100 pai JN 101 002 N 02 WY 103 Do 004 W 04 005 N 105 N 106 DQ7 N 107 za _ Dasi DQS1 M DM DM CS DQS bas 100 Dag JN 4 VO 1 DQ10 02 0011 103 D1 DQi2 N 04 0013 105 0014 N 1 06 0015 N 107 za 5052 DQS2 004 DM2 DM CS 005 DAS pais N 00 DQi7 1 pais 02 0019 N 03 02 0020 1 04 0021 105 0022 N 1 06 0023 N 1 07 za 5953 M DQS3 N T DM3 DM CS 005 595 0024 N 100 0025 101 DQ26 N 2 0027 N 1 03 D3 0028 1 04 0029 N 05 0030 1 06 0031 N 107 501 scL sao 3 A0 SPD 4 gt SDA sai gt 1 m gt A2 WP DDR3 SDRAM CKEO A 13 0 RAS CAS WE ODTO BA 2 0 50 DDR3 SDRAM N vop CK REV 1 1 09 2011 DQS4 M DQS4 N p DM4 DM cs Das 4 roo DQ33 J 4
29. he right to change products and specifications without notice M2F2G64CB88D7 H N M2F4G64CB8HD5 9 N 2GB 256M x 64 4GB 512M x 64 Wi PC3 8500 PC3 10600 e Unbuffered DDR3 SDRAM DIMM tRDPDENmin RL 4 1 Timing of RD RDA command to Power Down entry tRDPDEN tRDPDENmax Timing of WR command to Power Down entry IWRPDEN tWRPDENmin WL 4 tCK avg BL8OTF BL8MRS tWRPDENmax Timing of WRA command to Power Down entry IWRAPDENmin WL 4 WR 1 tWRAPDEN BL8MRS tWRAPDENmax Timing of WR command to Power Down entry BCAMRS tWRPDEN tWRPDENmin WL 2 tCK avg tWRPDENmax Timing of WRA command to Power Down entry tWRAPDENmin WL 2 WR 1 tWRAPDEN BC4MRS tWRAPDENmax tREFPDENmin 1 Timing of REF command to Power Down entry tREFPDEN tREFPDENmax tMRSPDENmin tMOD min Timing of MRS command to Power Down entry tMRSPDEN tMRSPDENmax ODT Timings NENNEN high time without write command or ODTH4min 4 ODTH4 with write command and 4 ODTH4max ODTH8min 6 ODT high time with Write command and BL8 ODTH8 ODTH8max Asynchronous RTT turn on delay tAONPD 2 8 5 Power Down with DLL frozen Asynchronous RTT turn off delay tAOFPD 2 8 5 Power Down with DLL frozen RTT turn on tAON e 4 RTT Nom and RTT WR turn off time tAOF 0 3 0 7 tCK avg from ODTLoff reference
30. nper min 1 0 68In n tJIT per min eo Cumulative error across n 13 14 49 50 cycles tERR nper tERR nper max 1 0 68In n tJIT per max ___ 005 DASH to DQ skew per group per access je S DQoutput hold DOSE DQlowimpedance time CKK 6 cps DQhihimpedenetimetromCK CKF kogo tts tDS base Data setup time to DQS DQS referenced to Vih ac Vil ac levels AC175 25 tDS base Data setup time to DQS DQS referenced to Vih ac Vil ac levels 150 75 0 tDH base Data hold time from DQS DQS referenced to Vih dc Vil dc levels DC100 0 and DM Input pulse width foreach input ow ps DQS DOS differential READ Preamble DOS DOSE differential READ Postamble DOS DASE differential output hightime jo oos ____ DOS DOSRdfeemiaowpulow m poss DOS DASE differential WRITE Preamble were 09 DOS DOSE differential WRITE Postamble west DOS DASE rising edge output access time from rising CK amp Di Di low i i QS and DQS low impedance time 42005 300 tCK avg Referenced from RL 1 DQS and DQS high impedance time tHZ DQS 300 tCK avg Referenced from RL BL 2 05 DASE differential input low pulse
31. oint of the rising edge of CK and falling edge of CK In addition to the column address AP is used to invoke autoprecharge operation at the end of the burst read or write cycle If AP is high autoprecharge is selected and BAO BAn defines the bank to be precharged If AP is low autoprecharge is disabled During a Precharge command cycle AP is used in conjunction with BAO BAn to control which bank s to precharge If AP is high all banks will be precharged regardless of the state of BAO BAn inputs If AP is low then BAO BAn are used to define which bank to precharge Data Input Output pins Power supplies for core I O Serial Presence Detect Temp sensor and ground for the module Reference voltage for SSTL15 inputs This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor A resistor must be connected from the SDA bus line to on the system planar to act as a pull up This signal is used to clock data into and out of the SPD EEPROM and Temp sensor Address pins used to select the Serial Presence Detect and Temp sensor base address The EVENT pin is reserved for use to flag critical module temperature This signal resets the DDR3 SDRAM NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2FA4G64CB8HD5 9 N 2GB 256M x 64 512M x 64 PC3 8500 PC3 10600 Unbuffered DDR3 SDRAM DIMM Functional Block Dia
32. s Cumuatveemoraeoss3cydes HERS tops S Cumulative eroracross4cycles Cumulative error across Scycles Cumulative eror across 6oyoles Cumulative error across 7 oyoles HERAT Cumulative error across 8 cycles tERR s Cumulative error aoross 9 oyoles __ __ ts S Cumulative error across 10 cycles __ 25 265 S Cumulative error across 11 cycles 20 Cumulative error across i2cydes tERR nper min 1 0 68In n tJIT per min s Cumulative error across n 13 14 49 50 cycles tERR nper tERR nper max 1 0 68In n tJIT per max pump m Mcr DOS DAS to DA skew per group peraccess feasa 100 5 0056 __ DOlowimpedane meromCK CK zoo so S DQhighimpedenetimetromCK CKF tDS Data setup time to DQS DQS referenced to Vih ac Vil ac levels 175 tDS base Data setup time to DQS DQS referenced to Vih ac Vil ac levels AC180 30 tDH base Data hold time from DQS DQS referenced to Vih dc Vil dc levels DC100 DQandDMipupusewidhforeachinut ow p sss mee cce c oen DQS DOS differential READ Preamble meE 09 Nee cK DOS 005 differential READ Postamble ___ meSr os DOS
33. s relative to Vss 0 4 V 1 975 V V 1 Storage Temperature 55 to 100 C 1 2 Note 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 VDD and VDDQ must be within 300 mV of each other at all times and VREF must be not greater Operating temperature Conditions Normal Operating Temperature Range 0 to 85 1 OPER Extended Temperature Range 85 to 95 C T 3 Note 1 Operating Temperature TOPER is the case surface temperature on the center top side of the DRAM For measurement conditions please refer to the JEDEC document JESD51 2 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported During operation the DRAM case temperature must be maintained between 0 to 85 C under all operating conditions 3 Some applications require operation of the DRAM in the Extended Temperature Range between 85 and 95 C case temperature Full specifications are supported in this range but the following
34. width 0o45 05 DOS differential input high pulse width 045 DOS DASE rising edge to CK rising edge Doass os DOS DASE falling edge setup time to CK amp rsmgedge 055 oe DOS DOS falling edge hold time from CK rising edge SH ice ___ REV 1 1 12 09 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2F4G64CB8HD5 9 N 2GB 256M x 64 4GB 512M x 64 A PC3 8500 PC3 10600 e Unbuffered DDR3 SDRAM DIMM tRTPmin max 4nCK 7 5ns Internal READ Command to PRECHARGE Command delay tRTP tRTPmax Delay from start of internal write WTR tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery time Register Set command cycle time web 00 ck tMODmin max 12nCK 15ns Mode Register Set command update delay to internal read or write delaytime eeo 0 0 0 0 0 0 0 0 0 0 S command period IO ACT or REF command period ee ICAS to CASH command delay too Auto precharge write recovery precharge time __ _ _ WReromdupiRe Kavg Multi Purpose Register Recovery Time MPR PR
35. xit timing tCKESR tCKESRmax Valid Clock Requirement after Self Refresh Entry SRE ICKSRE tCKSREmin max 5 nCK 10 ns or Power Down Entry PDE tCKSREmax in Valid Clock Requirement before Self Refresh Exit SRX tCKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax tXPmin max 3nCK 7 5ns tXPmax A n 2 Power Down Timings Exit Power Down with DLL on to any valid command Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL tXPDLLmin max 10nCK 24ns tXPDLLmax tCKEmin max 3nCK 5 625ns tCKE tCKEmax tCPDEDmin 1 tCPDED tCPDEDmin tPDmin tCKE min tPDmax Exit Precharge Power Down with DLL frozen to commands XPDLL requiring a locked DLL CKE minimum pulse width Command pass disable delay Power Down Entry to Exit Timing Timing of ACT command to Power Down entry tACTPDENmax tPRPDENmax tRDPDENmin RL 4 1 Timing of PRE or PREA command to Power Down entry Timing of RD RDA command to Power Down entry 5 T gt MEN E U 9 g tRDPDENmax REV 1 1 13 09 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F2G64CB88D7 H N M2F4G64CB8HD5 9 N 2GB 256M x 64 4GB 512M x 64 Wi PC3 8500 PC3 10600 e Unbuffered DDR3 SDRAM DIMM Timing of WR comman

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