Silicon Power 4GB DDR3 1600MHz SO-DIMM
Contents
1. 21 0 0 827 TY _ 24 8 0 976 1 TYP Note 1 All dimensions are in millimeters inches MAX MIN or typical TYP where noted Note 2 The dimensional diagram is for reference only 7 Rev 1 4 Dec 2011 a pee DDR3 SODIMM iB a z ii Product Specification Simplified Mechanical Drawing x16 2Ranks Front view 3 80 0 150 67 75 2 667 67 45 2 656 30 15 1 187 2 0 0 079 R 2 1 80 n 29 85 1 175 20 0 0 787 TYP 6 0 0 236 O ae ln en 1 10 0 083 SAN SAW gh fe pe ou WW 0 90 0 035 e TYP TYP TYP isit Pin 1 Pin 203 l Je 63 60 2 504 _______ TYP Back view 4 0 0 157 2 55 0 10 TYP TYP Pin 2 Pin 204 ee We 12 m 39 0 1 535 r fe 21 0 0 827 TYP TYP 24 8 0 376 TYP Note 1 All dimensions are in millimeters inches MAX MIN or typical TYP where noted Note 2 The dimensional diagram is for reference only 8 Rev 1 4 Dec 20112. EVENTH 43 vss 95 A 147 Daso 199 VDDSPD 44 vss 96 A2 148 Dass 200 SDA 45 DOS2 o7 At 19 Das 201 sa se DW fes ao 150 vss j202 sct 47 Dasz 99 vob 151 vss 203 vrt 48 vss too vob 152 Dass 204 VIT 49 vss 101 cko 153 Dm5 50 DQZZ 102 CK1 154 pass 51 pas 103 cKo 155 vss 52 paz io4 ck ise vss 3 Rev 1 4 Dec 2011 a pee DDR3 SODIMM iB a z Product Specification Pin Description Description Address inputs Provide the row address for ACTIVE commands and the column address and auto precharge bit for READ WRITE commands to select one location out of the memory array in the respective bank A10 is sampled during a PRECHARGE command to determine A0 A44 aout whether the PRECHARGE applies to one bank A10 LOW or all banks A10 HIGH If only p one bank is to be precharged the bank is selected by BA A12 is sampled during READ and WRITE commands to determine if burst chop on the fly will be performed The address inputs also provide the opcode during mode register command set A0 A13 128Mx8 256Mx8 Bank address inputs BAO BA1 define to which device bank an ACTIVE READ WRITE or BAO BA2 Input PRECHARGE command is being applied BAO BA1 define which mode register including MR EMR EMR 2 and EMR 3 is loaded during the LOAD MODE command CKO CKO input Fark CK and CK are differential clock inputs All address and contr
3. 99 9 2GB 256Mx64 PC3 8500 DDR3 1066 128Mx16 2Ranks PC3 10600 DDR3 1333 999 PC3 8500 DDR3 1066 288 208NK04 RG3 10600 DDR3 1333 999 128Mx8 2Ranks PC3 12800 DDR3 1600 11 11 11 2 4GBx2Kit Package PC3 8500 DDR3 1066 2 4GB x 2 Kit Package PC3 10600 DDR3 1333 999 Note 1 This document supports all STU Series DDR3 204Pin SODIMM products 2 Some item was being EOL in this list Please contact with our sales Dep 3 All part numbers end with a double digit code is for customize use only Example SP001GBSTU133S02 XX 2 Rev 1 4 Dec 2011 ou oe DDR3 SODIMM iB a z Product Specification Pin Assignments 204 Pin DDR3 SODIMM Front 204 Pin DDR3 SODIMM Back 4 vas 56 paz 108 Bai 160 DA 5 Dao 57 Daz 109 Bao 161 vss 6 Das ss paz 110 Rase 162 vss 8 vss 6s vss 12 vop 164 DQsZ 9 ves et vss 13 we 165 Dass 10 paso 62 pasa 114 sog 166 Dass a vss 66 vss 118 vop 170 DM6 16 Da es Daso 120 opt 172 vss 17 Das e9 Dazz 121 Sik 173 vss 23 Da 75 vob 127 vss 179 vss 28 Dm1 80 ncia14 132 Dasz 184 vss 32 vss s4a an 136 Dm4 188 Das7 34 pata s6 A7 138 vss 190 vss 37 vss 9 as 141 pasa tes pasa 38 vss o0 as 142 Dass 194 Daes 39 pae 91 As 143 pass 195 vss 40 pazo 92 as i44 vss 196 vss 4 Da 93 voo 145 vss 197 sao 42 paz 94 voo t46 Dasa 198
4. a pee DDR3 SODIMM iB a z ii Product Specification Features e DDR3 functionality and operations supported as defined in the component data sheet e 204pin small outline dual in line memory module SODIMM e Fast data transfer rates PC3 8500 PC3 10600 PC3 12800 e Single or Dual rank e 1GB 128 Meg x 8 2GB 256 Meg x 64 4GB 512Meg x 64 e Voo Vppa 1 5V 0 075V e Vppspp 3 0V to 3 6V e Reset pin for improved system stability e Nominal and dynamic on die termination ODT for data strobe and mask signals e Fixed burst chop BC of 4 and burst length BL of 8 via the mode register set MRS e Adjustable data output drive strength e Fly by topology e Terminated control command and address bus e Serial presence detect SPD EEPROM e Gold edge contacts e Pb free 1 Rev 1 4 Dec 2011 a pee DDR3 SODIMM iB a z Product Specification Module Specification Module Density amp Timing Part Number Bandwidth Data Rate Partnumber getan EMT Bandwidth Data Rate MO e 1GB 128Mx64 PC3 8500 DDR3 1066 128Mx8 1Rank PC3 10600 DDR3 1333 99 9 1GB 128Mx64 PC3 8500 DDR3 1066 128Mx8 1Rank PC3 10600 DDR3 1333 999 1GB 128Mx64 PC3 8500 DDR3 1066 64Mx16 2Ranks PC3 10600 DDR3 1333 9 9 9 PC3 8500 DDR3 1066 eee posib PC3 10600 DDR3 1333 999 256Mx8 1Rank PC3 12800 DDR3 1600 11 11 11 PC3 8500 DDR3 1066 al AAA PC3 10600 DDR3 1333 99 9 128Mx8 2Ranks PC3 12800 DDR3 1600
5. agram is for reference only 5 Rev 1 4 Dec 2011 a pee DDR3 SODIMM iB a z ii Product Specification Simplified Mechanical Drawing x16 1Rank Front view 67 75 2 667 67 45 2 656 2 0 0 079 R 2X 30 15 1 187 1 8 ai 29 85 1 175 20 0 0 787 TYP 6 0 0 236 TYP Iil Ii i N X Pin 1 1 0 0 039 0 45 0 018 0 60 0 024 Pin 203 2 0 0 079 TYP TYP TYP TYP 63 60 2 504 iii Back view No components this side of module 2 55 0 10 i Il I SOTE TYP Ncp 204 3 0 0 12 i E A 2 TYP 39 0 1 535 gt 21 0 0 827 TYP TYP 24 8 0 976 TYP Note 1 All dimensions are in millimeters inches MAX MIN or typical TYP where noted Note 2 The dimensional diagram is for reference only 2 45 0 096 MAX _1 1 0 043 0 9 0 035 6 Rev 1 4 Dec 2011 a pee DDR3 SODIMM iB a z ii Product Specification Simplified Mechanical Drawing x8 2Ranks l 3 8 0 15 Front view MAX 67 75 2 667 67 45 2 656 2 0 0 079 R 2X 30 15 1 187 1 8 a 29 85 1 175 20 0 0 787 TYP 6 0 0 236 TYP 1 0 kimen war pov 0 60 l 024 ee 2 0 0 079 a ai y diyo ae yo 0 9 0 035 TYP Pin 1 i d 63 6 2 504 ey daki TYP Back view 2 55 0 1 m TYP f Pin 204 gt lt 3 0 0 12 lika TYP 39 0 1 535
6. ol input signals are CK1 CK1 EX sampled on the crossing of the positive edge of CK and negative edge of CK Output data DQs and DQS DQSA is referenced to the crossings of CK and CK Clock enable CKE registered HIGH activates and CKE registered LOW deactivates kt km clocking circuitry on the DDR3 SDRAM Data input mask DM is an input mask signal for write data Input data is masked when DM is DMO DM7 oti sampled HIGH along with that input data during a write access DM is sampled on both p edges of DQS Although DM pins are input only the DM loading is designed to match that of DQ and DQSTpins ODTO On die termination ODT registered HIGH enables termination resistance internal to the ODT1 Input DDR3 SDRAM When enabled ODT is only applied to the following pins DQ DQS DQS and DM The ODT input will be ignored if disabled via the LOAD MODE command RAS CAS Aout Command inputs RAS CAS and WE along with S define the command being WE p entered Reset RESET is an active LOW CMOS input referenced to Vss The RESET input receiver RESET o is a CMOS input defined as a rail to rail signal with DC HIGH 2 0 8 xVpp and DC LOW lt 0 2 LVCMOS xV op SO S1 eerie S enables registered LOW and disables registered HIGH the command SAI2 0 net Presence detect address inputs These pins are used to configure the SPD EEPROM 2 0 nes address range Serial clock for presence detect SCL is used to synchronize the
7. presence detect data transfer to and from the module Data strobe Output with read data input with write data for source synchronous operation DQS0 DQS Edge aligned with read data center aligned with write data Serial presence detect data SDA is a bidirectional pin used to transfer addresses and data into and out of the SPD EEPROM on the module Supply oe supply 1 5V 0 075V The component Vpp and Vppa are connected to the module Temperature sensor SPD EEPROM power supply 3 0V to 3 6V NC Noconnect These pins are not connected on the module NU Not used These pins are not used in specific module configuration operations Input 4 Rev 1 4 Dec 2011 a pee DDR3 SODIMM iB a z ii Product Specification Simplified Mechanical Drawing x8 1Rank Front view 67 75 2 667 67 45 2 656 2 0 0 079 R 2X 30 15 1 187 1 8 an 29 85 1 175 20 0 0 787 TYP 6 0 0 236 IN san ee N Pin 1 1 0 0 039 0 45 0 018 0 6 0 024 Pin 203 2 0 0 079 TYP TYP TYP TYP AA 636 2 504 ________ TYP Back view 4 0 0 157 2 55 0 1 0 1 TYP TYP A an a gt 3 0 A 12 NOU Pin 204 Pin 2 39 0 1 535 1 jf 21 0 as ni TYP 248 0 976 gt TYP 3 8 0 15 MAX 1 1 0 043 0 9 0 035 Note 1 All dimensions are in millimeters inches MAX MIN or typical TYP where noted Note 2 The dimensional di
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