Dataram 1GB DD2-800
Contents
1. Specifications and Conditions T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Test Condition Max unit Value Operating CKE is HIGH CS is HIGH between valid commands Address Bank Active IppO Senate SD 360 mA bus inputs are switching Data bus inputs are switching Precharge Current Operating One lout 0 mA BL 4 CL 5 ns AL 0 CKE is HIGH CS is Bank Active Read 1 1 HIGH between valid commands Address bus inputs switch 408 mA Precharge Current ing Precharge Power All banks idle CKE is LOW Other control and address bus inputs Ipp2P 80 Down Current are stable Data bus inputs are floating Precharge Quiet 20 All banks idle is HIGH CS is HIGH Other control 160 Standby Current dress bus inputs are stable Data bus inputs are floating Precharge Standby All banks idle CKE is HIGH CS is HIGH Other control and ad Current dress bus inputs are switching Data bus inputs are switching Active PowarDown All banks open CKE is LOW Other control and address bus in Current 03 puts are stable Data bus inputs are floating Fast Power down 184 mA exit Mode Register bit 12 0 All banks open tras 70 ms is HIGH CS is HIGH between Active Standby Ipp3N valid commands Other control and address bus inputs are 296 mA Current be switching Data bus inputs are switching2. wue aed Performance 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit DQ Output Access Time from Clock tac 400 400 ps CAS to CAS Command Delay 2 tck Clock High Level Width tcH 0 48 0 52 Clock Cycle Time tck 2500 8000 ps Clock Low Level Width teL 0 48 0 52 tck Data Input Hold Time after DQS Strobe tou 125 ps DQ Input Pulse Width toipw 0 35 tck DQS Output Access Time from Clock tposck 350 350 ps Write DQS High Level Width tposH 0 35 tck Write DQS Low Level Width toast 0 35 tck DQS Out Edge to Data Out Edge Skew toasa 200 ps Data Input Setup Time Before DQS Strobe tos 50 ps DQS Falling Edge from Clock Hold Time tosH 0 2 DQS Falling Edge to Clock Setup Time toss 0 2 tck Clock Half Period tup minimum of tcu or tci ns Address and Command Hold Time after Clock 250 Address and Command Setup Time before Clock tis 175 ps Load Mode Command Cycle Time tMRD 2 tck DQ to DQS Hold tup tans Data Hold Skew Factor tans 400 ps Active to Precharge Time tras 45 70K ns Active to Active Auto Refresh Time 60 ns RAS to CAS Delay trop 15 ns Average Periodic Refresh Interval tREFI 7 8 Hs Auto Refresh Row Cycle Time terc 127 5 ns Row Precharge Time trp 15 ns Read DQS Preamble Time RPRE 0 9 1 1 tck Read DQS
3. 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 0 125 Vpp 0 300 V Logical Low Logic 0 0 300 VREF 0 125 V AC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 ViH AC VREF 0 250 V Logical Low Logic 0 ViL AC Vrer 0 250 V Document 06833 Revision A 28 Sep 11 Dataram Corporation 2011 Page 4 yn DTM67220 Opening wue ard Performance 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM Differential Input Logic Levels T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note DC Input Signal Voltage ViN DC 0 300 Vpp 0 300 V 1 DC Differential Input Voltage 0 250 Vpp 0 600 V 2 AC Differential Input Voltage 0 500 Vpp 0 600 V 3 AC Differential Cross Point Voltage Vix AC 0 50 0 175 0 50 0 175 V 4 Notes 1 specifies the allowable DC excursion of each input of a differential pair 2 Vip po specifies the input differential voltage i e the absolute value of the difference between the two voltages of a differential pair 3 Specifies the input differential voltage required for switching 4 The typical value of Vixiac is expected to be 0 5 Vpp and is expected to track
4. All banks open Continuous burst writes BL 4 CL 5 Operating Burst AL 0 tras 70 ms is HIGH CS is HIGH between valid 576 Write Current pe commands Address bus inputs are switching Data bus inputs are switching All banks open Continuous burst reads lout 0 mA BL 4 Operating Burst IoAR CL 5 tcx AL 0 tras 70 ms is HIGH CS is HIGH be 640 mA Read Current DU tween valid commands Address bus inputs are switching Data bus inputs are switching Burst Refresh Cur Refresh command at every 75 ns CKE is HIGH CS is HIGH be Ipp5 tween valid commands Other control and address bus inputs are 840 mA rent 53 switching Data bus inputs are switching Self Refresh Cur CK and CK at 0 V CKE lt 0 2 V Other control and address bus Ipp6 TM 80 rent inputs are floating Data bus inputs are floating All bank interleaving reads lour 0 mA BL 4 CL 5 tcx Operating Bank In AL 70 ns tarp 7 5 ns CKE is HIGH CS is HIGH between terleave Read Cur Ipp7 _ 1280 mA rent valid commands Address bus inputs are stable during deselects Data bus inputs are switching Note For all measurements 2 5 ns tac 60 ns trcn 15 ns tras 45 ns and tre 15 ns unless otherwise specified All currents are based on DRAM absolute maximum values Document 06833 Revision A 28 Sep 11 Dataram Corporation 2011 Page 6 DTM67220
5. The information contained in this document has been carefully checked and is believed to be reliable However Da taram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trade marks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06833 Revision A 28 Sep 11 Dataram Corporation 2011 Page 13
6. R A 13 0 AI13 0 R 1 IRAS Q AAN O RASR SDRAM X 4 ICK1 ICAS Q AA O CASR O A AN O 3 OHMS CKEO O VW CKEOR DECOUPLING O A N ODTOR VopsPD t Serial PD VDD T All Devices Vss All Devices SCL SERIAL PD SDA SA0 SA1 SA2 Document 06833 Revision A 28 Sep 11 Dataram Corporation 2011 Page 3 yn DTM67220 DIL Value aed Performa 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TsTORAGE 55 100 Ambient Temperature Operating Ta 0 70 DRAM Case Temperature Operating TcasE 0 85 C Voltage on Vpp relative to Vss 0 5 2 3 V Voltage on Any Pin relative to Vss Vin Vout 0 5 2 3 V 95C at 2x Refresh Recommended DC Operating Conditions T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Vpp 1 7 1 8 1 9 V I O Reference Voltage VREF 0 49 Vpp 0 50 Vpp 0 51 V 1 Bus Termination Voltage Vit Vrer 0 04 VREF Vrer 0 04 V Notes 1 The value of Vggr is expected to equal one half Vpp and to track variations in the Voo DC level Peak to peak noise on Vrer may not exceed 1 of its DC value DC Input Logic Levels Single Ended
7. variations in Vpp Capacitance 25 C f 100 MHz PARAMETER Pin Symbol Min Max Unit Input Capacitance Clock CK 1 0 CK 1 0 CIN1 4 8 pF Input Capacitance Address 13 0 RAS CAS WE ODTO CKEO SO CIN2 14 pF and Control Input Output Capacitance DQ 63 0 DQS 7 0 DQS 7 0 DM 7 0 CIO 2 5 3 5 pF DC Characteristics T4 0 to 70 C Voltage referenced to 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current Command and Address lu 80 80 pA 1 Input Leakage Current 50 ODTO lu 40 40 1 Input Leakage Current CK 1 0 CK 1 0 lu 30 30 1 Input Leakage Current lu 10 10 1 Output Leakage Current DQS DQ loz 10 10 pA 2 Output Minimum Source DC Current 13 4 3 Output Minimum Sink DC Current lot 13 4 mA 4 Notes 1 These values are guaranteed by design and are tested on a sample basis only 2 DQx and ODT are disabled and 0 V lt S 3 Voo 1 7 V Vout 1420 mV Vpp lou must be less than 21 Ohms for values of Vour between Von and Voo 280 mV 4 Vpp 1 7 V Vout 280 mV Vour lo must be less than 21 Ohms for values of Vour between 0 V 280 mV Document 06833 Revision A 28 Sep 11 Dataram Corporation 2011 Page 5 EYgDATARAM Opening Vue and Performance 1GB DTM67220 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM
8. Analysis Probe Characteristics UNUSED 0x00 Extension of Byte 41 tRC and Byte 42 tRFC ns 0x06 40 Add this value to byte 41 0 Add this value to byte 42 0 5 SDRAM Device Minimum Active to Active Auto Refresh Time tRC 41 ns 60 0x3C SDRAM Device Minimum Auto Refresh to Active Auto Refresh 42 Command Period tRFC ns 127 5 Ox7F 43 SDRAM Device Maximum Cycle Time tCK max ns 8 0x80 44 SDRAM Dev DQS DQ Skew for DQS amp DQ signals tDQSQ ns 0 2 0x14 45 DDR SDRAM Device Read Data Hold Skew Factor tQHS ns 0 3 Ox1E 46 PLL Relock Time us UNUSED 0x00 DRAM maximum Case Temperature Delta Degree 0x00 47 DT4R4W Delta Bits 0 3 Tcasemax delta Bits 7 4 48 Thermal Resistance of DRAM Package from Top Case to Ambient 58 0x74 Psi T A DRAM C Watt DRAM Case Temperature Rise from Ambient due to Activate Precharge 0x58 Mode Bits DTO Mode Bits Degree C 49 Bit 0 If 0 DRAM does not support high temperature self refresh entry 0 Bit 1 If 0 Do not need double refresh rate for the proper operation 0 Bits 2 7 6 6 50 DRAM Case Temperature Rise from Ambient due to Precharge Quiet 44 0 2 Standby DT2N DT2Q Degree DRAM Case Temperature Rise from Ambient due to Precharge 91 Power Down DT2P Degree C O18 a 52 DRAM Case Temperature Rise from Ambient due to Active Standby 6 0x28 DT3N Degree C 53 DRAM Case temperature Rise from Ambient due to Active Power 33 0x42 Down with Fas
9. DTM67220 1GB wt bite bere ten reds n itm x Features 200 pin JEDEC SO DIMM Dual sided assembly 67 600mm 2 661 wide by 30 0mm 1 181 high Operating Voltage 1 8 V 0 1 Type SSTL 18 Data Transfer Rate 6 4 Gigabytes sec Bursts Length 4 and 8 CAS Latencies 4 5 and 6 Programmable I O driver strength OCD Programmable On Die Termination ODT Differential Redundant Data Strobe signals SDRAM Addressing Row Col Bank 14 10 3 One Physical Rank Fully RoHS Compliant Pin Configurations Front side Back side 1 A1 DM2 3 Vas Vss 5 pao A10 AP DQ22 DQ23 9 Va Vss 11 DQSO 0028 13 paso DQ29 15 Vas Vss 17 DQ2 DQS3 19 53 21 Vss Vss 23 DQ8 DQ30 25 DQ9 DQ31 27 Vas Vss 29 DQS1 CKE1 31 DQS1 33 Vss NC A15 35 DQ10 NC A14 37 DQ11 39 Vss 11 41 Vss AT 43 DQ16 A6 45 DQ17 Voo 47 Vss A4 49 DQS2 VopSPD 50 Event 100 A2 not used on the DTM67220 ge are Ssss 200 1Rx8 Unbuffered Non ECC DDR2 SO DIMM Identification DTM67220 128Mx64 1GB 1Rx8 PC2 6400S 666 12 F1 Performance range Clock Module Speed CL trcp 400 MHz PC2 6400 6 6 6 333 MHz PC2 5300 5 5 5 266 MHz PC2 4200 4 4 4 Description The DTM67220 assembly is a 128Mx64bit Un buffered Non ECC memory module which conforms to JEDEC s DDR2 PC2 6400 standard The assem bly
10. Postamble Time trest 0 4 0 6 Row Active to Row Active Delay trRD 7 5 ns Internal Read to Precharge Command Delay 7 5 ns Write DQS Preamble Time twPRE 0 35 tck Write DQS Postamble Time twpst 0 4 0 6 Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR 7 5 ns Exit Self Refresh to Non Read Command txsnr tarc min 10 ns Exit Self Refresh to Read Command txsrp 200 tck Document 06833 Revision A 28 Sep 11 Dataram Corporation 2011 Page 7 yin DTM67220 Opening wue and Performance 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM SERIAL PRESENCE DETECT MATRIX Byte Function Value Hex 0 Number of Bytes Utilized by Module Manufacturer 128 bytes 0x80 1 Total number of Bytes in Serial PD device 256 bytes 0x08 2 Memory Type DDR2 SDRAM 0x08 3 Number of Row Addresses 14 OxOE Number of Column Addresses 10 Ox0A Module Attributes Number of Ranks Package and Height 0x60 of Ranks 1 5 Card on Card No DRAM Package Planar Module Height 30mm 6 Module Data Width 64 0x40 7 Reserved UNUSED 0x00 8 Voltage Interface Level of this assembly SSTL 1 8V 0x05 9 SDRAM Cycle time Max Supported CAS Latency CL X tCK ns 2 5 0x25 10 SDRAM Access from Clock Highest CAS latency ns 0 4 0 40 DIMM configuration type No
11. consists of one rank comprised of eight 128Mx8 DDR2 SDRAMs in a 60 Ball FBGA package A 2Kbit EEPROM for serial presence detect pro vides critical timing and configuration information used by the system to identify and configure the memory The assembly is a Small Outline Dual In line Mem ory Module intended for mounting into 200 pin edge connector sockets Pin Names Pin name Function RAS Row address strobe 154 0047 Column address strobe BA1 156 Vss IWE Write enable RAS 158 DQ52 IS 1 0 Chip select input 150 160 DQ53 CK 1 0 CK 1 0 Differential Clock inputs 162 Vss CKE 1 0 Clock enable input ODT 164 CK1 BA 2 0 Bank select input A13 166 CK1 A 15 0 Address input Multiplexed Vop 168 Vss ODT 1 0 On Die Termination NC 170 DM6 DQS 7 0 DQS 7 0 Data strobes Vss 172 Vss DM 7 0 Data masks DQ36 174 DQ54 DQ 63 0 Data I Os Data bus DQ37 176 DQ55 SCL Serial clock Vss 178 Vss SDA Serial data DM4 180 DQ60 SA 1 0 Address EEPROM Vss 182 DQ61 Event Temperature sensing DQ38 184 Vss VREF Reference voltage DQ39 186 DQS7 VDD Power supply 1 8V 0 1V Vss 188 DQS7 VSS Ground DQ44 190 Vss VDDSPD Serial EEPROM power supply DQ45 192 DQ62 NC No connects Vss 194 DQ63 DQS5 196 Vss DQS5 198 SA0 Vss 200 SA1 Document 06833 Revision A 28 Sep 11 Dataram Corporation 2011 Page 1 DTM67220 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM Fr
12. n parity Parity or ECC 0x00 Data Parity Data ECC Address Command Parity 11 TBD TBD TBD TBD TBD 12 Refresh Rate Type us 7 8 SR 0x82 13 Primary SDRAM Width 8 0x08 14 Error Checking SDRAM Width None 0x00 15 Reserved UNUSED 0x00 SDRAM Device Attributes Burst Lengths Supported 0 0 TBD TBD Burst Length 4 X 16 Burst Length 8 X TBD TBD TBD TBD 17 SDRAM Device Attributes Number of Banks on SDRAM Device 8 0x08 18 SDRAM Device Attributes CAS Latency 0x70 Document 06833 Revision A 28 Sep 11 Dataram Corporation 2011 Page 8 D Pte DTM67220 wue and Pesfomaeur 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM TBD TBD Latency 2 Latency 3 Latency 4 X Latency 5 X Latency 6 X TBD 19 DIMM Mechanical Characteristics Max module thickness mm x lt 3 80 0x01 DIMM type information 0x04 Regular RDIMM 133 35mm Regular UDIMM 133 35mm SODIMM 67 6mm X 20 Micro DIMM 45 5mm Mini RDIMM 82 0mm Mini UDIMM 82 0mm TBD TBD SDRAM Module Attributes Refer to Byte20 for DIMM type information 0x00 Number of active registers on the DIMM N A for UDIMM 1 Number of PLL on the DIMM N A for UDIMM 0 21 FET Switch External Enable No TBD Anal
13. ont view 67 600 2 661 30 000 1 181 4 000 157 2 150 leg 47 400 2 540 Min 130 i _ 11 400 1 866 100 Min 449 4 200 165 63 000 2 480 i Back view Side view 3 500 Max 138 Max 4 000 Min 157 Min 1 000 100 0403 004 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches Oo a C KG CN CCUN MIC C MM lM Document 06833 Revision A 28 Sep 11 Dataram Corporation 2011 Page 2 Value ard Performan ZIZ DTM67220 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM 3 OHMS SO DMRO DMR4 Piso ne DQS DQS CS DM DM DQS CS DM DQR 7 0 V O 7 0 DQR 39 32 I O 7 0 DM DQS CS DM DQR 47 40 O 1 0 7 0 DQR 15 8 DMR2 DMR6O DQSR2 DQRS6 IDQSR2 DQS DQS jcs DM DM DQS jcs DM DQR 23 16 I O 7 0 DQR 55 48 VO 7 0 DMR3 DMR7 O DQSR3 DQRS7 1005830 DASR7O DQS DQS CS DM DM DQS CS DM DQR 31 24 VO 7 0 DQR 63 56 0 1 0 7 0 22 OHMS DQ 63 0 O O DQR 63 0 DQS 7 0 O VW O DQSR 7 0 DQS 7 0 O O DQSRI7 0 2X 200 OHMS DM 7 0 O V O DMR 7 0 co SDRAM X 4 CKO GLOBAL SDRAM CONNECTS 10 5 2 X 200 OHMS 2 0 O VW O BA 2 0
14. t PDN Exit DT3Pfast Degree C Document 06833 Revision A 28 Sep 11 Dataram Corporation 2011 Page 10 D DTM67220 1GB DATARAM Value aed Performs DRAM Case temperature Rise from Ambient due to Active Power 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM a Down with Slow PDN Exit DT3Pslow Degree C 006 DRAM Case Temperature Rise from Ambient due to Page Open Burst Ox4A Read DT4R4W Mode Bit DT4R DT4R4W Mode Bit Degree C 55 Bit 0 0 if DT4W is greater than DT4R 0 DTAR Bits 1 7 14 8 DRAM Case Temperature Rise from Ambient due to Burst Refresh 56 DT5B Degree C exe 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave 31 Ox3E Reads with Auto Precharge DT7 Degree C Thermal Resistance of PLL Package from Top to Ambient Psi T A 58 PLL C Watt UNUSED 0x00 Thermal Resistance of Register Package from Top to Ambient Psi T 59 A Register C Watt UNUSED 60 PLL Case Temperature Rise from Ambient due to PLL Active DT PLL UNUSED 0x00 Active Degree Register Case Temperature Rise from Ambient due to Register Ac 0x00 tive Mode Bit DT Register Active Mode Bit 61 Bit O Unit for Bits 2 7 is 0 75C 0 75 Bit 1 RFU Default 0 0 Register Active Bits 2 7 0 62 SPD Revision Revision 1 2 0x12 63 Checksum for By
15. tes 0 62 0x41 64 Module Manufacturer s JEDEC ID Code Dataram ID Ox7F 65 Module Manufacturer s JEDEC ID Code Dataram ID 0x91 66 71 Module Manufacturer s JEDEC ID Code UNUSED 0x00 72 Module Manufacturing Location UNUSED 0x00 73 Module Part Number D 0x44 74 Module Part Number A 0x41 75 Module Part Number T 0x54 76 Module Part Number A 0x41 77 Module Part Number R 0x52 78 Module Part Number A 0x41 79 Module Part Number M Ox4D 80 Module Part Number 0x20 81 Module Part Number 6 0x36 82 Module Part Number 7 0x37 Document 06833 Revision A 28 Sep 11 Dataram Corporation 2011 Page 11 yin DTM67220 vig Value and Pesformas 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM 83 Module Part Number 0x32 84 Module Part Number 0x32 85 Module Part Number 0x30 86 90 Module Part Number 0x20 91 92 Module Revision Code UNUSED 0x00 93 94 Module Manufacturing Date UNUSED 0x00 95 Module Serial Number S 0x53 96 Module Serial Number E 0x45 97 Module Serial Number R 0x52 98 Module Serial Number 0x23 ree Manufacturer s Specific Data UNUSED 0x00 Document 06833 Revision A 28 Sep 11 Dataram Corporation 2011 Page 12 DTM67220 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM ree DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved
16. ysis probe installed No TBD SDRAM Device Attributes General 0x03 Includes Weak Driver X Supports 50 ohm ODT X Supports PASR Partial Array Self Refresh 22 TBD TBD TBD TBD TBD 23 Minimum Clock Cycle Time at Reduced CAS Latency CL X 1 ns 3 0x30 24 Maximum Data Access Time tAC from Clock at CL X 1 ns 0 4 0x40 25 Minimum Clock Cycle Time at CL X 2 ns 3 75 Ox3D 26 Maximum Data Access Time tAC from Clock at CL X 2 ns 0 4 0x40 27 Minimum Row Precharge Time tRP ns 15 0x3C 28 Minimum Row Active to Row Active Delay tRRD ns 7 5 Ox1E 29 Minimum RAS to CAS Delay tRCD ns 15 0x3C 30 Minimum Active to Precharge Time tRAS ns 45 0x2D 31 Module Rank Density 1GB 0x01 Document 06833 Revision A 28 Sep 11 Dataram Corporation 2011 Page 9 DTM67220 Vue and Pesfonmasu 1GB 200 Pin 1Rx8 Unbuffered Non ECC DDR2 SO DIMM 32 Address and Command Setup Time Before Clock tIS ns 0 17 0x17 33 Address and Command Hold Time After Clock ns 0 25 0x25 34 Data Input Setup Time Before Strobe tDS ns 0 05 0x05 35 Data Input Hold Time After Strobe tDH ns 0 12 0x12 36 Write Recovery Time tWR ns 15 0x3C 37 Internal write to read command delay tWTR ns 7 5 Ox1E 38 Internal read to precharge command delay tRTP ns 7 5 Ox1E 39 Memory
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