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Intel Core i7-3612QM

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2. Table 8 3 BGA1023 Processor Ball List Table 8 3 BGA1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball 4 Buffer Type Dir SA_BS 1 BF36 DDR3 O SA_DQ 26 AY17 DDR3 Wie SA_BS 2 BA28 DDR3 O SA_DQ 27 AR19 DDR3 o SA_CAS BE39 DDR3 O SA_DQ 28 BA14 DDR3 1 0 SA CKE 0 AY26 DDR3 O SA_DQ 29 AU14 DDR3 o SA CKE 1 BB26 DDR3 O SA_DQ 30 BB14 DDR3 Wie SA_CLK 0 AV36 DDR3 O SA_DQ 31 BB17 DDR3 I O SA_CLK 1 AU40 DDR3 O SA_DQ 32 BA45 DDR3 Wie SA CK 0 AU36 DDR3 O SA_DQ 33 AR43 DDR3 1 0 SA_CK 1 AT40 DDR3 O SA_DQ 34 AW48 DDR3 1 0 SA_CS 0 BB40 DDR3 O SA_DQ 35 BC48 DDR3 1 0 SA_CS 1 BC41 DDR3 O SA_DQ 36 BC45 DDR3 1 0 SA DQ 0 AG6 DDR3 1 0 SA_DQ 37 AR45 DDR3 Wie SA DQ 1 AJ6 DDR3 1 0 SA_DQ 38 AT48 DDR3 1 0 SA_DO 2 AP11 DDR3 1 0 SA_DQ 39 AY48 DDR3 1 0 SA_DQ 3 AL6 DDR3 1 0 SA_DQ 40 BA49 DDR3 1 0 SA_DQ 4 AJ10 DDR3 o SA DQ 41 AVa9 DDR3 Wie SA DQ 5 AJ8 DDR3 1 0 SA_DQ 42 BB51 DDR3 1 0 SA DQ 6 AL8 DDR3 1 0 SA_DQ 43 AY53 DDR3 o SA_DO 7 AL7 DDR3 1 0 SA_DQ 44 BB49 DDR3 1 0 SA_DQ 8 AR11 DDR3 o SA DQ 45 AU49 DDR3 I O SA_DQ 9 AP6 DDR3 1 0 SA DQ 46 BA53 DDR3 1 0 SA_DQ 10 AU6 DDR3 1 0 SA_DQ 47 BB55 DDR3 o SA_DQ 11 AV9 DDR3 1 0 SA_DQ 48 BA55 DDR3 1 0 SA_DQ 12 AR6 DDR3 o SA DQ 4
3. Table 8 3 BGA1023 Processor Ball List Table 8 3 BGA1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball 4 Buffer Type Dir SB_DQ 25 BE17 DDR3 1 0 SB_DQ 62 AF61 DDR3 Wie SB_DQ 26 BE18 DDR3 1 0 SB_DQ 63 AH60 DDR3 I O SB_DQ 27 BE21 DDR3 1 0 SB_DQS 0 AL3 DDR3 1 0 SB_DQ 28 BE14 DDR3 o SB_DQS 1 AV3 DDR3 1 0 SB_DQ 29 BG14 DDR3 Wie SB_DQS 2 BG11 DDR3 1 0 SB_DQ 30 BG18 DDR3 o SB_DQS 3 BD17 DDR3 I O SB_DQ 31 BF19 DDR3 1 0 SB_DQS 4 BG51 DDR3 Wie SB_DQ 32 BD50 DDR3 1 0 SB_DQS 5 BA59 DDR3 o SB DQ 33 BF48 DDR3 1 0 SB_DQS 6 AT60 DDR3 1 0 SB_DQ 34 BD53 DDR3 1 0 SB_DQS 7 AK59 DDR3 1 0 SB_DQ 35 BF52 DDR3 1 0 SB_DOS 0 AM2 DDR3 1 0 SB_DQ 36 BD49 DDR3 1 0 SB_DQS 1 AV1 DDR3 1 0 SB_DQ 37 BE49 DDR3 1 0 SB_DQS 2 BE11 DDR3 1 0 SB_DQ 38 BD54 DDR3 1 0 SB_DQS 3 BD18 DDR3 1 0 SB_DQ 39 BE53 DDR3 1 0 SB_DQS 4 BE51 DDR3 1 0 SB_DQ 40 BF56 DDR3 I O SB_DQS 5 BA61 DDR3 1 0 SB DQ 41 BE57 DDR3 1 0 SB_DQS 6 AR59 DDR3 1 0 SB_DQ 42 BC59 DDR3 1 0 SB_DQS 7 AK61 DDR3 1 0 SB_DQ 43 AY60 DDR3 1 0 SB MA 0 BF32 DDR3 O SB_DQ 44 BE54 DDR3 o SB_MA 1 BE33 DDR3 O SB_DQ 45 BG54 DDR3 1 0 SB_MA 2 BD33 DDR3 O SB_DQ 46 BA58 DDR3 1 0 SB_MA 3 AU30 DDR3 O SB_DQ 47 AW59 DDR3 1 0 SB_MA 4 BD30 DDR3 O SB_DQ 48 AW58 DDR3 o SB_MA 5 AV30
4. Pin Name Pin 4 Buffer Type Dir Pin Name Pin 4 Buffer Type Dir VAXG AH23 PWR VAXG AT21 PWR VAXG AH24 PWR VAXG AT23 PWR VAXG AJ17 PWR VAXG AT24 PWR VAXG AJ18 PWR VAXG_SENSE AK35 Analog O VAXG AJ20 PWR VAXG_VAL_SENSE AJ31 Analog O VAXG AJ21 PWR VCC AA26 PWR VAXG AJ23 PWR VCC AA27 PWR VAXG AJ24 PWR VCC AA28 PWR VAXG AK17 PWR VCC AA29 PWR VAXG AK18 PWR VCC AA30 PWR VAXG AK20 PWR VCC AA31 PWR VAXG AK21 PWR VCC AA32 PWR VAXG AK23 PWR VCC AA33 PWR VAXG AK24 PWR VCC AA34 PWR VAXG AL17 PWR VCC AA35 PWR VAXG AL18 PWR VCC AC26 PWR VAXG AL20 PWR VCC AC27 PWR VAXG AL21 PWR VCC AC28 PWR VAXG AL23 PWR VCC AC29 PWR VAXG AL24 PWR VCC AC30 PWR VAXG AM17 PWR VCC AC31 PWR VAXG AM18 PWR VCC AC32 PWR VAXG AM20 PWR VCC AC33 PWR VAXG AM21 PWR VCC AC34 PWR VAXG AM23 PWR VCC AC35 PWR VAXG AM24 PWR VCC AD26 PWR VAXG AN17 PWR VCC AD27 PWR VAXG AN18 PWR VCC AD28 PWR VAXG AN20 PWR VCC AD29 PWR VAXG AN21 PWR VCC AD30 PWR VAXG AN23 PWR VCC AD31 PWR VAXG AN24 PWR VCC AD32 PWR VAXG AP17 PWR VCC AD33 PWR VAXG AP18 PWR VCC AD34 PWR VAXG AP20 PWR vcc AD35 PWR VAXG AP21 PWR VCC AF26 PWR VAXG AP23 PWR VCC AF27 PWR VAXG AP24 PWR VCC AF28 PWR VAXG AR17 PWR VCC AF29 PWR VAXG AR18 PWR VCC AF30 PWR VAXG AR20 PWR VCC AF31 PWR VAXG AR21 PWR VCC AF32 PWR VAXG AR23 PWR VCC AF33 PWR VAXG AR24 PWR VCC AF34 PWR VAXG AT17 PWR VC
5. Datasheet Volume 1 Ball Name Ball 4 Buffer Type Dir Ball Name Ball 4 Buffer Type Dir VSS C30 GND VSSAXG SENSE E50 Analog O VSS C20 GND VSSAXG VAL SENSE A48 Analog O VSS C16 GND VSS SENSE VCCIO AU10 Analog O VSS C12 GND VSS C8 GND VSS B39 GND VSS B33 GND VSS B27 GND VSS A56 GND VSS A52 GND VSS A42 GND VSS A36 GND VSS A30 GND VSS A24 GND VSS A20 GND VSS A16 GND VSS A12 GND VSS A8 GND VSS NCTF BJ60 VSS NCTF BJ6 VSS NCTF BH61 VSS NCTF BH5 VSS NCTF BE64 VSS NCTF BE2 VSS NCTF BD65 VSS NCTF BD1 VSS_NCTF F65 VSS_NCTF Fi VSS_NCTF E64 VSS_NCTF E2 VSS_NCTF B61 VSS NCTF B5 VSS NCTF A60 VSS NCTF A6 VSS SENSE A46 Analog VSS SENSE VDDQ AW20 Analog VSS VAL SENSE C48 Analog 139 m n tel Processor Pin Signal and Package Information Figure 8 4 BGA1023 Ballmap left side 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 AR PMUOUOMNOTCArSZVAACKS lt PFSE PERE PS SSL 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 140 Datasheet Volume 1 Processor Pin Signal and Package Information i n tel Figure 8 5 BGA1023 Ballmap right side 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 Uoommorcarzzvz4c z 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 Datasheet Volume 1 141 m
6. Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VSS L50 GND VSS G46 GND VSS L46 GND VSS G42 GND VSS L42 GND VSS G36 GND VSS L36 GND VSS G30 GND VSS L30 GND VSS G24 GND VSS L24 GND VSS G20 GND VSS L20 GND VSS G16 GND VSS L16 GND VSS G12 GND VSS L12 GND VSS G8 GND VSS L8 GND VSS F39 GND VSS K39 GND VSS F33 GND VSS K33 GND VSS F27 GND VSS K27 GND VSS E60 GND VSS K1 GND VSS E56 GND VSS J64 GND VSS E52 GND VSS J60 GND VSS E48 GND VSS J56 GND vss E46 GND VSS J52 GND VSS E42 GND VSS J48 GND VSS E36 GND VSS J46 GND VSS E30 GND VSS J42 GND VSS E24 GND VSS J36 GND VSS E22 GND VSS J30 GND VSS E18 GND VSS J24 GND VSS E14 GND VSS J22 GND VSS E10 GND VSS J18 GND VSS E6 GND VSS J14 GND VSS E4 GND VSS J10 GND VSS D63 GND VSS J6 GND VSS D39 GND VSS H39 GND VSS D33 GND VSS H33 GND VSS D27 GND VSS H27 GND VSS C58 GND VSS H3 GND VSS C54 GND VSS G62 GND VSS C50 GND VSS G58 GND VSS C46 GND VSS G54 GND VSS C42 GND VSS G50 GND VSS C36 GND 138 Datasheet Volume 1 Processor Pin Signal and Package Information Table 8 2 BGA1224 Processor Ball List by Ball Name Continued intel Table 8 2 BGA1224 Processor Ball List by Ball Name Continued
7. Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir RSVD BA48 RSVD G52 RSVD BA16 RSVD G48 RSVD AY45 RSVD G4 RSVD AY41 RSVD F5 RSVD AY17 RSVD D49 RSVD AY15 RSVD D25 RSVD AY13 RSVD D3 RSVD AW50 RSVD C52 RSVD AW46 RSVD C24 RSVD AW42 RSVD CA RSVD AW14 RSVD B53 RSVD AJ10 RSVD B25 RSVD AJ6 SA BS 0 BA36 DDR3 O RSVD AH5 SA_BS 1 BC38 DDR3 O RSVD AD5 SA_BS 2 BB19 DDR3 O RSVD AC6 SA_CAS BE44 DDR3 O RSVD AC4 SA_CKE 0 BC18 DDR3 O RSVD AA4 SA_CKE 1 BD17 DDR3 O RSVD P7 SA_CLK 0 BA32 DDR3 O RSVD N6 SA_CLK 1 AY33 DDR3 O RSVD M9 SA_CK 0 BB31 DDR3 O RSVD M5 SA_CK 1 AW34 DDR3 O RSVD L10 SA_CS 0 BD41 DDR3 O RSVD L6 SA_CS 1 BD45 DDR3 O RSVD L4 SA DQ 0 AL6 DDR3 1 0 RSVD L2 SA DQ 1 AL8 DDR3 1 0 RSVD K49 SA_DQ 2 AP7 DDR3 1 0 RSVD K47 SA_DQ 3 AM5 DDR3 1 0 RSVD K9 SA DQ 4 AK7 DDR3 1 0 RSVD K7 SA DQ 5 AL10 DDR3 1 0 RSVD K5 SA_DQ 6 AN10 DDR3 1 0 RSVD 350 SA_DQ 7 AM9 DDR3 1 0 RSVD J4 SA_DQ 8 AR10 DDR3 1 0 RSVD J2 SA_DQ 9 AR8 DDR3 1 0 RSVD H49 SA_DQ 10 AV7 DDR3 1 0 RSVD H47 SA_DQ 11 AY5 DDR3 1 0 RSVD H5 SA_DQ 12 AT5 DDR3 1 0 126 Datasheet Volume 1 Processor Pin Signal and Package Information intel
8. Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir SA DQ 13 AR6 DDR3 1 0 SA_DQ 50 BA60 DDR3 1 0 SA_DQ 14 AW6 DDR3 1 0 SA_DQ 51 BB61 DDR3 1 0 SA_DQ 15 AT9 DDR3 1 0 SA_DQ 52 BE60 DDR3 1 0 SA_DQ 16 BA6 DDR3 1 0 SA_DQ 53 BD63 DDR3 1 0 SA_DQ 17 BAS DDR3 1 0 SA_DQ 54 BB59 DDR3 1 0 SA_DQ 18 BG6 DDR3 1 0 SA_DQ 55 BC58 DDR3 1 0 SA_DQ 19 AY9 DDR3 1 0 SA_DQ 56 AW58 DDR3 1 0 SA_DQ 20 AW8 DDR3 1 0 SA_DQ 57 AY59 DDR3 1 0 SA DQ 21 BB7 DDR3 1 0 SA_DQ 58 AL60 DDR3 1 0 SA_DQ 22 BC8 DDR3 1 0 SA_DQ 59 AP61 DDR3 1 0 SA_DQ 23 BE4 DDR3 1 0 SA_DQ 60 AW60 DDR3 1 0 SA_DQ 24 AW12 DDR3 1 0 SA_DQ 61 AY57 DDR3 1 0 SA_DQ 25 AV11 DDR3 1 0 SA_DQ 62 AN60 DDR3 1 0 SA_DQ 26 BB11 DDR3 1 0 SA_DQ 63 AR60 DDR3 1 0 SA_DQ 27 BA12 DDR3 1 0 SA_DQS 0 AN8 DDR3 1 0 SA_DQ 28 BE8 DDR3 1 0 SA_DQS 1 AU6 DDR3 1 0 SA_DQ 29 BA10 DDR3 1 0 SA_DQS 2 BC6 DDR3 1 0 SA_DQ 30 BD11 DDR3 1 0 SA_DQS 3 BD9 DDR3 1 0 SA_DQ 31 BE12 DDR3 1 0 SA_DQS 4 BC50 DDR3 1 0 SA_DQ 32 BB49 DDR3 1 0 SA_DQS 5 BB55 DDR3 1 0 SA_DQ 33 AY49 DDR3 1 0 SA_DQS 6 BD59 DDR3 1 0 SA_DQ 34 BE52 DDR3 1 0 SA_DQS 7 AU60 DDR3 1 0 SA_DQ 35 BD51 DDR3 1 0 SA_DQS 0 AN6 DDR3 1 0 SA_DQ 36 BD49 DDR3 1 0 SA_DQS 1 AU8 DDR3 1 0 SA_DQ 37 BE48 DDR3 1 0 SA_DQS 2 BD5 DDR3 1 0 SA_DQ 38 BA52 DDR3 1 0 SA_DQS 3 BC10 DDR3 1 0 SA_DQ 39 AY51 DD
9. 156 Datasheet Volume 1 Processor Pin Signal and Package Information intel Figure 8 7 Processor rPGA988B 2C GT1 G24406 Mechanical Package Sheet 2 of 2 F Es wer 2 Lj ES TTOM t Eu DETAIL Datasheet Volume 1 157 Processor Pin Signal and Package Information intel DEIER EU i8 ms sane dae 135440 Ol a Su313AL TIIW 1NA 1108 LAA Processor rPGA988B 2C GT2 G23867 Mechanical Package Sheet 1 of 2 er JON 310 LI MAAARI 3 LLU UL Figure 8 8 Datasheet Volume 1 158 intel Processor Pin Signal and Package Informati
10. Multi Format Decode Encode Full MPEG2 VC1 AVC Decode Fixed Function Post Processing Full AVC Encode Partial MPEG2 VC1 Encode 2 4 1 3D and Video Engines for Graphics Processing The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive All the cores are fully programmable increasing the versatility of the 3D Engine The Gen 7 0 3D engine provides the following performance and power management enhancements e Up to 16 Execution units EUs e Hierarchal Z e Video quality enhancements 2 4 1 1 3D Engine Execution Units e Supports up to 16 EUs The EUs perform 128 bit wide execution per clock e Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel processing Datasheet Volume 1 33 intel Interfaces 2 4 1 2 2 4 1 2 1 2 4 1 2 2 2 4 1 2 3 2 4 1 2 4 2 4 1 2 5 2 4 1 2 6 2 4 1 3 34 3D Pipeline Vertex Fetch VF Stage The VF stage executes 3DPRIMITIVE commands Some enhancements have been included to better support legacy D3D APIs as well as SGI OpenGL Vertex Shader VS Stage The VS stage performs shading of vertices output by the VF function The VS unit produces an output vertex reference for every input vertex reference received from the VF unit in the order received Geometry Shader GS Stage The GS stage receives inputs from the VS stage
11. 159 8 10 Processor rPGA988B 4C GT2 E95127 Mechanical Package Sheet 1 of 2 160 8 11 Processor rPGA988B 4C GT2 E95127 Mechanical Package Sheet 2 of 2 161 8 12 Processor BGA1023 2C GT1 G24405 Mechanical Package seen 162 8 13 Processor BGA1023 2C GT2 G23866 Mechanical Package sese 163 8 14 Processor BGA1224 4C GT2 G26204 Mechanical Package sess 164 Tables 1 Mobile 3rd Generation Intel Core Processor Family SkUs 18 1 2 cenminol0gy eneu Ee DD GG cU I A Ee 20 1 3 Related DOCUMENTS iie been teen xke cta un ne si FR OR RF ARR FN des acne A nd a FEE ST E MEAE 22 2 1 Processor Mobile DIMM Support Summary by Product occccccncncnnnnnnnnnonannnnnnnnnncnnnanannnnnns 23 2 2 Supported DDR3 DDR3L DDR3L RS SO DIMM Module Configurations 24 2 3 Supported Maximum Memory Size Per DIMM ssssssssseee emen nene eene 24 2 4 DDR3 DDR3L DDR3L RS 1 5 V System Memory Timing Support seeseseeeese 25 2 5 DDR3L DDR3L RS System Memory Timing Support 25 2 6 Reference Clock eese epe e ANT Ri A GR bnn oia 38 47 System States diu Da ei tn a a Rd Cd Odd E O Ln topo ddan 48 4 2 Processor Core Package State Support 48 4 3 Integrated Memory Controller States LL LA YEAR AL nennen eee nnns 48 4 4 PET EXpress link EEN 49 425 DMI States i nin 49 4 6 Processor Graphics Controller Gtates eect eee eee ee eee ee ee eee nemen een
12. Electrical Sub block Electrical Sub block RX TX RX TX Datasheet Volume 1 Interfaces Figure 2 3 2 2 1 1 2 2 1 2 2 2 1 3 intel PCI Express uses packets to communicate information between components Packets are formed in the Transaction and Data Link Layers to carry the information from the transmitting component to the receiving component As the transmitted packets flow through the other layers they are extended with additional information necessary to handle packets at those layers At the receiving side the reverse process occurs and packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally for Transaction Layer Packets to the form that can be processed by the Transaction Layer of the receiving device Packet Flow Through the Layers a2 T l HA EE D I l Framing sequence Header Data ECRC LCRC Framing Number L d A t A Transaction Layer M Data Link Layer Physical Layer Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer The Transaction Layer s primary responsibility is the assembly and disassembly of Transaction Layer Packets TLPs TLPs are used to communicate transactions such as read and write as well as certain types of events The Transaction Layer also manages flow control of TLPs Data Link Layer
13. em E 10 Datasheet Volume 1 Introduction Note Note Note Note Note intel Introduction The Mobile 3rd Generation Intel Core processor family is the next generation of 64 bit multi core mobile processors built on 22 nanometer process technology The processor is designed for a two chip platform The two chip platform consists of a processor and a Platform Controller Hub PCH and enables higher performance lower cost easier validation and improved x y footprint The processor includes Integrated Display Engine Processor Graphics and an Integrated Memory Controller The processor is designed for mobile platforms The Mobile 3rd Generation Intel Core processor family offers either 6 or 16 graphic execution units EUs The number of EU engines supported may vary between processor SKUs The processor is offered in a rPGA988B BGA1224 or BGA1023 package The Datasheet provides DC specifications pinout and signal definitions interface functional descriptions thermal specifications and additional feature information pertinent to the implementation and operation of the processor on its respective platform Throughout this document the Mobile 3rd Generation Intel Core processor family may be referred to simply as processor Throughout this document the Mobile 3rd Generation Intel Core processor family refers to the Intel Core processors listed in Table 1 1 Throughout th
14. n tel Processor Pin Signal and Package Information Table 8 3 BGA1023 Processor Ball List Table 8 3 BGA1023 Processor Ball List by Ball Name by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir BCLK 33 Diff Clk I DC_TEST_BD61 BD61 N A BCLK H2 Diff Clk I DC_TEST_BE1 BE1 N A BCLK_ITP N59 Diff Clk I DC_TEST_BE3 BE3 N A BCLK_ITP N58 Diff Clk I DC_TEST_BE59 BE59 N A BPM 0 G58 Asynch CMOS 1 0 DC_TEST_BE61 BE61 N A BPM 1 E55 Asynch CMOS 1 0 DC_TEST_BG1 BG1 N A BPM 2 E59 Asynch CMOS 1 0 DC_TEST_BG3 BG3 N A BPM 3 G55 Asynch CMOS 1 0 DC_TEST_BG4 BG4 N A BPM 4 G59 Asynch CMOS 1 0 DC_TEST_BG58 BG58 N A BPM 5 H60 Asynch CMOS 1 0 DC_TEST_BG59 BG59 N A BPM 6 J59 Asynch CMOS 1 0 DC_TEST_BG61 BG61 N A BPM 7 J61 Asynch CMOS 1 0 DC_TEST_C4 C4 N A CATERR C49 Asynch CMOS O DC_TEST_C59 C59 N A CFG 0 B50 CMOS I DC_TEST_C61 C61 N A CFG 1 C51 CMOS I DC TEST D1 D1 N A CFG 2 B54 CMOS I DC_TEST_D3 D3 N A CFG 3 D53 CMOS I DC TEST D61 D61 N A CFG 4 A51 CMOS I DMI_RX 0 M2 DMI I CFG 5 C53 CMOS I DMI_RX 1 P6 DMI I CFG 6 C55 CMOS I DMI_RX 2 P1 DMI I CFG 7 H49 CMOS I DMI_RX 3 P10 DMI I CFG 8 A55 CMOS I DMI RX 0 N3 DMI I CFG 9 H51 CMOS I pMLRXi P7 DM I CFG 10 K49 CMOS I DMI RX 2 P3 DMI I CFG 11 K53 CMOS I DMI RX 3 P11 DMI I CFG 12 F53 CMOS I DMI_TX 0 K1 DMI O CFG 13 G53 CMOS
15. The middle layer in the PCI Express stack the Data Link Layer serves as an intermediate stage between the Transaction Layer and the Physical Layer Responsibilities of Data Link Layer include link management error detection and error correction The transmission side of the Data Link Layer accepts TLPs assembled by the Transaction Layer calculates and applies data protection code and TLP sequence number and submits them to Physical Layer for transmission across the Link The receiving Data Link Layer is responsible for checking the integrity of received TLPs and for submitting them to the Transaction Layer for further processing On detection of TLP error s this layer is responsible for requesting retransmission of TLPs until information is correctly received or the Link is determined to have failed The Data Link Layer also generates and consumes packets which are used for Link management functions Physical Layer The Physical Layer includes all circuitry for interface operation including driver and input buffers parallel to serial and serial to parallel conversion PLL s clock recovery circuits and impedance matching circuitry It also includes logical functions related to interface initialization and maintenance The Physical Layer exchanges data with the Data Link Layer in an implementation specific format and is responsible for converting this to an appropriate serialized format and transmitting it across the PCI Express Link at
16. DQ28 SB DQ 31 M1 BF19 BG18 DQ29 SB DQ 32 AM5 BD50 BH49 DQ35 SB DQ 33 AM6 BF48 BF47 DQ32 SB DQ 34 AR3 BD53 BH53 DQ37 SB DQ 35 AP3 BF52 BG50 DQ36 SB DQ 36 AN3 BD49 BF49 DQ33 SB DQ 37 AN2 BE49 BH47 DQ34 Datasheet Volume 1 Table 9 2 DDR Data Swizzling Table for Package Channel B Pin Name TM ibus Mesue pee rPGA BGA1023 BGA1224 SB DQ 38 AN1 BD54 BF53 DQ38 SB DQ 39 AP2 BE53 BJ50 DQ39 SB DQ 40 AP5 BF56 BF55 DQ43 SB DQ 41 AN9 BE57 BH55 DQ44 SB DQ 42 AT5 BC59 BJ58 DQ41 SB DQ 43 AT6 AY60 BH59 DQ40 SB DQ 44 AP6 BE54 BJ54 DQ47 SB DQ 45 AN8 BG54 BG54 DQ45 SB DQ 46 AR6 BA58 BG58 DO42 SB DQ 47 AR5 AW59 BF59 DQ46 SB DQ 48 AR9 AW58 BA64 DQ52 SB DQ 49 AJ11 AU58 BC62 DO54 SB DQ 50 AT8 AN61 AU62 DO51 SB DQ 51 AT9 AN59 AW64 DO55 SB DQ 52 AH11 AU59 BA62 DQ50 SB DQ 53 AR8 AU61 BC64 DQ53 SB DQ 54 AJ12 AN58 AU64 DQ49 SB DQ 55 AH12 AR58 AW62 DQ48 SB DQ 56 AT11 AK58 AR64 DQ63 SB DQ 57 AN14 AL58 AT65 DQ61 SB DQ 58 AR14 AG58 AL64 DQ58 SB DQ 59 AT14 AG59 AM65 DO56 SB DQ 60 AT12 AM60 AR62 DQ62 SB DQ 61 AN15 AL59 AT63 DO60 SB DQ 62 AR15 AF61 AL62 DQ57 SB DQ 63 AT15 AH60 AM63 DO59 88 167 DDR Data Swizzling 168 Datasheet Volume 1
17. 0 1 Output Low Voltage ES Vppo 2 Ron tRon Rrerm i Output High m Vppo Vppo 2 Vou Voltage Ron Ron ren v K DDR3 Data Buffer RON_UP DO pull up Resistance 20 28 6 40 i 5 DDR3 Data Buffer RON_DN DQ pull down 20 28 6 40 Q 5 Resistance DDR3 On die termination RopT DQ equivalent 40 50 60 Q resistance for data signals DDR3 On die termination DC Vopr Dc working point 0 4 Vppo 0 5 Vppo 0 6 Vppo V driver set to receive mode DDR3 Clock Buffer RON_UP CK pull up Resistance 20 26 40 i 5 12 DDR3 Clock Buffer Ron_DN CK pull down 20 26 40 o 5 12 Resistance DDR3 Command Ron_up cmp Buffer pull up 15 20 25 Q 5 12 Resistance DDR3 Command Ron_pnccmp Buffer pull down 15 20 25 Q 5 12 Resistance DDR3 Control RoN UP CTL Buffer pull up 15 20 25 o 5 12 Resistance DDR3 Control Ron_on cri Buffer pull down 15 20 25 Q 5 12 Resistance Datasheet Volume 1 103 intel Electrical Specifications Table 7 11 DDR3 DDR3L DDR3L RS Signal Group DC Specifications Sheet 2 of 2 Symbol Parameter Min Typ Max Units Notes Input Leakage Current DQ CK i ov t 0 75 ink LI 0 2 VDDQ 0 55 0 8 VDDQ 0 9 VDDQ 1 4 Input Leakage Current CMD CTL i ov 0 85 A u 0 2 Vppq 0 65 m 0 8 Vppq 1 10 VppQ 1 65 Command COMP Data COMP SM_RCOMP1 Resistance 25 245 25 5 25 755 Q 8 ODT COM
18. 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 2 3 4 5 6 VID VID VID VID VID VID VID VID 7 Datasheet Volume 1 94 Electrical Specifications m L 7 4 Note Note Table 7 2 7 5 System Agent SA Vcc VID The Vccsa is configured by the processor output pins VCCSA VID 1 0 VCCSA_VID O output default logic state is low for 2nd Generation Intel Core family mobile processors During boot the processor Vccsa voltage is 0 9 V The VccsA may change only once during the reset sequence For Ultra products for power optimization purposes the VCCSA VID may change dynamically during the processor s operation Table 7 2 specifies the different VCCSA VID configurations VCCSA VID Configuration Selected VccsA VCCSA VID 0 VCCSA VID 1 XE amp SV regen a segments 9 0 0 0 9 V 0 9 V 0 1 0 8 V 0 85 V 1 0 0 725 V 0 775 V 1 1 0 675 V 0 75 V Reserved or Unused Signals The following are the general types of reserved RSVD signals and connection guidelines e RSVD these signals should not be connected e RSVD TP these signals should be routed to a test point e RSVD NCTF these signals are non critical to function a
19. Average Current for Vppg Rail IccavG vbDQ Standby during Standby 66 133 mA Note 1 The current supplied to the SO DIMM modules is not included in this specification Table 7 8 System Agent Vccsa Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note Voltage for the System Agent and V 0 675 0 90 V GESA VCCSA_SENSE TOLccsA VccsA Tolerance AC DC 5 Max Current for Vccs Rail XE and SV 6 A IccMAx vCCSA n Max Current for Vccs Rail Ultra 4 A Thermal Design Current TDC for VccsA _ 6 A Rail XE and SV Icctpc_vccsa T Thermal Design Current TDC for Vecsa m _ 3 A Rail Ultra Slew Rate Voltage Ramp rate dV dT 0 5 10 mV us Note 1 Long term reliability cannot be assured in conditions above or below Max Min functional limits Datasheet Volume 1 101 intel Electrical Specifications Table 7 9 Processor PLL Vccp Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note PLL supply voltage DC AC u _ Vecrun specification DR S TOLccpLL VccPLL Tolerance AC DC 5 Iccmax_veceiL Max Current for Vccpi Rail 1 2 A I Thermal Design Current TDC for _ T 1 2 A CCTDC_VCCPLL Vecp Rail Note 1 Long term reliability cannot be assured in conditions above or below Max Min functional limits Table 7 1
20. Memory Thermal Throttling e External Thermal Sensor TS on DIMM and TS on Board e Render Thermal Throttling e Fan speed control with DTS 1 4 Mobile 3rd Generation Intel Core Processor Family SKU Definition Table 1 1 Mobile 3rd Generation Intel Core Processor Family SKUs Processor TDP EE Tjmax LFM LPM IA Frequency Range GT Frequency Range Number W Mr doe ec 55 1900 MHz i7 3920XM Down 45 Up 65 LPM 2 9 GHz up to 3 8 GHz 650 MHz up to 1300 MHz 105 enabled i7 3820QM 45 1200 MHz 2 7 GHz up to 3 7 GHz 650 MHz up to 1250 MHz 105 i7 3720QM 45 1200 MHz 2 6 GHz up to 3 6 GHz 650 MHz up to 1250 MHz 105 i7 3520M 35 1200 MHz 2 9 GHz up to 3 6 GHz 650 MHz up to 1250 MHz 105 i5 3360M 35 1200 MHz 2 8 GHz up to 3 5 GHz 650 MHz up to 1200 MHz 105 i5 3320M 35 1200 MHz 2 6 GHz up to 3 3 GHz 650 MHz up to 1200 MHz 105 17 800 MHz i7 3667U Down 14 Up 25 LPM 2 GHz up to 3 2 GHz 350 MHz up to 1150 MHz 105 enabled 17 800 MHz i5 3427U Down 14 Up 25 LPM 1 8 GHz up to 2 8 GHz 350 MHz up to 1150 MHz 105 enabled 1 5 Package The processor is available on two packages e A 37 5 x 37 5 mm rPGA package rPGA988B e A 31 x 24 mm BGA package BGA1023 for dual core processors or BGA1224 for quad core processors 18 Datasheet Volume 1 Introduction intel 1 6 Processor Compatibility The Mobile 3rd Generation Intel Core processor family has specific platform requirements tha
21. PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Notes Rup Output resistance 15 45 Q 3 Vin Input Voltage Range 0 15 Vccio Vhysteresis Hysteresis 0 1 Vccio N A V Vn Negative Edge Threshold Voltage 0 275 Vecio 0 500 Vccro V Vp Positive Edge Threshold Voltage 0 550 Vecio 0 725 Vecio V Cbus Bus Capacitance per Node N A 10 pF Cpad Pad Capacitance 0 7 1 8 pF Ileak000 leakage current OV d 0 6 mA Ileak025 leakage current O 0 25 Vccro 0 4 mA Ileak050 leakage current 0 50 Vccro 0 2 mA Ileak075 leakage current O 0 75 Vccro 0 13 mA Ileak100 leakage current O Ve cjo 0 10 mA Notes 1 Vccro supplies the PECI interface PECI behavior does not affect Vccjo min max specifications 2 The leakage specification applies to powered devices on the PECI bus 3 The PECI buffer internal pull up resistance measured at 0 75 Vccro Input Device Hysteresis The input buffers in both client and host models must use a Schmitt triggered input design for improved noise immunity Use Figure 7 2 as a guide for input buffer design Input Device Hysteresis Vy TD PECI High Range Yj Maximum Vp J Minimum Vp Minimum gt Valid Input Hysteresis Signal Range Maximum Vu 4 Minimum Vy PECI Low Range SS PECI Ground a 107 Electrical Specifications
22. VCCIO AM16 PWR VCCIO AB17 PWR VCCIO AL48 PWR VCCIO AA15 PWR VCCIO AL45 PWR VCCIO AA14 PWR VCCIO AL26 PWR VCCIO W17 PWR VCCIO AL22 PWR VCCIO W16 PWR VCCIO AL20 PWR VCCIO SEL BC22 N A VCCIO AL16 PWR VCCIO SENSE AN16 Analog VCCIO AL15 PWR VCCPLL BC4 PWR VCCIO AL14 PWR VCCPLL BC1 PWR VCCIO AK51 PWR VCCPLL BB3 PWR VCCIO AK50 PWR VCCPQE AN22 PWR VCCIO AJ47 PWR VCCPOE AM25 PWR VCCIO AJ43 PWR VCCSA W20 PWR VCCIO AJ25 PWR VCCSA V21 PWR VCCIO AJ21 PWR VCCSA V18 PWR VCCIO AJ17 PWR VCCSA V17 PWR VCCIO AJ15 PWR VCCSA V16 PWR VCCIO AJ14 PWR VCCSA U15 PWR VCCIO AG51 PWR VCCSA R21 PWR VCCIO AG50 PWR VCCSA R18 PWR VCCIO AG48 PWR VCCSA R16 PWR VCCIO AG21 PWR VCCSA P20 PWR VCCIO AG20 PWR VCCSA P17 PWR VCCIO AG17 PWR VCCSA N22 PWR VCCIO AG16 PWR VCCSA N20 PWR 150 Datasheet Volume 1 Processor Pin Signal and Package Information intel Table 8 3 BGA1023 Processor Ball List Table 8 3 BGA1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VCCSA N16 PWR vss BG49 GND VCCSA L21 PWR vss BG45 GND VCCSA L17 PWR vss BG41 GND VCCSA_SENSE U10 Analog vss BG37 GND VCCSA_VID 0 D48 CMOS vss BG28 GND VCCSA_VID 1 D49
23. 1 0 SB Ck 1 BA36 DDR3 O SA_DQS 1 AR10 DDR3 1 0 SB_CS 0 BE41 DDR3 O SA_DQS 2 AY11 DDR3 1 0 SB_CS 1 BE47 DDR3 O SA_DQS 3 AU17 DDR3 1 0 SB_DQ O AL4 DDR3 1 0 SA_DQS 4 AW45 DDR3 1 0 SB_DQ 1 AL1 DDR3 1 0 SA_DQS 5 AV51 DDR3 1 0 SB_DQ 2 AN3 DDR3 1 0 SA_DQS 6 AT56 DDR3 1 0 SB_DQ 3 AR4 DDR3 1 0 SA_DQS 7 AK54 DDR3 1 0 SB_DQ 4 AK4 DDR3 1 0 SA MA 0 BG35 DDR3 o SB_DO 5 AK3 DDR3 1 0 SA_MA 1 BB34 DDR3 O SB DQ 6 ANA DDR3 1 0 SA_MA 2 BE35 DDR3 O SB_DQ 7 AR1 DDR3 1 0 SA_MA 3 BD35 DDR3 O SB_DQ 8 AU4 DDR3 1 0 SA_MA 4 AT34 DDR3 O SB_DQ 9 AT2 DDR3 1 0 SA_MA 5 AU34 DDR3 O SB_DQ 10 AV4 DDR3 1 0 SA_MA 6 BB32 DDR3 O SB_DQ 11 BA4 DDR3 1 0 SA_MA 7 AT32 DDR3 O SB_DQ 12 AU3 DDR3 1 0 SA_MA 8 AY32 DDR3 O SB_DQ 13 AR3 DDR3 1 0 SA_MA 9 AV32 DDR3 O SB_DQ 14 AY2 DDR3 1 0 SA_MA 10 BE37 DDR3 O SB_DQ 15 BA3 DDR3 1 0 SA_MA 11 BA30 DDR3 O SB_DQ 16 BES DDR3 1 0 SA_MA 12 BC30 DDR3 O SB_DQ 17 BD9 DDR3 1 0 SA_MA 13 AW41 DDR3 O SB_DQ 18 BD13 DDR3 1 0 SA_MA 14 AY28 DDR3 O SB_DQ 19 BF12 DDR3 1 0 SA_MA 15 AU26 DDR3 O SB_DQ 20 BF8 DDR3 1 0 SA ODT 0 AY40 DDR3 o SB_DQ 21 BD10 DDR3 1 0 SA_ODT 1 BA41 DDR3 O SB_DQ 22 BD14 DDR3 1 0 SA_RAS BD39 DDR3 O SB_DQ 23 BE13 DDR3 1 0 SA_WE AT41 DDR3 O SB_DQ 24 BF16 DDR3 1 0 146 Datasheet Volume 1 Processor Pin Signal and Package Information intel
24. 1 47000 1 47500 1 48000 1 48500 1 49000 1 49500 1 50000 1 50500 1 51000 1 51500 1 52000 Vcc_Max HEX 1 2 3 A 5 6 7 8 9 B E F 0 1 2 3 4 5 6 7 8 9 B E F 0 1 2 3 4 5 6 7 8 9 B E F D D D D D D D D D D A D D C DD D D E E E E E E E E E E EJA E E C EJD E E F F F F F F F F F F FIA F FIC F D F 0 0 0 0 0 0 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HEX Vcc Max 5 1 0 65000 5 2 0 65500 5 3 0 66000 5 4 0 66500 5 5 0 67000 5 6 0 67500 5 7 0 68000 5 8 0 68500 5 9 0 69000 5 A 0 69500 5 B 0 70000 5 C 0 70500 5 D 0 71000 5 E 0 71500 5 F 0 72000 6 0 0 72500 6 1 0 73000 6 2 0 73500 6 3 0 74000 6 4 0 74500 6 5 0 75000 6 6 0 75500 6 7 0 76000 6 8 0 76500 6 9 0 77000 6 A 0 77500 6 B 0 78000 6 C 0 78500 6 D 0 79000 6 E 0 79500 6 F 0 80000 7 O 0 80500 7 1 0 81000 7 2 0 81500 7 3 0 82000 7 4 0 82500 7 5 0 83000 7 6 0 83500 7 7 0 84000 7 8 0 84500 7 9 0 85000 7 A 0 85500 7 B 0 86000 7 C 0 86500 7 D 0 87000 7 E 0 87500 7 F 0 88000 0 1 0 1 0 1 0 1 0
25. 10 E33 PCIe I RSVD B29 PEG_RX 11 F32 PCIe I RSVD D30 PEG RX 12 D34 PCIe I RSVD B31 PEG RX 13 E31 PCIe I RSVD A30 PEG_RX 14 C33 PCIe I RSVD C29 PEG_RX 15 B32 PCIe I RSVD F25 PEG TX4 0 M29 PCIe O RSVD F24 PEG_TX 1 M32 PCIe O RSVD F23 PEG_TX 2 M31 PCIe O RSVD D24 PEG_TX 3 L32 PCIe 9 RSVD G25 PEG TX4 4 L29 PCIe 9 RSVD G24 PEG TX4 5 K31 PCIe 9 RSVD E23 PEG TX4 6 K28 PCIe 9 RSVD D23 PEG TX4 7 J30 PCIe O RSVD AT26 PEG_TX 8 J28 PCIe O RSVD AG7 PEG_TX 9 H29 PCIe 9 RSVD AE7 PEG_TX 10 G27 PCIe 9 RSVD w8 PEG_TX 11 E29 PCIe O RSVD T8 PEG_TX 12 F27 PCle O RSVD L7 PEG_TX 13 D28 PCIe O RSVD 320 PEG_TX 14 F26 PCIe O RSVD J16 PEG TX 15 E25 PCIe O RSVD AM33 PEG TX 0 M28 PCIe O RSVD J15 PEG TX 1 M33 PCIe O RSVD H16 PEG_TX 2 M30 PCIe O RSVD G16 PEG_TX 3 L31 PCIe O RSVD B18 Datasheet Volume 1 111 m n tel Processor Pin Signal and Package Information Table 8 1 rPGA988B Processor Pin List Table 8 1 rPGA988B Processor Pin List by Pin Name Continued by Pin Name Continued Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir RSVD AK32 SA_CKE 1 vio DDB o RSVD AK2 sAGH0O AK3 DDR3 O RSVD AJ32 SA_CS 1 AL3 DDR3 O RSVD AJ27 SA_DIMM_VREFDQ B4 Analog O RSVD AJ26 SA_DQ O C5 DDR3 1 0 RSVD_NCTF AT34 SA_DO 1 D5 DDR3 1 0 RSVD_NCTF B35 SA_DQ 2 D3 DDR
26. 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 122 Datasheet Volume 1 Processor Pin Signal and Package Information intel Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir BCLK D5 Diff Clk I DC_TEST_B65 B65 N A BCLK C6 Diff Clk I DC_TEST_BF1 BF1 N A BCLK_ITP K63 Diff Clk I DC_TEST_BF65 BF65 N A BCLK_ITP K65 Diff Clk I DC_TEST_BG2 BG2 N A BPM 0 C62 Asynch CMOS I O DC TEST BG64 BG64 N A BPM 1 D61 Asynch CMOS I O DC TEST BH1 BH1 N A BPM 2 E62 Asynch CMOS 1 0 DC_TEST_BH3 BH3 N A BPM 3 F63 Asynch CMOS 1 0 DC_TEST_BH63 BH63 N A BPM 4 D59 Asynch CMOS I O DC TEST BH65 BH65 N A BPM 5 F61 Asynch CMOS I O DC TEST BJ2 BJ2 N A BPM 6 F59 Asynch CMOS 1 0 DC_TEST_BJ4 BJ4 N A BPM 7 G60 Asynch CMOS 1 0 DC_TEST_BJ62 BJ62 N A CATERR H53 Asynch CMOS O DC_TEST_BJ64 BJ64 N A CFG 0 B57 CMOS I DC TEST C2 C2 N A CFG 1 D57 CMOS I DC TEST C64 C64 N A CFG 2 B55 CMOS I DC TEST D1 D1 N A CFG 3 A54 CMOS I DC_TEST_D65 D65 N A CFG 4 A58 CMOS I DMI_RX 0 N10 DMI I CFG 5 D55 CMOS I DMI RX 1 R10 DMI I CFG 6 C56 CMOS I DMI_RX 2 R8 DMI I CFG 7 E54 CMOS I DMI_RX 3 U10 DMI I CFG 8 J54 CMOS I DMI RX 0 N8 DMI I CFG 9 G56 C
27. 5 2 If the power value and or Turbo Time Parameter is changed during runtime it may take a short period of time approximately 3 to 5 times the Turbo Time Parameter for the algorithm to settle at the new control limits 14 This is a hardware default setting and not a behavioral characteristic of the part 15 For controllable Turbo workloads limit may be exceeded for up to 10 ms 16 Refer to Table 5 2 for the definitions of TDP Nominal TDP Up TDP Down 17 LPM power level is an opportunistic power and is not an ensured value as usages and implementations may vary LPM power level assumes 1 core active processor core frequency at MFM Graphics Core running at non Turbo frequency and running an application according to Note 2 18 Power limits may vary depending on if the product supports the TDP up and or TDP down modes Default power limits can be found in the PKG PWR SKU MSR 614h 19 Might be changed based on SKU 20 Unlimited max power limit requires the latest BIOS revision 70 Datasheet Volume 1 Thermal Management Table 5 3 TDP Specifications Processor Segment State oe Core Graphics Core Thermal Units Notes requency frequency Design Power TDP Up 65 A 1 9 GHz TDP Nominal HFM up to 3 8 GHz 55 Extreme Edition XE TDP Down
28. 65 165 Q PREQ Pull Up VCCIO 65 165 Q TCK Pull Down VSS 5 15 kQ TDI Pull Up VCCIO 5 15 kQ TMS Pull Up VCCIO 5 15 kQ TRST Pull Up VCCIO 5 15 kQ CFG 17 0 Pull Up VCCIO 5 15 kQ 90 Datasheet Volume 1 Electrical Specifications m L 7 7 1 7 2 Caution 7 2 1 7 2 2 Electrical Specifications Power and Ground Pins The processor has VCC VCCIO VDDQ VCCPLL VCCSA VAXG and VSS ground inputs for on chip power distribution All power pins must be connected to their respective processor power planes while all VSS pins must be connected to the system ground plane Use of multiple power and ground planes is recommended to reduce I R drop The VCC pins and VAXG pins must be supplied with the voltage determined by the processor Serial Voltage IDentification SVID interface Table 7 4 specifies the voltage level for the various VIDs Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large current swings between low and full power states To keep voltages within specification output decoupling must be properly designed Design the board to ensure that the voltage provided to the processor remains within the specifications listed in Table 7 3 Failure to do so can result in timing violations or reduced lifetime of the processor Voltage Rail Decoupling The voltage regulator solution must e provide sufficient decoupling to compensat
29. 88 108 Datasheet Volume 1 Processor Pin Signal and Package Information m 8 Processor Pin Signal and Package Information 8 1 Processor Pin Assignments Figure 8 1 rPGA988B Socket G2 Pin Map 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 uoommoruzxzrzzvunmAac z Datasheet Volume 1 109 intel Processor Pin Signal and Package Information Table 8 1 rPGA988B Processor Pin List Table 8 1 rPGA988B Processor Pin List by Pin Name by Pin Name Continued Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir BCLK A28 Diff Clk I DMI_TX 3 C21 DMI O BCLK A27 Diff Clk I DPLL_REF_CLK A16 Diff Clk I BCLK ITP AN35 Diff Clk I DPLL REF CLK A15 Diff Clk I BCLK ITP AM35 Diff Clk I eDP_AUX C15 eDP I O BPM 0 AT28 Asynch CMOS I O eDP_AUX D15 eDP I O BPM 1 AR29 Asynch CMOS I O eDP COMPIO A18 Analog I BPM 2 AR30 Asynch CMOS I O eDP HPD B16 Asynch CMOS I BPM 3 AT30 Asynch CMOS I O eDP ICOMPO A17 Analog I BPM 4 AP32 Asynch CMOS 1 0 eDP_TX 0 C18 eDP O BPM 5 AR31 Asynch CMOS 1 0 eDP_TX 1 E16 eDP O BPM 6 AT31 Asynch CMOS 1 0 eDP_TX 2 D16 eDP O BPM 7 AR32 Asynch CMOS 1 0 eDP_TX 3 F15 eDP O CATERR AL33 Asynch CMOS O eDP_TX 0 C17 eDP O CFG 0 AK28 CMOS I eDP TX 1 F16 eDP O CFG 1 AK29 CMOS I eDP
30. CMOS I VAXG V52 PWR VAXG AE46 PWR VAXG V51 PWR VAXG AD59 PWR VAXG V50 PWR VAXG AD58 PWR VAXG V48 PWR VAXG AD56 PWR VAXG V47 PWR VAXG AD55 PWR VAXG U46 PWR VAXG AD53 PWR VAXG T61 PWR VAXG AD52 PWR VAXG T59 PWR VAXG AD51 PWR VAXG T58 PWR VAXG AD50 PWR VAXG T48 PWR VAXG AD48 PWR VAXG P61 PWR VAXG AD47 PWR VAXG P56 PWR VAXG AC61 PWR VAXG P55 PWR VAXG AB59 PWR VAXG P53 PWR VAXG AB58 PWR VAXG P52 PWR VAXG AB56 PWR VAXG P51 PWR VAXG AB55 PWR VAXG P50 PWR VAXG AB53 PWR VAXG P48 PWR VAXG AB52 PWR VAXG P47 PWR VAXG AB51 PWR VAXG N45 PWR VAXG AB50 PWR VAXG_SENSE F45 Analog VAXG AB47 PWR VAXG_VAL_SENSE H45 Analog VAXG AA46 PWR VCC N38 PWR VAXG Y61 PWR VCC N34 PWR 148 Datasheet Volume 1 Processor Pin Signal and Package Information Table 8 3 BGA1023 Processor Ball List by Ball Name Continued intel Table 8 3 BGA1023 Processor Ball List by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball 4 Buffer Type Dir VCC N30 PWR vcc G42 PWR VCC N26 PWR VCC F42 PWR VCC L40 PWR VCC F38 PWR VCC L36 PWR VCC F37 PWR VCC L33 PWR VCC F34 PWR VCC L28 PWR VCC F32 PWR VCC L25 PWR VCC F28 PWR VCC K42 PWR VCC F26 PWR VCC K39 PWR VCC F25 PWR VCC
31. Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball 4 Buffer Type Dir SB_DQ 49 BC62 DDR3 1 0 SB_MA 6 BH27 DDR3 O SB_DQ 50 AU62 DDR3 1 0 SB_MA 7 BG30 DDR3 O SB_DQ 51 AW64 DDR3 1 0 SB_MA 8 BH29 DDR3 O SB_DQ 52 BA62 DDR3 1 0 SB_MA 9 BF29 DDR3 O SB_DQ 53 BC64 DDR3 1 0 SB_MA 10 AY37 DDR3 O SB_DQ 54 AU64 DDR3 1 0 SB_MA 11 BJ30 DDR3 O SB_DQ 55 AW62 DDR3 1 0 SB_MA 12 AW30 DDR3 O SB_DQ 56 AR64 DDR3 1 0 SB_MA 13 BA40 DDR3 O SB_DQ 57 AT65 DDR3 1 0 SB_MA 14 BB29 DDR3 O SB_DQ 58 AL64 DDR3 1 0 SB_MA 15 BE28 DDR3 O SB_DQ 59 AM65 DDR3 1 0 SB_ODT 0 BG42 DDR3 O SB_DQ 60 AR62 DDR3 1 0 SB_ODT 1 BH45 DDR3 O SB_DQ 61 AT63 DDR3 1 0 SB_RAS BG38 DDR3 O SB_DQ 62 AL62 DDR3 1 0 SB_WE BF39 DDR3 O SB_DQ 63 AM63 DDR3 1 0 SM_DRAMPWROK AY25 Asynch CMOS I SB_DQS 0 AN4 DDR3 1 0 SM_DRAMRST BE24 DDR3 O SB_DQS 1 AW2 DDR3 1 0 SM_RCOMP 0 BJ46 Analog 1 0 SB_DQS 2 BH9 DDR3 1 0 SM_RCOMP 1 BG46 Analog 1 0 SB_DQS 3 BF15 DDR3 1 0 SM_RCOMP 2 BF45 Analog 1 0 SB_DQS 4 BF51 DDR3 1 0 SM_VREF BJ44 Analog I SB_DQS 5 BH57 DDR3 1 0 TCK J58 CMOS I SB_DQS 6 AY63 DDR3 1 0 TDI K61 CMOS I SB_DQS 7 AN62 DDR3 1 0 TDO K59 CMOS O SB_DQS 0 AN2 DDR3 1 0 THERMTRIP F51 Asynch CMOS O SB_DQS 1 AW4 DDR3 1 0 TMS H59 CMOS I SB_DQS 2 BF9 DDR3 1 0 TRST H63 CMOS I SB_DQS 3 BH15 DDR3 1 0 UNCOREPWRGOOD C60 Asynch CMOS I SB DQS 4 BH51 DDR3 1 0 VAXG AH65 PWR SB_DQS 5 BF57 DDR3 1 0 VAXG AH63 PWR SB_DQS 6 AY65 DDR3 1 0 VAXG AH61 PWR SB_DQS 7 AN64 DDR3 1 0 V
32. DPLL_REF_CLK DPLL_REF_CLK DDR3 Reference Clocks Differential DDR3 Output SA_CK 1 0 SA_CK 1 0 SB_CK 1 0 SB_CK 1 0 DDR3 Command Signals Single Ended DDR3 Output SA BS 2 0 SB BS 2 0 SA WE SB WE SA RAS SB RAS SA CAS SB CAS SA MA 15 0 SB MA 15 0 DDR3 Control Signals Single Ended DDR3 Output SA CKE 1 0 SB CKE 1 0 SA CS 1 0 SB CS 1 0 SA ODT 1 0 SB ODT 1 0 SM DRAMRST DDR3 Data Signals Single ended Differential DDR3 Bi directional DDR3 Bi directional SA DQ 63 0 SB DQ 63 0 SA DQS 7 0 SA_DQS 7 0 SB DQS 7 0 SB_DQS 7 0 DDR3 Compensation Analog Bi directional SM RCOMP 2 0 DDR3 Reference TAP ITP XDP Analog Input SM_VREF Input Input BCLK_ITP BCLK_ITP Single Ended CMOS Input TCK TDI TMS TRST Single Ended Open Drain Output TDO Single Ended Output DBR Asynchronous CMOS Bi BPM 7 0 Single Ended Directional i Asynchronous CMOS PREQ Single Ended Input Asynchronous CMOS PRDY Single Ended Output Control Sideband Single Ended CMOS Input CFG 17 0 Asynchronous PROCHOT Single Ended CMOS Open Drain Bi directional Single Ended eu nS CMOS THERMTRIP CATERR utput 342 AA 0 _ gt 92 222 Single Ended Asynchronous CMOS SM_DRAMPWROK UNCOREPWRGOOD PM SYNC RESET Datasheet Volume 1 Electrical Specifications
33. ESA 1531 T rd o e o SNIA 996 Y X E 399 4 Na 1 IF lg E MAAE B NA BS Datasheet Volume 1 160 Processor Pin Signal and Package Information intel Figure 8 11 Processor rPGA988B 4C GT2 E95127 Mechanical Package Sheet 2 of 2 Sf ae o m TTT 0000000000 205000000000 od 0600000000 0600000000000000000000000060000000000 G00000000000000000000000000000000000 000000000000000000000060000000000000 09000000000 9999999099999 6666000000 000000000000000000000000000000000000 900000000000000000000000000000000000 9000000000 600000000060000 0090089909 S o 666 ac i 8 La gt i A T SRO S TEST Era Datasheet Volume 1 161 Processor Pin Signal and Package Information intel Figure 8 12 Processor BGA1023 2C GT1 G24405 Mechanical Package ES ven qs 3 n anu waum E EU DEED y ONIMVYC IVOINVHO3A 30VXOVd y SEN un 2 y mua mu Y PUTET um Times n 4 0118 30311 ENS un 0c ie i Wiondld 1N34NO Ty 3LV8LSENS I a A aa ao 1199 F j Wun a 1H213H Y98 INS 0 D g a 1
34. GPE Any DMI related SERR activity is associated with Device 0 Processor PCH Compatibility Assumptions The processor is compatible with the Intel 7 Series Chipset PCH products DMI Link Down The DMI link going down is a fatal unrecoverable error If the DMI data link goes to data link down after the link was up then the DMI link hangs the system by not allowing the link to retrain to prevent data corruption This link behavior is controlled by the PCH Downstream transactions that had been successfully transmitted across the link prior to the link going down may be processed as normal No completions from downstream non posted transactions are returned upstream over the DMI link after a link down event Processor Graphics Controller GT New Graphics Engine Architecture includes 3D compute elements Multi format hardware assisted decode encode pipeline and Mid Level Cache MLC for superior high definition playback video quality and improved 3D performance and Media The Display Engine handles delivering the pixels to the screen and is the primary channel interface for display memory accesses and PCI like traffic in and out Datasheet Volume 1 Interfaces intel Figure 2 6 Processor Graphics Controller Unit Block Diagram VS GS Vertex Setup Rasterize a Fetch Hierachical Z Hardware Clipper E Unified Execution Unit Array Texture Pixel Backend Additional Post Processing
35. IA32 THERM STATUS MSR 19Ch Code execution is halted in C1 C7 Package temperature can still be monitored through PECI in lower C states It is not recommended to read the package temperature using the processor MSR while in any C state Doing this will bring a core back into CO Unlike traditional thermal devices the DTS outputs a temperature relative to the maximum supported operating temperature of the processor Tj max regardless of TCC activation offset It is the responsibility of software to convert the relative temperature to an absolute temperature The absolute reference temperature is readable in the TEMPERATURE TARGET MSR 1A2h The temperature returned by the DTS is an implied negative integer indicating the relative offset from T max The DTS does not report temperatures greater than Tj max Datasheet Volume 1 Thermal Management m L 5 6 2 1 5 6 2 2 5 6 3 Note Note 5 6 3 1 The DTS relative temperature readout directly impacts the Adaptive Thermal Monitor trigger point When a package DTS indicates that it has reached the TCC activation a reading of Oh except when the TCC activation offset is changed the TCC will activate and indicate a Adaptive Thermal Monitor event A TCC activation will lower both IA core and graphics core frequency voltage or both Changes to the temperature can be detected using two programmable thresholds located in the processor thermal MSRs These thresholds have the capab
36. If the P state target frequency is higher than the processor core optimized target frequency the p state transition will be deferred until the thermal event has been completed e If the P state target frequency is lower than the processor core optimized target frequency the processor will transition to the P state operating point Datasheet Volume 1 75 m L Thermal Management 5 6 1 3 5 6 2 Note Note 76 Clock Modulation If the frequency voltage changes are unable to end an Adaptive Thermal Monitor event the Adaptive Thermal Monitor will utilize clock modulation Clock modulation is done by alternately turning the clocks off and on at a duty cycle ratio between clock on time and total time specific to the processor The duty cycle is adjusted dynamically based on the throttling need and cannot be modified The period of the duty cycle is configured to 32 microseconds when the TCC is active Cycle times are independent of processor frequency A small amount of hysteresis has been included to prevent excessive clock modulation when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases Clock modulation is automatically engaged as part of the TCC activation when the frequency voltage targets are at their minimum settings Processor perfo
37. If the processor enters a low power package idle state such as C3 or C6 C7 with PROCHOT asserted PROCHOT will remain asserted until e The processor exits the low power state e The processor junction temperature drops below the thermal trip point For the package C7 state PROCHOT may de assert for the duration of C7 state residency even if the processor enters the idle state operating at the TCC activation temperature The PECI interface is fully operational during all C states and it is expected that the platform continues to manage processor core and package thermals even during idle states by regularly polling for thermal data over PECI Datasheet Volume 1 Thermal Management m L 5 6 3 5 5 6 3 6 5 6 4 5 6 4 1 5 6 4 2 THERMTRIP Signal Regardless of enabling the automatic or on demand modes in the event of a catastrophic cooling failure the package will automatically shut down when the silicon has reached an elevated temperature that risks physical damage to the product At this point the THERMTRIP signal will go active Critical Temperature Detection Critical Temperature detection is performed by monitoring the package temperature This feature is intended for graceful shutdown before the THERMTRIP is activated However the processor execution is not ensured between critical temperature and THERMTRIP If the Adaptive Thermal Monitor is triggered and the temperature remains high a critical temperature
38. Intel AMT 8 0 Intel Trusted Execution Technology Intel TXT Intel Streaming SIMD Extensions 4 1 Intel SSE4 1 Intel Streaming SIMD Extensions 4 2 Intel SSE4 2 Intel Hyper Threading Technology Intel 64 Architecture Execute Disable Bit Intel Turbo Boost Technology Intel Advanced Vector Extensions Intel AVX Advanced Encryption Standard New Instructions AES NI PCLMULQDQ Instruction RDRAND instruction for random number generation SMEP Supervisor Mode Execution Protection PAIR Power Aware Interrupt Routing 1 2 Interfaces 1 2 1 System Memory Support Datasheet Volume 1 Two channels of DDR3 DDR3L DDR3L RS memory with Unbuffered Small Outline Dual In Line Memory Modules SO DIMM with a maximum of two DIMMs per channel Note 2 DIMMs per channel supported only in Quad Core rPGA package only Single channel and dual channel memory organization modes Data burst length of eight for all memory organization modes System Memory Interface I O Voltage of 1 35 V and 1 5 V DDR3 DDR3L and DDR3L RS DIMMs DRAMs running at 1 5 V DDR3L and DDR3L RS DIMMS DRAMS running at 1 35 V Support memory configurations that mix DDR3 DIMMs DRAMs with DDR3L DDR3L RS DIMMs DRAMs running at 1 5 V 64 bit wide channels Non ECC Unbuffered DDR3 DDR3L DDR3L RS SO DIMMs only Theoretical maximum memory bandwidth of 21 3 GB s in dual channel mode assuming DDR3 1333 MT s 25 6 GB s in dual channel mode assumi
39. Intel Turbo Boost Technology power control is shown in the following sections and figures Multiple controls operate simultaneously allowing for customization for multiple system thermal and power limitations These controls allow for Turbo optimizations within system constraints and are accessible using MSR MMIO or PECI interfaces Package Power Control Intel Turbo Boost Technology package power control allows for customization in order to implement optimal Turbo within platform power delivery and package thermal solution limitations The control settings are shown in Table 5 1 while the behavior is illustrated in Figure 5 1 Datasheet Volume 1 Thermal Management intel Table 5 1 Intel Turbo Boost Technology Package Power Control Settings MSR Address MSR_TURBO_POWER_LIMIT 610h Control Bit Default Description POWER_LIMIT_1 PL1 14 0 SKU TDP This value sets the exponentially weighted moving average power limit over a long time period This is normally aligned to the TDP of the part and steady state cooling capability of the thermal solution This limit may be set lower than TDP real time for specific needs such as responding to a thermal event If set lower than TDP the processor may not be able to honor this limit for all workloads since this control only applies in the Turbo frequency range a very high powered application may exceed POWER_LIMIT_1 even at non Turbo frequencies PL
40. K37 PWR VCC E38 PWR VCC K35 PWR VCC E37 PWR VCC K34 PWR VCC E34 PWR VCC K32 PWR VCC E32 PWR VCC K29 PWR VCC E28 PWR VCC K27 PWR VCC E26 PWR VCC K26 PWR VCC D42 PWR VCC J42 PWR VCC D39 PWR VCC J40 PWR VCC D37 PWR VCC J38 PWR VCC D34 PWR VCC J37 PWR VCC D32 PWR VCC J35 PWR VCC D27 PWR VCC J34 PWR VCC C42 PWR VCC J32 PWR VCC C39 PWR VCC J29 PWR VCC C37 PWR VCC J28 PWR VCC C34 PWR VCC J26 PWR VCC C32 PWR VCC J25 PWR VCC C27 PWR VCC H40 PWR VCC C26 PWR VCC H38 PWR VCC A42 PWR VCC H37 PWR VCC A39 PWR VCC H35 PWR VCC A38 PWR VCC H34 PWR VCC A35 PWR VCC H32 PWR VCC A34 PWR VCC H29 PWR VCC A31 PWR VCC H28 PWR VCC A29 PWR VCC H26 PWR VCC A26 PWR VCC H25 PWR VCC_DIE_SENSE F48 Analog O Datasheet Volume 1 149 m n tel Processor Pin Signal and Package Information Table 8 3 BGA1023 Processor Ball List Table 8 3 BGA1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir vCC_SENSE F43 Analog O VCCIO AG15 PWR VCC_VAL_SENSE H43 Analog O VCCIO AF46 PWR VCCDQ AN26 PWR VCCIO AF20 PWR VCCDQ AM28 PWR VCCIO AF18 PWR VCCIO AN48 PWR VCCIO AF16 PWR VCCIO AN45 PWR VCCIO AE15 PWR VCCIO AN42 PWR VCCIO AE14 PWR VCCIO AN20 PWR VCCIO AD21 PWR VCCIO AM47 PWR VCCIO AD18 PWR VCCIO AM43 PWR VCCIO AD16 PWR VCCIO AM21 PWR VCCIO AC13 PWR VCCIO AM17 PWR VCCIO AB20 PWR
41. Memory Controller IMC supports DDR3 DDR3L DDR3L RS protocols with two independent 64 bit wide channels each accessing one or two DIMMs The IMC supports one or two unbuffered non ECC DDR3 DIMM per channel thus allowing up to four device ranks per channel The processor supports only JEDEC approved memory modules and devices 2 DIMMs per channel supported only in Quad Core rPGA package Processor Mobile DIMM Support Summary by Product DDR3 DDR3L DDR3L Processor cores Package DIMM per channel DDR3L RS DDR3L RS 1 5V 1 35 V Dual Core rPGA BGA 1 DPC 1333 1600 1333 1600 Quad Core Quad Core rPGA 2 DPC 1333 1600 1333 e DDR3 DDR3L DDR3L RS at 1 5 V Data Transfer Rates 1333 MT s PC3 10600 1600 MT s PC3 12800 e DDR3L DDR3L RS at 1 35 V Data Transfer Rates 1333 MT s PC3 10600 1600 MT s PC3 12800 e DDR3 DDR3L DDR3L RS DRAM Device Technology Standard 1 Gb 2 Gb and 4 Gb technologies and addressing are supported for x16 and x8 devices There is no support for memory modules with different technologies or capacities on opposite sides of the same memory module If one side of a memory module is populated the other side is either identical or empty Datasheet Volume 1 23 intel Table 2 2 Interfaces Supported DDR3 DDR3L DDR3L RS SO DIMM Module Configurations Table 2 3 2 1 2 24 Cd DI
42. Modulation Technology Intel GPMT is a method for saving power in the graphics adapter while continuing to display and process data in the adapter This method will switch the render frequency and or render voltage dynamically between higher and lower power states supported on the platform based on render engine workload When the system is running in battery mode and if the end user launches applications such as 3D or Video the graphics software may switch the render frequency dynamically between higher and lower power performance states depending on the render engine workload In products where Intel Graphics Dynamic Frequency also known as Turbo Boost Technology is supported and enabled the functionality of Intel GPMT will be maintained by Intel Graphics Dynamic Frequency also known as Turbo Boost Technology Datasheet Volume 1 61 m L Power Management 4 6 3 Caution 4 6 4 4 6 5 62 Graphics Render C State Render C State RC6 is a technique designed to optimize the average power to the graphics render engine during times of idleness of the render engine Render C state is entered when the graphics render engine blitter engine and the video engine have no workload being currently worked on and no outstanding graphics memory transactions When the idleness condition is met then the Integrated Graphics will program the VR into a low voltage state 0V through the SVID bus Long term reliability cannot be
43. PWR VAXG R62 PWR VCC N33 PWR VAXG R60 PWR VCC N30 PWR VAXG R55 PWR VCC N26 PWR VAXG R53 PWR VCC N24 PWR VAXG R48 PWR VCC N20 PWR 130 Datasheet Volume 1 Processor Pin Signal and Package Information Table 8 2 BGA1224 Processor Ball List by Ball Name Continued intel Table 8 2 BGA1224 Processor Ball List by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball 4 Buffer Type Dir VCC M46 PWR VCC H31 PWR VCC 42 PWR VCC H29 PWR VCC 40 PWR VCC H25 PWR VCC M36 PWR VCC G44 PWR VCC M34 PWR VCC G40 PWR VCC 29 PWR VCC G38 PWR VCC 27 PWR VCC G34 PWR VCC M23 PWR VCC G32 PWR VCC M21 PWR VCC G28 PWR VCC L44 PWR VCC G26 PWR VCC L40 PWR VCC F45 PWR VCC L38 PWR VCC F43 PWR VCC L34 PWR VCC F41 PWR VCC L32 PWR VCC F37 PWR VCC L28 PWR VCC F35 PWR VCC L26 PWR VCC F31 PWR VCC L22 PWR VCC F29 PWR VCC K45 PWR VCC F25 PWR VCC K43 PWR VCC E44 PWR VCC K41 PWR VCC E40 PWR VCC K37 PWR VCC E38 PWR VCC K35 PWR VCC E34 PWR VCC K31 PWR VCC E32 PWR VCC K29 PWR VCC E28 PWR VCC K25 PWR VCC E26 PWR VCC J44 PWR VCC D45 PWR VCC J40 PWR VCC D43 PWR VCC J38 PWR VCC D41 PWR VCC J34 PWR VCC D37 PWR VCC J32 PWR VCC D35 PWR VCC J28 PWR VCC D31 PWR VCC J26 PWR VCC D29 PWR VCC H45 PWR VCC C44 PWR VCC H43 PWR VCC C40 PWR VCC H41 PWR VCC C38 PWR VCC H37 PWR VCC C34
44. SOONE UB to 45 w ur MG LFM 1200 MHz 40 LPM 800 MHz 35 2 3 GHz up to HFM 45 Quad Core SV 3 7 GHz 330 MNZ Up tO w 1 2 7 LFM 1200 MHz 35 2 1 GHz up to HFM 35 Quad Core SV 3 1 GHz ER w 1 2 7 LFM 1200 MHz 30 2 4 GHz up to HFM 35 3 6 GHz 350 MHz up to Dual Core SV 1250 MHz WwW 1 2 7 LFM 1200 MHz 30 TDP Up 25 TDP Nominal HFM rs Ka 17 Dual Core 350 MHz up to 1 2 7 17 Ultra TDP Down 1100 MHz 14 w 18 LFM 800 MHz 14 LPM 800 MHz 12 5 Table 5 4 Junction Temperature Specification Segment Symbol Package Turbo Parameter Min Default Max Units Notes Extreme Edition XE T Junction temperature limit 0 105 3 4 5 Quad Core SV Tj Junction temperature limit 0 105 C 3 4 5 Dual Core SV T Junction temperature limit 0 105 3 4 5 16 Ultra Tj Junction temperature limit 0 105 3 4 5 Datasheet Volume 1 71 intel Thermal Management Table 5 5 Package Turbo Parameters Segment Symbol Package Turbo Parameter Min Bebe dE Max Units Notes um Turbo long duration time window urbo lime P t POWER LIMIT 1 TIME in N A 1 N A 10 11 package IURBO POWER LIMIT MSR 0610h bits R 14 23 17 Long duration Turbo power limit Extreme Long P POWER_LIMIT_1 in N A 55 N A w 10 12 Edition XE package TURBO_POWER_LIMIT MSR 0610h bits 13 14 14 0 Short duration Turbo power limit Short P POWER_LIMIT_2 in 1 25 x 10 14 N A N A W package TURBO_POWER_LIMIT MSR 0610
45. TURBO POWER LIMIT MSR 0610h bits 17 N 15 ud 46 32 72 Datasheet Volume 1 Thermal Management m L Table 5 6 Idle Power Specifications Segment Symbol Idle Parameter Min Typ Max Units Notes Po a power in the Package C6 a 36 w 6 9 Extreme Edition SHORE XE P Idle power in the Package 3 5 w 6 9 c7 C7state d s i d Pee EID in the Package C6 S 34 w 6 9 Quad Core SV 45W Idle power in the Package Pc CREE 9 3 0 W 6 9 Idle power in the Package C6 Dual Core and Pce state R 3 3 0 W 6 9 Quad Core SV 35W Idle power in the Package E l Pc C7state 2 9 Ww 6 9 Bie Idle power in the Package C6 E 23 w 6 9 state Dual Core Ultra Idle power in the Package Pc Cho 9 2 2 w 6 9 5 6 Datasheet Volume 1 Thermal Management Features Thermal management features for the entire processor complex including the processor core the graphics core and integrated memory controller hub will be referred to as processor package or by simply the package Occasionally the package will operate in conditions that exceed its maximum allowable operating temperature This can be due to internal overheating or due to overheating in the entire system To protect processor package and the system from thermal failure several thermal management features exist to reduce package power consumption and thereby temperature in order to remain
46. Up Down 1 9 3 SV QC 1 9 SLOPE Processor Loadline SV DC 1 9 mo Ultra TDP nom Up Down 2 9 Notes 1 Unless otherwise noted all specifications in this table are based on post silicon estimates and simulations or empirical data 2 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same freguency may have different settings within the VID range This differs from the VID employed by the processor during a power or thermal management event Intel Adaptive Thermal Monitor Enhanced Intel SpeedStep Technology or Low Power States 3 The voltage specification requirements are measured across VCC SENSE and VSS SENSE pins at the socket with a 20 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe 4 Processor core VR to be designed to electrically support this current 5 Processor core VR to be designed to thermally support this current indefinitely 6 This specification assumes that Intel Turbo Boost Technology is enabled 7 Long term reliability cannot be assured if tolerance ripple and core noise parameters are violated 8 Long term reliability cannot be ass
47. a frequency and width compatible with the remote device Datasheet Volume 1 29 PCI Express Configuration Mechanism Interfaces The PCI Express external graphics link is mapped through a PCI to PCI bridge structure Figure 2 4 PCI Express Related Register Structures in the Processor 30 PCI Express Device PEGO PCI PCI Bridge representing root PCI Express ports Device 1 and PCI Compatible Host Bridge Device Device 0 Device 6 DMI PCI Express extends the configuration space to 4096 bytes per device function as compared to 256 bytes allowed by the Conventional PCI Specification PCI Express configuration space is divided into a PCI compatible region that consists of the first 256 bytes of a logical device s configuration space and an extended PCI Express region that consists of the remaining configuration space The PCI compatible region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express configuration access mechanism described in the PCI Express Enhanced Configuration Mechanism section The PCI Express Host Bridge is required to translate the memory mapped PCI Express configuration space accesses from the host processor to PCI Express configuration cycles To maintain compatibility with PCI configuration addressing mechanisms it is recommended that system software access the enhanced configuration spa
48. and number of cores in deep C states e The core power and temperature are reduced while minimizing performance degradation Once the temperature has dropped below the maximum operating temperature operating frequency and voltage transition will go back to the normal system operating point This is illustrated in Figure 5 2 Datasheet Volume 1 Thermal Management intel Figure 5 2 Frequency and Voltage Ordering E PROCHOT Once a target frequency bus ratio is resolved the processor core will transition to the new target automatically e On an upward operating point transition the voltage transition precedes the frequency transition e On a downward transition the frequency transition precedes the voltage transition When transitioning to a target core operating voltage a new VID code to the voltage regulator is issued The voltage regulator must support dynamic VID steps to support this method During the voltage change e It will be necessary to transition through multiple VID steps to reach the target operating voltage e Each step is 5 mV for Intel MVP 7 0 compliant VRs e The processor continues to execute instructions However the processor will halt instruction execution for frequency transitions If a processor load based Enhanced Intel SpeedStep Technology P state transition through MSR write is initiated while the Adaptive Thermal Monitor is active there are two possible outcomes e
49. assured unless all the Low Power Idle States are enabled Intel Smart 2D Display Technology Intel S2DDT Intel S2DDT reduces display refresh memory traffic by reducing memory reads required for display refresh Power consumption is reduced by less accesses to the IMC S2DDT is only enabled in single pipe mode Intel S2DDT is most effective with e Display images well suited to compression such as text windows slide shows and so on Poor examples are 3D games e Static screens such as screens with significant portions of the background showing 2D applications processor benchmarks and so on or conditions when the processor is idle Poor examples are full screen 3D games and benchmarks that flip the display image at or near display refresh rates Intel Graphics Dynamic Frequency Intel Graphics Dynamic Frequency Technology is the ability of the processor and graphics cores to opportunistically increase frequency and or voltage above the ensured processor and graphics frequency for the given part Intel Graphics Dynamic Frequency Technology is a performance feature that makes use of unused package power and thermals to increase application performance The increase in frequency is determined by how much power and thermal budget is available in the package and the application demand for additional processor or graphics performance The processor core control is maintained by an embedded controller The graphics driver dynamically a
50. firmware Implementing cTDP using the DPTF driver is recommended as Intel does not provide specific application or EC source code CTDP consists of three modes as shown in Table 5 2 Datasheet Volume 1 Thermal Management m L Table 5 2 5 4 2 Configurable TDP Modes Mode Description Nominal This is the processor s rated frequency and TDP When extra cooling is available this mode specifies a higher TDP and higher ensured TDP Up frequency versus the nominal mode When a cooler or quieter mode of operation is desired this mode specifies a lower TDP and TDP Down 9 lower ensured frequency versus the nominal mode In each mode the Intel Turbo Boost Technology power and frequency ranges are reprogrammed and the operating system is given a new effective HFM operating point The driver assists in all these operations The cTDP mode does not change the maximum Turbo frequency Low Power Mode Low Power Mode LPM can provide an operation point at lower power than TDP down By combining several active power limiting techniques the processor can consume less power while running at equivalent low frequencies Active power is defined as processor power consumed while a workload is running and does not refer to the power consumed during idle modes of operation LPM is only available using the Intel DPTF driver Through the DPTF driver LPM can be configured to use each of the following methods t
51. hardware based flushing of translated but pending writes and pending reads on IOTLB invalidation e Support for page selective IOTLB invalidation e MSI cycles MemWr to address FEEx_xxxxh not translated Translation faults result in cycle forwarding to VBIOS region byte enables masked for writes Returned data may be bogus for internal agents PEG DMI interfaces return unsupported request status e Interrupt Remapping is supported e Queued invalidation is supported e VT d translation bypass address range is supported Pass Through Intel VT d Technology may not be available on all SKUs Intel VT d Features Not Supported The following features are not supported by the processor with Intel VT d e No support for PCIe endpoint caching ATS e No support for Intel VT d read prefetching snarfing that is translations within a cacheline are not stored in an internal buffer for reuse for subsequent translations e No support for advance fault reporting e No support for super pages e No support for Intel VT d translation bypass address range such usage models need to be resolved with VMM help in setting up the page tables correctly Intel Trusted Execution Technology Intel TXT Intel Trusted Execution Technology Intel TXT defines platform level enhancements that provide the building blocks for creating trusted platforms The Intel TXT platform helps to provide the authenticity of the controlling environment such that th
52. intel Mobile 3rd Generation Intel Core Processor Family Datasheet Volume 1 of 2 June 2012 Document Number 326768 003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT A Mission Critical Application is any application in which failure of the Intel Product could result directly or indirectly in personal injury or death SHOULD YOU PURCHASE OR USE INTEL S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES SUBCONTRACTORS AND AFFILIATES AND THE DIRECTORS OFFICERS AND EMPLOYEES OF EACH HARMLESS AGAINST ALL CLAIMS COSTS DAMAGES AND EXPENSES AND REASONABLE ATTORNEYS FEES ARISING OUT OF DIRECTLY OR INDIRECTLY ANY CLAIM OF PRODUCT LIABILITY PERSONAL INJURY OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN MANUFACTURE OR WARNING OF THE INTEL PRODUCT OR ANY
53. message is forwarded to the target core If the break event is not masked the target core enters the core CO state and the processor enters package CO e If the break event was due to a memory access or snoop request But the platform did not request to keep the processor in a higher package C state the package returns to its previous C state And the platform requests a higher power C state the memory access or snoop request is serviced and the package remains in the higher power C state Table 4 11 shows package C state resolution for a dual core processor Figure 4 4 summarizes package C state transitions Table 4 11 Coordination of Core Power States at the Package Level Core 1 Package C State co C1 c3 C6 C7 co co co CO CO CO C1 co cit ci ci cii Core 0 c3 CO C1 C3 C3 C3 C6 CO C1 C3 C6 C6 C7 CO cit C3 C6 C7 Note If enabled the package C state will be C1E if all cores have resolved a core C1 state or higher Figure 4 4 Package C State Entry and Exit Datasheet Volume 1 55 m L Power Management 4 2 5 1 4 2 5 2 4 2 5 3 4 2 5 4 56 Package CO Package CO is the normal operating state for the processor The processor remains in the normal state when at least one of its cores is in the CO or C1 state or when the platform has not granted permission to the processor to go into a low power stat
54. range field of the PMG_IO_CAPTURE MSR to restrict the range of I O addresses that are trapped and emulate MWAIT like functionality Any P_LVLx reads outside of this range does not cause an I O redirection to an MWAIT Cx like request They fall through like a normal I O instruction When P LVLx I O instructions are used MWAIT substates cannot be defined The MWAIT substate is always zero if I O MWAIT redirection is used By default P LVLx I O redirections enable the MWAIT break on EFLAGS IF feature that triggers a wakeup on an interrupt even if interrupts are masked by EFLAGS IF Datasheet Volume 1 Power Management intel 4 2 4 4 2 4 1 4 2 4 2 4 2 4 3 4 2 4 4 Core C states The following are general rules for all core C states unless specified otherwise e A core C State is determined by the lowest numerical thread state such as Thread O requests C1E while Thread 1 requests C3 resulting in a core C1E state See Table 4 7 e A core transitions to CO state when An interrupt occurs There is an access to the monitored address if the state was entered using an MWAIT instruction e For core C1 C1E core C3 and core C6 C7 an interrupt directed toward a single thread wakes only that thread However since both threads are no longer at the same core C state the core resolves to CO A system reset re initializes all processor cores Core CO State The normal operating state of a core where code is b
55. than its rated operating core and or render clock frequency when there is sufficient power headroom and the product is within specified temperature and current limits The Intel Turbo Boost Technology feature is designed to increase performance of both multi threaded and single threaded workloads The processor supports a Turbo mode where the processor can use the thermal capacity associated with the package and run at power levels higher than TDP power for short durations This improves the system responsiveness for short bursty usage conditions The turbo feature needs to be properly enabled by BIOS for the processor to operate Datasheet Volume 1 Technologies 3 4 1 3 4 2 Note intel with maximum performance Since the turbo feature is configurable and dependent on many platform design limits outside of the processor control the maximum performance cannot be ensured Turbo Mode availability is independent of the number of active cores however the Turbo Mode frequency is dynamic and dependent on the instantaneous application power load the number of active cores user configurable settings operating environment and system design Intel Turbo Boost Technology Frequency The processor s rated frequency assumes that all execution cores are active and are at the sustained thermal design power TDP However under typical operation not all cores are active or at executing a high power workload Therefore most applications ar
56. uA 3 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The Vccro referred to in these specifications refers to instantaneous Vccro 3 For Vjy between 0 V and Vccro Measured when the driver is tristated 4 Vy and Voy may experience excursions above Vccro However input signal drivers must comply with the 104 signal guality specifications Datasheet Volume 1 Electrical Specifications Table 7 13 PCI Express DC Specifications Symbol Parameter Min Typ Max Units Notes DC Differential Tx Impedance a ZTX DIFF DC Gen 1 Only 80 120 Q 2 DC Differential Tx Impedance Zwe orr 0c Gen 2 and Gen 3 tag Q 2 ZRX DC DC Common Mode Rx Impedance 40 60 Q 3 4 DC Differential Rx Impedance ZRX DIFF DC Gen1 Only 80 120 Q PEG_ICOMPO Comp Resistance 24 75 25 25 25 Q 5 6 PEG_ICOMPI Comp Resistance 24 75 25 25 25 Q 5 6 PEG_RCOMPO Comp Resistance 24 75 25 25 25 Q 5 Notes OO A Mr Refer to the PCI Express Base Specification for more details Low impedance defined during signaling Parameter is captured for 5 0 GHz by RLTX DIFF COMP resistance must be provided on the system board with 1 resistors COMP resistors are to Vccro PEG ICOMPO PEG ICOMPI PEG RCOMPO are the same resistor Intel allows using 24 9 O 1 resistors DC impedance limits are needed to ensure Receiver detect The Rx DC Common Mode Impedance must b
57. 0 Processor Graphics V ax Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note Active VID Range for VaxG XE SV QC 45W 0 65 1 35 Cre SV QC 35W SV DC 0 65 1 35 v Se Ultra DC 0 65 1 25 VAXG Processor Graphics core voltage 0 1 52 V Max Current for Processor Graphics Rail XE SV QC 45W 46 SV QC 35W 33 IccMAx VAXG sy DC GT2 E 33 A SV DC GT1 20 Ultra DC GT2 29 Ultra DC GT1 18 Thermal Design Current TDC for Processor Graphics Rail XE SV QC 45W 35 SV QC 35W 21 5 SV DC GT2 21 5 Iccroc_vax6 sy pc GT1 18 A Ultra DC GT2 TDP nominal 18 3 Ultra DC GT2 TDP Up 18 3 Ultra DC GT2 TDP Down 7 05 Ultra DC GT1 12 Vaxg Tolerance PSO PS1 15 mV 4 PS2 PS3 11 5 mV 4 Ripple Tolerance PSO PS1 18 mV 4 Ripple PS2 7 5 18 5 mV 4 PS3 7 5 27 5 mV Vaxg Loadline LLaxG GT2 based units 3 9 ma GTi based units 4 6 ma Notes 1 Unless otherwise noted all specifications in this table are based on post silicon estimates and simulations or empirical data 2 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Please note this differs from the VID employed by th
58. 0000000000 900000 3 t cos900000 0000000000000 900 990000 000 ooo o ooo9 99 29 99 So 00000 Sue 230000 08 9990 900009 9 99 8 Y ooo 998 385 999099 00 990 90000 p ooo 999 009 9000 000500 oo 08007 900 300009 9990 900000 9 99999 o 3 80008 0990 999899 Go 09999 goo 5 999 09009 9990 858858 9900 09 909 995 i 98 9 00000000000000000000000p000000000000099906 B Lo t 3829 909 999 909 990 900 999 909 999 999 999 209 0408000 X h 9090 0 0 o9g 0 0 ado 090 090 090 090 090 0900000 TH Ia 02 39YN2vd FHL E04 118 in S133W m e9 TEES n Datasheet Volume 1 162 intel Processor Pin Signal and Package Information Figure 8 13 Processor BGA1023 2C GT2 G23866 Mechanical Package 2 In A aim asc sE cos 9NIMVHCO IVOINVHO3W 30V DVd HU EEN mu 056 un SE aL Tn RTH hielo 71L des HIM d INV TOL CY SNOISNIN 3141345 2 IWA INIO EU 201 34 4d 10s 130 53434 1193810 139430 404 yA 9990090 950 050 0 00000000b0000 0 0 050 o 090 090 o 000069005090 0 G0 00000000000000000 0 009000000 o 80060 000090009 90 o o 20 doo 99898 90004000090 99 0 EES 28 288 08 8000400009025 99999 oc gos 989
59. 0000095 eebe EE ee d zi E dh La is ao x 4 i N H li I i j D oe p a 5 Fl x E A ken eat T gt r Qu 1 EIE 1 S cn o N o d A M a a an 164 Datasheet Volume 1 DDR Data Swizzling intel 9 DDR Data Swizzling To achieve better memory performance and timing Intel Design performed DDR Data pin swizzling that allows a better use of the product across different platforms Swizzling has no effect on functional operation and is invisible to the operating system software However during debug swizzling needs to be taken into consideration Therefore this swizzling information is presented When placing a DIMM logic analyzer the design engineer must pay attention to the swizzling table to be able to debug memory efficiently Datasheet Volume 1 165 n tel DDR Data Swizzling Table 9 1 DDR Data Swizzling Table 9 1 DDR Data Swizzling Table Channel A Table Channel A Pin ame number number number Wem Pin name number number number Nome SA DO 0 C5 AG6 AL6 DQ06 SA DQ 39 AJ6 AY48 AY51 DQ34 SA DO 1 D5 AJ6 ALS DQ05 SA DQ 40 AJ8 BA49 BC54 DQ45 SA DQ 2 D3 AP11 AP7 DQO1 SA DQ 41 AK8 AV49 AY53 DQ44 SA DQI3 D2 AL6 AM5 DQ00 SA DQ 42 A
60. 1 0 0 6 0 27500 1 0 0 0 0 1 1 0 8 6 0 91500 0 0 0 0 0 1 1 1 0 7 0 28000 1 0 0 0 0 1 1 1 8 7 0 92000 0 0 0 0 1 0 0 0 0 8 0 28500 1 0 0 0 1 0 0 O 8 8 0 92500 0 0 0 0 1 0 0 1 0 9 0 29000 1 0 0 0 1 0 0 1 8 9 0 93000 0 0 0 0 1 0 1 0 0 A 0 29500 1 0 0 0 1 0 1 0 8 A 0 93500 0 0 0 0 1 0 1 1 0 B 0 30000 1 0 0 0 1 0 1 1 8 B 0 94000 0 0 0 0 1 1 0 0 0 C 0 30500 1 0 0 0 1 1 0 O 8 C 0 94500 0 0 0 0 1 1 0 1 0 D 0 31000 1 0 0 0 1 1 0 1 8 DJ 0 95000 0 0 0 0 1 1 1 0 0 E 0 31500 1 0 0 0 1 1 1 O 8 E 0 95500 0 0 0 0 1 1 1 1 0j F 0 32000 1 0 0 0 1 1 1 1 8 F 0 96000 0 0 0 1 0 0 0 0 1 0 0 32500 1 0 0 1 0 0 0 019 0 0 96500 0 0 0 1 0 0 0 1 1 1 0 33000 1 0 0 1 0 0 0 1 9 1 0 97000 0 0 0 1 0 0 1 0 1 2 0 33500 1 0 0 1 0 0 1 O 9 2 0 97500 0 0 0 1 0 0 1 1 1 3 0 34000 1 0 0 1 0 0 1 1 9 3 0 98000 0 0 0 1 0 1 0 0 1 4 0 34500 1 0 0 1 0 1 0 0 9 4 0 98500 0 0 0 1 0 1 0 1 1 5 0 35000 1 0 0 1 0 1 0 1 91 5 0 99000 0 0 0 1 0 1 1 0 1 6 0 35500 1 0 0 1 0 1 1 O 9 6 0 99500 0 0 0 1 0 1 1 1 1 7 0 36000 1 0 0 1 0 1 1 1 9 7 1 00000 92 Datasheet Volume 1 intel Electrical Specifications Sheet 2 of 3 VID VID VID VID VID VID VID VID inition IMVP7 Voltage Identification Def Table 7 1 1 00500 1 01000 1 01500 1 02000 1 02500 1 03000 1 03500 1 04000 1 04500 1 05000 1 05500 1 06000 1 0
61. 1 0 SB_BS 2 R6 DDR3 O SA_DQ 56 AJ14 DDR3 1 0 SB_CAS AA10 DDR3 O SA_DQ 57 AH14 DDR3 1 0 SB_CLK 0 AD2 DDR3 O SA_DQ 58 AL15 DDR3 1 0 SB_CLK 1 AD1 DDR3 O SA_DQ 59 AK15 DDR3 1 0 SB CK 0 AE2 DDR3 O SA_DQ 60 AL14 DDR3 1 0 SB_CK 1 AE1 DDR3 O SA_DQ 61 AK14 DDR3 1 0 SB_CKE 0 R9 DDR3 O SA_DQ 62 AJ15 DDR3 1 0 SB_CKE 1 R10 DDR3 O SA_DQ 63 AH15 DDR3 1 0 SB_CS 0 AD3 DDR3 O SA_DQS 0 C4 DDR3 1 0 SB_CS 1 AE3 DDR3 O SA_DQS 1 G6 DDR3 1 0 SB_DIMM_VREFDQ D1 Analog O SA_DQS 2 33 DDR3 1 0 SB_DQ 0 C9 DDR3 1 0 SA_DQS 3 M6 DDR3 1 0 SB_DQ 1 A7 DDR3 1 0 SA_DQS 4 AL6 DDR3 1 0 SB_DQ 2 D10 DDR3 1 0 SA_DQS 5 AM8 DDR3 1 0 SB_DQ 3 C8 DDR3 1 0 SA_DQS 6 AR12 DDR3 1 0 SB DQ 4 A9 DDR3 1 0 SA_DQS 7 AM15 DDR3 1 0 SB DQ 5 A8 DDR3 1 0 SA_DQS 0 D4 DDR3 1 0 SB DQ 6 D9 DDR3 1 0 SA_DOS 1 F6 DDR3 1 0 SB_DQ 7 D8 DDR3 1 0 SA_DQS 2 K3 DDR3 1 0 SB_DQ 8 G4 DDR3 1 0 SA_DQS 3 N6 DDR3 1 0 SB_DQ 9 F4 DDR3 1 0 SA_DOS 4 AL5 DDR3 1 0 SB_DQ 10 F1 DDR3 1 0 SA DQS 5 AM9 DDR3 1 0 SB_DQ 11 G1 DDR3 1 0 SA_DQS 6 AR11 DDR3 1 0 SB_DQ 12 G5 DDR3 1 0 SA_DQS 7 AM14 DDR3 1 0 SB_DQ 13 FS DDR3 1 0 SA_MA 0 AD10 DDR3 O SB_DQ 14 F2 DDR3 1 0 SA_MA 1 wi DDR3 O SB_DQ 15 G2 DDR3 1 0 SA_MA 2 w2 DDR3 O SB DQ 16 J7 DDR3 1 0 SA_MA 3 Wi DDR3 O SB_DQ 17 J8 DDR3 1 0 SA_MA 4 v3 DDR3 O SB_DQ 18 K10 DDR3 1 0 SA_MA 5 v2 DDR3 O SB_DQ 19 K9 DDR3 1 0 SA_MA 6 w3 DDR3 O SB_DQ 20 J9 DDR3 1 0 SA_MA 7 W6 DDR3 O SB_DQ 21 J10 DDR3 1 0 SA_MA 8 Vi DDR3 O SB_DQ 22 K8 DDR
62. 1 limit may be set slightly higher than TDP If set higher than TDP the processor could stay at that power level continuously and cooling solution improvements may be required POWER LIMIT 1 TIME Turbo Time Parameter 23 17 1 sec This value is a time parameter that adjusts the algorithm behavior The exponentially weighted moving average Turbo algorithm will use this parameter to maintain time averaged power at or below POWER LIMIT 1 The default value is 1 second but 28 seconds is recommended for most mobile applications POWER LIMIT 2 PL2 46 32 1 25 x TDP Establishes the upper power limit of Turbo operation above TDP primarily for platform power supply considerations Power may exceed this limit for up to 10 ms The default for this limit is 1 25 x nominal TDP Setting this limit to TDP will limit the processor to only operating up to TDP but it does not disable Turbo Because Turbo is opportunistic and power temperature dependant many workloads will allow some Turbo frequencies at power at or below TDP Figure 5 1 Package Power Control Short duration turbo power limit Power limit 2 P gt Power limit 2 lt 10msec exceedence Long duration turbo power limit Power limit 1 d System Thermal Response Time Datasheet Volume 1 67 m L Thermal Management 5 3 2 5 3 3 5 4 5 4 1 Note 68 Power Plane Control The proce
63. 19 GND VSS AP10 GND VSS AY14 GND VSS AP7 GND VSS AY9 GND VSS AN54 GND VSS AY4 GND VSS AN50 GND VSS AW61 GND VSS AN47 GND VSS AW43 GND VSS AN43 GND VSS AW13 GND VSS AN40 GND VSS AW7 GND VSS AN36 GND VSS AV55 GND VSS AN33 GND VSS AV48 GND VSS AN28 GND VSS AV40 GND VSS AN25 GND VSS AV34 GND VSS AN21 GND VSS AV22 GND VSS AN1 GND VSS AV21 GND VSS AM58 GND VSS AV17 GND VSS AM48 GND VSS AU51 GND VSS AM45 GND VSS AU32 GND VSS AM42 GND VSS AU28 GND VSS AM38 GND VSS AU11 GND VSS AM34 GND VSS AU7 GND VSS AM30 GND VSS AU1 GND VSS AM26 GND VSS AT58 GND VSS AM22 GND VSS AT52 GND VSS AM20 GND VSS AT45 GND VSS AM13 GND VSS AT36 GND VSS AM4 GND VSS AT19 GND VSS AL61 GND VSS AT14 GND VSS AL47 GND VSS AT4 GND VSS AL43 GND VSS AR61 GND VSS AL40 GND VSS AR48 GND VSS AL36 GND VSS AR41 GND VSS AL33 GND 152 Datasheet Volume 1 Processor Pin Signal and Package Information Table 8 3 BGA1023 Processor Ball List by Ball Name Continued intel Table 8 3 BGA1023 Processor Ball List by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball 4 Buffer Type Dir VSS AL28 GND VSS AF48 GND VSS AL25 GND VSS AF47 GND VSS AL21 GND VSS AF21 GND VSS
64. 3 1 0 RSVD_NCTF B34 SA_DQ 3 D2 DDR3 1 0 RSVD_NCTF A34 SA_DQ 4 D6 DDR3 1 0 RSVD_NCTF A33 SA DQ 5 C6 DDR3 1 0 RSVD_NCTF AT33 F sanD08g c2 DDR y RSVD_NCTF AT2 sADQ7 c3 DDR yo RSVD NCTF ATI SA DQI8 Fi0 DR y0 RSVD NCTF AR35 sADQ S Fs DDR yo RSVD_NCTF AR34 F sa DQ U10 Gio DDR YO RSVD_NCTF AR1 SA DQ ii co DDR yo RSVD NCTF AP35 SA DQ 12 F9 DDR3 1 0 RSVD_NCTF C35 SA_DQ 13 F7 DDR3 1 0 SA_CKE 2 w9 DDR3 O SA_DQ 14 G8 DDR3 1 0 SA_CKE 3 W10 DDR3 O SA_DQ 15 G7 DDR3 1 0 SA_CLK 2 AAA DDR3 O SA_DQ 16 K4 DDR3 1 0 SA_CLK 3 AA3 DDR3 O SA_DQ 17 K5 DDR3 1 0 SA_CK 2 AB4 DDR3 O SA_DQ 18 Ki DDR3 1 0 SA_CK 3 AB3 DDR3 O SA_DQ 19 J1 DDR3 1 0 SA_CS 2 AG1 DDR3 O SA_DQ 20 J5 DDR3 1 0 SA_CS 3 AH1 DDR3 O SA_DQ 21 J4 DDR3 1 0 SA_ODT 2 AG2 DDR3 O SA_DQ 22 32 DDR3 1 0 SA_ODT 3 AH2 DDR3 O SA_DQ 23 K2 DDR3 1 0 SB_CKE 2 T9 DDR3 O SA_DQ 24 M8 DDR3 1 0 SB_CKE 3 T10 DDR3 O SA_DQ 25 N10 DDR3 1 0 SB_CLK 2 AA2 DDR3 O SA_DQ 26 N8 DDR3 1 0 SB_CLK 3 AB1 DDR3 O SA_DQ 27 N7 DDR3 1 0 SB_CK 2 AB2 DDR3 O SA_DQ 28 M10 DDR3 1 0 SB_CK 3 AA1 DDR3 O SA_DQ 29 M9 DDR3 1 0 SB_CS 2 AD6 DDR3 O SA_DQ 30 N9 DDR3 1 0 SB_CS 3 AE6 DDR3 O SA_DQ 31 M7 DDR3 1 0 SB_ODT 2 AD5 DDR3 O SA_DQ 32 AG6 DDR3 1 0 SB_ODT 3 AE5 DDR3 O SA_DQ 33 AG5 DDR3 1 0 SA_BS 0 AE10 DDR3 O SA_DQ 34 AK6 DDR3 1 0 SA_BS 1 AF10 DDR3 O SA_DQ 35 AK5 DDR3 1 0 SA_BS 2 V6 DDR3 O SA_DQ 36 AH
65. 3 1 0 SA_MA 9 W5 DDR3 O SB_DQ 23 K7 DDR3 1 0 Datasheet Volume 1 113 m n tel Processor Pin Signal and Package Information Table 8 1 rPGA988B Processor Pin List Table 8 1 rPGA988B Processor Pin List by Pin Name Continued by Pin Name Continued Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir SB DQ 24 M5 DDR3 1 0 SB_DQS 7 AP15 DDR3 1 0 SB_DQ 25 N4 DDR3 1 0 SB_DQS 0 C7 DDR3 1 0 SB DQ 26 N2 DDR3 1 0 SB_DQS 1 G3 DDR3 1 0 SB_DQ 27 N1 DDR3 1 0 SB_DQS 2 J6 DDR3 1 0 SB_DQ 28 M4 DDR3 1 0 SB_DQS 3 M3 DDR3 1 0 SB_DQ 29 N5 DDR3 1 0 SB_DQS 4 AN6 DDR3 1 0 SB DQ 30 M2 DDR3 1 0 SB_DQS 5 AP8 DDR3 1 0 SB DQ 31 M1 DDR3 1 0 SB_DQS 6 AK11 DDR3 1 0 SB DQ 32 AM5 DDR3 1 0 SB_DQS 7 AP14 DDR3 1 0 SB_DQ 33 AM6 DDR3 1 0 SB MA 0 AA8 DDR3 O SB_DQ 34 AR3 DDR3 1 0 SB_MA 1 T7 DDR3 O SB_DQ 35 AP3 DDR3 1 0 SB_MA 2 R7 DDR3 O SB_DQ 36 AN3 DDR3 1 0 SB_MA 3 T6 DDR3 O SB_DQ 37 AN2 DDR3 1 0 SB_MA 4 T2 DDR3 O SB_DQ 38 AN1 DDR3 1 0 SB_MA 5 T4 DDR3 O SB_DQ 39 AP2 DDR3 1 0 SB_MA 6 T3 DDR3 O SB_DQ 40 AP5 DDR3 1 0 SB_MA 7 R2 DDR3 O SB DQ 41 AN9 DDR3 1 0 SB_MA 8 T5 DDR3 O SB_DQ 42 ATS DDR3 1 0 SB_MA 9 R3 DDR3 O SB_DQ 43 AT6 DDR3 1 0 SB_MA 10 AB7 DDR3 O SB_DQ 44 AP6 DDR3 1 0 SB_MA 11 R1 DDR3 O SB_DQ 45 AN8 DDR3 1 0 SB_MA 12 T1 DDR3 O SB_DQ 46 AR6 DDR3 1 0 SB_MA 13 AB10 DDR3 O SB DQ 47 ARS DDR3 1 0 SB_
66. 3 GND VSS AK13 GND VSS AP16 GND VSS AK16 GND VSS AP19 GND VSS AK19 GND VSS AP22 GND VSS AK22 GND VSS AP25 GND VSS AK25 GND VSS AP28 GND VSS AK27 GND VSS AP31 GND VSS AK30 GND VSS AP34 GND VSS AK33 GND VSS AP4 GND VSS AK4 GND VSS AP7 GND VSS AK7 GND VSS AR10 GND VSS AL10 GND VSS AR13 GND VSS AL13 GND VSS AR16 GND VSS AL16 GND VSS AR19 GND VSS AL19 GND VSS AR2 GND VSS AL2 GND VSS AR22 GND VSS AL22 GND VSS AR25 GND VSS AL25 GND VSS AR4 GND VSS AL28 GND VSS AR7 GND VSS AL31 GND VSS AT10 GND VSS AL34 GND VSS AT13 GND VSS AL4 GND VSS AT16 GND VSS AL7 GND VSS AT19 GND VSS AM1 GND VSS AT22 GND VSS AM10 GND VSS AT25 GND VSS AM13 GND VSS AT27 GND VSS AM16 GND VSS AT29 GND VSS AM19 GND VSS AT3 GND VSS AM2 GND VSS AT32 GND VSS AM22 GND VSS AT35 GND VSS AM25 GND VSS AT4 GND VSS AM29 GND VSS AT7 GND VSS AM3 GND VSS B11 GND VSS AM4 GND VSS B13 GND 118 Datasheet Volume 1 Processor Pin Signal and Package Information Table 8 1 rPGA988B Processor Pin List by Pin Name Continued Table 8 1 rPGA988B Processor Pin List by Pin Name Continued intel Pin Name Pin 4 Buffer Type Dir Pi
67. 48500 3 1 0 49000 3 2 0 49500 3 3 0 50000 3 4 0 50500 3 5 0 51000 3 6 0 51500 3 7 0 52000 3 8 0 52500 3 9 0 53000 3 A 0 53500 3 B 0 54000 3 C 0 54500 3 D 0 55000 3 E 0 55500 3 F 0 56000 4 0 0 56500 411 0 57000 4 2 0 57500 4 3 0 58000 4 4 0 58500 4 5 0 59000 416 0 59500 4 7 0 60000 4 8 0 60500 4 9 0 61000 4 A 0 61500 4 B 0 62000 4 C 0 62500 4 D 0 63000 4 E 0 63500 4 F 0 64000 5 O 0 64500 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 VID VID VID VID VID VID VID VID 7 93 Datasheet Volume 1 Electrical Specifications intel Sheet 3 of 3 VID VID VID VID VID VID VID VID inition IMVP7 Voltage Identification Def Table 7 1 1 29000 1 29500 1 30000 1 30500 1 31000 1 31500 1 32000 1 32500 1 33000 1 33500 1 34000 1 34500 1 35000 1 35500 1 36000 1 36500 1 37000 1 37500 1 38000 1 38500 1 39000 1 39500 1 40000 1 40500 1 41000 1 41500 1 42000 1 42500 1 43000 1 43500 1 44000 1 44500 1 45000 1 45500 1 46000 1 46500
68. 5 DDR3 1 0 SA_CAS AES DDR3 O SA_DQ 37 AH6 DDR3 1 0 SA_CLK 0 AAG DDR3 O SA_DQ 38 AJ5 DDR3 1 0 SA_CLK 1 AB5 DDR3 O SA_DQ 39 AJ6 DDR3 1 0 SA CK 0 AB6 DDR3 O SA_DQ 40 AJ8 DDR3 1 0 SA CK 1 AAS DDR3 O SA_DQ 41 AK8 DDR3 1 0 SA_CKE 0 v9 DDR3 O SA_DQ 42 AJ9 DDR3 1 0 112 Datasheet Volume 1 Processor Pin Signal and Package Information intel Table 8 1 rPGA988B Processor Pin List Table 8 1 rPGA988B Processor Pin List by Pin Name Continued by Pin Name Continued Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir SA DQ 43 AK9 DDR3 1 0 SA_MA 10 AD8 DDR3 O SA_DQ 44 AH8 DDR3 1 0 SA_MA 11 V4 DDR3 O SA_DQ 45 AH9 DDR3 1 0 SA_MA 12 wa DDR3 O SA_DQ 46 AL9 DDR3 1 0 SA_MA 13 AF8 DDR3 O SA_DQ 47 AL8 DDR3 1 0 SA_MA 14 V5 DDR3 O SA_DQ 48 AP11 DDR3 1 0 SA_MA 15 V7 DDR3 O SA_DQ 49 AN11 DDR3 1 0 SA ODT 0 AH3 DDR3 O SA_DQ 50 AL12 DDR3 1 0 SA_ODT 1 AG3 DDR3 O SA_DQ 51 AM12 DDR3 1 0 SA_RAS AD9 DDR3 O SA_DQ 52 AM11 DDR3 1 0 SA_WE AF9 DDR3 O SA_DQ 53 AL11 DDR3 1 0 SB_BS 0 AA9 DDR3 O SA DQ 54 AP12 DDR3 1 0 SB_BS 1 AA7 DDR3 O SA_DQ 55 AN12 DDR3
69. 6500 1 07000 1 07500 1 08000 1 08500 1 09000 1 09500 1 10000 1 10500 1 11000 1 11500 1 12000 1 12500 1 13000 1 13500 1 14000 1 14500 1 15000 1 15500 1 16000 1 16500 1 17000 1 17500 1 18000 1 18500 1 19000 1 19500 1 20000 1 20500 1 21000 1 21500 1 22000 1 22500 1 23000 1 23500 1 24000 1 24500 1 25000 1 25500 1 26000 1 26500 1 27000 1 27500 1 28000 1 28500 Vec_max HEX 8 9 B E F 0 1 2 3 4 5 6 7 8 9 B E F 0 1 2 3 4 5 6 7 8 9 B E F 0 1 2 3 4 5 6 7 8 9 B E F 0 9 9 9 A 9 9 C 9 D 9 9 A A A A A A A A A AJA A AJC AJD A A B B B B B B B B B B B A B B C B D B B C C C C C C C C C C CIA C CC CD C C D 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HEX Vcc Max 1 8 0 36500 1 9 0 37000 1 A 0 37500 1 B 0 38000 1 Cj 0 38500 1 D 0 39000 1 E 0 39500 1 F 0 40000 2 O 0 40500 2 1 0 41000 21210 41500 2 3 0 42000 2 4 0 42500 2 5 0 43000 2 6 0 43500 2 7 0 44000 2 8 0 44500 2 9 0 45000 2 A 0 45500 2 B 0 46000 2 C 0 46500 2 D 0 47000 2 E 0 47500 2 F 0 48000 3 O 0
70. 8 1 3 7 Thermal Management Support cceceee cece ee ee eee eee menn eene 18 1 4 Mobile 3rd Generation Intel Core Processor Family SKU Definition 18 125 Packadgew ci RG ET 18 1 6 Processor CompatibilitY cui CG pb 19 BS Se KC elle ee 20 1 8 Related DOCUMENTS siii nete de den dE ga LLDD staid aids dE sa Ende aad Pani yates atlas 22 2 Inteifac sS Nee coer vine cade eta ys eem 23 2 1 System Memory Interface inicia io 23 2 1 1 System Memory Technology Supported 0ccccccccnconcncnnnnnonononnnanencnrnrananananannos 23 2 1 2 System Memory Timing Support 24 2 1 3 System Memory Organization Modes YY YL LARA EE R AEL Y RY enne 25 2 1 3 1 Single Channel Mode cerent nete KEEN KEENENN RENE DARO KEEN 25 2 1 3 2 Dual Channel Mode Intel Flex Memory Technology Mode 25 2 1 4 Rules for Populating Memory Glots enne meme 26 2 1 5 Technology Enhancements of Intel Fast Memory Access Intel FMA 27 2 1 5 1 Just in Time Command Scheduling ssssssssssssrsssrsssrrsnrssrrrrrrerresrns 27 2 1 5 2 Command Overlap EE 27 2 1 5 3 Out of Order Scheduling x 9Y Yk lt AE ARA RENE NENNEN ENEE nnne 27 2 16 Data Scramblilig iere Goa YR ne O ORG AG MA par ena e GR S ae PRU YD 27 2 1 7 DRAM Clock Generation NR SKN RENE ERER ENER AEN NR E a he nana RR ARR RR IRA RR EN AR NENNEN 27 2 1 8 DDR3 Reference Voltage Generation 28 2 2 PCL Express InterfdC a
71. 88 8 8 88 99 8 8 9 89 8 8 0800000 95 2 998 008 0 990 oon e oae oae co Po o og 99 7000000000 0 0000000000000 090000000 6G 900 0000000056 20000 0000000 Soo 900 00000000 00000 990 000000009 9996900000000 994 999 900000000 00000000 000 4 990 2000000995 99909 200 0000000 E Hc MW SEH 990 999988900 L 2000000000000 900 oog 0000000 0 0 0 0 0 ojo o o b o o 0000090000000 900 03 9299999999800 00000 000000000 900 150 000000000000000 0 0 o 0900 a dog990000000000D00000000000 00000 9 000 Ze one 98 80 099 30000 95 3883 999999909 90000099890 90908 2983932 029 909 990 ooob 899929 9 GS 890909 9899 o990b00 90 0 Foo So ooog 32 9 999098 9089 99008 o 8 9090000000000000090a0000I o 9 290 099 059 059 9p0 O50 5 924 090 0 0 o90 0 0 0 2 i i E 131113 TH EON AJLA dOl dano si aw co 163 Datasheet Volume 1 Processor Pin Signal and Package Information intel Figure 8 14 Processor BGA1224 4C GT2 G26204 Mechanical Package
72. 9 AV56 DDR3 1 0 SA_DQ 13 AP8 DDR3 Wie SA_DQ 50 AP50 DDR3 1 0 SA_DQ 14 AT13 DDR3 I O SA_DQ 51 AP53 DDR3 1 0 SA_DQ 15 AU13 DDR3 1 0 SA_DQ 52 AV54 DDR3 1 0 SA_DQ 16 BC7 DDR3 1 0 SA_DQ 53 AT54 DDR3 1 0 SA_DQ 17 BB7 DDR3 1 0 SA_DQ 54 AP56 DDR3 1 0 SA_DQ 18 BA13 DDR3 1 0 SA_DQ 55 AP52 DDR3 I O SA_DQ 19 BB11 DDR3 1 0 SA_DQ 56 AN57 DDR3 1 0 SA_DQ 20 BA7 DDR3 Wie SA_DQ 57 AN53 DDR3 I O SA_DQ 21 BA9 DDR3 1 0 SA_DQ 58 AG56 DDR3 Wie SA_DQ 22 BBO DDR3 1 0 SA_DQ 59 AG53 DDR3 1 0 SA_DQ 23 AY13 DDR3 1 0 SA_DQ 60 AN55 DDR3 1 0 SA_DQ 24 AV14 DDR3 1 0 SA_DQ 61 AN52 DDR3 Wie SA_DQ 25 AR14 DDR3 Wie SA_DQ 62 AG55 DDR3 Wie Datasheet Volume 1 145 m n tel Processor Pin Signal and Package Information Table 8 3 BGA1023 Processor Ball List Table 8 3 BGA1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir SA DQ 63 AK56 DDR3 1 0 SB BS 0 BG39 DDR3 O SA_DQS 0 AL11 DDR3 1 0 SB_BS 1 BD42 DDR3 O SA_DQS 1 AR8 DDR3 1 0 SB_BS 2 AT22 DDR3 O SA_DQS 2 AV11 DDR3 1 0 SB_CAS AV43 DDR3 O SA_DQS 3 AT17 DDR3 1 0 SB CKE 0 AR22 DDR3 O SA_DQS 4 AV45 DDR3 1 0 SB_CKE 1 BF27 DDR3 O SA_DQS 5 AY51 DDR3 1 0 SB_CLK 0 AY34 DDR3 O SA_DQS 6 AT55 DDR3 1 0 SB_CLK 1 BB36 DDR3 O SA_DQS 7 AK55 DDR3 1 0 SB_CK 0 BA34 DDR3 O SA_DQS 0 AJ11 DDR3
73. AL17 GND VSS AF17 GND VSS AL13 GND VSS AF1 GND VSS AL10 GND VSS AE13 GND VSS AK52 GND VSS AE8 GND VSS AK1 GND VSS AD61 GND VSS AJ48 GND VSS AD20 GND VSS AJ45 GND VSS AD17 GND VSS AJ42 GND VSS AD4 GND VSS AJ38 GND VSS AC46 GND VSS AJ34 GND VSS AC14 GND VSS AJ30 GND VSS AC10 GND VSS AJ26 GND VSS AC6 GND VSS AJ22 GND VSS AB61 GND VSS AJ20 GND VSS AB48 GND VSS AJ16 GND VSS AB21 GND VSS AJ13 GND VSS AB18 GND VSS AJ7 GND VSS AB16 GND VSS AH58 GND VSS AA56 GND VSS AH4 GND VSS AA55 GND VSS AG61 GND VSS AA53 GND VSS AG52 GND VSS AA52 GND VSS AG47 GND VSS AA51 GND VSS AG18 GND VSS AA50 GND VSS AG14 GND VSS AA13 GND VSS AG10 GND VSS AA8 GND VSS AG7 GND VSS AA1 GND VSS AF59 GND VSS Y59 GND VSS AF58 GND VSS Y58 GND VSS AF56 GND VSS Y47 GND VSS AF55 GND VSS Y4 GND VSS AF53 GND VSS W46 GND VSS AF52 GND VSS W21 GND VSS AF51 GND VSS W18 GND VSS AF50 GND VSS W15 GND Datasheet Volume 1 153 m n tel Processor Pin Signal and Package Information Table 8 3 BGA1023 Processor Ball List Table 8 3 BGA1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VSS W13 GND VSS N21 GND VSS ws GND VSS N17 GND VSS V61 GND VSS N1 GND VSS V20 GND VSS M58 GND VSS U13 GND VSS M15 GND VSS U8 GND VSS M11 GND VSS T56 GND VSS M6 GND VSS T55 GND VSS M4 GND VSS T53 GND VSS L61 GND
74. AXG AH58 PWR SB MA 0 BF31 DDR3 O VAXG AH56 PWR SB_MA 1 BH31 DDR3 O VAXG AG64 PWR SB_MA 2 BB37 DDR3 O VAXG AG62 PWR SB_MA 3 BC34 DDR3 O VAXG AG60 PWR SB_MA 4 BF27 DDR3 O VAXG AF58 PWR SB_MA 5 BB33 DDR3 O VAXG AF56 PWR Datasheet Volume 1 129 m n tel Processor Pin Signal and Package Information Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VAXG AE64 PWR VAXG N64 PWR VAXG AE62 PWR VAXG N62 PWR VAXG AE60 PWR VAXG N60 PWR VAXG AD65 PWR VAXG N58 PWR VAXG AD63 PWR VAXG N56 PWR VAXG AD61 PWR VAXG N52 PWR VAXG AD58 PWR VAXG N49 PWR VAXG AD56 PWR VAXG M65 PWR VAXG AB65 PWR VAXG M63 PWR VAXG AB63 PWR VAXG M61 PWR VAXG AB61 PWR VAXG M59 PWR VAXG AB58 PWR VAXG M55 PWR VAXG AB56 PWR VAXG M53 PWR VAXG AA64 PWR VAXG M48 PWR VAXG AA62 PWR VAXG L56 PWR VAXG AA60 PWR VAXG L52 PWR VAXG Y58 PWR VAXG L48 PWR VAXG Y56 PWR VAXG_SENSE F49 Analog VAXG W64 PWR VAXG_VAL_SENSE B49 Analog VAXG W62 PWR VCC R46 PWR VAXG wen PWR VCC R42 PWR VAXG V65 PWR VCC R40 PWR VAXG v63 PWR VCC R36 PWR VAXG v61 PWR VCC R34 PWR VAXG V58 PWR VCC R29 PWR VAXG V56 PWR VCC R27 PWR VAXG T65 PWR VCC R23 PWR VAXG T63 PWR VCC R21 PWR VAXG T61 PWR VCC N45 PWR VAXG T58 PWR VCC N43 PWR VAXG T56 PWR VCC N39 PWR VAXG R64 PWR VCC N37
75. Access DMI Direct Media Interface DP DisplayPort DTS Digital Thermal Sensor ECC Error Correction Code eDP Embedded DisplayPort Enhanced Intel Technology that provides power management capabilities to laptops SpeedStep Technology The Execute Disable bit allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the Execute Disable Bit operating system This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system See the Intel 64 and IA 32 Architectures Software Developer s Manuals for more detailed information EU Execution Unit IMC Integrated Memory Controller Intel 64 Technology 64 bit memory extensions to the IA 32 architecture Intel DPST Intel Display Power Saving Technology Intel FDI Intel Flexible Display Interface Intel TXT Intel Trusted Execution Technology Intel Virtualization Processor SE a ug a in comuna on WS Virtual Machine Technology Monitor software enables multiple robust independent software environments inside a single platform Intel virtualization Technology Intel VT for Directed I O Intel VT d is a hardware assist under system software Virtual Machine Manager or operating Intel VT d system control for enabling I O device virtualization Intel VT d al
76. C AF35 PWR VAXG AT18 PWR VCC AG26 PWR VAXG AT20 PWR VCC AG27 PWR Datasheet Volume 1 intel Processor Pin Signal and Package Information Table 8 1 rPGA988B Processor Pin List Table 8 1 rPGA988B Processor Pin List by Pin Name Continued by Pin Name Continued Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VCC AG28 PWR VCC V35 PWR VCC AG29 PWR VCC Y26 PWR VCC AG30 PWR VCC Y27 PWR VCC AG31 PWR VCC Y28 PWR VCC AG32 PWR VCC Y29 PWR VCC AG33 PWR VCC Y30 PWR VCC AG34 PWR VCC Y31 PWR VCC AG35 PWR VCC Y32 PWR VCC P26 PWR VCC Y33 PWR VCC P27 PWR VCC Y34 PWR VCC P28 PWR VCC Y35 PWR VCC P29 PWR VCC_DIE_SENSE AH27 Analog O VCC P30 PWR VCC_SENSE AJ35 Analog O VCC P31 PWR VCC_VAL_SENSE AJ33 Analog O VCC P32 PWR VCCIO 323 PWR VCC P33 PWR VCCIO A11 PWR VCC P34 PWR VCCIO A12 PWR VCC P35 PWR VCCIO AC10 PWR VCC R26 PWR VCCIO AG10 PWR VCC R27 PWR VCCIO AH10 PWR VCC R28 PWR VCCIO AH13 PWR VCC R29 PWR VCCIO B12 PWR VCC R30 PWR VCCIO C11 PWR VCC R31 PWR VCCIO C12 PWR VCC R32 PWR VCCIO D11 PWR VCC R33 PWR VCCIO D12 PWR VCC R34 PWR VCCIO E11 PWR VCC R35 PWR VCCIO E12 PWR VCC U26 PWR VCCIO F11 PWR VCC U27 PWR VCCIO F12 PWR VCC U28 PWR VCCIO G12 PWR VCC U29 PWR VCCIO H11 PWR VCC U30 PWR VCCIO H12 PWR VCC U31 PWR VCCIO Ji1 PWR VCC U32 PWR VCCIO 312 PWR VCC U33 PWR VCCIO L10 PWR VCC U34 PWR VCCIO P10 PWR VCC U35 PW
77. CIe I eDP TX 3 AE6 eDP O PEG_RX 11 A8 PCIe I FDI INT U11 Asynch CMOS I PEG RX 12 B6 PCIe I FDIO FSYNC AA11 CMOS I PEG RX 13 H8 PCIe I FDIO LSYNC AA10 CMOS I PEG RX 14 E5 PCIe I FDIO TX4 0 U7 FDI O PEG_RX 15 K7 PCIe I FDIO_TX 1 wil FDI O PEG_RX 0 K22 PCIe I FDIO_TX 2 wi FDI O PEG_RX 1 K19 PCIe I FDIO_TX 3 AA6 FDI O PEG_RX 2 C21 PCIe I FDIO TX 0 U6 FDI O PEG_RX 3 D19 PCIe I FDIO TX 1 W10 FDI O PEG_RX 4 C19 PCIe I FDIO TX 2 w3 FDI O PEG_RX 5 D16 PCIe I FDIO TX 3 AA7 FDI O PEG_RX 6 C13 PCIe I FDI1_FSYNC AC12 CMOS I PEG_RX 7 D12 PCIe I FDI1_LSYNC AG8 CMOS I PEG_RX 8 C11 PCIe I FDI1_TX 0 W6 FDI O PEG_RX 9 C9 PCIe I FDI1_TX 1 va FDI O PEG_RX 10 F8 PCIe I FDI1_TX 2 Y2 FDI O PEG_RX 11 C8 PCIe I FDI1_TX 3 AC9 FDI O PEG_RX 12 C5 PCIe I FDI1_TX 0 W7 FDI O PEG_RX 13 H6 PCIe I FDI1_TX 1 T4 FDI O PEG_RX 14 F6 PCIe I FDI1_TX 2 AA3 FDI O PEG_RX 15 K6 PCIe I FDI1_TX 3 AC8 FDI O PEG_TX 0 G22 PCIe O PECI A48 Asynch 1 0 PEG_TX 1 C23 PCIe O PEG_ICOMPI G3 Analog I PEG_TX 2 D23 PCIe O PEG_ICOMPO G1 Analog I PEG_TX 3 F21 PCIe O PEG_RCOMPO G4 Analog I PEG_TX 4 H19 PCIe O PEG_RX 0 H22 PCIe I PEG_TX 5 C17 PCIe O Datasheet Volume 1 143 intel Processor Pin Signal and Package Information Table 8 3 BGA1023 Processor Ball List Table 8 3 BGA1023 Processor Ball List by Ball Name Continued by Bal
78. CLMULQDQ Instruction The processor supports the carry less multiplication instruction PCLMULQDQ PCLMULODO is a Single Instruction Multiple Data SIMD instruction that computes the 128 bit carry less multiplication of two 64 bit operands without generating and propagating carries Carry less multiplication is an essential processing component of several cryptographic systems and standards Hence accelerating carry less multiplication can significantly contribute to achieving high speed secure computing and communication Datasheet Volume 1 Technologies 3 6 3 3 7 intel RDRAND Instruction The processor introduces a software visible random number generation mechanism supported by a high quality entropy source This capability will be made available to programmers through the new RDRAND instruction The resultant random number generation capability is designed to comply with existing industry standards in this regard ANSI X9 82 and NIST SP 800 90 Some possible usages of the new RDRAND instruction include cryptographic key generation as used in a variety of applications including communication digital signatures secure storage and so on Intel 64 Architecture x2APIC The x2APIC architecture extends the xAPIC architecture which provides key mechanism for interrupt delivery This extension is intended primarily to increase processor addressability Specifically x2APIC e Retains all key elements of compatibility to th
79. CMOS vss BG24 GND VDDQ BG33 PWR vss BG21 GND VDDQ BB28 PWR vss BG17 GND VDDQ BA40 PWR vss BG13 GND VDDQ AW26 PWR vss BG9 GND VDDQ AV41 PWR vss BE5 GND VDDQ AR40 PWR vss BD56 GND VDDQ AR36 PWR vss BD52 GND VDDQ AR34 PWR vss BD48 GND VDDQ AR32 PWR vss BD44 GND VDDQ AR30 PWR vss BD40 GND VDDQ AR28 PWR vss BD36 GND VDDQ AR26 PWR vss BD32 GND VDDQ AN38 PWR vss BD27 GND VDDQ AN34 PWR vss BD23 GND VDDQ AN30 PWR vss BD19 GND VDDQ AM40 PWR vss BD16 GND VDDQ AM36 PWR vss BD12 GND VDDQ AM33 PWR vss BD8 GND VDDQ AL42 PWR vss BC57 GND VDDQ AL38 PWR vss BC13 GND VDDQ AL34 PWR VSS BC5 GND VDDQ AL30 PWR VSS BB53 GND VDDQ AJ40 PWR vss BA51 GND VDDQ AJ36 PWR vss BA48 GND VDDQ AJ33 PWR vss BA32 GND VDDQ AJ28 PWR vss BA26 GND VDDQ_SENSE BC43 Analog O vss BA21 GND VIDALERT A44 CMOS I vss BA17 GND VIDSCLK B43 CMOS O vss BA11 GND VIDSOUT C44 CMOS 1 0 vss BA1 GND VSS BG53 GND vss AY58 GND Datasheet Volume 1 151 m n tel Processor Pin Signal and Package Information Table 8 3 BGA1023 Processor Ball List Table 8 3 BGA1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VSS AY55 GND VSS AR21 GND VSS AY49 GND VSS AR17 GND VSS AY45 GND VSS AR13 GND VSS AY41 GND VSS AR7 GND VSS AY36 GND VSS AP55 GND VSS AY30 GND VSS AP51 GND VSS AY
80. Compiled application provided GS programs specifying an algorithm to convert the vertices of an input object into some output primitives For example a GS shader may convert lines of a line strip into polygons representing a corresponding segment of a blade of grass centered on the line Or it could use adjacency information to detect silhouette edges of triangles and output polygons extruding out from the edges Clip Stage The Clip stage performs general processing on incoming 3D objects However it also includes specialized logic to perform a Clip Test function on incoming objects The Clip Test optimizes generalized 3D Clipping The Clip unit examines the position of incoming vertices and accepts rejects 3D objects based on its Clip algorithm Strips and Fans SF Stage The SF stage performs setup operations required to rasterize 3D objects The outputs from the SF stage to the Windower stage contain implementation specific information required for the rasterization of objects and also supports clipping of primitives to some extent Windower IZ WIZ Stage The WIZ unit performs an early depth test which removes failing pixels and eliminates unnecessary processing overhead The Windower uses the parameters provided by the SF unit in the object specific rasterization algorithms The WIZ unit rasterizes objects into the corresponding set of pixels The Windower is also capable of performing dithering whereby the illusion of a higher r
81. DDR3 O SB_DQ 49 AU58 DDR3 Wie SB MA 6 BG30 DDR3 O SB_DQ 50 AN61 DDR3 1 0 SB_MA 7 BD29 DDR3 O SB_DQ 51 AN59 DDR3 1 0 SB_MA 8 BE30 DDR3 O SB_DQ 52 AU59 DDR3 o SB_MA 9 BE28 DDR3 O SB_DQ 53 AU61 DDR3 Wie SB_MA 10 BD43 DDR3 O SB_DQ 54 AN58 DDR3 1 0 SB_MA 11 AT28 DDR3 O SB_DQ 55 AR58 DDR3 1 0 SB_MA 12 AV28 DDR3 O SB_DQ 56 AK58 DDR3 Wie SB_MA 13 BD46 DDR3 O SB_DQ 57 AL58 DDR3 Wie SB_MA 14 AT26 DDR3 O SB_DQ 58 AG58 DDR3 o SB_MA 15 AU22 DDR3 O SB_DQ 59 AG59 DDR3 1 0 SB ODT 0 AT43 DDR3 O SB_DQ 60 AM60 DDR3 1 0 SB_ODT 1 BG47 DDR3 O SB_DQ 61 AL59 DDR3 Wie SB_RAS BF40 DDR3 O Datasheet Volume 1 147 m n tel Processor Pin Signal and Package Information Table 8 3 BGA1023 Processor Ball List Table 8 3 BGA1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir SB_WE BD45 DDR3 O l vac vag PwR SM_DRAMPWROK BE45 Asynch CMOS I VAXG W61 PWR SM DRAMRST AT30 DDR3 O VAXG W56 PWR SM_RCOMP 0 BF44 Analog 1 0 VAXG W55 PWR SM_RCOMP 1 BE43 Analog 1 0 VAXG W53 PWR SM_RCOMP 2 BG43 Analog 1 0 VAXG W52 PWR SM_VREF AY43 Analog I VAXG W51 PWR TCK L56 CMOS I VAXG W50 PWR TDI M60 CMOS I VAXG V59 PWR TDO L59 CMOS O VAXG V58 PWR THERMTRIP D45 Asynch CMOS O VAXG V56 PWR TMS L55 CMOS I VAXG V55 PWR TRST J58 CMOS I VAXG v53 PWR UNCOREPWRGOOD B46 Asynch
82. DDR3 O SB_DQ 25 BG14 DDR3 1 0 SB_BS 1 BD37 DDR3 O SB_DQ 26 BF17 DDR3 1 0 SB_BS 2 AY29 DDR3 O SB_DQ 27 BJ18 DDR3 1 0 SB_CAS BH39 DDR3 O SB_DQ 28 BF13 DDR3 1 0 SB CKE 0 BD25 DDR3 O SB_DQ 29 BH13 DDR3 o SB_CKE 1 BJ26 DDR3 O SB_DQ 30 BH17 DDR3 1 0 SB_CLK 0 BH33 DDR3 O SB_DQ 31 BG18 DDR3 I O SB_CLK 1 BH37 DDR3 O SB_DQ 32 BH49 DDR3 1 0 SB CK 0 BF33 DDR3 O SB_DQ 33 BF47 DDR3 1 0 SB_CK 1 BF37 DDR3 O SB_DQ 34 BH53 DDR3 1 0 SB_CS 0 BE40 DDR3 O SB_DQ 35 BG50 DDR3 Wie SB_CS 1 BH41 DDR3 O SB_DQ 36 BF49 DDR3 1 0 SB_DQ O AL4 DDR3 1 0 SB_DQ 37 BH47 DDR3 I O SB_DQ 1 AK3 DDR3 1 0 SB_DQ 38 BF53 DDR3 Wie SB_DQ 2 AP3 DDR3 1 0 SB_DQ 39 BJ50 DDR3 o SB DQ 3 AR2 DDR3 Wie SB_DQ 40 BF55 DDR3 Wie SB_DQ 4 AL2 DDR3 1 0 SB_DQ 41 BH55 DDR3 1 0 SB_DQ 5 AK1 DDR3 1 0 SB_DQ 42 BJ58 DDR3 1 0 SB DQ 6 AP1 DDR3 o SB DQ 43 BH59 DDR3 1 0 SB DQ 7 ARA DDR3 Wie SB DQ 44 BJ54 DDR3 Wie SB_DQ 8 AV3 DDR3 o SB_DQ 45 BG54 DDR3 1 0 SB_DQ 9 AU4 DDR3 1 0 SB_DQ 46 BG58 DDR3 1 0 SB_DQ 10 BA4 DDR3 o SB_DQ 47 BF59 DDR3 I O SB_DQ 11 BB1 DDR3 1 0 SB_DQ 48 BA64 DDR3 o 128 Datasheet Volume 1 Processor Pin Signal and Package Information intel Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name
83. E12 DQ26 SA DQ 32 AG6 BA45 BB49 DQ36 SA DQ 33 AG5 AR43 AY49 DQ39 SA DQ 34 AK6 AW48 BE52 DQ32 SA DQ 35 AK5 BC48 BD51 DQ33 SA DQ 36 AH5 BC45 BD49 DQ38 SA DQ 37 AH6 AR45 BE48 DQ35 SA DQ 38 AIS AT48 BA52 DQ37 166 Datasheet Volume 1 DDR Data Swizzling intel Table 9 2 DDR Data Swizzling Table for Package Channel B Pin Name Made AC ML SE rPGA BGA1023 BGA1224 SB DQ 0 C9 AL4 AL4 DO04 SB DQ 1 A7 AL1 AK3 DO05 SB DQ 2 D10 AN3 AP3 DQO2 SB_DQ 3 C8 ARA AR2 DQ03 SB DQ 4 A9 AK4 AL2 DQO7 SB DQ 5 A8 AK3 AK1 DQ06 SB DQ 6 D9 ANA AP1 DO00 SB DQ 7 D8 AR1 AR4 DO01 SB_DQ 8 G4 AU4 AV3 DQ12 SB_DQ 9 F4 AT2 AU4 DQ13 SB DQ 10 F1 AV4 BA4 DQ11 SB DQ 11 G1 BA4 BB1 DO08 SB_DO 12 G5 AU3 AV1 DO15 SB DQ 13 F5 AR3 AU2 DQ14 SB DQ 14 F2 AY2 BA2 DQ10 SB DQ 15 G2 BA3 BB3 DQO9 SB DQ 16 37 BE9 BC2 DQ20 SB DQ 17 J8 BD9 BF7 DQ21 SB DQ 18 K10 BD13 BF11 DQ19 SB DQ 19 K9 BF12 BJ10 DQ16 SB DQ 20 J9 BF8 BC4 DQ22 SB DQ 21 J10 BD10 BH7 DQ23 SB DQ 22 K8 BD14 BH11 DQ18 SB DQ 23 K7 BE13 BG10 DQ17 SB DQ 24 M5 BF16 BJ14 DQ30 SB DQ 25 N4 BE17 BG14 DQ24 SB DQ 26 N2 BE18 BF17 DQ26 SB DQ 27 N1 BE21 BJ18 DQ27 SB DQ 28 M4 BE14 BF13 DQ31 SB DQ 29 N5 BG14 BH13 DQ25 SB DQ 30 M2 BG18 BH17
84. EG RX 15 0 PCI Express Receive Differential Pair I PEG RX 15 0 PCI Express PEG TX 15 0 PCI Express Transmit Differential Pair o PEG_TX 15 0 PCI Express 6 5 Embedded DisplayPort eDP Table 6 7 Embedded Display Port Signals Signal Name Description A eDP_TX 3 0 Embedded DisplayPort Transmit Differential Pair O eDP_TX 3 0 Diff eDP_AUX Embedded DisplayPort Auxiliary Differential Pair I O eDP_AUX Diff Embedded DisplayPort Hot Plug Detect I eDP_HPD Asynchronous CMOS eDP_COMPIO Embedded DisplayPort Current Compensation S eDP_ICOMPO Embedded DisplayPort Current Compensation M DPLL REF CLK Embedded DisplayPort Reference Clock Differential Pair I DPLL REF CLK Diff 6 6 Intel Flexible Display Interface Signals Table 6 8 Intel Flexible Display Interface Sheet 1 of 2 e GE Direction Signal Name Description Buffer Type FDIO_TX 3 0 Intel Flexible Display Interface Transmit Differential O FDIO_TX 3 0 Pair Pipe A FDI D s FDIO_FSYNC O Intel Flexible Display Interface Frame Sync Pipe A I CMOS D e FDIO LSYNC O Intel Flexible Display Interface Line Sync Pipe A I CMOS FDI1 TX 3 0 Intel Flexible Display Interface Transmit Differential O FD11_TX 3 0 Pair Pipe B and C FDI Datasheet Volume 1 85 intel Table 6 8 6 7 Table 6 9 6 8 Table 6 10 6 9 Table 6 11 86 Signal Description I
85. ENSE and VSSD_SENSE provides an isolated low o VSSD SENSE impedance connection to the Vppo voltage and ground They A can be used to sense or measure voltage near the silicon nalog DE NEED DIEI UTE TTE VSS SENSE VDDQ p DDQ g g Ter Analog can be used to sense or measure voltage near the silicon Datasheet Volume 1 89 intel Table 6 15 Sense Signals Sheet 2 of 2 6 14 Signal Description Table 6 16 Ground and NCTF 6 15 Kass Direction Signal Name Description Buffer Type VCCSA_SENSE provide an isolated low impedance connection o VCCSA_SENSE to the processor system agent voltage It can be used to sense Anal or measure voltage near the silicon nalog VCC_DIE SENSE Die Validation Sense o Analog VCC_VAL_SENSE VCC Validation Sense O VSS_VAL_SENSE Analog VAXG_VAL_SENSE VAXG Validation Sense o VSSAXG VAL SENSE Analog Ground and NCTF i m Direction Signal Name Description Buffer Type VSS Processor ground node GND VSS_NCTF BGA Only Non Critical to Function These signals are for package mechanical reliability DC TEST xx Daisy Chain These signals are for solder joint reliability and BGA Only non critical to function Processor Internal Pull Up Pull Down Table 6 17 Processor Internal Pull Up Pull Down Signal Name Pull Up Pull Down Rail Value BPM 7 0 Pull Up VCCIO 65 165 Q PRDY Pull Up VCCIO
86. GND VDDQ AL46 PWR VSS BE50 GND VDDQ AL42 PWR VSS BE46 GND VDDQ AL40 PWR VSS BE42 GND VDDQ AL36 PWR VSS BE38 GND 134 Datasheet Volume 1 Processor Pin Signal and Package Information Table 8 2 BGA1224 Processor Ball List by Ball Name Continued intel Table 8 2 BGA1224 Processor Ball List by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball 4 Buffer Type Dir VSS BE34 GND VSS BA30 GND VSS BE30 GND VSS BA26 GND VSS BE26 GND VSS BA22 GND VSS BE22 GND VSS BA18 GND VSS BE18 GND VSS BA14 GND VSS BE14 GND VSS AY61 GND VSS BE10 GND VSS AY11 GND VSS BD35 GND VSS AY7 GND VSS BD7 GND VSS AY3 GND VSS BD3 GND VSS AY1 GND VSS BC60 GND VSS AW56 GND VSS BC56 GND VSS AW52 GND VSS BC52 GND VSS AW48 GND VSS BC48 GND VSS AW44 GND VSS BC44 GND VSS AW40 GND VSS BC40 GND VSS AW36 GND VSS BC36 GND VSS AW32 GND VSS BC32 GND VSS AW28 GND VSS BC28 GND VSS AW24 GND VSS BC26 GND VSS AW16 GND VSS BC24 GND VSS AV65 GND VSS BC20 GND VSS AV63 GND VSS BC16 GND VSS AV59 GND VSS BC12 GND VSS AV57 GND VSS BB65 GND VSS AV50 GND VSS BB63 GND VSS AV44 GND VSS BB47 GND VSS AV38 GND VSS BB39 GND VSS AV31 GND VSS BB9 GND VSS AV25 GND VSS BB5 GND VSS AV19 GND VSS BA58 GND VSS AV9 GND VSS BA54 GND VSS AV5 GND VSS BA50 GND VSS AU54 GND VSS BA46 GND VSS AU47 GND V
87. HO13H 58 2 dl 111453011 3 801 RL DENTEN 83434 NOLIO7810 135340 804 og Zei Ve no 1 070 n EA I dlvelssns 130 Ze T CLINT ANSIA 0 U 39 131114 TI 4430 t so OFIE 8 31 OL Ny BEEM 185138 f 1188011 ele ig z I t j dic IN los 4 3 4 i 3 0000950 0 0 0 0 050000090 950 999 0 0 950 i 90909 308 909 9099959999 9p39 99 909 Sok 909 9 0990090000909 90 9 0 0 09000000000000 d 8 g o ooooodobo9 0090 O 1 pad 29 0 900 o ooo i doo 999808 8929990999099 099990999 9 i 00996090 0002999999009 96050 96000 MI j e o 08808 9980000000000 0 00 9 0 009 2 d 000000 o 9 COCO 900000 D 3 2 7 HE E Es H H ree 1989090 o o o0ooo00009009000000 c00000 9 9 1 Se 1 EE aleet eod00d0000 000000000p00000000 Soo Se 909 00000000 90000 0000000 Sao 900000000009 00000 800 880808500 1 de00990000000 999 2 250 000000509 0000020200007 980 T 4 d ERS eae 22090 0000000 SO 4 Zog Se 0 00 p rt bf Sooo 999 0909 QOO 990 999999995 9990900000000 990 oo 00000000 8 ol 0000000 0 0 0 0 o oo o o boo 200 96 298 2000009000000 9 9000000000000 ez 800
88. I DMI_TX 1 M8 DMI O CFG 14 L51 CMOS I DMI_TX 2 N4 DMI O CFG 15 F51 CMOS I DMI_TX 3 R2 DMI O CFG 16 D52 CMOS I DMI_TX 0 K3 DMI O CFG 17 L53 CMOS I DMI TX 1 M7 DMI O DBR K58 Asynch CMOS O DMI_TX 2 P4 DMI O DC_TEST_A4 A4 N A DMI TX 3 T3 DMI O DC_TEST_A58 A58 N A DPLL_REF_CLK AG3 Diff Clk I DC_TEST_A59 A59 N A DPLL_REF_CLK AG1 Diff Clk I DC_TEST_A61 A61 N A eDP AUX AF4 eDP 1 0 DC_TeEST_BDi Boi N A eppaux ac4 ep yo 142 Datasheet Volume 1 Processor Pin Signal and Package Information intel Table 8 3 BGA1023 Processor Ball List Table 8 3 BGA1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball 4 Buffer Type Dir eDP_COMPIO AF3 Analog I PEG_RX 1 J21 PCIe I eDP_HPD AG11 Asynch CMOS I PEG_RX 2 B22 PCIe I eDP ICOMPO AD2 Analog I PEG RX4 3 D21 PCIe I eDP_TX 0 AC3 eDP O PEG_RX 4 A19 PCIe I eDP_TX 1 AC4 eDP O PEG_RX 5 D17 PCIe I eDP_TX 2 AE11 eDP O PEG_RX 6 B14 PCIe I eDP_TX 3 AE7 eDP O PEG_RX 7 D13 PCIe I eDP TX 0 AC1 eDP O PEG_RX 8 A11 PCIe I eDP TX 1 AA4 eDP O PEG_RX 9 B10 PCIe I eDP_TX 2 AE10 eDP O PEG_RX 10 G8 P
89. J9 BB51 AW54 DQ43 SA DQ 4 D6 AJ10 AK7 DO04 SA DQ 43 AK9 AY53 AY55 DO41 SA DQ 5 C6 AJ8 AL10 DO07 SA DQ 44 AH8 BB49 BD53 DQ46 SA DQ 6 C2 AL8 AN10 DQ02 SA DQ 45 AH9 AU49 BB53 DQ47 SA DQU c3 AL7 AM9 D003 SA DQ 46 AL9 BA53 BE56 DQ40 SA DQ 8 F10 AR11 AR10 DO15 SA_DO 47 AL8 BB55 BA56 DO42 SA DQ 9 F8 AP6 AR8 DQ13 SA_DQ 48 AP11 BA55 BD57 DQ52 SA DQ 10 G10 AUG AV7 DQ08 SA DQ 49 AN11 AV56 BF61 DQ53 SA DQ 11 G9 AV9 AY5 DO09 SA_DO 50 AL12 AP50 BA60 DQ50 SA DO 12 F9 AR6 ATS DO14 SA DQ 51 AM12 AP53 BB61 DO51 SA DQ 13 F7 AP8 AR6 DO12 SA DQ 52 AM11 AV54 BE60 DO54 SA_DQ 14 G8 AT13 AW6 DQ10 SA DQ 53 AL11 AT54 BD63 DQ55 SA DO 15 G7 AU13 AT9 DO11 SA DQ 54 AP12 AP56 BB59 DO48 SA_DQ 16 K4 BC7 BA6 DQ21 SA DQ 55 AN12 AP52 BC58 DQ49 SA DQ 17 K5 BB7 BAS DQ19 SA DQ 56 AJi4 AN57 AW58 DQ61 SA DQ 18 K1 BA13 BG6 DQ16 SA DQ 57 AH14 AN53 AY59 DQ63 SA DQ 19 J1 BB11 AYO DQ18 SA DQ 58 AL15 AG56 AL60 DQ59 SA DQ 20 J5 BA7 AWS D023 SA DQ 59 AK15 AG53 AP61 DQ58 SA DQ 21 JA BA9 BB7 DQ22 SA DQ 60 AL14 AN55 AW60 DQ62 SA DQ 22 32 BBO BC8 DQ20 SA DQ 61 AK14 AN52 AY57 DQ60 SA DQ 23 K2 AY13 BE4 DQ17 SA DQ 62 AJ15 AG55 AN60 DQ57 SA Dg 24 M8 avia AW12 DQ28 SA DQ 63 AH15 AK56 AR60 DQ56 SA DQ 25 N10 AR14 AV11 DQ30 SA DQ 26 N8 AY17 BB11 DQ24 SA DQ 27 N7 AR19 BA12 DQ25 SA DQ 28 M10 BA14 BE8 DQ31 SA DQ 29 M9 AU14 BA10 DQ29 SA DQ 30 N9 BB14 BD11 DQ27 SA DQ 31 M7 BB17 B
90. K ITP probe to enable debug capacities DBR is used only in systems where no debug port is implemented on the system board DBR is used by a debug DBR 0 port interposer so that an in target probe can drive system reset PRDY is a processor output used by debug tools to determine O PRDY processor debug readiness Asynchronous CMOS Datasheet Volume 1 Signal Description Table 6 11 TAP Signals Sheet 2 of 2 intel Signal Name Description Direction Buffer Type PREQ PREQ is used by debug tools to request debug operation of the processor I Asynchronous CMOS TCK TCK Test Clock This signal provides the clock input for the processor Test Bus also known as the Test Access Port TCK must be driven low or allowed to float during power on Reset CMOS TDI TDI Test Data In This signal transfers serial test data into the processor TDI provides the serial input needed for JTAG specification support CMOS TDO TDO Test Data Out This signal transfers serial test data out of the processor TDO provides the serial output needed for JTAG specification support O Open Drain TMS TMS Test Mode Select A JTAG specification support signal used by debug tools I CMOS TRST TRST Test Reset This signal resets the Test Access Port TAP logic TRST must be driven low during power on Reset I CMOS 6 10 Error and Therma
91. MA 14 R5 DDR3 O SB_DQ 48 ARO DDR3 1 0 SB_MA 15 R4 DDR3 O SB_DQ 49 AJ11 DDR3 1 0 SB_ODT 0 AE4 DDR3 O SB_DQ 50 AT8 DDR3 1 0 SB_ODT 1 AD4 DDR3 O SB_DQ 51 ATO DDR3 1 0 SB_RAS AB8 DDR3 O SB_DQ 52 AH11 DDR3 1 0 SB_WE AB9 DDR3 O SB_DQ 53 AR8 DDR3 1 0 SKTOCC AN34 Analog O SB DQ 54 AJ12 DDR3 1 0 SM_DRAMPWROK V8 Asynch CMOS I SB DQ 55 AH12 DDR3 1 0 SM_DRAMRST R8 DDR3 O SB_DQ 56 AT11 DDR3 1 0 SM_RCOMP 0 AK1 Analog 1 0 SB_DQ 57 AN14 DDR3 1 0 SM RCOMP 1 A5 Analog 1 0 SB_DQ 58 AR14 DDR3 1 0 SM_RCOMP 2 A4 Analog 1 0 SB_DQ 59 AT14 DDR3 1 0 SM_VREF AL1 Analog I SB DQ 60 AT12 DDR3 1 0 TCK AR26 CMOS I SB DQ 61 AN15 DDR3 1 0 TDI AR28 CMOS I SB DQ 62 AR15 DDR3 1 0 TDO AP26 CMOS O SB DQ 63 AT15 DDR3 1 0 THERMTRIP AN32 Asynch CMOS O SB_DQS 0 D7 DDR3 1 0 TMS AR27 CMOS I SB_DQS 1 F3 DDR3 1 0 TRST AP30 CMOS I SB_DQS 2 K6 DDR3 1 0 UNCOREPWRGOOD AP33 Asynch CMOS I SB_DQS 3 N3 DDR3 1 0 VAXG AH17 PWR SB_DQS 4 AN5 DDR3 1 0 VAXG AH18 PWR SB_DQS 5 AP DDBS3 mo VAXG AH20 PWR SBDOSH6 AKi2 DDR3 Lo VAXG AH21 PWR 114 Datasheet Volume 1 Processor Pin Signal and Package Information Table 8 1 rPGA988B Processor Pin List by Pin Name Continued Table 8 1 rPGA988B Processor Pin List by Pin Name Continued intel
92. MM P erc DRAM M physical aye SS al de Page Version Capacity Technology Organization Devices rnit ee ic Size 2GB 2 Gb 128 M x 16 8 14 10 8 8K B 4 GB 4 Gb 256 M x 16 8 2 15 10 8 8K 1 GB 1 Gb 128Mx8 8 1 14 10 8 8K B 2 GB 2 Gb 256Mx8 8 1 15 10 8 8K 4 GB 4 Gb 512Mx8 8 1 16 10 8 8K 1 GB 2 Gb 128 M x 16 4 1 14 10 8 8K 2 2 GB 4 Gb 256 Mx 16 4 1 15 10 8 8K 2 GB 1Gb 128Mx8 16 2 14 10 8 8K F 4 GB 2Gb 256 Mx 8 16 2 15 10 8 8K 8 GB 4 Gb 512Mx8 16 2 16 10 8 8K Note 1 System memory configurations are based on availability and are subject to change Supported Maximum Memory Size Per DIMM e Max Size Per Configuration GB Max Size Platform Package Memory a ii 1 Ch 1 Ch 2 Ch 2 Ch 1 DPC 2 DPC 1 DPC 2 DPC SODIMM RCA 4 4 8 8 16 SODIMM RC B 4 4 8 8 16 Mobile rPGA SODIMM RC C 2 2 4 4 8 SODIMM BCE 8 8 16 16 32 SODIMM RC A 4 4 N A 8 N A SODIMM RC B 4 4 N A 8 N A Mobile SFF BGA SODIMM RC C 2 2 N A 4 N A SODIMM RC F 8 8 N A 16 N A MD like RC A 4 4 N A 8 N A Mobile SFF MD like RC B 4 4 N A 8 N A Memory Down MD like RC C 2 2 N A 4 N A MD like RC F 8 8 N A 16 N A System Memory Timing Support The IMC supports the following Speed Bins CAS Write Latency CWL and command signal mode timings on the main memory interface e tCL CAS Latency e tRCD Activate Command to READ or WRITE Command delay e tRP PRECHARGE Command Period e CWL CAS Write Latency e Command Sign
93. MOS I DMI_RX 1 T9 DMI I CFG 10 F55 CMOS I DMI_RX 2 R6 DMI I CFG 11 K55 CMOS I DMI_RX 3 U8 DMI I CFG 12 F57 CMOS I DMI_TX 0 N4 DMI O CFG 13 E58 CMOS I DMI_TX 1 R4 DMI O CFG 14 H57 CMOS I DMI_TX 2 P1 DMI O CFG 15 H55 CMOS I DMI_TX 3 U6 DMI O CFG 16 D53 CMOS I DMI_TX 0 N2 DMI O CFG 17 K57 CMOS I DMI_TX 1 R2 DMI O DBR H61 Asynch CMOS O DMI_TX 2 P3 DMI O DC_TEST_A4 A4 N A DMI_TX 3 T5 DMI O DC_TEST_A62 A62 N A DPLL_REF_CLK AJ4 Diff Clk I DC_TEST_A64 A64 N A DPLL REF CLK AJ2 Diff Clk I DC_TEST_B3 B3 N A eDP_AUX AE4 eDP 1 0 DC_TEST_B63 B63 N A eDP_AUX AE2 eDP 1 0 Datasheet Volume 1 123 intel Processor Pin Signal and Package Information Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type bir Ball Name Ball Buffer Type bir eDP COMPIO AC2 Analog I PEG RX 1 H23 PCIe I eDP_HPD AE8 Asynch CMOS I PEG_RX 2 H21 PCIe I eDP ICOMPO AB1 Analog I PEG RX4 3 H19 PCIe I eDP_TX 0 AG2 eDP O PEG_RX 4 320 PCIe I eDP_TX 1 AF1 eDP O PEG_RX 5 G18 PCIe I eDP_TX 2 AE6 eDP O PEG_RX 6 K17 PCle I eDP_TX 3 AG6 eDP O PEG_RX 7 F15 PCIe I eDP TX 0 AG4 eDP O PEG_RX 8 H15 PCIe I eDP_TX 1 AF3 eDP O PEG_RX 9 H13 PCIe I eDP TX 2 AF7 eDP O PEG_RX 10 H11 PCIe I eDP_TX 3 AG8 eDP O PEG_RX 11 J12 PCIe I FDI INT AD9 Asy
94. Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir PEG_TX 6 A14 PCIe O RSVD BH43 PEG_TX 7 D17 PCIe O RSVD BH35 PEG_TX 8 B15 PCIe O RSVD BH25 PEG_TX 9 E16 PCIe O RSVD BH23 PEG_TX 10 D13 PCIe O RSVD BH21 PEG_TX 11 A10 PCIe O RSVD BH19 PEG_TX 12 B11 PCIe O RSVD BG62 PEG_TX 13 D9 PCIe O RSVD BG34 PEG_TX 14 B7 PCIe O RSVD BG26 PEG_TX 15 E12 PCIe O RSVD BG22 PEG TX 0 C22 PCIe O SB_DIMM_VREFDQ BG4 Analog O PEG_TX 1 D23 PCIe O RSVD BF63 PEG_TX 2 A18 PCIe O RSVD BF43 PEG_TX 3 B21 PCIe O RSVD BF41 PEG_TX 4 D19 PCIe O RSVD BF35 PEG_TX 5 F21 PCIe O RSVD BF25 PEG_TX 6 C14 PCIe O RSVD BF23 PEG_TX 7 B17 PCIe O RSVD BF21 PEG_TX 8 D15 PCIe O RSVD BF19 PEG_TX 9 F17 PCIe O SA_DIMM_VREFDQ BF3 Analog O PEG_TX 10 B13 PCIe O RSVD BE32 PEG_TX 11 C10 PCIe O RSVD BE16 PEG_TX 12 D11 PCIe O RSVD BE6 PEG_TX 13 B9 PCIe O RSVD BD33 PEG_TX 14 D7 PCIe O RSVD BD29 PEG_TX 15 F13 PCIe O RSVD BD19 PM_SYNC K53 Asynch CMOS I RSVD BD15 PRDY J62 Asynch CMOS O RSVD BD13 PREQ H65 Asynch CMOS I RSVD BC42 PROC_DETECT B59 Analog RSVD BC30 PROC_SELECT AH9 N A RSVD BC14 PROCHOT H51 Asynch CMOS I O RSVD BB57 RESET K51 Asynch CMOS I RSVD BB43 RSVD G64 RSVD BB25 RSVD BJ42 RSVD BB17 RSVD BJ34 RSVD BB15 RSVD BJ22 RSVD BB13 Datasheet Volume 1 125 m n tel Processor Pin Signal and Package Information
95. O VSS AE28 GND VCCSA_VID 0 C22 CMOS O VSS AE29 GND VCCSA_VID 1 C24 CMOS O VSS AE30 GND VDDQ AC1 PWR VSS AE31 GND VDDQ AC4 PWR VSS AE32 GND VDDQ AC7 PWR VSS AE33 GND VDDQ AF1 PWR VSS AE34 GND VDDQ AF4 PWR VSS AE35 GND VDDQ AF7 PWR VSS AE9 GND VDDQ P1 PWR VSS AF2 GND VDDQ P4 PWR VSS AF3 GND VDDQ P7 PWR VSS AF5 GND VDDQ U1 PWR VSS AF6 GND VDDQ U4 PWR VSS AG4 GND VDDQ U7 PWR VSS AG8 GND VDDQ Yi PWR VSS AG9 GND VDDO Y4 PWR VSS AH16 GND VDDQ Y7 PWR VSS AH19 GND VIDALERT AJ29 CMOS I VSS AH22 GND VIDSCLK AJ30 CMOS O VSS AH25 GND VIDSOUT AJ28 CMOS I O VSS AH26 GND VSS A20 GND VSS AH28 GND VSS A23 GND VSS AH29 GND VSS A26 GND VSS AH30 GND VSS A29 GND VSS AH32 GND VSS A3 GND VSS AH34 GND VSS A32 GND VSS AH35 GND Datasheet Volume 1 117 m n tel Processor Pin Signal and Package Information Table 8 1 rPGA988B Processor Pin List Table 8 1 rPGA988B Processor Pin List by Pin Name Continued by Pin Name Continued Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VSS AH4 GND VSS AM7 GND VSS AH7 GND VSS AN10 GND VSS AJ1 GND VSS AN13 GND VSS AJ10 GND VSS AN16 GND VSS AJ13 GND VSS AN19 GND VSS AJ16 GND VSS AN22 GND VSS AJ19 GND VSS AN25 GND VSS AJ2 GND VSS AN27 GND VSS AJ22 GND VSS AN30 GND VSS AJ25 GND VSS AN4 GND VSS 23 GND VSS AN7 GND VSS AJ4 GND VSS AP1 GND VSS AJ7 GND VSS AP10 GND VSS AK10 GND VSS AP1
96. OF ITS PARTS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request This document contains information on products in the design phase of development Do not finalize a design with this information Revised information will be published when the product is available Verify with your local sales office that you have the latest datasheet before finalizing a design Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or go to http www intel com design literature htm Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a su
97. Overlap and Out of Order Scheduling Intel FMA technology enhancements Just in Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next The most efficient request is picked from all pending requests and issued to system memory Just in Time to make optimal use of Command Overlapping Thus instead of having all memory access requests go individually through an arbitration mechanism forcing requests to be executed one at a time they can be started without interfering with the current request allowing for concurrent issuing of requests This allows for optimized bandwidth and reduced latency while maintaining appropriate command spacing to meet system memory protocol Command Overlap Command Overlap allows the insertion of the DRAM commands between the Activate Precharge and Read Write commands normally used as long as the inserted commands do not affect the currently executing command Multiple commands can be issued in an overlapping manner increasing the efficiency of system memory protocol Out of Order Scheduling While leveraging the Just in Time Scheduling and Command Overlap enhancements the IMC continuously monitors pending requests to system memory for the best use of bandwidth and reduction of latency If there are multiple requests to the same open page these requests would be launched in a b
98. P SM_RCOMP2 Resistance 198 200 202 Q 8 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vr is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value 3 Viu is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 Viy and Voy may experience excursions above Vppg However input signal drivers must comply with the signal quality specifications 5 This is the pull up pull down driver resistance 6 Rrgau is the termination on the DIMM and in not controlled by the processor 7 The minimum and maximum values for these signals are programmable by BIOS to one of the two sets 8 SM RCOMPx resistance must be provided on the system board with 1 resistors SM RCOMPx resistors are to Vss 9 SM DRAMPWROK must have a maximum of 15 ns rise or fall time over Vppg 0 554 200 mV and the edge must be monotonic 10 SM VREF is defined as Vppo 2 11 Ron tolerance is preliminary and might be subject to change Table 7 12 Control Sideband and TAP Signal Group DC Specifications Symbol Parameter Min Max Units Notes VIL Input Low Voltage Vecio 0 3 V 2 Vin Input High Voltage Vecio 0 7 V 2 4 VoL Output Low Voltage Vccio 0 1 V 2 VoH Output High Voltage Vecio 0 9 V 2 4 Ron Buffer on Resistance 23 73 Q Ij Input Leakage Current 200
99. PCH When supporting Multi Graphics Multi Monitors drag and drop between monitors and the 2x8 PEG is not supported Platform Environment Control Interface PECI The PECI is a one wire interface that provides a communication channel between a PECI client processor and a PECI master The processor implements a PECI interface to e Allow communication of processor thermal and other information to the PECI master e Read averaged Digital Thermal Sensor DTS values for fan speed control Interface Clocking Internal Clocking Requirements Reference Clock Reference Input Clock Input Frequency Associated PLL BCLK BCLK 100 MHz Processor Memory Graphics PCIe DMI FDI DPLL REF CLK DPLL REF CLK 120 MHz Embedded DisplayPort eDP Datasheet Volume 1 Technologies 3 3 1 3 1 1 intel Technologies This chapter provides a high level description of Intel technologies implemented in the processor The implementation of the features may vary between the processor SKUs Details on the different technologies of Intel processors and other relevant external notes are located at the Intel technology web site http www intel com technology Intel Virtualization Technology Intel Virtualization Technology Intel VT makes a single system appear as multiple independent systems to software This allows multiple independent operating systems to run simultaneously on a single system Intel VT co
100. PWR VCC H35 PWR VCC C32 PWR Datasheet Volume 1 131 m n tel Processor Pin Signal and Package Information Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VCC C28 PWR VCCIO AT48 PWR VCC C26 PWR VCCIO AT17 PWR VCC B45 PWR VCCIO AT15 PWR VCC B43 PWR VCCIO AT12 PWR VCC B41 PWR VCCIO AR58 PWR VCC B37 PWR VCCIO AR56 PWR VCC B35 PWR VCCIO AR52 PWR VCC B31 PWR VCCIO AR49 PWR VCC B29 PWR VCCIO AR20 PWR VCC A44 PWR VCCIO AR18 PWR VCC A40 PWR VCCIO AR16 PWR VCC A38 PWR VCCIO AR14 PWR VCC A34 PWR VCCIO AP55 PWR VCC A32 PWR VCCIO AP53 PWR VCC A28 PWR VCCIO AP48 PWR VCC A26 PWR VCCIO AN58 PWR VCC_DIE_SENSE F47 Analog O VCCIO AN56 PWR VCC_SENSE B47 Analog O VCCIO AN52 PWR VCC_VAL_SENSE D47 Analog O VCCIO AN49 PWR VCCDQ AV23 PWR VCCIO AN20 PWR VCCDQ AT23 PWR VCCIO AN18 PWR VCCDQ AP23 PWR VCCIO AN16 PWR VCCDQ AL23 PWR VCCIO AN14 PWR VCCIO AV55 PWR VCCIO AM11 PWR VCCIO AV53 PWR VCCIO AL55 PWR VCCIO AVa8 PWR VCCIO AL53 PWR VCCIO AV17 PWR VCCIO AL48 PWR VCCIO AV15 PWR VCCIO AL17 PWR VCCIO AV12 PWR VCCIO AL15 PWR VCCIO AU58 PWR VCCIO AL12 PWR VCCIO AU56 PWR VCCIO AK58 PWR VCCIO AU52 PWR VCCIO AK56 PWR VCCIO AU49 PWR VCCIO AJ17 PWR VCCIO AU20 PWR VCCIO AJ15 PWR VCCIO AU18 PWR VCCIO AJ12 PWR VCCIO AT55 PW
101. PWR VDDQ AV27 PWR VCCSA T11 PWR VDDQ AU45 PWR VCCSA N18 PWR VDDQ AU43 PWR VCCSA N16 PWR VDDQ AU39 PWR VCCSA N14 PWR VDDQ AU37 PWR VCCSA M17 PWR VDDQ AU33 PWR Datasheet Volume 1 133 intel Processor Pin Signal and Package Information Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball Buffer Type Dir VDDQ AU30 PWR VDDQ AL34 PWR VDDQ AU26 PWR VDDQ AL29 PWR VDDQ AU24 PWR VDDQ AL27 PWR VDDQ AT46 PWR VDDQ_SENSE AY19 Analog O VDDQ AT42 PWR VIDALERT B51 CMOS I VDDQ AT40 PWR VIDSCLK D51 CMOS O VDDQ AT36 PWR VIDSOUT A50 CMOS 1 0 VDDQ AT34 PWR VSS BJ56 GND VDDQ AT29 PWR VSS BJ52 GND VDDQ AT27 PWR VSS BJ48 GND VDDQ AR45 PWR VSS BJ40 GND VDDQ AR43 PWR VSS BJ32 GND VDDQ AR39 PWR VSS BJ24 GND VDDQ AR37 PWR VSS BJ20 GND VDDQ AR33 PWR VSS BJ16 GND VDDQ AR30 PWR VSS BJ12 GND VDDQ AR26 PWR vss BJ8 GND VDDO AR24 PWR VSS BG60 GND VDDQ AP46 PWR VSS BG56 GND VDDQ AP42 PWR VSS BG52 GND VDDQ AP40 PWR VSS BG48 GND VDDQ AP36 PWR VSS BG44 GND VDDQ AP34 PWR VSS BG36 GND VDDQ AP29 PWR VSS BG28 GND VDDQ AP27 PWR VSS BG24 GND VDDQ AN45 PWR VSS BG20 GND VDDQ AN43 PWR VSS BG16 GND VDDQ AN39 PWR VSS BG12 GND VDDQ AN37 PWR vss BG8 GND VDDO AN33 PWR VSS BF5 GND VDDQ AN30 PWR VSS BE62 GND VDDQ AN26 PWR VSS BE58 GND VDDQ AN24 PWR VSS BE54
102. R VCCIO AH16 PWR VCCIO AT53 PWR VCCIO AH14 PWR 132 Datasheet Volume 1 Processor Pin Signal and Package Information Table 8 2 BGA1224 Processor Ball List by Ball Name Continued intel Table 8 2 BGA1224 Processor Ball List by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball 4 Buffer Type Dir VCCIO AH11 PWR VCCSA M15 PWR VCCIO AF16 PWR VCCSA M12 PWR VCCIO AF14 PWR VCCSA M11 PWR VCCIO AE17 PWR VCCSA L18 PWR VCCIO AE15 PWR VCCSA L14 PWR VCCIO AE12 PWR VCCSA_SENSE K3 Analog VCCIO AD11 PWR VCCSA_VID 0 AE10 CMOS VCCIO AC17 PWR VCCSA_VID 1 AG10 CMOS VCCIO AC15 PWR VDDQ BJ36 PWR VCCIO AC12 PWR VDDQ BJ28 PWR VCCIO AB16 PWR VDDQ BG40 PWR VCCIO AB14 PWR VDDQ BG32 PWR VCCIO Y16 PWR VDDQ BD47 PWR VCCIO Y14 PWR VDDQ BD43 PWR VCCIO Y11 PWR VDDQ BD39 PWR VCCIO SEL AJ8 N A VDDQ BD31 PWR VCCIO SENSE AW10 Analog VDDQ BD23 PWR VCCPLL AK65 PWR VDDQ BB35 PWR VCCPLL AK63 PWR VDDQ AY47 PWR VCCPLL AK61 PWR VDDQ AY43 PWR VCCPQE AV21 PWR VDDQ AY39 PWR VCCPQE AT21 PWR VDDQ AY35 PWR VCCPQE AP21 PWR VDDQ AY31 PWR VCCPQE AL21 PWR VDDQ AY27 PWR VCCSA W17 PWR VDDQ AY23 PWR VCCSA W15 PWR VDDO AV46 PWR VCCSA W12 PWR VDDO AV42 PWR VCCSA U17 PWR VDDQ AV40 PWR VCCSA U15 PWR VDDQ AV36 PWR VCCSA U12 PWR VDDQ AV34 PWR VCCSA T16 PWR VDDQ AV29 PWR VCCSA T14
103. R VCCIO U10 PWR VCC V26 PWR VCCIO Y10 PWR VCC V27 PWR VCCIO A13 PWR VCC V28 PWR VCCIO A14 PWR VCC V29 PWR VCCIO B14 PWR VCC V30 PWR VCCIO C13 PWR VCC v31 PWR VCCIO C14 PWR VCC V32 PWR VCCIO D13 PWR VCC V33 PWR VCCIO D14 PWR VCC V34 PWR VCCIO E14 PWR Datasheet Volume 1 Processor Pin Signal and Package Information Table 8 1 rPGA988B Processor Pin List by Pin Name Continued Table 8 1 rPGA988B Processor Pin List by Pin Name Continued intel Pin Name Pin 4 Buffer Type Dir Pin Name Pin 4 Buffer Type Dir VCCIO F13 PWR VSS A35 GND VCCIO F14 PWR VSS AB26 GND VCCIO G13 PWR VSS AB27 GND VCCIO G14 PWR VSS AB28 GND VCCIO H14 PWR VSS AB29 GND VCCIO J13 PWR VSS AB30 GND VCCIO J14 PWR VSS AB31 GND VCCIO_SEL A19 N A O VSS AB32 GND VCCIO_SENSE B10 Analog O VSS AB33 GND VCCPLL A2 PWR VSS AB34 GND VCCPLL A6 PWR VSS AB35 GND VCCPLL B6 PWR VSS AC2 GND VCCSA H25 PWR VSS AC3 GND VCCSA H26 PWR VSS AC5 GND VCCSA J24 PWR VSS AC6 GND VCCSA J25 PWR VSS AC8 GND VCCSA J26 PWR VSS AC9 GND VCCSA L26 PWR VSS AD7 GND VCCSA M26 PWR VSS AE26 GND VCCSA M27 PWR VSS AE27 GND VCCSA_SENSE H23 Analog
104. R3 1 0 SA_DQS 4 BB51 DDR3 1 0 SA_DQ 40 BC54 DDR3 1 0 SA_DQS 5 BD55 DDR3 1 0 SA_DQ 41 AY53 DDR3 1 0 SA_DQS 6 BD61 DDR3 1 0 SA_DQ 42 AW54 DDR3 1 0 SA_DQS 7 AV61 DDR3 1 0 SA_DQ 43 AY55 DDR3 1 0 SA_MA 0 BD27 DDR3 O SA_DQ 44 BD53 DDR3 1 0 SA_MA 1 BA28 DDR3 O SA DQ 45 BB53 DDR3 1 0 SA_MA 2 BB27 DDR3 O SA_DQ 46 BE56 DDR3 1 0 SA_MA 3 AW26 DDR3 O SA_DQ 47 BA56 DDR3 1 0 SA_MA 4 BB23 DDR3 O SA_DQ 48 BD57 DDR3 1 0 SA_MA 5 BA24 DDR3 O SA_DQ 49 BF61 DDR3 1 0 SA_MA 6 AY21 DDR3 O Datasheet Volume 1 127 m n tel Processor Pin Signal and Package Information Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir SA_MA 7 BD21 DDR3 O SB_DQ 12 AV1 DDR3 1 0 SA_MA 8 BC22 DDR3 O SB_DQ 13 AU2 DDR3 I O SA_MA 9 BB21 DDR3 O SB_DQ 14 BA2 DDR3 1 0 SA_MA 10 AW38 DDR3 O SB_DQ 15 BB3 DDR3 I O SA_MA 11 AW22 DDR3 O SB_DQ 16 BC2 DDR3 Wie SA_MA 12 BA20 DDR3 O SB_DQ 17 BF7 DDR3 o SA_MA 13 BB45 DDR3 O SB_DQ 18 BF11 DDR3 1 0 SA_MA 14 BE20 DDR3 O SB_DQ 19 BJ10 DDR3 o SA_MA 15 AW18 DDR3 O SB_DQ 20 BC4 DDR3 I O SA_ODT 0 BB41 DDR3 O SB_DQ 21 BH7 DDR3 1 0 SA_ODT 1 BC46 DDR3 O SB_DQ 22 BH11 DDR3 1 0 SA_RAS BE36 DDR3 O SB_DQ 23 BG10 DDR3 o SA_WE BA44 DDR3 O SB_DQ 24 BJ14 DDR3 1 0 SB BS 0 BJ38
105. SS BA42 GND VSS AU41 GND VSS BA38 GND VSS AU35 GND VSS BA34 GND VSS AU28 GND Datasheet Volume 1 135 m n tel Processor Pin Signal and Package Information Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VSS AU22 GND VSS AN47 GND VSS AU16 GND VSS AN41 GND VSS AU14 GND VSS AN35 GND VSS AT61 GND VSS AN28 GND VSS AT57 GND VSS AN22 GND VSS AT50 GND VSS AM61 GND VSS AT44 GND VSS AM7 GND VSS AT38 GND VSS AM3 GND VSS AT31 GND VSS AM1 GND VSS AT25 GND VSS AL57 GND VSS AT19 GND VSS AL50 GND VSS AT11 GND vss AL44 GND VSS AT7 GND VSS AL38 GND VSS AT3 GND VSS AL31 GND VSS AT1 GND VSS AL25 GND VSS AR54 GND VSS AL19 GND VSS AR47 GND vss AK16 GND VSS AR41 GND VSS AK14 GND VSS AR35 GND VSS AK11 GND VSS AR28 GND VSS AK9 GND VSS AR22 GND VSS AK5 GND VSS AP65 GND VSS AJ64 GND VSS AP63 GND VSS AJ62 GND VSS AP57 GND VSS AJ60 GND VSS AP50 GND VSS AJ57 GND VSS AP44 GND VSS AH7 GND VSS AP38 GND VSS AH3 GND VSS AP31 GND VSS AH1 GND VSS AP25 GND VSS AG57 GND VSS AP19 GND VSS AG17 GND VSS AP17 GND VSS AG15 GND VSS AP15 GND VSS AG12 GND VSS AP12 GND VSS AF65 GND VSS AP11 GND VSS AF63 GND VSS AP9 GND VSS AF61 GND VSS AP5 GND VSS AF11 GND VSS AN54 GND VSS AF9 GND 136 Da
106. Specifications 102 7 11 DDR3 DDR3L DDR3L RS Signal Group DC Gpechications 103 7 12 Control Sideband and TAP Signal Group DC Specifications Y YY YY Y nud 104 7 13 PCL Express DC SpecifIcations eiecit eade ou Dyd dong huis AE SAFE F R rA RU MAE 105 7 14 CDP DC Speciticat OnS ss iei ee Ride ZER a oae Fyn DRO nie dodge dra Ee erc 105 7 15 PECI DC Electrical Limit iiio eed rn ee ead edat eds dase rex he id eda da aa EE Sar EUR 107 8 1 rPGA988B Processor Pin List by Pin Name emen 110 8 2 BGA1224 Processor Ball List by Ball Name sss eee een 123 8 3 BGA1023 Processor Ball List by Ball Name ssssesses meme 142 9 1 DDR Data Swizzling Table Channel A 166 9 2 DDR Data Swizzling Table for Package Channel B sess 167 8 Datasheet Volume 1 Revision History Revision i us Number Description Revision Date 001 Initial release April 2012 Added Mobile 3rd Generation Intel Core i7 3520M i5 3360M i5 3320M i7 7U i5 3427 002 i7 3667U i5 3 U processors l June 2012 Updated Table 7 10 Processor Graphics Vaxc Supply DC Voltage and Current Specifications Updated Section 1 2 2 PCI Express Updated Section 1 5 Package Ri DDR 1 MH t 003 emoved 066 z suppor June 2012 Added support for DDR3L RS Updated Section 2 1 1 System Memory Technology Supported Updated Table 2 5 DDR3L DDR3L RS System Memory Timing Support 88 Datasheet Volume 1
107. T a CH CH CO CO CO Ss El co cit C1 cit cil Thread O C3 CO cit C3 ps C6 CO cil C3 C6 zm C7 CO cil C3 A Note If enabled the core C state will be C1E if all cores have resolved a core C1 state or higher Reguesting Low Power Idle States The primary software interfaces for reguesting low power idle states are through the MWAIT instruction with sub state hints and the HLT instruction for C1 and C1E However software may make C state reguests using the legacy method of I O reads from the ACPI defined processor clock control registers referred to as P_LVLx This method of requesting C states provides legacy support for operating systems that initiate C state transitions using I O reads To seamless support of legacy operating systems P_LVLx I O reads are converted within the processor to the eguivalent MWAIT C state reguest Therefore P_LVLx reads do not directly result in I O reads to the system The feature known as I O MWAIT redirection must be enabled in the BIOS The P_LVLx I O Monitor address needs to be set up before using the P_LVLx I O read interface Each P LVLx is mapped to the supported MWAIT Cx instruction as shown in Table 4 10 P_LVLx to MWAIT Conversion P_LVLx MWAIT Cx Notes P_LVL2 MWAIT C3 P_LVL3 MWAIT C6 C6 No sub states allowed P_LVL4 MWAIT C7 C7 No sub states allowed P_LVL5 MWAIT C7 C7 No sub states allowed The BIOS can write to the C state
108. Table 7 3 Note Signal Groups Sheet 2 of 2 PCI Express Graphics Signal Group Type Signals Single Ended AR Bi PECI CMOS Input VIDALERT Single Ended Open Drain Output VIDSCLK Bi directional VIDSOUT Voltage Regulator Single Ended CMOS Input VIDALERT Single Ended CMOS Output VCCSA_VID 1 0 Single Ended Open Drain Output VIDSCLK Single Ended ae a e VCCSA_SENSE Single Ended Analog Output VCC DIE SENSE VCC SENSE VSS SENSE VCCIO SENSE VSS SENSE VCCIO Differential Analog Output VAXG SENSE VSSAXG SENSE VCC VAL SENSE VSS VAL SENSE VAXG VAL SENSE VSSAXG VAL SENSE Power Ground Other Power VCC VCCIO VCCSA VCCPLL VDDQ VAXG VCCPOE VCCDQ Ground VSS VSS NCTF DC TEST A Single Ended No Connect RSVD RSVD_NCTF Test Point RSVD_TP Other SKTOCC PROC DETECT Differential PCI Express Input PEG RX 15 0 PEG RX 15 0 Differential PCI Express Output PEG TX 15 0 PEG_TX 15 0 Single Ended Analog Input PEG ICOMPO PEG ICOMPI PEG RCOMPO eDP Differential eDP Output eDP TX 3 0 eDP_TX 3 0 Differential eDP Bi directional eDP AUX eDP_AUX Single Ended Asynchronous CMOS eDP HPD Input Single Ended Analog Input eDP ICOMPO eDP COMPIO DMI Differential DMI Input DMI RX 3 0 DMI_RX 3 0 Differential DMI Output DMI TX 3 0 DMI TX2 3 0 Intel FDI FDIO FSYNC FDI1 FSYNC FDIO LSYNC Single Ended CMOS Input FDI1_LS
109. VSS T52 GND VSS L48 GND VSS T51 GND VSS L43 GND VSS T50 GND VSS L38 GND VSS T47 GND VSS L34 GND VSS T1 GND VSS L30 GND VSS R46 GND VSS L26 GND VSS R20 GND VSS L22 GND VSS R17 GND VSS L20 GND VSS R4 GND VSS L16 GND VSS P59 GND VSS K51 GND VSS P58 GND VSS K21 GND VSS P21 GND VSS K11 GND VSS P18 GND VSS K8 GND VSS P16 GND VSS J55 GND VSS P14 GND VSS J49 GND VSS P9 GND VSS JA GND VSS N61 GND VSS H58 GND VSS N56 GND VSS H53 GND VSS N52 GND VSS H21 GND VSS N51 GND VSS H17 GND VSS N48 GND VSS H14 GND VSS N47 GND VSS H10 GND VSS N43 GND VSS H4 GND VSS N40 GND VSS G61 GND VSS N36 GND VSS G51 GND VSS N33 GND VSS G48 GND VSS N28 GND VSS G6 GND VSS N25 GND VSS F55 GND 154 Datasheet Volume 1 Processor Pin Signal and Package Information Table 8 3 BGA1023 Processor Ball List by Ball Name Continued intel Table 8 3 BGA1023 Processor Ball List by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball 4 Buffer Type Dir VSS F40 GND VSS A21 GND VSS F35 GND VSS A17 GND VSS F29 GND VSS A13 GND VSS F19 GND VSS A9 GND VSS F15 GND VSS_NCTF BG57 VSS F13 GND VSS_NCTF BG5 VSS E40 GND VSS_NCTF BE58 VSS E35 GND VSS_NCTF BE4 VSS E29 GND VSS_NCTF BD59 VSS E25 GND VSS
110. YNC Single Ended Asynchronous CMOS FDI_INT Input FDIO TX 3 0 FDIO_TX 3 0 FDI1 TX 3 0 Differential FDI Output FDI1 TX4 3 0 Notes 1 Refer to Chapter 6 for signal description details 2 SAand SB refer to DDR3 Channel A and DDR3 Channel B 3 These signals only apply to BGA packages 4 The maximum rise fall time of UNCOREPWRGOOD is 20 ns All Control Sideband Asynchronous signals are required to be asserted deasserted for at least 10 BCLKs with a maximum Tyjse Trai of 6 ns in order for the processor to recognize the proper signal state See Section 7 9 for the DC specifications Datasheet Volume 1 97 7 8 Table 7 4 98 Electrical Specifications Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic Intel recommends the processor be first in the TAP chain followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Two copies of each signal may be required with each driving a different voltage level The processor supports Boundary Scan JTAG IEEE 1149 1 2001 and IEEE 1149 6 2003 standards Some small portion of the I O pins may support only one of these standards Component Storage Condition Specifications Prior to Board Attach This section applies to component level storage
111. _NCTF BD3 VSS E3 GND VSS_NCTF BC61 VSS D58 GND VSS_NCTF E61 VSS D54 GND VSS_NCTF E1 VSS D50 GND VSS_NCTF D59 VSS D46 GND VSS NCTF C58 VSS D43 GND VSS NCTF C3 VSS D40 GND VSS_NCTF A57 VSS D35 GND VSS_NCTF A5 VSS D29 GND VSS_SENSE G43 Analog O VSS D26 GND VSS_SENSE_VDDQ BA43 Analog O VSS D22 GND VSS_VAL_SENSE K43 Analog O VSS D18 GND VSSAXG SENSE G45 Analog O VSS D14 GND VSSAXG_VAL_SENSE K45 Analog O VSS D10 GND VSS SENSE VCCIO AN17 Analog O VSS D6 GND VSS D4 GND VSS C40 GND VSS C35 GND VSS C29 GND VSS A53 GND VSS A49 GND VSS A45 GND VSS A40 GND VSS A37 GND VSS A33 GND VSS A28 GND VSS A25 GND Datasheet Volume 1 155 Processor Pin Signal and Package Information intel 8 2 Package Mechanical Information Figure 8 6 Processor rPGA988B 2C GT1 G24406 Mechanical Package Sheet 1 of 2 m p 9 um A d SI E rm a Bo 3 i E 5 4 z 2 2 EL a 2 i 4 KETTER E DE E a 1 l gt E u i 2 dE E E
112. _TX 2 C16 eDP O CFG 2 AL26 CMOS I eDP_TX 3 G15 eDP O CFG 3 AL27 CMOS I FDI_INT H20 Asynch CMOS I CFG 4 AK26 CMOS I FDIO_FSYNC J18 CMOS I CFG 5 AL29 CMOS I FDIO LSYNC J19 CMOS I CFG 6 AL30 CMOS I FDIO_TX 0 A21 FDI O CFG 7 AM31 CMOS I FDIO_TX 1 H19 FDI O CFG 8 AM32 CMOS I FDIO_TX 2 E19 FDI O CFG 9 AM30 CMOS I FDIO_TX 3 F18 FDI O CFG 10 AM28 CMOS I FDIO TX 0 A22 FDI O CFG 11 AM26 CMOS I FDIO TX 1 G19 FDI O CFG 12 AN28 CMOS I FDIO_TX 2 E20 FDI O CFG 13 AN31 CMOS I FDIO_TX 3 G18 FDI O CFG 14 AN26 CMOS I FDI1_FSYNC J17 CMOS I CFG 15 AM27 CMOS I FDI1_LSYNC H17 CMOS I CFG 16 AK31 CMOS I FDI1_TX 0 B21 FDI O CFG 17 AN29 CMOS I FDI1_TX 1 C20 FDI O DBR AL35 Asynch CMOS O FDI1_TX 2 D18 FDI O DMI_RX 0 B27 DMI I FDI1_TX 3 E17 FDI O DMI_RX 1 B25 DMI I FDI1_TX 0 B20 FDI O DMI_RX 2 A25 DMI I FDI1_TX 1 C19 FDI O DMI_RX 3 B24 DMI I FDI1_TX 2 D19 FDI O DMI_RX 0 B28 DMI I FDI1_TX 3 F17 FDI O DMI_RX 1 B26 DMI I KEY B1 N A N A DMI_RX 2 A24 DMI I PECI AN33 Asynch 1 0 DMI_RX 3 B23 DMI I PEG_ICOMPI J22 Analog I DMI_TX 0 G21 DMI O PEG_ICOMPO J21 Analog I DMI TXZ 1 E22 DMI O PEG_RCOMPO H22 Analog I DMI_TX 2 F21 DMI O PEG_RX 0 K33 PCIe I DMI TX 3 D21 DMI O PEG_RX 1 M35 PCIe I DMI TX 0 G22 DMI O PEG_RX 2 L34 PCIe I DMI_TX 1 D22 DMI O PEG_RX 3 J35 PCIe I DMI_TX 2 F20 DMI O PEG_RX 4 J32 PCIe I 110 Datasheet Volume 1 Processor Pin Signal and Package Informa
113. ach direction simultaneously for an aggregate of 4 GB s when DMI x4 Shares 100 MHz PCI Express reference clock 15 1 2 4 1 2 5 16 Introduction 64 bit downstream address format however the processor never generates an address above 64 GB Bits 63 36 will always be zeros 64 bit upstream address format but the processor responds to upstream read transactions to addresses above 64 GB addresses where any of Bits 63 36 are nonzero with an Unsupported Request response Upstream write transactions to addresses above 64 GB will be dropped Supports the following traffic types to or from the PCH DMI gt DRAM DMI gt processor core Virtual Legacy Wires VLWs Resetwarn or MSIs only Processor core gt DMI APIC and MSI interrupt messaging support Message Signaled Interrupt MSI and MSI X messages Downstream SMI SCI and SERR error indication Legacy support for ISA regime protocol PHOLD PHOLDA required for parallel port DMA floppy drive and LPC bus masters DC coupling no capacitors between the processor and the PCH Polarity inversion PCH end to end lane reversal across the link Supports Half Swing low power low voltage Platform Environment Control Interface PECT The PECI is a one wire interface that provides a communication channel between a PECI client the processor and a PECI master The processor supports the PECI 3 0 Specification Processor Graphics The Processor Gra
114. ack to back manner to make optimum use of the open memory page This ability to reorder requests on the fly allows the IMC to further reduce latency and increase bandwidth efficiency Data Scrambling The memory controller incorporates a DDR3 Data Scrambling feature to minimize the impact of excessive di dt on the platform DDR3 VRs due to successive 1s and Os on the data bus Past experience has demonstrated that traffic on the data bus is not random Rather it can have energy concentrated at specific spectral harmonics creating high di dt that is generally limited by data patterns that excite resonance between the package inductance and on die capacitances As a result the memory controller uses a data scrambling feature to create pseudo random patterns on the DDR3 data bus to reduce the impact of any excessive di dt DRAM Clock Generation Every supported DIMM has two differential clock pairs There are total of four clock pairs driven directly by the processor to two DIMMs Datasheet Volume 1 27 2 2 2 2 1 Figure 2 2 28 Interfaces DDR3 Reference Voltage Generation The processor memory controller has the capability of generating the DDR3 Reference Voltage VREF internally for both read RDVREF and write VREFDQ operations The generated VREF can be changed in small steps and an optimum VREF value is determined for both during a cold boot through advanced DDR3 training procedures in order to provide the best voltage and s
115. al modes 1N indicates a new command may be issued every clock and 2N indicates a new command may be issued every 2 clocks Command launch mode programming depends on the transfer rate and memory configuration Datasheet Volume 1 Interfaces Table 2 4 Table 2 5 2 1 3 2 1 3 1 2 1 3 2 Note intel DDR3 DDR3L DDR3L RS 1 5 V System Memory Timing Support Transfer tCL tRCD tRP CWL CMD 1 Segment Rate tCK tCK tCK tCK DPC Mode Notes MT s 1 1N 2N D 1333 9 9 9 7 Extreme Edition 2 2N XE and Quad Core SV 1 1N 2N 1600 11 11 11 8 2 2N Dual Core 1333 9 9 9 y 1 1N 2N rage ta e Voltage SV Ultra 1600 11 11 11 8 1 1N 2N Note 1 System memory timing support is based on availability and is subject to change DDR3L DDR3L RS System Memory Timing Support Transfer tCL tRCD tRP CWL CMD 1 Segment Rate tCK tCK tCK tCK DPC Mode Notes MT s 1 1N 2N oo 1333 9 9 9 7 Extreme Edition 2 2N XE and Quad Core SV 1 1N 2N 1600 11 11 11 8 2 2N Dual Core 1333 9 9 9 7 1 1N 2N fees Voltage SV and Ultra 1600 11 11 11 8 1 1N 2N Notes 1 System memory timing support is based on availability and is subject to change System Memory Organization Modes The IMC supports two memory organization modes single channel and dual channel Depending upon how the DIMM Modules are populated in each memory channel a num
116. andle backlight phase in and ensures the documented and validated method to interrupt hardware phase in Automatic Display Brightness ADB This is a mobile only supported power management feature The Intel Automatic Display Brightness feature dynamically adjusts the backlight brightness based upon the current ambient light environment This feature requires an additional sensor to be on the panel front The sensor receives the changing ambient light conditions and sends the interrupts to the Intel Graphics driver As per the change in Lux current ambient light illuminance the new backlight setting can be adjusted through BLC The converse applies for a brightly lit environment Intel Automatic Display Brightness increases the back light setting Seamless Display Refresh Rate Switching Technology SDRRST This is a mobile only supported power management feature When a Local Flat Panel LFP supports multiple refresh rates the Intel Display Refresh Rate Switching power conservation feature can be enabled The higher refresh rate will be used when on plugged in power or when the end user has not selected enabled this feature The graphics software will automatically switch to a lower refresh rate for maximum battery life when the notebook is on battery power and when the user has selected enabled this feature There are two distinct implementations of Intel DRRS static and seamless The static Intel DRRS method uses a mode change to assign
117. aphics Render CSState ode a genua hus gri x ue saca ada NR aie sa EY de 62 4 6 4 Intel Smart 2D Display Technology Intel S2DDT cccsssssssssseseeeeeeseeees 62 4 6 5 Intel Graphics Dynamic Freguencn enne 62 4 6 6 Display Power Savings Technology 6 0 DPI 63 4 6 7 Automatic Display Brightness ADB sss meme 63 4 6 8 Seamless Display Refresh Rate Switching Technology SDRRST 63 4 7 Graphics Thermal Power Management 64 5 Thermal Management diri cree DEEN EE RENE a dE dA AR ANEN 65 5 1 Thermal Considerations eerte a Seed ENEE NEE 65 5 2 Intel Turbo Boost Technology Power Monitoring 65 5 3 Intel Turbo Boost Technology Power Control 66 5 3 1 Package Power Control nre A ta dek deeds dad Rx Eed EEN 66 5 3 2 Power Plane Controla EE 68 5 3 3 Turbo Time Parameter serie cintia oda ad tdi 68 5 4 Configurable TDP and Low Power Mode sss memet 68 EE D e ein et E KEIER 68 5 4 2 LOW POWer Mode sere cio ede a di 69 5 5 Thermal and Power Gpechficattons enne seems 70 5 6 Thermal Management Features KENE ENNEN ENER NNN ana de ha ku ai ka dnas i saa dada ARRA aa RR RR RR da 73 5 6 1 Adaptive Thermal MohitOr irren eher snn inna hs ina SEENEN NEEN NEEN 73 5 6 1 1 TCC Activation Offset ascii EES id eer dE RR RR deg AER 74 5 6 1 2 Frequency Voltage Control 74 5 6 1 3 Clock Modulation 1 3 erotik ennt tn dn dh rn a enc a ER RN 76 56 2 Dig
118. ately 130 C This is signaled to the system by the THERMTRIP signal 0 Asynchronous CMOS Datasheet Volume 1 87 intel 6 11 Table 6 13 Power Sequencing Power Sequencing Signal Description Signal Name Description Direction Buffer Type SM_DRAMPWROK SM_DRAMPWROK Processor Input Connects to PCH DRAMPWROK I Asynchronous CMOS UNCOREPWRGOOD The processor requires this input signal to be a clean indication that the VccsA Vecio Vaxg and Vppg power supplies are stable and within specifications This requirement applies regardless of the S state of the processor Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state This is connected to the PCH PROCPWRGD signal I Asynchronous CMOS SKTOCC rPGA only PROC_DETECT BGA SKTOCC Socket Occupied PROC_DETECT Processor Detect This signal is pulled down directly 0 Ohms on the processor package to the ground There is no connection to the processor silicon for this signal System board designers may use this signal to determine if the processor is present PROC_SELECT Processor Select This signal is an output that indicates if the processor used is 2nd Generation Intel Core processor family mobile or M
119. ature limit of the VR is reached By asserting PROCHOT pulled low and activating the TCC the VR will cool down as a result of reduced processor power consumption Bi directional PROCHOT can allow VR thermal designs to target thermal design current Iccrpc instead of maximum current Systems should still provide proper cooling for the VR and rely on bi directional PROCHOT only as a backup in case of system cooling failure Overall the system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP Thermal Solution Design and PROCHOT Behavior With a properly designed and characterized thermal solution it is anticipated that PROCHOT will only be asserted for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable However an under designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may e Cause a noticeable performance loss e Result in prolonged operation at or above the specified maximum junction temperature and affect the long term reliability of the processor e May be incapable of cooling the processor even when the TCC is active continuously in extreme situations Low Power States and PROCHOT Behavior
120. b fields a 16 bit cluster ID and a 16 bit logical ID within the cluster Consequently 2 20 16 processors can be addressed in logical destination mode Processor implementations can support fewer than 16 bits in the cluster ID sub field and logical ID sub field in a software agnostic fashion Datasheet Volume 1 45 m L l Technologies Note 3 8 3 9 46 e More efficient MSR interface to access APIC registers To enhance inter processor and self directed interrupt delivery as well as the ability to virtualize the local APIC the APIC register set can be accessed only through MSR based interfaces in the x2APIC mode The Memory Mapped IO MMIO interface used by xAPIC is not supported in the x2APIC mode e The semantics for accessing APIC registers have been revised to simplify the programming of frequently used APIC registers by system software Specifically the software semantics for using the Interrupt Command Register ICR and End Of Interrupt EOI registers have been modified to allow for more efficient delivery and dispatching of interrupts The x2APIC extensions are made available to system software by enabling the local X2APIC unit in the x2APIC mode To benefit from x2APIC capabilities a new operating system and a new BIOS are both needed with special support for the x2APIC mode The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendibility for future Int
121. ber of different configurations can exist Single Channel Mode In this mode all memory cycles are directed to a single channel Single channel mode is used when either Channel A or Channel B DIMM connectors are populated in any order but not both Dual Channel Mode Intel Flex Memory Technology Mode The IMC supports Intel Flex Memory Technology Mode Memory is divided into a symmetric and a asymmetric zone The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached In this mode the system runs with one zone of dual channel mode and one zone of single channel mode simultaneously across the whole memory array Channels A and B can be mapped for physical channel O and 1 respectively or vice versa however channel A size must be greater or equal to channel B size Datasheet Volume 1 25 intel Interfaces Figure 2 1 Intel Flex Memory Technology Operation 2 1 3 2 1 Note 2 1 4 26 TOM Non interleaved access B Dual channel interleaved access B B B CHA CHB CH A and CH B can be configured to be physical channels 0 or 1 B The largest physical memory amount of the smaller size memory module C The remaining physical memory amount of the larger size memory module Dual Channel Symmetric Mode Dual Channel Symmetric mode also known as interleaved mo
122. ble Control Signal This signal is used with SB RAS and O SB_CAS along with SB_CS to define the SDRAM Commands DDR3 SB RAS RAS Control Signal This signal is used with SB_CAS and SB_WE O along with SB CS to define the SRAM Commands DDR3 SB CAS CAS Control Signal This signal is used with SB RAS and SB WE O along with SB_CS to define the SRAM Commands DDR3 Data Strobes SB_DQS 7 0 and its complement signal group make SB_DQS 7 0 up a differential strobe pair The data is captured at the crossing point 1 0 SB_DQS 7 0 of SB_DQS 8 0 and its SB_DQS 7 0 during read and write DDR3 transactions Data Bus Channel B data signal interface to the SDRAM data bus I O SB DQ 63 0 9 DDR3 SB MAT15 0 Memory Address These signals are used to provide the multiplexed O MA 15 0 row and column address to the SDRAM DDR3 SDRAM Differential Clock Channel B SDRAM Differential clock signal pair The crossing of the positive edge of SB CK and the o SB_CK 3 0 negative edge of its complement SB_CK are used to sample the command and control signals on the SDRAM DDR3 Signals 3 2 are used only for 2 DPC system SDRAM Inverted Differential Clock Channel B SDRAM Differential o SB_CK 3 0 clock signal pair complement DDRS Signals 3 2 are used only for 2 DPC system Clock Enable 1 per rank These signals are used to e Initialize the SDRAMs during power up o SB_CKE 3 0 e Power down SDRAM ranks DDR3 Place all SDRAM ranks into a
123. c L3 Cache Sizing Upon entry into the package C7 state the L3 cache is reduced by N ways until it is completely flushed The number of ways N is dynamically chosen per concurrent C7 entry Similarly upon exit the L3 cache is gradually expanded based on internal heuristics IMC Power Management The main memory is power managed during normal operation and in low power ACPI Cx states Disabling Unused System Memory Outputs Any System Memory SM interface signal that goes to a memory module connector in which it is not connected to any actual memory devices such as SO DIMM connector is unpopulated or is single sided is tri stated The benefits of disabling unused SM signals are Reduced power consumption e Reduced possible overshoot undershoot signal quality issues seen by the processor I O buffer receivers caused by reflections from potentially un terminated transmission lines When a given rank is not populated the corresponding chip select and CKE signals are not driven At reset all rows must be assumed to be populated until it can be proven that they are not populated This is due to the fact that when CKE is tri stated with a SO DIMM present the SO DIMM is not ensured to maintain data integrity SCKE tri state should be enabled by BIOS where appropriate since at reset all rows must be assumed to be populated Datasheet Volume 1 57 m L Power Management 4 3 2 58 DRAM Power Management and Initial
124. cache All execution cores share the L3 cache Processor Graphics Rank SCI Intel Processor Graphics A unit of DRAM corresponding four to eight devices in parallel ignoring ECC These devices are usually but not always mounted on a single side of a SO DIMM System Control Interrupt Used in ACPI protocol Storage Conditions A non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor landings should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air that is unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material TAC Thermal Averaging Constant TDP Thermal Design Power TLP Transaction Layer Packets VaxG Graphics core power supply Vcc Processor core power supply Vccio High Frequency I O logic power supply VccPLL PLL power supply Vecsa System Agent memory controller DMI PCIe controllers and display engine power supply VDDQ DDR3 power supply VLD Variable Length Decoding Vss Processor ground x1 Refers to a Link or Port with one Physical Lane x16 Refers to a Link or Port with sixteen Physical Lanes x4 Refers to a Link or Port wi
125. ce using 32 bit operations 32 bit aligned only See the PCI Express Base Specification for details of both the PCI compatible and PCI Express Enhanced configuration mechanisms and transaction rules Datasheet Volume 1 Interfaces 2 2 3 The external graphics attach PEG on the processor is a single 16 lane x16 port The PEG port is being designed to be compliant with the PCI Express Base Specification Revision 3 0 2 2 3 1 PCI Express Graphics PCI Express Lanes Connection Figure 2 5 demonstrates the PCIe lanes mapping Figure 2 5 PCI Express Typical Operation 16 Lanes Mapping 1 X 4 Controller LELI 1 X 8 Controller AHORA 1X 16 Controller a As Lane 0 Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 lt gt Lane 6 Lane 7 Lane 8 cb Lane 9 Lane 10 lt Lane 11 Lane 12 Lane 13 AY Lane 14 E eg Lane 15 ENBIBIBIBIBIBIBIEIBIEUBIBIBIBIE AB Datasheet Volume 1 intel Interfaces 2 3 Note 2 3 1 2 3 2 2 3 3 2 4 32 Direct Media Interface DMI Direct Media Interface DMI connects the processor and the PCH Next generation DMI 2 0 is supported Only DMI x4 configuration is supported DMI Error Flow DMI can only generate SERR in response to errors never SCI SMI MSI PCI INT or
126. cessor and the ODO VIDALERT voltage regulator controllers This serial VID interface replaces CMOS I the parallel VID interface on previous processors Voltage selection for VCCSA For the platforms this signal o VCCSA VID 1 must have a pull down resistor to ground The output may be CMOS high or low and may change dynamically Voltage selection for VCCSA For 2nd Generation Intel Core processor family mobile the output will be low O VCCSA_VID O be 0 For Mobile 3rd Generation Intel Core processor family the CMOS output may be high or low and may change dynamically Note 1 The VCCSA_VID can toggle at most once in 500 uS The slew rate of VCCSA_VID is 1 V nS Sense Signals Table 6 15 Sense Signals Sheet 1 of 2 Direction Signal Name Description Buffer Type VCC_SENSE and VSS_SENSE provide an isolated low VCC_SENSE impedance connection to the processor core voltage and o VSS_SENSE ground They can be used to sense or measure voltage near the Analog silicon VAXG_SENSE VAXG_SENSE and VSSAXG_SENSE provide an isolated low o VSSAXG SENSE impedance connection to the Vayg voltage and ground They A can be used to sense or measure voltage near the silicon nalog VCCIO SENSE and VSS SENSE VCCIO provide an isolated low VCCIO SENSE impedance connection to the processor VCCIO voltage and o VSS_SENSE_VCCIO ground They can be used to sense or measure voltage near the Analog silicon VDDO_SENSE VDDO_S
127. cket overhead and link maintenance Maximum theoretical bandwidth on the interface of 8 GB s in each direction simultaneously for an aggregate of 16 GB s when x16 Gen 2 Gen 3 raw bit rate on the data pins of 8 0 GT s resulting in a real bandwidth per pair of 984 MB s using 128b 130b encoding to transmit data across this interface This also does not account for packet overhead and link maintenance Maximum theoretical bandwidth on the interface of 16 GB s in each direction simultaneously for an aggregate of 32 GB s when x16 Gen 3 Hierarchical PCI compliant configuration mechanism for downstream devices Traditional PCI style traffic asynchronous snooped PCI ordering Datasheet Volume 1 Introduction intel PCI Express extended configuration space The first 256 bytes of configuration space aliases directly to the PCI Compatibility configuration space The remaining portion of the fixed 4 KB block of memory mapped space above that starting at 100h is known as extended configuration space PCI Express Enhanced Access Mechanism Accessing the device configuration space in a flat memory mapped fashion Automatic discovery negotiation and training of link out of reset Traditional AGP style traffic asynchronous non snooped PCI X Relaxed ordering Peer segment destination posted write traffic no peer to peer read traffic in Virtual Channel 0 DMI gt PCI Express Port 0 DMI gt PCI Express Port 1 PCI Ex
128. de provides maximum performance on real world applications Addresses are ping ponged between the channels after each cache line 64 byte boundary If there are two requests and the second request is to an address on the opposite channel from the first that request can be sent before data from the first request has returned If two consecutive cache lines are requested both may be retrieved simultaneously since they are ensured to be on opposite channels Use Dual Channel Symmetric mode when both Channel A and Channel B DIMM connectors are populated in any order with the total amount of memory in each channel being the same When both channels are populated with the same memory capacity and the boundary between the dual channel zone and the single channel zone is the top of memory IMC operates completely in Dual Channel Symmetric mode The DRAM device technology and width may vary from one channel to the other Rules for Populating Memory Slots In all System Memory Organization Modes the frequency and latency timings of the system memory is the lowest supported frequency and slowest supported latency timings of all memory DIMM modules placed in the system as determined through the SPD registers Datasheet Volume 1 Interfaces 2 1 5 2 1 5 1 2 1 5 2 2 1 5 3 2 1 6 2 1 7 intel Technology Enhancements of Intel Fast Memory Access Intel FMA The following sections describe the Just in Time Scheduling Command
129. device storage temperature qualification methods may follow JESD22 A119 low temp and JESD22 A103 high temp standards when applicable for volatile memory 3 Component stress testing is conducted in conformance with JESD22 A104 4 The JEDEC J JSTD 020 moisture level rating and associated handling practices apply to all moisture sensitive devices removed from the moisture barrier bag Datasheet Volume 1 Electrical Specifications intel 7 9 DC Specifications The processor DC specifications in this section are defined at the processor pins unless noted otherwise See Chapter 8 for the processor pin listings and Chapter 6 for signal definitions e The DC specifications for the DDR3 signals are listed in Table 7 7 Control Sideband and Test Access Port TAP are listed in Table 7 8 e Table 7 14 lists the DC specifications for the processor and are valid only while meeting specifications for junction temperature clock frequency and input voltages Care should be taken to read all notes associated with each parameter e ACtolerances for all DC rails include dynamic load currents at switching frequencies up to 1 MHz 7 9 1 Voltage and Current Specifications Note Noise measurements on SENSE pins for all voltage supplies should be made with a 20 MHz bandwidth oscilloscope Table 7 5 Processor Core Vcc Active and Idle Mode DC Voltage and Current Specifications Sheet 1 of 2 Symbol Parameter Segment Mi
130. djusts between P States to maintain optimal performance power and thermals Datasheet Volume 1 Power Management 4 6 6 4 6 7 4 6 8 Display Power Savings Technology 6 0 DPST This is a mobile only supported power management feature The Intel DPST technique achieves backlight power savings while maintaining a good visual experience This is accomplished by adaptively enhancing the displayed image while decreasing the backlight brightness simultaneously The goal of this technique is to provide equivalent end user perceived image quality at a decreased backlight power level 1 The original input image produced by the operating system or application is analyzed by the Intel DPST subsystem An interrupt to Intel DPST software is generated whenever a meaningful change in the image attributes is detected A meaningful change is when the Intel DPST software algorithm determines that enough brightness contrast or color change has occurred to the displaying images that the image enhancement and backlight control needs to be altered 2 Intel DPST subsystem applies an image specific enhancement to increase image contrast brightness and other attributes 3 A corresponding decrease to the backlight brightness is applied simultaneously to produce an image with similar user perceived quality such as brightness as the original image Intel DPST 5 0 has improved the software algorithms and has minor hardware changes to better h
131. droom The opposite can happen when the processor cores are not consuming enough power to reach the package power limit For the integrated graphics this could mean an increase in the render core frequency above its rated frequency and increased graphics performance Both the processor core s and the graphics render core can increase frequency higher than possible without power sharing The processor Utilization of turbo graphic frequencies requires that the Intel Graphics driver to be properly installed Turbo graphic frequencies are not dependent on the operating system processor P state requests and may turbo while the processor is in any processor P states Datasheet Volume 1 43 m L l Technologies 3 5 3 6 3 6 1 3 6 2 44 Intel Advanced Vector Extensions AVX Intel Advanced Vector Extensions AVX is the latest expansion of the Intel instruction set It extends the Intel Streaming SIMD Extensions SSE from 128 bit vectors to 256 bit vectors Intel AVX addresses the continued need for vector floating point performance in mainstream scientific and engineering numerical applications visual processing recognition data mining synthesis gaming physics cryptography and other application areas The enhancement in Intel AVX allows for improved performance due to wider vectors new extensible syntax and rich functionality including the ability to better manage rearrange and sort data In the processor new inst
132. e Individual cores may be in lower power idle states while the package is in CO Package C1 C1E No additional power reduction actions are taken in the package C1 state However if the C1E sub state is enabled the processor automatically transitions to the lowest supported core clock frequency followed by a reduction in voltage The package enters the C1 low power state when e At least one core is in the C1 state e The other cores are in a C1 or lower power state The package enters the C1E state when e All cores have directly requested C1E using MWAIT C1 with a C1E sub state hint All cores are in a power state lower that C1 C1E but the package low power state is limited to C1 C1E using the PMG CST CONFIG CONTROL MSR e All cores have requested C1 using HLT or MWAIT C1 and C1E auto promotion is enabled in IA32 MISC ENABLES No notification to the system occurs upon entry to C1 C1E Package C3 State A processor enters the package C3 low power state when e At least one core is in the C3 state e The other cores are in a C3 or lower power state and the processor has been granted permission by the platform e The platform has not granted a request to a package C6 C7 state but has allowed a package C6 state In package C3 state the L3 shared cache is valid Package C6 State A processor enters the package C6 low power state when e At least one core is in the C6 state e The other cores are in a C6 or lower power state a
133. e C7 Execution cores in this state behave similarly to the C6 state If all execution cores request C7 L3 cache ways are flushed until it is cleared Integrated Memory Controller States Integrated Memory Controller States State Description Power up CKE asserted Active mode Pre charge Power Down CKE de asserted not self refresh with all banks closed Active Power Down CKE de asserted not self refresh with minimum one bank active Self Refresh CKE de asserted using device self refresh Datasheet Volume 1 Power Management 4 1 4 Table 4 4 4 1 5 Table 4 5 4 1 6 Table 4 6 4 1 7 Table 4 7 PCI Express Link States PCI Express Link States State Description LO Full on Active transfer state LOs First Active Power Management low power state Low exit latency L1 Lowest Active Power Management Longer exit latency L3 Lowest power state power off Longest exit latency DMI States DMI States State Description LO Full on Active transfer state LOs First Active Power Management low power state Low exit latency L1 Lowest Active Power Management Longer exit latency L3 Lowest power state power off Longest exit latency Processor Graphics Controller States Processor Graphics Controller States State Description DO Full on display active D3 Cold Power off Interface Sta
134. e This will represent a DC shift in the loadline Note Transitions above the maximum specified VID are not permitted Table 7 5 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained At condition outside functional operation condition limits neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded on exposure to conditions exceeding the functional operation condition limits The VR used must be capable of regulating its output to the value defined by the new VID values issued DC specifications for dynamic VID transitions are included in Table 7 5 and Table 7 10 Table 7 1 IMVP7 Voltage Identification Definition Sheet 1 of 3 Y Ka Mia ud Ka Ka Ka Ku HEX Vcc Max Ka Ka Ki g um kd TER Se HEX e hax 0 0 0 0 0 0 0 0 0 0 0 00000 1 0 0 0 0 0 0 O 8 0 0 88500 0 0 0 0 0 0 0 1 0 1 0 25000 1 0 0 0 0 0 0 1 8 1 0 89000 0 0 0 0 0 0 1 0 0 2 0 25500 1 0 0 0 0 0 1 O 8 2 0 89500 0 0 0 0 0 0 1 1 0 3 0 26000 1 0 0 0 0 0 1 1 8 3 0 90000 0 0 0 0 0 1 0 0 0 4 0 26500 1 0 0 0 0 1 0 O 8 4 0 90500 0 0 0 0 0 1 0 1 0 5 0 27000 1 0 0 0 0 1 0 1 8 5 0 91000 0 0 0 0 0 1
135. e 49 4 7 G S and C State Combinations 2 0 nennen nennen nnn nnn nnns 49 4 8 D S and C State Combinati N ceci SNE NEEN ia DRE UD DRY YR TR CERTE same 50 4 9 Coordination of Thread Power States at the Core Level 52 4 10 P LEVLX to MWATT Conversion Sita ua Y A e te Rare a DD Ee rk e Cu QR D M RENDER 52 Datasheet Volume 1 7 4 11 Coordination of Core Power States at the Package Level 55 4 12 Targeted Memory State Conditions 60 5 1 Intel Turbo Boost Technology Package Power Control Settings eee 67 5 2 Configurable TDP Modes eerie turni oni ver erga nora a sa xx AREA D ENER P wr amara ERG FRY BF 69 5 3 TDP Specifications coii Di tenerent A 71 5 4 Junction Temperature Specification YYY YY eee eee esee nnn 71 5 5 Package Turbo Parameters iion rtt cecal chads LAWR ENN eu GNAU AC OND ARR hae ees ners E ENEE AR 72 5 6 Idle Power Specifications x caisson a dna de FE Rei ES WE 73 6 1 Signal Description Buffer Types cccccsseccccececececcaeeeeeceaeaserecueeeceaueeaeeeeaeanaeaeereaeaeees 81 6 2 Memory Channel zedin PrvAR DAI agus eed We ER AU EAT dA DRAG 82 6 3 Memory Channel Bent dag e gt RUN nk ur EE mph OCR au e vice Laden AUR UR AN adds Ee setae DEN vad on nn 83 6 4 Memory Reference and Compensation ssssssssssssssessess eese eee ese 84 6 5 Reset and Miscellaneous Signals ALLA eee eee ee ee eee eee emnes 84 6 6 PCI Express Graphics Interface Signals e ee ee eee eee
136. e consuming less than the TDP at the rated frequency Intel Turbo Boost Technology takes advantage of the available TDP headroom and active cores are able to increase their operating frequency To determine the highest performance frequency amongst active cores the processor takes the following into consideration to recalculate turbo frequency during runtime e The number of cores operating in the CO state e The estimated core current consumption e The estimated package prior and present power consumption e The package temperature Any of these factors can affect the maximum frequency for a given workload If the power current or thermal limit is reached the processor will automatically reduce the frequency to stay with its TDP limit Turbo processor frequencies are only active if the operating system is requesting the PO state For more information on P states and C states refer to Chapter 4 Power Management Intel Turbo Boost Technology Graphics Frequency The graphics render frequency is selected dynamically based on graphics workload demand as permitted by the processor turbo control The processors can optimize both processor and integrated graphics performance through power sharing The processor cores and the integrated graphics core share a package power limit If the graphics core is not consuming enough power to reach the package power limit the cores can increase frequency to take advantage of the unused thermal power hea
137. e for large current swings generated during different power mode transitions e provide low parasitic resistance from the regulator to the socket e meet voltage and current specifications as defined in Table 7 3 PLL Power Supply An on die PLL filter solution is implemented on the processor Datasheet Volume 1 91 Electrical Specifications 7 3 Voltage Identification VID The processor uses three signals for the serial voltage identification interface to support automatic selection of voltages Table 7 4 specifies the voltage level corresponding to the eight bit VID value transmitted over serial VID A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the voltage regulation circuit cannot supply the voltage that is requested the voltage regulator must disable itself See the VR12 IMVP7 PWM Specification for further details The VID codes will change due to temperature and or current load changes in order to minimize the power of the part A voltage range is provided in Table 7 4 The specifications are set so that one voltage regulator can operate with all supported frequencies Individual processor VID values may be set during manufacturing so that two devices at the same core frequency may have different default VID settings This is shown in the VID range values in Table 7 5 The processor provides the ability to operate while transitioning to an adjacent VID and its associated voltag
138. e is defined by tXP and tXPDLL 10 20 according to the DDR type until first data transfer is allowed The processor supports 6 different types of power down The different modes are the power down modes supported by DDR3 and combinations of these The type of CKE power down is defined by configuration The options are as follows 1 No power down 2 APD The rank enters power down as soon as the idle timer expires independent of the bank status 3 PPD When idle timer expires the MC sends PRE all to rank and then enters power down 4 DLL off Same as option 2 but DDR is configured to DLL off 5 APD change to PPD APD PPD Begins as option 1 and when all page close timers of the rank are expired it wakes the rank issues PRE all and returns to PPD 6 APD change to DLL off APD_DLLoff Begins as option 1 and when all page close timers of the rank are expired it wakes the rank issues PRE all and returns to DLL off power down The CKE is determined per rank when it is inactive Each rank has an idle counter The idle counter starts counting as soon as the rank has no accesses and if it expires the rank may enter power down while no new transactions to the rank arrive to queues The idle counter begins counting at the last incoming transaction arrival Datasheet Volume 1 Power Management intel Note 4 3 2 1 4 3 2 2 It is important to understand that since the power down decision is per rank the MC can find a
139. e present when the Receiver terminations are first enabled to ensure that the Receiver Detect occurs properly Compensation of this impedance can start immediately and the 15 Rx Common Mode Impedance constrained by RLRX CM to 50 Q 20 must be within the specified range by the time Detect is entered Table 7 14 eDP DC Specifications Symbol Parameter Min Typ Max Units Notes eDP HPD Z VIL Input Low Voltage 0 1 0 3 Vccro Vin Input High Voltage 0 7 Vccio Vccio eDP AUX eDP_AUX AUX Peak to Peak Voltage at Vaux DIFFp p TX the transmitting device 0 4 mu 0 6 M 1 AUX Peak to Peak Voltage at VAUX DIFFp p RX the receiving device d ue B 136 M 1 eDP COMPs eDP_ICOMPI Comp Resistance 24 75 25 25 25 Q 2 3 eDP_COMPIO Comp Resistance 24 75 25 25 25 Q 23 Notes 1 Vaux piFFp p 2 lVauxp Vauxul Refer to the VESA DisplayPort Standard specification for more details 2 COMP resistance must be provided on the system board with 1 resistors COMP resistors are to Vss 3 eDP ICOMPI eDP_COMPIO are the same resistor Datasheet Volume 1 105 7 10 1 Figure 7 1 106 Electrical Specifications Platform Environmental Control Interface PECI DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external Adaptive Thermal Monitor devices The processor contains a Dig
140. e processor during a power or thermal management event Intel Adaptive Thermal Monitor Enhanced Intel SpeedStep Technology or Low Power States 102 Datasheet Volume 1 Electrical Specifications intel 3 The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE pins at the socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe 4 _PSx refers to the voltage regulator power state as set by the SVID protocol 5 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range This differs from the VID employed by the processor during a power or thermal management event Intel Adaptive Thermal Monitor Enhanced Intel SpeedStep Technology or Low Power States Table 7 11 DDR3 DDR3L DDR3L RS Signal Group DC Specifications Sheet 1 of 2 Symbol Parameter Min Typ Max Units Notes ViL Input Low Voltage SM_VREF 0 1 V 2 4 11 Vin Input High Voltage eal V 3 11 Input Low Voltage m X Vil SM_DRAMPWROK Ke N 10 Input High Voltage Vppo9 0 55 SM DRAMPWROK
141. e signals are used to provide the multiplexed o MA 15 0 row and column address to the SDRAM DDR3 SDRAM Differential Clock Channel A SDRAM Differential clock signal pair The crossing of the positive edge of SA CK and the negative edge SA CK 3 0 of its complement SA CK are used to sample the command and O control signals on the SDRAM DDR3 Signals 3 2 are used only for 2 DPC system SDRAM Inverted Differential Clock Channel A SDRAM Differential o SA_CK 3 0 clock signal pair complement DORS Signals 3 2 are used only for 2 DPC system Clock Enable 1 per rank These signals are used to e Initialize the SDRAMs during power up o SA_CKE 3 0 e Power down SDRAM ranks DDR3 Place all SDRAM ranks into and out of self refresh during STR e Signals 3 2 are used only for 2 DPC system Chip Select 1 per rank These signals are used to select particular SA CS4 3 SDRAM components during the active state There is one Chip Select O A_CS 3 0 for each SDRAM rank DDR3 Signals 3 2 are used only for 2 DPC system On Die Termination Active Termination Control O SA_ODT 3 0 7 3 0 Signals 3 2 are used only for 2 DPC system DDR3 82 Datasheet Volume 1 Signal Description Table 6 3 Memory Channel B intel Signal Name Description dus iiis SB BSI2 0 Bank Select These signals define which banks are selected within O BS 2 0 each SDRAM rank DDR3 SB WE Write Ena
142. e xAPIC architecture delivery modes interrupt and processor priorities interrupt sources interrupt destination types e Provides extensions to scale processor addressability for both the logical and physical destination modes e Adds new features to enhance performance of interrupt delivery e Reduces complexity of logical destination mode interrupt delivery on link based architectures The key enhancements provided by the x2APIC architecture over xAPIC are the following e Support for two modes of operation to provide backward compatibility and extensibility for future platform innovations In xAPIC compatibility mode APIC registers are accessed through memory mapped interface to a 4 KB page identical to the xAPIC architecture In x2APIC mode APIC registers are accessed through Model Specific Register MSR interfaces In this mode the x2APIC architecture provides significantly increased processor addressability and some enhancements on interrupt delivery e Increased range of processor addressability in x2APIC mode Physical xAPIC ID field increases from 8 bits to 32 bits allowing for interrupt processor addressability up to 4 GB 1 processors in physical destination mode A processor implementation of x2APIC architecture can support fewer than 32 bits in a software transparent fashion Logical xAPIC ID field increases from 8 bits to 32 bits The 32 bit logical x2APIC ID is partitioned into two su
143. eDP 1i eiii EK hw chest angen a e aea a IR ADR RARE tes 85 6 6 Intel Flexible Display Interface Signals een nennen nnn 85 6 7 Direct Media Interface DMI eode ege EEN a EEN SS ka ken Ra eR dnd EE e dE EN 86 6 8 Phase Lock Loop PLL Signals ones rir pun DM a 86 6 9 Test Access Points TAP Gionale eee eee ee ee n ipaa ane semen emen een 86 6 10 Error and Thermal Protection c cccecseceeeeeeeeeeedeeeeaeeeaeeenenneseeenseaeeeaaeanaeaseenaneeeenes 87 6 11 Power Sequencing niri tr etra terim bt Eln rata cutee be ROME DYNO CEG Ra kar DOR RAY ree EA 88 6 12 Processor Power Signals eiu a iei tnnc einn vn ERE RR ER ROC R apa MER RSEN EU FADE ands 89 6 13 Sense SignalS5 iiu Ems 89 6 14 Ground and NET Eaton ADG E Y NAY ERE REO fA WR GAD AM SG FA TO 90 6 15 Processor Internal Pull Up Pull Down sse 90 7 Electrical Specifications 11 204 YY GYNAR a AERE uS ERR NER NEEN 91 7 1 Power ANd Ground Pins gen NEE eere YN YRWAN EA Ng DENU A ED ea ER FR REN EN Gn Ronan dE ARIA V n 91 7 2 JDeco pling Guidelines eati Seege ENEE x ete SEENEN SEENEN SEANCE en Es 91 7 2 1 Voltage Rail Decoupling Y cent cette eter ARALL eene nennen een 91 A222 PUL Power Supply ice iS ds abla DUO UN Dex abu IPIS dI DU ea ig 91 7 3 Moltage Identification VID eiie geereggekageege ge eain NR axe ci ttt Di 92 7 4 System Agent SA Vee VID iieri t eee etie ca adie nade ada ed HRN a cages EROR E ri ETE 95 Zb Reserved or Unused Sig
144. ee ee emen 85 6 7 Embedded Display Port Gigonals YA RAY eee eee ee ensem nnne 85 6 8 Intel Flexible Display Interface te side niea da dae rota iud d auda diia 85 6 9 DMI Processor to PCH Serial Interface 86 6 10 PLLSIGMAlS Sce 86 6 11 RTL EE 86 6 12 Error and Thermal Protection iie tette nnde desea ee FER DAR aaa Dr dA E RA dek 87 6 13 Power Seguemncihd RE 88 6 14 Processor Power Signals iere r nennen hat RES an RR RENE NEE ENNEN EN EGRE ADN wn Adn ORA Hn HNN RR 89 Le Ke EE 89 6 16 Ground and INGEF E 90 6 17 Processor Internal Pull Up Pull Down 90 7 1 IMVP7 Voltage Identification Definition cececcee cece eee LL RAA ARA etree emm 92 7 2 VCESA VID Configuration 95 7 3 Signal Grous occisa te sese tenere rota eheu SEN Sa HR DUC EM henge ad ME RR RF EA CE 96 7 4 Storage Condition Ratings c cene YAR Y YR SARAH aenea a RYAN RYN RR EU a e CE ERR RR PEOR Y EE EY 98 7 5 Processor Core Vcc Active and Idle Mode DC Voltage and Current Specifications 99 7 6 Processor Uncore Vccro Supply DC Voltage and Current Specifications 101 7 7 Memory Controller VDDQ Supply DC Voltage and Current Specifications 101 7 8 System Agent VCCSA Supply DC Voltage and Current Specifications 101 7 9 Processor PLL VCCPLL Supply DC Voltage and Current Specifications 102 7 10 Processor Graphics VAXG Supply DC Voltage and Current
145. eing executed Core C1 C1E State C1 C1E is a low power state entered when all threads within a core execute a HLT or MWAIT C1 C1E instruction A System Management Interrupt SMI handler returns execution to either Normal state or the C1 C1E state See the Intel 64 and IA 32 Architecture Software Developer s Manual Volume 3A 3B System Programmer s Guide for more information While a core is in C1 C1E state it processes bus snoops and snoops from other threads For more information on C1E see Package C1 C1E Core C3 State Individual threads of a core can enter the C3 state by initiating a P LVL2 I O read to the P BLK or an MWAIT C3 instruction A core in C3 state flushes the contents of its L1 instruction cache L1 data cache and L2 cache to the shared L3 cache while maintaining its architectural state All core clocks are stopped at this point Because the core s caches are flushed the processor does not wake any core that is in the C3 state when either a snoop is detected or when another core accesses cacheable memory Core C6 State Individual threads of a core can enter the C6 state by initiating a P LVL3 I O read or an MWAIT C6 instruction Before entering core C6 the core will save its architectural state to a dedicated SRAM Once complete a core will have its voltage reduced to zero volts During exit the core is powered on and its architectural state is restored Datasheet Volume 1 53 m L Power Mana
146. el platform innovations Intel x2APIC technology may not be available on all SKUs For more information refer to the Intel 64 Architecture x2APIC specification at http www intel com products processor manuals Supervisor Mode Execution Protection SMEP The processor introduces a new mechanism that provides next level of system protection by blocking malicious software attacks from user mode code when the system is running in the highest privilege level This technology helps to protect from virus attacks and unwanted code to harm the system For more information please refer to Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A at http www intel com Assets PDF manual 253668 pdf Power Aware Interrupt Routing PAIR The processor added enhanced power performance technology which routes interrupts to threads or cores based on their sleep states For example concerning energy savings it routes the interrupt to the active cores without waking the deep idle cores For Performance it routes the interrupt to the idle C1 cores without interrupting the already heavily loaded cores This enhancement is mostly beneficial for high interrupt scenarios like Gigabit LAN WLAN peripherals and so on 88 Datasheet Volume 1 Power Management 4 Power Management This chapter provides information on the following power management topics ACPI States Processor Core Integrated Memory Controller IMC PCI Exp
147. elf refresh Datasheet Volume 1 59 intel Power Management The target behavior is to enter self refresh for the package C3 C6 and C7 states as long as there are no memory requests to service Table 4 12 Targeted Memory State Conditions Memory State with Processor Graphics Memory State with External Graphics Dynamic memory rank power down based on idle conditions Dynamic memory rank power down based on idle conditions If the processor graphics engine is idle and there are no pending display requests then enter self refresh Otherwise use dynamic memory rank power down based on idle conditions If there are no memory requests then enter self refresh Otherwise use dynamic memory rank power down based on idle conditions Self Refresh Mode Self Refresh Mode Memory power down contents lost Memory power down contents lost Dynamic Power Down Operation Dynamic power down of memory is employed during normal operation Based on idle conditions a given memory rank may be powered down The IMC implements aggressive CKE control to dynamically put the DRAM devices in a power down state The processor core controller can be configured to put the devices in active power down CKE de assertion with open pages or precharge power down CKE de assertion with all pages closed Precharge power down provides greater power savings but has a bigger performance impact since all pages will fi
148. elopers intel txt software development guide html Intel Hyper Threading Technology The processor supports Intel Hyper Threading Technology Intel HT Technology that allows an execution core to function as two logical processors While some execution resources such as caches execution units and buses are shared each logical processor has its own architectural state with its own set of general purpose registers and control registers This feature must be enabled using the BIOS and requires operating system support Intel recommends enabling Hyper Threading Technology with Microsoft Windows 7 Microsoft Windows Vista Microsoft Windows XP Professional Windows XP Home and disabling Hyper Threading Technology using the BIOS for all previous versions of Windows operating systems For more information on Hyper Threading Technology see http www intel com technology platform technology hyper threading Intel Turbo Boost Technology Intel Turbo Boost Technology will increase the ratio of application power to TDP Thus thermal solutions and platform cooling that are designed to less than thermal design guidance might experience thermal and performance issues since more applications will tend to run at the maximum power limit for significant periods of time Intel Turbo Boost Technology may not be available on all SKUs Intel Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster
149. emory and contains one image desktop cursor overlay It is the portion of the display hardware logic that defines the format and location of a rectangular region of memory that can be displayed on display output device and delivers that data to a display pipe This is clocked by the Core Display Clock Primary Planes A B and C Planes A B and C are the main display planes and are associated with Pipes A B and C respectively Sprite A B and C Sprite A and Sprite B are planes optimized for video decode and are associated with Planes A and B respectively Sprite A and B are also double buffered Cursors A B and C Cursors A and B are small fixed sized planes dedicated for mouse cursor acceleration and are associated with Planes A and B respectively These planes support resolutions up to 256 x 256 each VGA VGA is used for boot safe mode legacy games and so on It can be changed by an application without operating system driver notification due to legacy requirements Datasheet Volume 1 Interfaces 2 4 2 2 2 4 2 3 2 4 2 4 2 4 3 Display Pipes The display pipe blends and synchronizes pixel data received from one or more display planes and adds the timing of the display output device upon which the image is displayed The display pipes A B and C operate independently of each other at the rate of 1 pixel per clock They can attach to any of the display ports Each pipe sends display data to eDP or to t
150. ent processor families See www intel com products processor number for details Intel Intel Core and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2012 Intel Corporation All rights reserved 2 Datasheet Volume 1 Contents 1 Introduction eoe rex xti ri ne zien a 11 1 1 Processor Feature DetailS iicet aa dE DA erra eh Pech daa dE d e den 13 1 1 1 Supported Technologies ooi ee einn rnit de NEEN na BM gna na ae a uc Ri 13 1 2 Interfaces MT 13 1 2 1 System Memory SU ppOrt esisiini a pv PX area EE 13 1 2 2 PCL TEE 14 1 2 3 Direct Media Interface DMI cceccecceeceeeeeeeeseeeaeeenenseeeaeeeeananaenenenaeeesanes 15 1 2 4 Platform Environment Control Interface DECI 16 1 2 5 Processor Graphics odii cena aei ape da Sea OO REN AE e ERE DDUG Fd ELEM RARI 16 1 2 6 Embedded DisplayPort ep 17 1 2 7 Intel Flexible Display Interface Intel EDD 17 1 3 Power Management Support een gt age t duces deeg xn inm nick exi mace Ride Sek eu wa Da a ole de Ee x 17 1 34L Processor Corea yd Cea ca alan dane ee oce tes du Senet ea Ne ad 17 LIZ OS SM E EEE E EE E REER 17 1 3 3 Memory Controller siirsin ra tenen a RR XR ARR aaaea RR 17 1 3 4 PCI Express su 17 L35 DM Tr 17 1 3 6 Processor Graphics Controller GT 1
151. eserved configuration lane A test point may be placed on the board for this lane e CFG 2 PCI Express Static x16 Lane Numbering Reversal 1 Normal operation 0 Lane numbers reversed e CFG 3 Reserved CFG 17 0 e CFG 4 eDP enable CMOS 1 Disabled 0 Enabled e CFG 6 5 PCI Express Bifurcation 00 1 x8 2 x4 PCI Express 01 reserved 10 2 x8 PCI Express 11 1 x16 PCI Express e CFG 17 7 Reserved configuration lanes A test point may be placed on the board for these pins PM SYNC Power Management Sync A sideband signal to communicate I power management status from the platform to the processor CMOS RESET Platform Reset pin driven by the PCH m RSVD Reserved All signals that are RSVD and RSVD_NCTF must be left No Connect RSVD TP unconnected on the board However Intel recommends that all Test Point RSVD NCTF RSVD TP signals have via test points Non Critical to gt Function DDR3 DRAM Reset Reset signal from processor to DRAM devices O SM DRAMRST One common to all channels CMOS Datasheet Volume 1 Signal Description 6 4 PCI Express based Interface Signals Table 6 6 PCI Express Graphics Interface Signals d T Direction Signal Name Description Buffer Type A PEG_ICOMPI PCI Express Input Current Compensation e z PEG_ICOMPO PCI Express Current Compensation PEG RCOMPO PCI Express Resistance Compensation H P
152. esolution when using low bpp channels in color buffers is possible Color dithering diffuses the sharp color bands seen on smooth shaded objects Video Engine The video engine is part of the Intel Processor Graphics for image processing play back and transcode of Video applications The Processor Graphics video engine has a dedicated fixed hardware pipe line for high quality decode and encode of media content This engine supports Full hardware acceleration for decode of AVC H 264 VC 1 and MPEG 2 contents along with encode of MPEG 2 and AVC H 264 apart from various video processing features The new Processor Graphics Video engine adds support for processing features such as frame rate conversion image stabilization and gamut conversion Datasheet Volume 1 Interfaces 2 4 1 4 2 4 1 4 1 2 4 1 4 2 intel The Display Engine fetches the raw data from the memory puts the data into a stream converts the data into raw pixels organizes pixels into images blends different planes into a single image encodes the data and sends the data out to the display device 2D Engine The Display Engine executes its functions with the help of three main functional blocks Planes Pipes and Ports except for eDP The Planes and Pipes are in the processor while the Ports reside in the PCH Intel FDI connects the display engine in the processor with the Ports in the PCH The 2D Engine adds a new display pipe C that enables support for three s
153. gement 4 2 4 5 Core C7 State Note The terms Core C6 state and Core C7 state defines the same individual core power state In both cases the processor cores that request either C6 or C7 will enter the C6 state Individual threads of a core can enter the C7 state by initiating a P_LVL4 I O read to the P_BLK or by an MWAIT C7 instruction The core C7 state exhibits the same behavior as the core C6 state unless the core is the last one in the package to enter the C7 state If it is that core is responsible for flushing L3 cache ways The processor supports the C7s substate When an MWAIT C7 command is issued with a C7s sub state hint the entire L3 cache is flushed one step as opposed to flushing the L3 cache in multiple steps 4 2 4 6 C State Auto Demotion In general deeper C states such as C6 or C7 have long latencies and have higher energy entry exit costs The resulting performance and energy penalties become significant when the entry exit frequency of a deeper C state is high Therefore incorrect or inefficient usage of deeper C states have a negative impact on battery life To increase residency and improve battery life in deeper C states the processor supports C state auto demotion There are two C State auto demotion options e C7 C6 to C3 e C7 C6 C3 To C1 The decision to demote a core from C6 C7 to C3 or C3 C6 C7 to C1 is based on each core s immediate residency history Upon each core C6 C7 request the core C sta
154. h bits 55 15 46 32 indiam Turbo long duration time window urpo lime n Parameter POWER LIMIT 1 TIME in 0 001 1 64 S 10 11 package TURBO POWER LIMIT MSR 0610h bits 14 23 17 Long duration Turbo power limit 10 12 Quad Core Long P POWER LIMIT 1 in a SV 45W package TURBO_POWER_LIMIT MSR 0610h bits 38 a a d m 14 0 Short duration Turbo power limit Short P POWER LIMIT 2 in 36 1 25X 72 N A w 10 14 package TURBO_POWER_LIMIT MSR 0610h bits 45 N 15 20 46 32 Beete Turbo long duration time window urbo lime n Parameter POWER LIMIT 1 TIME in 0 001 1 64 S 10 11 package TURBO POWER LIMIT MSR 0610h bits 14 23 17 Quad Core Long duration Turbo power limit 10 12 and Long P POWER_LIMIT_1 in GE 24 35 48 N A w Dual Core package TURBO_POWER_LIMIT MSR 0610h bits SIN de d SV 35 W 14 0 Short duration Turbo power limit Short P POWER LIMIT 2 in 24 1 25X 56 N A w 10 14 package TURBO POWER LIMIT MSR 0610h bits 35 SES 15 20 46 32 best Turbo long duration time window urbo lime d P t POWER LIMIT 1 TIME in 0 001 1 32 S 10 11 package TURBO POWER LIMIT MSR 0610h bits 14 23 17 Long duration Turbo power limit TET Dual Core Long P POWER_LIMIT_1 in 14 0 17 24 N A w 13 14 Ultra package TURBO_POWER_LIMIT MSR 0610h bits N 50 14 0 Short duration Turbo power limit 10 14 Short P POWER_LIMIT_2 in 0 1 25X 44 N A W PN package
155. he PCH over the Intel Flexible Display Interface Intel FDI Display Ports The display ports consist of output logic and pins that transmit the display data to the associated encoding logic and send the data to the display device that is LVDS HDMI DVI SDVO and so on All display interfaces connecting external displays are now repartitioned and driven from the PCH with the exception of the eDP DisplayPort Refer to the PCH datasheet for more details on display port support Embedded DisplayPort eDP The Processor Graphics supports the Embedded Display Port eDP interface intended for display devices that are integrated into the system such as laptop LCD panel DisplayPort consolidates internal and external connection methods to reduce device complexity support cross industry applications and provide performance scalability The eDP interface supports link speeds of 1 62 Gbps and 2 7 Gbps on 1 2 or 4 data lanes The eDP supports 0 5 SSC and non SSC clock settings eDP on the processor is compliant with VESA DP specification 1 1a except the electrical parameters that appears in chapter 7 eDP DC Specification tables eDP interface supports Alternate Scrambler Seed Reset ASSR for eDP display authentication thereby enabling secure transfer of protected content over the cable to sink device Intel Flexible Display Interface The Intel Flexible Display Interface Intel FDI is a proprietary link for carrying display traffic f
156. he platform to the memory controller using PECI If no physical thermal sensor is available the memory controller can estimate the temperature based on memory activity Memory thermal throttling that is initiated with no direct temperature reading is known as Open Loop Thermal Throttling OLTT The processor features the Virtual Temperature Sensor VTS for OLTT Platform Environment Control Interface PECI The Platform Environment Control Interface PECI is a one wire interface that provides a communication channel between Intel processor and chipset components to external monitoring devices The processor implements a PECI interface to allow communication of processor thermal information to other devices on the platform The processor provides a digital thermal sensor DTS for fan speed control The DTS is calibrated at the factory to provide a digital representation of relative processor temperature Averaged DTS values are read using the PECI interface The PECI physical layer is a self clocked one wire bus that begins each bit with a driven rising edge from an idle level near zero volts The duration of the signal driven high depends on whether the bit value is a Logic O or Logic 1 PECI also includes variable data transfer rate established with every message The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components Bus speed er
157. i iet is 45 3 7 intel 64 Architecture x2APTC acia aX rrr dado o c etn AN i e t 45 3 8 Supervisor Mode Execution Protection SMEP sssssssssssseee mme 46 3 9 Power Aware Interrupt Routing DAIR eee eee ARALL LARA EA REAL emen nnn 46 Power Management AA 47 4 1 ACPI States Supported YR renda ene an une ni RR e RR ANY ERE OFO AAA Uo dad SES 48 4 1 1 System States acid iia 48 4 1 2 Processor Core Package Idle Gates 48 4 1 3 Integrated Memory Controller Gtates A A ARAE Y mme 48 4 1 4 PCIBxpress Link States See ASSEN ink vacant ikea e E Pad a cn BEE 49 4 1 5 DMLStateS itin eie Ladd ERES OC RN e cR RE EE Od Six DN IZNiF AEN PUES 49 4 1 6 Processor Graphics Controller States s sse 49 4 1 7 Interface State Combinations ssssssssssssssssss enne eee 49 4 2 Processor Core Power Management 50 4 2 1 Enhanced Intel SpeedStep Technology cs 50 4 2 2 Low Power Idle States sne piceno snn NES ieu Ew NENNEN e gege 51 4 2 3 Requesting Low Power Idle States sssssssssssssss nemen 52 4 2 4 Core Eeer E 53 ALZA Core CO State oot A ae nd cue 53 4 2 4 2 Core CI CIE State iun iu iei d oix dw AERE ES Eee Fa eA ERUC SERO E 53 4 2 4 3 Core C3 State ient eene Ee ut eniro fies Feb FRE ER RUN YO RR Ri ge 53 Datasheet Volume 1 4 2 44 COTO CO State eege aaa 53 4 2 4 5 Core C7 Statuii ege NR HY AREA AU AGER UN Cl nn NEWN Yn Gun RR GN 54 4 2 4 6 C State Auto Dem
158. ial for software conflicts e More secure The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system Datasheet Volume 1 39 m L Technologies 3 1 2 Intel VT x Features The processor core supports the following Intel VT x features e Extended Page Tables EPT EPT is hardware assisted page table virtualization It eliminates VM exits from guest operating system to the VMM for shadow page table maintenance e Virtual Processor IDs VPID Ability to assign a VM ID to tag processor core hardware structures such as TLBs This avoids flushes on VM transitions to give a lower cost VM transition time and an overall reduction in virtualization overhead e Guest Preemption Timer Mechanism for a VMM to preempt the execution of a guest operating system after an amount of time specified by the VMM The VMM sets a timer value before entering a guest The feature aids VMM developers in flexibility and Quality of Service QoS guarantees e Descriptor Table Exiting Descriptor table exiting allows a VMM to protect a guest operating system from internal malicious software based attack by preventing relocation of key system data structures like IDT interrupt descriptor table GDT global descriptor table LDT local descriptor table and TSS task segment selector A VMM using this feature can
159. ignal margins PCI Express Interface This section describes the PCI Express interface capabilities of the processor See the PCI Express Base Specification for details of PCI Express The processor has one PCI Express controller that can support one external x16 PCI Express Graphics Device The primary PCI Express Graphics port is referred to as PEG 0 PCI Express Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers may operate unchanged The PCI Express configuration uses standard mechanisms as defined in the PCI Plug and Play specification The processor external graphics ports support Gen 3 speed as well At 8 GT s Gen 3 operation results in twice as much bandwidth per lane as compared to Gen 2 operation The 16 lane PCI Express graphics port can operate at either 2 5 GT s 5 GT s or 8 GT s PCI Express Gen 3 uses a 128 130b encoding scheme eliminating nearly all of the overhead of the 8b 10b encoding scheme used in Gen 1 and Gen 2 operation The PCI Express architecture is specified in three layers Transaction Layer Data Link Layer and Physical Layer The partitioning in the component is not necessarily along these same boundaries Refer to Figure 2 2 for the PCI Express layering diagram PCI Express Layering Diagram Transaction Transaction Data Link Data Link Physical Physical Logical Sub block Logical Sub block
160. ility of generating interrupts using the core s local APIC Refer to the Inte 64 and IA 32 Architectures Software Developer s Manuals for specific register and programming details Digital Thermal Sensor Accuracy Taccuracy The error associated with DTS measurement will not exceed 5 C at Tj max The DTS measurement within the entire operating range will meet a 5 C accuracy Fan Speed Control with Digital Thermal Sensor Digital Thermal Sensor based fan speed control Tran is a recommended feature to achieve optimal thermal performance At the Tray temperature Intel recommends full cooling capability well before the DTS reading reaches Tj max An example of this would be TFAN Tj max 10 C PROCHOT Signal PROCHOT processor hot is asserted when the processor core temperature has reached its maximum operating temperature T max See Figure 5 2 Frequency and Voltage Ordering on page 75 for a timing diagram of the PROCHOT signal assertion relative to the Adaptive Thermal Response Only a single PROCHOT pin exists at a package level When any core arrives at the TCC activation point the PROCHOT signal will be asserted PROCHOT assertion policies are independent of Adaptive Thermal Monitor enabling Bus snooping and interrupt latching are active while the TCC is active For the package C7 state PROCHOT may de assert for the duration of the C7 state residency even if the processor enters the idle state operat
161. imultaneous and concurrent display configurations Processor Graphics Registers The 2D registers consists of original VGA registers and others to support graphics modes that have color depths resolutions and hardware acceleration features that go beyond the original VGA standard Logical 128 Bit Fixed BLT and 256 Fill Engine This BLT engine accelerates the GUI of Microsoft Windows operating systems The 128 bit BLT engine provides hardware acceleration of block transfers of pixel data for many common Windows operations The BLT engine can be used for the following e Move rectangular blocks of data between memory locations e Data alignment e To perform logical operations raster ops The rectangular block of data does not change as it is transferred between memory locations The allowable memory transfers are between cacheable system memory and frame buffer memory frame buffer memory and frame buffer memory and within system memory Data to be transferred can consist of regions of memory patterns or solid color fills A pattern is always 8 x 8 pixels wide and may be 8 16 or 32 bits per pixel The BLT engine expands monochrome data into a color depth of 8 16 or 32 bits BLTs can be either opaque or transparent Opaque transfers move the data specified to the destination Transparent transfers compare destination color to source color and write according to the mode of transparency selected Data is horizontally and vertically a
162. ing at the TCC activation temperature The PECI interface is fully operational during all C states and it is expected that the platform continues to manage processor package thermals even during idle states by regularly polling for thermal data over PECI Bi Directional PROCHOT By default the PROCHOT signal is defined as an output only However the signal may be configured as bi directional When configured as a bi directional signal PROCHOT can be used for thermally protecting other platform components should they overheat as well When PROCHOT is driven by an external device e the package will immediately transition to the minimum operation points voltage and frequency supported by the processor and graphics cores This is contrary to the internally generated Adaptive Thermal Monitor response e Clock modulation is not activated Datasheet Volume 1 77 m L Thermal Management Note 5 6 3 2 5 6 3 3 5 6 3 4 78 The TCC will remain active until the system de asserts PROCHOT The processor can be configured to generate an interrupt upon assertion and de assertion of the PROCHOT signal Toggling PROCHOT more than once in 1 5 ms period will result in constant Pn state of the processor Voltage Regulator Protection versus PROCHOT PROCHOT may be used for thermal protection of voltage regulators VR System designers can create a circuit to monitor the VR temperature and activate the TCC when the temper
163. intercept by a VM exit attempts to relocate these data structures and prevent them from being tampered by malicious software 3 1 3 Intel VT d Objectives The key Intel VT d objectives are domain based isolation and hardware based virtualization A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated Virtualization allows for the creation of one or more partitions on a single system This could be multiple partitions in the same operating system or there can be multiple operating system instances running on the same system offering benefits such as system consolidation legacy migration activity partitioning or security 3 1 4 Intel VT d Features The processor supports the following Intel VT d features Memory controller and processor graphics comply with Intel VT d 1 2 specification Two VT d DMA remap engines iGFX DMA remap engine DMI PEG Support for root entry context entry and default context 39 bit guest physical address and host physical address widths Support for 4K page sizes only 40 Datasheet Volume 1 Technologies Note 3 1 5 3 2 e Support for register based fault recording only for single entry only and support for MSI interrupts for faults e Support for both leaf and non leaf caching e Support for boot protection of default page table e Support for non caching of invalid page table entries e Support for
164. is document the Intel 6 7 Series Chipset Platform Controller Hub may also be referred to as PCH Some processor features are not available on all platforms Refer to the processor specification update for details The term MBL refers to mobile platforms Datasheet Volume 1 11 D L Introduction Figure 1 1 Mobile Processor Platform PCI Express 3 0 q A DDR3 DDR3L DDR3L RS 1 x16 or 2x8 Discrete Intel Processor Embedded Display Po PECI Intel Flexible Display Interface BM Serial ATA ntel HD Audic Intel y Digital Display x 3 Management E Engine m LVDS Flat Panel Analog CRT Intel 6 7 Series Chipset Families q J SMBUS 2 0 Controller Link 1 8 PCI Express 2 0 x1 Ports 5 GT s JE GPIO Note 1 USB 3 0 is supported on the Intel 7 Series Chipset family only 12 Datasheet Volume 1 Introduction intel 1 1 Processor Feature Details Four or two execution cores A 32 KB instruction and 32 KB data first level cache L1 for each core A 256 KB shared instruction data second level cache L2 for each core Up to 8 MB shared instruction data third level cache L3 shared among all cores 1 1 1 Supported Technologies Intel Virtualization Technology for Directed I O Intel VT d Intel Virtualization Technology Intel VT x Intel Active Management Technology 8 0
165. ital Thermal Sensor irre exer pene DW Re nu Cyd PER ee 76 5 6 2 1 Digital Thermal Sensor Accuracy Taccuracy 77 5 6 2 2 Fan Speed Control with Digital Thermal Sensor ssss 77 56 3 PROCHOT4F Signal cede enne pu entree dE Deka NOx CR ENDE NX E EE dee UN R 77 5 6 3 1 Bi Directional PROCHOTA ENNER REENEN ee ern e nena nd auk YRR Yd 77 5 6 3 2 Voltage Regulator Protection versus PROCHOTR eee ee ea ees 78 5 6 3 3 Thermal Solution Design and PROCHOT Behavior 78 5 6 3 4 Low Power States and PROCHOT Behavior eceeeeeeeeeeeeeees 78 5 6 3 5 THERMTRIP Signal 79 5 6 3 6 Critical Temperature Detection sssssseseenene nnne 79 Datasheet Volume 1 5 56 4 On Demand Mode iei ten cies dei 79 5 6 4 1 MSR Based On Demand Mode eee eee ee emen 79 5 6 4 2 I O Emulation Based On Demand Mode cccceeceeeeeeeeeneeaeeaeeaes 79 5 6 5 Memory Thermal Management 80 5 6 6 Platform Environment Control Interface PECI c sceseeeeeeeeeeeeeeeee Y Y uan 80 6 Signal Descriptlon uei eiri Ryn rax A AE GEESS FAX RR UE AA Kun RE me DIE e RU EA CR 81 6 1 System Memory Interface ciem os 82 6 2 Memory Reference and Compensation ssssssssssse enne nene 84 6 3 Reset and Miscellaneous Signals cc NNN SKS KEE ER ENER nn nn rana E 84 6 4 PCI Express based Interface Gionals ee ee eee eee eens eee nemen emen 85 6 5 Embedded DisplayPort
166. ital Thermal Sensor DTS that reports a relative die temperature as an offset from Thermal Control Circuit TCC activation temperature Temperature sensors located throughout the die are implemented as analog to digital converters calibrated at the factory PECI provides an interface for external devices to read the DTS temperature for thermal management and fan speed control PECI Bus Architecture The PECI architecture based on wired OR bus which the clients as the processor PECI can pull up high with strong drive The idle state on the bus is near zero Figure 7 1 demonstrates PECI design and connectivity while the host originator can be 3rd party PECI host and one of the PECI client is the processor PECI device Example for PECI Host Clients Connection Vtt Q1 nix LE S lt 10pF Node Host Originator PECI Client Additional PECI Clients Datasheet Volume 1 Electrical Specifications 7 10 2 Table 7 15 7 10 3 Figure 7 2 Datasheet Volume 1 intel PECI DC Characteristics The PECI interface operates at a nominal voltage set by Vccro The set of DC electrical specifications shown in Table 7 15 is used with devices normally operating from a Vccjo interface supply Vccro nominal levels will vary between processor families All PECI devices will operate at the Vccro level determined by the processor installed in the system For specific nominal Vccro levels refer to Table 7 6
167. ive Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines The Adaptive Thermal Monitor is not intended as a mechanism to maintain processor TDP The system design should provide a thermal solution that can maintain TDP within its intended usage range Adaptive Thermal Monitor protection is always enabled TCC Activation Offset TCC Activation Offset can be used to activate the TCC at temperatures lower than T3 max It is the preferred thermal protection mechanism for Intel Turbo Boost operation since ACPI passive throttling states will pull the processor out of Turbo mode operation when triggered An offset in degrees Celsius can b e written to TEMPERATURE_TARGET 1A2h MSR bits 27 24 This value will be subtracted from the value found in bits 23 16 The default offset is 0 C where throttling will occur at T max The offset should be set lower than any other protection such as ACPI _PSV trip points Frequency Voltage Control Upon TCC activation the processor core attempts to dynamically reduce processor core power by lowering the frequency and voltage operating point The operating points are automatically calculated by the processor core itself and do not require the BIOS to program them as with previous generations of Intel processors The processor core will scale the operating points such that e The voltage will be optimized according to the temperature the core bus ratio
168. ization The processor implements extensive support for power management on the SDRAM interface There are four SDRAM operations associated with the Clock Enable CKE signals that the SDRAM controller supports The processor drives four CKE pins to perform these operations The CKE is one means of power saving When CKE is off the internal DDR clock is disabled and the DDR power is reduced The power saving differs according to the selected mode and the DDR type used For more information refer to the IDD table in the DDR specificaiton The DDR defines 3 levels of power down that differ in power saving and in wakeup time 1 Active power down APD This mode is entered if there are open pages when de asserting CKE In this mode the open pages are retained Power saving in this mode is the lowest Power consumption of DDR is defined by IDD3P Exiting this mode is defined by tXP small number of cycles 2 Precharged power down PPD This mode is entered if all banks in DDR are precharged when de asserting CKE Power saving in this mode is intermediate better than APD but less than DLL off Power consumption is defined by IDD2P1 Exiting this mode is defined by tXP The difference relative to APD mode is that when waking up in PPD mode all page buffers are empty 3 DLL off In this mode the data in DLLs on DDR are off Power saving in this mode is the best among all power modes Power consumption is defined by IDD2P1 Exiting this mod
169. l Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball 4 Buffer Type Dir PEG_TX 6 K15 PCIe O RSVD BE26 PEG_TX 7 F17 PCIe O RSVD BE24 PEG_TX 8 F14 PCIe O RSVD BE22 PEG_TX 9 A15 PCIe O SA_DIMM_VREFDQ BE7 Analog O PEG_TX 10 J14 PCIe O RSVD BD26 PEG_TX 11 H13 PCIe O RSVD BD25 PEG_TX 12 M10 PCIe O RSVD BD22 PEG_TX 13 F10 PCIe O RSVD BD21 PEG_TX 14 D9 PCIe O RSVD BB21 PEG_TX 15 J4 PCIe O RSVD BB19 PEG TX 0 F22 PCIe O RSVD BA22 PEG_TX 1 A23 PCIe O RSVD BA19 PEG_TX 2 D24 PCIe O RSVD AY22 PEG_TX 3 E21 PCIe O RSVD AY21 PEG_TX 4 G19 PCIe O RSVD AV19 PEG_TX 5 B18 PCIe O RSVD AU21 PEG_TX 6 K17 PCIe O RSVD AU19 PEG_TX 7 G17 PCIe O RSVD AT49 PEG_TX 8 E14 PCIe O RSVD AT21 PEG_TX 9 C15 PCIe O RSVD AM15 PEG_TX 10 K13 PCIe O RSVD AM14 PEG_TX 11 G13 PCIe O RSVD AH2 PEG_TX 12 K10 PCIe O RSVD AG13 PEG_TX 13 G10 PCIe O RSVD W14 PEG_TX 14 D8 PCIe O RSVD U14 PEG TX 15 K4 PCIe O RSVD P13 PM_SYNC C48 Asynch CMOS I RSVD N50 PRDY N53 Asynch CMOS O RSVD N42 PREQ N55 Asynch CMOS I RSVD M14 PROC_DETECT C57 Analog RSVD M13 PROC_SELECT F49 N A RSVD L47 PROCHOT C45 Asynch CMOS 1 0 RSVD L45 RESET D44 Asynch CMOS I RSVD L42 RSVD BG26 RSVD K48 RSVD BG22 RSVD K24 SB_DIMM_VREFDQ BG7 Analog O RSVD H48 RSVD BF23 SA_BS 0 BD37 DDR3 O 144 Datasheet Volume 1 Processor Pin Signal and Package Information intel
170. l Protection Table 6 12 Error and Thermal Protection Signal Name Description Direction Buffer Type CATERR PECI Catastrophic Error This signal indicates that the system has experienced a catastrophic error and cannot continue to operate The processor will set this for non recoverable machine check errors or other unrecoverable internal errors On the processor CATERR is used for signaling the following types of errors Legacy MCERRs CATERR is asserted for 16 BCLKs Legacy IERRs CATERR remains asserted until warm or cold reset PECI Platform Environment Control Interface A serial sideband interface to the processor it is used primarily for thermal power and error management CMOS I O Asynchronous PROCHOT Processor Hot PROCHOT goes active when the processor temperature monitoring sensor s detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled This signal can also be driven to the processor to activate the TCC CMOS Input Open Drain Output THERMTRIP Thermal Trip The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating temperature to ensure that there are no false trips The processor will stop all execution when the junction temperature exceeds approxim
171. ligned at the destination If the destination for the BLT overlaps with the source memory location the BLT engine specifies which area in memory to begin the BLT transfer Hardware is included for all 256 raster operations source pattern and destination defined by Microsoft including transparent BLT The BLT engine has instructions to invoke BLT and stretch BLT operations permitting software to set up instruction buffers and use batch processing The BLT engine can perform hardware clipping during BLTs Datasheet Volume 1 35 intel Interfaces 2 4 2 Figure 2 7 2 4 2 1 2 4 2 1 1 2 4 2 1 2 2 4 2 1 3 2 4 2 1 4 36 Processor Graphics Display The Processor Graphics controller display pipe can be broken down into three components e Display Planes e Display Pipes e Embedded DisplayPort and Intel FDI Processor Display Block Diagram VGA Transcoder eDP Bm m bi eDP eDP Tx side gt Mux y d m PipeA Panel e Transcoder Memory Hs Plane Fitting A gt FDIO xa eT Tx side Outside of Display Si PipeB Panel Transcoder Cross Engine Plane Fitting B Point Mux FDI 1 gt gt L x4 PipeC Panel Transcoder Tx side Li Plane Fitting C Display Planes A display plane is a single displayed surface in m
172. loLlOrn eoe seen eerie we FEN SEENEN SE AER Dn ds 54 4 2 5 Package C States ege ite gae irent e Ly aU YAR NEEN ENEE ELAN ROE ADNA Cn AER A RE Ra 54 4 2 5 1 Package CU i e ode eee cuida putare dre a dra ced MR RA REN 56 4 2 5 2 Package Cl CTE irse tees sunto aries gece te oe CW t Re e esr e Sege en d 56 4 2 5 3 Package C3 State i idee niente da ER XR ERR 56 4 2 5 4 Package C6 Station eene cie DR wea REDE MEER 56 4 2 5 5 Package C7 Static en Corby e eda Ex UR da DRY nad AA ARY HON DR 57 4 2 5 6 Dynamic L3 Cache Sizing einen ater a E ER REN RE 57 4 3 IMC Power Management 57 4 3 1 Disabling Unused System Memory Outputs ee 57 4 3 2 DRAM Power Management and Inttialtzation sse 58 4 3 2 1 Initialization Role Of CKE eret YRR NEE d RENE seed nana ra kun 59 4 3 2 2 Conditional Self Refresh ENER EEN NENNEN YRU ERYR UN na kun nmn ENEE NEEN 59 4 3 2 3 Dynamic Power Down Operation 60 4 3 2 4 DRAM I O Power Management 60 4 3 3 DDR Electrical Power Gating EPG YY RAA AL AL LARLL AELE EY YR eens 60 4 4 PCI Express Power Management 61 4 5 DMI Power Management au NEEN ER REN ARR denn khan AER E ENEE ENER RS ENER RENE ka ada REN ad ande is 61 4 6 Graphics Power Management ccococnnnconcocnoncnncnenenccnnnna rana rre a nr arca nena anni 61 4 6 1 Intel Rapid Memory Power Management RMPM also known as CxSR 61 4 6 2 Intel Graphics Performance Modulation Technology GPMT seeren 61 4 6 3 Gr
173. lot of opportunities to power down ranks even while running memory intensive applications savings may be significant up to a few Watts depending on DDR configuration This becomes more significant when each channel is populated with more ranks Selection of power modes should be according to power performance or thermal trade offs of a given system e When trying to achieve maximum performance and power or thermal consideration is a non issue use no power down e In a system that tries to minimize power consumption try to use the deepest power down mode possible DLL off or APD_DLLoff e In high performance systems with dense packaging that is tricky thermal design the power down mode should be considered in order to reduce the heating and avoid DDR throttling caused by the heating Control of the power mode through CRB BIOS BIOS selects by default no power down Another control is the idle timer expiration count This is set through PM PDWN config bits 7 0 MCHBAR 4CBO As this timer is set to a shorter time the IMC will have more opportunities to put DDR in power down The minimum recommended value for this register is 15 There is no BIOS hook to set this register Customers who choose to change the value of this register can do it by changing the BIOS For experiments this register can be modified in real time if BIOS did not lock the MC registers In APD APD PPD and APD DLLoff there is no point in setting the idle co
174. mp uei ii iN YR GRE RR NGR ER EES N E ENEE gd NR EE Ce 28 2 2 1 PCI Express Architecture Y iau Na Latein dk LONA isa dat a dek eae dE RE EE D 28 2 21 3hransaction ET EE 29 2 2 1 2 Data Link Layer i ea ence a setter FURRY a d EN 29 22 1 3 Physical Layer i sss au pena deua CANY tenn ated Dd Fa TUR ARRA YR 29 2 2 2 PCI Express Configuration Mechanisme 30 2 243 PCI Express Graphic ba cod 31 2 2 3 1 PCI Express Lanes Connection occocccccnconnnnnnnnnnnnnnnnnarenennnrnnananan 31 2 3 Direct Media Interface DMI RSR RR REN ENRNEK REN ER acacia narrada ER 2 3 1 DMI Error low iiis cese teen pee KEEN dE EEN ENEE NNN ES EES Ee a SE e 32 2 3 2 Processor PCH Compatibility Assumptions YARLL eee eeeaee es 32 Datasheet Volume 1 3 ntel 2 33 DML Link DOWN iia ni os 32 2 4 Processor Graphics Controller GT 32 2 4 1 3D and Video Engines for Graphics Processing ccocococononcnnnnnnnnnnnnnnnnnnnnnannnos 33 2 4 1 1 3D Engine Execution UNES rv ege EY Win Ex EEN her ni de ee 33 2 4 1 2 3D Pipeline a ii iic er cen rendir stands tua eR OY a eaa da eda sa XE RR ERR 34 2 4 1 3 Video Engine cerent deeg sa teen tke GR Reu EEN ga a sr E e FR 34 2 4 1 4 2D ENGINE iere tmr ri DR AN edere OR ko d ERR ax TENER dude 35 2 4 2 Processor Graphics Display ERNEIEREN ERR enn NENNEN NR NENNEN ERR RR REA RARE RA 36 2 4 2 1 Display Planes uasa renean YRRU da a DR RAT EN UR 36 2 4 2 2 Display EIDA i perio ba
175. mprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets Intel Virtualization Technology Intel VT x added hardware support in the processor to improve the virtualization performance and robustness Intel Virtualization Technology for Directed I O Intel VT d adds chipset hardware implementation to support and improve I O virtualization performance and robustness Intel VT x specifications and functional descriptions are included in the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B and is available at http www intel com products processor manuals index htm Other VT documents can be referenced at http www intel com technology virtualization index htm Intel VT x Objectives Intel VT x provides hardware acceleration for virtualization of IA platforms Virtual Machine Monitor VMM can use Intel VT x features to provide improved reliable virtualized platform By using Intel VT x a VMM is e Robust VMMs no longer need to use paravirtualization or binary translation This means that they will be able to run off the shelf operating systems and applications without any special steps e Enhanced Intel VT enables VMMs to run 64 bit guest operating systems on IA x86 processors e More reliable Due to the hardware support VMMs can now be smaller less complex and more efficient This improves reliability and availability and reduces the potent
176. mum sustained power from realistic applications TDP may be exceeded for short periods of time or if running a power virus workload The processor integrates multiple CPU and graphics cores on a single die This may result in differences in the power distribution across the die and must be considered when designing the thermal solution Intel Boost Technology allows processor cores and processor graphics cores to run faster than the baseline frequency It is invoked opportunistically and automatically as long as the processor is conforming to its temperature power delivery and current specification limits When Intel Turbo Boost Technology is enabled e Applications are expected to run closer to TDP more often as the processor will attempt to maximize performance by taking advantage of available TDP headroom in the processor package e The processor may exceed the TDP for short durations to utilize any available thermal capacitance within the thermal solution The duration and time of such operation can be limited by platform runtime configurable registers within the processor e Thermal solutions and platform cooling that are designed to less than thermal design guidance may experience thermal and performance issues since more applications will tend to run at or near the maximum power limit for significant periods of time Intel Turbo Boost Technology Power Monitoring When operating in the Turbo mode the processor will monitor its ow
177. n Name Pin 4 Buffer Type Dir VSS B15 GND VSS G17 GND VSS B17 GND VSS G20 GND VSS B19 GND VSS G23 GND VSS B2 GND VSS G26 GND VSS B22 GND VSS G29 GND VSS B3 GND VSS G32 GND VSS B5 GND VSS G35 GND VSS B7 GND VSS H1 GND VSS B8 GND VSS H10 GND VSS B9 GND VSS H13 GND VSS Ci GND VSS H15 GND VSS C10 GND VSS H18 GND VSS C23 GND VSS H2 GND VSS C25 GND VSS H21 GND VSS C27 GND VSS H24 GND VSS C28 GND VSS H27 GND VSS C31 GND VSS H3 GND VSS C34 GND VSS H30 GND VSS D17 GND VSS H33 GND VSS D20 GND VSS H4 GND VSS D26 GND VSS H5 GND VSS D29 GND VSS H6 GND VSS D32 GND VSS H7 GND VSS D35 GND VSS H8 GND VSS E1 GND VSS H9 GND VSS E10 GND VSS J31 GND VSS E13 GND VSS J34 GND VSS E15 GND VSS K26 GND VSS E18 GND VSS K29 GND VSS E2 GND VSS K32 GND VSS E21 GND VSS K35 GND VSS E24 GND VSS L1 GND VSS E27 GND VSS L2 GND VSS E3 GND VSS L27 GND VSS E30 GND VSS L3 GND VSS E4 GND VSS L30 GND VSS E5 GND VSS L33 GND VSS E6 GND VSS L4 GND VSS E7 GND VSS L5 GND VSS E8 GND VSS L6 GND VSS E9 GND VSS L8 GND VSS F19 GND VSS L9 GND VSS F22 GND VSS M34 GND VSS F29 GND VSS N26 GND VSS F31 GND VSS N27 GND VSS F34 GND VSS N28 GND VSS G11 GND VSS N29 GND Datasheet Volume 1 119 intel Processor Pin Signal and Package Information Table 8 1 rPGA988B Processor Pin List Table 8 1 rPGA988B Processor Pin List by Pin Name Continued by Pin Name Conti
178. n Typ Max Unit Note XE 0 8 1 35 E Range ES SV QC 35W 0 8 1 35 i5 HFM VID Includes Turbo Mode SV QC 45W 0 8 1 35 V 68 Operation SV DC 0 8 1 35 Ultra DC 0 65 1 2 XE 0 65 0 95 SV QC 35W 0 65 0 95 FREE VID Range for lowest SV QC 45W 0 65 E 0 95 v 1 2 8 requency Mode SV DC 0 65 0 95 Ultra DC 0 65 0 9 Vcc Vcc for processor core 0 3 1 52 V ET XE 97 5 SV QC 45W 94 ltem pm Processor Core SV QC 35W _ I 53 A 4 6 8 SV DC 53 Ultra DC 33 XE TDP nominal 69 5 XE TDP Up 75 0 XE TDP Down 54 6 SV QC 45W 54 6 Icc roc Thermal Design Icc SV QC 35W 32 0 A 8 s SV DC 32 0 Ultra TDP nominal 15 8 Ultra TDP Up 20 0 Ultra TDP Down 10 5 XE 32 0 SV QC 45W 32 0 Icc_LFM Icc at LFM SV QC 35W _ 28 0 A 5 SV DC 25 0 Ultra DC 12 5 Datasheet Volume 1 99 intel Electrical Specifications Table 7 5 Processor Core Vcc Active and Idle Mode DC Voltage and Current Specifications Sheet 2 of 2 Symbol Parameter Segment Min Typ Max Unit Note XE 5 5 SV QC 45W 5 0 Icc ce c7 Icc at C6 C7 Idle state SV QC 35W 5 0 A 10 SV DC 3 0 Ultra DC 2 5 PSO 15 TOLycc Voltage Tolerance PS1 12 mV 7 9 PS2 PS3 11 5 PSO amp Icc gt TDC 30 B i as PSO amp Icc lt TDC 3096 5 TM Ripple Ripple Tolerance mV 7 9 PS1 13 PS2 7 5 18 5 PS3 7 5 27 5 VR Step VID resolution 5 mV XE TDP nom
179. n power and adjust the Turbo frequency to maintain the average power within limits over a thermally significant time period The package processor core and graphic core powers are estimated using architectural counters and do not rely on any input from the platform Datasheet Volume 1 65 m L Thermal Management Note 5 3 5 3 1 66 The following considerations and limitations apply to the Intel Turbo Boost Technology power monitoring e Internal power monitoring is calibrated per processor family and is not conducted on a part by part basis Therefore some difference between actual and reported power may be observed e Power monitoring is calibrated with a variety of common realistic workloads near Tj Max Workloads with power characteristics markedly different from those used during the calibration process or lower temperatures may result in increased differences between actual and estimated power e In the event an uncharacterized workload or power virus application were to result in exceeding programmed power limits the processor Thermal Control Circuitry TCC will protect the processor when properly enabled Adaptive Thermal Monitor must be enabled for the processor to remain within specification It is recommended to use TCC Activation Offset to optimize thermal control of the processor while in Turbo See Section 5 6 1 1 for more information Intel Turbo Boost Technology Power Control Illustration of
180. nals eis rrr nt ree gren a d a RE ia 95 TO Signal GroUPS mir A AE Aa AA a a a 96 74 7 Test Access Port TAP Connection rene ex ein e DR A 98 7 8 Component Storage Condition Specifications Prior to Board Attach 98 79 EPI eeu MET II TL LOUER 99 7 9 1 Voltage and Current Specifications esesssssssssssese eee nnn 99 7 10 Platform Environmental Control Interface PECI DC SpecificationS 106 7 10 1 PECI Bus Architecture acie entere ente next ca aa inu LR n A DYNA UE 106 7 10 2 PECI DC Characteristics iris visiteur ee GR ar 107 7 10 3 Input Device Hysteresis ies iier tente nnb YND YND RA DRENAU NEEN NN REN 107 8 Processor Pin Signal and Package Information 109 8 1 Processor Pin AssignmentS eie EE REREN NEE nh ENER SE ADRA RAO FAU FAU DRE a RR RA ROD Yna 109 8 2 Package Mechanical Information 156 9 DDR Data Swizzling erat a Ze e Rx CE dE Cyw dE ada EXER dee 165 6 Datasheet Volume 1 Figures 1 1 Mobile Processor Blattorm 2 VdEVER ENER KEEN ca RR RH ARR NEE SEN chides sete lee a a PER Ra s 12 1 2 Mobile Processor Compatibility Diagram sss mene 19 2 1 Intel Flex Memory Technology Operation 26 2 2 PCLExpress Layering DiagrafTle awe cine tnra RR RANU A iaa 28 2 3 Packet Flow Through the Layers seseisseeeee sean nnn nennen hahaha ENER ENNEN Ra uo dun un 29 2 4 PCI Express Related Register Structures in the Pr
181. nch CMOS I PEG RX 12 E8 PCle I FDIO_FSYNC AC8 CMOS I PEG_RX 13 G10 PCIe I FDIO LSYNC AB7 CMOS I PEG_RX 14 J8 PCIe I FDIO_TX 0 v7 FDI O PEG_RX 15 F7 PCIe I FDIO_TX 1 ws FDI O PEG_RX 0 G22 PCIe I FDIO_TX 2 AA8 FDI O PEG_RX 1 K23 PCIe I FDIO_TX 3 AC10 FDI O PEG_RX 2 K21 PCIe I FDIO TX 0 W6 FDI O PEG_RX 3 F19 PCIe I FDIO TX 1 W10 FDI O PEG_RX 4 K19 PCIe I FDIO TX 2 Y9 FDI O PEG_RX 5 H17 PCIe I FDIO TX 3 AA10 FDI O PEG_RX 6 K15 PCIe I FDI1_FSYNC AA2 CMOS I PEG_RX 7 G14 PCIe I FDI1_LSYNC AB3 CMOS I PEG RX 8 J16 PCIe I FDI1_TX 0 U4 FDI O PEG_RX 9 K13 PCIe I FDI1_TX 1 w2 FDI O PEG_RX 10 Fil PCIe I FDI1_TX 2 vi FDI O PEG_RX 11 K11 PCIe I FDI1_TX 3 Y5 FDI O PEG_RX 12 F9 PCIe I FDI1 TX 0 U2 FDI O PEG_RX 13 H9 PCIe I FDI1_TX 1 w4 FDI O PEG_RX 14 H7 PCIe I FDI1_TX 2 v3 FDI O PEG_RX 15 G6 PCIe I FDI1_TX 3 AA6 FDI O PEG_TX 0 A22 PCIe O PECI F53 Asynch 1 0 PEG_TX 1 B23 PCIe O PEG_ICOMPI G2 Analog I PEG_TX 2 C18 PCIe O PEG_ICOMPO H1 Analog I PEG_TX 3 D21 PCIe O PEG_RCOMPO F3 Analog I PEG_TX 4 B19 PCIe O PEG_RX 0 F23 PCIe I PEG TX4 5 E20 PCIe O 124 Datasheet Volume 1 Processor Pin Signal and Package Information intel Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball
182. nd may be left un connected Arbitrary connection of these signals to Vcc Vccior VDDQ VCCPLL Vccsa VaxG Vss Or to any other signal including each other may result in component malfunction or incompatibility with future processors See Chapter 8 for a pin listing of the processor and the location of all reserved signals For reliable operation always connect unused inputs or bi directional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground Vss Unused outputs maybe left unconnected however this may interfere with some Test Access Port TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bi directional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Datasheet Volume 1 95 Table 7 3 96 Signal Groups Signals are grouped by buffer type and similar characteristics as listed in Table 7 3 The buffer type indicates which signaling technology and specifications apply to the signals All the differential signals and selected DDR3 and Control Sideband signals have On Die Termination ODT resistors There are some signals that do not have ODT and need to be terminated on the board Signal Groups Sheet 1 of 2 Electrical Specifications Signal Group Type Signals System Reference Clock Differential CMOS Input POLK BELKA
183. nd out of self refresh during STR e Signals 3 2 are used only for 2 DPC system Chip Select 1 per rank These signals are used to select particular S S 13 0 SDRAM components during the active state There is one Chip Select O B_CS 3 0 for each SDRAM rank DDR3 Bits 3 2 are used only for 2 DPC system On Die Termination Active Termination Control O SB_ODT 3 0 3 0 Bits 3 2 are used only for 2 DPC system DDR3 Datasheet Volume 1 83 intel 6 2 Table 6 4 6 3 Table 6 5 84 Memory Reference and Compensation Memory Reference and Compensation Signal Description i ES Direction Signal Name Description Buffer Type SM RCOMP 2 0 System Memory Impedance Compensation Ce DDR3 DDR3L DDR3L RS Reference Voltage This signal is I SM_VREF used as a reference voltage to the DDR3 DDR3L DDR3L RS A controller Memory Channel A B DIMM DQ Voltage Reference These output pins are connected to the DIMMs and are programmed to SA_DIMM_VREFDQ have a reference voltage with optimized margin o SB_DIMM_VREFDQ The nominal source impedance for these pins is 150 Q A The step size is 7 7 mV for DDR3 with no load and 6 99 mV for DDR3L DDR3L RS with no load Reset and Miscellaneous Signals Reset and Miscellaneous Signals Signal Name Direction Description Buffer Type Configuration Signals The CFG signals have a default value of 1 if not terminated on the board e CFG 1 0 R
184. nd the processor has been granted permission by the platform e The platform has not granted a package C7 request but has allowed a C6 package state In package C6 state all cores have saved their architectural state and have had their core voltages reduced to zero volts The L3 shared cache is still powered and snoopable in this state The processor remains in package C6 state as long as any part of the L3 cache is active Datasheet Volume 1 Power Management intel 4 2 5 5 4 2 5 6 4 3 4 3 1 Package C7 State The processor enters the package C7 low power state when all cores are in the C7 state and the L3 cache is completely flushed The last core to enter the C7 state begins to shrink the L3 cache by N ways until the entire L3 cache has been emptied This allows further power savings Core break events are handled the same way as in package C3 or C6 However snoops are not sent to the processor in package C7 state because the platform by granting the package C7 state has acknowledged that the processor possesses no snoopable information This allows the processor to remain in this low power state and maximize its power savings Upon exit of the package C7 state the L3 cache is not immediately re enabled It re enables once the processor has stayed out of the C6 or C7 state for a preset amount of time Power is saved since this prevents the L3 cache from being re populated only to be immediately flushed again Dynami
185. ng DDR3 1600 MT s 13 1 2 2 Introduction Processor on die Reference Voltage VREF generation for both DDR3 Read RDVREF and Write VREFDQ 1Gb 2Gb and 4Gb DDR3 DRAM device technologies are supported Using 4Gb DRAM device technologies the largest memory capacity possible is 32 GB assuming Dual Channel Mode with four x8 dual ranked DIMM memory configuration Up to 64 simultaneous open pages 32 per channel assuming 8 ranks of 8 bank devices Command launch modes of 1N 2N On Die Termination ODT Asynchronous ODT Intel Fast Memory Access Intel FMA Just in Time Command Scheduling Command Overlap Out of Order Scheduling PCI Express The PCI Express lanes PEG 15 0 TX and RX are fully compliant to the PCT Express Base Specification Revision 3 0 including support for 8 0 GT s transfer speeds PCI Express supported configurations in mobile products Configuration Organization Mobile 1x8 1 Graphics I O 2x4 2 2x8 Graphics I O 3 1x16 Graphics I O The port may negotiate down to narrower widths Support for x16 x8 x4 x2 x1 widths for a single PCI Express mode 2 5 GT s 5 0 GT s and 8 0 GT s PCI Express frequencies are supported Geni Raw bit rate on the data pins Gen 2 Raw bit rate on the data pins of 5 0 GT s resulting in a real bandwidth per pair of 500 MB s given the 8b 10b encoding used to transmit data across this interface This also does not account for pa
186. ntel Flexible Display Interface Sheet 2 of 2 Signal Name Description Direction Buffer Type FDI1_FSYNC 1 Intel Flexible Display Interface Frame Sync Pipe B and C I CMOS i i i Pi FDI1_LSYNC 1 Intel Flexible Display Interface Line Sync Pipe B and C I CMOS Intel Flexible Display Interface Hot Plug Interrupt I FDI_INT Asynchronous CMOS Direct Media Interface DMI DMI Processor to PCH Serial Interface Direction Signal Name Description Buffer Type DMI_RX 3 0 DMI Input from PCH Direct Media Interface receive I DMI_RX 3 0 differential pair DMI DMI_TX 3 0 DMI Output to PCH Direct Media Interface transmit O DMI_TX 3 0 differential pair DMI Phase Lock Loop PLL Signals PLL Signals Direction Signal Name Description Buffer Type BCLK Differential bus clock input to the processor I BCLK Diff Clk DPLL_REF_CLK Embedded Display Port PLL Differential Clock In 120 MHz I DPLL_REF_CLK Diff Clk Test Access Points TAP Signals TAP Signals Sheet 1 of 2 Direction Signal Name Description Buffer Type Breakpoint and Performance Monitor Signals These signals BPM 7 0 are outputs from the processor that indicate the status of LO i breakpoints and programmable counters used for monitoring CMOS processor performance BCLK_ITP These signals are connected in parallel to the top side debug I BCL
187. nued Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VSS N30 GND VSS_VAL_SENSE AH33 Analog O VSS N31 GND VSSAXG_SENSE AK34 Analog O VSS N32 GND VSSAXG_VAL_SENSE AH31 Analog O VSS N33 GND VSS N34 GND VSS N35 GND VSS P2 GND VSS P3 GND VSS P5 GND VSS P6 GND VSS P8 GND VSS P9 GND VSS T26 GND VSS T27 GND VSS T28 GND VSS T29 GND VSS T30 GND VSS T31 GND VSS T32 GND VSS T33 GND VSS T34 GND VSS T35 GND VSS U2 GND VSS U3 GND VSS US GND VSS U6 GND VSS U8 GND VSS U9 GND VSS W26 GND VSS W27 GND VSS W28 GND VSS w29 GND VSS W30 GND VSS W31 GND VSS w32 GND VSS W33 GND VSS W34 GND VSS W35 GND VSS Y2 GND VSS Y3 GND VSS Y5 GND VSS Y6 GND VSS Y8 GND VSS Y9 GND VSS_SENSE AJ34 Analog O VSS_SENSE_VCCIO A10 Analog O 120 Datasheet Volume 1 Processor Pin Signal and Package Information Figure 8 2 BGA1224 Ballmap left side intel 65 64 63 62 961 PMWOOMNOICAPEzVMAACKS lt PRERERPHSSPSELEr SE E 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 40 39 38 37 36 Datasheet Volume 1 121 m n tel Processor Pin Signal and Package Information Figure 8 3 BGA1224 Ballmap right side 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Y W V U T R P N M L K J H G F E D c B A 35 34 33 32 31
188. nvironment AC Specifications but are DC coupled The buffers are not 3 3 V tolerant CMOS CMOS buffers DDR3 DDR3 buffers 1 5 V tolerant DDR3L DDR3L buffers 1 35 V tolerant A Analog reference or output May be used as a threshold voltage or for buffer compensation Ref Voltage reference signal Asynchronous Signal has no timing relationship with any reference clock Note 1 Qualifier for a buffer type Datasheet Volume 1 81 Signal Description intel 6 1 System Memory Interface Table 6 2 Memory Channel A Signal Name Description GE SA BS 2 0 Bank Select These signals define which banks are selected within 0 BS 2 0 each SDRAM rank DDR3 SA WE Write Enable Control Signal This signal is used with SA_RAS and O SA_CAS along with SA_CS to define the SDRAM Commands DDR3 SA RAS RAS Control Signal This signal is used with SA_CAS and SA_WE O along with SA_CS to define the SRAM Commands DDR3 SA CAS CAS Control Signal This signal is used with SA_RAS and SA_WE O along with SA_CS to define the SRAM Commands DDR3 Data Strobes SA_DQS 7 0 and its complement signal group make SA_DQS 7 0 up a differential strobe pair The data is captured at the crossing point I O SA_DQS 7 0 of SA_DQS 7 0 and its SA_DQS 7 0 during read and write DDR3 transactions Data Bus Channel A data signal interface to the SDRAM data bus I O SA_DQ 63 0 a DDRS SA MAT15 0 Memory Address Thes
189. o reduce active power e Restricting Turbo Boost Power limits and IA core Turbo Boost availability e Off Lining core activity Move processor traffic to a subset of cores e Placing an IA Core at LFM or MFM Minimum Frequency Mode e Utilizing IA clock modulation Off lining core activity is the ability to execute a workload on a limited subset of cores in conjunction with a lower Turbo power limit However not all processor activity is ensured to be able to shift to a subset of cores Shifting a workload to a limited subset of cores allows other cores to remain idle and save power Therefore when LPM is enabled with core offlining less power is consumed at equivalent frequencies Minimum Frequency Mode MFM of operation has been incorporated into the processor to allow clocked frequencies at or below the Low Frequency Mode LFM When MFM is lower than LFM it allows more active power reduction versus LFM Datasheet Volume 1 69 intel Thermal Management 5 5 Thermal and Power Specifications The following notes apply to the tables in this section Note Definition The TDPs given are not the maximum power the processor can generate Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained periods of time TDP workload may consist of a combination of a processor core intensive and a graphics core intensive applications The
190. obile 3rd Generation Intel Core processor family For 2nd Generation Intel Core processor family mobile the output will be high For Mobile 3rd Generation Intel Core processor family the output will be low VCCIO_SEL Voltage selection for VCCIO This output signal was initially intended to select the I O voltage depending on the processor being used Since the Vccro voltage is the same for 2nd Generation Intel Core processor family mobile and Mobile 3rd Generation Intel Core processor family the usage of this signal was changed as follows This signal should not be used 88 Datasheet Volume 1 Signal Description 6 12 Processor Power Signals Table 6 14 Processor Power Signals 6 13 Signal Name Description Direction Buffer Type VCC Processor core power rail Ref VCCIO Processor power for I O Ref VDDQ Processor I O supply voltage for DDR3 Ref VAXG Graphics core power supply Ref VCCPLL VCCPLL provides isolated power for internal processor PLLs Ref VCCSA System Agent power supply Ref VCCPQE BGA Only e low noise derivative of VCCIO Load current is less than Ref VCCDQ BGA Only ie low noise derivative of VDDQ Load current is less than Ref VIDALERT VIDSCLK and VIDSCLK comprise a three signal VIDSOUT serial synchronous interface used to transfer power CMOS I OD O VIDSCLK management information between the pro
191. ocessor sss 30 2 5 PCI Express Typical Operation 16 Lanes Mapping ee 31 2 6 Processor Graphics Controller Unit Block Diagramm 33 2 7 Processor Display Block Diagramm 36 4 1 Processor Power States ui iiu c AREE EE EES Een REP RAE ADR KR e de eu 47 4 2 Idle Power Management Breakdown of the Processor Cores oooccccccnnnnonnnnnnnnenenananennnnanos 51 4 3 Thread and Core C State Entry and Eat 51 4 4 Package C State Entry and Exit icisescscscsrcecsnencencteeedeeesscadetvieenedennedet a AA wdd RR TW RR UD 55 5 1 Package BowerCopnbtol 27212 SEN ER reet Atanas ade SE e dE EEN da See edad be AER eet 67 5 2 Frequency and Voltage Ordering cissecccceeecccesedeceeseceatacernensecccceeedeceedacendaeaeersarececseree 75 7 1 Example for PECI Host Clients Connection 106 7 2 Input Device Hysteresis 4 tede degree eins is 107 8 1 rPGA988B Socket G2 Pin Map 109 8 2 BGA1224 Ballmap left side i ete i 121 8 3 BGA1224 Ballmap right side 122 8 4 BGA1023 Ballmap Ieft sid amp u iau ia ia Ya DR rer OAOD Ee D EDDU ANF RANA 140 8 5 BGA1023 Ballmap right side 141 8 6 Processor rPGA988B 2C GT1 G24406 Mechanical Package Sheet 1 of 2 156 8 7 Processor rPGA988B 2C GT1 G24406 Mechanical Package Sheet 2 of 2 157 8 8 Processor rPGA988B 2C GT2 G23867 Mechanical Package Sheet 1 of 2 158 8 9 Processor rPGA988B 2C GT2 G23867 Mechanical Package Sheet 2 of 2
192. olume 1 Power Management 4 4 Note Note 4 5 4 6 4 6 1 4 6 2 There is no change to the signals driven by the processor to the DIMMs during DDR IO EPG mode During EPG mode all the DDR IO logic will be powered down except for the Physical Control registers that are powered by the un gated Vccro power supply Unlike S3 exit at DDR EPG exit the DDR will not go through training mode Rather it will use the previous training information retained in the physical control registers and will immediately resume normal operation PCI Express Power Management e Active power management support using LOs and L1 states e All inputs and outputs disabled in L2 L3 Ready state PCIe interface does not support Hot Plug An increase in power consumption may be observed when PCIe ASPM capabilities are disabled DMI Power Management e Active power management support using LOs L1 state Graphics Power Management Intel Rapid Memory Power Management RMPM also known as CxSR The Intel Rapid Memory Power Management puts rows of memory into self refresh mode during C3 C6 C7 to allow the system to remain in the lower power states longer Processors routinely save power during runtime conditions by entering the C3 C6 or C7 state Intel RMPM is an indirect method of power saving that can have a significant effect on the system as a whole Intel Graphics Performance Modulation Technology GPMT Intel Graphics Power
193. on Processor rPGA988B 2C GT2 G23867 Mechanical Package Sheet 2 of 2 Figure 8 9 oo 2 J 13m kde suere 301 AN3NLNY230 138 13 RK llann gn AY AA 1HO12H 1N3 JTEWMO TW 159 Datasheet Volume 1 Processor Pin Signal and Package Information intel Figure 8 10 Processor rPGA988B 4C GT2 E95127 Mechanical Package Sheet 1 of 2 2 y 3 pw S Neu WOINVHOSN 20W OVd RES deu AN3W1BYc 30 d Fe 9007 1 Ll Zu m X ER Y 111 40N i 314 T MILA 1NOYA 8 4 7 Rm 95 g ABADDON AH AA AAO AA 1N3WW02 1080 e Sy via dis Mi M3IA dOl HI aR 7 a d a a z p E i q dL e LL a L 3 an CT A OAL TS Maa i 7
194. ose wishing to rely on the platform can make an appropriate trust decision The Intel TXT platform determines the identity of the controlling environment by accurately measuring and verifying the controlling software Another aspect of the trust decision is the ability of the platform to resist attempts to change the controlling environment The Intel TXT platform will resist attempts by software processes to change the controlling environment or bypass the bounds set by the controlling environment Intel TXT is a set of extensions designed to provide a measured and controlled launch of system software that will then establish a protected environment for itself and any additional software that it may execute Datasheet Volume 1 41 m L l Technologies 3 3 3 4 Note 42 These extensions enhance two areas e The launching of the Measured Launched Environment MLE e The protection of the MLE from potential corruption The enhanced platform provides these launch and control interfaces using Safer Mode Extensions SMX The SMX interface includes the following functions e Measured Verified launch of the MLE e Mechanisms to ensure the above measurement is protected and stored in a secure location e Protection mechanisms that allow the MLE to control attempts to modify itself For more information refer to the Intel TXT Measured Launched Environment Developer s Guide in http www intel com content www us en software dev
195. phics contains a refresh of the seventh generation graphics core enabling substantial gains in performance and lower power consumption Up to 16 EU support Next Generation Intel Clear Video Technology HD Support is a collection of video playback and enhancement features that improve the end user s viewing experience Encode transcode HD content Playback of high definition content including Blu ray Disc Superior image quality with sharper more colorful images Playback of Blu ray disc S3D content using HDMI V 1 4 with 3D DirectX Video Acceleration DXVA support for accelerating video processing Full AVC VC1 MPEG2 HW Decode Advanced Scheduler 2 0 1 0 XPDM support Windows 7 Windows XP OSX Linux OS Support DirectX 11 DirectX 10 1 DirectX 10 DirectX 9 support OpenGL 3 0 support Datasheet Volume 1 Introduction 1 2 6 Embedded DisplayPort eDP e Stand alone dedicated port unlike two generations ago that shared pins with PCIe interface 1 2 7 Intel Flexible Display Interface Intel FDI e For SKUs with graphics carries display traffic from the Processor Graphics in the processor to the legacy display connectors in the PCH e Based on DisplayPort standard e The two FDI links are capable of being configured to support three independent channels one for each display pipeline e There are two FDI channels each one consists of four unidirectional downstream differential transmitter pair
196. pporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality Enhanced Intel SpeedStep Technology See the Processor Spec Finder or contact your Intel representative for more information 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 architecture Performance will vary depending on your hardware and software configurations Consult with your system vendor for more information No computer system can provide absolute security under all conditions Intel Trusted Execution Technology Intel TXT requires a computer system with Intel Virtualization Technology an Intel TXT enabled processor chipset BIOS Authenticated Code Modules and an Intel TXT compatible measured launched environment MLE The MLE could consist of a virtual machine monitor an OS or an application In addition Intel TXT requires the system to contain a TPM v1 2 as defined by the Trusted Computing Group and specific software for some uses For more information see http www intel com technology security Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain computer system software enabled for it Functionality performance or other benefits will vary depending on hardware and softwa
197. press Port 0 gt DMI PCI Express Port 1 gt DMI 64 bit downstream address format however the processor never generates an address above 64 GB Bits 63 36 will always be zeros 64 bit upstream address format however the processor responds to upstream read transactions to addresses above 64 GB addresses where any of Bits 63 36 are nonzero with an Unsupported Request response Upstream write transactions to addresses above 64 GB will be dropped Re issues Configuration cycles that have been previously completed with the Configuration Retry status PCI Express reference clock is 100 MHz differential clock Power Management Event PME functions Dynamic width capability Message Signaled Interrupt MSI and MSI X messages Polarity inversion Static lane numbering reversal Does not support dynamic lane reversal as defined optional by the PCI Express Base Specification Supports Half Swing low power low voltage mode Note The processor does not support PCI Express Hot Plug 1 2 3 Direct Media Interface DMI Datasheet Volume 1 DMI 2 0 support Four lanes in each direction 5 GT s point to point DMI interface to PCH is supported Raw bit rate on the data pins of 5 0 Gb s resulting in a real bandwidth per pair of 500 MB s given the 8b 10b encoding used to transmit data across this interface Does not account for packet overhead and link maintenance Maximum theoretical bandwidth on interface of 2 GB s in e
198. prior to board attach Environmental storage condition limits define the temperature and relative humidity to which the device is exposed to while being stored in applicable Intel shipping media trays reels moisture barrier bags and Boxes and the component is not electrically connected Post board attach storage conditions and limits are not specified for non intel branded boards However component qualification and certification details are provided in the Product Qualification Report and associated EDS document Table 7 4 specifies absolute maximum and minimum storage temperature and humidity limits for given time durations Failure to adhere to the specified limits could result in physical damage to the component If this is suspected Intel recommends a visual inspection to determine possible physical damage to the silicon or surface components Storage Condition Ratings Symbol Parameter Min Max Notes 2 3 4 a storage ra e when exceeded for 25 C 125 C EE E storage temperature and time for up 25 C 85 C Tsustained storage Time The ambient storage temperature and time for up 5 C 40 C and Temp to 30 months RH A HU a ae storage relative humidity 60 amp 24 C Notes 1 Specified temperatures are not to exceed values based on data collected Exceptions for surface mount reflow are specified by the applicable JEDEC standard Non adherence may affect processor reliability 2 Component product
199. rammable using Bits 3 1 of the same IA32_CLOCK_MODULATION MSR In this mode the duty cycle can be programmed in either 12 5 or 6 25 increments discoverable using CPUID Thermal throttling using this method will modulate each processor core s clock independently I O Emulation Based On Demand Mode I O emulation based clock modulation provides legacy support for operating system software that initiates clock modulation through I O writes to ACPI defined processor clock control registers on the chipset PROC CNT Thermal throttling using this method will modulate all processor cores simultaneously Datasheet Volume 1 79 m L Thermal Management 5 6 6 80 Memory Thermal Management The integrated memory controller IMC provides thermal protection for system memory DIMMs using memory bandwidth throttling Like processor package throttling memory throttling is initiated based on temperature The IMC offers two levels of throttling warm and hot The temperature and the amount of bandwidth reduced while throttling is programmable for the warm and hot trip points through memory mapped I O registers Memory temperature can be read directly by a physical thermal sensor on the DIMM TS on DIMM or a physical temperature sensor placed on the motherboard TS on Board Memory throttling based on physical temperature sensor readings is known as Closed Loop Thermal Throttling CLTT The memory temperature readings are reported from t
200. re configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Intel Active Management Technology requires the computer system to have an Intel amp AMT enabled chipset network hardware and software as well as connection with a power source and a corporate network connection Setup requires configuration by the purchaser and may require scripting with the management console or further integration into existing security frameworks to enable certain functionality It may also require modifications of implementation of new business processes With regard to notebooks Intel AMT may not be available or certain capabilities may be limited over a host OS based VPN or when connecting wirelessly on battery power sleeping hibernating or powered off For more information see http www intel com technology platform technology intel amt Intel Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability Intel Turbo Boost Technology performance varies depending on hardware software and overall system configuration Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology For more information see http www intel com technology turboboost Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across differ
201. ress Direct Media Interface DMI Processor Graphics Controller Figure 4 1 Processor Power States C0 Active mode C1 Auto halt CIE Auto halt low freq low voltage C3 L1 L2 caches flush clocks off C6 save core states before shutdown C7 similar to C6 L3 flush Note Power states availability may vary between the different SKUs Datasheet Volume 1 47 4 1 1 Table 4 1 4 1 2 Table 4 2 4 1 3 Table 4 3 48 Power Management ACPI States Supported The ACPI states supported by the processor are described in this section System States System States State Description G0 S0 Full On G1 S3 Cold mc cm STR Context saved to memory S3 Hot is not supported by the G1 S4 Suspend to Disk STD All power lost except wakeup on PCH G2 S5 Soft off All power lost except wakeup on PCH Total reboot G3 Mechanical off All power AC and battery removed from system Processor Core Package Idle States Processor Core Package State Support State Description CO Active mode processor executing code C1 AutoHALT state CIE AutoHALT state with lowest frequency and voltage operating point C3 Execution cores in C3 flush their L1 instruction cache L1 data cache and L2 cache to the L3 shared cache Clocks are shut off to each core Execution cores in this state save their architectural state before removing core C6 voltag
202. rmance will be decreased by the same amount as the duty cycle when clock modulation is active Snooping and interrupt processing are performed in the normal manner while the TCC is active Digital Thermal Sensor Each processor execution core has an on die Digital Thermal Sensor DTS that detects the core s instantaneous temperature The DTS is the preferred method of monitoring processor die temperature because e It is located near the hottest portions of the die e It can accurately track the die temperature and ensure that the Adaptive Thermal Monitor is not excessively activated Temperature values from the DTS can be retrieved through e A software interface using the processor Model Specific Register MSR e A processor hardware interface as described in Section 5 6 6 Platform Environment Control Interface PECI on page 80 When temperature is retrieved by the processor MSR it is the instantaneous temperature of the given core When temperature is retrieved using PECI it is the average of the highest DTS temperature in the package over a 256 ms time window Intel recommends using the PECI reported temperature for platform thermal control that benefits from averaging such as fan speed control The average DTS temperature may not be a good indicator of package Adaptive Thermal Monitor activation or rapid increases in temperature that triggers the Out of Specification status bit within the PACKAGE THERM STATUS MSR 1B1h and
203. rom the Processor Graphics controller to the PCH display I Os Intel FDI supports two or three independent channels one for pipe A one for pipe B and one for Pipe C Channels A and B have a maximum of four transmit Tx differential pairs used for transporting pixel and framing data from the display engine in two display configurations In three display configurations Channel A has 4 transmit Tx differential pairs while Channel B and C have two transmit Tx differential pairs e Each channel has four transmit Tx differential pairs used for transporting pixel and framing data from the display engine e Each channel has one single ended LineSync and one FrameSync input 1 V CMOS signaling e One display interrupt line input LAM CMOS signaling e Intel FDI may dynamically scale down to 2X or 1X based on actual display bandwidth requirements e Common 100 MHz reference clock e Each channel transports at a rate of 2 7 Gbps e PCH supports end to end lane reversal across both channels no reversal support required in the processor Datasheet Volume 1 37 intel Interfaces Note 2 5 2 6 2 6 1 Table 2 6 38 Multi Graphics Controllers Multi Monitor Support The processor supports simultaneous use of the Processor Graphics Controller GT and a x16 PCI Express Graphics PEG device The processor supports a maximum of 2 displays connected to the PEG card in parallel with up to 2 displays connected to the processor and
204. ror checking and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information 88 Datasheet Volume 1 Signal Description 6 Signal Description This chapter describes the processor signals They are arranged in functional groups according to their associated interface or category The following notations are used to describe the signal type Notations Signal Type I Input Signal O Output Signal I O Bi directional Input Output Signal The signal description also includes the type of buffer used for the particular signal see Table 6 1 Table 6 1 Signal Description Buffer Types Signal Description PCI Express interface signals These signals are compatible with PCI Express 3 0 PCI Express Signalling Environment AC Specifications and are AC coupled The buffers are not 3 3 V tolerant Refer to the PCIe specification Embedded Display Port interface signals These signals are compatible with VESA eDP Revision 1 1a DP specifications and the interface is AC coupled The buffers are not 3 3 V tolerant Intel Flexible Display interface signals These signals are based on PCI Express 2 0 FDI Signaling Environment AC Specifications 2 7 GT s but are DC coupled The buffers are not 3 3 V tolerant Direct Media Interface signals These signals are compatible with PCI Express 2 0 DMI Signaling E
205. rst be closed before putting the devices in power down mode If dynamic power down is enabled all ranks are powered up before doing a refresh cycle and all ranks are powered down at the end of refresh DRAM I O Power Management Unused signals should be disabled to save power and reduce electromagnetic interference This includes all signals associated with an unused memory channel Clocks can be controlled on a per SO DIMM basis Exceptions are made for per SO DIMM control signals such as CS CKE and ODT for unpopulated SO DIMM slots The I O buffer for an unused signal should be tri stated output driver disabled the input receiver differential sense amp should be disabled and any DLL circuitry related ONLY to unused signals should be disabled The input path must be gated to prevent spurious results due to noise on the unused signals typically handled automatically when input receiver is disabled Mode CO C1 C1E C3 C6 C7 S3 S4 4 3 2 3 4 3 2 4 4 3 3 DDR Electrical Power Gating EPG The DDR I O of the processor supports on die Electrical Power Gating DDR EPG during normal operation S0 mode while the processor is at package C3 or deeper 60 power state During EPG the Vccjo internal voltage rail will be powered down while Vppg and the un gated Vecio will stay powered on The processor will transition in and out of DDR EPG mode on an as needed basis without any external pins or signals Datasheet V
206. ructions were added to allow graphics media and imaging applications to speed up the processing of large amount of data by reducing the memory bandwidth and footprint The new instructions convert operands between single precision floating point values and half precision 16 bit floating point values For more information on Intel AVX see http www intel com software avx Security and Cryptography Technologies Advanced Encryption Standard New Instructions AES NI The processor supports Advanced Encryption Standard New Instructions AES NI that are a set of Single Instruction Multiple Data SIMD instructions that enable fast and secure data encryption and decryption based on the Advanced Encryption Standard AES AES NI are valuable for a wide range of cryptographic applications for example applications that perform bulk encryption decryption authentication random number generation and authenticated encryption AES is broadly accepted as the standard for both government and industry applications and is widely deployed in various protocols AES NI consists of six Intel SSE instructions Four instructions namely AESENC AESENCLAST AESDEC and AESDELAST facilitate high performance AES encryption and decryption The other two AESIMC and AESKEYGENASSIST support the AES key expansion procedure Together these instructions provide a full hardware for support AES offering security high performance and a great deal of flexibility P
207. s Scalable down to 3X 2X or 1X based on actual display bandwidth requirements Fixed frequency 2 7 GT s data rate e Two sideband signals for display synchronization FDI FSYNC and FDI LSYNC Frame and Line Synchronization e One Interrupt signal used for various interrupts from the PCH FDI INT signal shared by both Intel FDI Links e PCH supports end to end lane reversal across both links e Common 100 MHz reference clock 1 3 Power Management Support 1 3 1 Processor Core e Full support of ACPI C states as implemented by the following processor C states CO C1 CIE C3 C6 C7 e Enhanced Intel SpeedStep Technology 1 3 2 System SO S3 S4 S5 1 3 3 Memory Controller e Conditional self refresh Intel Rapid Memory Power Management Intel RMPM e Dynamic power down 1 3 4 PCI Express e LOs and L1 ASPM power management capability 1 3 5 DMI e LOs and L1 ASPM power management capability Datasheet Volume 1 17 m L Introduction 1 3 6 Processor Graphics Controller GT e Rapid Memory Power Management RMPM CxSR e Graphics Performance Modulation Technology GPMT e Intel Smart 2D Display Technology Intel S2DDT e Graphics Render C State RC6 e Intel Seamless Display Refresh Rate Switching with eDP port 1 3 7 Thermal Management Support Digital Thermal Sensor e Intel Adaptive Thermal Monitor e THERMTRIP and PROCHOT support e On Demand Mode Open and Closed Loop Throttling
208. so brings robust security by providing protection from errant DMAs by using DMA remapping a key feature of Intel VT d IOV I O Virtualization ITPM Integrated Trusted Platform Module LCD Liquid Crystal Display LFM Low Frequency Mode HFM High Frequency Mode LVDS Low Voltage Differential Signaling A high speed low power data transmission standard used for display connections to LCD panels Non Critical to Function NCTF locations are typically redundant ground or non NCTF critical reserved so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality 20 Datasheet Volume 1 Introduction Table 1 2 intel Terminology Sheet 2 of 2 Term Description Platform Controller Hub The chipset with centralized platform capabilities PCH including the main I O interfaces along with display connectivity audio features power management manageability security and storage features PECI Platform Environment Control Interface PCI Express Graphics External Graphics using PCI Express Architecture A PEG high speed serial interface whose configuration is software compatible with the existing PCI specifications Processor The 64 bit single core or multi core component package Processor Core The term processor core refers to Si die itself which can contain multiple execution cores Each execution core has an instruction cache data cache and 256 KB L2
209. ssor core and graphics core power plane controls allow for customization to implement optimal Turbo within voltage regulator thermal limitations It is possible to use these power plane controls to protect the voltage regulator from overheating due to extended high currents Power limiting per plane cannot be ensured in all usages This function is similar to the package level long duration Turbo control Graphics Turbo frequencies can be efficiently limited by setting the Secondary Plane Turbo Power Limit to an artificially low setting that may be designed in certain cases Primary Plane Turbo Power Limit lower settings are bound to the same limits as found in the PACKAGE MIN POWER MSR 0x614 30 16 Turbo Time Parameter Turbo Time Parameter is a mathematical parameter units in seconds that controls the Intel Turbo Boost Technology algorithm using an exponentially weighted moving average of energy usage During a maximum power Turbo event of about 1 25 x TDP the processor could sustain POWER LIMIT 2 for up to approximately 1 5 times the Turbo Time Parameter If the power value and or Turbo Time Parameter is changed during runtime it may take a period of time possibly up to approximately 3 to 5 times the Turbo Time Parameter depending on the magnitude of the change and other factors for the algorithm to settle at the new control limits There is an individual Turbo Time parameter associated with Package Power Control and another associa
210. status and sticky bit are latched in the PACKAGE_THERM_STATUS MSR 1B1h and also generates a thermal interrupt if enabled For more details on the interrupt mechanism refer to the Inte 64 and IA 32 Architectures Software Developer s Manuals On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption using clock modulation This mechanism is referred to as On Demand mode and is distinct from Adaptive Thermal Monitor and bi directional PROCHOT The processor platforms must not rely on software usage of this mechanism to limit the processor temperature On Demand Mode can be done using processor MSR or chipset I O emulation On Demand Mode may be used in conjunction with the Adaptive Thermal Monitor However if the system software tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode If the I O based and MSR based On Demand modes are in conflict the duty cycle selected by the I O emulation based On Demand mode will take precedence over the MSR based On Demand Mode MSR Based On Demand Mode If Bit 4 of the IA32 CLOCK MODULATION MSR is set to a 1 the processor will immediately reduce its power consumption using modulation of the internal core clock independent of the processor temperature The duty cycle of the clock modulation is prog
211. t differentiate it from a 2nd Generation Intel Core processor family mobile processor Platforms intending to support both processor families need to address the platform compatibility requirements detailed in Figure 1 2 Figure 1 2 Mobile Processor Compatibility Diagram VAXG 2 ph required for some SKUs 2 x 330 UF 2 x 330 UF 1 placeholder DDR3 3L PEG AC Decoupling 2G Core 15V wuel PEG Gen 1 2 100 nF 3d Sere 11 3 Vior PEG Gen 1 2 3 220 nF 1 35 V 2G Core 1 05 V 3G Core 1 05 V 1 35 V for eegen BGA DC only Mobile Processor VCCSA_VID 1 0 VCCIO_SEL 2G_Core bis id PROC_SELECT 3G_Core 0 Need to be disconnected 2G Core 1 To use same Voltage 3G Core P Controls DMI Selected and FDI VCCSA VID 0 VCCSA VID 1 ESA Y termination Notes 1 2G Core 2nd Generation Intel Core processor family mobile 2 3G Core Mobile 3rd Generation Intel Core processor family Datasheet Volume 1 19 intel 1 7 Terminology Introduction Table 1 2 Terminology Sheet 1 of 2 Term Description BLT Block Level Transfer CRT Cathode Ray Tube DDR3 Third generation Double Data Rate SDRAM memory technology DDR3L DDR3 Low Voltage DDDR3L RS DDR3L Reduced Standby Power DMA Direct Memory
212. tasheet Volume 1 Processor Pin Signal and Package Information Table 8 2 BGA1224 Processor Ball List by Ball Name Continued intel Table 8 2 BGA1224 Processor Ball List by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball 4 Buffer Type Dir VSS AF5 GND VSS R57 GND VSS AE57 GND VSS R50 GND VSS AD16 GND VSS R44 GND VSS AD14 GND VSS R38 GND VSS AD7 GND VSS R31 GND VSS AD3 GND VSS R25 GND VSS AD1 GND VSS R19 GND VSS AC64 GND VSS R17 GND VSS AC62 GND VSS R15 GND VSS AC60 GND VSS R12 GND VSS AC57 GND VSS P65 GND VSS AB11 GND VSS P63 GND VSS AB9 GND VSS P61 GND VSS AB5 GND VSS P11 GND VSS AA57 GND VSS P9 GND VSS AA17 GND VSS P5 GND VSS AA15 GND VSS N54 GND VSS AA12 GND VSS N47 GND VSS Y65 GND VSS N41 GND VSS Y63 GND VSS N35 GND VSS Y61 GND VSS N28 GND VSS Y7 GND VSS N22 GND VSS Y3 GND VSS M57 GND VSS Yi GND VSS M50 GND VSS W57 GND VSS M44 GND VSS V16 GND VSS M38 GND VSS V14 GND VSS M31 GND VSS vil GND VSS M25 GND VSS V9 GND VSS M19 GND VSS V5 GND VSS M7 GND VSS U64 GND VSS M3 GND VSS U62 GND VSS M1 GND VSS U60 GND VSS L64 GND VSS U57 GND VSS L62 GND VSS TZ GND VSS L60 GND VSS T3 GND VSS L58 GND VSS T1 GND VSS L54 GND Datasheet Volume 1 137 m n tel Processor Pin Signal and Package Information
213. te Combinations G S and C State Combinations Datasheet Volume 1 Giona 9 a Package Y System Clocks Description GO S0 co Full On On Full On GO S0 C1 C1E Auto Halt On Auto Halt GO S0 C3 Deep Sleep On Deep Sleep GO so C6 C7 Deep rower On Deep Power Down G1 S3 Power off Off except RTC Suspend to RAM G1 S4 Power off Off except RTC Suspend to Disk G2 S5 Power off Off except RTC Soft Off G3 NA Power off Power off Hard off 49 intel Table 4 8 4 2 4 2 1 50 Power Management D S and C State Combination e Sleep S State Package C State Description DO S0 co Full On Displaying DO S0 C1 C1E Auto Halt Displaying DO S0 C3 Deep sleep Displaying DO S0 C6 C7 Deep Power Down Displaying D3 S0 Any Not displaying D3 S3 N A Nate Graphics Core is D3 S4 N A Not displaying suspend to disk Processor Core Power Management While executing code Enhanced Intel SpeedStep Technology optimizes the processor s frequency and core voltage based on workload Each frequency and voltage operating point is defined by ACPI as a P state When the processor is not executing code it is idle A low power idle state is defined by ACPI as a C state In general lower power C states have longer entry and exit latencies Enhanced Intel SpeedStep Technology The following are the key features of Enhanced Intel SpeedStep Technology e Multiple frequenc
214. te ee on er Cai AG esa Ce cH DNA DNE 37 2 4 2 3 Display POMS iei suck renis send mese keine REI Xe ae ea RES A e 37 2 4 2 4 Embedded DisplayPort ep 37 2 4 3 Intel Flexible Display Interface eene 37 2 4 4 Multi Graphics Controllers Multi Monitor Support 38 2 5 Platform Environment Control Interface PECI ssssssssseee mme 38 2 6 Interface Clocking u ui etra irre A e SEE RYN FAN dee Ee AREA Ryw CyT 38 2 6 1 Internal Clocking Requirements nennen eene 38 U4nppMIIm 39 3 1 Intel Virtualization Technology vei iie WORN YR AF YN aca c idco Cr i e le bai a rE rn 39 3 1 1 Intel VT x Objectives PET 39 3 1 2 Intel VT x Pea tes ie NG wb YU EE 40 EE A0 3 1 4 Intel WEE pis io ia 40 3 1 5 Intel VT d Features Not Supported c ccccccccccccsesesensceececesnceecceneseneneceenunas 41 3 2 Intel Trusted Execution Technology Intel TT 41 3 3 Intel Hyper Threading Technology eene nennen nena 42 244 Intel Turbo Boost Ted noria 42 3 4 1 Intel Turbo Boost Technology Ereguencny 43 3 4 2 Intel Turbo Boost Technology Graphics Freguencn 43 3 5 Intel Advanced Vector Extensions AVN 44 3 6 Security and Cryptography Technologies 44 3 6 1 Advanced Encryption Standard New Instructions AES NI sess 44 3 6 2 PCLMULODO Instriction e d SEENEN EE NEE ot a rne Ihe EY ero reru rena E dE arare 44 3 6 3 RDRAND Instr ction
215. te is demoted to C3 or C1 until a sufficient amount of residency has been established At that point a core is allowed to go into C3 C6 or C7 Each option can be run concurrently or individually This feature is disabled by default BIOS must enable it in the PMG CST CONFIG_ CONTROL register The auto demotion policy is also configured by this register 4 2 5 Package C States The processor supports CO C1 C1E C3 C6 and C7 power states The following is a summary of the general rules for package C state entry These apply to all package C states unless specified otherwise e A package C state request is determined by the lowest numerical core C state amongst all cores A package C state is automatically resolved by the processor depending on the core idle power states and the status of the platform components Each core can be at a lower idle power state than the package if the platform does not grant the processor permission to enter a requested package C state The platform may allow additional power savings to be realized in the processor For package C states the processor is not required to enter CO before entering any other C state 54 Datasheet Volume 1 Power Management intel The processor exits a package C state when a break event is detected Depending on the type of break event the processor does the following e If a core break event is received the target core is activated and the break event
216. ted with each power plane Configurable TDP and Low Power Mode Configurable TDP cTDP and Low Power Mode LPM form a new design vector where the processor s behavior and package TDP are dynamically adjusted to a desired system performance and power envelope Configurable TDP and Low Power Mode technologies are not battery life improvement technologies but they offer new opportunities to differentiate system design while running active workloads using Intel s premium processor products through scalability configurability and adaptability The scenarios or methods by which each technology is used are customizable but typically involve changes to TDP with a resultant change in performance depending on system s usage Either technology can be triggered by but are not limited to changes in operating system power policies or hardware events such as docking a system flipping a switch or pressing a button cTDP and LPM are designed to be configured dynamically and do not require an operating system reboot Configurable TDP Configurable TDP is limited to a subset of Ultra and Extreme Edition parts but is subject to change With cTDP the processor is now capable of altering the TDP power with an alternate ensured frequency Configurable TDP allows operation in situations where extra cooling is available or situations where a cooler and quieter mode of operation is desired Configurable TDP can be enabled using an Intel driver or through HW EC
217. th four Physical Lanes x8 Refers to a Link or Port with eight Physical Lanes Datasheet Volume 1 21 intel 1 8 Related Documents Table 1 3 Related Documents Introduction Document Number Document Location Mobile 3rd Generation Intel Core Processor Family Datasheet Volume 2 326769 Mobile 3rd Generation Intel Core Processor Family Specification Update 326770 Advanced Configuration and Power Interface Specification 3 0 http www acpi info PCI Local Bus Specification 3 0 http www pcisig com speci fications PCI Express Base Specification 2 0 DDR3 SDRAM Specification http www pcisig com http www jedec org DisplayPort Specification http www vesa org Intel 64 and IA 32 Architectures Software Developer s Manuals http www intel com produ cts processor manuals inde x htm Volume 1 Basic Architecture 253665 Volume 2A Instruction Set Reference A M 253666 Volume 2B Instruction Set Reference N Z 253667 Volume 3A System Programming Guide 253668 Volume 3B System Programming Guide 253669 Note Contact your Intel representative for the latest revision of this item 88 22 Datasheet Volume 1 Interfaces 2 2 1 2 1 1 Note Note Table 2 1 Interfaces This chapter describes the interfaces supported by the processor System Memory Interface System Memory Technology Supported The Integrated
218. the new refresh rate The seamless Intel DRRS method is able to accomplish the refresh rate assignment without a mode change and therefore does not experience some of the visual artifacts associated with the mode change SetMode method Datasheet Volume 1 63 Power Management 4 7 Graphics Thermal Power Management See Section 4 6 for all graphics thermal power management related features 88 64 Datasheet Volume 1 Thermal Management intel 5 Caution 5 1 5 2 Thermal Management The thermal solution provides both the component level and the system level thermal management To allow for the optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed so that the processor Remains below the maximum junction temperature T max specification at the maximum thermal design power TDP e Conforms to system constraints such as system acoustics system skin temperatures and exhaust temperature requirements Thermal specifications given in this chapter are on the component and package level and apply specifically to the processor Operating the processor outside the specified limits may result in permanent damage to the processor and potentially other components in the system Thermal Considerations The processor TDP is the maximum sustained power that should be used for design of the processor thermal solution TDP represents an expected maxi
219. thermal solution needs to ensure that the processor temperature does not exceed the maximum junction temperature T max limit as measured by the DTS and the critical temperature bit The processor junction temperature is monitored by Digital Temperature Sensors DTS For DTS accuracy refer to Section 5 6 2 1 Digital Thermal Sensor DTS based fan speed control is required to achieve optimal thermal performance Intel recommends full cooling capability well before the DTS reading reaches Tj max An example of this would be Tj max 10 C The idle power specifications are not 100 tested These power specifications are determined by the characterization at higher temperatures and extrapolating the values for the junction temperature indicated At Tj of Tj max At T of 50 C At T of 35 9C Can be modified at runtime by MSR writes with MMIO and with PECI commands 11 Turbo Time Parameter is a mathematical parameter seconds that controls the processor Turbo algorithm using a moving average of energy usage Do not set the Turbo Time Parameter to a value less than 0 1 seconds Refer to Section 5 3 3 for further information 12 Shown limit is a time averaged power based upon the Turbo Time Parameter Absolute product power may exceed the set limits for short durations or under virus or uncharacterized workloads 13 Processor will be controlled to specified power limit as described in Section
220. tion intel Table 8 1 rPGA988B Processor Pin List Table 8 1 rPGA988B Processor Pin List by Pin Name Continued by Pin Name Continued Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir PEG_RX 5 H34 PCIe I PEG_TX 4 L28 PCIe O PEG_RX 6 H31 PCIe I PEG_TX 5 K30 PCIe O PEG_RX 7 G33 PCIe I PEG_TX 6 K27 PCIe O PEG_RX 8 G30 PCIe I PEG TX 7 J29 PCIe O PEG_RX 9 F35 PCIe I PEG TX 8 327 PCIe O PEG_RX 10 E34 PCIe I PEG_TX 9 H28 PCIe O PEG_RX 11 E32 PCIe I PEG TX 10 G28 PCIe 9 PEG_RX 12 D33 PCIe I PEG TX 11 E28 PCIe O PEG_RX 13 D31 PCIe I PEG TX 12 F28 PCIe O PEG_RX 14 B33 PCIe I PEG TX 13 D27 PCIe O PEG_RX 15 C32 PCIe I PEG_TX 14 E26 PCIe 9 PEG RX 0 33 PCIe I PEG TX 15 D25 PCIe O PEG_RX 1 L35 PCIe I PM_SYNC AM34 Asynch CMOS I PEG_RX 2 K34 PCIe I PRDY AP29 Asynch CMOS O PEG_RX 3 H35 PCIe I PREQ AP27 Asynch CMOS I PEG_RX 4 H32 PCIe I PROC SELECT C26 N A O PEG_RX 5 G34 PCIe I PROCHOT AL32 Asynch CMOS 1 0 PEG_RX 6 G31 PCIe I RESET AR33 Asynch CMOS I PEG_RX 7 F33 PCIe I RSVD C30 PEG RX 8 F30 PCIe I RSVD A31 PEG_RX 9 E35 PCIe I RSVD B30 PEG RX
221. to save power More power savings actions are taken for numerically higher C states However higher C states have longer exit and entry latencies Resolution of C states occur at the thread processor core and processor package level Thread level C states are available if Intel Hyper Threading Technology is enabled Long term reliability cannot be assured unless all the Low Power Idle States are enabled Idle Power Management Breakdown of the Processor Cores Thread O Thread 1 Thread O Thread 1 Core 0 State Core 1 State Processor Package State Entry and exit of the C States at the thread and core level are shown in Figure 4 3 Figure 4 3 Thread and Core C State Entry and Exit MWAIT C1 HLT a MWAIT C7 d MWAIT C1 ur MWAIT C6 PI LVL4 1 0 Read AF on MWAIT C3 PL ae js ai P LVL2 1 0 Read g a l A D CIE C3 d ww OKOLO While individual threads can request low power C states power saving actions only take place once the core C state is resolved Core C states are automatically resolved by the processor For thread and core C states a transition to and from CO is required before entering any other C state Datasheet Volume 1 51 m L Power Management Table 4 9 4 2 3 Note Table 4 10 Note 52 Coordination of Thread Power States at the Core Level Processor Core Thread 1 C State En a E
222. unter in the same range of page close idle timer Another option associated with CKE power down is the S DLL off When this option is enabled the SBR I O slave DLLs go off when all channel ranks are in power down Do not confuse it with the DLL off mode in which the DDR DLLs are off This mode requires an I O slave DLL wakeup time be defined Initialization Role of CKE During power up CKE is the only input to the SDRAM that has its level recognized other than the DDR3 reset pin once power is applied The signal must be driven LOW by the DDR controller to make sure the SDRAM components float DQ and DQS during power up CKE signals remain LOW while any reset is active until the BIOS writes to a configuration register Using this method CKE is ensured to remain inactive for much longer than the specified 200 us after power and clocks to SDRAM devices are stable Conditional Self Refresh Intel Rapid Memory Power Management Intel RMPM conditionally places memory into self refresh in the package C3 C6 and C7 low power states RMPM functionality depends on graphics display state relevant only when processor graphics is being used as well as memory traffic patterns generated by other connected I O devices When entering the S3 Suspend to RAM STR state or SO conditional self refresh the processor core flushes pending cycles and then enters all SDRAM ranks into self refresh the CKE signals remain LOW so the SDRAM devices perform s
223. ured in conditions above or below Max Min functional limits 9 PSx refers to the voltage regulator power state as set by the SVID protocol 10 Refer to Configurable TDP in Chapter 5 Thermal Management for TDP Up and TDP Down definition 100 Datasheet Volume 1 Electrical Specifications intel Table 7 6 Processor Uncore Vccro Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note Voltage for the memory controller and V shared cache defined at the _ 1 05 _ v ccio motherboard Vccio_SENSE and i Vss_SENSE_VCCIO TOL Vecio Tolerance defined across DC 2 including ripple y LO Vccro seNsE and Vss sENsE vccio AC 3 IccMax vccio Max Current for Vccro Rail 8 5 A I Thermal Design Current TDC for 8 A CCTDC VCCIO Vecto Rail 5 Note 1 Long term reliability cannot be assured in conditions above or below Max Min functional limits Table 7 7 Memory Controller Vppo Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note Processor I O supply voltage a ce for DDR3 DC AC 1 5 v specification Processor I O supply voltage Vppq DC AC E u 8 DDR3L DDR3L RS 9 DDR3L DDR3L RS DC AC 1 35 V specification Vppq Tolerance DC 13 TOLppo AC 2 AC DC 5 Iccmax_vDDQ Max Current for VppQ Rail c 5 A 1 I Thermal Design Current TDC _ 5 A 1 CCTDC_VDDQ for VDDQ Rail
224. within normal operating limits Furthermore the processor supports several methods to reduce memory power Adaptive Thermal Monitor The purpose of the Adaptive Thermal Monitor is to reduce processor core power consumption and temperature until it operates at or below its maximum operating temperature Processor core power reduction is achieved by e Adjusting the operating frequency using the core ratio multiplier and input voltage using the SVID bus e Modulating starting and stopping the internal processor core clocks duty cycle The Adaptive Thermal Monitor can be activated when any package temperature monitored by a digital thermal sensor DTS meets or exceeds its maximum junction temperature specification Tj max and asserts PROCHOT The assertion of PROCHOT activates the thermal control circuit TCC and causes both the processor core and graphics core to reduce frequency and voltage adaptively The TCC will remain active as long as any package temperature exceeds its specified limit Therefore the Adaptive Thermal Monitor will continue to reduce the package frequency and voltage until the TCC is de activated 73 m L Thermal Management Note 5 6 1 1 5 6 1 2 74 The temperature at which the Adaptive Thermal Monitor activates the thermal control circuit is factory calibrated and is not user configurable The default value is software visible in the TEMPERATURE_TARGET 1A2h MSR bits 23 16 The Adapt
225. y and voltage points for optimal performance and power efficiency These operating points are known as P states e Frequency selection is software controlled by writing to processor MSRs The voltage is optimized based on the selected frequency and the number of active processor cores If the target frequency is higher than the current frequency Vcc is ramped up in steps to an optimized voltage This voltage is signaled by the SVID bus to the voltage regulator Once the voltage is established the PLL locks on to the target frequency If the target frequency is lower than the current frequency the PLL locks to the target frequency then transitions to a lower voltage by signaling the target voltage on SVID bus All active processor cores share the same frequency and voltage In a multi core processor the highest frequency P state requested amongst all active cores is selected Software requested transitions are accepted at any time If a previous transition is in progress the new transition is deferred until the previous transition is completed e The processor controls voltage ramp rates internally to ensure glitch free transitions e Because there is low transition latency between P states a significant number of transitions per second are possible Datasheet Volume 1 Power Management intel 4 2 2 Caution Figure 4 2 Low Power Idle States When the processor is idle low power idle states C states are used

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