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Intel Core i3-2312M

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1. 61 60 59 58 57 56 55 53 51 49 48 47 45 43 42 4 40 39 38 3 36 35 34 33 32 B 55 BD 58 paja 54 2 s BB 54 DO 4 5 5 7 2 ga soot ss se sa 5 4 5 9 AY 58 paja sa 5 0655 5 3 3 s AW ss se sa 1 4 4 SA Das SA AV 4 il au 58298 58 sa E 3 E AR AP AN AM AL AK A gx AG s dis se sa 54 aja aja 3 58 AE 140 Datasheet Volume 1 Processor Pin and Signal Information Figure 8 10 BGA1023 Ballmap Top View Upper Right Quadrant 31 30 29 28 27 26 5 24 28 22 21 20 19 i8 17 16 5 10 9 8 7 6 5 4 3 2 1 ss se 55 a sl El 58 58 Ed 3 5 58 58 pa 2 ss 58 58 58 58 pat 21 s 5 8 1 8 58 0051 58 005 58 Da 2 58 58 58 3
2. Table 8 3 1023 Processor Ball Table 8 3 BGA1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VCC E38 PWR VCCIO AL15 PWR VCC E37 PWR VCCIO AL14 PWR VCC E34 PWR VCCIO AK51 PWR VCC E32 PWR VCCIO AK50 PWR VCC E28 PWR VCCIO AJ47 PWR VCC E26 PWR VCCIO AJ43 PWR VCC D42 PWR VCCIO AJ25 PWR VCC D39 PWR VCCIO AJ21 PWR VCC D37 PWR VCCIO AJ17 PWR VCC D34 PWR VCCIO 15 PWR VCC D32 PWR VCCIO AJ14 PWR VCC D27 PWR VCCIO AG51 PWR VCC C42 PWR VCCIO 50 PWR VCC C39 PWR VCCIO AG48 PWR VCC C37 PWR VCCIO AG21 PWR VCC C34 PWR VCCIO AG20 PWR VCC C32 PWR VCCIO AG17 PWR VCC C27 PWR VCCIO AG16 PWR VCC C26 PWR VCCIO AG15 PWR VCC A42 PWR VCCIO AF46 PWR VCC A39 PWR VCCIO AF20 PWR VCC A38 PWR VCCIO AF18 PWR VCC A35 PWR VCCIO AF16 PWR VCC A34 PWR VCCIO AE15 PWR VCC A31 PWR VCCIO AE14 PWR VCC A29 PWR VCCIO AD21 PWR VCC A26 PWR VCCIO AD18 PWR VCC_DIE_SENSE F48 Analog VCCIO AD16 PWR VCC_SENSE F43 Analog VCCIO AC13 PWR VCC_VAL_SENSE H43 Analog VCCIO AB20 PWR VCCDQ AN26 PWR VCCIO AB17 PWR VCCDQ AM28 PWR VCCIO AA15 PWR VCCIO AN48 PWR VCCIO AA14 PWR VCCIO 45 PWR VCCIO W17 PWR VCCIO AN42 PWR VCCIO W16 PWR VCCIO AN20 PWR VCCIO SEL BC22 N A VCCIO AM47 PWR VCCIO_SENSE AN16 Analog VCCIO AM43 PWR VCCPLL BC4 PWR VCCIO AM21 PWR VCCPLL BC1 PWR VCCIO AM17 PWR VCCPLL BB3 PWR VCCIO AM16 PWR VCCPQE AN2
3. 00000 0 0 0 0999 o o o o o o 05090 5 0009 000900000040 0 0 0 O O 0 0 0900000000000000 09 4 00 O 5040 000000000009 0000 00000909 000 96 ooo900000000 000500905000 9 9 oO 2520 09009 0000 Soo 99909 900000000 o oo 008 o ooo oo 9 o 0 0 0 O O O O ooooo ooo 000000000 900000000000000000 0000009 660 000000008 0000 0000000 ooo 900 990000005 00000 coooooo 999 999 559000990 9099900000000 990 999 000000990 99669900 0000009900000 o 1 000009000000 990 J 099 00000099 00000000 90 31 009 00000000 90000 000 00000000 9 0000999999900 000 o o 00000000 9 z 00000 000 1 869 000000000000000000000000000000 96 000000000000080000 0699 22 25 00000 000 9 900000 0090 o 909 9999 666258 5050 59920000299 900 999 0000 0006 9000 90 908 9999 999969 000 6 c 000008 0009 000000 000 90500900 4 ooo 00005 9009690 9006 00 008 005990
4. 4 gt r LT THEE Pi EC 7 Datasheet Volume 1 157 Processor Pin and Signal Information intel Figure 8 16 Processor rPGA988B 4C GT2 Mechanical Package Sheet 2 of 2 I z t 5 9 1 AJIA MOLIDB 3015 401 LEE Datasheet Volume 1 158 intel Processor Pin and Signal Information Figure 8 17 Processor BGA1023 2C GT2 Mechanical Package Sheet 1 of 2 ONIMVEG TVOINVHJAN aun aic wei MEM a 93501530 310 3040 1H913H 3134111 2555 5 5 5 9295592950 TT o900 0000000 90 0 9909 0000000000000000000 0000000000 000 gt N88 b 1830 899 08 959525252029 2 89929 59 5 459999509 00000000d000 09889 99 09999 999999000000 209559900 109 00 o o o o 8991 1 000000000900000000000000000079000000 009 89900000090 0 00000 0000000 oo 900009008 200004 455000 958839928 000000500 009900000000 99 8225985
5. 89 Datasheet Volume 1 intel Electrical Specifications 7 4 System Agent SA Vcc VID The is configured by the processor output pins VCCSA VID 1 0 VCCSA VID 0 output default logic state is low for the 2nd Generation Intel Core processor family mobile and Intel Celeron processor family mobile Logic high is reserved for future compatibility VCCSA VID 1 output default logic state is low will not change the SA voltage Logic high will reduce the voltage Note During boot the processor s is 0 9 V Table 7 2 specifies the different VCCSA VID configurations Table 7 2 VID configuration Selected VCCSA Selected VCCSA Processor family VCCSA VID 0 VCCSA VID 1 XE and SV LV and ULV segments segments 2nd Generation Intel 0 0 0 9 V 0 9 V Core processor family mobile Intel Celeron 0 1 0 8 V 0 85 V processor family mobile Future Intel processors 1 0 Note 1 Note 1 1 1 Note 1 Note 1 Notes 1 Some of Vccs configurations are reserved for future Intel processor families 7 5 Reserved or Unused Signals 90 The following are the general types of reserved RSVD signals and connection guidelines e RSVD these signals should not be connected e RSVD_TP these signals should be routed to a test point e RSVD_NCTF these signals are non critical to function and may be left un connected Arbitrary connection of
6. Datasheet Volume 1 147 m e n tel Processor Pin and Signal Information Table 8 3 BGA1023 Processor Ball Table 8 3 1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir SB DQ 31 BF19 DDR3 I O SB_DQS 6 AR59 DDR3 1 0 SB_DQ 32 BD50 DDR3 I O SB_DQS 7 AK61 DDR3 1 0 SB_DQ 33 BF48 DDR3 I O SB_MA 0 BF32 DDR3 SB DQ 34 BD53 DDR3 1 0 SB_MA 1 BE33 DDR3 SB_DQ 35 BF52 DDR3 1 0 SB_MA 2 BD33 DDR3 SB_DQ 36 BD49 DDR3 10 SB_MA 3 AU30 DDR3 SB_DQ 37 BE49 DDR3 1 0 SB_MA 4 BD30 DDR3 SB_DQ 38 BD54 DDR3 I O SB_MA 5 AV30 DDR3 SB_DQ 39 BE53 DDR3 I O SB MA 6 BG30 DDR3 SB_DQ 40 BF56 DDR3 1 0 SB_MA 7 BD29 DDR3 SB DQ 41 BE57 DDR3 1 0 SB_MA 8 BE30 DDR3 SB_DQ 42 BC59 DDR3 1 0 SB_MA 9 BE28 DDR3 SB_DQ 43 AY60 DDR3 1 0 SB_MA 10 BD43 DDR3 SB_DQ 44 BE54 DDR3 1 0 SB MA 11 AT28 DDR3 SB_DQ 45 BG54 DDR3 1 0 SB_MA 12 AV28 DDR3 SB DQ 46 BA58 DDR3 I O SB_MA 13 BD46 DDR3 SB_DQ 47 AW59 DDR3 1 0 SB_MA 14 AT26 DDR3 SB DQ 48 AW58 DDR3 1 0 SB_MA 15 AU22 DDR3 SB DQ 49 AU58 DDR3 I O SB_ODT 0 AT43 DDR3 SB_DQ 50 AN61 DDR3 1 0 SB_ODT 1 BG47 DDR3 SB_DQ 51 AN59 DDR3 1 0 SB_RAS BF40 DDR3 SB_DQ 52 59 DDR3 1 0 SB_WE BD45 DDR3 SB_DQ
7. 122 Datasheet Volume 1 Processor Pin and Signal Information Figure 8 7 BGA1224 Ballmap Top View Lower Left Quadrant 58 CrG 9 cels VIDSCL K D creto 65 64 63 62 61 60 59 58 57 56 cre 3 53 52 VIDALE 51 49 47 Datasheet Volume 1 123 intel Processor Pin and Signal Information Figure 8 8 BGA1224 Ballmap Top View Lower Right Quadrant 35 33 32 31 5 19 PEG 15 PEG 55 TX 13 PEG TX 17 8 PEG TX 10 TX 2 TX 13 PEG TX 0 21 PEG TX 6 n PEG 11 PEG 3 4 PEG eG TX 8 PEG 10 PEG TX 12 PEG 13 PEG Tx 14 10 21 18 15 PEG TX 81 14 13 12 11 TX e AC AB 124 Datasheet Volume 1 Processor Pin and Signal
8. 97 Processor Graphics VAXG Supply DC Voltage and Current Specifications 98 DDR3 Signal Group DC Specifications nemen eene 99 Control Sideband and TAP Signal Group DC 100 PCI Express DC Specifications iore ik inane taraen tae qasaqa tates dad RR RAE 100 Embedded DisplayPort DC Specifications sss meme 101 PECI DC Electrical Limits a ceci rir A a A x HR sa 102 rPGA988B Processor Pin List by Pin 4 eene ene 110 BGA1224 Processor Ball List by Ball 125 BGA1023 Processor Ball List by Ball emen 144 DDR Data Swizzling Table Channel 10 1 168 DDR Data Swizzling Table Channel B r rr emen 169 Datasheet Volume 1 Revision History Datasheet Volume 1 Revision ET Number Description Date 001 Initial Release January 2011 Added Intel Core i7 2677M i7 2637M and i5 2557M 002 processors June 2011 Added Intel Celeron B800 and 847 processors 003 Added Intel Celeron 787 and 857 processors July 2011 004 Added Intel Celeron B710 processor July 2011 Added Intel Core i7 2960XM i7 2860QM i7 2760QM and i7 September 005 i7 2640M processors Added I
9. 30 2 4 1 1 35 Engine Execution 4 4 6 30 2 4 1 2 3D Pipeline eie ote aaa nne ced eet aa ete ERR EYE 30 2 4 1 3 Video ENGINE iere anette E AYER TETN 31 2 4 1 4 2DBnDglle d s eise tes ete en qua 31 2 4 2 Processor Graphics Display pe reet unen kiere RA 32 2 4 2 1 Display Pl nes eene entre dina enia en dic i BERE RE PA d ds 32 2 4 2 2 Display BID8S um Sua send KERN 33 2 4 2 3 Display aa er tangata hm 33 2 4 2 4 Embedded DisplayPort iniiaiee rera vasa n 33 2 4 3 Intel Flexible Display Interface Intel 2 2 33 2 4 4 Multi Graphics Controller Multi Monitor 34 2 5 Platform Environment Control Interface r 34 2 6 Interface Clocking enr e rn teur Pea De Jaca MERI Gea RE 34 2 6 1 Internal Clocking Requirements 34 Technologies nons n RR et a a a du De Rx a us 35 3 1 Intel virtualization Technology Intel VT nene 35 3 1 1 Intel Virtualization Technology Intel VT for IA 32 Intel 64 and Intel Architecture Intel ana ERR n ERO dened nen ce 35 3 1 2 Intel
10. 24 2 1 5 1 Just in Time Command 5 Y 24 2 1 5 2 COMMANG Overlap 24 2 1 5 3 Out of Order Scheduling 24 2 1 6 Memory Type Range Registers MTRRs Enhancement 24 2 1 7 Data Scrambling uuu a C n eR 24 2 1 8 DRAM Clock Generation a treten an a Rd 24 2 2 PCGCLExpress Interface eost Y nequa sa ga wasa 25 2 2 1 PCL Expr ss Architecture uiii a 25 2 2 1 1 Transaction LAYER 26 2 2 1 2 Data Link Layer aaa a axi RARE RE 26 2 2 1 3 Physical a 26 2 2 2 PCI Express Configuration Mechanism 12222 27 2 2 3 PCI Express 27 2 2 4 PCI Express Lanes nemen 28 2 3 Direct Media Interface 1 A 28 2 3 1 DMI Error FlOW PP 28 2 3 2 Processor PCH Compatibility 2 28 2 3 3 DMI Link DOWN 29 2 4 Processor Graphics Controller GT sana nana aa 29 Datasheet Volume 1 3 2 4 1 3D and Video Engines for Graphics Processing
11. processor TDO provides the serial output needed for JTAG Drai specification support pen Prat TMS TMS Test Mode Select A JTAG specification support signal used by I debug tools CMOS TRST TRST Test Reset This signal resets the Test Access Port TAP I logic TRST must be driven low during power on Reset CMOS Error and Thermal Protection Signals Table 6 12 Error and Thermal Protection Signals Sheet 1 of 2 Direction ntel Signal Name Description Buffer Type Catastrophic Error This signal indicates that the system has experienced a catastrophic error and cannot continue to operate The processor will set this for non recoverable machine check errors or other unrecoverable internal errors Datasheet Volume 1 CATERR On the processor CATERR is used for signaling the following types of o errors CMOS e Legacy MCERRs CATERR is asserted for 16 BCLKs Legacy IERRs CATERR remains asserted until warm or cold reset PECI Platform Environment Control Interface A serial sideband 1 0 PECI interface to the processor it is used primarily for thermal power and A h error management syhenronous Processor Hot PROCHOT goes active when the processor temperature monitoring sensor s detects that the processor has CMOS Input PROCHOT reached its maximum safe operating temperature This indicates that pu the processor Thermal Control Circuit T
12. 9299992999992929999992929090909599 A m 1 A E E 9 NI S 1 x 162 Datasheet Volume 1 Processor Pin and Signal Information Figure 8 21 Processor rPGA988B 2C GT1 Mechanical Package Sheet 1 of 2 a gt t 5 m 5 lt k m E 3 lt 5 lt o Lu le up lt 8 a 999 999 999 968 600000 6600 98 09900005 39809990900000090909 6000000 9999 0000000000000 6000000 00000 9000009000090900090 900000900 60000 600000000000000000000000000 660000 0000000000000000000000000000000000060 06000000000000000000000000000000000 ile 1 i gt d 4 E z be 5 2 E gt i i 3 M M ES E ui m 5
13. i saga Dr peser Da DRAKE CE 48 Coordination of Core Power States at the Package 51 Targeted Memory State Conditions ccccccsceceeececeeeaseceaeesececeeeececeneaeeeeaqaessaenaeeeenees 56 Thermal Design Power TDP Specifications r rr 65 Junction Temperature 5 2 4 7 44 1 121 memes 65 Package Turbo Parameters u uuu E REEL NOE SL SER AEN SR EUG 65 Idle Power Specifications eene enne nan heh hk n hanh w aaa ERRARE ERR NER nuda 67 Signal Description Buffer ertt nete 75 Memory Channel A Signals reri re en no awqawan saa RR C MEE n 76 Memory Channel B Signals rre a 77 Memory Reference and Compensation 77 Reset and Miscellaneous Signals 78 PCI Express Graphics Interface Signals enter 79 Embedded DisplayPort Signals sissien Aa a cat ane dada cage tidied 79 Intel Flexible Display Interface Intel 80 Direct Media Interface DMI Signals Processor to PCH Serial Interface
14. 6 9 Pcie e in the Package 11 6 8 Pre 2 in the Package _ 3 9 6 9 Po in the Package 3 8 6 9 Pcie 1 E in the Package 8 8 6 8 4 2 in the Package 3 1 6 9 Po in the Package 2 95 6 9 Pcie EI dad in the Package 6 4 6 8 Pce P in the Package 2 5 6 9 Pc the Package 2 35 6 9 Por E p in the Package 5 8 6 8 Pce 2 the Package _ 23 6 9 Idle power the Package _ 2 2 6 9 C7state Thermal Management Features Processor Package Thermal Features This section covers thermal management features for the entire processor complex including the processor core the graphics core and integrated memory controller hub and will be referred to as processor package or by simply the package Occasionally the package will operate in conditions that exceed its maximum allowable operating temperature This can be due to internal overheating or due to overheating in the entire system To protect itself and the system from thermal failure the package is capable of reducing its power consumption and thereby its temperature to attempt to remain within normal operating limits using the Adaptive Thermal Monitor Datasheet Volume 1 67 m Thermal Management intel Note 5 4 1 1 5 4 1 1 1 68 The Adaptive Thermal Monitor can be activated when any package temperature m
15. View Upper Right Quadrant 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 EM E Q 63 Q 59 Q 60 Q 56 Q 43 Q 42 MU ERES ESE g o SB D SB D SA D SA D 9161 01571 9 55 0149 SB_D SB_D PT SBD SBD SB D UA gt SA_D SA_D 4 SA D SA D SA D SB D SB D 2 95 7 9517 9151 5 9515 QS 5 Q 33 Q 32 VSS VSS S AM SA D SA D SA SA D Bam SA D AL Q 58 Q 60 Q 50 Q 53 Q 46 Q 47 Qs 4 SB D 0 SA_D BE 56 2 SA D SA D SA sa lt gt sa 0 SB_D NEM sa sa SA D SAD AJ Q 62 9 56 Q 54 0 49 EI Q 42 Q 40 Q 39 Q 38 SA 0 SA_D 899 SB_D SB_D 9 SA_D SA_D mE s SAD AH 9163 9 57 17 01551 Q 52 45 Q 44 MEI Q 37 Q 36 NES EMT o vss AG SAM gt VSS VSS VDDQ vss VDDQ AF C 9 AD SA RA SA_M SB_O SB_C SB_C SB_C s A 10 S 0 K 0 K 1 iren vss VSS VDDQ VSS VSS VDDQ VSS VSS VDDQ AC SB RA SB M SA C SAC AB s A 10 K 0 1 sB Bs sB M 5 sa AA 0 0 1 hr VSS VSS VDDQ VSS VSS VDDQ VSS
16. also known as CXSR a 57 4 6 2 Intel Graphics Performance Modulation Technology Intel 57 4 6 3 Graphics Render C State a aga men A MERE NIE MEER 57 4 6 4 Intel Smart 2D Display Technology Intel 525 58 4 6 5 Intel Graphics Dynamic Frequency nennen nnn nnne 58 4 6 6 Display Power Savings Technology 6 0 DPST 58 4 6 7 Automatic Display Brightness ADB a mem 59 4 6 8 Intel Seamless Display Refresh Rate Switching Technology Intel SDRRS Technology sese nS crx ez rx DA 59 4 7 Thermal Power 4 1 4 7444 444 senem nennen nnns 59 5 Thermal Management a a 61 5 1 Thermal Design Power TDP and Junction Temperature 61 5 2 Thermal Considerations u u u re a ER 61 5 2 1 Intel Turbo Boost Technology Power Control and 62 5 2 2 Package Power Control 55 u ends e eR A WEE apa Riesa COR EA e 63 5 2 3 Power Plane Control iced enirn than qa canes Ran ERE E 63 5 2 4 Turbo Time Parameter REA 63 5 3 Thermal and
17. 60 at 24 C 6 7 8 A prolonged or extended period of time 30 TiMsustained storage typically associated with customer shelf life 0 Months Months 7 term storage A short period of time 0 hours 72 hours Notes 1 Refers to a component device that is not assembled in a board or socket and is not electrically connected to a voltage reference or I O signal 2 Specified temperatures are not to exceed values based on data collected Exceptions for surface mount reflow are specified by the applicable JEDEC standard Non adherence may affect processor reliability 3 Tapsolute storage applies to the unassembled component only and does not apply to the shipping media moisture barrier bags or desiccant 4 Component product device storage temperature qualification methods may follow JESD22 A119 low temp and JESD22 A103 high temp standards when applicable for volatile memory 5 Intel branded products are specified and certified to meet the following temperature and humidity limits that are given as an example only Non Operating Temperature Limit 40 C to 70 C and Humidity 50 to 90 non condensing with a maximum wet bulb of 28 C Post board attach storage temperature limits are not specified for non Intel branded boards 6 The JEDEC J JSTD 020 moisture level rating and associated handling practices apply to all moisture sensitive devices removed from the moisture barrier bag 7 Nominal temperature and humidity c
18. 900000 6000 090094200 3 90000000000000000000000000000000000000 000000 000 000 969 059 000 020 969 059 040 000 000 0509000 0000 o 0 09 000 119130 335 9134 335 1H213H 1 3 W H H amr 160 intel 161 23 1336 5 9129 n deno ox une 9NIMVHO IVOINVHO3A 39V39Vd nu 1 mulis ost 2 EN Z z ac d 319415815 39409 0 1215 2 804 CIAO 131113 111353 MIIA 401 pee PE UE 595070002020900020209000092020001959200000502020000020200000 a 9 6 OoOo OoOo OoOo OPO OOO OoOo OoOo 000 0 0200 9800900000 3 5050 0 92920 005020509 0029 0209 00000000004 90000000004 A BEL DOM ood 2 2 5 See 00095920 02020 2020002020 gt 9595 O O O O
19. DDR3 SA 15 0 Memory Address These signals are used to provide the multiplexed MA 15 0 row and column address to the SDRAM DDR3 SDRAM Differential Clock Channel A SDRAM Differential clock signal SA CK 1 0 pair The crossing of the positive edge of SA CK and the negative edge of its complement SA_CK are used to sample the command and DDR3 control signals on the SDRAM SA CK 1 0 SDRAM Inverted Differential Clock Channel A SDRAM Differential 0 1 0 clock signal pair complement DDR3 Clock Enable 1 per rank These signals are used to e Initialize the SDRAMs during power up SA GKE 1 6 Power down SDRAM ranks DDR3 Place all SDRAM ranks into and out of self refresh during STR Chip Select 1 per rank These signals are used to select particular SA_CS 1 0 SDRAM components during the active state There is one Chip Select DDR3 for each SDRAM rank SA_ODT 1 0 On Die Termination Active Termination Control anes Datasheet Volume 1 Signal Description Table 6 3 6 2 Table 6 4 intel Memory Channel B Signals Signal Name Description Direction Buffer Type SB BSI2 0 Bank Select These signals define which banks are selected within B5 2 0 each SDRAM rank DDR3 Write Enable Control Signal This signal is used with SB_RAS and 0 SB CAS along with SB CS to define the SDRAM Commands DDR3 SB RAS RAS
20. 164 Datasheet Volume 1 intel Processor Pin and Signal Information Figure 8 23 Processor BGA1023 2C GT1 Mechanical Package Sheet 1 of 2 r TTT 9NIMYHO TVOINVHO3N mu N 19 25056 3931102 TT t 313 I 310 13013 1H913H 1H213H 08 149 3 5317 sv 0 0000000 9000 00000000000000000 099 90000 0099999999 9999999939 999099 8600000000 99900 99989995do o o 0 0 199000 0 o o o o oo o o oo 9o 555 00000009 900000000 9000000 50 99 00000000 00000 0000000 000000005 90000 s l 50 9009090909 9099900000000 22 oo 000000050 2909990000000 994 900000509 00000000 099 90099990000 55 0900005 naana 9099999 09 000000005 00000 00000000 6 0000099999090 504 9 0000000 9 o o o o o o 0 o b o o o o o 000000000 9d 5 900000000090000000000000000 00000000000000 0 0 0 0 0000 9 25920999 55002200052 50020000 99 0008 999099 0000 8000000 99 09 9999 000900 9000 og 9 900 900 2999 000000 9000 25 0909 90990
21. 2 Interface does not support ULV LV memory modules or ULV LV DIMMs Datasheet Volume 1 21 intel 2 1 2 Table 2 2 2 1 3 2 1 3 1 2 1 3 2 Note 22 Interfaces System Memory Timing Support The IMC supports the following DDR3 Speed Bin CAS Write Latency CWL and command signal mode timings on the main memory interface tc CAS Latency Activate Command to READ or WRITE Command delay tgp PRECHARGE Command Period e CWL CAS Write Latency Command Signal modes in indicates a new command may be issued every clock and 2n indicates a new command may be issued every 2 clocks Command launch mode programming depends on the transfer rate and memory configuration DDR3 System Memory Timing Support MCI tCL tRCD tRP CWL CMD M MT s tCK tCK tCK tCK Mode eae 1066 7 7 7 6 1n 2n hu 1333 9 9 9 7 in 2n Quad Core SV 1600 11 11 8 inm Dual SV 1066 7 7 6 1n 2n Low voltage and Ultra low 8 8 8 6 1n 2n voltage 1333 9 9 9 P TE Notes 1 System memory timing support is based on availability and is subject to change System Memory Organization Modes The IMC supports two memory organization modes single channel and dual channel Depending upon how the DIMM Modules are populated in each memory channel a number of different configurations can exist Single Channel Mode In this mode all memory cycles are directed to a
22. 29020 0000000000 k 12550 0550000606000660002060606666 9255500 8 8 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000000 decoro 02000200999 ao o o o o o 55526209 SR 6060000 d 020909000050000050005000005000005000505000005000500000500000000 2 3 0 0 0 0 a o s SU SO SD NOS RO IO S SOOO SU RIO RR EH 53449 13 1 271 87311 133 39 er Figure 8 19 Processor BGA1224 4C GT2 Mechanical Package Sheet 1 of 2 Processor Pin and Signal Information Datasheet Volume 1 Processor Pin and Signal Information intel Figure 8 20 Processor BGA1224 4C GT2 Mechanical Package Sheet 2 of 2 1 522022222 202020 6 50 0 0 0 062656060 9 OoOO OoOo 0200000900000 o o o o o o 0950005900000 0 0 0 O O O O O O O O 0 0 07076000 0000000000 00 00 0 o o o 9 0 0 0 0 0 0 0 02020202090 972020 5600 50500050000 070202020 o C 02090
23. 80 Phase Lock Loop PLL Signalsu dieci onte ER UK eases dx NERA UA 80 Test Access Points TAP 5 2 4 1 nens 81 Error and Thermal Protection Signals nr 81 Power Sequencing Signals A 82 Processor Power 82 Sense Signals Dj a AM FUR D qawa AR 83 Ground and Non Critical to Function NCTF Signals 83 Future Compatibility Signals errechnet ne ka yeu pasaq qawa qaa Dua ada 84 Processor Internal Pull Up Pull Down Resistors emm 84 IMVP7 Voltage Identification Definition een nemen nen 87 VGCSA VID configuration aid kk a inne RR RR EROR EE EA EI saint 90 Signal M 91 Storage Condition RatiNgS er A a 94 Processor Core Vcc Active and Idle Mode DC Voltage and Current Specifications 95 Processor Uncore Supply DC Voltage and Current Specifications 96 Memory Controller Supply DC Voltage and Current Specifications 97 System Agent VccsA Supply DC Voltage and Current 5 97 Processor PLL Supply DC Voltage and Current Specifications
24. AR6 2011 SA DQ 55 AN12 AP52 BC58 DQ55 SA DQ 14 G8 AT13 AW6 DQ13 SA DQ 56 114 57 AW58 DQ58 SA DQ 15 G7 AU13 AT9 DQ12 SA DQ 57 AH14 AN53 AY59 DQ56 SA DQ 16 K4 BC7 2018 SA DQ 58 AL15 AG56 AL60 DQ60 SA DQ 17 K5 BB7 DQ20 SA DQ 59 15 AG53 AP61 DQ61 SA DQ 18 Ki BA13 BG6 DQ22 SA DQ 60 AL14 AN55 AW60 DQ57 SA DQ 19 21 BB11 AY9 DQ21 SA DQ 61 14 AN52 AY57 DQ59 SA DQ 20 J5 BA7 AW8 DQ16 SA DQ 62 15 55 AN60 DQ63 SA DQ 21 J4 BA9 BB7 DQ17 SA_DQ 63 AH15 AK56 AR60 DQ62 SA_DQ 22 12 BBO BC8 DQ19 SA 23 K2 AY13 BE4 DQ23 SA DQ 24 M8 14 AW12 DQ27 SA DQ 25 N10 AR14 11 20925 SA DQ 26 N8 AY17 BB11 DQ30 SA_DQ 27 N7 AR19 BA12 DQ31 SA_DQ 28 M10 BA14 BE8 DQ24 SA_DQ 29 M9 AU14 BA10 DQ26 SA_DQ 30 N9 BB14 BD11 DQ28 SA_DQ 31 M7 BB17 BE12 DQ29 SA_DQ 32 AG6 BA45 BB49 DQ35 SA_DQ 33 5 AR43 AY49 DQ32 SA DQ 34 AK6 AW48 BE52 DQ38 SA_DQ 35 5 BC48 BD51 DQ39 SA DQ 36 5 BC45 BD49 DQ33 SA DQ 37 AH6 AR45 BE48 DQ36 SA DQ 38 A15 AT48 BA52 DQ34 SA DQ 39 AJ6 AY48 AY51 DQ37 SA DQ 40 AJ8 BA49 BC54 DQ42 SA DQ 41 AK8 AV49 AY53 DQ43 168 Datasheet Volume 1 DDR Data Swizzling Table 9 2 DDR Data Swizzling Table Channel B Pin Pin Pin MC Pin Name Number Number Number Pin rPGA BGA1023 BGA1224 Name SB DQ O0 C9 AL4 AL4 DQ03 SB_DQ 1 A7 2002 S
25. Buffer Type Datasheet Volume 1 VSS Processor ground node GND VSS_NCTF Non Critical to Function These pins are for package mechanical BGA Only reliability DC TEST xx Daisy Chain These pins are for solder joint reliability and non critical to function For BGA only 83 intel 6 15 Signal Description Future Compatibility Signals Table 6 17 Future Compatibility Signals 6 16 Signal Name Description Direction Buffer Type PROC SELECT This pin is for compatibility with future platforms A pull up resistor to is required if connected to the DF TVS strap on the PCH SA DIMM VREFDQ SB DIMM VREFDQ Memory Channel A B DIMM DQ Voltage Reference These signals are not used by the processors and are for future compatibility only No connection is required VCCIO SEL Voltage selection for VCCIO This pin must be pulled high on the motherboard when using dual rail voltage regulator which will be used for future compatibility VCCSA VID 0 Voltage selection for VCCSA This pin must have a pull down resistor to ground Table 6 18 Processor Internal Pull Up Pull Down Resistors 84 Processor Internal Pull Up Pull Down Resistors Signal Name Pull Up Pull Down Rail Value BPM 7 0 Pull Up VCCIO 65 165 Q PRDY Pull Up VCCIO 65 1650 Pull Up VCCIO 65 165 Q TCK Pull Down VSS 5 15 kQ TDI Pull Up VCCIO 5 15 k
26. Pipe A gt Control lt Display A Planes amp VGA Display Display Port Control Display Arbiter Memory Host Interface Outside of Display Engine PCH Display Engine Display Planes A display plane is a single displayed surface in memory and contains one image desktop cursor overlay It is the portion of the display hardware logic that defines the format and location of a rectangular region of memory that can be displayed on display output device and delivers that data to a display pipe This is clocked by the Core Display Clock Planes A and B Planes A and B are the main display planes and are associated with Pipes A and B respectively The two display pipes are independent allowing for support of two independent display streams They are both double buffered which minimizes latency and improves visual quality Sprite A and B Sprite A and Sprite B are planes optimized for video decode and are associated with Planes A and B respectively Sprite A and B are also double buffered Datasheet Volume 1 Interfaces 2 4 2 1 3 2 4 2 1 4 2 4 2 2 2 4 2 3 2 4 2 4 2 4 3 Cursors A and B Cursors A and B are small fixed sized planes dedicated for mouse cursor acceleration and are associated with Planes A and B respectively These planes support resolutions up to 256 x 256 each Video Graphics
27. is changed during runtime it may take a period of time possibly up to approximately 3 to 5 times the Turbo Time Parameter depending on the magnitude of the change and other factors for the algorithm to settle at the new control limits Datasheet Volume 1 63 5 3 64 intel Thermal Management Thermal and Power Specifications The following notes apply to Table 5 1 Table 5 2 Table 5 3 and Table 5 4 Notes Description The TDPs given are not the maximum power the processor can generate Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained periods of time TDP workload may consist of a combination of a CPU core intensive and a graphics core intensive applications The thermal solution needs to ensure that the processor temperature does not exceed the maximum junction temperature Tj max limit as measured by the DTS and the critical temperature bit The processor junction temperature is monitored by Digital Temperature Sensors DTS For DTS accuracy refer to Section 5 4 1 2 1 Digital Thermal Sensor DTS based fan speed control is required to achieve optimal thermal performance Intel recommends full cooling capability well before the DTS reading reaches Tj Max An example of this is Tj Max 10 C The idle power specifications are not 100 tested These power specifications are determined by
28. 123 2 17 1 3 3 Memory Controller iieri da ides needs RR Ra 17 1 3 4 PGLEXpresS nurse nue ERA E 17 1 3 5 Direct Media Interface 17 1 3 6 Processor Graphics 41 1 18 1 44 Thermal Management Support 21 2 1 1 1 nns 18 145 5 5 18 1 6 Terminology uo 18 1 7 Related Doc rmnents eere esto dre RE aka baa 20 2 21 2 1 System Memory Interface cccccssccecseeceeeeseneneedeanatercenaeeseeeeeeeeeeeeeeneaseaesseneeeenneen 21 2 1 1 System Memory Technology Supported r 21 2 1 2 System Memory Timing 0 Hee 22 2 1 3 System Memory Organization Modes r 22 2 1 3 1 Single Channel MOde c cccccccsseeseeeseaeaeeecanteeeeeeteaeeeeneavensenensasaees 22 2 1 3 2 Dual Channel Mode Intel Flex Memory Technology Mode 22 2 1 4 Rules for Populating Memory 11 1 1 23 2 1 5 Technology Enhancements of Intel Fast Memory Access Intel
29. 2 3 Reference diee ean aa Ni DE ca han dnd 34 4 1 5 P 44 4 2 Processor Core Package State 44 4 3 Integrated Memory Controller States 1 0 44 4 4 PCL Express LINK States unie la a cad abide an en huay DA Rn qashan 45 4 5 Direct Media Interface DMI States u aaa 45 Datasheet Volume 1 7 3 em EE o X d do WS Pod N 00 NJ N SN SN SS S S SS O O O O O O UUU 1 NJ HL QJ NJ HL N O UI N R R ER R R O IJ OO Q N Processor Graphics Controller States cassi rirse 45 G S C State 0 44 2 45 D 5 and State Combination do cen ice tav edness aah RR Gade ead 46 Coordination of Thread Power States at the Core Level 0 nr nn 48 to MWAIT COnVersiOn iecit pire e Exec
30. 7 2 1 Voltage Rail Decoupling aaa 85 7 2 2 PLL Power SUPPLY axes NA a I RI RE E UK 85 7 3 Voltage Identification a e RANA RR 4a 86 7 4 System Agent SA VID aldni 90 7 5 Reserved or Unused Signals uuu ga nnn reg 90 7 6 Signal GOUD 91 7 77 TestAccess Port Connection a cokers 93 7 8 Storage Condition Specifications rr 93 7 9 DC Specifications metere da D Fd Da RR RE 94 7 9 1 Voltage and Current Specifications 95 7 10 Platform Environmental Control Interface PECI DC Specifications 101 7 1021 PECI Bus Architect re orator pe ct ORIS ua papap ace dies ki a RARE 101 7 10 2 PECI DC Characteristics eene eere erreur heh enr ekle ae a RI HR X ERA 102 7 10 3 Input Device 5 uu u a 103 Processor Pin and Signal Information 105 8 1 Processor Pin RE 105 8 2 Package Mechanical Information 41 1 44442 4 44 1 155 DDR breed r
31. 79 Signal Description intel 6 6 Intel Flexible Display Interface Intel FDI Signals Table 6 8 Intel Flexible Display Interface Intel FDI Signal Name Description FDIO_TX 3 0 Intel Flexible Display Interface Transmit Differential Pair FDIO_TX 3 0 Pipe FDI FDIO FSYNC O Intel Flexible Display Interface Frame Sync Pipe A FDI0_LSYNC 0 Intel Flexible Display Interface Line Sync Pipe eus FDI1 TX 3 0 Intel Flexible Display Interface Transmit Differential Pair 1 4 3 0 Pipe B FDI FDI1_FSYNC 1 Intel Flexible Display Interface Frame Sync Pipe FDI1 LSYNC 1 Intel Flexible Display Interface Line Sync Pipe B Bice Intel Flexible Display Interface Hot Plug Interrupt I FDI INT Asynchronous CMOS 6 7 Direct Media Interface DMI Signals Table 6 9 Direct Media Interface DMI Signals Processor to PCH Serial Interface Signal Name Description Ruhe Dodo DMI RX 3 0 DMI Input from PCH Direct Media Interface receive differential pair I DMI_RX 3 0 DMI DMI_TX 3 0 DMI Output to PCH Direct Media Interface transmit differential pair DMI_TX 3 0 DMI 6 8 Phase Lock Loop PLL Signals Table 6 10 Phase Lock Loop PLL Signals Direction 80 Signal Name Description Buffer Type BCLK Differential bus clock input to the processor I BCLK Diff Clk DPLL
32. AN2 DDR3 10 SB_MA 4 T2 DDR3 SB_DQ 38 AN1 DDR3 10 SB_MA 5 T4 DDR3 SB_DQ 39 AP2 DDR3 I O SB MA 6 T3 DDR3 SB_DQ 40 AP5 DDR3 7 SB_MA 7 R2 DDR3 SB_DQ 41 AN9 DDR3 10 SB_MA 8 T5 DDR3 SB_DQ 42 AT5 DDR3 1 0 SB_MA 9 R3 DDR3 SB_DQ 43 AT6 DDR3 1 0 SB_MA 10 AB7 DDR3 SB_DQ 44 AP6 DDR3 10 SB MA 11 R1 DDR3 SB DQ 45 AN8 DDR3 1 0 SB_MA 12 Ti DDR3 SB_DQ 46 DDR3 1 0 SB_MA 13 AB10 DDR3 SB_DQ 47 AR5 DDR3 1 0 SB_MA 14 R5 DDR3 SB_DQ 48 ARQ DDR3 1 0 SB_MA 15 R4 DDR3 SB_DQ 49 AJ11 DDR3 I O SB_ODT 0 AE4 DDR3 SB_DQ 50 AT8 DDR3 10 SB_ODT 1 AD4 DDR3 SB_DQ 51 AT9 DDR3 1 0 SB_RAS AB8 DDR3 SB_DQ 52 AH11 DDR3 1 0 SB_WE AB9 DDR3 SB_DQ 53 8 DDR3 10 SKTOCC AN34 Analog SB_DQ 54 AJ12 DDR3 10 SM_DRAMPWROK vs Asynch CMOS 1 SB_DQ 55 AH12 DDR3 1 0 SM_DRAMRST R8 DDR3 SB_DQ 56 AT11 DDR3 I O SM_RCOMP 0 AK1 Analog I O SB_DQ 57 AN14 DDR3 I O SM_RCOMP 1 A5 Analog I O SB_DQ 58 AR14 DDR3 10 SM_RCOMP 2 A4 Analog 1 0 SB_DQ 59 AT14 DDR3 10 SM_VREF Analog I SB_DQ 60 AT12 DDR3 I O TCK AR26 CMOS I SB DQ 61 AN15 DDR3 10 TDI AR28 CMOS I SB_DQ 62 AR15 DDR3 I O TDO AP26 CMOS SB_DQ 63 AT15 DDR3 1 0 THERMTRIP AN32 Asynch CMOS SB_DQS 0 D7 DDR3 10 TMS AR27 CMOS I SB_DQS 1 F3 DDR3 10 TRST AP30 CMOS I SB_DQS 2 K6 DDR3 10 UNCOREPWRGOOD AP33 Asynch CMOS I SB DQS 3 N3 DDR3 10 VAXG AH17 PWR SB_DQS 4 AN5 DDR3 1 0 VAXG AH18 PWR SB_DQS 5 AP9 DDR3 10 VAXG AH20 PWR SB_DQ
33. Datasheet Volume 1 163 intel Processor Pin and Signal Information Figure 8 22 Processor rPGA988B 2C GT1 Mechanical Package Sheet 2 of 2 DNE UN E E EL E6154 1 600000000000000000000000000000000000 i 000000000000000000000000000000000000 90009099909090999009909000090000099090 900000000000000000000000000000000000 000000000000000000000000000000000000 90000000000000000000000000000000000 000000000000000000000000000000000000 00999000 600000000 000000000 660000000 999900009 900000009 000000000 90000990009 990000000 900000000 000000000 999990009 900000000 000000000 000000000 000000000 600000000 00000000 RENS _ 0000000069 00000000 000000000000000000000000000000000000 F890000000000000000000000000000000000 000000000000000000000000000000000000 999999999999999999000999222999999999 o 999000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 E 000000000000000000000000000000000000 000000000000060000000000000000000 AME AU SEE DETAIL 8 DETAIL C VIEW BOTTON VIEW SEE DETAIL B WERT NOE
34. Datasheet Volume 1 5 em 5 6 5 Embedded DisplayPort EDP 79 6 6 Intel Flexible Display Interface Intel FDI 5 80 6 7 Direct Media Interface DMI 5 0 80 6 8 Phase Lock Loop PLL Signals eerie tnn tnn 80 6 9 Test Access Points TAP Signals a Rak va RE MR 81 6 10 Error and Thermal Protection 1 11 81 6 11 Power Sequencing Signals oer ses cans ne De be Sas kasaq 82 6 12 Processor Power Signals ua Wasa rock e ERR San ERES 82 6 13 Sense Signal Srp CE 83 6 14 Ground and Non Critical to Function NCTF Signals 83 6 15 Future Compatibility 5 4 1 1 eres eese 84 6 16 Processor Internal Pull Up Pull Down Resistors 2 4 3 84 Electrical Specifications 85 7A Powerand Ground Pins nadie RA 85 7 2 Decoupling Guidelines nn ken GA RR 85
35. F35 PCIe I PEG TX 8 J27 PCIe _ 10 4 1 PEG_TX 9 H28 PCIe _ 11 2 1 PEG_TX 10 G28 PCIe PEG_RX 12 D33 PCIe I PEG TX 11 E28 PCIe _ 13 D31 PCIe I PEG TX 12 F28 PCIe _ 14 33 PCIe I PEG TX 13 D27 PCIe PEG_RX 15 C32 PCIe I PEG TX 14 E26 PCIe PEG_RX 0 133 PCIe I PEG TX 15 D25 PCIe PEG RX 1 L35 PCIe I PM SYNC AM34 Asynch CMOS I PEG_RX 2 K34 PCIe I PRDY 29 Asynch 5 PEG RX 3 H35 PCIe I PREQ 27 Asynch 5 1 PEG_RX 4 H32 PCIe I PROC SELECT C26 N A PEG_RX 5 G34 PCIe I PROCHOT AL32 Asynch CMOS PEG_RX 6 G31 PCIe I RESET AR33 Asynch CMOS I PEG RX 7 F33 PCIe I RSVD C30 PEG RX 8 F30 PCIe I RSVD A31 PEG RX 9 E35 PCIe I RSVD B30 PEG RX 10 E33 PCIe I RSVD B29 PEG RX 11 F32 PCIe I RSVD D30 PEG RX 12 D34 PCIe I RSVD B31 PEG RX 13 E31 PCIe I RSVD A30 PEG RX 14 C33 PCIe I RSVD C29 PEG RX 15 B32 PCIe I RSVD F25 PEG 0 M29 PCIe RSVD F24 PEG_TX 1 M32 PCIe RSVD F23 PEG_TX 2 M31 PCIe RSVD D24 PEG_TX 3 L32 PCIe RSVD G25 PEG_TX 4 L29 PCIe RSVD G24 PEG_TX 5 K31 PCIe RSVD E23 PEG_TX 6 K28 PCIe RSVD D23 PEG_TX 7 J30 PCIe RSVD AT26 PEG_TX 8 J28 PCIe RSVD AG7 PEG_TX 9 H29 PCIe RSVD AE7 PEG TX 10 G27 PCIe RSVD w8 PEG_TX 11 E29 PCIe RSVD T8 PEG TX 12 F27 PCIe RSVD L7 PEG_TX 13 D28 PCIe 0 RSVD J20 PEG_TX 14 F26 PCIe RSVD J16 PE
36. Graphics Power Management Intel Rapid Memory Power Management Intel RMPM also known as CxSR The Intel Rapid Memory Power Management puts rows of memory into self refresh mode during C3 C6 C7 to allow the system to remain in the lower power states longer Mobile processors routinely save power during runtime conditions by entering the C3 C6 or C7 state Intel RMPM is an indirect method of power saving that can have a significant effect on the system as a whole Intel Graphics Performance Modulation Technology Intel GPMT Intel Graphics Power Modulation Technology Intel GPMT is a method for saving power in the graphics adapter while continuing to display and process data in the adapter This method will switch the render frequency and or render voltage dynamically between higher and lower power states supported on the platform based on render engine workload When the system is running in battery mode and if the end user launches applications such as 3D or Video the graphics software may switch the render frequency dynamically between higher and lower power performance states depending on the render engine workload In products where Intel Graphics Dynamic Frequency also known as Turbo Boost Technology is supported and enabled the functionality of Intel GPMT will be maintained by Intel Graphics Dynamic Frequency also known as Turbo Boost Technology Graphics Render C State Render C State RC6 is a technique des
37. MWAIT C7 C7 No sub states allowed The BIOS can write to the C state range field of the PMG_IO_CAPTURE MSR to restrict the range of I O addresses that are trapped and emulate MWAIT like functionality Any P_LVLx reads outside of this range does not cause an I O redirection to MWAIT Cx like request They fall through like a normal I O instruction When P_LVLx I O instructions are used MWAIT substates cannot be defined The MWAIT substate is always zero if I O MWAIT redirection is used By default P_LVLx I O redirections enable the MWAIT break on EFLAGS IF feature that triggers a wakeup on an interrupt even if interrupts are masked by EFLAGS IF Datasheet Volume 1 Power Management intel 4 2 4 4 2 4 1 4 2 4 2 4 2 4 3 4 2 4 4 4 2 4 5 Core C states The following are general rules for all core C states unless specified otherwise core C State is determined by the lowest numerical thread state such as Thread 0 requests C1E while Thread 1 requests C3 resulting in a core C1E state See Table 4 7 A core transitions to CO state when An interrupt occurs There is an access to the monitored address if the state was entered using an MWAIT instruction e For core C1 C1E core C3 and core C6 C7 an interrupt directed toward a single thread wakes only that thread However since both threads are no longer at the same core C state the core resolves to CO A system reset re initia
38. Package a d cans induit kgs SERIE ARR RU DU cade 50 4 2 5 1 Package CU su EX REA ERU akawa 51 4 2 5 2 Package asan dead canes EXER REA 52 4 2 5 3 Package C3 State a suse ee easet DR RR aaa q 52 4 2 5 4 Package C6 State uuu sity ingre menie tasa 52 4 2 5 5 Package C7 State u u a ir 53 4 2 5 6 Dynamic Cache Sizing enhn sen nnn nhanh nan nnn 53 4 3 Integrated Memory Controller IMC Power Management 53 4 3 1 Disabling Unused System Memory Outputs r 53 4 3 2 DRAM Power Management and Initialization 54 4 3 2 1 Initialization Role of CKE uu sinna tana die 55 4 3 2 2 Conditional Self Refresh esee sese naa ka sas qua na nna ann Ra 55 4 3 2 3 Dynamic Power down Operation 56 4 3 2 4 DRAM Power Management memes 56 4 4 PCI Express Power Man agernent a sassa ssssssssassrsssnqasasasasssasassasassssaaa 56 4 5 Direct Media Interface DMI Power Management 1 56 4 6 Graphics Power Management 0000000 00 nenna 57 4 6 1 Intel Rapid Memory Power Management Intel RMPM
39. Parameter POWER_LIMIT_1_TIME in N A 1 N A 5 14 package TURBO_POWER_LIMIT MSR 0610h bits 23 17 Extreme Long duration turbo power limit Edition Long P POWER_LIMIT_1 in 10 12 13 N A N A w package TURBO_POWER_LIMIT MSR 0610h 14 bits 14 0 Short duration turbo power limit Short P POWER LIMIT 2 in 10 14 package TURBO POWER LIMIT MSR 0610h NA e 15 bits 46 32 Datasheet Volume 1 65 Thermal Management intel Table 5 3 Package Turbo Parameters Sheet 2 of 2 Segment Package Turbo Parameter i Notes Processor turbo long duration time TurboTime Window Parameter POWER LIMIT 1 TIME in E package TURBO POWER LIMIT MSR 0610h bits 23 17 dC Long duration turbo power limit Quad Core POWER_LIMIT_1 in 10 12 13 package TURBO_POWER_LIMIT MSR 0610h 14 bits 14 0 Short duration turbo power limit Short POWER LIMIT 2 in 1 25 x45 10 14 package TURBO POWER LIMIT MSR 0610h 15 bits 46 32 Processor turbo long duration time Turbo Time Window Parameter POWER LIMIT 1 TIME in package TURBO_POWER_LIMIT MSR 0610h bits 23 17 Babe Long duration turbo power limit HS Long POWER_LIMIT_1 in 10 12 package TURBO_POWER_LIMIT MSR 0610h 13 14 bits 14 0 Short duration turbo power limit Short POWER LIMIT 2 in 1 25 x 35 10 14
40. SB_DQ 45 AN8 BG54 BG54 DQ42 SB_DQ 46 AR6 BA58 BG58 DQ45 SB_DQ 47 AR5 AW59 BF59 DQ41 SB_DQ 48 AR9 AW58 BA64 DQ51 SB_DQ 49 AJ11 AU58 BC62 DQ49 SB_DQ 50 AT8 AN61 AU62 DQ52 SB_DQ 51 AT9 AN59 AW64 DQ48 SB_DQ 52 AH11 AU59 BA62 DQ53 SB_DQ 53 AR8 AU61 BC64 DQ50 SB_DQ 54 AJ12 AN58 AU64 DQ55 SB_DQ 55 AH12 AR58 AW62 DQ54 SB_DQ 56 AT11 AK58 AR64 DQ56 SB_DQ 57 AN14 AL58 AT65 DQ58 SB_DQ 58 AR14 AG58 AL64 DQ61 SB_DQ 59 AT14 AG59 AM65 DQ62 SB_DQ 60 AT12 AM60 AR62 DQ57 SB_DQ 61 AN15 AL59 AT63 DQ59 SB_DQ 62 AR15 AF61 AL62 DQ63 SB_DQ 63 AT15 AH60 AM63 DQ60 88 169 DDR Data Swizzling 170 Datasheet Volume 1
41. VDDQ AY27 PWR VDDQ AN33 PWR VDDQ AY23 PWR VDDQ AN30 PWR VDDQ AV46 PWR VDDQ AN26 PWR VDDQ AV42 PWR VDDQ AN24 PWR VDDQ AV40 PWR VDDQ AL46 PWR VDDQ AV36 PWR VDDQ AL42 PWR VDDQ AV34 PWR VDDQ AL40 PWR VDDQ AV29 PWR VDDQ AL36 PWR VDDQ AV27 PWR VDDQ AL34 PWR VDDQ AU45 PWR VDDQ AL29 PWR VDDQ AU43 PWR VDDQ AL27 PWR VDDQ AU39 PWR VDDQ_SENSE AY19 Analog VDDQ AU37 PWR VIDALERT B51 CMOS I VDDQ AU33 PWR VIDSCLK D51 CMOS VDDQ AU30 PWR VIDSOUT A50 CMOS I O VDDQ AU26 PWR VSS BJ56 GND VDDQ AU24 PWR VSS BJ52 GND Datasheet Volume 1 Processor Pin and Signal Information Table 8 2 BGA1224 Processor Ball List by Ball Name intel Table 8 2 BGA1224 Processor Ball List by Ball Name Datasheet Volume 1 Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type bir VSS BJ48 GND VSS BC40 GND VSS BJ40 GND VSS BC36 GND VSS BJ32 GND VSS BC32 GND VSS BJ24 GND VSS BC28 GND VSS BJ20 GND VSS BC26 GND VSS BJ16 GND VSS BC24 GND VSS BJ12 GND VSS BC20 GND VSS BJ8 GND VSS BC16 GND VSS BG60 GND VSS BC12 GND VSS BG56 GND VSS BB65 GND VSS BG52 GND VSS BB63 GND VSS BG48 GND VSS BB47 GND VSS BG44 GND VSS BB39 GND VSS BG36 GND VSS BB9 GND VSS BG28 GND VSS BB5 GND VSS BG24 GND VSS BA58 GND VSS BG20 GND VSS BA54 GND VSS BG16 GND VSS BA50 GND VSS BG12 GND VSS BA46 GND VSS BG8 GND VSS BA42 GND VSS BF5
42. VSS AB5 GND VSS N35 GND VSS AA57 GND VSS N28 GND VSS AA17 GND VSS N22 GND VSS AA15 GND VSS M57 GND VSS AA12 GND VSS M50 GND VSS Y65 GND vss M44 GND vss Y63 GND vss M38 GND vss Y61 GND VSS M31 GND VSS Y7 GND VSS M25 GND VSS Y3 GND VSS M19 GND VSS Yi GND VSS M7 GND VSS w57 GND VSS M3 GND VSS V16 GND VSS 1 GND VSS V14 GND VSS L64 GND VSS Vil GND VSS L62 GND VSS v9 GND VSS L60 GND VSS V5 GND VSS L58 GND VSS U64 GND VSS L54 GND VSS U62 GND VSS L50 GND VSS U60 GND vss L46 GND vss U57 GND VSS L42 GND VSS T7 GND VSS L36 GND VSS T3 GND VSS L30 GND VSS GND VSS L24 GND VSS R57 GND VSS L20 GND VSS R50 GND VSS L16 GND 137 m e n tel Processor Pin and Signal Information Table 8 2 BGA1224 Processor Ball Table 8 2 BGA1224 Processor Ball List by Ball Name List by Ball Name Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VSS L12 GND VSS E52 GND VSS L8 GND VSS E48 GND VSS K39 GND VSS E46 GND VSS K33 GND VSS E42 GND VSS K27 GND VSS E36 GND VSS K1 GND VSS E30 GND VSS J64 GND VSS E24 GND VSS J60 GND VSS E22 GND VSS J56 GND VSS E18 GND VSS J52 GND VSS E14 GND VSS J48 GND VSS E10 GND VSS J46 GND VSS E6 GND VSS J42 GND VSS E4 GND VSS J36 GND VSS D63 GND VSS J30 GND VSS D39 GND VSS J24 GND VSS D33 GND VSS J22 GND VSS D27 GND VSS J18 GND VSS C58 GND VSS J14 GND VSS C54 GND VSS J10 GND VSS c50 GND VSS
43. cooo co 0090000000 9999 900080009 2 99000000000 9950000995 sas 0000 0050000009 00000000000 0059000090 3 50000009000 00599009 9 5560 902999000 0000000 o pre 00000902 00000000 0000 9950000660 909 00500009056 9 000009000 0050000550 2 0000 _ 205000 00 T cooooooooo 2009 00000000 0000 2 0909000000000 2000000000 2 0 0 000900000008 9 9 9 99 0000 909 09 000000000000000000000 0000000 25 900906 00099909 oo oo B 992 2990000 000009000 0000900 600008000 0000 60008000 9000000095 09550095 00999999 9990000 000090000 0000000 09000000 999 00000 600 00009000 000 99 0 0 900000000000000000000000009000 0000 909 969 050 050 909 059 0 0 0500 OQ 0000 000 009 lt n oo 1 ui os 3 NE NR 7 1 7 I rM NDE 166 Datasheet Volume 1 DDR Data Swizzling inte 9 DDR Data Swizzling To achieve better memory performance and better memory timing Intel design performed the DDR Data pin swizzling which will allow a better use of the product across different platforms Swizzling has no effect on functional op
44. page these requests would be launched in a back to back manner to make optimum use of the open memory page This ability to reorder requests on the fly allows the IMC to further reduce latency and increase bandwidth efficiency Memory Type Range Registers MTRRs Enhancement The processor has 2 additional MTRRs total 10 MTRRs These additional MTRRs are specially important in supporting larger system memory beyond 4 GB Data Scrambling The memory controller incorporates a DDR3 Data Scrambling feature to minimize the impact of excessive di dt on the platform DDR3 VRs due to successive 1s and Os on the data bus Past experience has demonstrated that traffic on the data bus is not random and can have energy concentrated at specific spectral harmonics creating high di dt that is generally limited by data patterns that excite resonance between the package inductance and on die capacitances As a result the memory controller uses a data scrambling feature to create pseudo random patterns on the DDR3 data bus to reduce the impact of any excessive di dt DRAM Clock Generation Every supported DIMM has two differential clock pairs There are a total of four clock pairs driven directly by the processor to two DIMMs Datasheet Volume 1 Interfaces 2 2 2 2 1 PCI Express Interface This section describes the PCI Express interface capabilities of the processor See the PCI Express Base Specification for details of PCI Express The pro
45. processor core flushes pending cycles and then enters all SDRAM ranks into self refresh The CKE signals remain LOW so the SDRAM devices perform self refresh Datasheet Volume 1 55 intel Table 4 12 Targeted Memory State Conditions 4 3 2 3 4 3 2 4 4 4 Note Note 4 5 56 Power Management Dynamic Power down Operation Mode Memory State with Processor Graphics Memory State with External Graphics CO C1 C1E Dynamic memory rank power down based on Dynamic memory rank power down based on ase idle conditions idle conditions If the Processor Graphics engine is idle and If there are no memory requests then enter there are no pending display requests then self refresh Otherwise use dynamic C3 C6 C7 enter self refresh Otherwise use dynamic memory rank power down based on idle memory rank power down based on idle conditions conditions S3 Self Refresh Mode Self Refresh Mode S4 Memory power down contents lost Memory power down contents lost Dynamic power down of memory is employed during normal operation Based on idle conditions a given memory rank may be powered down The IMC implements aggressive CKE control to dynamically put the DRAM devices in a power down state The processor core controller can be configured to put the devices in active power down CKE de assertion with open pages or precharge power down CKE de assertion with all pages closed Precharge power down provides grea
46. 0 65 0 9 ULV 0 65 0 9 Vec Vcc for processor core 0 3 1 5 V 2 3 XE 97 c SV QC 94 oe Processor Core SV DC _ E 53 A 4 6 8 2 Lv 43 ULV 33 XE 62 SV QC 52 Thermal Design Icc SV DC 36 A 5 6 8 LV 25 ULV 21 5 XE 31 SV QC 28 Icc_LFM Icc at LFM SV DC T TS 11 6 A 5 LV 17 6 ULV 12 5 XE 6 SV QC 5 5 Ic6 c7 Icc at C6 C7 Idle state SV DC 2 5 A 10 LV 3 8 ULV 2 6 PSO 15 TOLycc Voltage Tolerance PS1 12 mV 7 9 PS2 PS3 11 5 PSO amp 15 Icc gt TDC 30 PSO amp 10 Icc lt Ripple Ripple Tolerance TDC 30 mV 7 9 PS1 13 PS2 7 5 18 5 PS3 7 5 27 5 VR Step VID resolution 95 Electrical Specifications intel Table 7 5 Processor Core Vcc Active and Idle Mode DC Voltage and Current Specifications Sheet 2 of 2 Symbol Parameter Segment Min Typ Max Unit Note XE 1 9 SV QC 1 9 SLOPE Processor Loadline SV DC 1 9 mQ LV 2 9 ULV 2 9 Notes 1 Unless otherwise noted all specifications in this table are based on post silicon estimates and simulations or empirical data 2 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range This d
47. 1 3 a pec x 1 1 mat Pc 1 3 1 1 n r 1 a u 2 2 a 2 19 w a 16 5 gt s 2 1 Datasheet Volume 1 143 m e n tel Processor Pin and Signal Information Table 8 3 BGA1023 Processor Ball Table 8 3 1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir BCLK J3 Diff Clk I DC_TEST_BG61 BG61 N A BCLK H2 Diff Clk I DC_TEST_C4 C4 N A BCLK ITP N59 Diff Clk I DC_TEST_C59 C59 N A BCLK_ITP N58 Diff Clk I DC_TEST_C61 C61 N A BPM 0 6586 Asynch CMOS 1 0 DC_TEST_D1 01 BPM 1 E55 Asynch CMOS 1 0 DC_TEST_D3 D3 N A BPM 2 E59 Asynch CMOS 1 0 DC_TEST_D61 D61 N A BPM 3 655 CMOS 1 0 DMI_RX 0 M2 DMI I BPM 4 659 Asynch CMOS 1 0 DMI_RX 1 P6 DMI I BPM 5 H60 Asynch CMOS 1 0 DMI_RX 2 P1 DMI I BPM 6 359 Asynch CMOS DMI_RX 3 P10 DMI I BPM 7 261 CMOS DMI_RX 0 N3 DMI I CATERR C49 CMOS DMI RX 1 7 DMI I CFG 0 B50 CMOS I DMI_RX 2 P3 DMI I CFG 1 C51 CMOS I DMI RX 3 11 DMI
48. 10 SB_CS 1 BE47 DDR3 SA_DQS 1 8 DDR3 10 SB DQ 0 AL4 DDR3 1 0 SA_DQS 2 AV11 DDR3 I O SB_DQ 1 DDR3 1 0 SA_DQS 3 AT17 DDR3 10 SB_DQ 2 AN3 DDR3 1 0 SA_DQS 4 AV45 DDR3 7 SB_DQ 3 AR4 DDR3 1 0 SA_DQS 5 AY51 DDR3 10 SB_DQ 4 AK4 DDR3 1 0 SA_DQS 6 AT55 DDR3 10 SB_DQ 5 AK3 DDR3 1 0 SA_DQS 7 AK55 DDR3 10 SB_DQ 6 AN4 DDR3 1 0 SA_DQS 0 AJ11 DDR3 I O SB_DQ 7 AR1 DDR3 1 0 SA_DQS 1 AR10 DDR3 10 SB DQ 8 AUA DDR3 10 SA_DQS 2 AY11 DDR3 10 SB_DQ 9 AT2 DDR3 1 0 SA_DQS 3 AU17 DDR3 10 SB_DQ 10 DDR3 1 0 SA_DQS 4 AW45 DDR3 10 SB DQ 11 BA4 DDR3 1 0 SA_DQS 5 AV51 DDR3 10 SB_DQ 12 AU3 DDR3 1 0 SA_DQS 6 AT56 DDR3 10 SB_DQ 13 AR3 DDR3 1 0 SA_DQS 7 AK54 DDR3 10 SB DQ 14 AY2 DDR3 1 0 SA MA 0 BG35 DDR3 SB_DQ 15 BA3 DDR3 1 0 SA_MA 1 BB34 DDR3 SB_DQ 16 9 DDR3 1 0 SA_MA 2 BE35 DDR3 SB_DQ 17 BD9 DDR3 1 0 SA_MA 3 BD35 DDR3 SB_DQ 18 BD13 DDR3 10 SA_MA 4 AT34 DDR3 SB_DQ 19 BF12 DDR3 1 0 SA_MA 5 AU34 DDR3 SB_DQ 20 BF8 DDR3 SA_MA 6 BB32 DDR3 SB_DQ 21 BD10 DDR3 1 0 SA_MA 7 AT32 DDR3 SB_DQ 22 BD14 DDR3 1 0 SA_MA 8 AY32 DDR3 SB_DQ 23 BE13 DDR3 1 0 SA_MA 9 AV32 DDR3 SB_DQ 24 BF16 DDR3 1 0 SA_MA 10 BE37 DDR3 SB_DQ 25 BE17 DDR3 1 0 SA_MA 11 BA30 DDR3 SB_DQ 26 BE18 DDR3 1 0 SA_MA 12 BC30 DDR3 SB_DQ 27 BE21 DDR3 1 0 SA_MA 13 AW41 DDR3 SB_DQ 28 BE14 DDR3 1 0 SA_MA 14 AY28 DDR3 SB_DQ 29 BG14 DDR3 1 0 SA_MA 15 AU26 DDR3 SB DQ 30 BG18 DDR3 1 0
49. 1066 MT s 21 3 GB s in dual channel mode assuming DDR3 1333 MT s 25 6 GB s in dual channel mode assuming DDR3 1600 MT s 1Gb 2Gb and 4Gb DDR3 DRAM technologies are supported for x8 and x16 devices Using 4Gb device technologies the largest memory capacity possible is 16 GB assuming dual channel mode with two x8 dual ranked un buffered non ECC SO DIMM memory configuration Up to 32 simultaneous open pages 16 per channel assuming 4 Ranks of 8 Bank Devices 13 Introduction Memory organizations Single channel modes Dual channel modes Intel Flex Memory Technology Dual channel symmetric Interleaved Command launch modes of 1n 2n On Die Termination ODT Asynchronous ODT Intel Fast Memory Access Intel FMA Just in Time Command Scheduling Command Overlap Out of Order Scheduling 1 2 2 PCI Express e PCI Express port s are fully compliant with the PCI Express Base Specification Revision 2 0 e Processor with mobile PCH supported configurations Table 1 1 PCI Express Supported Configurations in Mobile Products 14 Configuration Organization Mobile 1x8 Graphics 2x4 I O 2 2x8 Graphics I O 3 1x16 Graphics I O The port may negotiate down to narrower widths Support for x16 x8 x4 x1 widths for a single PCI Express mode 2 5 GT s and 5 0 GT s PCI Express frequencies are supported Geni Raw bit rate on the data pins of 2 5 GT s resulting in
50. AC Specifications 5 GT s but are DC coupled The buffers are not 3 3 V tolerant CMOS CMOS buffers 1 1 V tolerant DDR3 DDR3 buffers 1 5 V tolerant A Analog reference or output May be used as a threshold voltage or for buffer compensation Ref Voltage reference signal Asynchronous Signal has no timing relationship with any reference clock Notes 1 Qualifier for a buffer type Datasheet Volume 1 75 intel 6 1 Table 6 2 76 Signal Description System Memory Interface Signals Memory Channel A Signals Signal Name Description Direction Buffer Type SA BSI2 0 Bank Select These signals define which banks are selected within BS 2 0 each SDRAM rank DDR3 SA WE Write Enable Control Signal This signal is used with SA RAS and SA_CAS along with SA_CS to define the SDRAM Commands DDR3 SA RAS RAS Control Signal This signal is used with SA_CAS and SA_WE along with SA_CS to define the SRAM Commands DDR3 SA CAS CAS Control Signal This signal is used with SA_RAS and SA_WE along with SA_CS to define the SRAM Commands DDR3 Data Strobes SA_DQS 7 0 and its complement signal group make SA_DQS 7 0 up a differential strobe pair The data is captured at the crossing point 1 0 SA_DQS 7 0 of SA_DQS 7 0 and its SA_DQS 7 0 during read and write DDR3 transactions Data Bus Channel A data signal interface to the SDRAM data bus 1 0 SA_DQ 63 0
51. AN52 PWR VCCPQE AL21 PWR VCCIO AN49 PWR VCCSA W17 PWR VCCIO AN20 PWR VCCSA w15 PWR VCCIO AN18 PWR VCCSA W12 PWR VCCIO AN16 PWR VCCSA U17 PWR VCCIO AN14 PWR VCCSA U15 PWR VCCIO AM11 PWR VCCSA U12 PWR VCCIO AL55 PWR VCCSA T16 PWR VCCIO AL53 PWR VCCSA T14 PWR VCCIO AL48 PWR VCCSA T11 PWR VCCIO AL17 PWR VCCSA N18 PWR 133 intel 134 Table 8 2 BGA1224 Processor Ball List by Ball Name Processor Pin and Signal Information Table 8 2 BGA1224 Processor Ball List by Ball Name Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VCCSA N16 PWR VDDQ AT46 PWR VCCSA N14 PWR VDDQ AT42 PWR VCCSA M17 PWR VDDQ AT40 PWR VCCSA M15 PWR VDDQ AT36 PWR VCCSA M12 PWR VDDQ AT34 PWR VCCSA M11 PWR VDDQ AT29 PWR VCCSA L18 PWR VDDQ AT27 PWR VCCSA L14 PWR VDDQ AR45 PWR VCCSA SENSE K3 Analog VDDQ AR43 PWR VCCSA_VID 0 AE10 CMOS VDDQ AR39 PWR VCCSA_VID 1 AG10 CMOS VDDQ AR37 PWR VDDQ BJ36 PWR VDDQ AR33 PWR VDDQ BJ28 PWR VDDQ AR30 PWR VDDQ BG40 PWR VDDQ AR26 PWR VDDQ BG32 PWR VDDQ AR24 PWR VDDQ BD47 PWR VDDQ AP46 PWR VDDQ BD43 PWR VDDQ AP42 PWR VDDQ BD39 PWR VDDQ AP40 PWR VDDQ BD31 PWR VDDQ AP36 PWR VDDQ BD23 PWR VDDQ AP34 PWR VDDQ BB35 PWR VDDQ AP29 PWR VDDQ AY47 PWR VDDQ AP27 PWR VDDQ AY43 PWR VDDQ AN45 PWR VDDQ AY39 PWR VDDQ AN43 PWR VDDQ AY35 PWR VDDQ AN39 PWR VDDQ AY31 PWR VDDQ AN37 PWR
52. AT23 PWR VCC F31 PWR VCCDQ AP23 PWR 132 Datasheet Volume 1 Processor Pin and Signal Information Table 8 2 BGA1224 Processor Ball List by Ball Name intel Table 8 2 BGA1224 Processor Ball List by Ball Name Datasheet Volume 1 Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type bir VCCDQ AL23 PWR VCCIO AL15 PWR VCCIO AV55 PWR VCCIO AL12 PWR VCCIO AV53 PWR VCCIO AK58 PWR VCCIO AV48 PWR VCCIO AK56 PWR VCCIO AV17 PWR VCCIO 217 PWR VCCIO AV15 PWR VCCIO AJ15 PWR VCCIO AV12 PWR VCCIO 12 PWR VCCIO AU58 PWR VCCIO AH16 PWR VCCIO AU56 PWR VCCIO AH14 PWR VCCIO AU52 PWR VCCIO AH11 PWR VCCIO AU49 PWR VCCIO AF16 PWR VCCIO AU20 PWR VCCIO AF14 PWR VCCIO AU18 PWR VCCIO AE17 PWR VCCIO AT55 PWR VCCIO AE15 PWR VCCIO AT53 PWR VCCIO AE12 PWR VCCIO AT48 PWR VCCIO 11 PWR VCCIO AT17 PWR VCCIO AC17 PWR VCCIO AT15 PWR VCCIO AC15 PWR VCCIO AT12 PWR VCCIO AC12 PWR VCCIO AR58 PWR VCCIO AB16 PWR VCCIO AR56 PWR VCCIO AB14 PWR VCCIO AR52 PWR VCCIO Y16 PWR VCCIO AR49 PWR VCCIO 14 PWR VCCIO AR20 PWR VCCIO Y11 PWR VCCIO AR18 PWR VCCIO SEL AJ8 N A AR16 PWR VCCIO_SENSE AW10 Analog VCCIO AR14 PWR VCCPLL AK65 PWR VCCIO AP55 PWR VCCPLL AK63 PWR VCCIO AP53 PWR VCCPLL AK61 PWR VCCIO AP48 PWR VCCPQE AV21 PWR VCCIO AN58 PWR VCCPQE AT21 PWR VCCIO AN56 PWR VCCPQE AP21 PWR VCCIO
53. BI a 8 3 vecio t 5 karesi isa a 9 lara sa Dal sa_po 2 sa 58 8 4 sa pop 58_pos 56 54 Das sa 3 9 si 5 pean 58 294 56 aR 1 Em AP cera AN Datasheet Volume 1 AL AK AF AE m e n tel Processor Pin and Signal Information Figure 8 11 BGA1023 Ballmap Top View Lower Left Quadrant 142 Datasheet Volume 1 Processor Pin and Signal Information Figure 8 12 BGA1023 Ballmap Top View Lower Right Quadrant te 100 ac as w N 13 1 a 5 PEG E 18 PEG sd 1 1 n 3
54. Express external graphics link is mapped through a PCI to PCI bridge structure Figure 2 4 PCI Express Related Register Structures in the Processor PCI PCI Bridge PCI representing PCI Compatible Express PEG0 root PCI Host Bridge Device Express ports Device Device 1 and Device 0 Device 6 DMI PCI Express extends the configuration space to 4096 bytes per device function as compared to 256 bytes allowed by the Conventional PCI Specification PCI Express configuration space is divided into a PCI compatible region that consists of the first 256 bytes of a logical device s configuration space and an extended PCI Express region that consists of the remaining configuration space The PCI compatible region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express configuration access mechanism described in the PCI Express Enhanced Configuration Mechanism section The PCI Express Host Bridge is required to translate the memory mapped PCI Express configuration space accesses from the host processor to PCI Express configuration cycles To maintain compatibility with PCI configuration addressing mechanisms it is recommended that system software access the enhanced configuration space using 32 bit operations 32 bit aligned only See the PCI Express Base Specification for details of both the PCI compatible and PCI Express Enhanced config
55. GND VDDQ AM36 PWR VSS BA21 GND VDDQ AM33 PWR VSS BA17 GND VDDQ AL42 PWR VSS BA11 GND VDDQ AL38 PWR VSS BA1 GND VDDQ AL34 PWR VSS AY58 GND VDDQ AL30 PWR VSS AY55 GND VDDQ AJ40 PWR VSS AY49 GND VDDQ AJ36 PWR VSS AY45 GND VDDQ AJ33 PWR vss AY41 GND VDDQ AJ28 PWR vss AY36 GND VDDQ_SENSE BC43 Analog VSS AY30 GND VIDALERT A44 CMOS I VSS AY19 GND VIDSCLK B43 CMOS VSS AY14 GND VIDSOUT C44 CMOS 1 0 VSS AYO GND vss BG53 GND vss AY4 GND vss BG49 GND vss AW61 GND vss BG45 GND vss AW43 GND Datasheet Volume 1 m e n tel Processor Pin and Signal Information Table 8 3 1023 Processor Ball Table 8 3 1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VSS AW13 GND VSS AM42 GND VSS AW7 GND VSS AM38 GND VSS AV55 GND VSS AM34 GND VSS AV48 GND VSS AM30 GND VSS AV40 GND VSS AM26 GND VSS AV34 GND VSS AM22 GND VSS AV22 GND VSS AM20 GND VSS AV21 GND VSS AM13 GND VSS AV17 GND VSS AM4 GND VSS AU51 GND VSS AL61 GND VSS AU32 GND VSS AL47 GND VSS AU28 GND VSS AL43 GND VSS AU11 GND VSS AL40 GND VSS AU7 GND VSS AL36 GND VSS AU1 GND VSS AL33 GND VSS AT58 GND VSS AL28 GND VSS AT52 GND VSS AL25 GND VSS AT45 GND VSS AL21 GND VSS AT36 GND VSS AL17 GND VSS AT19 GND VSS AL13 GND VSS AT14 GND VSS A
56. I CFG 2 B54 CMOS I DMI_TX 0 Ki DMI CFG 3 D53 CMOS I DMI_TX 1 M8 DMI 4 51 5 1 DMI_TX 2 N4 DMI CFG 5 C53 CMOS I DMI_TX 3 R2 DMI CFG 6 C55 CMOS I DMI TX 0 K3 DMI CFG 7 H49 CMOS I DMI TX 1 M7 DMI CFG 8 A55 CMOS I DMI_TX 2 P4 DMI CFG 9 H51 CMOS I DMI_TX 3 T3 DMI CFG 10 K49 CMOS I DPLL_REF_CLK AG3 Diff Clk I CFG 11 K53 CMOS I DPLL_REF_CLK AG1 Diff Clk I CFG 12 F53 CMOS I eDP_AUX AF4 eDP 1 0 CFG 13 G53 CMOS I eDP_AUX AG4 eDP 1 0 CFG 14 L51 CMOS I eDP_COMPIO AF3 Analog I CFG 15 F51 CMOS I eDP_HPD AG11 Asynch CMOS I CFG 16 D52 CMOS I eDP_ICOMPO AD2 Analog I CFG 17 L53 CMOS I eDP_TX 0 AC3 eDP DBR K58 Asynch CMOS eDP_TX 1 AC4 eDP DC_TEST_A4 A4 N A eDP_TX 2 AE11 eDP DC TEST A58 A58 N A eDP TX 3 AE7 eDP DC TEST A59 A59 N A eDP_TX 0 1 eDP DC TEST A61 A61 N A eDP TX 1 AA4 eDP DC TEST BD1 BD1 N A eDP_TX 2 AE10 eDP 0 DC_TEST_BD61 BD61 N A eDP_TX 3 AE6 eDP DC TEST BE1 BE1 N A FDI INT 011 Asynch CMOS I DC_TEST_BE3 BE3 N A FDIO_FSYNC AA11 CMOS I DC TEST BE59 BE59 N A FDIO LSYNC AA10 CMOS I DC TEST BE61 BE61 N A FDIO_TX 0 U7 FDI DC TEST BG1 BG1 N A FDIO_TX 1 Wil FDI DC_TEST_BG3 BG3 N A FDIO_TX 2 FDI DC_TEST_BG4 BG4 N A FDIO_TX 3 AA6 FDI DC_TEST_BG58 BG58 N A FDIO_TX 0 U6 FDI DC_TEST_BG59 BG59 N A FDIO_TX 1 W10 FDI 144 Datasheet Volume 1 Processor Pin and Signal Information
57. Information Table 8 2 BGA1224 Processor Ball List by Ball Name intel List by Ball Name Table 8 2 BGA1224 Processor Ball Datasheet Volume 1 Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir BCLK DS Diff Clk I DC_TEST_BH3 BH3 N A BCLK C6 Diff Clk I DC_TEST_BH63 BH63 N A BCLK_ITP K63 Diff Clk I DC_TEST_BH65 BH65 N A BCLK_ITP K65 Diff Clk I DC TEST BJ2 BJ2 N A BPM 0 C62 Asynch CMOS 1 0 DC_TEST_BJ4 BJ4 N A BPM 1 061 Asynch CMOS 10 DC TEST BJ62 BJ62 N A BPM 2 E62 Asynch CMOS 1 0 DC TEST BJ64 BJ64 N A BPM 3 F63 Asynch CMOS 1 0 DC_TEST_C2 C2 N A BPM 4 059 Asynch CMOS 1 0 DC_TEST_C64 C64 N A BPM 5 F61 Asynch CMOS 1 0 DC TEST D1 Di N A BPM 6 F59 Asynch CMOS 1 0 DC_TEST_D65 D65 N A BPM 7 G60 Asynch CMOS 1 0 DMI_RX 0 N10 DMI I CATERR H53 Asynch CMOS DMI_RX 1 R10 DMI I CFG 0 B57 CMOS I DMI_RX 2 R8 DMI I CFG 1 D57 CMOS I DMI RX 31 U10 DMI I CFG 2 B55 CMOS I DMI RX 0 N8 DMI I CFG 3 54 CMOS I DMI RX 1 T9 DMI I CFG 4 A58 CMOS I DMI RX 2 R6 DMI I CFG 5 D55 CMOS I DMI RX 3 U8 DMI I CFG 6 C56 CMOS I DMI_TX 0 N4 DMI 7 54 CMOS I DMI_TX 1 R4 DMI CFG 8 154 5 DMI_TX 2 1 DMI 9 G56 CMOS I DMI_TX 3 U6 DMI 10 55 CMOS I DMI TX 0 N2 DMI 11 55 CMOS I DMI_TX
58. MLE e Mechanisms to ensure the above measurement is protected and stored in a secure location e Protection mechanisms that allow the MLE to control attempts to modify itself For more information refer to the Intel TXT Measured Launched Environment Developer s Guide http www intel com technology security Intel Hyper Threading Technology Intel HT Technology The processor supports Intel Hyper Threading Technology Intel HT Technology that allows an execution core to function as two logical processors While some execution resources such as caches execution units and buses are shared each logical processor has its own architectural state with its own set of general purpose registers and control registers This feature must be enabled using the BIOS and requires operating system support Intel recommends enabling Intel HT Technology with Microsoft Windows 7 Microsoft Windows Vista Microsoft Windows XP Professional Windows XP Home and disabling Intel HT Technology using the BIOS for all previous versions of Windows operating systems For more information on Intel HT Technology see http www intel com technology platform technology hyper threading Datasheet Volume 1 Technologies 3 4 Note 3 4 1 Note intel Intel Turbo Boost Technology Compared with previous generation products Intel Turbo Boost Technology will increase the ratio of application power to TDP Thus thermal solutions and pl
59. O SB MA 10 AY37 DDR3 SB_DQ 48 BA64 DDR3 I O SB_MA 11 BJ30 DDR3 SB_DQ 49 BC62 DDR3 I O SB MA 12 AW30 DDR3 SB_DQ 50 AU62 DDR3 58_ 13 BA40 DDR3 SB_DQ 51 AW64 DDR3 I O SB MA 14 BB29 DDR3 SB_DQ 52 BA62 DDR3 I O SB_MA 15 BE28 DDR3 SB_DQ 53 BC64 DDR3 I O SB ODT 0 BG42 DDR3 SB_DQ 54 AU64 DDR3 I O SB ODT 1 BH45 DDR3 SB_DQ 55 AW62 DDR3 I O SB_RAS BG38 DDR3 SB_DQ 56 AR64 DDR3 I O SB WE BF39 DDR3 O SB_DQ 57 AT65 DDR3 1 0 SM_DRAMPWROK AY25 Asynch CMOS I SB_DQ 58 AL64 DDR3 1 0 SM_DRAMRST BE24 DDR3 O SB_DQ 59 AM65 DDR3 I O SM RCOMP O0 BJ46 Analog I O SB DQ 60 AR62 DDR3 I O SM RCOMP 1 BG46 Analog I O SB DQ 61 AT63 DDR3 I O SM RCOMP 2 BF45 Analog I O SB DQ 62 AL62 DDR3 I O SM VREF BJ44 Analog I SB 63 AM63 DDR3 TCK J58 CMOS I SB DQSZ 0 DDR3 1 O TDI K61 CMOS I SB_DQS 1 AW2 DDR3 I O TDO K59 CMOS SB_DQS 2 BH9 DDR3 I O THERMTRIP F51 Asynch CMOS SB_DQS 3 BF15 DDR3 I O TMS H59 CMOS I SB_DQS 4 BF51 DDR3 I O TRST H63 CMOS I SB_DQS 5 BH57 DDR3 I O UNCOREPWRGOOD C60 Asynch CMOS I SB_DQS 6 AY63 DDR3 I O VAXG AH65 PWR SB_DQS 7 AN62 DDR3 I O VAXG AH63 PWR SB DQS 0 AN2 DDR3 I O VAXG AH61 PWR SB DQS 1 AW4 DDR3 I O VAXG AH58 PWR SB_DQS 2 BF9 DDR3 I O VAXG AH56 PWR SB_DQS 3 BH15 DDR3 I O VAXG AG64 PWR SB DQS 4 BH51 DDR3 I O VAXG AG62 PWR SB DQS 5 BF57 DDR3 I O VAXG AG60 PWR Datasheet Volume 1 Processor Pin and Signal Information Table 8 2 BGA1224
60. Power 5 5 u eese einen nine n aaa dana Rr na RR nua 64 5 4 Thermal Management Features cccccccscecceceneececeeeeceseecnendstceeeecenaeceaeeteananeceeeeenees 67 5 4 1 Processor Package Thermal 11122222 67 5 4 1 1 Adaptive Thermal Monitor esee aa aq nnn 68 5 4 1 2 Digital Thermal Sensor 70 5 4 1 3 PROCHOT3 Signal roii Qul tonne dern a cnet 71 5 4 2 Processor Core Specific Thermal Features 73 5 4 2 1 On Demand a RR deems 73 5 4 3 Memory Controller Specific Thermal Features 73 5 4 3 1 Programmable Trip Points eect ee eee eee mne 73 5 4 4 Platform Environment Control Interface 74 5 4 4 1 Fan Speed Control with Digital Thermal 74 6 Signal Description esi sa DER RED NER e DRAN E 75 6 1 System Memory Interface 1 emen eese 76 6 2 Memory Reference and Compensation Signals r 77 6 3 Reset and Miscellaneous 6 2 2 1 2 eene 78 6 4 PCI Express Based Interface Signals nemen 79
61. R4 GND VSS AD20 GND VSS P59 GND VSS AD17 GND VSS P58 GND VSS AD4 GND VSS P21 GND VSS AC46 GND VSS P18 GND VSS AC14 GND VSS P16 GND VSS AC10 GND VSS P14 GND VSS AC6 GND VSS P9 GND VSS AB61 GND VSS N61 GND VSS AB48 GND VSS N56 GND VSS AB21 GND VSS N52 GND VSS AB18 GND VSS N51 GND VSS AB16 GND VSS N48 GND VSS AA56 GND VSS N47 GND VSS AA55 GND VSS N43 GND VSS AA53 GND VSS N40 GND VSS AA52 GND VSS N36 GND VSS 51 GND VSS N33 GND VSS AA50 GND vss N28 GND vss AA13 GND vss N25 GND vss AA8 GND vss N21 GND vss AA1 GND vss N17 GND vss Y59 GND vss N1 GND vss Y58 GND vss M58 GND vss Y47 GND vss M15 GND vss Y4 GND vss M11 GND vss W46 GND vss M6 GND vss W21 GND vss M4 GND vss W18 GND vss L61 GND vss W15 GND vss L48 GND vss W13 GND vss L43 GND vss w8 GND vss L38 GND vss V61 GND vss L34 GND vss V20 GND VSS L30 GND VSS U13 GND VSS L26 GND Datasheet Volume 1 153 m e n tel Processor Pin and Signal Information Table 8 3 BGA1023 Processor Ball Table 8 3 1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VSS L22 GND VSS D4 GND VSS L20 GND VSS C40 GND VSS L16 GND VSS C35 GND VSS K51 GND VSS C29 GND VSS K21 GND VSS A53 GND VSS K11 GND VSS A49 GND VSS K8 GND VSS A45 GND VSS J55 GND VSS A40 GND VSS 14
62. VSS AN30 GND VSS 125 GND VSS AN4 GND VSS GND VSS AN7 GND VSS AJ4 GND vss AP1 GND vss AJ7 GND vss AP10 GND vss AK10 GND vss AP13 GND vss AK13 GND vss AP16 GND vss AK16 GND vss AP19 GND vss AK19 GND vss AP22 GND vss AK22 GND vss AP25 GND vss AK25 GND vss AP28 GND vss AK27 GND vss AP31 GND vss AK30 GND vss AP34 GND vss AK33 GND vss AP4 GND vss AK4 GND vss AP7 GND vss AK7 GND vss AR10 GND vss AL10 GND vss AR13 GND vss AL13 GND vss AR16 GND vss AL16 GND vss AR19 GND vss AL19 GND vss AR2 GND vss AL2 GND vss AR22 GND vss AL22 GND vss AR25 GND vss AL25 GND vss AR4 GND vss AL28 GND vss AR7 GND vss AL31 GND vss AT10 GND vss AL34 GND vss AT13 GND vss AL4 GND vss AT16 GND vss AL7 GND vss AT19 GND vss AM1 GND vss AT22 GND vss AM10 GND vss AT25 GND vss AM13 GND vss AT27 GND vss AM16 GND vss AT29 GND vss AM19 GND vss AT3 GND vss AM2 GND vss AT32 GND vss AM22 GND vss AT35 GND vss AM25 GND vss AT4 GND vss AM29 GND vss AT7 GND vss AM3 GND vss B11 GND vss AM4 GND vss B13 GND 118 Datasheet Volume 1 Processor Pin and Signal Information intel Table 8 1 rPGA988B Processor Pin Table 8 1 rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VSS B15 GND VSS G17 GN
63. Virtualization Technology Intel VT for IA 32 Intel 64 and Intel Architecture Intel VT x Features 36 3 1 3 Intel Virtualization Technology Intel VT for Directed I O Intel VT d Objectives 36 3 1 4 Intel Virtualization Technology Intel VT for Directed I O Intel VT d Features aa 37 3 1 5 Intel Virtualization Technology Intel VT for Directed 1 0 Intel VT d Features Not 5 ene 37 3 2 Intel Trusted Execution Technology Intel TXT cccscsssssccccscsssecccseseseneceesuseneaees 38 3 3 Intel Hyper Threading Technology Intel HT 38 3 4 Intel Turbo du d 39 3 4 1 Intel Turbo Boost Technology Frequency 1 39 3 4 2 Intel Turbo Boost Technology Graphics 40 3 5 Intel Advanced Vector Extensions Intel 40 3 6 Intel Advanced Encryption Standard New Instructions Intel AES NI 40 3 6 1 PCEMULQDO InstrUCctlOl ass 41 3 7 Intel 64 Architecture X2APIC 3 ar 41 Power Management 41 2 4 4 4 nnn 43 4 1 Advanced Configuration and Power Interfac
64. a real bandwidth per pair of 250 MB s given the 8b 10b encoding used to transmit data across this interface This also does not account for packet overhead and link maintenance Maximum theoretical bandwidth on the interface of 4 GB s in each direction simultaneously for an aggregate of 8 GB s when x16 Gen 1 Gen 2 Raw bit rate on the data pins of 5 0 GT s resulting in a real bandwidth per pair of 500 MB s given the 8b 10b encoding used to transmit data across this interface This also does not account for packet overhead and link maintenance Maximum theoretical bandwidth on the interface of 8 GB s in each direction simultaneously for an aggregate of 16 GB s when x16 Gen 2 Hierarchical PCI compliant configuration mechanism for downstream devices Traditional PCI style traffic asynchronous snooped PCI ordering PCI Express extended configuration space The first 256 bytes of configuration space aliases directly to the PCI Compatibility configuration space The remaining portion of the fixed 4 KB block of memory mapped space above that starting at 100h is known as extended configuration space PCI Express Enhanced Access Mechanism accessing the device configuration space in a flat memory mapped fashion Automatic discovery negotiation and training of link out of reset Datasheet Volume 1 Introduction intel Traditional AGP style traffic asynchronous non snooped PCI X Relaxed ordering Peer segment destination posted write
65. describe the Just in Time Scheduling Command Overlap and Out of Order Scheduling Intel FMA technology enhancements Just in Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next The most efficient request is picked from all pending requests and issued to system memory Just in Time to make optimal use of Command Overlapping Thus instead of having all memory access requests go individually through an arbitration mechanism forcing requests to be executed one at a time they can be started without interfering with the current request allowing for concurrent issuing of requests This allows for optimized bandwidth and reduced latency while maintaining appropriate command spacing to meet system memory protocol Command Overlap Command Overlap allows the insertion of the DRAM commands between the Activate Precharge and Read Write commands normally used as long as the inserted commands do not affect the currently executing command Multiple commands can be issued in an overlapping manner increasing the efficiency of system memory protocol Out of Order Scheduling While leveraging the Just in Time Scheduling and Command Overlap enhancements the IMC continuously monitors pending requests to system memory for the best use of bandwidth and reduction of latency If there are multiple requests to the same open
66. for thermal management and fan speed control More detailed information may be found in the Platform Environment Control Interface PECI Specification PECI Bus Architecture The PECI architecture based on wired OR bus that the clients such as 2nd Generation Intel Core processor family mobile PECI can pull up high with strong drive The idle state on the bus is near zero Figure 7 1 demonstrates PECI design and connectivity while the host originator can be 3rd party PECI host and one of the PECI client is a 2nd Generation Intel Core processor family mobile PECI and Intel Celeron processor family mobile PECI device Datasheet Volume 1 101 Electrical Specifications intel Figure 7 1 Example for PECI Host clients Connection Creci 10pF Node Host Originator PECI Client Additiona PECI Clients 7 10 2 DC Characteristics The interface operates at a nominal voltage set by The set of DC electrical specifications shown in Table 7 15 are used with devices normally operating from a interface supply nominal levels will vary between processor families All devices will operate at the level determined by the processor installed in the system For specific nominal Vccro levels refer to Table 7 6 Table 7 15 PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units N
67. future platform innovations In xAPIC compatibility mode APIC registers are accessed through a memory mapped interface to a 4 KB page identical to the xAPIC architecture In x2APIC mode APIC registers are accessed through Model Specific Register MSR interfaces In this mode the x2APIC architecture provides significantly increased processor addressability and some enhancements on interrupt delivery e Increased range of processor addressability in x2APIC mode Physical xAPIC ID field increases from 8 bits to 32 bits allowing for interrupt processor addressability up to 4G 1 processors in physical destination mode A processor implementation of x2APIC architecture can support fewer than 32 bits in a software transparent fashion Logical xAPIC ID field increases from 8 bits to 32 bits The 32 bit logical 2 ID is partitioned into two sub fields a 16 bit cluster ID and a 16 bit logical ID within the cluster Consequently 2 20 16 processors can be addressed in logical destination mode Processor implementations can support fewer than 16 bits in the cluster ID sub field and logical ID sub field in a software agnostic fashion Datasheet Volume 1 41 m Technologies intel Note 42 More efficient MSR interface to access APIC registers To enhance inter processor and self directed interrupt delivery as well as the ability to virtualize the local APIC the APIC register set can be accessed on
68. including ripple 0 Vccio sense and vccio AC 3 vccio Max Current for Vccio Rail 8 5 Thermal Design Current TDC for Iccrpc vccio 8 5 A Vccio Rail Note Long term reliability cannot be assured in conditions above or below Max Min functional limits 96 Datasheet Volume 1 Electrical Specifications Table 7 7 Table 7 8 Table 7 9 intel Memory Controller Vppq Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note Processor I O supply voltage for _ Vopa DCtAC DDR3 DC AC specification v Tolerance DC 3 2 AC DC 5 Iccmax_VDDQ Max Current for Rail 5 A 1 IccavG Average Current for Rail _ Standby during Standby 66 193 mA Notes 1 The current supplied to the SO DIMM modules is not included in this specification System Agent VccsA Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note Voltage for the System Agent and V 0 75 0 90 V CESA VCCSA_SENSE TOLccsA VccsA Tolerance AC DC 5 Iccmax VCCSA Max Current for Vecsa Rail and 6 A I Thermal Design Current TDC for 6 CCTDC_VCCSA Vccsa Rail Slew Rate Voltage Ramp rate dV dT 0 5 10 mV us Note Long term reliability cann
69. m Thermal Management intel 5 4 4 1 74 Platform Environment Control Interface PECI The Platform Environment Control Interface PECI is a one wire interface that provides a communication channel between Intel processor and chipset components to external monitoring devices The processor implements a PECI interface to allow communication of processor thermal information to other devices on the platform The processor provides a digital thermal sensor DTS for fan speed control The DTS is calibrated at the factory to provide a digital representation of relative processor temperature Averaged DTS values are read using the PECI interface The PECI physical layer is a self clocked one wire bus that begins each bit with a driven rising edge from an idle level near zero volts The duration of the signal driven high depends on whether the bit value is a Logic 0 or Logic 1 PECI also includes variable data transfer rate established with every message The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components Bus speed error checking and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information Fan Speed Control with Digital Thermal Sensor Digital Thermal Sensor based fan speed control Tran is a recommended feature to achieve optimal th
70. on and its architectural state is restored Core C7 State Individual threads of a core can enter the C7 state by initiating a I O read to the P BLK or by an MWAIT C7 instruction The core C7 state exhibits the same behavior as the core C6 state unless the core is the last one in the package to enter the C7 state If it is that core is responsible for flushing L3 cache ways The processor supports the C7s substate When an MWAIT C7 command is issued with a C7s sub state hint the entire L3 cache is flushed in one step as opposed to flushing the L3 cache in multiple steps Datasheet Volume 1 49 m Power Management intel 4 2 4 6 C State Auto Demotion In general deeper C states such as C6 or C7 have long latencies and have higher energy entry exit costs The resulting performance and energy penalties become significant when the entry exit frequency of a deeper C state is high Therefore incorrect or inefficient usage of deeper C states have a negative impact on battery life idle To increase residency and improve battery life idle in deeper C states the processor supports C state auto demotion There are two C State auto demotion options C7 C6 to C3 C7 C6 C3 To C1 The decision to demote a core from C6 C7 to C3 or C3 C6 C7 to C1 is based on each core s immediate residency history Upon each core C6 C7 request the core C state is demoted to C3 or C1 until a sufficient amount of residency has been established At tha
71. package TURBO POWER LIMIT MSR 0610h 15 bits 46 32 Processor turbo long duration time Turbo Time Window Parameter POWER_LIMIT_1_TIME in mon package TURBO POWER LIMIT MSR 0610h bits 23 17 L Long duration turbo power limit Voltage LongP POWER LIMIT 1 in 10 12 package TURBO POWER LIMIT MSR 0610h 13 14 bits 14 0 Short duration turbo power limit Short POWER LIMIT 2 in 1 25 x 25 10 14 package TURBO POWER LIMIT MSR 0610h 15 bits 46 32 Processor turbo long duration time Turbo Time window Parameter POWER_LIMIT_1_TIME in 10 11 14 package TURBO_POWER_LIMIT MSR 0610h bits 23 17 Long duration turbo power limit Long P POWER LIMIT 1 in 10 12 package TURBO POWER LIMIT MSR 0610h 13 14 bits 14 0 Ultra Low Voltage Short duration turbo power limit Short P POWER LIMIT 2 in 1 25 x 17 10 14 15 package TURBO POWER LIMIT MSR 0610h 2 pr bits 46 32 66 Datasheet Volume 1 Thermal Management Table 5 4 Idle Power Specifications 5 4 This section covers thermal management features for the processor 5 4 1 Segment Extreme Edition XE Idle Parameter Min Quad Core SV Dual Core SV Low Voltage Ultra Low Voltage Symbol Typ Max Units Notes e power in the Package _ 12 5 6 8 Pis Er in the Package 1 4 6 9 Po in the Package _ 3 85
72. relative to the Adaptive Thermal Response Only a single PROCHOT pin exists at a package level When any core arrives at the TCC activation point the PROCHOT signal will be asserted PROCHOT assertion policies are independent of Adaptive Thermal Monitor enabling Bus snooping and interrupt latching are active while the TCC is active Bi Directional PROCHOTZ By default the PROCHOT signal is defined as an output only However the signal may be configured as bi directional When configured as a bi directional signal PROCHOT can be used for thermally protecting other platform components should they overheat as well When PROCHOT is driven by an external device e the package will immediately transition to the minimum operation points voltage and frequency supported by the processor and graphics cores This is contrary to the internally generated Adaptive Thermal Monitor response Clock modulation is not activated The TCC will remain active until the system de asserts PROCHOT The processor can be configured to generate an interrupt upon assertion and de assertion of the PROCHOT signal Toggling PROCHOT more than once in 1 5ms period will result in constant Pn state of the processor Datasheet Volume 1 71 m Thermal Management intel 5 4 1 3 2 5 4 1 3 3 5 4 1 3 4 5 4 1 3 5 5 4 1 3 6 72 Voltage Regulator Protection PROCHOT may be used for thermal protection of voltage regulators VR System de
73. single channel Single channel mode is used when either Channel A or Channel B DIMM connectors are populated in any order but not both Dual Channel Mode Intel Flex Memory Technology Mode The IMC supports Intel Flex Memory Technology Mode Memory is divided into a symmetric and an asymmetric zone The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached In this mode the system runs with one zone of dual channel mode and one zone of single channel mode simultaneously across the whole memory array Channels A and B can be mapped for physical channels 0 and 1 respectively or vice versa however channel A size must be greater or equal to channel B size Datasheet Volume 1 Interfaces Figure 2 1 Intel Flex Memory Technology Operation 2 1 3 2 1 Note 2 1 4 TOM Non interleaved access Dual channel interleaved access CHA CHB B The largest physical memory amount of the smaller size memory module C The remaining physical memory amount of the larger size memory module Dual Channel Symmetric Mode Dual Channel Symmetric mode also known as interleaved mode provides maximum performance on real world applications Addresses are ping ponged between the channels after each cache line 64 byte boundary If there are two requests
74. traffic no peer to peer read traffic in Virtual Channel 0 DMI gt PCI Express Port 0 DMI gt PCI Express Port 1 PCI Express Port 0 gt DMI PCI Express Port 1 gt DMI 64 bit downstream address format but the processor never generates an address above 64 GB Bits 63 36 will always be zeros 64 bit upstream address format but the processor responds to upstream read transactions to addresses above 64 GB addresses where any of Bits 63 36 are nonzero with an Unsupported Request response Upstream write transactions to addresses above 64 GB will be dropped Re issues Configuration cycles that have been previously completed with the Configuration Retry status PCI Express reference clock is 100 MHz differential clock Power Management Event PME functions Dynamic width capability Message Signaled Interrupt MSI and MSI X messages Polarity inversion Dynamic lane numbering reversal as defined by the PCI Express Base Specification Static lane numbering reversal Does not support dynamic lane reversal as defined optional by the PCI Express Base Specification Supports Half Swing low power low voltage mode Note The processor does not support PCI Express Hot Plug 1 2 3 Direct Media Interface DMI Datasheet Volume 1 DMI 2 0 support Four lanes in each direction 5 GT s point to point DMI interface to PCH is supported Raw bit rate on the data pins of 5 0 GB s resulting in a re
75. 0 999005 99 00008 2559 09009 o 00009 8899 oowoo 9000 09009 90908 9990 000900 008 004 90 0 0000000000000000000000000000000000000 590 999009 050 040 000 050 059 OJP 059 900 059 050 909 050900 000099 0 000 00 00 090 090 o90 o5 606000 11148348 1181 WNS 01 03 131113 111393031 01 994 310 a 03171 5133 01 680 0 10 8 165 Datasheet Volume 1 Processor Pin and Signal Information intel Figure 8 24 Processor BGA1023 2C GT1 Mechanical Package Sheet 2 of 2 m m 0000 050 960 0 0 050 0000000000 60 0 0 0000 0000 090000000 00 0000 9000000000000 o o 0000000000 900 2008 900000000000 e T B 999 0 o 9 9000000000 0000 00 E 0000000000 000999 0 00 46600000000 00000 ooo 5059 og 0000000000 000 o9 0000000000 000293995 000000000000 0090095 954 o D 000000000000 oo 4 do 0090000000 9000 6799 0000 55 0090000000 9909
76. 0 1 35000 1 35500 1 36000 1 36500 1 37000 1 37500 1 38000 1 38500 1 39000 1 39500 1 40000 1 40500 1 41000 1 41500 1 42000 1 42500 1 43000 1 43500 1 44000 1 44500 1 45000 1 45500 1 46000 1 46500 1 47000 1 47500 1 48000 1 48500 1 49000 1 49500 1 50000 1 50500 1 51000 1 51500 1 52000 HEX 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F E E E E E HEX Vcc_max 1 0 73000 1 0 81000 5 6 0 67500 5 7 0 68000 5 8 0 68500 5 9 0 69000 5 0 69500 5 B 0 70000 5 C 0 70500 5 D 0 71000 5 E 0 71500 5 F 0 72000 6 0 0 72500 6 6 2 0 73500 6 3 0 74000 6 4 0 74500 6 5 0 75000 6 6 0 75500 6 7 0 76000 6 8 0 76500 6 9 0 77000 6 0 77500 6 0 78000 6 0 78500 6 D 0 79000 6 0 79500 6 F 0 80000 7 0 0 80500 7 7 2 0 81500 7 3 0 82000 7 4 0 82500 7 5 0 83000 7 6 0 83500 7 7 0 84000 7 8 0 84500 7 9 0 85000 7 0 85500 7 0 86000 7 0 86500 7 D 0 87000 7 E 0 87500 7 F 0 88000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 VID VID VID VID VID VID VID VID 7
77. 0 BD25 DDR3 SA_DQ 62 AN60 DDR3 I O SB CKE 1 BJ26 DDR3 SA_DQ 63 AR60 DDR3 I O SB_CK 0 BH33 DDR3 SA_DQS 0 AN8 DDR3 1 0 SB_CK 1 BH37 DDR3 SA_DQS 1 AU6 DDR3 I O SB CK 0 BF33 DDR3 SA_DQS 2 BC6 DDR3 I O SB CK 1 BF37 DDR3 SA_DQS 3 BD9 DDR3 1 0 SB_CS 0 BE40 DDR3 SA_DQS 4 BC50 DDR3 I O SB CS 1 BH41 DDR3 SA_DQS 5 BB55 DDR3 I O SB DQ 0 AL4 DDR3 I O SA_DQS 6 BD59 DDR3 I O SB DQ 1 AK3 DDR3 I O SA_DQS 7 AU60 DDR3 I O SB 2 AP3 DDR3 I O SA DQS 0 AN6 DDR3 I O SB DQI 3 AR2 DDR3 I O SA DQS 1 AU8 DDR3 1 0 SB_DQ 4 AL2 DDR3 1 O SA_DQS 2 BD5 DDR3 I O SB DQ 5 AK1 DDR3 I O SA DQS 3 BC10 DDR3 I O SB DQI 6 AP1 DDR3 I O SA DQS 4 BB51 DDR3 I O SB DQI 7 AR4 DDR3 I O SA DQS 5 BD55 DDR3 1 0 SB_DQ 8 AV3 DDR3 1 0 SA_DQS 6 BD61 DDR3 I O SB DQI 9 AU4 DDR3 I O SA_DQS 7 AV61 DDR3 1 0 SB_DQ 10 BA4 DDR3 I O SA MA 0 BD27 DDR3 O SB_DQ 11 BB1 DDR3 I O SA MA 1 BA28 DDR3 SB_DQ 12 AVi DDR3 I O SA MA 2 BB27 DDR3 SB_DQ 13 AU2 DDR3 I O SA MA 3 AW26 DDR3 O SB_DQ 14 BA2 DDR3 I O SA MA 4 BB23 DDR3 SB_DQ 15 BB3 DDR3 I O SA MA 5 BA24 DDR3 SB_DQ 16 BC2 DDR3 I O SA MA 6 AY21 DDR3 SB_DQ 17 BF7 DDR3 I O SA MA 7 BD21 DDR3 SB_DQ 18 BF11 DDR3 1 0 5 8 22 DDR3 SB_DQ 19 BJ10 DDR3 I O SA MA 9 BB21 DDR3 SB_DQ 20 BC4 DDR3 I O SA MA 10 AW38 DDR3 SB_DQ 21 BH7 DDR3 I O SA MA 11 AW22 DDR3 SB_DQ 22 BH11 DDR3 I O SA MA 12 BA20 DDR3 O SB_DQ 23 BG10 DDR3 I O SA MA 13 BB45 D
78. 00 1 27500 1 28000 1 28500 1 29000 1 29500 1 30000 1 30500 1 31000 3 4 5 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HEX 1 0 49000 1 0 57000 1 0 65000 2 0 46000 2 0 46500 2 D 0 47000 2 E 0 47500 2 F 0 48000 3 0 0 48500 3 3 2 0 49500 3 3 0 50000 3 4 0 50500 3 5 0 51000 3 6 0 51500 3 7 0 52000 3 8 0 52500 3 9 0 53000 3 10 53500 3 B 0 54000 3 10 54500 3 D 0 55000 3 E 0 55500 3 F 0 56000 4 0 0 56500 4 4 2 0 57500 4 3 0 58000 4 4 0 58500 4 5 0 59000 4 6 0 59500 4 7 0 60000 4 8 0 60500 4 9 0 61000 4 0 61500 4 0 62000 4 C 0 62500 4 D 0 63000 4 E 0 63500 4 F 0 64000 5 0 0 64500 5 5 2 0 65500 5 3 0 66000 5 4 0 66500 5 5 0 67000 0 0 0 0 0 1 2 3 4 5 6 VID VID VID VID VID VID VID VID 7 Datasheet Volume 1 88 intel Electrical Specifications Sheet 3 of 3 VID VID VID VID VID VID VID VID inition IMVP7 Voltage Identification Def Table 7 1 Vcc MAX 1 31500 1 32000 1 32500 1 33000 1 33500 1 34000 1 3450
79. 1 R2 DMI 12 57 CMOS I DMI_TX 2 P3 DMI 13 58 CMOS I DMI_TX 3 T5 DMI 14 57 CMOS I DPLL_REF_CLK AJ4 Diff Clk I CFG 15 H55 CMOS I DPLL_REF_CLK AJ2 Diff Clk I CFG 16 D53 CMOS I eDP_AUX AE4 eDP I O CFG 17 K57 CMOS I eDP_AUX AE2 eDP I O DBR H61 Asynch CMOS eDP_COMPIO AC2 Analog I DC_TEST_A4 A4 N A eDP_HPD AE8 Asynch CMOS I DC_TEST_A62 A62 N A eDP_ICOMPO AB1 Analog I DC_TEST_A64 A64 N A eDP_TX 0 AG2 eDP DC_TEST_B3 B3 N A eDP_TX 1 AF1 eDP DC_TEST_B63 B63 N A eDP_TX 2 AE6 eDP DC_TEST_B65 B65 N A eDP_TX 3 AG6 eDP DC_TEST_BF1 BF1 N A eDP_TX 0 AG4 eDP DC_TEST_BF65 BF65 N A eDP TX 1 AF3 eDP DC_TEST_BG2 BG2 N A eDP_TX 2 AF7 eDP DC_TEST_BG64 BG64 N A eDP_TX 3 AGS eDP DC TEST BH1 BH1 N A FDI_INT AD9 Asynch CMOS I 125 intel List by Ball Name Table 8 2 BGA1224 Processor Ball Processor Pin and Signal Information List by Ball Name Table 8 2 BGA1224 Processor Ball 126 Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir FDI0_FSYNC AC8 CMOS I PEG_RX 3 F19 PCIe I FDI0_LSYNC AB7 CMOS I PEG_RX 4 K19 PCle I FDIO_TX 0 V7 FDI PEG_RX 5 H17 PCIe I FDIO_TX 1 w8 FDI PEG_RX 6 K15 PCIe I FDIO 4 2 FDI PEG_RX 7 G14 PCIe I FDIO TX 3 AC10 FDI PEG_RX 8 116 I FDIO_TX 0 6 FDI PEG_
80. 13 G10 PCIe I PEG TX 8 D15 PCIe PEG_RX 14 J8 PCIe I PEG TX 9 F17 PCIe PEG_RX 15 F7 PCIe I PEG TX 10 B13 PCIe _ 0 G22 PCIe I PEG TX 11 C10 PCIe _ 1 K23 PCIe I PEG TX 12 D11 PCIe _ 2 K21 PCIe I PEG TX 13 B9 PCIe Datasheet Volume 1 Processor Pin and Signal Information Table 8 2 BGA1224 Processor Ball List by Ball Name intel Table 8 2 BGA1224 Processor Ball List by Ball Name Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type bir PEG TX 14 D7 PCIe RSVD 14 PEG_TX 15 F13 PCle RSVD BB57 PM_SYNC K53 Asynch CMOS I RSVD BB43 PRDY J62 Asynch CMOS RSVD BB25 PREQ H65 Asynch CMOS I RSVD BB17 PROC_DETECT B59 Analog RSVD BB15 PROC_SELECT AH9 N A RSVD BB13 PROCHOT H51 Asynch CMOS 1 0 RSVD BA48 RESET K51 Asynch CMOS I RSVD BA16 RSVD G64 RSVD AY45 RSVD BJ42 RSVD AY41 RSVD BJ34 RSVD AY17 RSVD BJ22 RSVD AY15 RSVD BH43 RSVD AY13 RSVD BH35 RSVD AW5O RSVD BH25 RSVD AW46 RSVD BH23 RSVD AW42 RSVD BH21 RSVD AW14 RSVD BH19 RSVD AJ10 RSVD BG62 RSVD AJ6 RSVD BG34 RSVD AH5 RSVD BG26 RSVD AD5 RSVD BG22 RSVD AC6 RSVD BG4 RSVD ACA RSVD BF63 RSVD AAA RSVD BF43 RSVD P7 RSVD BF41 RSVD N6 RSVD BF35 RSVD M9 RSVD BF25 RSVD M5 RSVD BF23 RSVD L10 RSVD BF21 RSVD L6 RSVD BF19 RSVD 14 RSVD BF3 RSVD L2 RSVD BE
81. 2 PWR VCCIO AL48 PWR VCCPQE AM25 PWR VCCIO AL45 PWR VCCSA w20 PWR VCCIO AL26 PWR VCCSA V21 PWR VCCIO AL22 PWR VCCSA V18 PWR VCCIO AL20 PWR VCCSA V17 PWR VCCIO AL16 PWR VCCSA V16 PWR 150 Datasheet Volume 1 Processor Pin and Signal Information intel Table 8 3 1023 Processor Ball Table 8 3 1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VCCSA U15 PWR vss BG41 GND VCCSA R21 PWR vss BG37 GND VCCSA R18 PWR vss BG28 GND VCCSA R16 PWR vss BG24 GND VCCSA P20 PWR vss BG21 GND VCCSA P17 PWR vss BG17 GND VCCSA N22 PWR vss BG13 GND VCCSA N20 PWR vss BG9 GND VCCSA N16 PWR vss BE5 GND VCCSA L21 PWR vss BD56 GND VCCSA L17 PWR vss BD52 GND VCCSA_SENSE U10 Analog VSS BD48 GND VCCSA VID 0 D48 CMOS VSS BD44 GND VCCSA_VID 1 D49 CMOS VSS BD40 GND VDDQ BG33 PWR VSS BD36 GND VDDQ BB28 PWR VSS BD32 GND VDDQ 40 PWR VSS BD27 GND VDDQ AW26 PWR VSS BD23 GND VDDQ AV41 PWR vss BD19 GND VDDQ AR40 PWR VSS BD16 GND VDDQ AR36 PWR VSS BD12 GND VDDQ AR34 PWR VSS BD8 GND VDDQ AR32 PWR VSS BC57 GND VDDQ AR30 PWR VSS BC13 GND VDDQ AR28 PWR VSS BC5 GND VDDQ AR26 PWR VSS BB53 GND VDDQ AN38 PWR VSS 51 GND VDDQ AN34 PWR VSS BA48 GND VDDQ AN30 PWR VSS BA32 GND VDDQ AM40 PWR VSS BA26
82. 32 RSVD K49 RSVD BE16 RSVD K47 RSVD BE6 RSVD K9 RSVD BD33 RSVD K7 RSVD BD29 RSVD K5 RSVD BD19 RSVD 150 RSVD BD15 RSVD J4 RSVD BD13 RSVD J2 RSVD BC42 RSVD H49 RSVD BC30 RSVD H47 Datasheet Volume 1 intel Table 8 2 BGA1224 Processor Ball List by Ball Name Processor Pin and Signal Information Table 8 2 BGA1224 Processor Ball List by Ball Name Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir RSVD H5 SA_DQ 18 BG6 DDR3 I O RSVD G52 SA_DQ 19 AY9 DDR3 I O RSVD G48 SA DQ 20 AW8 DDR3 1 0 RSVD G4 SA_DQ 21 BB7 DDR3 I O RSVD F5 SA DQ 22 BC8 DDR3 1 0 RSVD D49 SA_DQ 23 BE4 DDR3 I O RSVD D25 SA DQ 24 AW12 DDR3 I O RSVD D3 SA DQ 25 11 DDR3 I O RSVD C52 SA DQ 26 BB11 DDR3 I O RSVD C24 SA 27 BA12 DDR3 I O RSVD C4 SA DQ 28 BE8 DDR3 I O RSVD B53 SA_DQ 29 BA10 DDR3 I O RSVD B25 SA DQ 30 BD11 DDR3 I O SA BS 0 BA36 DDR3 SA DQ 31 BE12 DDR3 I O SA BS 1 BC38 DDR3 SA_DQ 32 BB49 DDR3 I O SA BS 2 BB19 DDR3 SA_DQ 33 AY49 DDR3 I O SA_CAS BE44 DDR3 SA_DQ 34 BE52 DDR3 I O SA CKE 0 BC18 DDR3 SA_DQ 35 BD51 DDR3 I O SA CKE 1 BD17 DDR3 SA_DQ 36 BD49 DDR3 I O SA_CK 0 BA32 DDR3 SA_DQ 37 BE48 DDR3 1 0 SA_CK 1 AY33 DDR3 SA_DQ 38 BA52 DDR3 I O SA CK 0 BB31 DDR3 SA_DQ 39 AY51 DDR3 I O SA CK 1 AW
83. 34 DDR3 SA_DQ 40 BC54 DDR3 I O SA CS 0 BD41 DDR3 SA_DQ 41 AY53 DDR3 1 O SA_CS 1 BD45 DDR3 SA_DQ 42 AW54 DDR3 I O SA DQ 0 AL6 DDR3 I O SA DQ 43 AY55 DDR3 I O SA DQ 1 AL8 DDR3 I O SA_DQ 44 BD53 DDR3 I O SA DQ 2 AP7 DDR3 I O SA DQ 45 BB53 DDR3 I O SA DQ 3 5 DDR3 I O SA DQ 46 BE56 DDR3 I O SA DQ 4 AK7 DDR3 I O SA_DQ 47 BA56 DDR3 1 0 SA DQ 5 AL10 DDR3 I O SA DQ 48 BD57 DDR3 I O SA_DQ 6 AN10 DDR3 I O SA_DQ 49 BF61 DDR3 I O SA DQ 7 AM9 DDR3 I O SA DQ 50 BA60 DDR3 I O SA DQ 8 AR10 DDR3 SA_DQ 51 BB61 DDR3 I O SA DQ 9 AR8 DDR3 I O SA_DQ 52 BE60 DDR3 1 O SA_DQ 10 AV7 DDR3 I O SA DQ 53 BD63 DDR3 I O SA DQ 11 AY5 DDR3 SA_DQ 54 BB59 DDR3 1 0 SA DQ 12 AT5 DDR3 I O SA_DQ 55 BC58 DDR3 I O SA DQ 13 AR6 DDR3 I O SA_DQ 56 AW58 DDR3 I O SA DQ 14 AW6 DDR3 I O SA DQ 57 AY59 DDR3 I O SA DQ 15 AT9 DDR3 SA_DQ 58 AL60 DDR3 1 0 SA_DQ 16 BA6 DDR3 I O SA DQ 59 AP61 DDR3 I O SA DQ 17 BA8 DDR3 SA_DQ 60 AW60 DDR3 I O 128 Datasheet Volume 1 Processor Pin and Signal Information Table 8 2 BGA1224 Processor Ball List by Ball Name intel Table 8 2 BGA1224 Processor Ball List by Ball Name Datasheet Volume 1 Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir SA_DQ 61 AY57 DDR3 I O SB CKE
84. 4 2 5 4 52 Package C1 C1E No additional power reduction actions are taken in the package C1 state However if the C1E sub state is enabled the processor automatically transitions to the lowest supported core clock frequency followed by a reduction in voltage The package enters the C1 low power state when e At least one core is in the C1 state e The other cores are in a C1 or lower power state The package enters the C1E state when All cores have directly requested C1E using MWAIT C1 with a C1E sub state hint e All cores are in a power state lower that C1 C1E but the package low power state is limited to C1 C1E using the PMG CST CONFIG CONTROL MSR e All cores have requested C1 using HLT or MWAIT C1 and C1E auto promotion is enabled in IA32 MISC ENABLES No notification to the system occurs upon entry to Package C3 State A processor enters the package C3 low power state when e At least one core is in the C3 state e The other cores are in a C3 or lower power state and the processor has been granted permission by the platform The platform has not granted a request to a package C6 C7 state but has allowed a package C6 state In package C3 state the L3 shared cache is valid Package C6 State A processor enters the package C6 low power state when e At least one core is in the C6 state e The other cores are in a C6 or lower power state and the processor has been granted permission by the
85. 500 7 0 36000 8 0 36500 9 0 37000 0 38000 0 39500 F 0 40000 1 0 41000 0 0 0 00000 0 0 2 0 25500 0 3 0 26000 0 4 0 26500 0 5 0 27000 0 6 0 27500 0 7 0 28000 0 8 0 28500 0 9 0 29000 0 0 29500 0 0 30000 0 0 30500 0 D 0 31000 0 0 31500 0 F 0 32000 1 1 1 1 1 1 1 1 1 1 1 A 0 37500 1 1 C 0 38500 1 D 0 39000 1 1 2 0 0 40500 2 2 2 0 41500 2 3 0 42000 2 4 0 42500 2 5 0 43000 2 6 0 43500 2 7 0 44000 2 8 0 44500 2 9 0 45000 2 0 45500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 VID VID VID VID VID VID VID VID 7 87 Datasheet Volume 1 Electrical Specifications intel ion Sheet 2 of 3 VID VID VID VID VID VID VID VID 7 ini IMVP7 Voltage Identification Def 1 Table 7 x lt o gt HEX 1 10000 1 10500 1 11000 1 11500 1 12000 1 12500 1 13000 1 13500 1 14000 1 14500 1 15000 1 15500 1 16000 1 16500 1 17000 1 17500 1 18000 1 18500 1 19000 1 19500 1 20000 1 20500 1 21000 1 21500 1 22000 1 22500 1 23000 1 23500 1 24000 1 24500 1 25000 1 25500 1 26000 1 26500 1 270
86. 53 AU61 DDR3 10 SM DRAMPWROK BE45 lAsynch CMOS I SB DQ 54 AN58 DDR3 I O SM DRAMRST AT30 DDR3 SB_DQ 55 AR58 DDR3 1 0 SM_RCOMP 0 BF44 Analog 1 0 SB_DQ 56 AK58 DDR3 1 0 SM_RCOMP 1 BE43 Analog 1 0 SB_DQ 57 AL58 DDR3 1 0 SM_RCOMP 2 BG43 Analog 1 0 SB_DQ 58 AG58 DDR3 1 0 SM_VREF AY43 Analog I SB_DQ 59 AG59 DDR3 1 0 TCK L56 CMOS I SB_DQ 60 AM60 DDR3 I O TDI M60 CMOS I SB DQ 61 AL59 DDR3 10 TDO L59 CMOS SB_DQ 62 AF61 DDR3 1 0 THERMTRIP D45 Asynch 5 O SB_DQ 63 AH60 DDR3 1 0 TMS L55 CMOS I SB_DQS 0 AL3 DDR3 1 0 TRST 158 CMOS I SB_DQS 1 AV3 DDR3 10 UNCOREPWRGOOD B46 CMOS I SB_DQS 2 BG11 DDR3 I O VAXG AE46 PWR SB_DQS 3 BD17 DDR3 1 0 VAXG AD59 PWR SB_DQS 4 BG51 DDR3 I O VAXG AD58 PWR SB_DQS 5 BA59 DDR3 I O VAXG AD56 PWR SB DQSZ 6 AT60 DDR3 I O VAXG AD55 PWR SB DQSZ 7 AK59 DDR3 I O VAXG AD53 PWR SB DQS 0 AM2 DDR3 I O VAXG AD52 PWR SB_DQS 1 AV1 DDR3 I O VAXG AD51 PWR SB DQS 2 BE11 DDR3 I O VAXG AD50 PWR SB DQS 3 BD18 DDR3 I O VAXG AD48 PWR SB_DQS 4 BE51 DDR3 I O VAXG AD47 PWR SB_DQS 5 BA61 DDR3 1 0 VAXG AC61 PWR 148 Datasheet Volume 1 Processor Pin and Signal Information intel Table 8 3 1023 Processor Ball Table 8 3 BGA1023 Processor Ball List by Ball Name List by
87. 7 CMOS I FDI1_LSYNC H17 CMOS I CFG 16 AK31 CMOS I FDI1_TX 0 B21 FDI CFG 17 AN29 CMOS I FDI1_TX 1 C20 FDI DBR AL35 Asynch CMOS FDI1_TX 2 D18 FDI DMI_RX 0 B27 DMI I FDI1_TX 3 E17 FDI DMI_RX 1 B25 DMI I FDI1_TX 0 B20 FDI DMI_RX 2 A25 DMI I FDI1_TX 1 C19 FDI DMI_RX 3 B24 DMI I FDI1_TX 2 D19 FDI DMI_RX 0 B28 DMI I FDI1_TX 3 F17 FDI DMI RX 1 B26 DMI I KEY B1 N A N A DMI_RX 2 A24 DMI I PECI AN33 Asynch 1 0 DMI RX 3 B23 DMI I PEG ICOMPI 122 Analog I DMI_TX 0 G21 DMI 121 Analog I DMI_TX 1 E22 DMI RCOMPO H22 Analog I DMI_TX 2 F21 DMI _ 0 K33 PCle I DMI_TX 3 D21 DMI _ 1 35 PCle I DMI TX 0 G22 DMI _ 2 134 PCle I DMI TX 1 D22 DMI _ 3 135 PCle I DMI_TX 2 F20 DMI _ 4 132 PCle I Datasheet Volume 1 Processor Pin and Signal Information intel Table 8 1 rPGA988B Processor Pin Table 8 1 rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir PEG RX4 5 H34 PCIe I PEG TX 4 L28 PCIe PEG_RX 6 H31 PCIe I PEG TX 5 K30 PCIe _ 7 G33 PCIe I PEG TX 6 K27 PCIe PEG_RX 8 G30 PCIe I PEG TX 7 129 PCle PEG_RX 9
88. 9 GND VSS A37 GND VSS Ji GND VSS A33 GND VSS H58 GND VSS A28 GND VSS H53 GND VSS A25 GND VSS H21 GND VSS A21 GND VSS H17 GND VSS A17 GND VSS H14 GND VSS A13 GND VSS H10 GND VSS A9 GND VSS H4 GND VSS NCTF BG57 VSS G61 GND VSS NCTF BG5 VSS G51 GND VSS_NCTF BE58 vss G48 GND VSS_NCTF BE4 VSS G6 GND VSS_NCTF BD59 VSS F55 GND VSS_NCTF BD3 VSS F40 GND VSS_NCTF BC61 VSS F35 GND VSS NCTF E61 VSS F29 GND VSS NCTF El VSS Fi9 GND VSS_NCTF D59 VSS F15 GND VSS_NCTF C58 VSS F13 GND VSS NCTF C3 VSS E40 GND VSS NCTF A57 VSS E35 GND VSS NCTF A5 VSS E29 GND VSS SENSE G43 Analog VSS E25 GND VSS_SENSE_VDDQ BA43 Analog VSS E3 GND VSS_VAL_SENSE K43 Analog VSS D58 GND VSSAXG_SENSE G45 Analog VSS D54 GND VSSAXG VAL SENSE 45 Analog VSS D50 GND VSS SENSE VCCIO AN17 Analog VSS D46 GND VSS D43 GND VSS D40 GND VSS D35 GND VSS D29 GND VSS D26 GND VSS D22 GND VSS D18 GND VSS 014 GND VSS D10 GND VSS D6 GND 154 Datasheet Volume 1 Processor Pin and Signal Information 8 2 Package Mechanical Information Figure 8 13 Processor rPGA988B 2C GT2 Mechanical Package Sheet 1 of 2 L a r e 8 e _ amp ET
89. 9090000 0950 9 0 09020505000 050 000 0 950 050 09099 999 0000000000 0070 0 050502020 07070 0 0 00 0 0 0 407000 KCN NN ocococococo 9 999 9 07070202002 00 0 2050202070 95909090902 9990209 90202090209 25902020202 95959595950 05009020209 95902090909 05000005000 0000000 4 020 99999 9799 N 0909090050 05050595050 z 0 0 0 0 0 0 090959 9 9 9 0 0 0 050506 SN 2525252525 000000 095952592200 5 90000500050 000000 90929509950 2 90000005000 2 90000000000 05020205020 0705000020 0202020502 0 cococococo 05050505050 a 0 9 99 lo 29595959592 20202020 959 02090909090 NSW 52029920950 BK 520299590 2502000020 9595959 595959595959595959 050 050 050 020 0 0 0 9 9 90 o 0 0 o o o o 0000000000 5 209090909090009090900090909000909000000000909000 _ 950505020202072070707070705070202020207207020702020 99 05020 0202020707070702020202020202070707070902020 5 OO
90. 98259 9090000000000 899 0000000 29 29252222020 CC 000999090000 995999909250 L 0000500000000 904 59 000000000000000 0b 0000 900 000000000 94 3338999999099999999000000000 8388999998999090 8090 5 5900000089890999900 9999999 6000 9d 499 990000 990090 000 9o P83 0000 08 9959 000805 Zooo 9990000075 o99 9999 229208 0599 ooo 09999 99499 000896 99007 199 9990 9295002 966909 99999 9 45952955 9298 999888 5525 09989 909 20522592 3899 999899 2888 85889053 69 9 022902 900040 0 0 000 040 00 0 0 0 0 059 059 00 000 0000009 000 06 00 eo oo 9 98 m lt 159 Datasheet Volume 1 Processor Pin and Signal Information EE 0119 3931 117139 335 Wl Datasheet Volume 1 intel Figure 8 18 Processor BGA1023 2C GT2 Mechanical Package Sheet 2 of 2
91. AC p Rx AC Peak Common Mode Input Voltage 150 mV 1 PEG ICOMPO Comp Resistance 24 75 25 25 25 4 5 Comp Resistance 24 75 25 25 25 Q 5 PEG RCOMPO Comp Resistance 24 75 25 25 25 Q 4 5 Notes 1 Refer to the PCI Express Base Specification for more details 2 Vr x AC CM pp and are defined in the PCI Express Base Specification Measurement is made over at least 10 9 UI 3 As measured with compliance test load Defined as 2 V xp Vrxp 4 COMP resistance must be provided on the system board with 1 resistors COMP resistors to 5 PEG ICOMPO ICOMPI RCOMPO are the same resistor Intel allows using 24 9 1 resistors 6 RMS value 7 Measured at Rx pins into a pair of 50 Q terminations into ground Common mode peak voltage is defined by the expression max Vd Vd V CMDC 8 DC impedance limits are needed to ensure Receiver detect 9 The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled to ensure that the Receiver Detect occurs properly Compensation of this impedance can start immediately and the 15 Rx Common Mode Impedance constrained by RLRX CM to 50 20 must be within the specified range by the time Detect is entered 10 Low impedance defined during signaling Parameter is captured for 5 0 GHz by RLTX DIFF 11 This specification is the same as Vnx EYE 100 Datasheet Volume 1 Electrical Specif
92. AMT enabled chipset network hardware and software as well as connection with a power source and a corporate network connection Setup requires configuration by the purchaser and may require scripting with the management console or further integration into existing security frameworks to enable certain functionality It may also require modifications of implementation of new business processes With regard to notebooks Intel AMT may not be available or certain capabilities may be limited over a host OS based VPN or when connecting wirelessly on battery power sleeping hibernating or powered off For more information see http www intel com technology platform technology intel amt Intel Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability Intel Turbo Boost Technology performance varies depending on hardware software and overall system configuration Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology For more information see http www intel com technology turboboost Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See www intel com products processor_number for details Code names featured are used internally within Intel to identify products that are in development and not yet publicly announced for release Customers licensees and oth
93. AT57 GND VSS AL50 GND VSS AT50 GND VSS AL44 GND VSS AT44 GND VSS AL38 GND VSS AT38 GND VSS AL31 GND VSS AT31 GND VSS AL25 GND VSS AT25 GND VSS AL19 GND VSS AT19 GND VSS AK16 GND VSS AT11 GND VSS AK14 GND VSS AT7 GND VSS AK11 GND VSS AT3 GND VSS AK9 GND VSS AT1 GND vss AK5 GND vss AR54 GND vss AJ64 GND vss AR47 GND vss AJ62 GND vss AR41 GND vss AJ60 GND vss AR35 GND vss AJ57 GND vss AR28 GND vss AH7 GND vss AR22 GND vss AH3 GND vss AP65 GND vss AH1 GND vss AP63 GND vss AG57 GND vss AP57 GND vss AG17 GND vss AP50 GND vss AG15 GND vss AP44 GND vss AG12 GND vss AP38 GND vss AF65 GND 136 Datasheet Volume 1 Processor Pin and Signal Information Table 8 2 BGA1224 Processor Ball List by Ball Name intel Table 8 2 BGA1224 Processor Ball List by Ball Name Datasheet Volume 1 Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type bir VSS AF63 GND VSS R44 GND VSS AF61 GND VSS R38 GND VSS AF11 GND VSS R31 GND VSS AF9 GND VSS R25 GND VSS AF5 GND VSS R19 GND VSS AE57 GND VSS R17 GND VSS AD16 GND VSS R15 GND VSS AD14 GND VSS R12 GND VSS AD7 GND VSS P65 GND VSS AD3 GND VSS P63 GND VSS AD1 GND VSS P61 GND VSS AC64 GND VSS Pil GND VSS AC62 GND VSS P9 GND VSS AC60 GND VSS P5 GND VSS AC57 GND VSS N54 GND VSS AB11 GND VSS N47 GND VSS AB9 GND VSS N41 GND
94. AXG AP21 PWR VCC AF26 PWR VAXG AP23 PWR VCC AF27 PWR VAXG AP24 PWR VCC AF28 PWR VAXG AR17 PWR VCC AF29 PWR VAXG AR18 PWR VCC AF30 PWR VAXG AR20 PWR VCC AF31 PWR VAXG AR21 PWR VCC AF32 PWR VAXG AR23 PWR VCC AF33 PWR VAXG AR24 PWR VCC AF34 PWR VAXG AT17 PWR VCC AF35 PWR VAXG AT18 PWR VCC AG26 PWR VAXG AT20 PWR VCC AG27 PWR Datasheet Volume 1 intel 116 Processor Pin and Signal Information Table 8 1 rPGA988B Processor Pin Table 8 1 rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VCC AG28 PWR VCC v35 PWR VCC AG29 PWR VCC Y26 PWR VCC AG30 PWR VCC Y27 PWR VCC AG31 PWR VCC Y28 PWR VCC AG32 PWR VCC Y29 PWR VCC AG33 PWR VCC Y30 PWR VCC AG34 PWR VCC Y31 PWR VCC AG35 PWR VCC Y32 PWR VCC P26 PWR VCC Y33 PWR VCC P27 PWR VCC Y34 PWR VCC P28 PWR VCC Y35 PWR VCC P29 PWR VCC_DIE_SENSE AH27 Analog VCC P30 PWR VCC_SENSE AJ35 Analog VCC P31 PWR VCC_VAL_SENSE AJ33 Analog VCC P32 PWR VCCIO J23 PWR VCC P33 PWR VCCIO 11 PWR VCC P34 PWR VCCIO A12 PWR VCC P35 PWR VCCIO AC10 PWR VCC R26 PWR VCCIO AG10 PWR VCC R27 PWR VCCIO AH10 PWR VCC R28 PWR VCCIO AH13 PWR VCC R29 PWR VCCIO 812 PWR VCC R30 PWR VCCIO C11 PWR VCC R31 PWR VCCIO C12 PWR VCC R32 PWR VCCIO D11 PWR VCC R33 PWR VCCIO D12 PWR
95. Array VGA VGA is used for boot safe mode legacy games etc It can be changed by an application without OS driver notification due to legacy requirements Display Pipes The display pipe blends and synchronizes pixel data received from one or more display planes and adds the timing of the display output device upon which the image is displayed This is clocked by the Display Reference clock inputs The display pipes A and B operate independently of each other at the rate of 1 pixel per clock They can attach to any of the display ports Each pipe sends display data to the PCH over the Intel Flexible Display Interface Intel FDI Display Ports The display ports consist of output logic and pins that transmit the display data to the associated encoding logic and send the data to the display device that is LVDS HDMI DVI SDVO and so on All display interfaces connecting external displays are now repartitioned and driven from the PCH with the exception of the DisplayPort Embedded DisplayPort The Processor Graphics supports the Embedded DisplayPort eDP interface intended for display devices that are integrated into the system such as laptop LCD panel The DisplayPort abbreviated DP is different than the generic term display port The DisplayPort specification is a VESA standard DisplayPort consolidates internal and external connection methods to reduce device complexity support cross industry applications and provide p
96. B14 PCIe I PEG TX 5 B18 PCIe _ 7 D13 PCIe I PEG TX 6 K17 PCIe PEG_RX 8 A11 PCIe I PEG TX 7 G17 PCIe PEG_RX 9 B10 PCIe I PEG TX 8 E14 PCIe PEG_RX 10 G8 PCIe I PEG TX 9 C15 PCIe PEG_RX 11 A8 PCIe I PEG TX 10 K13 PCIe _ 12 B6 PCIe I PEG TX 11 G13 PCIe _ 13 H8 PCIe I PEG TX 12 K10 PCIe _ 14 5 1 _ 13 G10 PCle _ 15 K7 PCIe I PEG TX 14 D8 PCIe _ 0 K22 PCIe I PEG TX 15 K4 PCle _ 1 K19 PCIe I SYNC C48 CMOS I PEG RX 2 C21 PCIe I PRDY N53 5 PEG RX 3 D19 PCIe I PREQ N55 Asynch CMOS I PEG RX 4 C19 PCIe I PROC DETECT C57 Analog PEG_RX 5 D16 PCIe I PROC SELECT F49 N A PEG_RX 6 C13 PCIe I PROCHOT C45 Asynch CMOS 1 0 PEG_RX 7 D12 PCIe I RESET D44 Asynch CMOS I PEG_RX 8 C11 PCIe 1 RSVD BG26 PEG_RX 9 C9 PCIe I RSVD BG22 PEG RX 10 F8 PCIe I RSVD BG7 PEG RX 11 C8 PCIe I RSVD BF23 PEG RX 12 C5 PCIe I RSVD BE26 PEG RX 13 H6 PCIe I RSVD BE24 PEG RX 14 F6 PCIe I RSVD BE22 Datasheet Volume 1 145 m e n tel Processor Pin and Signal Information Table 8 3 BGA1023 Processor Ball Table 8 3 1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball Buffer Type Dir Ball Name
97. B_DQ 2 D10 AN3 AP3 005 SB DQ 3 C8 AR2 004 SB DQ 4 A9 AKA AL2 DQ00 SB_DQ 5 A8 AK3 AK1 DQ01 SB_DQ 6 D9 AN4 AP1 DQ06 SB_DQ 7 D8 1 AR4 007 SB_DQ 8 G4 AU4 AV3 DQ11 SB 0191 F4 AT2 AU4 DQ10 SB DQ 10 F1 AV4 BA4 DQ12 SB DQ 11 Gi BA4 BB1 DQ14 SB DQ 12 G5 AU3 AV1 DQ08 SB DQ 13 F5 AR3 AU2 009 SB DQ 14 F2 AY2 BA2 DQ13 SB DQ 15 G2 BA3 BB3 DQ15 SB DQ 16 77 BE9 BC2 DQ19 SB DQ 17 J8 BD9 BF7 DQ18 SB DQ 18 K10 BD13 BF11 DQ20 SB DQ 19 K9 BF12 BJ10 DQ22 SB_DQ 20 19 BF8 BC4 DQ17 SB 01211 J10 BD10 BH7 DQ16 SB 22 K8 BD14 BH11 DQ21 SB DQ 23 K7 BE13 BG10 DQ23 SB DQ 24 M5 BF16 BJ14 DQ25 SB_DQ 25 N4 BE17 BG14 DQ30 SB_DQ 26 N2 BE18 BF17 DQ29 SB_DQ 27 1 BE21 BJ18 DQ28 SB_DQ 28 M4 BE14 BF13 DQ24 SB_DQ 29 N5 BG14 BH13 DQ31 SB DQ 30 M2 BG18 BH17 DQ27 SB DQ 31 M1 BF19 BG18 DQ26 SB_DQ 32 AM5 BD50 BH49 DQ36 SB_DQ 33 AM6 BF48 BF47 DQ38 SB_DQ 34 AR3 BD53 BH53 DQ34 SB DQ 35 AP3 BF52 BG50 DQ35 SB DQ 36 AN3 BD49 BF49 DQ39 SB 01371 AN2 BE49 BH47 DQ37 SB DQ 38 AN1 BD54 BF53 DQ33 SB_DQ 39 AP2 BE53 BJ50 DQ32 SB DQ 40 BF56 BF55 DQ44 SB DQ 41 AN9 BE57 BH55 DQ43 Datasheet Volume 1 Table 9 2 DDR Data Swizzling intel Table Channel B Pin Pin Pin MC Pin Name Number Number Number Pin rPGA BGA1023 BGA1224 Name SB_DQ 42 AT5 BC59 BJ58 DQ47 SB_DQ 43 AT6 AY60 BH59 DQ46 SB_DQ 44 AP6 BE54 BJ54 DQ40
98. Ball Buffer Type Dir RSVD BE7 SA DQ 2 AP11 DDR3 1 0 RSVD BD26 SA_DQ 3 16 DDR3 1 0 RSVD BD25 SA_DQ 4 110 DDR3 1 0 RSVD BD22 SA DQ 5 AJ8 DDR3 10 RSVD BD21 SA_DQ 6 ALS DDR3 10 RSVD BB21 SA_DQ 7 AL7 DDR3 1 0 RSVD BB19 SA_DQ 8 AR11 DDR3 10 RSVD BA22 SA_DQ 9 6 DDR3 1 0 RSVD BA19 SA_DQ 10 AUG DDR3 1 0 RSVD AY22 SA_DQ 11 AV9 DDR3 1 0 RSVD AY21 SA_DQ 12 AR6 DDR3 1 0 RSVD AV19 SA_DQ 13 AP8 DDR3 1 0 RSVD AU21 SA DQ 14 AT13 DDR3 1 0 RSVD AU19 SA_DQ 15 AU13 DDR3 1 0 RSVD 49 SA_DQ 16 BC7 DDR3 10 RSVD AT21 SA_DQ 17 BB7 DDR3 1 0 RSVD 15 SA_DQ 18 BA13 DDR3 10 RSVD AM14 SA_DQ 19 BB11 DDR3 1 0 RSVD AH2 SA_DQ 20 BA7 DDR3 1 0 RSVD AG13 SA_DQ 21 BAS DDR3 1 0 RSVD W14 SA DQ 22 BB9 DDR3 1 0 RSVD U14 SA DQ 23 AY13 DDR3 1 0 RSVD P13 SA DQ 24 AV14 DDR3 1 0 RSVD N50 SA_DQ 25 AR14 DDR3 1 0 RSVD N42 SA_DQ 26 AY17 DDR3 1 0 RSVD M14 SA_DQ 27 AR19 DDR3 1 0 RSVD M13 SA_DQ 28 BA14 DDR3 10 RSVD L47 SA_DQ 29 AU14 DDR3 1 0 RSVD L45 SA_DQ 30 BB14 DDR3 1 0 RSVD L42 SA DQ 31 BB17 DDR3 1 0 RSVD K48 SA DQ 32 BA45 DDR3 10 RSVD K24 SA_DQ 33 AR43 DDR3 1 0 RSVD H48 SA_DQ 34 AW48 DDR3 10 SA_BS 0 BD37 DDR3 SA_DQ 35 BC48 DDR3 I O SA BS 1 BF36 DDR3 SA_DQ 36 BC45 DDR3 I O SA BS 2 BA28 DDR3 SA DQ 37 AR45 DDR3 1 0 SA_CAS BE39 DDR3 SA_DQ 38 AT48 DDR3 I O SA CKE 0 AY26 DDR3 SA_DQ 39 AY48 DDR3 I O SA CKE 1 BB26 DDR3 SA_DQ 40 BA49 DDR3 1 0 SA_CK 0 AV36 DDR3 SA DQ 41 AV49 DDR3 1 0 SA_CK 1 AU40 DDR3
99. Ball Name Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VAXG AB59 PWR VCC N34 PWR VAXG AB58 PWR VCC N30 PWR VAXG AB56 PWR VCC N26 PWR VAXG AB55 PWR VCC L40 PWR VAXG AB53 PWR VCC L36 PWR VAXG AB52 PWR VCC L33 PWR VAXG AB51 PWR VCC L28 PWR VAXG AB50 PWR VCC L25 PWR VAXG AB47 PWR VCC K42 PWR VAXG AA46 PWR VCC K39 PWR VAXG PWR VCC K37 PWR VAXG Y48 PWR VCC K35 PWR VAXG W61 PWR VCC K34 PWR VAXG W56 PWR VCC K32 PWR VAXG W55 PWR VCC K29 PWR VAXG W53 PWR VCC K27 PWR VAXG W52 PWR VCC K26 PWR VAXG W51 PWR VCC 142 PWR VAXG w50 PWR VCC J40 PWR VAXG v59 PWR VCC J38 PWR VAXG v58 PWR VCC J37 PWR VAXG v56 PWR VCC J35 PWR VAXG V55 PWR VCC J34 PWR VAXG V53 PWR VCC 132 PWR VAXG 52 PWR VCC 129 PWR VAXG V51 PWR VCC 128 PWR VAXG V50 PWR VCC 126 PWR VAXG V48 PWR VCC 125 PWR VAXG V47 PWR VCC H40 PWR VAXG U46 PWR VCC H38 PWR VAXG T61 PWR VCC H37 PWR VAXG T59 PWR VCC H35 PWR VAXG T58 PWR VCC H34 PWR VAXG T48 PWR VCC H32 PWR VAXG P61 PWR VCC H29 PWR VAXG P56 PWR VCC H28 PWR VAXG P55 PWR VCC H26 PWR VAXG P53 PWR VCC H25 PWR VAXG P52 PWR VCC G42 PWR VAXG P51 PWR VCC F42 PWR VAXG P50 PWR VCC F38 PWR VAXG P48 PWR VCC F37 PWR VAXG P47 PWR VCC F34 PWR VAXG N45 PWR VCC F32 PWR VAXG_SENSE F45 Analog VCC F28 PWR VAXG_VAL_SENSE H45 Analog VCC F26 PWR VCC N38 PWR VCC F25 PWR Datasheet Volume 1 149 m e n tel Processor Pin and Signal Information
100. CC has been activated if enabled This signal can also be driven to the processor to activate the TCC 81 intel Signal Description Table 6 12 Error and Thermal Protection Signals Sheet 2 of 2 Signal Name Description Direction Buffer Type Thermal Trip The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set 6 11 well above the normal operating temperature to ensure that there Eas no false trips The processor will stop all execution when the junction Asyncaronous temperature exceeds approximately 130 C This is signaled to the system by the THERMTRIP pin Power Sequencing Signals Table 6 13 Power Sequencing Signals Direction Signal Name Description Buffer Type SM_DRAMPWROK Processor Input Connects to PCH I SM_DRAMPWROK DRAMPWROK Asynchronous CMOS The processor requires this input signal to be a clean indication that the Vccsa and Vppo power supplies are stable and within specifications This requirement applies regardless of the S I state of the processor Clean implies that the signal will remain low UNCOREPWRGOOD capable of sinking leakage current without glitches from the time Async that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high sta
101. Control Signal This signal is used with SB CAS and SB WE along with SB_CS to define the SRAM Commands DDR3 SB CAS CAS Control Signal This signal is used with SB_RAS and SB_WE O along with SB_CS to define the SRAM Commands DDR3 Data Strobes SB_DQS 7 0 and its complement signal group make SB_DQS 7 0 up a differential strobe pair The data is captured at the crossing point I O SB_DQS 7 0 of SB_DQS 8 0 and its SB_DQS 7 0 during read and write DDR3 transactions SB_DQ 63 0 Data Bus Channel B data signal interface to the SDRAM data bus I O DDR3 SB 15 0 Memory Address These signals are used to provide the multiplexed _ 15 0 row and column address to the SDRAM DDR3 SDRAM Differential Clock Channel B SDRAM Differential clock signal SB_CK 1 0 pair The crossing of the positive edge of SB_CK and the negative edge of its complement SB_CK are used to sample the command DDR3 control signals on the SDRAM SB CK I1 0 SDRAM Inverted Differential Clock Channel B SDRAM Differential 0 1 0 clock signal pair complement DDR3 Clock Enable 1 per rank These signals are used to Initialize the SDRAMs during power up 5B_CK 1 0 e Power down SDRAM ranks DDR3 Place all SDRAM ranks into and out of self refresh during STR Chip Select 1 per rank These signals are used to select particular SB_CS 1 0 SDRAM components during the active state There is one Chip Select DDR3 for each SD
102. D VSS B17 GND VSS G20 GND VSS B19 GND VSS G23 GND VSS B2 GND VSS G26 GND VSS B22 GND vss G29 GND vss B3 GND VSS G32 GND VSS B5 GND VSS G35 GND VSS B7 GND VSS H1 GND VSS B8 GND VSS H10 GND VSS B9 GND VSS H13 GND VSS GND VSS H15 GND VSS C10 GND VSS H18 GND VSS C23 GND VSS H2 GND VSS C25 GND VSS H21 GND VSS C27 GND VSS H24 GND VSS C28 GND VSS H27 GND VSS C31 GND vss H3 GND vss C34 GND vss H30 GND vss D17 GND vss H33 GND vss D20 GND vss H4 GND vss D26 GND vss H5 GND vss D29 GND vss H6 GND vss D32 GND vss H7 GND vss D35 GND vss H8 GND vss El GND VSS H9 GND VSS E10 GND VSS J31 GND VSS E13 GND VSS 134 GND VSS E15 GND VSS K26 GND VSS E18 GND VSS K29 GND VSS E2 GND VSS K32 GND VSS E21 GND VSS K35 GND VSS E24 GND VSS L1 GND VSS E27 GND VSS L2 GND VSS E3 GND VSS 127 GND VSS E30 GND VSS L3 GND VSS E4 GND VSS L30 GND VSS E5 GND VSS L33 GND VSS E6 GND VSS L4 GND VSS E7 GND VSS L5 GND VSS E8 GND VSS L6 GND VSS E9 GND VSS L8 GND VSS F19 GND VSS L9 GND VSS F22 GND VSS M34 GND VSS F29 GND VSS N26 GND VSS F31 GND VSS N27 GND VSS F34 GND VSS N28 GND VSS G11 GND VSS N29 GND Datasheet Volume 1 119 intel 120 Processor Pin and Signal Information Table 8 1 rPGA988B Processor Pin Table 8 1 rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin Buffer Type D
103. DR3 O SB_DQ 24 BJ14 DDR3 I O SA MA 14 BE20 DDR3 O SB_DQ 25 BG14 DDR3 I O SA MA 15 AW18 DDR3 SB_DQ 26 BF17 DDR3 1 0 SA_ODT 0 BB41 DDR3 SB_DQ 27 BJ18 DDR3 1 0 SA ODT 1 BC46 DDR3 SB_DQ 28 BF13 DDR3 1 0 SA_RAS BE36 DDR3 SB_DQ 29 BH13 DDR3 I O SA WE BA44 DDR3 SB_DQ 30 BH17 DDR3 I O SB BS 0 BJ38 DDR3 SB_DQ 31 BG18 DDR3 1 0 SB_BS 1 BD37 DDR3 SB_DQ 32 BH49 DDR3 I O SB BS 2 AY29 DDR3 SB_DQ 33 BF47 DDR3 I O SB 5 BH39 DDR3 SB_DQ 34 BH53 DDR3 I O 129 intel 130 Table 8 2 BGA1224 Processor Ball List by Ball Name Processor Pin and Signal Information Table 8 2 BGA1224 Processor Ball List by Ball Name Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir SB_DQ 35 BG50 DDR3 I O SB DQS 6 AY65 DDR3 I O SB 36 BF49 DDR3 I O SB DQS 7 AN64 DDR3 I O SB DQ 37 BH47 DDR3 I O SB MA 0 BF31 DDR3 SB_DQ 38 BF53 DDR3 SB MA 1 BH31 DDR3 SB_DQ 39 BJ50 DDR3 58_ 2 8837 DDR3 SB_DQ 40 BF55 DDR3 I O SB MA 3 BC34 DDR3 SB_DQ 41 BH55 DDR3 1 O SB MA 4 BF27 DDR3 SB_DQ 42 BJ58 DDR3 1 0 SB_MA 5 BB33 DDR3 SB_DQ 43 BH59 DDR3 I O SB MA 6 BH27 DDR3 SB_DQ 44 BJ54 DDR3 I O SB MA 7 BG30 DDR3 SB_DQ 45 BG54 DDR3 1 0 5 8 BH29 DDR3 SB_DQ 46 BG58 DDR3 1 0 SB_MA 9 BF29 DDR3 SB_DQ 47 BF59 DDR3 I
104. Electrical Specifications 104 Datasheet Volume 1 Processor Pin and Signal Information m L D 8 Processor Pin and Signal Information 8 1 Processor Pin Assignments Table 8 1 Table 8 2 and Table 8 3 all pins ordered alphabetically for the rPGA988B BGA1224 and BGA1023 package respectively e Figure 8 1 Figure 8 2 Figure 8 3 and Figure 8 4 show the Top Down view of the rPGA988B pinmap e Figure 8 5 Figure 8 6 Figure 8 7 and Figure 8 8 show the Top Down view of the BGA1224 ballmap e Figure 8 9 Figure 8 10 Figure 8 11 and Figure 8 12 show the Top Down view of the BGA1023 ballmap Datasheet Volume 1 105 intel Figure 8 1 Processor Pin and Signal Information rPGA988B Socket G2 Pinmap Top View Upper Left Quadrant 35 34 33 RESET UNCO REPW RGOO BCLK BCLK_ PM_SY ITP NC VSS CATER DBR VSS R VAXG VSSA SENS XG_SE E NSE VSS 5 SENSE ENSE VSS vcc_ VAL_S ENSE VSS V AL SE NSE VSS VSS VCC n pP 32 31 30 29 28 27 26 PREQ CFG 1 CFG 1 CFG 1 0 5 1 CFG 4 THERM erp TRIP PROC T vss T ies VIDSC VIDAL vIDSO Bed ERT UT VSSA V AL_SE vss FG O Veen DIE_S ENSE VSS VSS VSS VCC VCC 25 24 23 22 21 18 106 Datasheet Volume 1 Processor Pin and Signal Information n tel Figure 8 2 rPGA988B Socket G2 Pinmap
105. Execution cores in this state behave similarly to the C6 state If all execution cores request C7 L3 cache ways are flushed until it is cleared Integrated Memory Controller States Power down Integrated Memory Controller States State Description Power up CKE asserted Active mode Pre charge CKE de asserted not self refresh with all banks closed Active Power Down Self Refresh CKE de asserted not self refresh with minimum one bank active CKE de asserted using device self refresh Datasheet Volume 1 Power Management 4 1 4 PCI Express Link States Table 4 4 PCI Express Link States State Description LO Full on Active transfer state LOs First Active Power Management low power state Low exit latency 1 Lowest Active Power Management Longer exit latency L3 Lowest power state power off Longest exit latency 4 1 5 Direct Media Interface DMI States Table 4 5 Direct Media Interface DMI States State Description LO Full on Active transfer state LOs First Active Power Management low power state Low exit latency L1 Lowest Active Power Management Longer exit latency L3 Lowest power state power off Longest exit latency 4 1 6 Processor Graphics Controller States Table 4 6 Processor Graphics Controller States State Description DO Full on display active D3 Cold Power off 4 1 7 Interface State Combinations T
106. G TX 15 E25 PCIe RSVD AM33 PEG_TX 0 M28 PCIe RSVD 115 PEG TX 1 M33 PCIe RSVD H16 PEG TX 2 M30 PCIe RSVD G16 PEG_TX 3 L31 PCIe RSVD B18 Datasheet Volume 1 111 m e n tel Processor Pin and Signal Information Table 8 1 rPGA988B Processor Pin Table 8 1 rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir RSVD AK32 SA_CKE 1 vio DDR3 RSVD AK2 SA CS 0 AK3 DDR3 RSVD 132 SA_CS 1 AL3 DDR3 RSVD AJ27 SA DIMM VREFDQ B4 N A RSVD AJ26 SA DQ 0 C5 DDR3 I O RSVD NCTF AT34 SA DQ 1 D5 DDR3 1 0 RSVD_NCTF B35 SA_DQ 2 D3 DDR3 1 0 RSVD_NCTF B34 SA_DQ 3 D2 DDR3 1 0 RSVD_NCTF A34 SA DQ 4 D6 DDR3 1 0 RSVD_NCTF A33 SA_DQ 5 C6 DDR3 1 0 RSVD_NCTF AT33 SA_DQ 6 C2 DDR3 I O RSVD NCTF AT2 SA DQ 7 C3 DDR3 1 0 RSVD_NCTF 1 SA_DQ 8 F10 DDR3 1 0 RSVD_NCTF AR35 SA_DQ 9 F8 DDR3 1 0 RSVD_NCTF AR34 SA_DQ 10 G10 DDR3 1 0 RSVD_NCTF AR1 SA DQ 11 G9 DDR3 1 0 RSVD_NCTF AP35 SA_DQ 12 F9 DDR3 1 0 RSVD_NCTF C35 SA_DQ 13 F7 DDR3 1 0 RSVD_TP w9 SA_DQ 14 G8 DDR3 1 0 RSVD_TP W10 SA DQ 15 G7 DDR3 1 0 RSVD_TP AA4 SA DQ 16 K4 DDR3 1 0 RSVD_TP AA3 SA_DQ 17 K5 DDR3 1 0 RSVD_TP AB4 SA_DQ 18 K1 DDR3 1 0 RSVD_TP AB3 SA_DQ 19 11 DDR3 1 0 RSVD_TP AG1 SA_DQ 20 15 DDR3 7 0 RSVD_TP AH1 SA_DQ 21 14 DDR3 1 0 RSVD
107. GND VSS BA38 GND VSS BE62 GND VSS BA34 GND VSS BE58 GND VSS BA30 GND VSS BE54 GND VSS BA26 GND VSS BE50 GND VSS BA22 GND VSS BE46 GND VSS BA18 GND VSS BE42 GND VSS BA14 GND VSS BE38 GND VSS AY61 GND VSS BE34 GND VSS AY11 GND VSS BE30 GND VSS AY7 GND VSS BE26 GND VSS AY3 GND VSS BE22 GND VSS AY1 GND VSS BE18 GND VSS AW56 GND VSS BE14 GND VSS AW52 GND VSS BE10 GND VSS AW48 GND VSS BD35 GND VSS AW44 GND VSS BD7 GND VSS AW40 GND VSS BD3 GND VSS AW36 GND VSS BC60 GND VSS AW32 GND VSS BC56 GND VSS AW28 GND VSS BC52 GND VSS AW24 GND VSS BC48 GND VSS AW16 GND VSS BC44 GND VSS AV65 GND 135 m e n tel Processor Pin and Signal Information Table 8 2 BGA1224 Processor Ball Table 8 2 BGA1224 Processor Ball List by Ball Name List by Ball Name Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VSS AV63 GND VSS AP31 GND VSS AV59 GND VSS AP25 GND VSS AV57 GND VSS AP19 GND VSS AV50 GND VSS AP17 GND VSS AV44 GND VSS AP15 GND VSS AV38 GND VSS AP12 GND VSS AV31 GND VSS AP11 GND VSS AV25 GND VSS AP9 GND VSS AV19 GND VSS AP5 GND VSS AV9 GND VSS AN54 GND VSS AV5 GND VSS AN47 GND VSS AU54 GND VSS AN41 GND VSS AU47 GND VSS AN35 GND VSS AU41 GND VSS AN28 GND VSS AU35 GND VSS AN22 GND VSS AU28 GND VSS AM61 GND VSS AU22 GND VSS AM7 GND VSS AU16 GND VSS AM3 GND VSS AU14 GND VSS AM1 GND VSS AT61 GND VSS AL57 GND VSS
108. Groups Sheet 3 of 3 Signal Group Type Signals Intel FDI Single Ended CMOS Input EH ENC FDI1FSYNC FDIO_LSYNC Single Ended CMOS EDI INT Differential FDI Output FDIO TX 3 0 FDIO_TX 3 0 FDI1 TX 3 0 FDI1_TX 3 0 Future Compatibility PROC_SELECT VCCSA_VID 0 VCCIO_SEL SA_DIMM_VREFDQ SB_DIMM_VREFDQ Notes 1 Refer to Chapter 6 for signal description details 2 SAand SB refer to DDR3 Channel A and DDR3 Channel B 3 These signals only apply to BGA packages 4 The maximum rise fall time of UNCOREPWRGOOD is 20 ns All Control Sideband Asynchronous signals are required to be asserted de asserted for at least 10 BCLKs with a maximum Trise Tfall of 6 ns for the processor to recognize the proper signal state See Section 7 10 for the DC specifications Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic Intel recommends the processor be first in the TAP chain followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Two copies of each signal may be required with each driving a different voltage level The processor supports Boundary Scan JTAG IEEE 1149 1 2001 and IEEE 1149 6 2003 standards Some small portion of the I O pins may support only one of
109. J6 GND VSS C46 GND VSS H39 GND VSS C42 GND VSS H33 GND VSS C36 GND VSS H27 GND VSS C30 GND VSS H3 GND VSS C20 GND VSS G62 GND VSS C16 GND VSS G58 GND VSS C12 GND VSS G54 GND VSS C8 GND VSS G50 GND VSS B39 GND VSS G46 GND VSS B33 GND VSS G42 GND VSS B27 GND VSS G36 GND VSS A56 GND VSS G30 GND VSS A52 GND VSS G24 GND VSS A42 GND VSS G20 GND VSS A36 GND VSS G16 GND VSS A30 GND VSS G12 GND VSS A24 GND VSS G8 GND VSS A20 GND VSS F39 GND VSS A16 GND VSS F33 GND VSS A12 GND VSS F27 GND VSS A8 GND VSS E60 GND VSS_NCTF BJ60 VSS E56 GND VSS_NCTF BJ6 138 Datasheet Volume 1 Processor Pin and Signal Information Table 8 2 BGA1224 Processor Ball List by Ball Name Ball Name Ball Buffer Type Dir VSS_NCTF BH61 VSS NCTF BH5 VSS NCTF BE64 VSS NCTF BE2 VSS NCTF BD65 VSS NCTF BD1 VSS_NCTF F65 VSS_NCTF Fi VSS NCTF E64 VSS NCTF E2 VSS NCTF B61 VSS NCTF B5 VSS NCTF A60 VSS NCTF A6 VSS SENSE A46 Analog VSS_SENSE_VDDQ AW20 Analog VSS_VAL_SENSE C48 Analog O VSSAXG_SENSE E50 Analog VSSAXG VAL SENSE A48 Analog VSS SENSE VCCIO AU10 Analog Datasheet Volume 1 139 intel Processor Pin and Signal Information Figure 8 9 BGA1023 Ballmap Top View Upper Left Quadrant
110. L10 GND VSS AT4 GND VSS AK52 GND VSS AR61 GND VSS AK1 GND VSS AR48 GND VSS AJ48 GND VSS AR41 GND VSS AJ45 GND VSS AR21 GND VSS AJ42 GND VSS AR17 GND VSS AJ38 GND VSS AR13 GND VSS AJ34 GND VSS AR7 GND VSS AJ30 GND VSS AP55 GND VSS AJ26 GND VSS AP51 GND VSS AJ22 GND VSS AP10 GND VSS AJ20 GND VSS AP7 GND VSS AJ16 GND VSS AN54 GND VSS AJ13 GND VSS 50 GND VSS AJ7 GND VSS AN47 GND VSS AH58 GND VSS AN43 GND VSS AH4 GND VSS AN40 GND VSS AG61 GND VSS AN36 GND VSS AG52 GND VSS AN33 GND VSS AG47 GND VSS AN28 GND VSS AG18 GND VSS AN25 GND VSS AG14 GND VSS AN21 GND VSS AG10 GND VSS AN1 GND VSS AG7 GND VSS AM58 GND VSS AF59 GND VSS AM48 GND VSS AF58 GND VSS AM45 GND VSS AF56 GND 152 Datasheet Volume 1 Processor Pin and Signal Information intel Table 8 3 BGA1023 Processor Ball Table 8 3 BGA1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VSS AF55 GND VSS U8 GND VSS AF53 GND VSS T56 GND VSS AF52 GND VSS T55 GND VSS AF51 GND VSS T53 GND VSS AF50 GND VSS T52 GND VSS AF48 GND VSS T51 GND VSS AF47 GND VSS T50 GND VSS AF21 GND VSS T47 GND VSS AF17 GND VSS GND VSS AF1 GND VSS R46 GND VSS AE13 GND VSS R20 GND VSS AE8 GND VSS R17 GND VSS AD61 GND VSS
111. N CTL Resistance P us 5 Input Leakage Current DQ 0 75 I 0 2 Vppg 0 55 mA 0 8 Vppo 0 9 Vppq 1 4 Input Leakage Current CMD CTL 0 85 0 2 Vppo 0 65 mA VDDQ 1 65 SM RCOMPO Command COMP Resistance 138 6 140 141 4 Q SM_RCOMP1 Data COMP Resistance 25 74 26 26 26 Q SM_RCOMP2 ODT COMP Resistance 198 200 202 Q 8 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value 3 is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 signal quality specifications 5 This is the pull up down driver resistance 6 7 8 to Vss 9 DDR3 values pre silicon estimations and are subject to change 1 edge must be monotonic SM VREF is defined as Vppo 2 Datasheet Volume 1 is the termination on the DIMM and not controlled by the Processor Vin and Voy may experience excursions above Vppo However input signal drivers must comply with the The minimum and maximum values for these signals are programmable by BIOS to one of the two sets SM RCOMPx resistance must be provided the system board with 1 resistors SM RCOMPXx resistors 0 SM DRAMPWROK must have a maximum of 15 ns rise or fall time over 0 55 200 mV
112. Notes 1 Unless otherwise noted all specifications in this table are based on post silicon estimates and simulations or empirical data 2 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range This differs from the VID employed by the processor during a power or thermal management event Intel Adaptive Thermal Monitor Enhanced Intel SpeedStep Technology or Low Power States 3 The voltage specification requirements are measured across VCC SENSE and VSS SENSE lands at the Socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe 4 PSx refers to the voltage regulator power state as set by the SVID protocol 5 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range This differs from the VID employed by the processor during a power or thermal management event Inte
113. PCH ENS RSVD RESERVED All signals that RSVD and RSVD NCTF must be left No Connect RSVD TP unconnected on the board However Intel recommends that all RSVD TP Test Point signals have using test points iti RSVD_NCTF J dixil Non Critical to Function DDR3 DRAM Reset Reset signal from processor to DRAM devices One SM_DRAMRST common to all channels CMOS 78 Datasheet Volume 1 Signal Description 6 4 Table 6 6 6 5 Table 6 7 PCI Express Based Interface Signals PCI Express Graphics Interface Signals ntel PEG_RX 15 0 PEG_RX 15 0 PCI Express Receive Differential Pair Signal Name Description PEG ICOMPI PCI Express Input Current Compensation 1 PEG_ICOMPO PCI Express Current Compensation 1 PEG_RCOMPO PCI Express Resistance Compensation n I PCI Express PEG TX 15 0 PEG TX 15 0 PCI Express Transmit Differential Pair PCI Express Embedded DisplayPort eDP Signals Embedded DisplayPort Signals Direction Signal Name Description Buffer Type eDP_TX 3 0 Embedded DisplayPort Transmit Differential Pair eDP_TX 3 0 Diff eDP_AUX Embedded DisplayPort Auxiliary Differential Pair IO eDP AUX Diff Embedded DisplayPort Hot Plug Detect I eDP HPD Asynchronous CMOS eDP COMPIO Embedded DisplayPort Current Compensation H eDP Embedded DisplayPort Current Compensation Hi Datasheet Volume 1
114. PDLL 10 20 according to DDR type cycles until first data transfer is allowed The processor supports 5 different types of power down The different modes are the power down modes supported by DDR3 and combinations of these The type of CKE power down is defined by the configuration The are options are 1 No power down 2 APD The rank enters power down as soon as idle timer expires no matter what is the bank status 3 PPD When idle timer expires the MC sends PRE all to rank and then enters power down 4 DLL off same as option 2 but DDR is configured to DLL off 5 APD change to PPD APD PPD Begins as option 1 and when all page close timers of the rank are expired it wakes the rank issues PRE all and returns to PPD APD change to DLL off APD DLLoff Begins as option 1 and when all page close timers of the rank are expired it wakes the rank issues PRE all and returns to DLL off power down The CKE is determined per rank when it is inactive Each rank has an idle counter The idle counter starts counting as soon as the rank has no accesses and if it expires the rank may enter power down while no new transactions to the rank arrive to queues The idle counter begins counting at the last incoming transaction arrival It is important to understand that since the power down decision is per rank the MC can find many opportunities to power down ranks even while running memory intensive applications and savings are s
115. Processor Ball List by Ball Name intel Table 8 2 BGA1224 Processor Ball List by Ball Name Datasheet Volume 1 Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type bir VAXG AF58 PWR VAXG N56 PWR VAXG AF56 PWR VAXG N52 PWR VAXG AE64 PWR VAXG N49 PWR VAXG AE62 PWR VAXG M65 PWR VAXG AE60 PWR VAXG M63 PWR VAXG AD65 PWR VAXG M61 PWR VAXG AD63 PWR VAXG M59 PWR VAXG AD61 PWR VAXG M55 PWR VAXG AD58 PWR VAXG M53 PWR VAXG AD56 PWR VAXG M48 PWR VAXG AB65 PWR VAXG L56 PWR VAXG AB63 PWR VAXG L52 PWR VAXG AB61 PWR VAXG L48 PWR VAXG AB58 PWR VAXG_SENSE F49 Analog 56 PWR VAXG_VAL_SENSE B49 Analog AA64 PWR VCC R46 PWR VAXG AA62 PWR VCC R42 PWR VAXG AA60 PWR VCC R40 PWR VAXG Y58 PWR VCC R36 PWR VAXG Y56 PWR VCC R34 PWR VAXG W64 PWR VCC R29 PWR VAXG W62 PWR VCC R27 PWR VAXG W60 PWR VCC R23 PWR VAXG V65 PWR VCC R21 PWR VAXG V63 PWR VCC N45 PWR VAXG V61 PWR VCC N43 PWR VAXG V58 PWR VCC N39 PWR VAXG V56 PWR VCC N37 PWR VAXG T65 PWR VCC N33 PWR VAXG T63 PWR VCC N30 PWR VAXG T61 PWR VCC N26 PWR VAXG T58 PWR VCC N24 PWR VAXG T56 PWR VCC N20 PWR VAXG R64 PWR VCC M46 PWR VAXG R62 PWR VCC M42 PWR VAXG R60 PWR VCC M40 PWR VAXG R55 PWR VCC M36 PWR VAXG R53 PWR VCC M34 PWR VAXG R48 PWR VCC M29 PWR VAXG N64 PWR VCC M27 PWR VAXG N62 PWR VCC M23 PWR VAXG N60 PWR VCC M21 PWR VA
116. Q TMS Pull Up VCCIO 5 15 TRST Pull Up VCCIO 5 15 CFG 17 0 Pull Up VCCIO 5 15 kQ 58 Datasheet Volume 1 Electrical Specifications L 7 7 1 7 2 Caution 7 2 1 7 2 2 Electrical Specifications Power and Ground Pins The processor has VCC VCCIO VDDQ VCCPLL VCCSA VAXG and VSS ground inputs for on chip power distribution All power pins must be connected to their respective processor power planes while all VSS pins must be connected to the system ground plane Use of multiple power and ground planes is recommended to reduce I R drop The VCC pins and VAXG pins must be supplied with the voltage determined by the processor Serial Voltage IDentification SVID interface Table 7 1 specifies the voltage level for the various VIDs Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large current swings between low and full power states To keep voltages within specification output decoupling must be properly designed Design the board to ensure that the voltage provided to the processor remains within the specifications listed in Table 7 3 Failure to do so can result in timing violations or reduced lifetime of the processor Voltage Rail Decoupling The voltage regulator solution must e provide sufficient decoupling to compensate for large current swings generated during different power mode tra
117. Q 47 ALS DDR3 1 0 SA_MA 14 V5 DDR3 SA_DQ 48 AP11 DDR3 1 0 SA_MA 15 V7 DDR3 SA_DQ 49 AN11 DDR3 1 0 SA_ODT 0 AH3 DDR3 SA_DQ 50 AL12 DDR3 1 0 SA_ODT 1 AG3 DDR3 SA_DQ 51 AM12 DDR3 1 SA_RAS AD9 DDR3 SA_DQ 52 AM11 DDR3 1 0 SA_WE AF9 DDR3 SA_DQ 53 AL11 DDR3 1 0 SB_BS 0 AA9 DDR3 SA_DQ 54 AP12 DDR3 1 0 SB_BS 1 AA7 DDR3 SA_DQ 55 AN12 DDR3 1 0 SB_BS 2 R6 DDR3 SA_DQ 56 114 DDR3 1 0 SB_CAS AA10 DDR3 SA_DQ 57 AH14 DDR3 1 0 SB_CK 0 AD2 DDR3 SA_DQ 58 AL15 DDR3 1 0 SB_CK 1 AD1 DDR3 SA_DQ 59 AK15 DDR3 1 0 SB_CK 0 AE2 DDR3 SA_DQ 60 AL14 DDR3 1 0 SB_CK 1 3 SA_DQ 61 AK14 DDR3 1 0 SB_CKE 0 R9 DDR3 SA_DQ 62 AJ15 DDR3 1 0 SB_CKE 1 R10 DDR3 SA_DQ 63 AH15 DDR3 I O SB_CS 0 AD3 DDR3 SA_DQS 0 C4 DDR3 I O SB CSZ 1 AE3 DDR3 SA_DQS 1 G6 DDR3 1 0 SB DIMM VREFDQ Di N A SA_DQS 2 J3 DDR3 I O SB DQ 0 C9 DDR3 I O SA DQS 3 M6 DDR3 1 0 SB 1 A7 DDR3 1 0 SA_DQS 4 AL6 DDR3 1 0 SB_DQ 2 D10 DDR3 1 0 SA_DQS 5 8 DDR3 I O SB DQI 3 C8 DDR3 I O SA_DQS 6 AR12 DDR3 1 0 SB_DQ 4 A9 DDR3 1 0 SA_DQS 7 AM15 DDR3 1 0 SB DQ 5 A8 DDR3 1 0 SA_DQS 0 D4 DDR3 1 O SB_DQ 6 D9 DDR3 I O SA DQS 1 F6 DDR3 1 0 SB DQ 7 D8 DDR3 1 0 SA_DQS 2 K3 DDR3 I O SB DQI 8 G4 DDR3 I O SA DQS 3 N6 DDR3 I O SB DQI 9 F4 DDR3 I O SA DQS 4 ALS DDR3 1 0 SB_DQ 10 F1 DDR3 1 0 SA_DQS 5 AM9 DDR3 1 0 SB DQ 11 G1 DDR3 SA_DQS 6 AR11 DDR3 1 0 SB_DQ 12 G5 DDR3 10 SA_DQS 7 AM14 DD
118. R3 1 0 SB_DQ 13 F5 DDR3 1 0 SA MA 0 AD10 DDR3 SB DQ 14 F2 DDR3 1 0 SA_MA 1 wi DDR3 SB_DQ 15 G2 DDR3 10 SA_MA 2 w2 DDR3 SB_DQ 16 17 DDR3 1 0 SA_MA 3 W7 DDR3 SB_DQ 17 J8 DDR3 1 0 SA_MA 4 v3 DDR3 SB_DQ 18 K10 DDR3 1 0 SA_MA 5 v2 DDR3 SB_DQ 19 K9 DDR3 1 0 SA_MA 6 w3 DDR3 SB_DQ 20 J9 DDR3 I O SA MA 7 W6 DDR3 SB_DQ 21 J10 DDR3 1 0 SA_MA 8 V1 DDR3 SB_DQ 22 K8 DDR3 1 0 SA_MA 9 w5 DDR3 SB_DQ 23 K7 DDR3 1 0 Datasheet Volume 1 113 m e n tel Processor Pin and Signal Information Table 8 1 rPGA988B Processor Pin Table 8 1 rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir SB DQ 24 M5 DDR3 1 0 SB_DQS 7 AP15 DDR3 1 0 SB_DQ 25 N4 DDR3 I O SB DQS 0 C7 DDR3 I O SB 26 N2 DDR3 I O SB DQS 1 G3 DDR3 I O SB 27 1 DDR3 I O SB DQS 2 J6 DDR3 1 0 SB_DQ 28 M4 DDR3 I O SB DQS 3 M3 DDR3 I O SB DQ 29 N5 DDR3 1 0 SB_DQS 4 AN6 DDR3 1 0 SB_DQ 30 M2 DDR3 I O SB DQS 5 AP8 DDR3 1 0 SB_DQ 31 M1 DDR3 1 0 SB_DQS 6 AK11 DDR3 1 0 SB_DQ 32 AM5 DDR3 10 SB_DQS 7 AP14 DDR3 1 0 SB_DQ 33 AM6 DDR3 1 0 SB DDR3 SB_DQ 34 AR3 DDR3 10 SB_MA 1 T7 DDR3 SB_DQ 35 AP3 DDR3 10 SB_MA 2 R7 DDR3 SB_DQ 36 AN3 DDR3 I O SB MA 3 T6 DDR3 SB_DQ 37
119. RAM rank SB ODT 1 0 On Die Termination Active Termination Control DDR3 Memory Reference and Compensation Signals Memory Reference and Compensation Direction Signal Name Description Buffer Type SM_RCOMP 2 0 SM_VREF System Memory Impedance Compensation DDR3 Reference Voltage This provides reference voltage to the DDR3 interface and is defined as 2 I A gt Datasheet Volume 1 77 Signal Description intel 6 3 Reset and Miscellaneous Signals Table 6 5 Reset and Miscellaneous Signals Direction Signal Name Description Buffer Type Configuration Signals The CFG signals have a default value of 1 if not terminated on the board e CFG 1 0 Reserved configuration lane A test point may be placed on the board for this lane e CFG 2 PCI Express Static x16 Lane Numbering Reversal 1 Normal operation 0 Lane numbers reversed CFG 3 Reserved CFG 4 eDP enable I CFG 17 0 1 Disabled CMOS 0 Enabled CFG 6 5 PCI Express Bifurcation 00 1 x8 2 x4 PCI Express 01 Reserved 10 2 8 PCI Express 11 1x16 PCI Express CFG 17 7 Reserved configuration lanes A test point may be placed on the board for these lands PM SYNC Power Management Sync A sideband signal to communicate power I management status from the platform to the processor CMOS RESET Platform Reset pin driven by the
120. REF CLK Embedded Display Port PLL Differential Clock In 120 MHz I DPLL REF CLK Diff Clk Datasheet Volume 1 Signal Description 6 9 Test Access Points TAP Signals Table 6 11 Test Access Points TAP Signals 6 10 TT Direction Signal Name Description Buffer Type Breakpoint and Performance Monitor Signals These signals are outputs from the processor that indicate the status of breakpoints I O BPM 7 0 pe and programmable counters used for monitoring processor CMOS performance BCLK ITP These pins are connected in parallel to the top side debug probe to I BCLK_ITP enable debug capacities DBR is used only in systems where no debug port is implemented DBR on the system board DBR is used by a debug port interposer so that in target probe can drive system reset PRDY is a processor output used by debug tools to determine PRDY processor debug readiness Asynchronous CMOS PREQ is used by debug tools to request debug operation of the I PREQ processor Asynchronous CMOS TCK Test Clock This signal provides the clock input for the I TCK processor Test Bus also known as the Test Access Port TCK must be CMOS driven low or allowed to float during power on Reset TDI Test Data In This signal transfers serial test data into the I TDI processor TDI provides the serial input needed for JTAG specification CMOS support TDO Test Data Out This signal transfers serial test data out of the
121. RX 9 K13 PCIe I FDIO TX 1 W10 FDI PEG RX 10 F11 PCIe I FDIO TX 2 Y9 FDI PEG RX 11 K11 PCIe I FDIO TX 3 AA10 FDI RX 12 F9 PCIe I FDI1 FSYNC AA2 CMOS I PEG RX 13 H9 PCIe I FDI1 LSYNC AB3 CMOS I PEG RX 14 H7 PCIe I FDI1_TX 0 U4 FDI PEG_RX 15 G6 PCIe I FDI1_TX 1 w2 FDI PEG_TX 0 A22 PCIe FDI1_TX 2 vi FDI _ 1 B23 PCIe FDI1_TX 3 Y5 FDI PEG_TX 2 C18 PCIe FDI1_TX 0 U2 FDI _ 3 D21 PCIe O FDI1_TX 1 4 FDI _ 4 B19 PCIe FDI1_TX 2 FDI _ 5 20 FDI1_TX 3 AA6 FDI _ 6 14 PECI F53 Asynch I O PEG_TX 7 D17 PCIe PEG_ICOMPI G2 Analog I PEG_TX 8 B15 PCIe 1 Analog I PEG_TX 9 E16 PCIe PEG_RCOMPO F3 Analog I PEG_TX 10 D13 PCIe PEG_RX 0 F23 PCIe I PEG TX 11 A10 PCIe O PEG_RX 1 H23 PCIe I PEG TX 12 Bil PCIe _ 2 H21 PCIe I PEG TX 13 D9 PCIe _ 3 H19 PCIe I PEG TX 14 B7 PCIe _ 4 120 1 _ 15 12 PEG_RX 5 G18 PCIe I PEG TX 0 C22 PCIe PEG_RX 6 K17 PCIe I PEG TX 1 D23 PCIe _ 7 15 I PEG_TX 2 A18 PCIe 9 PEG RX 8 H15 PCIe I PEG TX 3 B21 PCIe O PEG_RX 9 H13 PCIe I PEG TX 4 D19 PCIe O PEG_RX 10 H11 PCIe I PEG TX 5 F21 PCIe O PEG_RX 11 112 1 _ 6 C14 PCIe O PEG_RX 12 E8 PCIe I PEG TX 7 B17 PCIe PEG_RX
122. S 6 AK12 DDR3 1 0 VAXG AH21 PWR 114 Datasheet Volume 1 Processor Pin and Signal Information intel Table 8 1 rPGA988B Processor Pin Table 8 1 rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VAXG AH23 PWR VAXG AT21 PWR VAXG AH24 PWR VAXG AT23 PWR VAXG AJ17 PWR VAXG AT24 PWR VAXG AJ18 PWR VAXG SENSE AK35 Analog 120 PWR VAXG_VAL_SENSE AJ31 Analog 121 PWR VCC AA26 PWR VAXG 123 PWR VCC AA27 PWR VAXG AJ24 PWR VCC AA28 PWR VAXG AK17 PWR VCC AA29 PWR VAXG AK18 PWR VCC AA30 PWR VAXG AK20 PWR VCC AA31 PWR VAXG AK21 PWR VCC AA32 PWR VAXG AK23 PWR VCC AA33 PWR VAXG AK24 PWR VCC AA34 PWR VAXG AL17 PWR VCC AA35 PWR VAXG AL18 PWR VCC AC26 PWR VAXG AL20 PWR VCC AC27 PWR VAXG AL21 PWR VCC AC28 PWR VAXG AL23 PWR VCC AC29 PWR VAXG AL24 PWR VCC AC30 PWR VAXG AM17 PWR VCC AC31 PWR VAXG AM18 PWR VCC AC32 PWR VAXG AM20 PWR VCC AC33 PWR VAXG AM21 PWR VCC AC34 PWR VAXG AM23 PWR VCC AC35 PWR VAXG AM24 PWR VCC AD26 PWR VAXG AN17 PWR VCC AD27 PWR VAXG AN18 PWR VCC AD28 PWR VAXG AN20 PWR VCC AD29 PWR VAXG AN21 PWR VCC AD30 PWR VAXG AN23 PWR VCC AD31 PWR VAXG AN24 PWR VCC AD32 PWR VAXG AP17 PWR VCC AD33 PWR VAXG AP18 PWR VCC AD34 PWR VAXG AP20 PWR VCC AD35 PWR V
123. SA_DQ 42 BB51 DDR3 1 0 SA CK 0 AU36 DDR3 SA_DQ 43 AY53 DDR3 I O SA CK 1 AT40 DDR3 SA_DQ 44 BB49 DDR3 1 0 SA_CS 0 BB40 DDR3 SA_DQ 45 AU49 DDR3 1 0 SA_CS 1 BC41 DDR3 SA_DQ 46 BA53 DDR3 1 0 5 AG6 DDR3 1 0 SA_DQ 47 BB55 DDR3 1 0 SA DQ 1 AJ6 DDR3 1 0 SA_DQ 48 BA55 DDR3 10 146 Datasheet Volume 1 Processor Pin and Signal Information intel Table 8 3 1023 Processor Ball Table 8 3 1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir SA DQ 49 AV56 DDR3 10 SA ODT 0 AY40 DDR3 SA_DQ 50 AP50 DDR3 10 SA_ODT 1 BA41 DDR3 SA_DQ 51 AP53 DDR3 1 0 SA_RAS BD39 DDR3 SA_DQ 52 AV54 DDR3 1 0 SA_WE AT41 DDR3 SA_DQ 53 AT54 DDR3 I O SB BS 0 BG39 DDR3 SA_DQ 54 AP56 DDR3 10 SB_BS 1 BD42 DDR3 SA_DQ 55 AP52 DDR3 10 SB_BS 2 AT22 DDR3 SA_DQ 56 AN57 DDR3 1 0 SB_CAS AV43 DDR3 SA_DQ 57 AN53 DDR3 10 SB CKE 0 AR22 DDR3 SA_DQ 58 AG56 DDR3 1 0 SB_CKE 1 BF27 DDR3 SA_DQ 59 AG53 DDR3 10 SB_CK 0 DDR3 SA_DQ 60 AN55 DDR3 10 SB_CK 1 BB36 DDR3 SA_DQ 61 AN52 DDR3 10 SB_CK 0 BA34 DDR3 SA_DQ 62 AG55 DDR3 I O SB CK 1 BA36 DDR3 SA_DQ 63 AK56 DDR3 10 SB_CS 0 BE41 DDR3 SA_DQS 0 AL11 DDR3
124. States Active mode 1 Auto Auto halt low freq low voltage C3 L1 L2 caches flush clocks off C6 save core states before shutdown C7 similar to C6 L3 flush Note Power states availability may vary between the different SKUs Datasheet Volume 1 43 4 1 1 Table 4 1 4 1 2 Table 4 2 4 1 3 Table 4 3 44 Power Management Advanced Configuration and Power Interface ACPI States Supported The ACPI states supported by the processor are described in this section System States System States State Description FulOn G1 S3 Cold Suspend to RAM STR Context saved to memory S3 Hot is not supported by the processor G1 S4 Suspend to Disk STD All power lost except wakeup on PCH G2 S5 Soft off All power lost except wakeup on PCH Total reboot G3 Mechanical off All power AC and battery removed from system Processor Core Package Idle States Processor Core Package State Support State Description Active mode processor executing code Ci AutoHALT state C1E AutoHALT state with lowest frequency and voltage operating point c3 Execution cores in C3 flush their L1 instruction cache L1 data cache and L2 cache to the L3 shared cache Clocks are shut off to each core C6 Execution cores in this state save their architectural state before removing core voltage C7
125. U Additional Post Processing Multi Format Decode Encode Full MPEG2 VC1 AVC Decode Fixed Function Post Processing Full AVC Encode Partial MPEG2 VC1 Encode Datasheet Volume 1 29 2 4 1 1 2 4 1 2 2 4 1 2 1 2 4 1 2 2 2 4 1 2 3 2 4 1 2 4 2 4 1 2 5 30 Interfaces 3D and Video Engines for Graphics Processing The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive All the cores are fully programmable increasing the versatility of the 3D Engine The Gen 6 0 3D engine provides the following performance and power management enhancements e Up to 12 Execution units EUs e Hierarchal Z e Video quality enhancements 3D Engine Execution Units e Supports up to 12 EUs The EUs perform 128 bit wide execution per clock e Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel processing 3D Pipeline Vertex Fetch VF Stage The VF stage executes 3DPRIMITIVE commands Some enhancements have been included to better support legacy D3D APIs as well 85 SGI OpenGL Vertex Shader VS Stage The VS stage performs shading of vertices output by the VF function The VS unit produces an output vertex reference for every input vertex reference received from the VF unit in the order received Geometry Shader GS Stage The GS stage receives inputs from the VS stage Comp
126. VCC R34 PWR VCCIO E11 PWR VCC R35 PWR VCCIO E12 PWR VCC U26 PWR VCCIO Fil PWR VCC U27 PWR VCCIO F12 PWR VCC U28 PWR VCCIO G12 PWR VCC U29 PWR VCCIO 11 PWR VCC U30 PWR VCCIO H12 PWR VCC U31 PWR VCCIO 111 PWR VCC U32 PWR VCCIO 112 PWR VCC 033 PWR VCCIO L10 PWR VCC U34 PWR VCCIO P10 PWR VCC U35 PWR VCCIO U10 PWR VCC V26 PWR VCCIO Y10 PWR VCC V27 PWR VCCIO A13 PWR VCC V28 PWR VCCIO A14 PWR VCC v29 PWR VCCIO B14 PWR VCC V30 PWR VCCIO C13 PWR VCC V31 PWR VCCIO C14 PWR VCC V32 PWR VCCIO D13 PWR VCC V33 PWR VCCIO D14 PWR VCC V34 PWR VCCIO E14 PWR Datasheet Volume 1 Processor Pin and Signal Information intel Table 8 1 rPGA988B Processor Pin Table 8 1 rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VCCIO F13 PWR VSS A35 GND VCCIO F14 PWR VSS AB26 GND VCCIO G13 PWR VSS AB27 GND VCCIO G14 PWR VSS AB28 GND VCCIO H14 PWR VSS AB29 GND VCCIO 113 PWR VSS AB30 GND VCCIO J14 PWR vss AB31 GND VCCIO_SEL A19 N A 0 VSS AB32 GND VCCIO_SENSE B10 Analog VSS AB33 GND VCCPLL A2 PWR VSS AB34 GND VCCPLL A6 PWR VSS AB35 GND VCCPLL B6 PWR VSS AC2 GND VCCSA H25 PWR VSS AC3 GND VCCSA H26 PWR VSS AC5 GND VCCSA J24 PWR VSS AC6 GND VCCSA J25 PWR VSS AC8 GND VCCSA J26 PWR v
127. VSS VDDQ w SAM SA M A 3 7 12 A 6 A 1 Datasheet Volume 1 107 tel Processor Pin and Signal Information Figure 8 3 rPGA988B Socket G2 Pinmap Top View Lower Left Quadrant v U T R P N VSS VSS vss M V PEG T PEG T PEG T PEG T PEG T PEG x 1 1 2 2 x o xio A L vs xe 4 x4 K TON T PEG EE 6 1 _ PEG T PEG 2 17 42 4 84 41 iz 7 X 7 8 X 8 EM C vccs PEG T PEG TAM vecs vccs gt b _ PEG _ E 55 X 11 vss PE FDI1 PEG_T PEG T I S bs PROC vss vss 55 55 AT xl i Rove vss 108 Datasheet Volume 1 Processor Pin and Signal Information ntel Figure 8 4 rPGA988B Socket G2 Pinmap Top View Lower Right Quadrant SA C SA C De sa_Bs SAM SAM y KE 1 Buen 2 14 11 5 8 MO VSS VDDQ vss vss VDDQ vss vss VDDQ SB M SB M SB M SB M T A 1 A 8 A 6 A 4 SB C 98 c SB BS SB M M SB M SB M SB M R pes 2 15 A 9 11 vss VSS VDDQ vss vss VDDQ vss vss VDDQ BE s
128. Volume 1 Thermal Management Table 5 1 Thermal Design Power TDP Specifications Segment State CPU Core Processor Graphics Thermal Design Units Notes Frequency Core frequency Power 2 5 GHz up to 650 MHz up to HEM 3 5 GHz 1300 MHz 55 Extreme Edition XE 650 MHz up to m LFM 800 MHz 1300 MHz 36 2 2 GHz up to 650 MHz up to HER 3 4 GHz 1300 MHz 25 Quad Core SV w 1 2 7 650 MHz up to LFM 800 MHz 1300 MHz 33 2 5 GHz up to 650 MHz up to HEM 3 4 GHz 1300 MHz Dual Core SV w 1 2 7 650 MHz up to LFM 800 MHz 1300 MHz 26 2 1 GHz up to 500 MHz up to HEN 3 2 GHz 1100 MHz 25 Low Voltage w 1 2 7 500 MHz up to LFM 800 MHz 1100 MHz 12 1 4 GHz up to 350 MHz up to 2 7 GHz 1000 MHz 17 Ultra Low Voltage 350 MHz up to Senor LFM 800 MHz 1000 MHz 10 Table 5 2 Junction Temperature Specification Segment Symbol Min Default Max Units Notes Extreme Edition Tj Junction temperature limit 0 100 ec 3 4 5 Quad Core SV Junction temperature limit 0 100 C 3 4 5 Dual Core SV Tj Junction temperature limit 0 100 C 3 4 5 16 Low Voltage Tj Junction temperature limit 0 100 3 4 5 ele Tj Junction temperature limit 0 100 C 3 4 5 Table 5 3 Package Turbo Parameters Sheet 1 of 2 Segment Symbol Package Turbo Parameter Min H W Max Units Notes Default Processor turbo long duration time Turbo Time window 10 11
129. XG N58 PWR VCC L44 PWR 131 intel Table 8 2 BGA1224 Processor Ball List by Ball Name Processor Pin and Signal Information List by Ball Name Table 8 2 BGA1224 Processor Ball Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VCC L40 PWR VCC F29 PWR VCC L38 PWR VCC F25 PWR VCC L34 PWR VCC E44 PWR VCC L32 PWR VCC E40 PWR VCC L28 PWR VCC E38 PWR VCC L26 PWR VCC E34 PWR VCC L22 PWR VCC E32 PWR VCC K45 PWR VCC E28 PWR VCC K43 PWR VCC E26 PWR VCC K41 PWR VCC D45 PWR VCC K37 PWR VCC D43 PWR VCC K35 PWR VCC D41 PWR VCC K31 PWR VCC D37 PWR VCC K29 PWR VCC D35 PWR VCC K25 PWR VCC D31 PWR VCC J44 PWR VCC D29 PWR VCC J40 PWR VCC C44 PWR VCC J38 PWR VCC C40 PWR VCC J34 PWR VCC C38 PWR VCC J32 PWR VCC C34 PWR VCC J28 PWR VCC C32 PWR VCC J26 PWR VCC C28 PWR VCC H45 PWR VCC C26 PWR VCC H43 PWR VCC B45 PWR VCC H41 PWR VCC B43 PWR VCC H37 PWR VCC B41 PWR VCC H35 PWR VCC B37 PWR VCC H31 PWR VCC B35 PWR VCC H29 PWR VCC B31 PWR VCC H25 PWR VCC B29 PWR VCC G44 PWR VCC A44 PWR VCC G40 PWR VCC A40 PWR VCC G38 PWR VCC A38 PWR VCC G34 PWR VCC A34 PWR VCC G32 PWR VCC A32 PWR VCC G28 PWR VCC A28 PWR VCC G26 PWR VCC A26 PWR VCC F45 PWR VCC_DIE_SENSE F47 Analog VCC F43 PWR VCC_SENSE B47 Analog VCC F41 PWR VCC_VAL_SENSE D47 Analog VCC F37 PWR VCCDQ AV23 PWR VCC F35 PWR VCCDQ
130. _TP AG2 SA_DQ 22 J2 DDR3 I O RSVD TP AH2 SA DQ 23 K2 DDR3 1 0 RSVD_TP T9 SA_DQ 24 M8 DDR3 1 0 RSVD_TP T10 SA_DQ 25 N10 DDR3 1 0 RSVD_TP AA2 SA_DQ 26 N8 DDR3 1 0 RSVD_TP 1 SA_DQ 27 N7 DDR3 1 0 RSVD_TP AB2 SA_DQ 28 M10 DDR3 1 0 RSVD_TP AAI SA DQ 29 M9 DDR3 1 0 RSVD_TP AD6 SA_DQ 30 N9 DDR3 1 0 RSVD_TP AE6 SA DQ 31 M7 DDR3 1 0 RSVD_TP AD5 SA DQ 32 AG6 DDR3 1 0 RSVD_TP AE5 SA DQ 33 AG5 DDR3 1 0 SA_BS 0 AE10 DDR3 SA_DQ 34 AK6 DDR3 I O SA BS 1 AF10 DDR3 SA DQ 35 AK5 DDR3 1 0 SA_BS 2 V6 DDR3 O SA_DQ 36 AH5 DDR3 I O SA_CAS DDR3 SA DQ 37 AH6 DDR3 1 0 SA_CK 0 6 DDR3 SA_DQ 38 AJ5 DDR3 1 0 SA_CK 1 AB5 DDR3 SA DQ 39 AJ6 DDR3 I O SA CK 0 AB6 DDR3 O SA_DQ 40 AJ8 DDR3 I O SA_CK 1 5 DDR3 SA_DQ 41 AK8 DDR3 1 0 SA_CKE 0 vg DDR3 O SA_DQ 42 AJ9 DDR3 1 0 112 Datasheet Volume 1 Processor Pin and Signal Information intel Table 8 1 rPGA988B Processor Pin Table 8 1 rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir SA DQ 43 AK9 DDR3 1 0 SA_MA 10 AD8 DDR3 SA_DQ 44 AH8 DDR3 10 SA_MA 11 V4 DDR3 SA_DQ 45 AH9 DDR3 1 0 SA_MA 12 W4 DDR3 SA_DQ 46 ALO DDR3 1 0 SA_MA 13 AF8 DDR3 SA_D
131. a_o sa_o 5 se_p P P seo seo N Q 25 Q 30 9 26 9 27 QS 3 9 29 9 25 9 26 9 27 SA_D SA D SA D 5 D sB D sBD 0128 9159 9 24 9131 9124 9128 QS 3 30 9131 ks VSS VSS 55 VSS VSS VSS VSS VSS 58_ 58_ 58 SA D SAD SAD Q 18 0119 9 22 9 23 Q 17 Q 16 Q 18 SB D SB_D sB_D sB_D SA_D SA_D Ed 540 Q 21 9117 01161 05121 01201 9 21 0119 vss S vsS VSS VSS VSS VSS VSS H eDP_T SA D sA lt D sA D sBD sBD sB D sB D SBD X 3 Q 10 9 11 9 14 9 15 9 12 9 8 QS 1 Q 15 Q 11 FDI1_ eDP_T eDP T 5 _0 SA_D SB_D SB_D BD sBD TX 3 X 1 X 3 0181 01121 9 9 01131 05111 9 13 Q 9 01141 Q 10 VSS VSS VSS VSS VSS E SB D SB DI T eDP A D 58 1 SAD SAD SA_D SA_D eDP_T eDP_T eDP_A p sB D sB 5 _ VCCI vss trig vss vss B SEN vss vss vss m vss VSS B EFDQ 1 EN E E VSS_S SM_R Boos SS zm o Bran vccr 9 Q 5 Q 1 17 16 15 14 13 12 11 10 6 5 4 3 2 Datasheet Volume 1 109 intel Processor Pin and Signal Information 110 Table 8 1 rPGA988B Processor Pin Table 8 1 rPGA988B Pro
132. able 4 7 G and C State Combinations Processor Global Sleep Package Processor State System Clocks Description G State S State C State GO 50 Full On On Full On GO 50 C1 C1E Auto Halt On Auto Halt GO 50 Deep Sleep On Deep Sleep GO 50 C6 C7 Deep Power down On Deep Power down G1 S3 Power off Off except RTC Suspend to RAM G1 S4 Power off Off except RTC Suspend to Disk G2 S5 Power off Off except RTC Soft Off G3 NA Power off Power off Hard off Datasheet Volume 1 45 intel Table 4 8 4 2 4 2 1 46 Power Management D S and C State Combination d Sleep S State Package C State Description DO 50 CO Full On Displaying DO SO C1 C1E Auto Halt Displaying D0 SO C3 Deep sleep Displaying DO S0 C6 C7 Deep Power Down Displaying D3 50 Not displaying D3 S3 N A Graphics Core is D3 S4 N A Not displaying suspend to disk Processor Core Power Management While executing code Enhanced Intel SpeedStep Technology optimizes the processor s frequency and core voltage based on workload Each frequency and voltage operating point is defined by ACPI as a P state When the processor is not executing code it is idle A low power idle state is defined by ACPI as a C state In general lower power C states have longer entry and exit latencies Enhanced Intel SpeedStep Technology The following are the key features of Enhanced Intel S
133. al bandwidth per pair of 500 MB s given the 8b 10b encoding used to transmit data across this interface Does not account for packet overhead and link maintenance Maximum theoretical bandwidth on interface of 2 GB s in each direction simultaneously for an aggregate of 4 GB s when DMI x4 Shares 100 MHz PCI Express reference clock 64 bit downstream address format but the processor never generates an address above 64 GB Bits 63 36 will always be zeros 64 bit upstream address format but the processor responds to upstream read transactions to addresses above 64 GB addresses where any of Bits 63 36 are nonzero with an Unsupported Request response Upstream write transactions to addresses above 64 GB will be dropped 15 Introduction Supports the following traffic types to or from the PCH DMI gt DRAM DMI gt processor core Virtual Legacy Wires VLWs Resetwarn or MSIs only Processor core gt DMI APIC and MSI interrupt messaging support Message Signaled Interrupt MSI and MSI X messages Downstream SMI SCI and SERR error indication Legacy support for ISA regime protocol PHOLD PHOLDA required for parallel port DMA floppy drive and LPC bus masters DC coupling no capacitors between the processor and the PCH Polarity inversion PCH end to end lane reversal across the link Supports Half Swing low power low voltage 1 2 4 Platform Environment Control Interface PECI The PECI is a one wire in
134. and Intel Intel 6 Series Chipset and Intel C200 Series Chipset Datasheet www intel com Assets PDF specu pdate 324693 pdf www intel com Assets PDF datas heet 324645 pdf Intel 6 Series Chipset and Intel C200 Series Chipset Thermal Mechanical Specifications and Design Guidelines www intel com Assets PDF desig nguide 324647 pdf Advanced Configuration and Power Interface Specification 3 0 http www acpi info PCI Local Bus Specification 3 0 Intel9 TXT Measured Launched Environment Developer s Guide http www pcisig com specifica tions http www intel com technology security Intel 64 Architecture x2APIC Specification PCI Express Base Specification 2 0 http www intel com products pr ocessor manuals http www pcisig com DDR3 SDRAM Specification http www jedec org DisplayPort Specification Intel 64 and IA 32 Architectures Software Developer s Manuals http www vesa org http www intel com products pr ocessor manuals index htm Volume 1 Basic Architecture 253665 Volume 2A Instruction Set Reference A M 253666 Volume 2B Instruction Set Reference N Z 253667 Volume 3A System Programming Guide 253668 Volume 3B System Programming Guide 253669 58 20 Datasheet Volume 1 Interfaces intel 2 Interfaces This chapter describes the interfaces supported by the processor 2 1 System Memory Interface 2 1 1 System Memory Tec
135. and the 99 intel Electrical Specifications Table 7 12 Control Sideband and TAP Signal Group DC Specifications Symbol Parameter Min Max Units Notes Input Low Voltage 0 3 2 Vin Input High Voltage 0 7 V 2 4 VoL Output Low Voltage 0 1 V 2 Vou Output High Voltage 0 9 V 2 4 Ron Buffer on Resistance 23 73 Q Ij Input Leakage Current 200 3 Notes PWNS signal quality specifications Table 7 13 PCI Express DC Specifications Unless otherwise noted all specifications in this table apply to all processor frequencies The referred to in these specifications refers to instantaneous Vccio For between 0 V and Measured when the driver is tristated and Voy may experience excursions above However input signal drivers must comply with the Symbol Parameter Min Typ Max Units Notes Differential Peak to Peak Tx Voltage V x DIFF p p Swing 0 4 0 5 0 6 V 3 Tx AC Peak Common Mode Output CM AC p Voltage Gen 1 Only 0 8 1 1 2 mV 1 2 6 DC Differential Tx Impedance Gen 1 Zisome p 80 120 Q 1 10 ZRX DC DC Common Mode Rx Impedance 40 60 Q 1 8 9 DC Differential Rx Impedance 1 ZRX DIFF DC Only p 80 120 1 Differential Rx Input Peak to Peak m VRX DIFFp p Voltage Gen 1 only 0 175 12 T Vex CM
136. and the second request is to an address on the opposite channel from the first that request can be sent before data from the first request has returned If two consecutive cache lines are requested both may be retrieved simultaneously since they are ensured to be on opposite channels Use Dual Channel Symmetric mode when both Channel A and Channel B DIMM connectors are populated in any order with the total amount of memory in each channel being the same When both channels are populated with the same memory capacity and the boundary between the dual channel zone and the single channel zone is the top of memory IMC operates completely in Dual Channel Symmetric mode The DRAM device technology and width may vary from one channel to the other Rules for Populating Memory Slots In all modes the frequency of system memory is the lowest frequency of all memory modules placed in the system as determined through the SPD registers on the memory modules The system memory controller supports only one DIMM connector per channel The usage of DIMM modules with different latencies is allowed For dual channel modes both channels must have an DIMM connector populated For single channel mode only a single channel can have a DIMM connector populated Datasheet Volume 1 23 intel Interfaces 2 1 5 1 2 1 5 2 2 1 5 3 2 1 6 2 1 7 2 1 8 24 Technology Enhancements of Intel Fast Memory Access Intel FMA The following sections
137. ard Two independent links one for each display pipe e Four unidirectional downstream differential transmitter pairs Scalable down to 3X 2X or 1X based on actual display bandwidth requirements Fixed frequency 2 7 GT s data rate Two sideband signals for Display synchronization FDI FSYNC and FDI LSYNC Frame and Line Synchronization e One Interrupt signal used for various interrupts from the PCH FDI INT signal shared by both Intel FDI Links e PCH supports end to end lane reversal across both links Common 100 MHz reference clock Power Management Support Processor Core e Full support of Advanced Configuration and Power Interface ACPI C states as implemented by the following processor C states CO Ci C1E C3 C6 C7 Enhanced Intel SpeedStep Technology System SO S3 S4 S5 Memory Controller Conditional self refresh Intel Rapid Memory Power Management Intel RMPM Dynamic power down PCI Express e LOs and L1 ASPM power management capability Direct Media Interface DMI e LOs and L1 ASPM power management capability Datasheet Volume 1 17 Introduction intel 1 3 6 Processor Graphics Controller Intel Rapid Memory Power Management Intel RMPM CxSR Intel Graphics Performance Modulation Technology Intel GPMT Intel Smart 2D Display Technology Intel S2DDT Graphics Render C State RC6 Intel Seamless Display Refresh Rate Switching with Embedde
138. atform cooling that are designed to less than thermal design guidance might experience thermal and performance issues since more applications will tend to run at the maximum power limit for significant periods of time Intel Turbo Boost Technology may not be available on all SKUs Intel Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster than its rated operating core and or render clock frequency when there is sufficient power headroom and the product is within specified temperature and current limits The Intel Turbo Boost Technology feature is designed to increase performance of both multi threaded and single threaded workloads The processor supports a Turbo mode where the processor can use the thermal capacity associated with package and run at power levels higher than TDP power for short durations This improves the system responsiveness for short bursty usage conditions The turbo feature needs to be properly enabled by BIOS for the processor to operate with maximum performance Since the turbo feature is configurable and dependent on many platform design limits outside of the processor control the maximum performance cannot be ensured Turbo Mode availability is independent of the number of active cores however the Turbo Mode frequency is dynamic and dependent on the instantaneous application power load the number of active cores user configurable settings operating environmen
139. ature status and sticky bit are latched in the PACKAGE_THERM_STATUS MSR 1Bih and also generates a thermal interrupt if Datasheet Volume 1 Thermal Management L 5 4 2 5 4 2 1 5 4 2 1 1 5 4 2 1 2 5 4 3 5 4 3 1 enabled For more details on the interrupt mechanism refer to the Inte 64 and IA 32 Architectures Software Developer s Manuals Processor Core Specific Thermal Features On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption using clock modulation This mechanism is referred to as On Demand mode and is distinct from Adaptive Thermal Monitor and bi directional PROCHOT The processor platforms must not rely on software usage of this mechanism to limit the processor temperature On Demand Mode can be done using processor MSR or chipset I O emulation On Demand Mode may be used in conjunction with the Adaptive Thermal Monitor However if the system software tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode If the I O based and MSR based On Demand modes are in conflict the duty cycle selected by the I O emulation based On Demand mode will take precedence over the MSR based On Demand Mode MSR Based On Demand Mode If Bit 4 of the IA32 CLOCK MODULATION MSR is set to a 1 the processor will immediately
140. be on the panel front The sensor receives the changing ambient light conditions and sends the interrupts to the Intel Graphics driver As per the change in Lux current ambient light illuminance the new backlight setting can be adjusted through BLC see section 11 The converse applies for a brightly lit environment Intel Automatic Display Brightness increases the back light setting Intel Seamless Display Refresh Rate Switching Technology Intel SDRRS Technology This is a mobile only supported power management feature When a Local Flat Panel LFP supports multiple refresh rates the Intel Display Refresh Rate Switching power conservation feature can be enabled The higher refresh rate will be used when on plugged in power or when the end user has not selected enabled this feature The graphics software will automatically switch to a lower refresh rate for maximum battery life when the notebook is on battery power and when the user has selected enabled this feature There are two distinct implementations of Intel DRRS static and seamless The static Intel Display Refresh Rate Switching Technology Intel DRRS Technology method uses a mode change to assign the new refresh rate The seamless Intel Seamless Display Refresh Rate Switching Technology Intel SDRRS Technology method is able to accomplish the refresh rate assignment without a mode change and therefore does not experience some of the visual artifacts associated w
141. cessor Pin List by Pin Name List by Pin Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir BCLK A28 Diff Clk I DMI TX 3 C21 DMI BCLK A27 Diff Clk I DPLL_REF_CLK A16 Diff Clk I BCLK ITP AN35 Diff Clk I DPLL REF CLK A15 Diff Clk I BCLK_ITP AM35 Diff Clk I eDP_AUX C15 eDP I O BPM 0 AT28 Asynch CMOS 1 0 eDP_AUX D15 eDP I O BPM 1 AR29 Asynch CMOS 1 0 eDP_COMPIO A18 Analog I BPM 2 AR30 Asynch CMOS 1 0 eDP_HPD 816 Asynch CMOS I BPM 3 AT30 Asynch CMOS eDP_ICOMPO A17 Analog I BPM 4 AP32 Asynch CMOS 1 0 eDP_TX 0 C18 eDP 5 AR31 Asynch 5 1 0 eDP_TX 1 E16 eDP 4 6 1 Asynch CMOS 1 0 eDP_TX 2 D16 eDP 7 AR32 Asynch CMOS 1 0 eDP_TX 3 15 eDP CATERR AL33 Asynch CMOS eDP TX 0 C17 eDP CFG 0 AK28 CMOS I eDP TX 1 F16 eDP CFG 1 AK29 CMOS I eDP_TX 2 C16 eDP CFG 2 AL26 CMOS I eDP_TX 3 615 eDP CFG 3 AL27 CMOS I FDI_INT H20 Asynch CMOS I CFG 4 AK26 CMOS I FDIO FSYNC J18 CMOS I CFG 5 AL29 CMOS I FDIO LSYNC J19 CMOS I CFG 6 AL30 CMOS I FDIO_TX 0 A21 FDI CFG 7 AM31 CMOS I FDIO_TX 1 H19 FDI CFG 8 AM32 CMOS I FDIO_TX 2 E19 FDI CFG 9 AM30 CMOS I FDIO_TX 3 F18 FDI CFG 10 AM28 CMOS I FDIO_TX 0 A22 FDI 11 26 5 1 FDIO_TX 1 G19 FDI CFG 12 AN28 CMOS I FDIO_TX 2 E20 FDI 13 1 5 1 FDIO_TX 3 G18 FDI 14 26 CMOS I FDI1_FSYNC J17 CMOS I CFG 15 AM2
142. cessor has one PCI Express controller that can support one external x16 PCI Express Graphics Device The primary PCI Express Graphics port is referred to as PEG 0 PCI Express Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged The PCI Express configuration uses standard mechanisms as defined in the PCI Plug and Play specification The initial recovered clock speed of 1 25 GHz results in 2 5 Gb s direction that provides a 250 MB s communications channel in each direction 500 MB s total That is close to twice the data rate of classic PCI The fact that 8b 10b encoding is used accounts for the 250 MB s where quick calculations would imply 300 MB s The external graphics ports support Gen2 speed as well At 5 0 GT s Gen 2 operation results in twice as much bandwidth per lane as compared to Gen 1 operation When operating with two PCIe controllers each controller can be operating at either 2 5 GT s or 5 0 GT s The PCI Express architecture is specified in three layers Transaction Layer Data Link Layer and Physical Layer The partitioning in the component is not necessarily along these same boundaries Refer to Figure 2 2 for the PCI Express Layering Diagram Figure 2 2 PCI Express Layering Diagram Transaction Transaction Data Link Data Link Physical Physical Logical Sub block Logical Sub block Electrical Sub block Electrical Sub bloc
143. cution cores A 32 KB instruction and 32 KB data first level cache L1 for each core A 256 KB shared instruction data second level cache L2 for each core Up to 8 MB shared instruction data third level cache L3 shared among all cores 1 1 1 Supported Technologies Intel virtualization Technology Intel VT for Directed I O Intel VT d Intel virtualization Technology Intel VT for IA 32 Intel 64 and Intel Architecture Intel VT x Intel Active Management Technology 7 0 Intel AMT 7 0 Intel Trusted Execution Technology Intel TXT Intel Streaming SIMD Extensions 4 1 Intel SSE4 1 Intel Streaming SIMD Extensions 4 2 Intel SSE4 2 Intel Hyper Threading Technology Intel HT Technology Intel 64 Architecture Execute Disable Bit Intel Turbo Boost Technology Intel Advanced Vector Extensions Intel AVX Intel Advanced Encryption Standard New Instructions Intel AES NI PCLMULQDQ Instruction 1 2 Interfaces 1 2 1 System Memory Support Datasheet Volume 1 Two channels of DDR3 memory with a maximum of one SO DIMM per channel Single channel and dual channel memory organization modes Data burst length of eight for all memory organization modes Memory DDR3 data transfer rates of 1066 MT s 1333 MT s and 1600 MT s 64 bit wide channels DDR3 I O Voltage of 1 5 V Non ECC unbuffered DDR3 SO DIMMs only Theoretical maximum memory bandwidth of 17 1 GB s in dual channel mode assuming DDR3
144. d DisplayPort 1 4 Thermal Management Support Digital Thermal Sensor Intel Adaptive Thermal Monitor e THERMTRIP and PROCHOT support On Demand Mode Open and Closed Loop Throttling 1 5 1 6 Table 1 2 18 Memory Thermal Throttling e External Thermal Sensor TS on DIMM and TS on Board e Render Thermal Throttling e Fan speed control with DTS Package e The processor is available on two packages 37 5 x 37 5 mm rPGA package rPGA988B A 31 x 24 mm BGA package BGA1023 or BGA1224 Terminology Terminology Sheet 1 of 3 Term ACPI Description Advanced Configuration and Power Interface BLT Block Level Transfer CRT Cathode Ray Tube DDR3 Third generation Double Data Rate SDRAM memory technology DMA Direct Memory Access DMI DP Direct Media Interface DisplayPort DTS Digital Thermal Sensor eDP Embedded DisplayPort Enhanced Intel SpeedStep Technology EU Technology that provides power management capabilities to laptops Execution Unit Datasheet Volume 1 Introduction Table 1 2 intel Terminology Sheet 2 of 3 Term Description Execute Disable Bit IMC The Execute Disable bit allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operat
145. d the Physical Layer Responsibilities of Data Link Layer include link management error detection and error correction The transmission side of the Data Link Layer accepts TLPs assembled by the Transaction Layer calculates and applies data protection code and TLP sequence number and submits them to Physical Layer for transmission across the Link The receiving Data Link Layer is responsible for checking the integrity of received TLPs and for submitting them to the Transaction Layer for further processing On detection of TLP error s this layer is responsible for requesting retransmission of TLPs until information is correctly received or the Link is determined to have failed The Data Link Layer also generates and consumes packets that are used for Link management functions Physical Layer The Physical Layer includes all circuitry for interface operation including driver and input buffers parallel to serial and serial to parallel conversion PLL s and impedance matching circuitry It also includes logical functions related to interface initialization and maintenance The Physical Layer exchanges data with the Data Link Layer in an implementation specific format and is responsible for converting this to an appropriate serialized format and transmitting it across the PCI Express Link at a frequency and width compatible with the remote device Datasheet Volume 1 Interfaces intel 2 2 2 PCI Express Configuration Mechanism The PCI
146. data structures like IDT interrupt descriptor table GDT global descriptor table LDT local descriptor table and TSS task segment selector A VMM using this feature can intercept by a VM exit attempts to relocate these data structures and prevent them from being tampered by malicious software 3 1 3 Intel virtualization Technology Intel VT for Directed I O Intel VT d Objectives The key Intel VT d objectives are domain based isolation and hardware based virtualization A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated Virtualization allows for the creation of one or more partitions on a single system This could be multiple partitions in the same operating system or there can be multiple operating system instances running on the same system offering benefits such as system consolidation legacy migration activity partitioning or security 36 Datasheet Volume 1 Technologies 3 1 4 Intel Virtualization Technology Intel VT for Directed I O Intel VT d Features The processor supports the following Intel VT d features Memory controller and Processor Graphics comply with Intel VT d 1 2 specification Two VT d DMA remap engines iGraphics DMA remap engine DMI PEG Support for root entry context entry and default context 39 bit guest physical address and host physical address widths Support for 4K page sizes onl
147. e ACPI States Supported 44 4 1 1 payaa a 44 4 1 2 Processor Core Package Idle 44 4 1 3 Integrated Memory Controller States nenna 44 4 1 4 PCIExpress Link States aan biker ker En err sensi a ew Renee dmt LARA FR ER RE e 45 4 1 5 Direct Media Interface DMI States 45 4 1 6 Processor Graphics Controller States 0 nenna 45 4 1 7 Interface State CombiNations 00 45 4 2 Processor Core Power 1 46 4 2 1 Enhanced Intel SpeedStep Technology 1 1 46 4 2 2 Low Power Idle States iieri een aeta a dens 47 4 2 3 Requesting Low Power Idle States 48 4 2 4 ne meae lawataq ass aaa asnaq 49 4 2 4 1 Core CO State wana a E tebe anes 49 4 2 4 2 Core State um tusa isa deeded umasa a a 49 4 2 4 3 State a MERE AFER sk 49 Datasheet Volume 1 42 44 COKE 49 4 2 4 5 Core C7 State 49 4 2 4 6 C State uuu uu i a sawa saa 50 4 2 5
148. e L3 cache is reduced by N ways until it is completely flushed The number of ways N is dynamically chosen per concurrent C7 entry Similarly upon exit the L3 cache is gradually expanded based on internal heuristics Integrated Memory Controller IMC Power Management The main memory is power managed during normal operation and in low power ACPI Cx states Disabling Unused System Memory Outputs Any system memory SM interface signal that goes to a memory module connector in which it is not connected to any actual memory devices such as SO DIMM connector is unpopulated or is single sided is tri stated The benefits of disabling unused SM signals are Reduced power consumption e Reduced possible overshoot undershoot signal quality issues seen by the processor I O buffer receivers caused by reflections from potentially un terminated transmission lines When a given rank is not populated the corresponding chip select and CKE signals are not driven At reset all rows must be assumed to be populated until it can be proven that they are not populated This is due to the fact that when CKE is tristated with an SO DIMM present the SO DIMM is not ensured to maintain data integrity SCKE tri state should be enabled by BIOS where appropriate since at reset all rows must be assumed to be populated Datasheet Volume 1 53 m Power Management intel 4 3 2 54 DRAM Power Management and Initialization The processor
149. eive any clocks Upon exposure to free air that is unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material TAC Thermal Averaging Constant TAP Test Access Point TDP Thermal Design Power VaxG Graphics core power supply Datasheet Volume 1 19 intel Table 1 2 Terminology Introduction Sheet 3 of 3 Term Description Vcc Processor core power supply Vccio High Frequency I O logic power supply VccPLL PLL power supply VCCSA System Agent memory controller DMI PCIe controllers and display engine power supply Vppq DDR3 power supply VLD Variable Length Decoding Vss Processor ground x1 Refers to a Link or Port with one Physical Lane x16 Refers to a Link or Port with sixteen Physical Lanes x4 Refers to a Link or Port with four Physical Lanes x8 Refers to a Link or Port with eight Physical Lanes 1 7 Related Documents Refer to Table 1 3 for additional information Table 1 3 Related Documents Document Document Number Location Celeron Processor Family Mobile Datasheet Volume 2 2nd Generation Intel Core Processor Family Mobile and Intel www intel com Assets PDF datas heet 324803 pdf Celeron9 Processor Family Mobile Specification Update 2nd Generation Intel Core Processor Family Mobile
150. election for VCCSA This pin must have a pull down resistor VCCSA_VID 1 to ground CMOS Sense Signals Direction Signal Name Description Buffer Type VCC SENSE and VSS SENSE provide an isolated low impedance VCC SENSE VSS SENSE connection to the processor core voltage and ground They can be Anal used to sense or measure voltage near the silicon VAXG_SENSE VAXG_SENSE and VSSAXG_SENSE provide an isolated low VSSAXG SENSE impedance connection to the voltage and ground They Anal be used to sense or measure voltage near the silicon na og CCIO VSS_SENSE_VCCIO They can be used to sense or measure voltage near the silicon Analog VDDQ_SENSE VDDQ_SENSE and VSS_SENSE_VDDQ provides an isolated low VSS SENSE VDD impedance connection to the voltage and ground They can Anal 9 be used sense measure voltage near the silicon 14 09 VCCSA_SENSE provide an isolated low impedance connection to VCCSA_SENSE the processor system agent voltage It can be used to sense or Anal measure voltage near the silicon 9 09 VCC_DIE_SENSE Die Validation Sense Analog VCC_VAL_SENSE Vcc Validation Sense VSS_VAL_SENSE Analog VAXG_VAL_SENSE Vaxg Validation Sense VSSAXG_VAL_SENSE Analog Ground and Non Critical to Function NCTF Signals Table 6 16 Ground and Non Critical to Function NCTF Signals Direction Signal Name Description
151. en supporting Multi Graphics controllers Multi Monitors drag and drop between monitors and the 2x8 PEG is not supported Platform Environment Control Interface PECI The PECI is a one wire interface that provides a communication channel between a PECI client processor and a PECI master The processor implements a PECI interface to Allow communication of processor thermal and other information to the master Read averaged Digital Thermal Sensor DTS values for fan speed control Interface Clocking Internal Clocking Requirements Reference Clock Reference Input Clock Input Frequency Associated PLL BCLK BCLK 100 MHz Processor Memory Graphics PCIe DMI FDI DPLL REF CLK DPLL REF CLK 120 MHz Embedded DisplayPort eDP Datasheet Volume 1 Technologies 3 3 1 3 1 1 intel Technologies This chapter provides a high level description of Intel technologies implemented in the processor The implementation of the features may vary between the processor SKUs Details on the different technologies of Intel processors and other relevant external notes are located at the Intel technology web site http www intel com technology Intel Virtualization Technology Intel VT Intel Virtualization Technology Intel VT makes a single system appear as multiple independent systems to software This allows multiple independent operating systems to run simultaneously on a single sy
152. er third parties are not authorized by Intel to use code names in advertising promotion or marketing of any product or services and any such use of Intel s internal code names is at the sole risk of the user Intel Intel Core Celeron Speedstep and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2012 Intel Corporation All rights reserved 2 Datasheet Volume 1 Contents 1 I UrOGuUI nR n 11 1 1 Processor Details uuu unan canes a RR E Yn 13 1 1 1 Supported Technologies sasssa 13 1 2 2 2 ettet eH a ja PRA ERR A RR 13 1 2 1 System Memory Suppoft uuu ecrire hse ki e i reni uo kc vena wax qaa 13 1 2 2 Leld idi 14 1 2 3 Direct Media Interface DMI u in ne hah Rana 15 1 2 4 Platform Environment Control Interface 16 1 2 5 Processor oh miis te n E o ri Ad has 16 1 2 6 Embedded DisplayPort 2 1 nnn 17 1 2 7 Intel Flexible Display Interface Intel FDI 17 1 3 Power Management SUDDOLFEt eese mas latratu ciens ten DRE Ru 17 1 3 1 IPFOCESSOR a 17
153. eration and is invisible to the OS SW However during debug swizzling needs to be taken into consideration thus swizzling data is presented in this chapter When placing DIMM logic analyzer the design engineer must pay attention to the swizzling table to perform an efficient memory debug Datasheet Volume 1 167 m e n tel DDR Data Swizzling Table 9 1 DDR Data Swizzling Table 9 1 DDR Data Swizzling Table Channel A Table Channel A Pin Name Number 1 Number umb ML rPGA BGA1023 BGA1224 rPGA BGA1023 BGA1224 SA DQ O C5 AG6 AL6 001 SA 42 AJ9 BB51 AW54 DQ44 SA 1 D5 AJ6 18 DQ02 SA DQ 43 AK9 AY53 AY55 DQ47 SA D3 AP11 AP7 DQ07 SA DQ 44 8 49 BD53 DQ41 SA DQ 3 D2 16 5 006 SA DQ 45 AH9 AU49 BB53 DQ40 SA DQ 4 D6 AJ10 AK7 DQ03 SA DQ 46 AL9 BA53 BE56 DQ46 SA DQ 5 C6 AJ8 AL10 DQ00 SA_DQ 47 AL8 BB55 BA56 DQ45 SA_DQ 6 C2 18 10 005 SA 48 11 55 BD57 DQ51 SA_DQ 7 C3 AL7 004 SA DQ 49 11 AV56 BF61 DQ50 SA 8 F10 AR11 AR10 DQ08 SA_DQ 50 AL12 AP50 BA60 DQ53 SA_DQ 9 F8 AP6 AR8 DQ10 SA_DQ 51 AM12 AP53 BB61 DQ52 SA_DQ 10 G10 AU6 AV7 DQ14 SA_DQ 52 AM11 AV54 BE60 DQ49 SA_DQ 11 G9 AV9 AY5 DQ15 SA_DQ 53 AL11 AT54 BD63 DQ48 SA DQ 12 F9 AR6 2909 SA DQ 54 AP12 AP56 BB59 DQ54 SA DQ 13 F7
154. ere netu E haqa 167 Datasheet Volume 1 Figures 1 1 Mobile Platform System Block Diagram Example 12 2 1 Intel Flex Memory Technology 23 2 2 PCI Express Layering Diagram recen ceri a cated eae Pd qaa aqa ER 25 2 3 Packet Flow through the Layers assa duy dias sewer iret us Essa as sr ERN nee 26 2 4 PCI Express Related Register Structures in the 27 2 5 PCI Express Typical Operation 16 lanes Mapping 28 2 6 Processor Graphics Controller Unit Block sss 29 2 7 Processor Display Block 4 4 44 4 444 4 1 eene emisse 32 L2 NB ks _ ______ 43 4 2 Idle Power Management Breakdown of the Processor 47 4 3 Thread and Core C State Entry and uu u u aa awas aaa 47 4 4 Package C State Entry and EXIE t RA TERR 51 5 1 Package Power uu saa RA 63 5 2 Frequency and Voltage Ordering ceeds ax aa ER RR ARR 69 7 1 Example for Host clients Connection emen nene 102 7 25 Inpu
155. erformance scalability The eDP interface supports link speeds of 1 62 Gbps and 2 7 Gbps on 1 2 or 4 data lanes The eDP supports 0 5 SSC and non SSC clock settings Intel Flexible Display Interface Intel FDI The Intel Flexible Display Interface Intel FDI is a proprietary link for carrying display traffic from the Processor Graphics controller to the PCH display I Os Intel FDI supports two independent channels one for pipe A and one for pipe B Each channel has four transmit Tx differential pairs used for transporting pixel and framing data from the display engine Each channel has one single ended LineSync and one FrameSync input 1 V CMOS signaling One display interrupt line input 1 V CMOS signaling Intel FDI may dynamically scalable down to 2X or 1X based on actual display bandwidth requirements Common 100 MHz reference clock Each channel transports at a rate of 2 7 Gbps e PCH supports end to end lane reversal across both channels no reversal support required in the processor Datasheet Volume 1 33 intel Interfaces Note 2 5 2 6 2 6 1 Table 2 3 34 Multi Graphics Controller Multi Monitor Support The processor supports simultaneous use of the Processor Graphics Controller GT and a x16 PCI Express Graphics PEG device The processor supports a maximum of 2 displays connected to the PEG card in parallel with up to 2 displays connected to the processor and PCH Wh
156. ermal performance At the Tray temperature Intel recommends full cooling capability well before the DTS reading reaches T max An example of this would be TFAN Tj max 10 C SS Datasheet Volume 1 Signal Description 6 Signal Description This chapter describes the processor signals They are arranged in functional groups according to their associated interface or category The following notations are used to describe the signal type Notations Signal Type I Input Pin Output Pin 1 0 Bi directional Input Output Pin The signal description also includes the type of buffer used for the particular signal see Table 6 1 Table 6 1 Signal Description Buffer Types Signal Description PCI Express interface signals These signals are compatible with PCI Express 2 0 PCI Express Signalling Environment AC Specifications and are AC coupled The buffers are not 3 3 V tolerant Refer to the PCIe specification Embedded Display Port interface signals These signals are compatible with VESA eDP Revision 1 0 DP specifications and the interface is AC coupled The buffers are not 3 3 V tolerant Intel Flexible Display interface signals These signals are based on PCI Express 2 0 FDI Signaling Environment AC Specifications 2 7 GT s but are DC coupled The buffers are not 3 3 V tolerant Direct Media Interface signals These signals are based on PCI Express 2 0 Signaling DMI Environment
157. et Volume 1 Technologies intel 3 6 1 PCLMULQDQ Instruction The processor supports the carry less multiplication instruction PCLMULQDQ PCLMULQDOQ is a Single Instruction Multiple Data SIMD instruction that computes the 128 bit carry less multiplication of two 64 bit operands without generating and propagating carries Carry less multiplication is an essential processing component of several cryptographic systems and standards Hence accelerating carry less multiplication can significantly contribute to achieving high speed secure computing and communication 3 7 Intel 64 Architecture x2APIC The x2APIC architecture extends the xAPIC architecture that provides a key mechanism for interrupt delivery This extension is intended primarily to increase processor addressability Specifically 2 e Retains all key elements of compatibility to the xAPIC architecture delivery modes interrupt and processor priorities interrupt sources interrupt destination types Provides extensions to scale processor addressability for both the logical and physical destination modes e Adds new features to enhance performance of interrupt delivery Reduces complexity of logical destination mode interrupt delivery on link based architectures The key enhancements provided by the x2APIC architecture over xAPIC are the following e Support for two modes of operation to provide backward compatibility and extensibility for
158. et of pixels The Windower is also capable of performing dithering whereby the illusion of a higher resolution when using low bpp channels in color buffers is possible Color dithering diffuses the sharp color bands seen on smooth shaded objects Video Engine The Video Engine handles the non 3D media video applications It includes support for VLD and MPEG2 decode in hardware 2D Engine The 2D Engine contains BLT Block Level Transfer functionality and an extensive set of 2D instructions To take advantage of the 3D during engine s functionality some BLT functions make use of the 3D renderer Processor Graphics VGA Registers The 2D registers consists of original VGA registers and others to support graphics modes that have color depths resolutions and hardware acceleration features that go beyond the original VGA standard Logical 128 Bit Fixed BLT and 256 Fill Engine This BLT engine accelerates the GUI of Microsoft Windows operating systems The 128 bit BLT engine provides hardware acceleration of block transfers of pixel data for many common Windows operations The BLT engine can be used for the following Move rectangular blocks of data between memory locations Data alignment To perform logical operations raster ops The rectangular block of data does not change as it is transferred between memory locations The allowable memory transfers are between cacheable system memory and frame buffer memory frame buffe
159. eter to maintain time averaged power at or below POWER LIMIT 1 The default value is 1 second however 28 seconds is recommended for most mobile applications e POWER LIMIT 2 TURBO POWER LIMIT MSR 610h bits 46 32 This value establishes the upper power limit of turbo operation above TDP primarily for platform power supply considerations Power may exceed this limit for up to 10 mS The default for this limit is 1 25 x TDP The following considerations and limitations apply to the power monitoring feature e Calibration applies to the processor family and is not conducted on a part by part basis Therefore some difference between actual and reported power may be observed Power monitoring is calibrated with a variety of common realistic workloads near Tj max Workloads with power characteristic markedly different from those used during the calibration process or lower temperatures may result in increased differences between actual and estimated power e In the event an uncharacterized workload or power virus application were to result in exceeding programmed power limits the processor Thermal Control Circuitry TCC will protect the processor when properly enabled Adaptive Thermal Monitor must be enabled for the processor to remain within specification Illustration of Intel Turbo Boost Technology power control is shown in the following sections and figures Multiple controls operate simultaneously allowing for customization for
160. ftware drivers or interrupt handling routines The Adaptive Thermal Monitor is not intended as a mechanism to maintain processor TDP The system design should provide a thermal solution that can maintain TDP within its intended usage range Frequency Voltage Control Upon TCC activation the processor core attempts to dynamically reduce processor core power by lowering the frequency and voltage operating point The operating points are automatically calculated by the processor core itself and do not require the BIOS to program them as with previous generations of Intel processors The processor core will scale the operating points such that e The voltage will be optimized according to the temperature the core bus ratio and number of cores in deep C states e The core power and temperature are reduced while minimizing performance degradation A small amount of hysteresis has been included to prevent an excessive amount of operating point transitions when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature the operating frequency and voltage will transition back to the normal system operating point This is illustrated in Figure 5 2 Datasheet Volume 1 Thermal Management L Figure 5 2 Frequency and Voltage Ordering Temperature Frequency PROCHOT Time Once a target frequency b
161. have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order All products platforms dates and figures specified are preliminary based on current expectations and are subject to change without notice All dates specified are target dates are provided for planning purposes only and are subject to change This document contains information on products in the design phase of development Do not finalize a design with this information Revised information will be published when the product is available Verify with your local sales office that you have the latest datasheet before finalizing a design Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality Enhanced Intel SpeedStep Technology See the Processor Spec Finder or contact your Intel representative for more informa
162. hen the TCC is active continuously in extreme situations Low Power States and PROCHOT Behavior If the processor enters a low power package idle state such as C3 or C6 C7 with PROCHOT asserted PROCHOT will remain asserted until The processor exits the low power state e The processor junction temperature drops below the thermal trip point For the package C7 state PROCHOT may de assert for the duration of C7 state residency even if the processor enters the idle state operating at the TCC activation temperature The PECI interface is fully operational during all C states and it is expected that the platform continues to manage processor package core thermals even during idle states by regularly polling for thermal data over PECI THERMTRIP Signal Regardless of enabling the automatic or on demand modes in the event of a catastrophic cooling failure the package will automatically shut down when the silicon has reached an elevated temperature that risks physical damage to the product At this point the THERMTRIP signal will go active Critical Temperature Detection Critical Temperature detection is performed by monitoring the package temperature This feature is intended for graceful shutdown before the THERMTRIP is activated however the processor execution is not ensured between critical temperature and THERMTRIP If the package s Adaptive Thermal Monitor is triggered and the temperature remains high a critical temper
163. hnology Supported The Integrated Memory Controller IMC supports DDR3 protocols with two independent 64 bit wide channels each accessing one DIMM It supports a maximum of one unbuffered non ECC DDR3 DIMM per channel thus allowing up to two device ranks per channel DDR3 Data Transfer Rates 1066 MT s PC3 8500 1333 MT s PC3 10600 1600 MT s PC 12800 DDR3 SO DIMM Modules Raw Card A Dual Ranked x16 unbuffered non ECC Raw Card B Single Ranked x8 unbuffered non ECC Raw Card C Single Ranked x16 unbuffered non ECC Raw Card F Dual Ranked x8 planar unbuffered non ECC e DDR3 DRAM Device Technology Standard 1 Gb 2 Gb and 4 Gb technologies and addressing are supported for x16 and x8 devices There is no support for memory modules with different technologies or capacities on opposite sides of the same memory module If one side of a memory module is populated the other side is either identical or empty Table 2 1 Supported SO DIMM Module 5 2 of Card comet ii e ORAM mow Co inside page size Version Devices Ranks Address Bits DRAM 1 GB 1 Gb 64Mx 16 6 2 GB 2 Gb 128Mx 16 1 1 Gb 128 8 E 2 GB 2 Gb 256Mx8 512 MB 1Gb 64 16 1 2 Gb 128 16 2 GB 1 Gb 128Mx8 F 4 GB 2 Gb 256Mx8 8 GB 4 Gb 512Mx8 Notes 1 System memory configurations are based on availability and are subject to change
164. i 8 5 i 5 5 amp h 1 T po E 2 lo li Z E gt m Ec 8 A aan z 2 FUR g a Datasheet Volume 1 155 Processor Pin and Signal Information intel Figure 8 14 Processor rPGA988B 2C GT2 Mechanical Package Sheet 2 of 2 222128 1 5 eon vs 04 TED MI IK IRE runi m AJIA MOLIDB 1HBI3H INIMOMDI JIBMMOTN H 31 2 1 Datasheet Volume 1 156 Processor Pin and Signal Information d pe le l 60000000600000000 KEYING DE V SYMB wer 2 THE PACKAGE MECHANICAL DRAWING THE THE Tae
165. ications L Table 7 14 Embedded DisplayPort DC Specifications 7 10 7 10 1 Symbol Parameter Min Typ Max Units Notes eDP_HPD Vit Input Low Voltage 0 1 0 3 V Vin Input High Voltage 0 7 Vccio V eDP AUX eDP_AUX V Tx AUX Peak to Peak Voltage at the 0 4 0 6 1 AUX DIFFp p transmitting device V Rx AUX Peak to Peak Voltage at the 0 32 1 36 V 1 AUX DIFFp p receiving device eDP COMPs eDP ICOMPI Comp Resistance 24 75 25 25 25 eDP_COMPIO Comp Resistance 24 75 25 25 25 Q 2 3 Notes 1 VAUX DIFFp p 2 VAUXP VAUXM Refer to the VESA DisplayPort Standard specification for more details 2 COMP resistance must be provided on the system board with 1 resistors COMP resistors are to 3 eDP_ICOMPO eDP_ICOMPI eDP_RCOMPO the same resistor Platform Environmental Control Interface PECI DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external Adaptive Thermal Monitor devices The processor contains a Digital Thermal Sensor DTS that reports a relative die temperature as an offset from Thermal Control Circuit TCC activation temperature Temperature sensors located throughout the die are implemented as analog to digital converters calibrated at the factory PECI provides an interface for external devices to read the DTS temperature
166. iffers from the VID employed by the processor during a power or thermal management event Intel Adaptive Thermal Monitor Enhanced Intel SpeedStep Technology or Low Power States 3 The voltage specification requirements are measured across VCC SENSE and VSS SENSE lands at the Socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe Processor core VR to be designed to electrically support this current Processor core VR to be designed to thermally support this current indefinitely This specification assumes that Intel Turbo Boost Technology is enabled Long term reliability cannot be assured if tolerance ripple and core noise parameters are violated Long term reliability cannot be assured in conditions above or below Max Min functional limits PSx refers to the voltage regulator power state as set by the SVID protocol 0 Idle power specification is measured under temperature condition of 35 C Table 7 6 Processor Uncore Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note Voltage for the memory controller V and shared cache defined at the _ 1 05 _ V CCIO motherboard SENSE and Vss_SENSE_VCCIO TOL Tolerance defined across DC 2
167. igned to optimize the average power to the graphics render engine during times of idleness of the render engine Render C state is entered when the graphics render engine blitter engine and the video engine have no workload being currently worked on and no outstanding graphics memory transactions When the idleness condition is met the Integrated Graphics will program the VR into a low voltage state 0 4 V through the SVID bus Render C State RC6 is a technique designed to optimize the average power to the graphics render engine during times of idleness of the render engine Render C state is entered when the graphics render engine blitter engine and the video engine have no workload being currently worked on and no outstanding graphics memory transactions When the idleness condition is met the Processor Graphics will program the VR into a low voltage state 0 0 4 V through the SVID bus Datasheet Volume 1 57 m Power Management intel 4 6 5 4 6 6 58 Intel Smart 2D Display Technology Intel S2DDT Intel S2DDT reduces display refresh memory traffic by reducing memory reads required for display refresh Power consumption is reduced by less accesses to the IMC S2DDT is only enabled in single pipe mode Intel S2DDT is most effective with Display images well suited to compression such as text windows slide shows and so on Poor examples are 3D games e Static screens such as screens with significant portions
168. ignificant may be a few watts according to the DDR specification This is significant when each channel is populated with more ranks Datasheet Volume 1 Power Management intel Note 4 3 2 1 4 3 2 2 Selection of power modes should be according to power performance or thermal trade offs of a given system When trying to achieve maximum performance and power or thermal consideration is not an issue use no power down e In a system that tries to minimize power consumption try to use the deepest power down mode possible DLL off or APD DLLoff e In high performance systems with dense packaging that is complex thermal design the power down mode should be considered in order to reduce the heating and avoid DDR throttling caused by the heating Control of the power mode through CRB BIOS The BIOS selects by default no power down There are knobs to change the power down selected mode Another control is the idle timer expiration count This is set through PM PDWN config bits 7 0 MCHBAR 4 As this timer is set to a shorter time the MC will have more opportunities to put DDR in power down The minimum recommended value for this register is 15 There is no BIOS hook to set this register Customers who choose to change the value of this register can do it by changing the BIOS For experiments this register can be modified in real time if BIOS did not lock the MC registers In APD APD PPD and APD DLLoff there i
169. iled application provided GS programs specifying an algorithm to convert the vertices of an input object into some output primitives For example a GS shader may convert lines of a line strip into polygons representing a corresponding segment of a blade of grass centered on the line Or it could use adjacency information to detect silhouette edges of triangles and output polygons extruding out from the edges Clip Stage The Clip stage performs general processing on incoming 3D objects However it also includes specialized logic to perform a Clip Test function on incoming objects The Clip Test optimizes generalized 3D Clipping The Clip unit examines the position of incoming vertices and accepts rejects 3D objects based on its Clip algorithm Strips and Fans SF Stage The SF stage performs setup operations required to rasterize 3D objects The outputs from the SF stage to the Windower stage contain implementation specific information required for the rasterization of objects and also supports clipping of primitives to some extent Datasheet Volume 1 Interfaces 2 4 1 2 6 2 4 1 3 2 4 1 4 2 4 1 4 1 2 4 1 4 2 intel The WIZ unit performs an early depth test which removes failing pixels and eliminates unnecessary processing overhead Windower IZ WIZ Stage The Windower uses the parameters provided by the SF unit in the object specific rasterization algorithms The WIZ unit rasterizes objects into the corresponding s
170. implements extensive support for power management on the SDRAM interface There are four SDRAM operations associated with the Clock Enable CKE signals that the SDRAM controller supports The processor drives four CKE pins to perform these operations The CKE is one of the power save means When CKE is off the internal DDR clock is disabled and the DDR power is reduced The power saving differs according the selected mode and the DDR type used For more information please refer to the IDD table in the DDR specification The DDR specification defines 3 levels of power down that differ in power saving and in wakeup time 1 Active power down APD This mode is entered if there are open pages when de asserting CKE In this mode the open pages are retained Power saving in this mode is the lowest Power consumption of DDR is defined by IDD3P Exiting this mode is fined by tXP small number of cycles 2 Precharged power down PPD This mode is entered if all banks in DDR are precharged when de asserting CKE Power saving in this mode is intermediate better than APD but less than DLL off Power consumption is defined by IDD2P1 Exiting this mode is defined by tXP Difference from APD mode is that when waking up all page buffers are empty 3 DLL off In this mode the data in DLLs on DDR are off Power saving in this mode is the best among all power modes Power consumption is defined by IDD2P1 Exiting this mode is defined by tXP but also tX
171. ing system This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system See the Intel 64 and IA 32 Architectures Software Developer s Manuals for more detailed information Integrated Memory Controller Intel 64 Technology 64 bit memory extensions to the IA 32 architecture Intel DPST Intel Display Power Saving Technology Intel FDI Intel Flexible Display Interface Intel TXT Intel Trusted Execution Technology Intel Virtualization Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple robust independent software environments Technology inside a single platform Intel Virtualization Technology Intel VT for Directed I O Intel VT d is a hardware assist under system software Virtual Machine Manager or OS Intel VT d control for enabling I O device virtualization Intel VT d also brings robust security by providing protection from errant DMAs by using DMA remapping a key feature of Intel VT d IOV I O Virtualization ITPM Integrated Trusted Platform Module LCD Liquid Crystal Display LVDS Low Voltage Differential Signaling A high speed low power data transmission standard used for display connections to LCD panels Non Critical to Function NCTF locations are typically redundant ground or non NCTF critical rese
172. intel Table 8 3 BGA1023 Processor Ball Table 8 3 BGA1023 Processor Ball List by Ball Name List by Ball Name Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir FDI0_TX 2 w3 FDI _ 15 K6 PCIe I FDI0_TX 3 AA7 FDI _ 0 G22 PCle FDI1_FSYNC AC12 CMOS I PEG TX 1 C23 PCIe FDI1_LSYNC AG8 CMOS I PEG_TX 2 D23 PCIe FDI1_TX 0 W6 FDI PEG_TX 3 F21 PCIe FDI1_TX 1 v4 FDI _ 4 H19 PCle FDI1_TX 2 Y2 FDI _ 5 17 PCIe FDI1_TX 3 AC9 FDI _ 6 15 PCIe FDI1_TX 0 W7 FDI _ 7 17 PCIe FDI1_TX 1 T4 FDI PEG_TX 8 F14 PCIe FDI1_TX 2 AA3 FDI _ 9 15 PCle FDI1_TX 3 AC8 FDI PEG_TX 10 114 PCle A48 Asynch 1 0 PEG_TX 11 H13 PCIe PEG_ICOMPI G3 Analog I PEG_TX 12 M10 PCIe _1 Gi Analog I PEG TX4 13 F10 PCIe _ G4 Analog I PEG_TX 14 D9 PCIe _ 0 H22 PCIe I PEG TX4 15 14 PCIe _ 1 121 1 _ 0 22 PCIe _ 2 B22 PCIe I PEG TX 1 A23 PCIe _ 3 D21 PCIe I PEG TX 2 D24 PCIe PEG_RX 4 A19 PCIe I PEG TX 3 E21 PCIe _ 5 D17 PCIe I PEG TX 4 G19 PCIe _ 6
173. intel 2nd Generation Intel Core Processor Family Mobile and Intel Celeron Processor Family Mobile Datasheet Volume 1 Supporting Intel Core i7 Mobile Extreme Edition Processor Series and Intel Core i5 and i7 Mobile Processor Series Supporting Intel Celeron Mobile Processor Series This is Volume 1 of 2 September 2012 Document Number 324692 006 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS OTHERWISE AGREED IN WRITING BY INTEL THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall
174. ir Pin Name Pin Buffer Type Dir VSS N30 GND VSS VAL SENSE AH33 Analog VSS N31 GND VSSAXG_SENSE AK34 Analog VSS N32 GND VSSAXG VAL SENSE AH31 Analog VSS N33 GND VSS N34 GND VSS N35 GND VSS P2 GND VSS P3 GND VSS P5 GND VSS P6 GND VSS P8 GND VSS P9 GND VSS T26 GND VSS T27 GND VSS T28 GND VSS T29 GND VSS T30 GND VSS T31 GND VSS T32 GND VSS T33 GND VSS T34 GND VSS T35 GND VSS U2 GND VSS U3 GND VSS U5 GND VSS U6 GND VSS 08 GND VSS U9 GND VSS W26 GND VSS W27 GND VSS W28 GND VSS 29 GND VSS w30 GND VSS w31 GND VSS w32 GND VSS w33 GND VSS W34 GND VSS W35 GND VSS Y2 GND VSS Y3 GND VSS Y5 GND VSS Y6 GND VSS Y8 GND VSS Y9 GND VSS SENSE AJ34 Analog VSS_SENSE_VCCIO A10 Analog Datasheet Volume 1 Processor Pin and Signal Information Figure 8 5 BGA1224 Ballmap Top View Upper Left Quadrant Datasheet Volume 1 121 Processor Pin and Signal Information Figure 8 6 BGA1224 Ballmap Top View Upper Right Quadrant 20 19 18 17 x 15 s e Ba zm 4
175. ith the mode change SetMode method Thermal Power Management See Section 4 6 for all graphics thermal power management related features 58 Datasheet Volume 1 59 60 Power Management Datasheet Volume 1 Thermal Management L 5 Caution 5 1 5 2 Thermal Management The thermal solution provides both the component level and the system level thermal management To allow for the optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed so that the processor e Remains below the maximum junction temperature T max specification at the maximum thermal design power TDP Conforms to system constraints such as system acoustics system skin temperatures and exhaust temperature requirements Thermal specifications given in this chapter are on the component and package level and apply specifically to the 2nd Generation Intel Core processor family mobile and Intel Celeron processor family mobile Operating the processor outside the specified limits may result in permanent damage to the processor and potentially other components in the system Thermal Design Power TDP and Junction Temperature Tj The processor TDP is the maximum sustained power that should be used for design of the processor thermal solution TDP represents an expected maximum sustained power from realistic applications TDP may be exceeded for short
176. k RX TX RX TX PCI Express uses packets to communicate information between components Packets are formed in the Transaction and Data Link Layers to carry the information from the transmitting component to the receiving component As the transmitted packets flow Datasheet Volume 1 25 intel Interfaces Figure 2 3 2 2 1 1 2 2 1 2 2 2 1 3 26 through the other layers they are extended with additional information necessary to handle packets at those layers At the receiving side the reverse process occurs and packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally for Transaction Layer Packets to the form that can be processed by the Transaction Layer of the receiving device Packet Flow through the Layers A E RA fae ew Lues L IL L Transaction Layer 3 Data Link Layer Physical Layer Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer The Transaction Layer s primary responsibility is the assembly and disassembly of Transaction Layer Packets TLPs TLPs are used to communicate transactions such as read and write as well as certain types of events The Transaction Layer also manages flow control of TLPs Data Link Layer The middle layer in the PCI Express stack the Data Link Layer serves as an intermediate stage between the Transaction Layer an
177. l Celeron processor family mobile may be referred to simply as processor Throughout this document the Intel Core i7 Extreme Edition mobile processor series refers to the Intel Core i7 2920XM processor Throughout this document the Intel Core i7 mobile processor series refers to the Intel Core i7 2960XM i7 2860QM i7 2820QM i7 2760QM i7 2720QM i7 2677M i7 2640M i7 2637M and i7 2620M processors Throughout this document the Intel Core i5 mobile processor series refers to the Intel Core i5 2557M i5 2540M and i5 2520M processors Throughout this document the Intel Celeron processor family mobile refers to the Intel Celeron B830 B800 B710 887 857 847 B840 and 787 processors Throughout this document the Intel 6 Series Chipset Platform Controller Hub may also be referred to as PCH Some processor features are not available on all platforms Refer to the processor specification update for details Datasheet Volume 1 11 Introduction Figure 1 1 Mobile Platform System Block Diagram Example 55 2 0 1x16 or 2x8 Processor Intel Flexible Display DMI2 x4 Interface m Serial ATA Management v Platform Controller Hub PCH SMBUS 2 0 Controller Link 1 8 PCI Express 2 0 x1 Ports 5 GT s GPIO 12 Datasheet Volume 1 Introduction intel 1 1 Processor Feature Details Four or two exe
178. l Adaptive Thermal Monitor Enhanced Intel SpeedStep Technology or Low Power States Datasheet Volume 1 Electrical Specifications Table 7 11 DDR3 Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes Vu Input Low Voltage SM VREF 0 1 V 2 4 11 Vin Input High Voltage SM_VREF 0 1 V 3 11 Input Low Voltage SM_DRAMPWROk Vopg 0 55 0 1 V 10 Vin Input High Voltage SM DRAMPWROK Vppq 0 55 0 1 V 10 Output Low Voltage Vppo 2 R V Q N RrERM Output High Voltage u 2 _ Vor T 46 Ron_up pq DDR3 Data Buffer pull up Resistance 24 31 28 6 32 9 Q 5 Data Buffer pull down Resistance 22 88 28 6 34 32 Q 5 R DDR3 On die termination equivalent 83 100 117 ODT DQ resistance for data signals 41 5 50 65 DDR3 On die termination DC working point driver set to receive mode 0 43 Vcc 0 5 Vcc 0 56 Vcc Ron_up ck DDR3 Clock Buffer pull up Resistance 20 8 26 28 6 Q 5 Ron_pn ck DDR3 Clock Buffer pull down Resistance 20 8 26 31 2 Q 5 DDR3 Command Buffer pull u Ron_uP CMD Resistance P 29 20 22 5 2 DDR3 Command Buffer pull down Ron_DN CMD Resistance P 25 x 5 DDR3 Control Buffer pull up Resistance 16 20 22 e 5 DDR3 Control Buffer pull down RON D
179. lizes all processor cores Core CO State The normal operating state of a core where code is being executed Core C1 C1E State C1 C1E is low power state entered when all threads within a core execute a HLT or MWAIT C1 C1E instruction A System Management Interrupt SMI handler returns execution to either Normal state or the C1 C1E state See the Intel 64 and IA 32 Architecture Software Developer s Manual Volume 3A 3B System Programmer s Guide for more information While a core is in C1 C1E state it processes bus snoops and snoops from other threads For more information on C1E see Section 4 2 5 2 Core C3 State Individual threads of a core can enter the C3 state by initiating a P_LVL2 I O read to the P BLK or an MWAIT C3 instruction A core in C3 state flushes the contents of its L1 instruction cache L1 data cache and L2 cache to the shared L3 cache while maintaining its architectural state All core clocks are stopped at this point Because the core s caches are flushed the processor does not wake any core that is in the C3 state when either a snoop is detected or when another core accesses cacheable memory Core C6 State Individual threads of a core can enter the C6 state by initiating a P LVL3 I O read or an MWAIT C6 instruction Before entering core C6 the core will save its architectural state to a dedicated SRAM Once complete a core will have its voltage reduced to zero volts During exit the core is powered
180. ly through MSR based interfaces in the x2APIC mode The Memory Mapped IO MMIO interface used by xAPIC is not supported in the x2APIC mode e The semantics for accessing APIC registers have been revised to simplify the programming of frequently used APIC registers by system software Specifically the software semantics for using the Interrupt Command Register ICR and End Of Interrupt EOI registers have been modified to allow for more efficient delivery and dispatching of interrupts The x2APIC extensions are made available to system software by enabling the local x2APIC unit in the x2APIC mode To benefit from x2APIC capabilities a new Operating System and a new BIOS are both needed with special support for the x2APIC mode The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendibility for future Intel platform innovations Intel x2APIC technology may not be available on all processor SKUs For more information refer to the Intel 64 Architecture x2APIC Specification at http www intel com products processor manuals 58 Datasheet Volume 1 Power Management 4 Power Management This chapter provides information on the following power management topics e Advanced Configuration and Power Interface ACPI States Processor Core e Integrated Memory Controller IMC e PCI Express Direct Media Interface DMI e Processor Graphics Controller Figure 4 1 Power
181. multiple system thermal and power limitations These controls allow for turbo optimizations within system constraints Datasheet Volume 1 Thermal Management L 5 2 2 Package Power Control The package power control allows for customization to implement optimal turbo within platform power delivery and package thermal solution limitations Figure 5 1 Package Power Control P gt Power limit 2 Short duration turbo lt 10msec exceedence power limit Power limit 2 Long duration turbo power limit Power limit 1 lt Turbo Algorithm Response Te Time 5 2 3 Power Plane Control The processor core and graphics core power plane controls allow for customization to implement optimal turbo within voltage regulator thermal limitations It is possible to use these power plane controls to protect the voltage regulator from overheating due to extended high currents Power limiting per plane cannot be ensured in all usages This function is similar to the package level long duration window control 5 2 4 Turbo Time Parameter Turbo Time Parameter is a mathematical parameter units in seconds that controls the processor turbo algorithm using an exponentially weighted moving average of energy usage During a maximum power turbo event of about 1 25 x TDP the processor could sustain Power_Limit_2 for up to approximately 1 5 the Turbo Time Parameter If the power value and or Turbo Time Parameter
182. nsitioning to an adjacent VID and its associated voltage This will represent a DC shift in the loadline Transitions above the maximum specified VID are not permitted Table 7 5 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained The VR used must be capable of regulating its output to the value defined by the new VID values issued DC specifications for dynamic VID transitions are included in Table 7 5 and Table 7 10 See the VR12 IMVP7 SVID Protocol for further details Datasheet Volume 1 intel Electrical Specifications Sheet 1 of 3 VID VID VID VID VID VID VID VID inition IMVP7 Voltage Identification Def Table 7 1 Vcc 0 88500 0 89000 0 89500 0 90000 0 90500 0 91000 0 91500 0 92000 0 92500 0 93000 0 93500 0 94000 0 94500 0 95000 0 95500 0 96000 0 96500 0 97000 0 97500 0 98000 0 98500 0 99000 0 99500 1 00000 1 00500 1 01000 1 01500 1 02000 1 02500 1 03000 1 03500 1 04000 1 04500 1 05000 1 05500 1 06000 1 06500 1 07000 1 07500 1 08000 1 08500 1 09000 1 09500 HEX 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B D E F 0 1 2 3 4 5 6 7 8 9 A 8 8 8 8 8 8 8 8 8 8 2 3 4 5 6 7 HEX 1 0 25000 0 0 32500 1 0 33000 2 0 33500 3 0 34000 4 0 34500 5 0 35000 6 0 35
183. nsitions provide low parasitic resistance from the regulator to the socket e meet voltage and current specifications as defined in Table 7 3 PLL Power Supply An on die PLL filter solution is implemented on the processor Datasheet Volume 1 85 m 9 Electrical Specifications intel Note 86 Voltage Identification VID The VID specifications for the processor Vcc and are defined by the VR12 IMVP7 SVID Protocol The processor uses three signals for the serial voltage identification interface to support automatic selection of voltages Table 7 1 specifies the voltage level corresponding to the eight bit VID value transmitted over serial VID A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the voltage regulation circuit cannot supply the voltage that is requested the voltage regulator must disable itself See the VR12 IMVP7 SVID Protocol for further details The VID codes will change due to temperature and or current load changes in order to minimize the power of the part A voltage range is provided in Table 7 1 The specifications are set so that one voltage regulator can operate with all supported frequencies Individual processor VID values may be set during manufacturing so that two devices at the same core frequency may have different default VID settings This is shown in the VID range values in Table 7 5 The processor provides the ability to operate while tra
184. ntel Celeron B840 processor 006 Added Intel Celeron B830 887 processors 9 em e 10 Datasheet Volume 1 Introduction Note Note Note Note Note Note Note intel Introduction The 2nd Generation Intel Core processor family mobile and Intel Celeron processor family mobile are the next generation of 64 bit multi core mobile processor built on 32 nanometer process technology Based on a new micro architecture the processor is designed for a two chip platform The two chip platform consists of a processor and Platform Controller Hub PCH The platform enables higher performance lower cost easier validation and improved x y footprint The processor includes Integrated Display Engine Processor Graphics and Integrated Memory Controller and is designed for mobile platforms The processor comes with either 6 or 12 Processor Graphics execution units EU The processor may be offered in a rPGA988B BGA1224 or BGA1023 package Figure 1 1 shows an example platform block diagram This document provides DC electrical specifications signal integrity differential signaling specifications pinout and signal definitions interface functional descriptions thermal specifications and additional feature information pertinent to the implementation and operation of the processor on its respective platform Throughout this document the 2nd Generation Intel Core processor family mobile and Inte
185. ocks Differential DDR3 Output SA CK 1 0 SA CK 1 0 SB CK 1 0 SB_CK 1 0 DDR3 Command Signals Single Ended DDR3 Control Signals DDR3 Output SA BS 2 0 SB BS 2 0 SA WE SB SA RAS SB RAS SA CAS SB CAS SA MA 15 0 SB MA 15 0 Single Ended DDR3 Output SA CKE 1 01 SB CKE 1 0 SA CS 1 0 SB CS 1 0 SA ODT 1 0 SB ODT 1 0 SM DRAMRST DDR3 Data Signals Single ended DDR3 Bi directional SA DQ 63 0 SB DQ 63 0 Differential DDR3 Bi directional SA DQS 7 0 SA_DQS 7 0 SB DQS 7 0 SB DQS 7 0 DDR3 Compensation DDR3 Reference Analog Bi directional SM RCOMP 2 0 Analog Input SM VREF TAP ITP XDP Output Input BCLK ITP BCLK_ITP Single Ended CMOS Input TCK TDI TMS TRST Single Ended Open Drain Output TDO Single Ended Output DBR Asynchronous CMOS Single Ended Bi Directional BPM 7 0 Asynchronous CMOS Single Ended Input PREQ Single Ended Asynchronous CMOS pRpy Datasheet Volume 1 91 intel Table 7 3 Electrical Specifications Signal Groups Sheet 2 of 3 Signal Group Type Signals Control Sideband Single Ended CMOS Input CFG 17 0 Asynchronous Single Ended CMOS Open Drain Bi PROCHOT directional Single Ended Asynchronous CMOS CATERR Output Single Ended Asynchronous CMOS SM_DRAMPWROK UNCOREPWRGOOD g In
186. of the background showing 2D applications processor benchmarks and so on or conditions when the processor is idle Poor examples are full screen 3D games and benchmarks that flip the display image at or near display refresh rates Intel Graphics Dynamic Frequency Intel Graphics Dynamic Frequency Technology is the ability of the processor and graphics cores to opportunistically increase frequency and or voltage above the ensured processor and graphics frequency for the given part Intel Graphics Dynamic Frequency Technology is a performance feature that makes use of unused package power and thermals to increase application performance The increase in frequency is determined by how much power and thermal budget is available in the package and the application demand for additional processor or graphics performance The processor core control is maintained by an embedded controller The graphics driver dynamically adjusts between P States to maintain optimal performance power and thermals The graphics driver will always place the graphics engine in its lowest possible P State thereby acting in the same capacity as Intel GPMT Display Power Savings Technology 6 0 DPST This is a mobile only supported power management feature The Intel DPST technique achieves backlight power savings while maintaining a good visual experience This is accomplished by adaptively enhancing the displayed image while decreasing the backlight brightness sim
187. on graphics workload demand as permitted by the processor turbo control The processor can optimize both processor and Processor Graphics performance through power sharing The processor cores and the processor graphics core share a package power limit If the graphics core is not consuming enough power to reach the package power limit the cores can increase frequency to take advantage of the unused thermal power headroom The opposite can happen when the processor cores are not consuming enough power to reach the package power limit For the Processor Graphics this could mean an increase in the render core frequency above its rated frequency and increased graphics performance Both the processor core s and the graphics render core can increase frequency higher than possible without power sharing Processor utilization of turbo graphic frequencies requires that the Intel Graphics driver to be properly installed Turbo graphic frequencies are not dependent on the operating system processor P state requests and may turbo while the processor is in any processor P states Intel Advanced Vector Extensions Intel AVX Intel Advanced Vector Extensions Intel AVX is the latest expansion of the Intel instruction set It extends the Intel Streaming SIMD Extensions Intel SSE from 128 bit vectors into 256 bit vectors Intel AVX addresses the continued need for vector floating point performance in mainstream scientific and engineering numerical applica
188. onditions and durations are given and tested within the constraints imposed by Tsustained storage and customer shelf life in applicable Intel boxes and bags 7 9 DC Specifications The processor DC specifications in this section are defined at the processor pins unless noted otherwise See Chapter 8 for the processor pin listings and Chapter 6 for signal definitions 94 The DC specifications for the DDR3 signals are listed in Table 7 11 Control Sideband and Test Access Port TAP are listed in Table 7 12 e Table 7 5 lists the DC specifications for the processor and are valid only while meeting specifications for junction temperature clock frequency and input voltages Care should be taken to read all notes associated with each parameter AC tolerances for all DC rails include dynamic load currents at switching frequencies up to 1 MHz Datasheet Volume 1 Electrical Specifications 7 9 1 Voltage and Current Specifications Table 7 5 Processor Core Vcc Active and Idle Mode DC Voltage and Current Specifications Sheet 1 of 2 Datasheet Volume 1 Symbol Parameter Segment Min Typ Max Unit Note XE 0 8 1 35 VID Range for Highest SV QC 0 8 1 35 T HFM VID Frequency Mode Includes SV DC 0 8 1 35 V Us Turbo Mode Operation LV 0 75 13 ULV 0 7 1 2 XE 0 65 0 95 VDR fort SV QC 0 65 0 95 ange for Lowes LFM_VID Frequency Mode SV DC 0 65 0 95 V 1 2 8 LV
189. onitored by a digital thermal sensor DTS meets or exceeds its maximum junction temperature specification T max and asserts PROCHOT The thermal control circuit TCC can be activated prior to T max by use of the TCC activation offset The assertion of PROCHOT activates the thermal control circuit TCC and causes both the processor core and graphics core to reduce frequency and voltage adaptively The TCC will remain active as long as any package temperature exceeds its specified limit Therefore the Adaptive Thermal Monitor will continue to reduce the package frequency and voltage until the TCC is de activated Adaptive Thermal Monitor protection is always enabled Adaptive Thermal Monitor The purpose of the Adaptive Thermal Monitor is to reduce processor core power consumption and temperature until it operates at or below its maximum operating temperature according for TCC activation offset Processor core power reduction is achieved by e Adjusting the operating frequency using the core ratio multiplier and input voltage using the SVID bus e Modulating starting and stopping the internal processor core clocks duty cycle The temperature at which the Adaptive Thermal Monitor activates the Thermal Control Circuit is factory calibrated and is not user configurable The default value is software visible in the TEMPERATURE TARGET 1A2h MSR Bits 23 16 The Adaptive Thermal Monitor does not require any additional hardware so
190. ot be assured in conditions above or below Max Min functional limits Processor PLL Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note PLL supply voltage DC AC specification 18 M TOLccPLL VccPLL Tolerance AC DC 5 IccMAx_vccpLL Max Current for Vccp Rail 1 2 I Thermal Design Current TDC for 1 2 A CCTDC_VCCPLL Rail Note Long term reliability cannot be assured in conditions above or below Max Min functional limits 97 Datasheet Volume 1 intel Electrical Specifications Table 7 10 Processor Graphics Supply DC Voltage and Current Specifications 98 Symbol Parameter Min Typ Max Unit 5 Active VID Range for XE SV QC SV DC 0 65 1 35 GFX VID 0 65 1 35 V 2 3 ULV 0 65 1 35 VAXG Processor Graphics core voltage 0 1 52 V Max Current for Processor Graphics Rail XE SV QC SV DC GT2 33 Iccmax_vaxg SV DC GT1 24 A LV GT2 33 ULV GT2 26 ULV GT1 16 Thermal Design Current TDC for Processor Graphics Rail XE SV QC SV DC GT2 21 5 vAxG SV DC GT1 20 A LV GT2 21 5 ULV GT2 10 ULV GT1 8 Vaxg Tolerance PSO PS1 15 mV 4 PS2 PS3 11 5 mV 4 Ripple Tolerance PSO PS1 18 mV 4 Ripple PS2 7 5 18 5 mV 4 PS3 7 5 27 5 mV Loadline LLAXG GT2 based units 3 9 GT1 based units 4 6
191. otes Rup Internal pull up resistance 15 45 Ohm 3 Vin Input Voltage Range 0 15 Vccio Vhysteresis Hysteresis 0 1 N A Vn Negative Edge Threshold Voltage 0 275 0 500 Vp Positive Edge Threshold Voltage 0 550 Vccro 0 725 Chus Bus Capacitance per Node N A 10 pF Cpad Pad Capacitance 0 7 1 8 pF Ileak000 leakage current OV 0 6 mA 2 Ileak025 leakage current 0 25 Vccro 0 4 mA 2 050 leakage current 0 50 0 2 2 Ileak075 leakage current 0 75 0 13 mA 2 Ileak100 leakage current 0 10 mA 2 Notes 1 supplies the interface behavior does not affect min max specifications 2 leakage specification applies to powered devices on the bus 3 buffer internal pull up resistance measured at 0 75 102 Datasheet Volume 1 Electrical Specifications L 7 10 3 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt triggered input design for improved noise immunity Use Figure 7 2 as a guide for input buffer design Figure 7 2 Input Device Hysteresis 2 7 7 Maximum Vp m PECI High Range Minimum _ Minimum gt Valid Input Hysteresis Signal Range Maximum Minimum Vy E PECI Low Range PECI Ground Y 58 Datasheet Volume 1 103
192. ow power idle states C states are used to save power More power savings actions are taken for numerically higher C states However higher C states have longer exit and entry latencies Resolution of C states occur at the thread processor core and processor package level Thread level C states are available if Intel HT Technology is enabled Long term reliability cannot be assured unless all the Low Power Idle States are enabled Idle Power Management Breakdown of the Processor Cores Thread O Thread 1 Thread O Thread 1 Core 0 State Core 1 State Processor Package State Entry and exit of the C States at the thread and core level are shown in Figure 4 3 Figure 4 3 Thread and Core C State Entry and Exit MWAIT CIHLT 7 T a MWAIT C1 HUT MWAIT C6 Enabled MWAIT C3 P_LVL3 Read P_LVL2 1 0 Read l MWAIT C7 Read C6 C7 While individual threads can request low power C states power saving actions only take place once the core C state is resolved Core C states are automatically resolved by the processor For thread and core C states a transition to and from CO is required before entering any other C state Datasheet Volume 1 47 m Power Management intel Table 4 9 4 2 3 Note Table 4 10 Note 48 Coordination of Thread Power States at
193. peedStep Technology e Multiple frequency and voltage points for optimal performance and power efficiency These operating points are known as P states e Frequency selection is software controlled by writing to processor MSRs The voltage is optimized based on the selected frequency and the number of active processor cores If the target frequency is higher than the current frequency Vcc is ramped up in steps to an optimized voltage This voltage is signaled by the SVID bus to the voltage regulator Once the voltage is established the PLL locks on to the target frequency If the target frequency is lower than the current frequency the PLL locks to the target frequency then transitions to a lower voltage by signaling the target voltage on SVID bus All active processor cores share the same frequency and voltage In a multi core processor the highest frequency P state requested amongst all active cores is selected Software requested transitions are accepted at any time If a previous transition is in progress the new transition is deferred until the previous transition is completed The processor controls voltage ramp rates internally to ensure glitch free transitions e Because there is low transition latency between P states a significant number of transitions per second are possible Datasheet Volume 1 Power Management intel 4 2 2 Caution Figure 4 2 Low Power Idle States When the processor is idle l
194. periods of time or if running a power virus workload Due to Intel Turbo Boost Technology applications are expected to run closer to TDP more often as the processor attempts to take advantage of available headroom in the platform to maximize performance The processor may also exceed the TDP for short durations after a period of lower power operation due to its turbo feature This feature is intended to take advantage of available thermal capacitance in the thermal solution for momentary high power operation The duration and time of such operation can be limited by platform runtime configurable registers within the processor The processor integrates multiple processor and graphics cores on a single die This may result in differences in the power distribution across the die and must be considered when designing the thermal solution Thermal Considerations Intel Turbo Boost Technology allows processor cores and Processor Graphics cores to run faster than the baseline frequency During a turbo event the processor can exceed its TDP power for brief periods Turbo is invoked opportunistically and automatically as long as the processor is conforming to its temperature power delivery and current specification limits Thus thermal solutions and platform cooling that are designed to be less than thermal design guidance may experience thermal and performance issues since more applications will tend to run at or near the maximum power limit for
195. platform e The platform has not granted a package C7 request but has allowed a C6 package state In package C6 state all cores have saved their architectural state and have had their core voltages reduced to zero volts The L3 shared cache is still powered and snoopable in this state The processor remains in package C6 state as long as any part of the L3 cache is active Datasheet Volume 1 Power Management intel 4 2 5 5 4 2 5 6 4 3 4 3 1 Package C7 State The processor enters the package C7 low power state when all cores are in the C7 state and the L3 cache is completely flushed The last core to enter the C7 state begins to shrink the L3 cache by N ways until the entire L3 cache has been emptied This allows further power savings Core break events are handled the same way as in package C3 or C6 However snoops are not sent to the processor in package C7 state because the platform by granting the package C7 state has acknowledged that the processor possesses no snoopable information This allows the processor to remain in this low power state and maximize its power savings Upon exit of the package C7 state the L3 cache is not immediately re enabled It re enables once the processor has stayed out of C6 or C7 for an preset amount of time Power is saved since this prevents the L3 cache from being re populated only to be immediately flushed again Dynamic L3 Cache Sizing Upon entry into the package C7 state th
196. put PM_SYNC RESET Asynchronous Bi Single Ended directional PECI Voltage Regulator Single Ended CMOS Input VIDALERT Single Ended Open Drain Output VIDSCLK Single Ended CMOS Output VCCSA_VID 1 Bi directional CMOS Single Ended Input Open Drain VIDSOUT Output VCCSA_SENSE Single Ended Analog Output VCC DIE SENSE VCC SENSE VSS SENSE VCCIO SENSE VSS SENSE VCCIO Differential Analog Output VAXG SENSE VSSAXG SENSE Power Ground Other VCC VAL SENSE VSS VAL SENSE VAXG VAL SENSE VSSAXG VAL SENSE 3 Vecsar VccpaE Single Ended Power CCDQ Ground Vss DC_TEST_xx No Connect RSVD RSVD_NCTF Test Point RSVD_TP Other SKTOCC PROC_DETECT PCI Express Graphics Differential PCI Express Input PEG_RX 15 0 PEG_RX 15 0 Differential PCI Express Output PEG_TX 15 0 PEG_TX 15 0 Single Ended Analog Input PEG_ICOMPO PEG_ICOMPI PEG_RCOMPO Embedded DisplayPort Differential eDP Output eDP_TX 3 0 eDP_TX 3 0 Differential eDP Bi directional eDP_AUX eDP_AUX Single Ended Asynchronous CMOS rip Input Single Ended Analog Input eDP ICOMPO eDP COMPIO Direct Media Interface DMI Differential Differential 92 DMI Input DMI Output DMI_RX 3 0 DMI_RX 3 0 DMI_TX 3 0 DMI_TX 3 0 Datasheet Volume 1 Electrical Specifications L Table 7 3 7 7 7 8 Signal
197. r memory and frame buffer memory and within system memory Data to be transferred can consist of regions of memory patterns or solid color fills A pattern is always 8 x 8 pixels wide and may be 8 16 or 32 bits per pixel The BLT engine expands monochrome data into a color depth of 8 16 or 32 bits BLTs can be either opaque or transparent Opaque transfers move the data specified to the destination Transparent transfers compare destination color to source color and write according to the mode of transparency selected Data is horizontally and vertically aligned at the destination If the destination for the BLT overlaps with the source memory location the BLT engine specifies which area in memory to begin the BLT transfer Hardware is included for all 256 raster operations source pattern and destination defined by Microsoft including transparent BLT The BLT engine has instructions to invoke BLT and stretch BLT operations permitting software to set up instruction buffers and use batch processing The BLT engine can perform hardware clipping during BLTs Datasheet Volume 1 31 intel Interfaces Processor Graphics Display The Processor Graphics controller display pipe can be broken down into three components e Display Planes e Display Pipes Embedded DisplayPort and Intel FDI Figure 2 7 Processor Display Block Diagram 2 4 2 1 2 4 2 1 1 2 4 2 1 2 32 pH Displ ud lt isplay
198. re is readable in the TEMPERATURE TARGET MSR 1A2h The temperature returned by the DTS is an implied negative integer indicating the relative offset from Tj max The DTS does not report temperatures greater than Tj max Datasheet Volume 1 Thermal Management L 5 4 1 2 1 5 4 1 3 Note 5 4 1 3 1 Note The DTS relative temperature readout directly impacts the Adaptive Thermal Monitor trigger point When a package DTS indicates that it has reached the TCC activation a reading of Oh except when the TCC activation offset is changed the TCC will activate and indicate a Adaptive Thermal Monitor event A TCC activation will lower both IA core and graphics core frequency voltage or both Changes to the temperature can be detected using two programmable thresholds located in the processor thermal MSRs These thresholds have the capability of generating interrupts using the core s local APIC Refer to the Intel 64 and IA 32 Architectures Software Developer s Manuals for specific register and programming details Digital Thermal Sensor Accuracy Taccuracy The error associated with DTS measurement will not exceed 5 C at Tj max The DTS measurement within the entire operating range will meet a 5 C accuracy PROCHOT Signal PROCHOT processor hot is asserted when the processor core temperature has reached its maximum operating temperature T max See Figure 5 2 for a timing diagram of the PROCHOT signal assertion
199. reduce its power consumption using modulation of the internal core clock independent of the processor temperature The duty cycle of the clock modulation is programmable using Bits 3 1 of the same IA32 CLOCK MODULATION MSR In this mode the duty cycle can be programmed in either 12 5 or 6 25 increments discoverable using CPU ID Thermal throttling using this method will modulate each processor core s clock independently I O Emulation Based On Demand Mode I O emulation based clock modulation provides legacy support for operating system software that initiates clock modulation through I O writes to ACPI defined processor clock control registers on the chipset PROC Thermal throttling using this method will modulate all processor cores simultaneously Memory Controller Specific Thermal Features The memory controller provides the ability to initiate memory throttling based upon memory temperature The memory temperature can be provided to the memory controller using PECI or can be estimated by the memory controller based upon memory activity The temperature trigger points are programmable by memory mapped IO registers Programmable Trip Points This memory controller provides programmable critical hot and warm trip points Crossing a critical trip point forces a system shutdown Crossing a hot or warm trip point will initiate throttling The amount of memory throttle at each trip point is programmable Datasheet Volume 1 73
200. resolved with VMM help in setting up the page tables correctly 37 m Technologies intel 3 3 38 Intel Trusted Execution Technology Intel TXT Intel Trusted Execution Technology Intel TXT defines platform level enhancements that provide the building blocks for creating trusted platforms The Intel TXT platform helps to provide the authenticity of the controlling environment such that those wishing to rely on the platform can make an appropriate trust decision The Intel TXT platform determines the identity of the controlling environment by accurately measuring and verifying the controlling software Another aspect of the trust decision is the ability of the platform to resist attempts to change the controlling environment The Intel TXT platform will resist attempts by software processes to change the controlling environment or bypass the bounds set by the controlling environment Intel TXT is a set of extensions designed to provide a measured and controlled launch of system software that will then establish a protected environment for itself and any additional software that it may execute These extensions enhance two areas The launching of the Measured Launched Environment MLE e The protection of the MLE from potential corruption The enhanced platform provides these launch and control interfaces using Safer Mode Extensions SMX The SMX interface includes the following functions e Measured Verified launch of the
201. rved so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality Platform Controller Hub The new 2009 chipset with centralized platform PCH capabilities including the main I O interfaces along with display connectivity audio features power management manageability security and storage features PECI Platform Environment Control Interface PCI Express Graphics External Graphics using PCI Express Architecture A PEG high speed serial interface whose configuration is software compatible with the existing PCI specifications Processor The 64 bit single core or multi core component package Processor Core The term processor core refers to Si die itself which can contain multiple execution cores Each execution core has an instruction cache data cache and 256 KB L2 cache All execution cores share the L3 cache Processor Graphics Intel Processor Graphics Rank A unit of DRAM corresponding four to eight devices in parallel These devices are usually but not always mounted on a single side of a SO DIMM SCI Storage Conditions System Control Interrupt Used in ACPI protocol A non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor landings should not be connected to any supply voltages have any I Os biased or rec
202. s are unable to end an Adaptive Thermal Monitor event the Adaptive Thermal Monitor will use clock modulation Clock modulation is done by alternately turning the clocks off and on at a duty cycle ratio between clock on time and total time specific to the processor The duty cycle is factory configured to 25 on and 75 off and cannot be modified The period of the duty cycle is configured to 32 microseconds when the TCC is active Cycle times are independent of processor frequency A small amount of hysteresis has been included to prevent excessive clock modulation when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases Clock modulation is automatically engaged as part of the TCC activation when the frequency voltage targets are at their minimum settings Processor performance will be decreased by the same amount as the duty cycle when clock modulation is active Snooping and interrupt processing are performed in the normal manner while the TCC is active Digital Thermal Sensor Each processor execution core has an on die Digital Thermal Sensor DTS that detects the core s instantaneous temperature The DTS is the preferred method of monitoring processor die temperature because e It is located near the hottest portions of the die e It can accurately track the die
203. s no point in setting the idle counter in the same range of page close idle timer Another option associated with power down is the 5 DLL off When this option is enabled the SBR I O slave DLLs go off when all channel ranks are in power down Do not confuse it with the DLL off mode in which the DDR DLLs are off This mode requires to define the I O slave DLL wakeup time Initialization Role of CKE During power up CKE is the only input to the SDRAM that has its level recognized other than the DDR3 reset pin once power is applied It must be driven LOW by the DDR controller to make sure the SDRAM components float DQ and DQS during power up CKE signals remain LOW while any reset is active until the BIOS writes to a configuration register Using this method CKE is ensured to remain inactive for much longer than the specified 200 micro seconds after power and clocks to SDRAM devices are stable Conditional Self Refresh Intel Rapid Memory Power Management Intel RMPM conditionally places memory into self refresh in the package C3 C6 and C7 low power states Intel RMPM functionality depends on the graphics display state relevant only when processor graphics is being used as well as memory traffic patterns generated by other connected I O devices The target behavior is to enter self refresh as long as there are no memory requests to service When entering the S3 Suspend to RAM STR state or SO conditional self refresh the
204. s package CO e If the break event was due to a memory access or snoop request But the platform did not request to keep the processor in a higher package C state the package returns to its previous C state And the platform requests a higher power C state the memory access or snoop request is serviced and the package remains in the higher power C state Table 4 11 shows package C state resolution for a dual core processor Figure 4 4 summarizes package C state transitions 50 Datasheet Volume 1 Power Management Table 4 11 Coordination of Core Power States at the Package Level Package C State co 0 6 C7 co CO C1 Core 1 c3 co ci C3 C3 C6 CO cit C3 C6 C6 C6 C7 Note If enabled the package C state will be if all cores have resolved a core C1 state or higher Figure 4 4 Package C State Entry and Exit S 4 2 5 1 Package CO This is the normal operating state for the processor The processor remains in the normal state when at least one of its cores is in the CO or C1 state or when the platform has not granted permission to the processor to go into a low power state Individual cores may be in lower power idle states while the package is in CO Datasheet Volume 1 51 m Power Management intel 4 2 5 2 4 2 5 3
205. signers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached By asserting PROCHOT pulled low and activating the TCC the VR will cool down as a result of reduced processor power consumption Bi directional PROCHOT can allow VR thermal designs to target thermal design current instead of maximum current Systems should still provide proper cooling for the VR and rely on bi directional PROCHOT only as a backup in case of system cooling failure Overall the system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP Thermal Solution Design and PROCHOT Behavior With a properly designed and characterized thermal solution it is anticipated that PROCHOT will only be asserted for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable However an under designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may Cause a noticeable performance loss e Result in prolonged operation at or above the specified maximum junction temperature and affect the long term reliability of the processor e May be incapable of cooling the processor even w
206. significant periods of time Datasheet Volume 1 61 m Thermal Management intel 62 Intel Turbo Boost Technology Power Control and Reporting When operating in the turbo mode the processor will monitor its own power and adjust the turbo frequency to maintain the average power within limits over a thermally significant time period The package processor core and graphic core powers are estimated using architectural counters and do not rely on any input from the platform The behavior of turbo is dictated by the following controls that are accessible using MSR MMIO or PECI interfaces POWER LIMIT 1 TURBO POWER LIMIT MSR 610h bits 14 0 This value sets the exponentially weighted moving average power limit over a long time period This is normally aligned to the TDP of the part and steady state cooling capability of the thermal solution This limit may be set lower than TDP real time for specific needs such as responding to a thermal event If set lower than TDP the processor may not be able to honor this limit for all workloads since this control only applies in the turbo frequency range a very high powered application may exceed POWER LIMIT 1 even at non turbo frequencies The default value is the TDP for the SKU POWER LIMIT 1 TIME TURBO POWER LIMIT MSR 610h bits 23 17 This value is a time parameter that adjusts the algorithm behavior The exponentially weighted moving average turbo algorithm will use this param
207. ss AC9 GND VCCSA L26 PWR vss AD7 GND VCCSA M26 PWR vss AE26 GND VCCSA M27 PWR vss AE27 GND VCCSA_SENSE H23 Analog vss AE28 GND VCCSA VID 0 C22 CMOS VSS AE29 GND VCCSA_VID 1 C24 CMOS VSS AE30 GND VDDQ 1 PWR VSS AE31 GND VDDQ AC4 PWR VSS AE32 GND VDDQ AC7 PWR VSS AE33 GND VDDQ AF1 PWR VSS AE34 GND VDDQ AF4 PWR VSS AE35 GND VDDQ AF7 PWR VSS AE9 GND VDDQ P1 PWR VSS AF2 GND VDDQ P4 PWR VSS AF3 GND VDDQ P7 PWR VSS AF5 GND VDDQ 01 PWR VSS AF6 GND VDDQ U4 PWR VSS AG4 GND VDDQ U7 PWR VSS AG8 GND VDDQ Y1 PWR vss AG9 GND VDDQ Y4 PWR vss AH16 GND VDDQ Y7 PWR vss AH19 GND VIDALERT AJ29 CMOS I vss AH22 GND VIDSCLK AJ30 CMOS VSS AH25 GND VIDSOUT AJ28 CMOS I O VSS AH26 GND VSS A20 GND VSS AH28 GND VSS A23 GND VSS AH29 GND VSS A26 GND VSS AH30 GND VSS A29 GND VSS AH32 GND VSS A3 GND VSS AH34 GND VSS A32 GND VSS AH35 GND Datasheet Volume 1 117 m e n tel Processor Pin and Signal Information Table 8 1 rPGA988B Processor Pin Table 8 1 rPGA988B Processor Pin List by Pin Name List by Pin Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VSS AH4 GND VSS AM7 GND VSS AH7 GND VSS AN10 GND VSS 1 GND VSS AN13 GND VSS AJ10 GND VSS AN16 GND VSS AJ13 GND VSS AN19 GND VSS AJ16 GND VSS AN22 GND VSS AJ19 GND VSS AN25 GND VSS AJ2 GND VSS AN27 GND VSS AJ22 GND
208. stem Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets Intel Virtualization Technology Intel VT x added hardware support in the processor to improve the virtualization performance and robustness Intel Virtualization Technology for Directed I O Intel VT d adds chipset hardware implementation to support and improve I O virtualization performance and robustness Intel VT x specifications and functional descriptions are included the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B and is available at http www intel com products processor manuals index htm The Intel VT d specification and other VT documents can be referenced at http www intel com technology virtualization index htm Intel virtualization Technology Intel VT for IA 32 Intel 64 and Intel Architecture Intel VT x Objectives Intel VT x provides hardware acceleration for virtualization of IA platforms Virtual Machine Monitor VMM can use Intel VT x features to provide improved a reliable virtualized platform By using Intel VT x a VMM is Robust VMMs no longer need to use paravirtualization or binary translation This means that they will be able to run off the shelf OSs and applications without any special steps Enhanced Intel VT enables VMMs to run 64 bit guest operating systems on IA x86 processors More reliable Due to the hard
209. t and system design Intel Turbo Boost Technology Frequency The processor s rated frequency assumes that all execution cores are active and are at the sustained thermal design power TDP However under typical operation not all cores are active or at executing a high power workload Therefore most applications are consuming less than the TDP at the rated frequency Intel Turbo Boost Technology takes advantage of the available TDP headroom and active cores are able to increase their operating frequency To determine the highest performance frequency amongst active cores the processor takes the following into consideration to recalculate turbo frequency during runtime The number of cores operating in the CO state The estimated core current consumption e The estimated package prior and present power consumption e The package temperature Any of these factors can affect the maximum frequency for a given workload If the power current or thermal limit is reached the processor will automatically reduce the frequency to stay with its TDP limit Intel Turbo Technology processor frequencies are only active if the operating system is requesting the PO state For more information on P states and C states refer to Chapter 4 Power Management Datasheet Volume 1 39 m Technologies intel Note 3 5 3 6 40 Intel Turbo Boost Technology Graphics Frequency The graphics render frequency is selected dynamically based
210. t 2 of 2 156 8 15 Processor rPGA988B 4C GT2 Mechanical Package Sheet 1 of 2 157 8 16 Processor rPGA988B 4C GT2 Mechanical Package Sheet 2 of 2 158 8 17 Processor BGA1023 2C GT2 Mechanical Package Sheet 1072 159 8 18 Processor BGA1023 2C GT2 Mechanical Package Sheet 2 of 2 160 8 19 Processor BGA1224 4 GT2 Mechanical Package Sheet 1 2 161 8 20 Processor BGA1224 4C GT2 Mechanical Package Sheet 2 2 162 8 21 Processor rPGA988B 2C GT1 Mechanical Package Sheet 1072 163 8 22 Processor rPGA988B 2C GT1 Mechanical Package Sheet 2 of 2 164 8 23 Processor BGA1023 2C GT1 Mechanical Package Sheet 1072 165 8 24 Processor BGA1023 2C GT1 Mechanical Package Sheet 2 of 2 166 Tables 1 1 PCI Express Supported Configurations in Mobile Products 14 1 2 aiiis a 18 1 3 Rel ted Documents rrr erue xam eu aine ate sa ERRARE 20 2 1 Supported SO DIMM Module Configurations 21 2 2 DDR3 System Memory Timing SUpport uU mme enhn nnns 22
211. t Device uu u a a eua de qu 103 8 1 rPGA988B Socket G2 Pinmap Top View Upper Left Quadrant 106 8 2 rPGA988B Socket G2 Pinmap Top View Upper Right Quadrant 107 8 3 rPGA988B Socket G2 Top View Lower Left Quadrant 108 8 4 rPGA988B Socket G2 Pinmap Top View Lower Right Quadrant 109 8 5 BGA1224 Ballmap Top View Upper Left Quadrant 121 8 6 BGA1224 Ballmap Top View Upper Right Quadrant 122 8 7 BGA1224 Ballmap Top View Lower Left Quadrant 123 8 8 BGA1224 Ballmap Top View Lower Right Quadrant 124 8 9 BGA1023 Top View Upper Left Quadrant 140 8 10 BGA1023 Ballmap Top View Upper Right Quadrant 141 8 11 BGA1023 Ballmap Top View Lower Left Quadrant 142 8 12 BGA1023 Ballmap Top View Lower Right Quadrant 143 8 13 Processor rPGA988B 2C GT2 Mechanical Package Sheet 1072 155 8 14 Processor rPGA988B 2C GT2 Mechanical Package Shee
212. t point a core is allowed to go into C3 C6 or C7 Each option can be run concurrently or individually This feature is disabled by default BIOS must enable it in the PMG CST CONTROL register The auto demotion policy is also configured by this register 4 2 5 Package C States The processor supports CO C1 C1E C3 C6 and C7 power states The following is a summary of the general rules for package C state entry These apply to all package C states unless specified otherwise A package C state request is determined by the lowest numerical core C state amongst all cores e A package C state is automatically resolved by the processor depending on the core idle power states and the status of the platform components Each core can be at a lower idle power state than the package if the platform does not grant the processor permission to enter a requested package C state The platform may allow additional power savings to be realized in the processor For package C states the processor is not required to enter CO before entering any other C state The processor exits a package C state when a break event is detected Depending on the type of break event the processor does the following e If a core break event is received the target core is activated and the break event message is forwarded to the target core If the break event is not masked the target core enters the core CO state and the processor enter
213. te This is connected to the PCH PROCPWRGD signal SKTOCC SKTOCC Socket Occupied PROC_DETECT Processor rPGA only Detect Pulled down directly O Ohms on the processor package to PROC DETECT ground There is no connection to the processor silicon for this signal BGA System board designers may use this signal to determine if the processor is present 6 12 Processor Power Signals Table 6 14 Processor Power Signals Sheet 1 of 2 Direction Signal Name Description Buffer Type VCC Processor core power rail Ref VCCIO Processor power for I O Ref VDDQ Processor I O supply voltage for DDR3 Ref VAXG Graphics core power supply Ref VCCPLL VCCPLL provides isolated power for internal processor PLLs Ref VCCSA System Agent power supply Ref VCCPQE Filtered low noise derivative of VCCIO Ref BGA Only 82 Datasheet Volume 1 Signal Description intel Table 6 14 Processor Power Signals Sheet 2 of 2 Signal Name Description Direction Buffer Type Filtered low noise derivative of VDDQ 6 13 Table 6 15 Sense Signals 6 14 VCCDQ BGA Only Ref VIDALERT VIDSCLK and VIDSCLK comprise a three signal serial 1 0 VIDSOUT synchronous interface used to transfer power management information VIDSCLK between the processor and the voltage regulator controllers This serial I VIDALERT VID interface replaces the parallel VID interface on previous processors CMOS Voltage s
214. temperature and ensure that the Adaptive Thermal Monitor is not excessively activated Temperature values from the DTS can be retrieved through e A software interface using processor Model Specific Register MSR A processor hardware interface as described in Section 5 4 4 When temperature is retrieved by processor MSR it is the instantaneous temperature of the given core When temperature is retrieved using PECI it is the average of the highest DTS temperature in the package over a 256 ms time window Intel recommends using the PECI reported temperature for platform thermal control that benefits from averaging such as fan speed control The average DTS temperature may not be a good indicator of package Adaptive Thermal Monitor activation or rapid increases in temperature that triggers the Out of Specification status bit within the PACKAGE STATUS MSR 01B1h IA32 STATUS MSR 19Ch Code execution is halted in C1 C7 Therefore temperature cannot be read using the processor MSR without bringing a core back into CO However temperature can still be monitored through PECI in lower C states except for C7 Unlike traditional thermal devices the DTS outputs a temperature relative to the maximum supported operating temperature of the processor T max regardless of TCC activation offset It is the responsibility of software to convert the relative temperature to an absolute temperature The absolute reference temperatu
215. ter power savings but has a bigger performance impact since all pages will first be closed before putting the devices in power down mode If dynamic power down is enabled all ranks are powered up before doing a refresh cycle and all ranks are powered down at the end of refresh DRAM I O Power Management Unused signals should be disabled to save power and reduce electromagnetic interference This includes all signals associated with an unused memory channel Clocks can be controlled on a per SO DIMM basis Exceptions are made for per SO DIMM control signals such as CS CKE and ODT for unpopulated SO DIMM slots The I O buffer for an unused signal should be tri stated output driver disabled the input receiver differential sense amp should be disabled and any DLL circuitry related ONLY to unused signals should be disabled The input path must be gated to prevent spurious results due to noise on the unused signals typically handled automatically when input receiver is disabled PCI Express Power Management e Active power management support using LOs and L1 states e All inputs and outputs disabled in L2 L3 Ready state PEG interface does not support Hot Plug Power impact may be observed when PEG link disable power management state is used Direct Media Interface DMI Power Management e Active power management support using LOs L1 state Datasheet Volume 1 Power Management 4 6 4 6 1 4 6 2 4 6 3
216. terface that provides a communication channel between a PECI client the processor and a PECI master The processors support the PECI 3 0 Specification 1 2 5 Processor Graphics 16 The Processor Graphics contains a refresh of the sixth generation graphics core enabling substantial gains in performance and lower power consumption Up to 12 EU Support Next Generation Intel Clear Video Technology HD support is a collection of video playback and enhancement features that improve the end user s viewing experience Encode transcode HD content Playback of high definition content including Blu ray Disc Superior image quality with sharper more colorful images Playback of Blu ray disc S3D content using HDMI V 1 4 with 3D DirectX Video Acceleration DXVA support for accelerating video processing Full AVC VC1 MPEG2 HW Decode Advanced Scheduler 2 0 1 0 XPDM support Windows 7 XP Windows Vista OSX Linux OS Support DX10 1 DX10 DX9 support OGL 3 0 support Datasheet Volume 1 Introduction 1 2 6 1 2 7 1 3 1 3 1 1 3 2 1 3 3 1 3 4 1 3 5 Embedded DisplayPort eDP e Stand alone dedicated port unlike previous generation processor that shared pins with PCIe interface Intel Flexible Display Interface Intel FDI e For SKUs with graphics Intel FDI carries display traffic from the Processor Graphics in the processor to the legacy display connectors in the PCH e Based on DisplayPort stand
217. the Core Level Processor Core Thread 1 C State co zi ER gt co co co co CO CO cii cil cit cil Thread 0 co cit C6 CO cit C6 C6 C7 CO cil C6 C7 Note If enabled the core C state will be if all cores have resolved a core C1 state or higher Requesting Low Power Idle States The primary software interfaces for requesting low power idle states are through the MWAIT instruction with sub state hints and the HLT instruction for and However software may make C state requests using the legacy method of I O reads from the ACPI defined processor clock control registers referred to as P LVLx This method of requesting C states provides legacy support for operating systems that initiate C state transitions using I O reads For legacy operating systems P LVLx I O reads are converted within the processor to the equivalent MWAIT C state request Therefore P_LVLx reads do not directly result in I O reads to the system The feature known as I O MWAIT redirection must be enabled in the BIOS The P LVLx I O Monitor address needs to be set up before using the P LVLx I O read interface Each P LVLx is mapped to the supported MWAIT Cx instruction as shown in Table 4 10 P LVLx to MWAIT Conversion P LVLx MWAIT Cx Notes P_LVL2 MWAIT C3 P_LVL3 MWAIT C6 C6 No sub states allowed P_LVL4 MWAIT C7 C7 No sub states allowed P_LVL5
218. the characterization at higher temperatures and extrapolating the values for the junction temperature indicated At Tj of Tj max At Tj of 50 9C At Tj of 35 9C 10 Can be modified at runtime by MSR writes with MMIO and with PECI commands 11 Turbo Time Parameter is a mathematical parameter unit in seconds that controls the processor turbo algorithm using a moving average of energy usage Avoid setting the Turbo Time Parameter to a value less than 0 1 seconds Refer to Section 5 2 4 for further information 12 Shown limit is a time averaged power based upon the Turbo Time Parameter Absolute product power may exceed the set limits for short durations or under virus or uncharacterized workloads 13 Processor will be controlled to specified power limit as described in Section 5 2 1 If the power value and or Turbo Time Parameter is changed during runtime it may take a short period of time approximately 3 to 5 times the Turbo Time Parameter for the algorithm to settle at the new control limits 14 This is a hardware default setting and not a behavioral characteristic of the part 15 For controllable turbo workloads the limit may be exceeded for up to 10 ms 16 Tjmax for some Dual Core SV SKUs in rPGA package will be 85 C Refer to Dear Customer Letters DCLs or contact your field representative to get details of SKUs that have Tjmax of 85 C Datasheet
219. these standards Storage Condition Specifications Environmental storage condition limits define the temperature and relative humidity that the device is exposed to while being stored in a moisture barrier bag The specified storage conditions are for component level prior to board attach Table 7 5 specifies absolute maximum and minimum storage temperature limits that represent the maximum or minimum device condition beyond which damage latent or otherwise may occur The table also specifies sustained storage temperature relative humidity and time duration limits These limits specify the maximum or minimum device storage conditions for a sustained period of time Failure to adhere to the following specifications can affect long term reliability of the processor Datasheet Volume 1 93 intel Electrical Specifications Table 7 4 Storage Condition Ratings Symbol Parameter Min Max Notes The non operating device storage temperature Damage latent or otherwise Tapsolute storage may occur when exceeded for any length of 25 C 1 2 3 4 time The ambient storage temperature in shipping 5 Tsustained storage media for a sustained period of time 5 C 202C 5 6 The ambient storage temperature in shipping i555 Tshort term storage media for a short period of time iis The maximum device storage relative humidit RHsustained storage for a sustained period of time
220. these signals to VDDQ VccPLL Vccsa VAXG Vss or to any other signal including each other may result in component malfunction or incompatibility with future processors See Chapter 8 for a pin listing of the processor and the location of all reserved signals For reliable operation always connect unused inputs or bi directional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground Vss Unused outputs maybe left unconnected however this may interfere with some Test Access Port TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bi directional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Datasheet Volume 1 Electrical Specifications intel Signals are grouped by buffer type and similar characteristics as listed in Table 7 3 The buffer type indicates which signaling technology and specifications apply to the signals All the differential signals and selected DDR3 and Control Sideband signals have On Die Termination ODT resistors There are some signals that do not have ODT and 7 6 Signal Groups need to be terminated on the board Table 7 3 Signal Groups Sheet 1 of 3 Signal Group Type Signals System Reference Clock BCLK BCLK Differential CMOS Input DPLL REF DPLL REF CLK DDR3 Reference Cl
221. tion 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 architecture Performance will vary depending on your hardware and software configurations Consult with your system vendor for more information No computer system can provide absolute security under all conditions Intel Trusted Execution Technology Intel TXT requires a computer system with Intel Virtualization Technology an Intel TXT enabled processor chipset BIOS Authenticated Code Modules and an Intel TXT compatible measured launched environment MLE The MLE could consist of a virtual machine monitor an OS or an application In addition Intel TXT requires the system to contain a TPM v1 2 as defined by the Trusted Computing Group and specific software for some uses For more information see http www intel com technology security Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain computer system software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Intel Active Management Technology requires the computer system to have an Intel
222. tions The processor is compatible with the Intel 6 Series Chipset PCH The processor is not compatible with any previous PCH products 28 Datasheet Volume 1 Interfaces 2 3 3 2 4 intel DMI Link Down The DMI link going down is a fatal unrecoverable error If the DMI data link goes to data link down after the link was up then the DMI link hangs the system by not allowing the link to retrain to prevent data corruption This link behavior is controlled by the PCH Downstream transactions that had been successfully transmitted across the link prior to the link going down may be processed as normal No completions from downstream non posted transactions are returned upstream over the DMI link after a link down event Processor Graphics Controller GT New Graphics Engine Architecture includes 3D compute elements Multi format hardware assisted decode encode Pipeline and Mid Level Cache MLC for superior high definition playback video quality and improved 3D performance and Media Display Engine in the Uncore handles delivering the pixels to the screen GSA Graphics in System Agent is the primary Channel interface for display memory accesses and PCI like traffic in and out Figure 2 6 Processor Graphics Controller Unit Block Diagram VS GS Setup Rasterize Hierachical Z Hardware Clipper Unified Execution Unit Array Texture Unit Pixel Backend U EU E
223. tions visual processing recognition data mining synthesis gaming physics cryptography and other areas of applications The enhancement in Intel AVX allows for improved performance due to wider vectors new extensible syntax and rich functionality including the ability to better manage rearrange and sort data For more information on Intel AVX see http www intel com software avx Intel Advanced Encryption Standard New Instructions Intel AES NI The processor supports Advanced Encryption Standard New Instructions Intel AES NI that are a set of Single Instruction Multiple Data SIMD instructions that enable fast and secure data encryption and decryption based on the Advanced Encryption Standard AES Intel AES NI are valuable for a wide range of cryptographic applications such as applications that perform bulk encryption decryption authentication random number generation and authenticated encryption AES is broadly accepted as the standard for both government and industry applications and is widely deployed in various protocols Intel AES NI consists of six Intel SSE instructions Four instructions AESENC AESENCLAST AESDEC and AESDELAST facilitate high performance AES encryption and decryption The other two AESIMC and AESKEYGENASSIST support the AES key expansion procedure Together these instructions provide a full hardware for supporting AES offering security high performance and a great deal of flexibility Datashe
224. ultaneously The goal of this technique is to provide equivalent end user perceived image quality at a decreased backlight power level 1 The original input image produced by the operating system or application is analyzed by the Intel DPST subsystem An interrupt to Intel DPST software is generated whenever a meaningful change in the image attributes is detected A meaningful change is when the Intel DPST software algorithm determines that enough brightness contrast or color change has occurred to the displaying images that the image enhancement and backlight control needs to be altered 2 Intel DPST subsystem applies an image specific enhancement to increase image contrast brightness and other attributes 3 A corresponding decrease to the backlight brightness is applied simultaneously to produce an image with similar user perceived quality such as brightness as the original image Intel DPST 5 0 has improved the software algorithms and has minor hardware changes to better handle backlight phase in and ensures the documented and validated method to interrupt hardware phase in Datasheet Volume 1 Power Management 4 6 7 4 6 8 4 7 Automatic Display Brightness ADB This is a mobile only supported power management feature Intel Automatic Display Brightness feature dynamically adjusts the backlight brightness based upon the current ambient light environment This feature requires an additional sensor to
225. uration mechanisms and transaction rules 2 2 3 PCI Express Graphics The external graphics attach PEG on the processor is a single 16 lane x16 port The PEG port is compliant with the PCI Express Base Specification Revision 2 0 Datasheet Volume 1 27 Interfaces 2 2 4 PCI Express Lanes Connection Figure 2 5 demonstrates the PCIe lanes mapping Figure 2 5 PCI Express Typical Operation 16 lanes Mapping Lane 0 0 0 1 Lane 1 1 2 Lane 2 2 3 Lane 3 3 4 Lane 4 4 5 Lane 5 5 Lane 6 5 6 6 E 7 Lane 7 7 5 0 8 x 1 9 Lane 9 9 2 10 Lane 10 10 E L 11 9 11 ae 11 Lane 12 0 4 gt 12 5 1 5 13 Lane 13 13 8 gt 6 14 14 14 x b Lane 15 3 7 15 15 2 3 Direct Media Interface DMI Direct Media Interface DMI connects the processor and the PCH Next generation DMI2 is supported Note Only DMI x4 configuration is supported 2 3 1 DMI Error Flow DMI can only generate SERR in response to errors never SCI SMI MSI PCI INT or GPE Any DMI related SERR activity is associated with Device 0 2 3 2 Processor PCH Compatibility Assump
226. us ratio is resolved the processor core will transition to the new target automatically e On an upward operating point transition the voltage transition precedes the frequency transition On a downward transition the frequency transition precedes the voltage transition When transitioning to a target core operating voltage a new VID code to the voltage regulator is issued The voltage regulator must support dynamic VID steps to support this method During the voltage change e It will be necessary to transition through multiple VID steps to reach the target operating voltage e Each step is 5 mV for Intel MVP 7 0 compliant VRs e The processor continues to execute instructions However the processor will halt instruction execution for frequency transitions If a processor load based Enhanced Intel SpeedStep Technology P state transition through MSR write is initiated while the Adaptive Thermal Monitor is active there are two possible outcomes e If the P state target frequency is higher than the processor core optimized target frequency the p state transition will be deferred until the thermal event has been completed e If the P state target frequency is lower than the processor core optimized target frequency the processor will transition to the P state operating point Datasheet Volume 1 69 m Thermal Management intel 5 4 1 1 2 5 4 1 2 Note 70 Clock Modulation If the frequency voltage change
227. ware support VMMs can now be smaller less complex and more efficient This improves reliability and availability and reduces the potential for software conflicts More secure The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system Datasheet Volume 1 35 Technologies 3 1 2 Intel Virtualization Technology Intel VT for IA 32 Intel 64 and Intel Architecture Intel VT x Features The processor core supports the following Intel VT x features e Extended Page Tables EPT EPT is hardware assisted page table virtualization It eliminates VM exits from guest OS to the VMM for shadow page table maintenance e Virtual Processor IDs VPID Ability to assign a VM ID to tag processor core hardware structures such as TLBs This avoids flushes on VM transitions to give a lower cost VM transition time and an overall reduction in virtualization overhead Guest Preemption Timer Mechanism for a VMM to preempt the execution of a guest OS after an amount of time specified by the VMM The VMM sets a timer value before entering a guest The feature aids VMM developers in flexibility and Quality of Service QoS assurances Descriptor Table Exiting Descriptor table exiting allows a VMM to protect a guest OS from internal malicious software based attack by preventing relocation of key system
228. y Support for register based fault recording only for single entry only and support for MSI interrupts for faults Support for both leaf and non leaf caching Support for boot protection of default page table Support for non caching of invalid page table entries Support for hardware based flushing of translated but pending writes and pending reads on IOTLB invalidation Support for page selective IOTLB invalidation MSI cycles MemWr to address FEEx_xxxxh not translated Translation faults result in cycle forwarding to VBIOS region byte enables masked for writes Returned data may be bogus for internal agents PEG DMI interfaces return unsupported request status Interrupt Remapping is supported Queued invalidation is supported VT d translation bypass address range is supported Pass Through Note Intel VT d Technology may not be available on all SKUs 3 1 5 Intel Virtualization Technology Intel VT for Directed I O Intel VT d Features Not Supported The following features are not supported by the processor with Intel VT d Datasheet Volume 1 No support for PCISIG endpoint caching ATS No support for Intel VT d read prefetching snarfing that is translations within a cacheline are not stored in an internal buffer for reuse for subsequent translations No support for advance fault reporting No support for super pages No support for Intel VT d translation bypass address range such usage models need to be

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