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Intel Atom E620

1. Table 235 14h ECAP Extended Capabilities Size 32 bit Default 0000_0000h Power Well Core Access D F 0 27 Offset Start 14h PCI Configuration B D F 0 27 0 Offset End 17h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 31 1 0 RO RSVD Reserved Docking Supported A 1 indicates that processor supports Intel HD 0 Oh R WO DS AudioP Docking The GCTL DA bit is only writable when this bit is 1 This bit is reset to its default value only on RESET B but not on a CRST B or D3gor to DO transition 9 3 2 1 11 Offset 18h STRMPAY Stream Payload Capability Register Table 236 18h STRMPAY Stream Payload Capability Register Size 32 bit Default 0018 0030h Power Well Core Access D F 0 27 Offset Start 18h PCI Configuration B D F 0 27 0 Offset End 1Bh Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 31 24 0 RO RSVD Reserved Input Indicates the number of words per frame for the input streams is 23 16 18h RO IN zc words This measurement is in 16 bit word quantities per 48kHz rame 15 08 0 RO RSVD Reserved Output Indicates the number of words per frame for output streams is 07 00 30h RO OUT Mia words This measurement is in 16 bit word quantities per 48kHz rame 9 3 2 1 12 Offset 20h INTCTL Interrupt Control Register Table 237 20h INTCTL Interrupt Cont
2. 5 5 2 4 Table 51 3120h D261P Device 26 I nterrupt Pin Size 32 bit Default Power Well Memory Mapped IO BAR RCBA Offset 3120h Bit Range Default Access Acronym Description 31 04 0 RO RSVD Reserved 03 00 1h RW PAIP PCI Express 4 Pin Indicates which pin PCI Express port 3 uses 5 5 2 5 Offset 3124h D25IP Device 25 Interrupt Pin Table 52 3124h D25IP Device 25 Interrupt Pin Size 32 bit Default Power Well Memory Mapped IO BAR RCBA Offset 3124h Bit Range Default Access Acronym Description 31 04 0 RO RSVD Reserved 03 00 1h RW P3IP PCI Express 3 Pin Indicates which pin PCI Express port 2 uses 5 5 2 6 Offset 3128h D24IP Device 24 Interrupt Pin Table 53 3128h D24I P Device 24 Interrupt Pin Size 32 bit Default Power Well Memory Mapped IO BAR RCBA Offset 3128h Bit Range Default Access Acronym Description 31 04 0 RO RSVD Reserved 03 00 1h RW P2IP PCI Express 2 Pin Indicates which pin PCI Express port 1 uses 5 5 2 7 Offset 312Ch D23IP Device 23 Interrupt Pin Table 54 312Ch D23IP Device 23 Interrupt Pin Size 32 bit Default Power Well Memory Mapped IO BAR RCBA Offset 312Ch Bit Range Default Access Acronym Description 31 04 0 RO RSVD Reserved 03 00 1h RW P1IP PCI Express 1 Pin Indicates which pin PCI Express port 0 uses Intel Atom Processor E6xx Series Datasheet 63 m
3. 11 7 1 8 Offset 1Ch CGTS Core Well GPI O Trigger Status Table 348 1Ch CGTS Core Well GPIO Trigger Status Size 32 bit Default 00000000h Power Well Core Access DF 0 31 Offset Start 1Ch PCI Configuration B D F 0 31 0 Offset End 1Fh Memory Mapped lO BAR GPIO BAR 10 Offset Bit Range Default Access Acronym Description 31 05 0 RO RSVD Reserved Trigger Status When set the corresponding GPIO if enabled as input via GIO IO n triggered an SMI SCI This will be set if a 0 to 1 transition occurred and GTPE TE n was set or a 1 to 0 transition 04 00 0 RWC TS occurred and GTNE TE n was set If both GTPE TE n and GTNE TE n are set then this bit will be set on both a 0 to 1 and a 1 to 0 transition This bit will not be set if the GPIO is configured as an output 11 7 2 Resume Well GPIO 1 O Registers The control for the general purpose I O signals is handled through an independent 64 byte I O space The base offset for this space is selected by the GPIO BAR register in D31 FO config space The total GPIO in resume well is 9 Table 349 Resume Well GPI O Registers Start End Name 20 23 RGEN Resume Well GPIO Enable 24 27 RGIO Resume Well GPIO Input Output Select 28 2B RGLV Resume Well GPIO Level for Input or Output 2C 2F RGTPE Resume Well GPIO Trigger Positive Edge Enable 30 33 RGTNE Resume Well GPIO Trigger Negative Edg
4. Signal Name Direction Reset Post Reset S3 S4 S5 LVD DATAN 0 O High Z High Z off off LVD_DATAN_1 O High Z High Z Off Off LVD DATAN 2 O High Z High Z off off LVD_DATAN_3 O High Z High Z Off Off LVD DATAP O O High Z High Z off off LVD_DATAP_1 O High Z High Z Off Off LVD DATAP 2 O High Z High Z off off LVD_DATAP_3 O High Z High Z off off LVD_CLKN O High Z High Z Off Off LVD_CLKP Oo High Z High Z Off Off LVD IBG I High Z High Z Off Off LVD_VBG High Z High Z off off LVD_VREFL l High Z High Z off off LVD_VREFH l High Z High Z Off Off 3 3 2 Serial Digital Video Output SDVO Signals Table 22 Serial Digital Video Output Signals Sheet 1 of 2 Signal Name Direction Reset Post Reset S3 S4 S5 Svo MEN o VoL VoL Off Off ye CHEN 9 VoL VoL off off SR Gert S VoL VoL Off Off SUC ati VoL VoL Off Off a l VIX unknown VIX unknown off off Intel Atom Processor E6xx Series Datasheet 46 Pin States n tel Table 22 Serial Digital Video Output Signals Sheet 2 of 2 Signal Name Direction Reset Post Reset S3 S4 S5 SDVO TVCLKI NP SDVO TVCLKINN l VIX unknown VIX unknown off off SDVO_STALLP SDVO STALLN l VIX unknown VIX unknown off Off SDVO_CTRLCLK 1 0 High Z High Z Off Off SDVO_CTRLDATA 1 0 High Z High Z Off Off 3 4 PCI Express Signals Table 23 PCI
5. 9 3 2 1 34 Offset 84h A4h C4h E4h ISDOLPI B ISDILPI B OSDOLPI B OSD1LPIB I nput Output Stream Descriptor 0 1 Link Position in Buffer Register Table 259 84h A4h C4h E4h ISDOLPIB I SDILPI B OSDOLPI B OSD1LPIB Input Output Stream Descriptor 0 1 Link Position in Buffer Register Size 32 bit Default 0000_0000h Power Well Core Access D F 0 97 Offset Start 84h A4h C4h E4h PCI Configuration B D F 0 27 0 Offset End 87h A7h C7h E7h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description Link Position in Buffer ndicates the number of bytes that have been 31 00 0 RO LPIB received off the link This register will count from O to the value in the Cyclic Buffer Length register and then wrap to 0 9 3 2 1 35 Offset 88h A8h C8h E8h ISDOCBL ISD1CBL OSDOCBL OSD1CBL I nput Output Stream Descriptor 0 1 Cyclic Buffer Length Register Table 260 88h A8h C8h E8h ISDOCBL I SDI1CBL OSDOCBL OSD1CBL Input Output Stream Descriptor 0 1 Cyclic Buffer Length Register Size 32 bit Default 0000 0000h Power Well Core Access 3 DE 0 27 Offset Start 88h A8h C8h E8h PCI Configuration B D F 0 27 0 Offset End 8Bh ABh CBh EBh Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description Length Indicates the number of bytes in the complete cyclic buffer CBL must represent an integer number of samples Link Positi
6. 11 8 2 4 Offset 04h TSA Transmit Slave Address This register contains the address of the intended target Table 362 04h TSA Transmit Slave Address Size 8 bit Default 00h Power Well Core Access e Offset Start 04h PCI Configuration B D F Offset End 04h Bit Range Default Access Acronym Description 07 01 0 RW AD Address 7 bit address of the targeted slave 00 0 RW R Read Direction of the host transfer 1 read 0 write 11 8 2 5 Offset 05h HCMD Host Command Register This field is transmitted in the command field of the SMB protocol during the execution of any command Table 363 O5h HCMD Command Register Size 8 bit Default 00h Power Well Core Access Pis Offset Start 05h PCI Configuration B D F Offset End 05h Bit Range Default Access Acronym Description 07 00 00h RW CMD Command Command Field Intel Atom Processor E6xx Series Datasheet 243 intel Series 11 8 2 6 Offset 06h HDO Host Data O This field is transmitted in the DATAO field of an SMBus cycle For block writes this register reflects the number of bytes to transfer This register should be programmed to a value between 1h 1 bytes and 20h 32 bytes for block counts A count of 00h or above 20h will result in no transfer and HSTS CS will be cleared indicating a failure Table 364 06h HDO Host Data O
7. Size 8 bit Default 80h Power Well Access DF X 31 Offset Start 60h PCI Configuration B D F X 31 0 Offset End 67h Bit Range Default Access Acronym Description Interrupt Routing Enable REN 0 The corresponding PI RQ is routed to one of the legacy interrupts specified in bits 3 0 1 The PIRQ is not routed to the 8259 07 1 RW REN Note BIOS must program this bit to O during POST for any of the PIRQs that are being used The value of this bit may subsequently be changed by the OS when setting up for I O APIC interrupt delivery mode 06 04 000b RO RSVD Reserved IRQ Routing Indicates how to route PIRQx B Bits Mapping Bits Mapping Oh Reserved 8h Reserved 1h Reserved 9h IRQ9 2h Reserved Ah IRQ10 03 00 0 RW IR 3h IRQ3 Bh IRQ11 4h IRQ4 Ch IRQ12 5h IRQ5 Dh Reserved 6h IRQ6 Eh IRQ14 7h IRQ7 Fh IRQ15 Intel Atom Processor E6xx Series Datasheet 195 intel LPC Interface D31 F0 10 4 2 SCNT Serial I RQ Control Register Table 291 Offset 68h SCNT Serial IRQ Control Size 8 bit Default 80h Power Well Access D E X 31 Offset Start 68h PCI Configuration B D F X 31 0 Offset End 6Bh Bit Range Default Access Acronym Description Mode This bit must be set to ensure that the first action of the processor is a 07 0 RW MD start frame 0 Processor is in quiet mode 1 Processor is in continuous mode 06 00 00h RO
8. Intel Atom Processor E6xx Series Datasheet 290 Ballout and Package Information intel Table 407 Pin List Table 407 Pin List Table 407 Pin List Pin Name Ball Pin Name Ball Pin Name Ball M MA 0 AA8 PCIE_PETP 1 D27 SPI CS B H5 M MA 1 AA10 PCIE PETP 2 D31 SPI MISO E2 M MA 10 W10 PCIE PETP 3 H31 SPI MOSI F1 M MA 11 AG8 PCIE RBIAS E22 SPI SCK F5 M MA 12 AD5 PCIE RCOMPO A24 SPKR G2 M MA 13 AU10 PRDY B AM33 SUSCLK J2 M_MA 14 AJ8 PREQ B AM37 TCK AN22 M MA 2 ANA PROCHOT B AT27 TDI AN16 M MA 3 Y7 PWRMODE 0 AK23 TDO AN18 M MA 4 AN2 PWRMODE 1 AN26 TEST_B H3 M MA 5 AP7 PWRMODE 2 AL24 THERMTRIP B AU28 M MA 6 AH7 PWROK Y1 THRM B G10 M MA 7 ws RCOMP H37 THRMDA P33 M MA 8 AB7 RESET B K5 THRMDC N34 M MA 9 AF7 RSMRST B V1 TMS AL16 M ODI O0 AK11 RSTRDY B K7 TRST B AL14 M_ODT 1 AN12 RSTWARN L4 vcc R22 M_RASB AJ10 RTCRST B AA2 vcc R24 M_RCOMPOUT AE8 amp RTCX1 L8 VCC U22 M_RCVENIN AC8 RTCX2 M7 VCC U24 M_RCVENOUT AD7 SDVO_BLUEN D17 VCC W22 M_SRFWEN AT9 SDVO BLUEP E18 VCC W24 M_WEB AT13 SDVO_CLKN A12 VCC AA22 NCTCK AN28 SDVO_CLKP B13 VCC AA24 NCTDI AL22 SDVO_CTRLCLK E14 VCC AC22 NCTDO AU30 SDVO_CTRLDATA B7 VCC AC24 NCTMS AP27 SDVO_GREENN B19 VCC AE22 PCIE_CLKINN A26 SDVO_GREENP A18 VCC AE24 PCIE CLKI NP B27 SDVO INTN A20 VCC AG22 PCIE_ICOMPI B23 SDVO_INTP B21 VCC AG24 PCIE ICOMPO B25 SDVO REDN A16 VCC180 P17 PCIE PERN 0 B31 SDVO REDP B17 VCC180 R16 PCIE P
9. Symbol Parameter Min Max Unit Notes The non operating device storage TSTORAGE EE j S 25 125 C 1 2 3 1 The ambient storage temperature SUSTAINED limit in shipping media for a 5 40 OC 4 5 STORAGE sustained period of time RH The maximum device storage SUSTAINED relative humidity for a sustained 60 24 C 5 6 StORAGE period of time A prolonged or extended period of TIMESUSTAINED time typically associated with 0 6 month 6 STORAGE customer shelf life Vcc Processor Core Supply Voltage 0 5 2 1 V North Cluster Logic and Graphics VN Supply Voltage 0 5 2l V 1 05 V Supply Voltage DMI Fuses Vccp DDR digital DPLL PCle 10 SDVO 0 5 2 1 V DPLL SDVO pads HPLL Vccpsus 1 05 V Core Suspend Rail 0 5 2 1 VLVD_VBG 1 25 V LVDS External Voltage Ref 0 5 2 1 1 5 V Sensors Core PLL Core Veca Thermal Sensors Voltages 0 5 AT M 1 8 V Supply Voltage LVDS Digital Vccp180 Analog DDR I O super filter 0 3 2 3 V regulators Vccp180SR 1 8V Supply Voltage DDR SR 0 3 2 3 V 3 3 V Supply Voltage Legacy 10 Vccp33 SDVO pads RTC well 0 5 4 6 v 3 3 V Supply Voltage Suspend Vcce3asus Power SE ge Susp 0 5 4 6 V VMM 1 05 V Supply Voltage 0 5 2 1 V Notes 1 Refer to a component device that is not assembled in a board or socket that is not to be electrically 2 3 connected to a voltage reference or I O signals Specified temperatures are based on data collected Exceptions for surface mount reflo
10. Table 265 92h B2h D2h F2h ISDOFMT ISD1FMT OSDOFMT OSD1FMT Input Output Stream Descriptor 0 1 Format Register Sheet 2 of 2 Size 16 bit Default 0000h Power Well Core Access DE 0 27 Offset Start 92h B2h D2h F2h PCI Configuration B D F 0 27 0 Offset End 93h B3h D3h F3h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description Sample Base Rate Multiple 000 48 kHz 44 1 kHz or less 001 x2 96 kHz 88 2 kHz 32 kHz 13 11 000b RW MULT 010 x3 144 kHz 011 x4 192 kHz 176 4 kHz 100 111 Reserved Sample Base Rate Divisor 000 Divide by 1 48 kHz 44 1 kHz 001 Divide by 2 24 kHz 22 05 kHz 010 Divide by 3 16 kHz 32 kHz 10 08 000b RW DIV 011 Divide by 4 11 025 kHz 100 Divide by 5 9 6 kHz 101 Divide by 6 8 kHz 110 Divide by 7 111 Divide by 8 6 kHz 07 0 RO RSVD Reserved Bits per Sample 000 8 bits The data will be packed in memory in 8 bit containers on 16 bit boundaries 001 16 bits The data will be packed in memory in 16 bit containers on 16 bit boundaries 010 20 bits The data will be packed in memory in 32 bit containers on 06 04 000b RW BITS 32 bit boundaries 011 24 bits The data will be packed in memory in 32 bit containers on 32 bit boundaries 100 32 bits The data will be packed in memory in 32 bit containers on 32 bit boundaries Others Reserved Number of Channels Number of channels in each frame of the stream 0000 21 03 00 00
11. Bit Range Default Access Acronym Description 31 16 0 RO RSVD Reserved 15 0 RO PMES e Status This indicates that a PME was received on the downstream 14 09 0 RO RSVD Reserved Intel Atom Processor E6xx Series Datasheet 131 m e n tel PCI Express Table 170 Offset A4h PMCS PCI Power Management Control And Status Sheet 2 of 2 Size 32 bit Default 00000000h Power Well Core Access e TS Offset Start A4h PCI Configuration B D F 0 23 26 0 Offset End A7h Bit Range Default Access Acronym Description PME Enable The root port takes no action on this bit but it must be RW 08 0 RW PMEE for legacy Microsoft operating systems to enable PME on devices connected to this root port 07 02 0 RO RSVD Reserved Power State This field is used both to determine the current power state of the root port and to set a new power state The values are 00 DO state 01 00 00 RW PS 11 Dor state When in D3yor the port s configuration space is available but 1 0 memory and type 1 configuration cycles are not accepted Interrupts are blocked as software disables interrupts prior to placing the port into D3hor Writes of 10 or 01 are ignored 8 2 5 Port Configuration Table 171 Port Configuration Start End Symbol Register Name D8 DB MPC Miscellaneous Port Configuration DC DF SMSCS SMI SCI Status Intel Atom Pr
12. Size 8 bit Default 00h Power Well Core Access e Offset Start 00h PCI Configuration B D F Offset End 00h Bit Range Default Access Acronym Description Command Indicates the command the processor is to perform If enabled the processor will generate an interrupt or SMI when the command has completed If a reserved command is issued the processor will set HSTS DE and perform no command and will not operate until HSTS DE is cleared Bits Command Description 000 Quick Uses TSA 001 Byte Uses TSA and CMD registers TSA R determines the direction Byte Data Uses TSA CMD and HDO registers 010 TSA R determines the direction If a read HDO will contain the read data Word Data Uses TSA CMD HDO and HD1 011 registers TSA R determines the direction If a 02 00 0 RW CMD read HDO and HD1 contain the read data Process Call Uses TSA HCMD HDO and HD1 100 registers TSA R determines the direction Upon completion HDO and HD1 contain the read data Block Uses TSA CMD HDO and HBD registers For writes the count is stored in HDO and indicates how many bytes of data will be transferred For reads the count is received and 101 stored in HDO TSA R determines the direction For writes data is retrieved from the first n where n is equal to the specified count addresses of HBD For reads the data is stored in HBD 110 Reserved 111 Reserved
13. A 13 RO RO RO RO RO RO RO RO A 12 BO BO BO BO BO BO BO BO A 11 C9 C9 C9 C9 C9 C9 C9 C9 A 10 C8 C8 C8 C8 C8 C8 C8 C8 A 9 C7 C7 C7 C7 C7 C7 C7 C7 A 8 C6 C6 C6 C6 C6 C6 C6 C6 A 7 C5 C5 C5 C5 C5 C5 C5 C5 A 6 C4 C4 C4 C4 C4 C4 C4 C4 AIS C3 C3 C3 C3 C3 C3 C3 C3 ALA C2 C2 C2 C2 C2 C2 C2 C2 A 3 C1 C1 C1 C1 C1 C1 C1 C1 A 21 CO CO CO CO CO CO CO CO Notes 1 R Row Address bit 2 C Column Address bit 3 B Bank Select bit M_BS 2 0 4 RS Rank select If RS 0 then Chip Select bit M_CS 0 If RS 1 the Chip Select bit M_CS 1 88 Intel Atom Processor E6xx Series Datasheet 74 Bm e Graphics Video and Display n tel 7 0 Graphics Video and Display Jad Chapter Contents This chapter contains the following information Overview 3D Core Key Features Video Encode Overview Video Decode Overview Display Overview Register Description 7 2 Overview The Intel Atom Processor E6xx Series contains an integrated graphics engine video decode and encode capabilities and a display controller that can support one LVDS display and one SDVO display see Figure 5 Figure 5 Graphics Unit Intel Atom Processor E6xx Series Core Processor Memory Controller Graphics Unit 2D and Display Controller Pipe A amp B Video Video 3D Graphics Encoder Decoder LVDS Panel 7 2 1 3D
14. 145 9 3 1 13 Offset 2Eh SID Subsystem Ldentifler 146 9 3 1 14 Offset 34h CAP PIR Capabilities Pointer Register 146 9 3 1 15 Offset 3Ch INTLN Interrupt Line Register 146 9 3 1 16 Offset 3Dh INTPN Interrupt Pin Register 147 9 3 1 17 Offset 40h HDCTL Intel High Definition Audio Control e inti ME EE 147 9 3 1 18 Offset 4Ch DCKCTL Docking Control Register 147 9 3 1 19 Offset 4Dh DCKSTS Docking Status Register 148 9 3 1 20 Offset 50h PM CAPID PCI Power Management Capability ID hieu geseet BE ge EE Ee EE 148 9 3 1 21 Offset 52h PM CAP Power Management Capabilities Register 148 9 3 1 22 Offset 54h PM_CTL_STS Power Management Control And Status aei ELM 149 9 3 1 23 Offset 60h MSI CAPID MSI Capability ID Register 150 9 3 1 24 Offset 62h MSI CTL MSI Message Control Register 150 9 3 1 25 Offset 64h MSI ADR MSI Message Address Register 150 9 3 1 26 Offset 68h MSI DATA MSI Message Data Register 150 9 3 1 27 Offset 70h PCIE CAPID PCI Express Capability Identifiers e EE 151 Intel Atom Processor E6xx Series Datasheet 7 i n tel j Contents 9 3 1 28 Offset 72h PCIECAP PCI Express Capabilities Register 151 9 3 1 29 Offset 74h DEVCAP Device Capabilities Register 151 9 3 1 30 Offset
15. 231 337 OBh Register B General Confiouration eese nns 232 338 OCh Register C Flag Register 233 339 ODh Register D Flag Register RTC Well 233 340 GPIO O Register ioc I noted aide dE dE EE EE FEE PEU REN MERE 234 341 00h CGEN Core Well GPIO Enable Immer 234 342 04h CGIO Core Well GPIO Input Output Select cece ee mes 235 343 08h CGLVL Core Well GPIO Level for Input or Output 235 344 OCh CGTPE Core Well GPIO Trigger Positive Edge Enable s sese 235 345 10h CGTNE Core Well GPIO Trigger Negative Edge Enable o ooooccccocccncocnccccncnnnnnnnnnns 236 346 14h CGGPE Core Well GPIO GPE Enable sssssssesssee memes 236 347 18h CGSMI Core Well GPIO SMI Enable mme ee teense eaten nana 236 348 1Ch CGTS Core Well GPIO Trigger Status 237 349 Resume Well GPIO Registers ocococccccnccoconocconnnnncnnnnnnnnnncnnnnnr mmeme sessi NEEESE REEERE 237 350 20h RGEN Resume Well GPIO Enable mmm 237 351 24h RGIO Resume Well GPIO Input Output Select 238 352 28h RGLVL Resume Well GPIO Level for Input or Output 238 353 2Ch RGTPE Resume Well GPIO Trigger Positive Edge Enable oooooococnocccccnccccncnnnnnnnnos 239 354 30h RGTNE Resume Well GPIO Trigger Negative Edge Enable e 239 355 34h RGGPE Resume Well GPIO GPE Enable mms 239 356 38h RGSMI Resume Well GPIO SMI Enable ms 240 357 3Ch RGTS Resume Well GPIO Trigger Status 240 358 SMBus Controll
16. Memory Mapped IO BAR GPIO_BAR 10 Offset Bit Range Default Access Acronym Description 31 05 0 RO RSVD Reserved Trigger Enable When set the corresponding GPIO if enabled as input via GIO IO n will case an SMI SCI when a 1 to 0 transition occurs 04 00 0 RW TE When cleared the GPIO is not enabled to trigger an SMI SCI on a 1 to 0 transition This bit has no meaning if GIO IO n is cleared i e programmed for output 11 7 1 6 Offset 14h CGGPE Core Well GPI O GPE Enable Table 346 14h CGGPE Core Well GPI O GPE Enable Size 32 bit Default 00000000h Power Well Core Access D E 0 31 Offset Start 14h PCI Configuration B D F 0 31 0 Offset End 17h Memory Mapped IO BAR GPIO_BAR 10 Offset Bit Range Default Access Acronym Description 31 05 0 RO RSVD Reserved 04 00 00 RW EN Enable When set when CGTS TS n is set the ACPI GPEOS GPIO bit will 11 7 31 7 Offset 18h CGSMI Core Well GPI O SMI Enable Table 347 18h CGSMI Core Well GPI O SMI Enable Size 32 bit Default 00000000h Power Well Core Access D E 0 31 Offset Start 18h PCI Configuration B D F 0 31 0 Offset End 1Bh Memory Mapped IO BAR GPIO BAR 10 Offset Bit Range Default Access Acronym Description 31 05 0 RO RSVD Reserved 04 00 00 RW EN p When set when CGTS TS n is set the ACPI SMIS GPIO bit will Intel Atom Processor E6xx Series Datasheet 236 ACPI Devices
17. 105 Intel Atom Processor E6xx Series Datasheet 5 Contents 7 7 2 8 Offset 14h IOBAR I O Base Address cceceeeee cette eee eee tees 106 7 7 2 9 Offset 2Ch SS Subsystem Identifiers 1 0 0 0 cece eee eee eee ee 106 7 7 2 10 Offset 34h CAP PTR Capabilities Pointer sse 106 7 7 2 11 Offset 3Ch INTR Interrupt Information 106 7 7 2 12 Offset 58h SSRW Software Scratch Read Write 107 7 7 2 13 Offset 60h HSRW Hardware Scratch Read Write 107 7 7 2 14 Offset 90h MID Message Signaled Interrupts Capability 107 7 7 2 15 Offset 92h MC Message Control 107 7 7 2 16 Offset 94h MA Message Address 108 7 7 2 17 Offset 98h MD Message Data 108 7 7 2 18 Offset C4h FD Functional Disable cece erre 108 7 7 2 19 Offset EOh SWSCISMI Software SCI SMI siseses 109 7 7 2 20 Offset E4h ASLE System Display Event Register 109 7 7 2 21 Offset FOh GCR Graphics Clock Ratio 109 7 7 2 22 Offset F4h LBB Legacy Backlight Briobtness 110 8 0 PCI EXpresS iii ir ii ti a 111 ST Functional Description i oreet ie 111 8 1 1 Interrupt Generationi icit merenti id at odian 111 8 1 2 Power Management miii it 111 8 1 2 1 Sleep State Support eere terme da ia 111 8 1 2 2 Resuming from Suspended Grate cancere 111 8 1 2 3 Device Initiated PM PME Message sssseen rra 111 8 1 2 4 SMI SCI G
18. Size 8 bit Default 01h Power Well Core Access e y Offset Start Eh PCI Configuration B D F 0 23 26 0 Offset End Eh Bit Range Default Access Acronym Description e Header Type Register Returns 01h to indicate that this is a single 07 00 Sh RO HDR function device with a bridge header layout 8 2 1 9 PBN Primary Bus Number This register identifies that this virtual Host PCI Express bridge is connected to PCI bus 0 Table 135 Offset 18h PBN Primary Bus Number Size 8 bit Default 00h Power Well Core Access AEA Offset Start 18h PCI Configuration B D F 0 23 26 0 Offset End 18h Bit Range Default Access Acronym Description Primary Bus Number Configuration software typically programs this 07 00 00h RW PBN field with the number of the bus on the primary side of the bridge Since the device is an internal device its primary bus is always 0 8 2 1 10 SCBN Secondary Bus Number This register identifies the bus number assigned to the second bus side of the virtual bridge in other words to the PCI Express device This number is programmed by the PCI configuration software to allow mapping of configuration cycles to the PCI Express device Intel Atom Processor E6xx Series Datasheet 116 PCI Express n tel Table 136 Offset 19h SCBN Secondary Bus Number Size 8 bit Default 00h Power Well Core
19. 9 3 1 46 Offset 140h L1DESC Link 1 Description Register Table 223 140h L1DESC Link 1 Description Register Size 32 bit Default 0000_0001 Power Well Core Access d D F 0 27 Offset Start 140h PCI Configuration B D F 0 27 0 Offset End 143h Bit Range Default Access Acronym Description Target Port Number The Intel HD AudioP controller targets the 31324 00h RO TRORT processor RCRB egress port which is port BO Target Component ID This field returns the value of the ESD COMPID 23 16 Variable RO TCOMPID field of the chip configuration section ESD COMPID is programmed by BIOS 15 02 Oh RO RSVD Reserved 01 0 RO LNKTYP Link Type Indicates Type 0 00 1 RO LNKVLD Link Valid Hardwired to 1 9 3 1 47 Offset 148h LLADD Link 1 Address Register Table 224 148h L1ADD Link 1 Address Register Size 32 bit Default Variable Power Well Core ASS PCI Configuration B D F 0 27 0 SE er Bit Range Default Access Acronym Description 31 14 Variable RW poss E PC tudes 31 ton d to match the RCBA register value in the PCI 13 00 Oh RO RSVD Reserved 9 3 2 Memory Mapped Configuration Registers 9 3 2 1 Intel HD Audio Registers The base memory location for these memory mapped configuration registers is specified in the LBAR and UBAR D27 FO offset 10h and D27 FO offset 14h registers The individual registers are then accessible at LBA
20. 11 8 2 2 Offset O1h HSTS Host Status Register Table 360 01h HSTS Host Status Register Size 8 bit Default 00h Power Well Core Access e T Offset Start 01h PCI Configuration B D F Offset End 01h Bit Range Default Access Acronym Description 07 04 0 RO RSVD Reserved 03 0 RO BSY Busy When set indicates the processor is running a command No SMB registers should be accessed while this bit is set 02 0 RWC BE Bus Error When set indicates a transaction collision Device Error When set this indicates one of the following Illegal 01 0 RWC DE Command Field an unclaimed cycle or a time out error Completion Status When BSY is cleared if this bit is set the command 00 0 RWC CS completed successfully If cleared the command did not complete successfully Intel Atom Processor E6xx Series Datasheet 242 ACPI Devices I n tel 11 8 2 3 Offset 02h HCLK Host Clock Divider Table 361 02h HCLK Host Clock Divider Size 16 bit Default 0000h Power Well Core Access PCI Configuration B D F EE GE Bit Range Default Access Acronym Description Divider This controls how many legacy backbone clocks should be counted for the generation of SMBCLK Recommended values are listed below SMBus Legacy Backbone Frequency Frequency 33 MHz 1 kHz 208Eh 15 00 0 RW DIV 10 kHz 0342h 50 kHz 00A7h 100 kHz 0054h 400 kHz 0015h 1 MHz 0009h
21. Signal Name Strap Definition STRAP_BOOT_FLASH Defines whether TC boots from SPI or LPC 1 SPI GPIO 0 0 LPC Notes Boot from LPC is not supported STRAP CMC BA 1 0 GPI O 3 2 CMC Base Address defined the address the CMC will start fetching and executing code from 10 OxFFFE0000 eege 11 OxFFFD0000 01 OxFFFCO000 00 OxFFFBO000 STRAP LPCCLK STRENGTH LPC_CLKOUT O Buffer Strength Control Select the drive strength of the LPC CLKOUT O clock GPIO 4 0 1 load driver strength 1 2 load driver strength 2 14 Power and Ground Signals This section provides power and ground signals for the Intel Atom Processor E6xx Series Table 18 Power and Ground Signals Sheet 1 of 2 Signal i x XE Name Nominal Voltage Description VCC 0 75 1 15V SES Core Supply Voltage Power supply is required for processor VNN 0 75 0 9875 V North Cluster Logic and Graphics Supply Voltage VCCP 1 05 V Needed for most bus accesses VCCF 1 05 V Can be connected to VCCP VCCPQ 1 05 V Can be connected to VCCP VCCPDDR 1 05 V DDR DLL and logic Supply Voltage Required for memory bus accesses Requires a separate rail with noise isolation JTAG C6 SRAM Fuse Supply Voltage Needs to be on in Active or VESPA 1 05 V Standby This rail is connected to the VCCP rail VCCQ 1 05 V Connect to 1 05 V LVD VBG 1 25 V LVDS Band Gap Supply Voltage Needed for LVDS display VCCA 1 5 V Core PLL c
22. eere ete ncn Cni capter 27 1 3 2 System Memory Controller ssssssssssssssseenmemene memes 27 13 Wee EE 27 1 3 4 Vid DECO EE 28 1 3 5 Video Encoder qr VERO E E EE ERE AR RE caesarean 28 1 3 6 Display linterfaces crt eee EE ee ere etre bleed eee died 28 1 326 1 LVDS Interface ioo end Ed E AEA A A AUT 28 1 3 6 2 Serial DVO SDVO Display Interface nn 28 1 37 e Wel 28 WE eg e TEE 28 1 3 9 Intel High Definition Audio Intel HD Audio Controller 29 1 3 10 SMBus Host Controller ccc enna nennen 29 1 3 11 General Purposel O GblO erect renee et mnn nennen nne nnn 29 1 3 12 Serial Peripheral Interface bi 29 1 3 13 Power Management es cese KENE KANEEEE EREN KAREN A EE NASA 29 1 3 14 Watchdog Timer WDT cece cere mm emnes 30 1 3 15 Real Time Clock RTC issssseessn emen me eee enhn needs 30 1 3 16 Package oic e aia 30 1 3 17 Intel Atom Processor E6xx Series GK 30 2 0 Signal Description ooo DERI RR EYE RR UR EXE RE EL CURE dE NEE E AR ERR EE 31 2 1 System Memory Siga Sivad Ra RR DESEN EENS EES 32 2 2 Integrated Display Intertaces mmn seems sene memes nens 33 2 20 LVDS SIQNAIS INC 33 2 2 2 Serial Digital Video Output SDVO Signals ssassn 34 2 37 Ge e EE 35 2 4 Intel High Definition Audio Interface Signals ccccccccoconicononononnononnncnnonononononoss 35 2 5 PE Interface SigNalS coi o in 36 2 6 SMBus Interface Signals iste be
23. Size 8 bit Default 00h Power Well Core Access Offset Start 06h PCI Configuration B D F Offset End 06h Bit Range Default Access Acronym Description 07 00 00h RW CMD DataO Data Field 0 11 8 2 7 Offset 07h HD1 Host Data 1 This field is transmitted in the DATA1 field of an SMBus cycle Table 365 07h HD1 Host Data 1 Size 8 bit Default 00h Power Well Core Access e T Offset Start 07h PCI Configuration B D F Offset End 07h Bit Range Default Access Acronym Description 07 00 00h RW CMD Datal Data Field 1 11 8 2 8 Offset 20h 3Fh HBD Host Block Data Table 366 20h 3Fh HBD Host Block Data Size 256 bit Default Oh Power Well Core Access K Offset Start 20h PCI Configuration B D F Offset End 3Fh Bit Range Default Access Acronym Description Data This contains block data to be sent on a block write command or 255 00 0 RW D received block data on a block read command Any data received over 32 bytes will be lost 11 8 3 Overview The host controller is used to send commands to other SMB devices It runs off of the backbone clock with a minimum SMBCLK frequency the backbone clock divided by 4 i e SMBCLK at a minimum is 4 legacy backbone clocks The frequency to use for SMBCLK is chosen by programming HCLK DIV To ensure proper data capture the minimum value to be programmed into this register
24. Value Output Streams OFh 16B 16 20 24 or 32 bit Output Streams 1Fh 32B 16 20 24 or 32 bit Output Streams 3Fh 64B 16 20 24 or 32 bit Output Streams 7Fh 128B 16 20 24 or 32 bit Output Streams BFh 192B 8 16 or 32 bit Output Streams FFh 256B 20 24 bit Output Streams 8 8 8 8 Notes 1 All other values are Not Supported 2 When the output stream is programmed to an unsupported size the hardware sets itself to the default value BFh 3 Software must read the bit field to test if the value is supported after setting the bit field For Input Stream FIFOS is a RO field with the following value 8 16 32 bit Input Streams 120B 77h 20 24 bit Input Streams 160B 9Fh Note the default value is different for input and output streams and reflects the default state of the BITS fields in Stream Descriptor Format registers for the corresponding stream 9 3 2 1 39 Offset DOh FOh OSDOFI FOS OSD1FI FOS Output Stream Descriptor 0 1 FIFO Size Register Table 264 DOh FOh OSDOFI FOS OSD1FI FOS Output Stream Descriptor 0 1 FIFO Size Register Sheet 1 of 2 Size 16 bit Default OOBFh Power Well Core Access D IEQ 27 Offset Start DOh FOh PCI Configuration B D F 0 27 0 Offset End D1h Eih Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 15 08 0 RO RSVD Reserved Intel
25. 1 Fast Read Protocol is not supported 2 The Auto Address Increment type is not supported SPI Timings The SPI interface is designed to fall within the following protocol timing specs These specs are intended to operate with most SPI Flash devices SPI Cycle Timings Parameter Minimum Value Description SPI_CS Setup 30 ns SPI_CS low to SPI_SCK high SPI_CS Hold 30 ns SPI_SCK low to SPI_CS low Clock High 20 ns Time that SPI_SCK is Driven high per clock period Clock Low 30 ns Time that SPI_SCK is Driven Low per clock period Host Side I nterface SPI Host I nterface Registers The SPI Host Interface are memory mapped in the RCRB Chipset Memory Space in range 3020h to 308Fh Address locations that are not listed are considered reserved register locations Reads to reserved registers may return non zero values Writes to reserved locations may cause system failure The table below does NOT include the 3020h offset Intel Atom Processor E6xx Series Datasheet 249 i n tel j ACPI Devices Table 372 Bus O Device 31 Function 0 PCI Register Mapped Through RCBA BAR Offset Start Offset End Register ID Description Default Value 3020h 3021h Offset 00h SPIS SPI Status 0001h 3022h 3023h Offset 02h SPIC SPI Control 2005h 3024h 3027h Offset 04h SPIA SPI Address O0XXXXXh 3028h 302Bh Offset 08h SPIDO SPI Data 0 XXXXXXXXh 3030h at 4h 306C
26. 216 11 3 2 8 Offset 4DOh ELCR1 Master Edge Level Control 217 11 3 2 9 Offset 4D1h ELCR2 Slave Edge Level Control 218 13 3 3 Interrupt Handli innt rd et Rx dE Re EE e 218 11 3 3 1 GONE cari ecb aid weeded ended eri BERE EAR 218 11 3 3 2 Acknowledgirig ii ern er exe SER dE EE REES dE 218 11 3 3 3 Hardware Software Interrupt Geouence 219 11 3 4 Initialization Command Words ICW seesseemHenmmnnn 219 11 3 4 T Ke E 219 11 3 4 2 De eese tinea enrages ert pese Pa er HEC P pO HERR A FEE Rer 220 TESA CWS DEL 220 UN BAA OCW EE 220 11 3 5 Operation Command Words OCH 220 11 3 60 Modes of OperatiOn eo rete rte eter ko a dise 220 11 3 6 1 Fully Nested Mode 220 11 3 6 2 Special Fully Nested Mode 221 Intel Atom Processor E6xx Series Datasheet 9 n tel j Contents 11 7 11 3 6 3 Automatic Rotation Mode Equal Priority Devices ssss 221 11 3 6 4 Specific Rotation Mode Specific Priority ssssesseseess 221 11 3 6 5 Poll Mode iiec t ertet rer sione edes deeds ceed 221 11 3 6 6 Edge and Level Triggered Mode 222 11 3 7 End Of Interrupt EOI cece ccc reer nemen 222 113 21 NormalEOL i3 rt ete due d AER Eed dE 222 11 3 7 2 Automatic TEE 222 11 3 9 Masking Interr pts ui ie oo SEENEN SERA NO ORE RUE 222 11 3 8 1 Masking on an Individual Interrupt Request s c 222 11 3 8 2 Special Mask Mode 222
27. Update dt 324209 pdf Intel Atom Processor E6xx Series Thermal and http download intel com embedded processor designg Mechanical Design Guidelines uide 324210 pdf Low Pin Count Interface Specification Revision 1 1 http developer intel com design chipsets industry lpc LPC htm PCI Express Base Specification Rev 1 0a http www pcisig com specifications System Management Bus Specification Version http www smbus org specs 1 0 SMBus Notes 1 Contact your Intel Field Representative for the latest version of this document Intel Atom Processor E6xx Series Datasheet 25 intel 1 3 Components Overview The Intel Atom Processor E6xx Series incorporates a variety of PCI functions as listed in Table 1 Table 1 PCI Devices and Functions Device Function Function Description 0 0 Host Bridge 2 0 Integrated Graphics and Video Device 3 0 SDVO Display Unit 23 0 PCI Express Port 0 24 0 PCI Express Port 1 25 0 PCI Express Port 2 26 0 PCI Express Port 3 27 0 Intel High Definition Audio Intel HD AudioP Controller 31 0 LPC interface Note All devices are on PCI Bus 0 Figure 2 Components of the Intel Atom Processor E6xx Series Intel Atom Processor E6xx Series Datasheet 26 inte 1 3 1 Low Power Intel Architecture Core 600 MHz Ultra Low Power SKU 1 0 GHz Entry SKU 1 3 GHz Mainstream S
28. VID 6 0 1 0 CMOS Core Voltage I D Indicates a desired voltage for either VCC or the VNN depending on the VIDEN pins Resolution of 12 5 mV according to the Intel MVP 6 spec Intel Atom Processor E6xx Series Datasheet 40 Table 15 Signal Description intel Miscellaneous Signals and Clocks Sheet 3 of 4 s Direction Power Pee Signal Name Type Well Description Voltage I D Enable Indicates which voltage is being specified on the VID pins O 00 VID is Invalid VIDENLI 9 CMOS Core 01 VID vcc 10 VID Vnn 11 Unused l TEST When asserted component is put into TEST modes TEST_B CMOS3 3 SUS combinatorially RCOMP A Core Connect 249 Q resistor to 1 05 V 1 0 CMOS VREF I OCMREF A Core 1 kQ 1 pullup to VIPO5 S and 1 KQ 1 pull down to GND 1 0 IOCOMP1 0 externally connects to 18 2 Q resistor 1 to Vss IOCOMP1 1 0 C l A ore OCOMP1 1 externally connects to 35 7 Q resistor 1 to Vss 1 0 IOCOMPO 0 externally connects to 27 4 Q resistor 1 to Vss IOCOMPO 1 0 C l A ore IOCOMPO 1 externally connects to 54 9 Q resistor 1 to Vss 1 0 CMOS VREF IO RX CVREF A Core 510 Q 596 pullup to VIPO5 S and 1 KQ 1 pull down to GND 1 0 GTL VREF 10_RX_GVREF A Core 510 Q 5 pullup to VIPO5 S and 1 KQ 1 pull down to GND Connect to VCCP DLIOCMREF P Core 1kQ x 196 pullup to VIPO5 S and 2 kQ 1 pull down to o
29. sess emen 237 Intel Atom Processor E6xx Series Datasheet 10 Contents 11 7 2 1 Offset 20h RGEN Resume Well GPIO Enable 237 11 7 2 2 Offset 24h RGIO Resume Well GPIO Input Output Select 238 11 7 2 3 Offset 28h RGLVL Resume Well GPIO Level for Input or Output 238 11 7 2 4 Offset 2Ch RGTPE Resume Well GPIO Trigger Positive Edge ele pcm 239 11 7 2 5 Offset 30h RGTNE Resume Well GPIO Trigger Negative Edge dise E 239 11 7 2 6 Offset 34h RGGPE Resume Well GPIO GPE Enable 239 11 7 2 7 Offset 38h RGSMI Resume Well GPIO SMI Enable 240 11 7 2 8 Offset 3Ch RGTS Resume Well GPIO Trigger Status 240 11 7 3 Theory of Operation 240 11 7 3 I Power Wells creer da er eil ed 240 11 7 3 2 SMI and SCI Routing 240 11 7 3 3 OR le Le dee EE 240 11 8 SMBUS Controller cia ee ERR ERRARE CURRERE FAR ie aaa 241 RI Oe Dt e aici PETS 241 11 8 2 I O Registers ia UR DRE RR PROV EE EE Ee 241 11 8 2 1 Offset 00h HCTL Host Control Register 241 11 8 2 2 Offset O1h HSTS Host Status Register 242 11 8 2 3 Offset 02h HCLK Host Clock Divider ereere 243 11 8 2 4 Offset 04h TSA Transmit Slave Address 243 11 8 2 5 Offset 05h HCMD Host Command Register 243 11 8 2 6 Offset 06h HDO Host Data 244 11 8 2 7 Offset 07h HD1 Host Data l mmn 244 11 8 2 8 Offset 20h 3Fh HBD
30. 183 269 1008h OUTRC Output Stream Repeat Count Register 183 270 100Ch FIFOTRK FIFO Tracking Register 184 271 1010h 1014h 1020h 1024h IODPIB I1DPIB OODPIB O1DPIB Input Output Stream Descriptor 0 1 DMA Position in Buffer Register 184 272 1030h EM2 Extended Mode 2 Register 185 273 2030h WLCLKA Wall Clock Alias Register 185 274 2084h 20A4h 2104h 2124h ISDOLPIBA ISDILPI BA OSDOLPIBA OSD1LPIBA Input Output Stream Descriptor 0 1 Link Position in Buffer Alias Register 186 275 LPC Interface PCI Register Address Map 188 276 Offset 00h ID Identifiers tere Eee teria rece saa aia aeris ala s 188 277 Offset 04h CMD Device Commande 189 278 Offset 06h STS Device Status 189 279 Offset 08h RID Revision ID 189 280 Offset 09h CC Class Code ica teet nadie rp o eia iter err te de a FORE 190 281 Offset OEh HDTYPE Header Tvpe ene memes ener 190 282 Offset 2Ch SS Subsystem Identifiers sssssssssssssssssseeme memes 190 283 Offset 40h SMBA SMBus Base Address ssssssssssssssseeneeme nemen 191 284 Offset 44h GBA GPIO Base Address 191 285 Offset 48h PM1BLK PM1 BLK Base Address 191 286 Offset 4Ch GPEOBLK GPEO BLK Base Address 192 287 Offset 54h LPCS LPC Clock Strength Control 192 288 Offset 58h ACTL ACPI Control 193 289 Offset 5Ch MC Miscellaneous Control 193 290 Offset 60h 67h PxRC PIRQ A H Routing Control 195 291 Offs
31. 6 A minimum of four HDA CLKs after HDA DOCKRST B the controller will de aren HDA DOCK EN B to isolate the dock codec signals from the Intel HD AudioP link signals HDA DOCK EN B is de asserted synchronously to HDA CLK and timed such that HDA CLK HDA SYNC and HDA SDO are low 7 After this hardware undocking sequence is complete the controller hardware clears the DCKSTS DM bit to 0 indicating that the dock is now un mated ACPI BIOS software polls DCKSTS DM and when it sees DM set conveys to the end user that physical undocking can proceed The controller is now ready for a subsequent docking event Relationship Between HDA DOCKRST B and HDA RST B HDA RST B will be asserted when a RESET B occurs or when the CRST B bit is 0 As long as HDA RST B is asserted the HDA DOCKRST B signal will also be asserted When RESET B is asserted the DCKCTL DA and DCKSTS DM bits will be get cleared to their default state 0 s and the dock state machine will be reset such that HDA DOCK EN B will be de asserted and HDA DOCKRST B will be asserted After any RESET B POST BIOS software is responsible for detecting that a dock is attached and then writing a 1 to the DCKCTL DA bit prior to the Intel HD Audio Bus Driver de asserting CRST B When CRST B bit is O asserted the DCKCTL DA bit is not cleared The dock state machine will be reset such that HDA DOCK EN B will be de asserted HDA DOCKRST B will be asserted and the DCKSTS DM bit
32. IAF Base Address Base 10 Offset 15h Bit Range Default Access Acronym Description Down Counter 15 8 The Down Counter register holds the bits 8 through 15 of upper 20 bits of the 35 bit down counter that is continuously decremented The values from Preload Registers are loaded 07 00 00h RO DCNT_15_8 into the Down Counter every time the WDT enters stage The down counter decrements using a 33 MHz clock Any reads to this register return an indeterminate value This register is to be indicated as reserved 11 10 3 12 Offset 16h DCR2 Down Counter Register 2 Table 399 16h DCR2 Down Counter Register 2 Size 8 bit Default 00h Power Well Core WE PCI Configuration B D F Offset Start Th Offset End 16h IAF Base Address Base 10 Offset 16h Bit Range Default Access Acronym Description 07 04 Oh Reserved Reserved Down Counter 19 16 The Down Counter register holds the bits 16 through 19 of upper 20 bits of the 35 bit down counter that is continuously decremented The values from Preload Registers are loaded 03 00 Oh RO DCNT 19 16 into the Down Counter every time the WDT enters the stage The down counter decrements using a 33 MHz clock Note Any reads to this register return an indeterminate value This register is to be indicated as reserved 11 10 3 13 Offset 18h WDTLR WDT Lock Register Table 400 18h WDTLR WDT Lock Register Sheet 1 of 2 Size 8 b
33. Intel Atom Processor E6xx Series Datasheet 192 LPC Interface D31 FO Table 287 Offset 54h LPCS LPC Clock Strength Control Sheet 2 of 2 Size 32 bit Default Power Well Access en Offset Start 54h PCI Configuration B D F X 31 0 Offset End 57h Bit Range Default Access Acronym Description 00 Strap RW COAM Clock 0 4m Strength Clock 0 4m Strength Control 10 3 6 ACTL ACPI Control Register Table 288 Offset 58h ACTL ACPI Control Size 32 bit Default 00000003h Power Well Access EE Offset Start 58h PCI Configuration B D F X 31 0 Offset End 5Bh Bit Range Default Access Acronym Description 31 03 Oh RO RSVD Reserved SCI IRQ Select This field specifies on which IRQ SCI will rout to If not using APIC SCI must be routed to IRQ9 11 and that interrupt is not sharable with SERIRQ but is shareable with other interrupts If using APIC SCI can be mapped to IRQ20 23 and can be shared with other interrupts Bits SCI Map Bits SCI Map 000 IRQ9 100 IRQ20 02 00 011b RW SCIS 001 IRQ10 101 IRQ21 010 IRQ11 110 IRQ22 011 SCI Disabled 111 IRQ23 When the interrupt is mapped to APIC interrupts 9 10 or 11 APIC must be programmed for active high reception When the interrupt is mapped to APIC interrupts 20 through 23 APIC must be programmed for active low reception 10 3 7 MC Miscellaneo
34. SLPMODE O CMOS3 3 sus Sleep Mode SLPMODE determines which sleep state is entered When SLPMODE is high S3 will be chosen When SLPMODE is low S4 S5 will be the selected sleep mode RSTWARN l CMOS3 3 SUS Reset Warning Asserting the RSTWARN signal tells the chip to enter a sleep state or begin to power down A system management controller might do so after an external event such as pressing of the power button or occurrence of a thermal event SLPRDY_B O CMOS3 3 sus Sleep Ready The processor will drive the SLPRDY_B signal low to indicate to the system management controller that the processor is awake and able to placed into a sleep state Deassertion of this signal indicates that a wake is being requested from a system device RSTRDY_B CMOS3 3 sus Reset Ready Assertion of the RSTRDY_B signal indicates to the system management controller that it is ready to be placed into a low power state During a transition from SO to S3 4 5 sleep states the chip asserts RSTRDY_B and CPURST_B after detecting assertion of the RSTWARN signal from the external system management controller GPE_B CMOS3 3 OD SUS General Purpose Event GPE B is asserted by an external device typically the system management controller to log an event in the chip s ACPI space and cause an SCI if enabled Intel Atom Processor E6xx Series Datasheet 37 intel 2 9 Table 13 2 10
35. Table 14 Signal Description Real Time Clock I nterface Signals Real Time Clock Interface Signals Direction Power ees Signal Name Type Well Description Special Crystal Input 1 This signal is connected to the 32 768 kHz RTCX1 F RTC crystal If no external crystal is used then RTCX1 can be driven with the desired clock rate Special Crystal Output 2 This signal is connected to the 32 768 RTCX2 p RTC kHz crystal If no external crystal is used then RTCX2 should be left floating l VCCRTCEXT Power RTC External capacitor connection JTAG and Debug I nterface The JTAG interface is accessible only after PWROK is asserted JTAG and Debug I nterface Signals Direction Power Signal Name Type Well Description TCK Core CPU J TAG Test Clock Provides the clock input for the CMOS processor Test Bus also known as the Test Access Port CPU J TAG Test Data Input Transfers serial test data into TDI CMOS Core the processor TDI provides the serial input needed for J TAG specification support o CPU J TAG Test Data Output Transfers serial test data out TDO Core of the processor TDO provides the serial output needed for CMOS OD T JTAG specification support TMS Core CPU J TAG Test Mode Select A J TAG specification support CMOS signal used by debug tools CPU J TAG Test Reset Asynchronously resets the Test TRST B Core Access Port TAP
36. Table 185 ODh LT Latency Timer Register Size 8 bit Default 00h Power Well Core Access D E 0 97 Offset Start ODh PCI Configuration B D F 0 27 0 Offset End ODh Bit Range Default Access Acronym Description 07 00 00h RO LT Latency Timer Doesn t apply to PCI Express Hardwired to 00h 9 3 1 9 Offset OEh HEADTYP Header Type Register Table 186 OEh HEADTYP Header Type Register Size 8 bit Default 00h Power Well Core Access D E 0 27 Offset Start OEh PCI Configuration B D F 0 27 0 Offset End OEh Bit Range Default Access Acronym Description 07 00 00h RO HEADTYP Header Type Implements Type O Configuration header 9 3 1 10 Offset 10h LBAR Lower Base Address Register This BAR creates 16 Kbytes of memory space to signify the base address of Intel HD AudioP memory mapped configuration registers Intel Atom Processor E6xx Series Datasheet 144 Intel High Definition Audio D27 FO j n tel Table 187 10h LBAR Lower Base Address Register Size 32 bit Default 00000004h Power Well Core Access D F 0 27 Offset Start 10h PCI Configuration B D F 0 27 0 Offset End 13h Bit Range Default Access Acronym Description Lower Base Address Base address for the Intel HD AudioP 31 14 0 RW LBA controller s memory mapped config
37. The SDVO port supports both standard and high definition TV displays in a variety of formats The SDVO port generates the proper blank and sync timing but the external encoder is responsible for generation of the proper format signal and output timings The processor will support NTSC PAL SECAM standard definition formats The processor will generate the proper timing for the external encoder The external encoder is responsible for generation of the proper format signal Flicker Filter and Overscan Compensation The overscan compensation scaling and the flicker filter is done in the external TV encoder chip Care must be taken to allow for support of TV sets with high performance de interlacers and progressive scan displays connected to by way of a non interlaced signal Timing will be generated with pixel granularity to allow more overscan ratios to be supported Control Bus The SDVO port defines a two wire SDVO_CTRLCLK and SDVO_CTRLDATA communication path between the SDVO device and the processor Traffic destined for the PROM or DDC will travel across the control bus and will then require the SDVO device to act as a switch and direct traffic from the control bus to the appropriate receiver The control bus is able to operate at up to 1 MHz Display Pipe B is configured to use the SDVO port The SDVO port can support a variety of display types VGA LVDS DVI TV Out etc by an external SDVO device SDVO devices translate SDVO proto
38. m e Graphics Video and Display n tel 7 4 Table 73 7 4 1 Video Decode The video decode accelerator improves video performance power by providing hardware based acceleration at the macroblock level variable length decode stage entry point The Intel Atom Processor E6xx Series supports full hardware acceleration of the following video decode standards Hardware Accelerated Video Decoding Support Codec Profile Level Note H 264 Baseline profile L3 e L4 1 H 264 Main profile 1080p O 30 fps e e L4 1 H 264 High profile 1080p O 30 fps MPEG2 Main profile High MPEG4 Simple profile L3 MPEG4 Advanced simple profile L5 VC1 Simple profile Medium VC1 Main profile High A L3 up to VC1 Advanced profile 1080p G 30 fps WMV9 Simple profile Medium WMV9 Main profile High Video Decode is performed in four processing modules which are described in the following sections Entropy coding processing Motion compensation Deblocking Final pixel formatting Entropy Coding The entropy encoding module serves as the master controller for the video accelerator The master data stream control and bitstream parsing functions for the macroblock level and below are performed here Required control parameters are sent to the motion compensation and deblocking modules The macroblock bit stream parsing performs the entropy encoding functions for VLC CALVC and CABAC tech
39. 142 Offset 22h 143 Offset 24h 144 Offset 26h 145 Offset 34h 146 Offset 3Ch 147 Offset 3Dh 148 Offset 3Eh 150 Offset 40h 151 Offset 42h 152 Offset 44h 153 Offset 48h 154 Offset 4Ah 155 Offset 4Ch 156 Offset 50h 157 Offset 52h 158 Offset 54h 159 Offset 58h 160 Offset 5Ah 161 Offset 5Ch 162 Offset 5Eh HDR Header KEE 105 MMADR Memory Mapped Base Address sssssssesee 105 OBAR UO Base Address ee ssec a cusa etaient e E da der edad 106 CAP PTR Capabilities Pointer ANNER 106 INTR Interrupt Information 12 0 0 cece eee eee eee ee memes rens 106 SSRW Software Scratch Read Wrtte cece eee eee mee 107 HSRW Hardware Scratch Read Write cence ee eee eee neta teen een ene es 107 MID Message Signaled Interrupts Capability sese 107 MC Message e Tal EE 107 MA Message Address re nnns 108 MD Message Data eee tree emn E Ie en RARE KA ER ANETA AAA 108 ED Functional Disable cnica 108 SWSCISMI Software SCI SMI sssssssssssmmemmemememmemenrenes 109 ASLE System Display Event Register 109 GCR Graphics Clock Ratio nares bre tr te ia 109 LBB Legacy Backlight Brightness ococccoccccccoconcnnnnoroncnnnnnnnnrnnnnnnnnnn naar 110 125 MSI vs PCI IRQ AcHons cece HH ENRERE AEE REEERE EPEE INI EEEE aE 111 nr 112 VID Vendor Identification meme enn 113 DID Device Identification sss menm 114 CMD PCI Command esee cade EEN
40. 7 00 0 RV RSVD Reserved 11 9 5 8 Offset 54h PREOP Prefix Opcode Configuration This register is not writable when the SPI Configuration Lock Down bit in Offset 00h SPIS SPI Status register is set Intel Atom Processor E6xx Series Datasheet 253 i n tel i ACPI Devices Table 379 54h PREOP Prefix Opcode Configuration Size 16 bit Default 0004h Power Well Core Access e TT MESE Offset Start 3074h PCI Configuration B D F 0 31 0 Offset End 3075h Memory Mapped IO BAR RCBA Offset Bit Range Default Access Acronym Description Prefix Opcode 1 Software programs an SPI opcode into this field that is 15 08 0 RWS PO1 permitted to run as the first command in an atomic cycle sequence a Prefix Opcode 0 Software programs an SPI opcode into this field that is 7 00 04h RWS POO permitted to run as the first command in an atomic cycle sequence 11 9 5 9 Offset 56h OPTYPE Opcode Type Configuration This register is not writable when the SPI Configuration Lock Down bit in Offset 00h SPIS SPI Status register is set Entries in this register correspond to the entries in the Offset 58h OPMENU Opcode Menu Configuration register Note that the definition below only provides write protection for opcodes that have addresses associated with them Therefore any erase or write opcodes that do not use an address should be avoided for ex
41. Atom Processor E6xx Series Datasheet 71 intel Memory Controller 6 7 Supported DRAM Devices Table 69 Supported DDR2 DRAM Devices DRAM Density Data Width Banks Bank Address Row Address Column Address Page Size 256 Mb x8 4 BA 1 0 MA 12 0 MA 9 0 1 kB 512 Mb x8 4 BA 1 0 MA 13 0 MA 9 0 1 kB 1 Gb x8 8 BA 2 0 MA 13 0 MA 9 0 1 kB 2 Gb x8 8 BA 2 0 MA 14 0 MA 9 0 1 kB 512 Mb x16 4 BA 1 0 MA 12 0 MA 9 0 2 kB 1 Gb x16 8 BA 2 0 MA 12 0 MA 9 0 2 kB 2 Gb x16 8 BA 2 0 MA 13 0 MA 9 0 2 kB 6 8 Supported Rank Configurations Table 70 Memory Size Per Rank Memory DRAM DRAM Chip DRAM Chip Banks C Page Page Size O Size Rank Chips Rank Density Data Width hip Size Chip 32 bit Data Bus 4kB 1kBx4 128 MB 4 256 Mb x8 4 1kB Chips 4kB 1kBx4 256 MB 4 512 Mb x8 4 1kB Chips 512 MB 4 1 Gb x8 8 1kB AKB TT BAA ips 4kB 1kBx4 1 GB 4 2 Gb x8 8 1 kB Chips 4kB 2kBx2 128 MB 2 512 Mb x16 4 2 kB Chips 4kB 2kBx2 256 MB 2 1 Gb x16 8 2 kB Chips 4kB 2kBx2 512 MB 2 2 Gb x16 8 2 kB Chips Intel Atom Processor E6xx Series Datasheet 72 Memory Controller 6 9 Table 71 Address Mapping and Decoding intel For any rank the address range it implements is mapped into the physical address regions of the devices on that rank This is addressable by bank B row R and column C addresses Once a rank
42. Disable 1 Enable ame du 000000 RO RSVD Reserved 10 5 3 BC BI OS Control Register Table 295 Offset D8h BC BIOS Control Sheet 1 of 2 Size 32 bit Default 00000100h Power Well Access D FE X 31 Offset Start D8h PCI Configuration B D F X 31 0 Offset End DBh Bit Range Default Access Acronym Description 31 09 Oh RO RSVD Reserved Prefetch Enable 0 Disable 1 Enable BIOS prefetching An access to BIOS causes a 64 byte fetch of the line starting at that region Subsequent accesses 08 1b RW PFE within that region result in data being returned from the prefetch buffer Note The prefetch buffer is invalidated when this bit is cleared or a BIOS access occurs to a different line than what is currently in the buffer 07 03 ee RO RSVD Reserved 02 Ob RW CD Cache Disable Enable caching in read buffer for direct memory read Lock Enable When set setting the WP bit will cause SMIs When cleared setting the WP bit will not cause SMIs Once set this bit can only be cleared by a RESET B 01 Ob RWLO LE 0 Setting the BIOSWE will not cause SMIs 1 Enables setting the BIOSWE bit to cause SMIs Once set this bit can only be cleared by a RESET_B Intel Atom Processor E6xx Series Datasheet 198 LPC Interface D31 FO Table 295 Offset D8h BC BIOS Control Sheet 2 of 2 Size 32 bit Default 00000100h Power Well Access DF X31
43. Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or go to http www intel com Sien US 01 a Intel Hyper Threading Technology requires a computer system with a processor supporting Intel HT Technology and an Intel HT Technology enabled chipset BIOS and operating system Performance will vary depending on the specific hardware and software you use For more information including details on which processors support Intel HT Technology see http www intel com products ht hyperthreading more htm p Intel High Definiti
44. Reserved INTERRUPT PI IPIN Value indicates which interrupt pin this device uses This field is 15 8 Olh RO N 7 hard coded to 1h since the processor Device 2 is a single function device The PCI spec requires that it use INTA a INTERRUPT LI ILIN BIOS written value to communicate interrupt line routing 7 0 00h RW ie A NE information to the device driver Intel Atom Processor E6xx Series Datasheet 95 m e n tel Graphics Video and Display Table 88 50h GVD MGGC Graphics Control Size 32 bit Default 00300000h Power Well Core Access Offset Start 50h PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 14h Bit Range Default Access Acronym Description 31 23 0 RO RESERVED GMS This field is used to select the amount of memory pre allocated to support the graphics device in VGA non linear and Native linear modes If graphics is disabled this value must be programmed to 000h 000 No memory pre allocated Graphics does not claim VGA cycles Mem and 10 and CC SCC is 80h 001 DVMT UMA mode 1 MB of memory pre allocated for frame buffer 010 DVMT UMA mode 4 MB of memory pre allocated for frame buffer 011 DVMT UMA mode 8 MB of memory pre allocated for frame buffer 100 DVMT UMA mode 16 MB of memory pre allocated for frame buffer 101 DVMT UMA mode 32 MB of memory pre allocated for frame buffer y
45. n tel PCI Express 8 2 5 2 SMSCS SMI SCI Status Table 173 Offset DCh SMSCS SMI SCI Status Size 32 bit Default 00000000h Power Well Core Access DER A Offset Start DCh PCI Configuration B D F 0 23 26 0 Offset End DFh Bit Range Default Access Acronym Description Power Management SCI Status This is set if the root port PME control 31 0 RWC PMCS logic needs to generate an interrupt and this interrupt has been routed to generate an SCI Hot Plug SCI Status This is set if the hot plug controller needs to 30 0 RWC HPCS generate an interrupt and this interrupt has been routed to generate an SCI 29 05 0 RO RSVD Reserved Hot Plug Link Active State Changed SMI Status This is set when 04 0 RWC HPLAS SLSTS LASC transitions from 0 to 1 and MPC HPME is set When set SMI B is generated 03 02 0 RO RSVD Reserved Hot Plug Presence Detect SMI Status This is set when SLSTS PDC 01 0 RWC HPPDM transitions from 0 to 1 and MPC HPME is set When set SMI B is generated 00 0 RWC PMMS Power Management SMI Status This is set when RSTS PS transitions from 0 to 1 and MPC PMME is set When set SMI B is generated Intel Atom Processor E6xx Series Datasheet 134 PCI Express 8 2 6 Miscellaneous Configuration Table 174 Miscellaneous Configuration Start End Symbol Register Name FC FF FD Functio
46. 03 00 0001 RO RO Capability Version Indicates version 1 0a PCI Express capability 9 3 1 29 Offset 74h DEVCAP Device Capabilities Register Table 206 74h DEVCAP Device Capabilities Register Size 32 bit Default 0000_0000h Power Well Core Access D FE 0 27 Offset Start 74h PCI Configuration B D F 0 27 0 Offset End 77h Bit Range Default Access Acronym Description 31 00 0 RO RSVD Reserved 9 3 1 30 Offset 78h DEVC Device Control Table 207 78h DEVC Device Control Sheet 1 of 2 Size 16 bit Default 0800h Power Well Core Access E 0 27 Offset Start 78h PCI Configuration B D F 0 27 0 Offset End 79h Bit Range Default Access Acronym Description 15 0 RO RSVD Reserved Intel Atom Processor E6xx Series Datasheet 151 intel Intel High Definition Audio D27 FO Table 207 78h DEVC Device Control Sheet 2 of 2 Size 16 bit Default 0800h Power Well Core Access e Td Offset Start 78h PCI Configuration B D F 0 27 0 Offset End 79h Bit Range Default Access Acronym Description Max Read Request Size Hardwired to 000 enabling 128 B maximum 14 12 000 RO MRRS read request size Enable No Snoop 0 The Intel HD AudioP controller will not set the No Snoop bit In this case isochronous transfers will not use VC1 VCi even if it is enabled since VC1 is never snooped Iso
47. 11 3 9 Steering of PCI Interrupt 8 NEEN E SEAN EE NEEN EK heme nnne nea nemen ehe NN ENNEN 223 Advanced Peripheral Interrupt Controller APIC ccccceceeseeeeeeeeeeteeeeeeeeeet conan 223 11 4 1 Memory Register 223 11 4 1 1 Address FECO0000h IDX Index Register 223 11 4 1 2 Address FECOOO10h WDW Window Register ss 223 11 4 1 3 Address FECO0040h EOI EOI Register 223 11 4 2 Index Registers tec poo e ERR LER dE ERM RR ERR EE A 224 11 4 2 1 Offset 00h ID Identification Register 224 11 4 2 2 Offset O1h VS Version Register 224 11 4 2 3 Offset 10 11h 3E 3Fh RTE 0 23 Redirection Table Entry 225 11 4 3 Unsupported Modes 2 ve ende em eren eti ee C RC il c AA 226 11 4 4 Interrupt Delivery 0 Im memememesee memes sine 226 11 4 4 1 Theory of Operation 226 1T 4 4 2 EOD irse ee eege saath E EE Ud Ree LA ek ndi reise Se 226 11 4 4 3 Interrupt Message Format 226 11 4 4 4 Interrupt Delivery Address Value rererere 226 11 4 4 5 Interrupt Delivery Data Value ssssessm HH 227 11 4 5 PCI Express nterrupts iiec eee t reed reto rcr rn nete risk ra EOR E aad 227 11 4 6 Routing of Internal Device Interrupts sess 227 Sental INterrupt m 227 TEST O ON 227 11 5 2 Start ERAMOS as 228 11 5 3 Data ramita tdi at AER 228 11 54 STOP EC EE 228 11 5 5 Serial Interrupts Not SGupported cece eee need 229 11 5 6 Data Frame Format and Issues icc eee ene n
48. 5 5 3 4 Offset 314Ch D25IR Device 25 Interrupt Route Table 60 314Ch D25IR Device 25 Interrupt Route Size 16 bit Default Power Well Memory Mapped IO BAR RCBA Offset 314Ch Bit Range Default Access Acronym Description Interrupt D Pin Route Indicates which routing is used for INTD B of 15 12 3h RW IDR device 25 Interrupt C Pin Route Indicates which routing is used for INTC B of 11 08 2h RW ICR device 25 I nterrupt B Pin Route Indicates which routing is used for INTB B of 07 04 1h RW IBR device 25 03 00 Oh RW IAR ee A Pin Route Indicates which routing is used for INTA B of Intel Atom Processor E6xx Series Datasheet 65 intel Register and Memory Mapping 5 5 3 5 Offset 314Eh D24IR Device 24 Interrupt Route Table 61 314Eh D24IR Device 24 Interrupt Route Size 16 bit Default Power Well Memory Mapped IO BAR RCBA Offset 314Eh Bit Range Default Access Acronym Description 15 12 3h RW IDR Interrupt D Pin Route Indicates which routing is used for INTD_B of 11 08 2h RW ICR ee C Pin Route Indicates which routing is used for INTC_B of 07 04 1h RW IBR Interrupt B Pin Route Indicates which routing is used for INTB_B of 03 00 Oh RW IAR Interrupt A Pin Route Indicates which routing is used for INTA_B of 5 5 3 6 Offset 3150h D23IR Device 23 Interrupt Route Table 62 3150h D23IR Dev
49. Core RCOMP Connected to high precision resistors on the motherboard Used for compensating pull up pull down impedances COMP1 0 externally connects to 18 2 Q 1 to Vss COMP1 1 externally connects to 35 7 Q 1 to Vss BPM B 3 0 1 0 AGTL Core Break Perf Monitor Various debug input and output functions NCTDO Core North TAP TDO If the CPU TAP selects NCTAP mode this pin is used as TDO output for the NCTAP When NCTAP is not enabled this pin is undef When used as NCTAP TDO requires external 56 Q pullup to vccp open drain NCTDI CMOS Core North Complex J TAG Test Data Input Transfers serial test data into the processor TDI provides the serial input needed for JTAG specification support NCTCK CMOS Core NCTAP TCLK or Low Yield Analysis Negative If the CPU TAP selects NCTAP mode this pin is used as TCLK input for the NCTAP Otherwise this pin is used for testing of CPU s L2 cache When used as NCTAP TCLK requires external 56 Q resistor to Vss NCTMS CMOS Core NCTAP TMS or Low Yield Analysis Positive If the CPU TAP selects NCTAP mode this pin is used as TMS input for the NCTAP Otherwise this pin is used for testing of CPU s L2 cache When used as NCTAP TMS requires external 56 Q pullup to vccp PRDY B 1 0 AGTL Core Probe Mode Ready CPU is response to PREQ B assertion Indicates CPU is in probe mode Input unused PREQ B 1 0
50. Major Version Size 8 bit Default 01h Power Well Core Access D E 0 27 Offset Start 03h PCI Configuration B D F 0 27 0 Offset End 03h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description g Major Version Indicates that the processor supports major revision 07 00 01h RO VMAJ number 1 of the Intel HD AudioP specification 9 3 2 1 4 Offset 04h OUTPAY Output Payload Capability Register Table 229 O4h OUTPAY Output Payload Capability Register Size 16 bit Default 003Ch Power Well Core Access D E 0 27 Offset Start 04h PCI Configuration B D F 0 27 0 Offset End 05h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 15 07 0 RO RSVD Reserved Output Payload Capability Indicates the total output payload available on the link This does not include bandwidth used for command and control This measurement is in 16 bit word quantities per 48 kHz frame The default link clock speed of 24 000 MHz the data is double pumped provides 1000 bits per frame or 62 5 words in total 40 bits are 06 00 3Ch RO OUTPAY Sec command and control leaving 60 words available for data 00h 0 words 01h 1 word payload FFh 255h word payload 9 3 2 1 5 Offset 06h I NPAY Input Payload Capability Register Table 230 06h INPAY Input Payload Capability Register Sheet 1 of 2 Size 16 bit Default 001Dh Power Well Core Access d D F 0 27 Offset Start 06h PCI Configuration B D F 0 27 0 Offse
51. Power Management IC PWROK l CMOS3 3 RTC Power OK When asserted PWROK is an indication to the system that core power is stable PWROK can be driven asynchronously RSMRST_B l CMOS3 3 RTC Resume Well Reset This signal is used for resetting the resume well An external RC circuit is required to ensure that the resume well power is valid prior to RSMRST_B going high RTCRST_B l CMOS3 3 RTC RTC Well Reset This signal is normally held high but can be driven low on the motherboard to test the RTC power well and reset some bits in the RTC well registers that are otherwise not reset by SLPMODE or RSMRST_B An external RC circuit on the RTCRST_B signal creates a time delay such that RTCRST_B will go high some time after the battery voltage is valid This allows the chip to detect when a new battery has been installed The RTCRST_B input must always be high when other non RTC power planes are on SUSCLK O CMOS3 3 sus Suspend Clock This signal is an output of the RTC generator circuit 32 768 kHz SUSCLK can have a duty cycle from 30 to 70 WAKE_B l CMOS3 3 SUS PCI Express Wake Event This signal indicates a PCI Express port wants to wake the system This is a single signal that can be driven by any of the devices sitting on the PCle slots on the board It is normally pulled high by the devices but any devices that need to wake the processor will drive this signal low
52. SDVO device through the SDVO_CLK differential pair This signal pair has an operating range of 100 200 MHz so if the desired display frequency is less than 100 MHz the SDVO device must apply a multiplier to get the SDVO_TVCLKIN frequency into the 100 to 200 MHz range SDVO_STALLP l SDVO_STALLN PCle Core Serial Digital Video Field Stall Differential input pair that allows a scaling SDVO device to stall the pixel pipeline 1 0 SDVO_CTRLCLK CMOS3 3 OD Core SDVO Control Clock Single ended control clock line to the SDVO device Similar to 12C clock functionality but may run at faster frequencies SDVO CTRLCLK is used in conjunction with SDVO CTRLDATA to transfer device config PROM and monitor DDC information This interface directly connects to the SDVO device 1 0 SDVO_CTRLDATA CMOS3 3 OD Core SDVO Control Data SDVO CTRLDATA is used in conjunction with SDVO CTRLCLK to transfer device config PROM and monitor DDC information This interface directly connects to the SDVO device SDVO REFCLKP l SDVO_REFCLKN SDVO Core SDVO Reference Clock Display PLL Positive Negative Ref Clock Intel Atom Processor E6xx Series Datasheet 34 Signal Description n tel 2 3 PCI Express Signals Table 7 PCI Express Signals Signal Name Direction Type ied Description PCIE_PETp 3 0 O Core PCI Express Transmit PCIE_PET 3 0 are PCI Express PCIE
53. The only exception is the this register itself The Global Control register is write able as a DWord Word or Byte even when CRST B this bit is 0 if the byte enable for the byte containing the CRST B bit Byte Enable 0 is active If Byte Enable 0 is not active writes to the Global Control register will be ignored when CRST B is 0 When CRST B is 0 reads to Intel HD Audio memory mapped registers will return their default value except for registers that are not reset with RESET_B or on a D3hot gt DO transition 9 3 2 1 7 Offset OCh WAKEEN Wake Enable Table 232 OCh WAKEEN Wake Enable Size 16 bit Default 0000h Power Well Core Access DE 0 97 Offset Start OCH PCI Configuration B D F 0 27 0 Offset End ODh Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 15 02 0 RO RSVD Reserved SDIN Wake Enable Flags SDI WEN These bits control which SDI signal s may generate a wake event A 1 in the bit mask indicates that the associated SDIN signal is enabled to generate a wake RW Bit O is for SDIO SUS SECHER Bit 1 is for SDI1 These bits are in the suspend well and only cleared on a power on reset Software must not make assumptions about the reset state of these bits and must set them appropriately 01 00 0 Intel Atom Processor E6xx Series Datasheet 163 intel Intel High Definition Audio D27 FO 9 3 2 1 8 O
54. This indicates that hot plug is supported Hot Plug Surprise This indicates that the device may be removed from 05 1b RO HPS the slot without prior notification Power Indicator Present This indicates that a power indicator LED is 04 Ob RO PIP not present for this slot Attention Indicator Present This indicates that an attention indicator 03 Ob RO AIP LED is not present for this slot 02 Ob RO MSP MRL Sensor Present This indicates that an MRL sensor is not present Power Controller Present This indicates that a power controller is not 01 Ob RO PCP implemented for this slot Attention Button Present This indicates that an attention button is not 00 Ob RO ABR implemented for this slot 8 2 2 10 SLCTL Slot Control Table 159 Offset 58h SLCTL Slot Control Sheet 1 of 2 Size 16 bit Default 0000h Power Well Core Access e IWER Offset Start 58h PCI Configuration B D F 0 23 26 0 Offset End 59h Bit Range Default Access Acronym Description 15 13 Oh RO RSVD Reserved Link Active Changed Enable When set this field enables generation of 12 Ob RW LACE a hot plug interrupt when the Data Link Layer Link Active field is changed 11 10 Ob RO RSVD Reserved 09 08 00b RW PIC Power Indicator Control PIC is not supported 07 06 00b RW AIC Attention Indicator Control AIC is not supported Hot Plug Interrupt Enable When set enables generation of a hot plug 05 Ob RW HPE interrupt on enabled hot plug events 04 Ob RO CCE Command Completed I
55. VCCD DPL K19 VIDEN 1 AL26 vss F17 VCCD180 T25 VMM T23 VSS F19 VCCDSENSE N20 VNN R18 vss F21 VCCDSUS K15 VNN R20 vss F23 VCCF AM25 VNN U18 vss F25 VCCFHV P19 VNN U20 vss F27 VCCP L26 VNN W18 VSS F29 VCCP P15 VNN W20 VSS F31 VCCP R26 VNN AA18 VSS F33 VCCP W26 VNN AA20 VSS G6 VCCP AC26 VNN AC18 VSS G16 VCCP AG26 VNN AC20 VSS G18 VCCP AJ26 VNN AE18 VSS G20 VCCP AK15 VNN AE20 VSS G22 VCCP33 J16 VNN AG18 VSS G24 VCCP33 K17 VNN AJ 18 VSS G26 VCCP33 P25 VNNSENSE AG20 vss G28 VCCP33SUS K13 vss A4 VSS G30 VCCPA U26 VSS A34 VSS G34 VCCPA AK25 VSS B3 VSS H9 VCCPDDR V13 VSS B35 VSS H13 Intel Atom Processor E6xx Series Datasheet 292 m Ballout and Package Information n tel Table 407 Pin List Table 407 Pin List Table 407 Pin List Pin Name Ball Pin Name Ball Pin Name Ball vss H15 VSS P3 VSS W28 vss H21 vss P5 vss W32 vss H23 vss P7 vss Y3 vss H27 vss P9 vss Y9 vss H29 vss P13 vss Y11 VSS H33 VSS P21 VSS Y13 VSS H35 VSS P23 vss Y17 VSS J6 VSS P27 vss Y19 vss J10 VSS P29 VSS Y21 VSS J12 VSS P35 VSS Y23 VSS J14 VSS R8 VSS Y25 VSS J26 VSS R10 VSS Y27 VSS J28 VSS R12 VSS Y29 VSS J30 VSS R14 VSS Y35 VSS J32 VSS R28 VSS AA6 VSS K3 VSS R32 VSS AA12 VSS K9 VSS T3 VSS AA14 VSS K25 VSS T7 VSS AA26 VSS K27 VSS T9 VSS AA28 VSS K29 VSS T11 VSS AA32 VSS K31 VSS T17 VSS AB3 VSS K35 VSS T19 VSS AB9 VSS L6 VSS T21 VSS AB11 VSS L14 VSS T29 VSS AB15 VSS L16 VSS T35 VSS AB17 VSS L28 VSS U6 VSS AB19
56. VT x requires software Yes Yes Yes Yes Yes Yes Yes Yes support Commercial Temperature Yes Yes Yes Yes No No No No 0 to 70 C Extended Temperature No No No No Yes Yes Yes Yes 40 to 85 C TDP W 3 3 3 6 3 6 4 5 3 3 3 6 3 6 4 5 Intel Atom Processor E6xx Series Datasheet 30 Signal Description intel 2 0 Signal Description This chapter provides a detailed description of the signals and boot strap definitions The processor signals are arranged in functional groups according to their associated interface Each signal description table has the following headings Signal The name of the signal pin Type The buffer direction and type Buffer direction can be either input output or I O bidirectional See Table 3 for definitions of the different buffer types Power Well The power plane used to supply power to that signal Choices are core DDR Suspend and RTC Description A brief explanation of the signal s function Table 3 Buffer Types Buffer Type Buffer Description AGTL Assisted Gunning Transceiver Logic Plus CMOS Open Drain interface signals that require termination Refer to the AGTL I O Specification for complete details CMOS CMOS OD 1 05 V CMOS buffer or CMOS Open Drain CMOS HDA CMOS buffers for Intel HD AudioP interface that can be configured for either 1 5 V or 3 3 V operation The processor will only support 3 3 V CMOS1 8 1 8 V CMOS buf
57. WDTLR WDT Lock Register 269 1110 4 Theory Of Operation oreet EEN cae 270 11 10 4 1RTC Well and WDT TOUT Functionality sse 270 11 10 4 2Register Unlocking Sequence n 270 11 10 4 3Reload Sequence 0 ice cece ene ee emen nane 271 11 10 4 4L 0w Power State rox xe Ren E Re a a 271 12 0 Absolute Maximum Ratings memes emen eene 273 12 1 Absolute Maximum Rating 274 13 0 DC CharacteriSHcs ooo SEENEN AE 275 KE Va DE Ui UE 275 13 2 Power and Current Charactertstice cece cece ene mmm 276 13 3 General DC Characteristics reet eds era nob veces rea diea lebe Ente 277 14 0 Ballout and Package lIntormatton mmm meme ne 281 14 1 Package Diagrams ceci t ie EE AU 282 14 2 Ballout Definition and Signal Locations 284 Figures 1 System Block Diagram Example mem memes memes ene 23 2 Components of the Intel Atom Processor E6xx Series ooooooocococonoocccocncnnononononononononos 26 3 System Address Maps iex ta atar 55 AY PCI DGVICES EUM 58 5 Graphics a 75 6 Display Einik lee 84 7 Display Resolutions ie RR add ia 87 8 LVDS Control Signal SolUtiOni x bus Eege ENEE EE AR OEEREAU TERR ENEE 88 9 Basic SPI Protocol cer ad 247 10 Intel Atom Processor E6xx Series Silicon and Die Side Capacitor Top View 282 11 Intel Atom Processor E6xx Series Package Dimensions sse 283 12 Intel Atom Processor E6xx Series Package Ball Patten 284 13 Intel Atom Processor E6xx Seri
58. and the corresponding IRR bit cleared when an interrupt acknowledge cycle is seen and the vector returned is for that interrupt Interrupt Mask Register I MR Determines whether an interrupt is masked Masked interrupts will not generate INTR 11 3 3 2 Acknowledging The CPU generates an interrupt acknowledge cycle which is translated into an Interrupt Acknowledge Special Cycle The 8259 translates this cycle into two internal INTA pulses expected by the 8259 cores The 8259 uses the first internal INTA pulse to freeze the state of the interrupts for priority resolution On the second INTA pulse the master or slave will sends the interrupt vector to the processor with the acknowledged interrupt code This code is based upon bits 7 3 of the corresponding I CW2 register combined with three bits representing the interrupt within that controller Intel Atom Processor E6xx Series Datasheet 218 ACPI Devices Table 324 11 3 3 3 11 3 4 11 3 4 1 intel Content of Interrupt Vector Byte Master Slave Interrupt Bits 7 3 Bits 2 0 IRQ7 15 111 IRQ6 14 110 IRQ5 13 101 1RQ4 12 100 ICW2 7 3 IRQ3 11 011 IRQ2 10 010 IRQ1 9 001 IRQO 8 000 Hardware Software I nterrupt Sequence 1 One or more of the Interrupt Request lines IRQ are raised high in edge mode or seen high in level mode setting the corresponding IRR bit 2 The 8259 sends INTR acti
59. e n tel Register and Memory Mapping 5 5 2 8 Offset 3130h DO3IP Device 3 Interrupt Pin Table 55 3130h DO3IP Device 3 Interrupt Pin Size 32 bit Default Power Well Memory Mapped IO BAR RCBA Offset 3130h Bit Range Default Access Acronym Description 31 04 0 RO RSVD Reserved 03 00 1h RW DP iris PAA Indicates which pin the graphics controller uses for 5 5 3 Interrupt Route Configuration Indicates which interrupt routing is connected to the INTA B C D pins reported in the DxIP register fields This will be the internal routing the device interrupt is connected to the interrupt controller Table 56 Interrupt Route Configuration Bits Pin Bits Pin Oh PIRQA_B 4h PIRQE_B 1h PIRQB B 5h PIRQF B 2h PIRQC B 6h PIRQG B 3h PIRQD B 7h PIRQH_B 8h Fh Reserved 5 5 3 1 Offset 3140h D31IR Device 31 Interrupt Route Table 57 3140h D31IR Device 31 Interrupt Route Size 16 bit Default Power Well Memory Mapped IO BAR RCBA Offset 3140h Bit Range Default Access Acronym Description 15 12 3h RW IDR I nterrupt D Pin Route Indicates which routing is used for INTD B of device 31 11 08 2h RW ICR I nterrupt C Pin Route Indicates which routing is used for INTC B of device 31 07 04 1h RW IBR Interrupt B Pin Route Indicates which routing is used for INTB B of device 31 03 00 Oh RW IAR Interrupt A Pin Route Indicates which routing i
60. internal register Address FECO0010h WDW Window Register This 32 bit register specifies the data to be read or written to the register pointed to by the IDX register This register can be accessed only in DW quantities Address FECOO0O040h EOI EOI Register When a write is issued to this register the IOxAPIC will check the lower 8 bits written to this register and compare it with the vector field for each entry in the I O Redirection Table When a match is found RTE RIRR for that entry will be cleared If multiple entries have the same vector each of those entries will have RTE RIRR cleared Only bits 7 0 are used Bits 31 08 are ignored Intel Atom Processor E6xx Series Datasheet 223 i n tel j ACPI Devices 11 4 2 I ndex Registers The registers listed below can be accessed via the IDX register When accessing these registers accesses must be done as DWs otherwise unspecified behavior will result Software should not attempt to write to reserved registers Some reserved registers may return non zero values when read Table 326 Index Registers Offset Symbol Register 00h ID Identification 01h VS Version 02 0Fh Reserved 10 11h RTEO Redirection Table 0 12 13h RTE1 Redirection Table 1 3E 3Fh RTE23 Redirection Table 23 40 FFh Reserved 11 4 2 1 Offset 00h ID Identification Register Table 327 00h ID Identification Register Si
61. the Dock Attach DCKCTL DA bit and the Dock Mate DCKSTS DM bit are both de asserted The HDA DOCK EN B signal is de asserted and HDA DOCKRST B is asserted HDA CLK HDA SYNC and HDA SDO signals may or may not be running at the point in time that the docking event occurs 3 The physical docking event is signaled to ACPI BIOS software via ACPI control methods How this is done is outside the scope of this specification 4 ACPI BIOS software first checks that the docking is supported via DCKSTS DS 1 and that the DCKSTS DM 0 and then initiates the docking sequence by writing a 1 to the DCKCTL DA bit 5 The Intel HD AudioP controller then asserts the HDA DOCK EN B signal so that the HDA CLK signal begins toggling to the dock codec HDA DOCK EN B shall be asserted synchronously to HDA CLK and timed such that HDA CLK is low HDA SYNC is low and HDA SDO is low The first 8 bits of the Command field are reserved and always driven to 0 This creates a predictable point in time to always assert HDA DOCK EN B 6 After the controller asserts HDA DOCK EN B it waits for a minimum of 2400 HDA CLKs 100 us and then de asserts HDA DOCKRST B This is done in such a way to meet the Intel HD AudioP link reset exit specification HDA DOCKRST B de assertion should be synchronous to HDA CLK and timed such that there are least four full HDA CLKs from the de assertion of HDA DOCKRST B to the first frame HDA SYNC assertion 7 The Connect Turnaround Addr
62. 0 25 3 3 3 96 V 12 13 CMOS HDA Vu Input Low Voltage 0 35 Vecp33 V Vin Input High Voltage 0 65 Vecp33 V VoL Output Low Voltage 0 10 VCCP33 V Vou Output High Voltage 0 9 VCCP33 V ligAK Input Leakage Current 20 HA Cin Input Capacitance 7 8 pF Intel Atom Processor E6xx Series Datasheet 278 DC Characteristics Table 406 Active Signal DC Characteristics Sheet 2 of 3 Symbol Parameter Min Nom Max Unit Notes System Memory CMOS1 8 VCC180 2 VIL Input Low Voltage 0 4 7 Ce V VCC180 2 Vin Input High Voltage P eee 1 9 V VCC180 2 VoL Output Low Voltage 8 ed V VCC180 2 Vou Output High Voltage 0 250 V PCI e Differential Peak to Peak VTX DIFF P P Output Voltage 0 8 E v 6 AC Peak Common Mode Output VTx_CM ACp Voltage P 20 mV 6 ZTX DIFF DC DC Differential TX Impedance 80 100 120 Q Differential Input Peak to Peak AC peak Common Mode Input Vox CM ACp Voltage H 150 mV SDVO Differential Peak to Peak VTX DIFF P P Output Voltage 0 8 s H AC Peak Common Mode Output VTX_CM ACp Voltage S 20 my ZTX DIFF DC DC Differential TX Impedance 80 100 120 Q Differential Input Peak to Peak AC peak Common Mode Input VRX_CM ACp Voltage H 150 mV LVDS Vop Differential Output Voltage 250 350 450 mV Change in Vop between AVop Complementary Output States 50 my Vos Offset Voltage 1 125 1 25 1 375 V Change in Vos
63. 0000 0000h RW RO 58 59 RIRBWP RIRB Write Pointer 0000h WO RO 5A 5B RINTCNT Response Interrupt Count 0000h RW RO 5C 5C RIRBCTL RIRB Control 00h RW RO 5D 5D RIRBSTS RIRB Status 00h RWC RO 5E 5E RIRBSIZE RIRB Size 40h RO 60 63 IC Immediate Command 0000_0000h RW 64 67 IR Immediate Response 0000_0000h RO 68 69 ICS Immediate Command Status 0000h RW RWC RO 70 73 DPBASE DMA Position Base Address 0000_0000h RW RO 80 82 ISDOCTL Input Stream Descriptor 0 ISDO Control 04 0000h RW RO 83 83 ISDOSTS ISDO Status 00h RWC RO 84 87 ISDOLPIB ISDO Link Position in Buffer 0000 0000h RO 88 8B ISDOCBL ISDO Cyclic Buffer Length 0000 0000h RW DC 8D ISDOLVI ISDO Last Valid Index 0000h RW RO 8b 8F ISDOFIFOW ISDO FIFO Watermark 0004h RW RO 90 91 ISDOFIFOS ISDO FIFO Size 0077h RO 92 93 ISDOFMT ISDO Format 0000h RW RO Intel Atom Processor E6xx Series Datasheet 158 Intel High Definition Audio D27 FO intel Table 225 Intel HD Audio Register Summary Sheet 2 of 3 Offset Offset Symbol Full Name Reset Value Access Start End 98 9B ISDOBDPL ISDO Buffer Descriptor List Pointer 0000 0000h RW RO WO AO A2 ISD1CTL Input Stream Descriptor 1 ISD1 Control 04_0000h RW RO A3 A3 ISD1STS ISD1 Status 00h RWC RO A4 A7 ISD1LPIB ISD1 Link Position in Buffer 0000 0000h RO A8 AB ISD1CBL ISD1 Cyclic Buffer Length 000
64. 1 Header Device itself receives a Completion with Unsupported Request Completion Status Received Target Abort This bit is set when the Secondary Side for 12 Ob RWC RTA Type 1 Configuration Space Header Device for requests initiated by the Type 1 Header Device itself receives a Completion with Completer Abort Completion Status Signaled Target Abort Not applicable or implemented hardwired to 11 Ob RO STA 0 The processor does not generate Target Aborts the processor will never complete a request using the Completer Abort Completion status Secondary DEVSEL B Timing Status Reserved per PCI Express 10 09 00b RO SDTS Base Specification Data Parity Error Detected When set this indicates that the MCH 08 Ob RWC DPD received across the link upstream a Read Data Completion Poisoned TLP EP 1 This bit can only be set when the Parity Error Enable bit BCTRL PERE in the Bridge Control register is set Intel Atom Processor E6xx Series Datasheet 118 PCI Express intel Table 140 Offset 1Eh SSTS Secondary Status Sheet 2 of 2 Size 16 bit Default 0000h Power Well Core Access D FO R Offset Start 1Eh PCI Configuration B D F 0 23 26 0 Offset End 1Fh Bit Range Default Access Acronym Description 07 00 000000 RO RSVD Reserved 00b 8 2 1 15 MB Memory Base Address Accesses that
65. 179 seconds This counter is enabled while the Bit Clock bit is set to 1 Software uses this counter to synchronize between multiple controllers Will be reset on controller reset 9 3 2 1 15 Table 240 Offset 38h SSYNC Stream Synchronization Register 38h SSYNC Stream Synchronization Register Size 32 bit Default 0000 0000h Power Well Core Access PCI Configuration B D F 0 27 0 Offset Start 38h Offset End 3Bh Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 31 04 0 RO RSVD Reserved 03 00 Oh RW SSYNC Stream Synchronization Bits The Stream Synchronization bits when set to 1 block data from being sent on or received from the link Each bit controls the associated Stream Descriptor bit 0 corresponds to the first Stream Descriptor etc To synchronously start a set of DMA engines the bits in the SSYNC register are first set to a 1 The RUN bits for the associated Stream Descriptors are then set to a 1 to start the DMA engines When all streams are ready FIFORDY 1 the associated SSYNC bits can all be set to 0 at the same time and transmission or reception of bits to or from the link will begin together at the start of the next full link frame To synchronously stop streams first the bits are set in the SSYNC register and then the individual RUN bits in the Stream Descriptors are cleared by soft
66. 2 on page 269 00h 18h 18h Offset 18h WDTLR WDT Lock Register on page 269 00h Note Base Address for the Watchdog Timer registers listed in this section is configurable 11 10 3 1 Offset OOh PV1RO Preload Value 1 Register O Table 388 00h PV1RO Preload Value 1 Register O Size 8 bit Default FFh Power Well Core ReneS PCI Configuration B D F pat P Offset End 00h IAF Base Address Base 10 Offset 00h Bit Range Default Access Acronym Description 07 00 FFh RW PLOADI 7 0 register Preload Value 1 7 0 This register is used to hold the bits 0 through 7 of the preload value 1 for the WDT Timer The Value in the Preload Register is automatically transferred into the 35 bit down counter The value loaded into the preload register needs to be one less than the intended period This is because the timer makes use of zero based counting i e zero is counted as part of the decrement Refer to Section 11 10 4 2 for details on how to change the value of this Intel Atom Processor E6xx Series Datasheet 264 ACPI Devices I n tel 11 10 3 2 Offset 01h PV1R1 Preload Value 1 Register 1 Table 389 01h PV1R1 Preload Value 1 Register 1 Size 8 bit Default FFh Power Well Core Access Offset Start 01h PCI Configuration B D F Offset End 01h IAF Base Address Base 10 Offset 01h Bit Range Default Access Acronym Description Pre
67. 2 are 32 bits wide Intel Atom Processor E6xx Series Datasheet 209 i n tel j ACPI Devices Table 309 108h 128h 148h T 0 2 CV Timer 0 2 Comparator Value Size 64 bit Default Power Well Core Access e Offset Start 108h 128h 148h FCI Configuration BDF Offset End 10Fh 12Fh 14Fh Bit Range Default Access Acronym Description Timer Compare Value R W Reads to this register return the current value of the comparator Timers 0 1 or 2 are configured to non periodic mode Writes to this register load the value against which the main counter should be compared for this timer When the main counter equals the value last written to this register the corresponding interrupt can be generated if so enabled The value in this register does not change based on the interrupt being generated Timer 0 is configured to periodic mode When the main counter equals the value last written to this register the corresponding interrupt can be generated if so enabled 63 0 See RW After the main counter equals the value in this Desc register the value in this register is increased by the value last written to the register As each periodic interrupt occurs the value in this register will increment When the incremented value is greater than the maximum value possible for this register FFFFFFFFh for a 32 bit timer or FFFFFFFFFFFFFFFFh for a 64 bit timer the value will wrap around through 0
68. 2 mb 4 mb ST M25P80 35 Sector The Write process is executed to write bytes to the Flash device The atomic instructions that make up the Write process include a Write enable instruction a Write or Program instruction and finally a status poll Note that the Write Disable occurs automatically following the completion of the Write opcode in nearly all cases The processor does not support explicitly disabling writes as part of the Atomic write sequence It is recommended that BIOS avoid using instructions that take more than one second to complete inside the flash See Section 11 9 5 12 1 for details 11 9 7 1 Run Time Updates BIOS especially SMI code may log errors or record other run time variables in a section of the flash by writing a few bytes at a time It is recommended that run time updates be performed to a section of flash that has already been erased and allocated BIOS keeps a pointer to the next byte to be written and updates the pointer real time as bytes are written SMI may optionally be enabled by performing a programmed write with the SPI SMI Enable bit set to report to software when the update has completed Direct memory reads to the SPI flash can encounter long delays The processor may directly block progress of one or more threads in the system Therefore run time reads are recommended to use the programmed command mechanism and optionally the Software Based SPI Access Request Grant mechanism The programmed command mechan
69. 20 000h RO NXTCAP Next Capability Offset Indicates this is the last capability 19 16 1h RO Capability Version 15 00 0005h RO PCI Express Extended Capability ID 9 3 1 45 Offset 134h ESD Element Self Description Register Table 222 134h ESD Element Self Description Register Sheet 1 of 2 Size 32 bit Default OF00 0100h Power Well Core Access D F 0 27 Offset Start 134h PCI Configuration B D F 0 27 0 Offset End 137h Bit Range Default Access Acronym Description 31 24 OFh RO PORT Port Number Intel HD Audio assigned as Port _B15 Component I D This field returns the value of the ESD CID field of the 23 16 00h RO COMPID chip configuration section ESD CID is programmed by BIOS Intel Atom Processor E6xx Series Datasheet 156 Intel High Definition Audio D27 FO Table 222 134h ESD Element Self Description Register Sheet 2 of 2 Size 32 bit Default OFOO_0100h Power Well Core Access D F 0 27 Offset Start 134h PCI Configuration B D F 0 27 0 Offset End 137h Bit Range Default Access Acronym Description Number of Link Entries The Intel HD AudioP controller only connects 15 08 Olh RO LNKENT to one device the processor egress port Therefore this field reports a value of Lh 07 04 Oh RO RSVD Reserved Element Type The Intel HD Audio controller is an Integrated Root 03 00 Oh RO ELTYP Complex Device Therefore this field reports a value of Oh
70. 49 DCTL Device Control 4A 4B DSTS Device Status 4C Ar LCAP Link Capabilities 50 51 LCTL Link Control 52 53 LSTS Link Status 54 57 SLCAP Slot Capabilities 58 59 SLCTL Slot Control 5A 5B SLSTS Slot Status 5C 5D RCTL Root Control 5E 5F RCAP Root Capabilities 60 63 RSTS Root Status 64 65 LCTL2 Link Control 2 66 67 LSTS2 Link Status 2 Intel Atom Processor E6xx Series Datasheet 122 PCI Express 8 2 2 1 CLI ST Capabilities List Table 150 Offset 40h CLIST Capabilities List Size 16 bit Default 9010h Power Well Core Access Offset Start 40h PCI Configuration B D F 0 23 26 0 Offset End 41h Bit Range Default Access Acronym Description 15 08 90h RO NEXT Next Capability Value of 90h indicates the location of the next pointer 07 00 10h RO CID Capability 1D This indicates this is a PCI Express capability 8 2 2 2 XCAP PCI Express Capabilities Table 151 Offset 42h XCAP PCI Express Capabilities Size 16 bit Default 0041h Power Well Core Access A g Offset Start 42h PCI Configuration B D F 0 23 26 0 Offset End 43h Bit Range Default Access Acronym Description 15 14 Oh RO RSVD Reserved J Interrupt Message Number The processor does not have multiple 13 09 Oh RO TMN MSI interrupt numbers Slot Implemented This indicates whether the root port is connected t
71. 52h PM CAP Power Management Capabilities Register Sheet 1 of 2 Size 16 bit Default 4802h Power Well Core Access D F 0 27 Offset Start 52h PCI Configuration B D F 0 27 0 Offset End 53h Bit Range Default Access Acronym Description 15 11 01001 RO PME Support Indicates PME B can be generated from D3yo7 and DO states Intel Atom Processor E6xx Series Datasheet 148 Intel High Definition Audio D27 FO intel Table 198 52h PM CAP Power Management Capabilities Register Sheet 2 of 2 Size 16 bit Default 4802h Power Well Core Access D F 0 27 Offset Start 52h PCI Configuration B D F 0 27 0 Offset End 53h Bit Range Default Access Acronym Description 10 03 0 RO RSVD Reserved 02 00 010 RO vs Version Indicates support for Revision 1 1 of the PCI Power Management Specification 9 3 1 22 Offset 54h PM_CTL_STS Power Management Control And Status Register Table 199 54h PM_CTL_STS Power Management Control And Status Register Size 32 bit Default 0000h Power Well Core Access DIE 0 27 Offset Start 54h PCI Configuration B D F 0 27 0 Offset End 57h Bit Range Default Access Acronym Description 31 16 0 RO RSVD Reserved PME Status 0 Software clears the bit by writing a 1 to it 15 0 RWC PMES 1 This bit is set when the Intel HD AudioP controller would normally assert the PME
72. 78h DEVC Device Control 151 9 3 1 31 Offset 7Ah DEVS Device Status Register 152 9 3 1 32 Offset FCh FD Function Disable Register 152 9 3 1 33 Offset 100h VCCAP Virtual Channel Enhanced Capability Header 153 9 3 1 34 Offset 104h PVCCAP1 Port VC Capability Register 1 153 9 3 1 35 Offset 108h PVCCAP2 Port VC Capability Register 2 154 9 3 1 36 Offset 10Ch PVCCTL Port VC Control Register sss 154 9 3 1 37 Offset 10Eh PVCSTS Port VC Status Register 154 9 3 1 38 Offset 110h VCOCAP VCO Resource Capability Register 154 9 3 1 39 Offset 114h VCOCTL VCO Resource Control Register 155 9 3 1 40 Offset 11Ah VCOSTS VCO Resource Status Register 155 9 3 1 41 Offset 11Ch VC1CAP VC1 Resource Capability Register 155 9 3 1 42 Offset 120h VC1CTL VC1 Resource Control Register 155 9 3 1 43 Offset 126h VC1STS VC1 Resource Status Register 156 9 3 1 44 Offset 130h RCCAP Root Complex Link Declaration Enhanced Capability Header Register 156 9 3 1 45 Offset 134h ESD Element Self Description Register 156 9 3 1 46 Offset 140h L1DESC Link 1 Description Register 157 9 3 1 47 Offset 148h L1ADD Link 1 Address Register sss 157 9 3 2 Memory Mapped Configuration Reglsters sss 157 9 3 2 1 Intel HD Audio
73. C Video sprite plane DPST 3 0 The display contains the following functions Display data fetching Out of order display data handling Display blending Gamma correction Panel fitter function Display Output Stages The display output can be divided into three stages Planes Request Receive data from memory Format memory data into pixels Handle fragmentation tiling physical address mapping Pipes Generate display timing Scaling LUT e Ports Format pixels for output LVDS or SDVO Interface to physical layer Planes The Display Controller contains a variety of planes such as Display and Cursor A plane consists of a rectangular shaped image that has characteristics such as source size position method and format These planes get attached to source surfaces which are rectangular areas in memory with a similar set of characteristics They are also associated with a particular destination pipe Display Plane The primary and secondary display plane works in an indexed mode hi color mode or a true color mode The true color mode allows for an 8 bit alpha channel One of the primary operations of the display plane is the set mode operation The set mode operation occurs when it is desired to enable a display change the display timing or source format The secondary display plane can be used as a primary surface on the secondary display or as a sprite planes on either the primary o
74. Command Word 1 213 315 21h Alh ICW2 Initialization Command Word 3 214 316 21h MICW3 Master Initialization Command Word 3 215 317 Alh SICW3 Slave Initialization Command Word 3 sss 215 Intel Atom Processor E6xx Series Datasheet 18 Contents i n tel 318 21h Alh ICWA Initialization Command Word 4 Register 215 319 21h Alh OCW1 Operational Control Word 1 Interrupt Mask 216 320 20h AOh OCW2 Operational Control Word 2 ccc cece cece eee ee eee eee ee ns 216 321 20h AOh OCW3 Operational Control Word 3 cccceeee eee ee eee tee e Hs 217 322 4DOh ELCR1 Master Edge Level Control 217 323 4D1h ELCR2 Slave Edge Level Control 218 324 Content of Interrupt Vector Bvte 0 cece ee eee seem nenne eese ees 219 ERR Leg Ce 223 326 Index Registers dr oe erret teta tex tek exe skr pa Ru bn Geen ened Renee ee me Me RA E e ERE EIE NEED ERA 224 327 00h ID Identification Register 224 328 01h VS Version Reglster uere oda wie AM KR DX EXER RENE M AER RARE 224 329 10 11h 3E 3Fh RTE 0 23 Redirection Table Ent 225 330 Interrupt Delivery Address Value mensem sie emnes 226 331 Interrupt Delivery Data Value 2 0 0 mms eem se nee emen nns 227 332 Serial Interrupt Mode Gelection memes emen ens 228 333 Data Frame Format csset EAR SEA SE AFER DEES NEE ERR ERRARE AEA ANARAN 229 Ep RTC erc 230 335 RTC Indexed Registers eco b tdci uda 231 ESO Eoi M
75. Controller The Intel High Definition Audio Specification defines a digital interface that can be used to attach different types of codecs such as audio and modem codecs The Intel HD AudioP controller supports up to four audio streams two in and two out With the support of multi channel audio stream 32 bit sample KSE and sample rate up to 192 kHz the Intel High Definition Audio Intel HD Audio controller provides audio quality that can deliver consumer electronic CE levels of audio experience On the input side the Intel Atom Processor E6xx Series adds support for an array of microphones The Intel HD Audio controller uses a set of DMA engines to effectively manage the link bandwidth and support simultaneous independent streams on the link The Intel HD Audio controller also supports isochronous data transfers allowing glitch free audio to the system SMBus Host Controller The Intel Atom Processor E6xx Series contains an SMBus host interface that allows the processor to communicate with SMBus slaves This interface is compatible with most I C devices The SMBus host controller provides a mechanism for the processor to initiate communications with SMBus peripherals slaves See the System Management Bus SMBus Specification Version 1 0 General Purpose I O GPIO The Intel Atom Processor E6xx Series contains a total of 14 GPIO pins Five of these GPIOs are powered by core power rail and are
76. Controller provides the 2D graphics functionalities for the display pipeline The Display Controller converts a set of source images or surfaces and merges them and delivers them at the proper timing to output interfaces that are connected to the Intel Atom Processor E6xx Series Datasheet 83 m l n tel Graphics Video and Display Figure 6 LVDS display devices see Figure 6 Along the display pipe the display data can be converted from one format to another stretched or shrunk and color corrected or gamma converted Display Link I nterface LVDS Panel Internal Display Display Controller SDVO Panel External Display The Display Controller supports five display planes and two cursor planes and is running in the core display clock domain The Display Controller supports the following features Seven planes Display Plane A B Display C sprite Overlay Cursor A Cursor B and VGA Dual Independent display pipes Pipe A and Pipe B Display Pipe A Outputs directly as LVDS Display Pipe B Outputs directly as SDVO Supports 64 bit FP color format NPO2 Tiling and 180 degree rotation Output pixel width 24 bit RGB LVDS 24 1 24 0 and 18 0 as well Intel Atom Processor E6xx Series Datasheet 84 Bm e Graphics Video and Display n tel 7 5 1 7 5 1 1 Supports NV12 data format 3x3 Panel Fitter shared by two pipes Support Constant Alpha mode on Display
77. Default 00008FCOh Power Well Core Access e i Offset Start 44h PCI Configuration B D F 0 23 26 0 Offset End 47h Bit Range Default Access Acronym Description Endpoint L1 Acceptable Latency This indicates more than 4 us This 11 09 111b RO E1AL field essentially has no meaning for root ports since root ports are not endpoints Endpoint LO Acceptable Latency This indicates more than 64 us This 08 06 111b RO EOAL field essentially has no meaning for root ports since root ports are not endpoints Extended Tag Field Supported This bit indicates that 5 bit tag fields 05 Ob RO ETFS are supported 04 03 00b RO PFS Phantom Functions Supported No phantom functions supported 02 00 000b RO MPS Max Payload Size Supported This indicates that the maximum payload size supported is 128B 8 2 2 4 DCTL Device Control Table 153 Offset 48h DCTL Device Control Size 16 bit Default 0000h Power Well Core Access PCI Configuration B D F 0 23 26 0 Eer Bit Range Default Access Acronym Description 15 Ob RO RSVD Reserved 14 12 000b RO MRRS Max Read Request Size Hardwired to 0 11 Ob RO ENS Enable No Snoop Not supported The root port will never issue non snoop requests AUX Power PM Enable This must be RW for OS testing The OS will set 10 Ob RW APME this bit to 1 if the device connected has detected AUX power It has no effect on the root port otherwise 09 Ob R
78. Default 80h Power Well Access D EX 31 Offset Start OEh PCI Configuration B D F X 31 0 Offset End OEh Bit Range Default Access Acronym Description 07 1 RO MED HERE Device This bit is 1 to indicate a multi function evice 06 00 00h RO HTYPE Header Type Identifies the header layout is a generic device 10 2 7 SS Subsystem Identifiers Register This register is initialized to logic O by the assertion of RESET B This register can be written only once after RESET B de assertion Table 282 Offset 2Ch SS Subsystem Identifiers Size 32 bit Default 00000000h Power Well Access D F X 31 Offset Start 2Ch PCI Configuration B D F X 31 0 Offset End 2Fh Bit Range Default Access Acronym Description 31 16 0000h RWO SSID Subsystem ID This is written by BIOS No hardware action is taken 15 00 0000h RWO SSVID Subsystem Vendor ID This is written by BIOS No hardware action Intel Atom Processor E6xx Series Datasheet 190 LPC Interface D31 FO n tel l 10 3 ACPI Device Configuration 10 3 1 SMBA SMBus Base Address Register Table 283 Offset 40h SMBA SMBus Base Address Size 32 bit Default 00000000h Power Well ACESS PCI Configuration B D F X 31 0 ye a aan Bit Range Default Access Acronym Description Enable 31 0 RW EN 1 Decode of the I O range pointed to by
79. Default Power Well Memory Mapped IO BAR RCBA Offset 0000h 0003h Bit Range Default Access Acronym Description 31 20 000h RO NEXT Next Capability Indicates the next item in the list 19 16 1h RO CV Capability Version ndicates the version of the capability structure 15 00 0005h RO CID Capability I D Indicates that this is a PCI Express link capability section of an RCRB Intel Atom Processor E6xx Series Datasheet 60 Register and Memory Mapping 5 5 1 2 Offset 0004h ESD Element Self Description Table 44 0004h ESD Element Self Description Size 32 bit Default Power Well Memory Mapped IO BAR RCBA Offset 0004h 0007h Bit Range Default Access Acronym Description 31 24 00h RO PN Port Number A value of 0 indicates the egress port Component ID This indicates the component ID assigned to this 23 16 00h RWO CID element by software This is written once by the platform BIOS and is locked until a platform reset 15 08 01h RO NLE Number of Link Entries Indicates that one link entry is described by this RCRB 07 04 0 RO RSVD Reserved d Element Type ndicates that the element type is a root complex 02 00 2h R ET internal link 5 5 1 3 Offset 0010h HDD Intel High Definition Audio Description Table 45 0010h HDD Intel High Definition Audio Description Size 32 bit Default
80. E A E E E 5 4 Register Access Method The registers and the connected devices can be accessed by the host through either a direct register access method or an indirect register access method 5 4 1 Direct Register Access 5 4 1 1 Hard Coded IO Access The Intel Atom Processor E6xx Series decodes the 16 bit address for a PORT IN and or PORT OUT from the CPU and directly accesses the register These addresses are unmovable Intel Atom Processor E6xx Series Datasheet 58 m e Register and Memory Mapping i n tel 5 4 1 2 5 4 1 3 5 4 1 4 5 4 2 5 4 2 1 5 4 2 1 1 Table 40 Note 5 4 2 1 2 10 BAR The Intel Atom Processor E6xx Series uses a programmable base address BAR to set a range of IO locations that it will use to decode PORT IN and or PORT OUT from the CPU and directly accesses a register s The BAR register is generally located in the PCI configuration space and is programmable by the BIOS OS Hard Coded Memory Access The Intel Atom Processor E6xx Series decodes CPU memory reads writes to memory locations not covered by system DRAM These locations are unmovable Memory BAR The Intel Atom Processor E6xx Series uses a programmable base address BAR to set a range of memory locations that it will use to decode CPU memory reads writes to memory locations not covered by system DRAM and directly accesses a register s The BAR register is generally located in PCI co
81. E6xx Series Datasheet 94 Graphics Video and Display Table 85 2Ch GVD SSI D Subsystem Identifiers Size 32 bit Default 00000000h Power Well Core Access D F 0 2 Offset Start 2Ch PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address OBh Bit Range Default Access Acronym Description The value in this field is programmed by the system BIOS According to SUBSYSTEM p the PCI spec only the BIOS can write it and only once after reset After 310 Oh WOARnROAW e the first write this register becomes read only The content of this ENTIFIERS e register may also be read not written from the Device 0 subsystem register address Table 86 34h GVD CAPPOI NT Capabilities Pointer Size 32 bit Default 000000DOh Power Well Core Access DF 0 2 Offset Start 34h PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 0Dh Bit Range Default Access Acronym Description 31 8 Diode RO RESERVED Reserved 7 0 DOh RO CAPABILITIES The first item in the capabilities list is at address DOh Table 87 3Ch GVD I NTR Interrupt Size 32 bit Default 00000100h Power Well Core Access D F 0 2 Offset Start 3Ch PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address OFh Bit Range Default Access Acronym Description 31 16 0000h RO RESERVED
82. Express Signals Signal Name Direction Reset Post Reset S3 S4 S5 PCIE PETp 3 0 0 pull up VOL off off PCIE_PETn 3 0 0 VOH VOH off off PCIE_PERp 3 0 l VI X unknown VI X unknown Off Off PCIE PERn 3 0 l VIX unknown VIX unknown Off Off PCIE_CLKINP PCIE_CLKINN l VIX unknown VIX unknown Off Off PCIE ICOMPO 1 0 High Z High Z Off Off PCIE ICOMPI 1 0 High Z High Z Off Off PCIE RCOMPO 1 0 High Z High Z Off Off PCIE_RBIAS 1 0 High Z High Z Off Off 3 5 Intel High Definition Audio Interface Signals Table 24 Intel High Definition Audio I nterface Signals Signal Name Direction Reset Post Reset S3 S4 S5 HDA RST B 0 VOL VOL off off HDA_SYNC 0 High Z High Z Off Off HDA_CLK 0 VOL VOL off off HDA_SDO 0 High Z High Z off off HDA_SDI 1 0 l Don t Care Don t Care Off Off HDA DOCKEN B O VOH VOH Off Off HDA_DOCKRST_B 0 VOH VOH off off Intel Atom Processor E6xx Series Datasheet 47 intel 3 6 Table 25 3 7 Table 26 3 8 Table 27 3 9 Table 28 Pin States LPC I nterface Signals LPC I nterface Signals Signal Name Direction Reset Post Reset S3 S4 S5 LPC AD 3 0 1 0 High Z High Z Off Off LPC_FRAME_B O VOH VOH Off Off LPC_SERIRQ 1 0 High Z High Z Off Off LPC_CLKRUN_B 1 0 VOL VOL Off Off LPC_CLKOUT 2 0 O VOH VOH Off Off SMBus Interface Signals
83. For B 1 Stepping this value is 02h 7 7 2 5 Offset 09h CC Class Codes Table 108 Offset 09h CC Class Codes Sheet 1 of 2 Size 24 bit Default 00000000h Power Well Core Access DE 0 2 Offset Start 09h PCI Configuration B D F 0 3 0 Offset End OBh Bit Range Default Access Acronym Description Refer to d gt 23 16 bit RO BCC Base Class Code ndicates a display controller descript For B 0 stepping this value is 03h For B 1 stepping this value is 04h ion Intel Atom Processor E6xx Series Datasheet 104 Graphics Video and Display Table 108 Offset 09h CC Class Codes Sheet 2 of 2 Size 24 bit Default 00000000h Power Well Core Access D F 0 3 Offset Start 09h PCI Configuration B D F 0 3 0 Offset End OBh Bit Range Default Access Acronym Description d 00h 80 Sub Class Code When GC VD is cleared this value is 00h When GC VD 15 08 h RO SCC is set this value is 80h 07 00 00h RO PI Programming I nterface ndicates a display controller 7 7 2 6 Offset OEh HDR Header Type Table 109 Offset OEh HDR Header Type Size 8 bit Default 00000000h Power Well Core Access DE 0 2 Offset Start OEh PCI Configuration B D F 0 3 0 Offset End OEh Bit Range Default Access Acronym Description 07 0 RO MFUNC Multi Function Status Integrated graphics is a single function 06 0
84. Graphics The following lists the key features of the 3D graphics engine Two pipe scalable unified shader implementation Intel Atom Processor E6xx Series Datasheet 75 m e n tel Graphics Video and Display 3D peak performance Fill rate two pixels per clock Vertex rate One triangle 15 clocks transform only Vertex Triangle ratio average 1 vtx tri peak 0 5 vtx tri Texture maximum size 2048 x 2048 Programmable 4x multi sampling anti aliasing MSAA Rotated grid SP performance related to AA mode TSP performance unaffected by AA mode Optimized memory efficiency using multi level cache architecture 7 2 2 Shading Engine Key Features The unified pixel vertex shader engine supports a broad range of instructions Unified programming model Multi threaded with four concurrently running threads Zero cost swapping in out of threads Cached program execution model unlimited program size Dedicated pixel processing instructions Dedicated vertex processing instructions 2048 32 bit registers SIMD pipeline supporting operations in 32 Bit IEEE Float 2 way 16 bit fixed point 4 way 8 bit integer 32 bit bit wise logical only Static and dynamic flow control Subroutine calls Loops Conditional branches Zero cost instruction predication Procedural geometry Allows generation of more primitives on output compared with inpu
85. Handling on Direct Memory Reads ssssssesssese nmm 257 384 Flash Protection Summary sssssssssesesesee eme emen eese sense emnes eser enn nnn 259 385 Flash Erase Time eti o rr retos Ae Seege Ae 261 386 Flash VEIREL A CR E REI USR EES 262 387 Watchdog Timer Register Summary IA F Base 10 View 264 388 00h PV1RO Preload Value 1 Register D 264 389 O1h PV1R1 Preload Value 1 Register 1 0 cece memes 265 390 02h PV1R2 Preload Value 1 Register 2 1 0 0 cece ene memes 265 391 04h PV2RO Preload Value 2 Register D 266 392 05h PV2R1 Preload Value 2 Register 1 266 393 06h PV2R2 Preload Value 2 Register 2 266 394 OCh RRO Reload Register 0 267 395 ODh RRI Reload Register 1 cece cece ee eee nemen e ener 267 396 10h WDTCR WDT Configuration Register 268 397 14h DCRO Down Counter Register 0 268 398 15h DCR1 Down Counter Register 1 00 nemen emen eene 269 399 16h DCR2 Down Counter Register 2 0 0 ccc nemen ememem esee nnns 269 400 18h WDTLR WDT Lock Register 269 401 Absolute Maximum Rating 274 402 Memory Controller Buffer Types ssssssssssseeem tenner 275 403 Thermal Design POWOGF erre rara PR REG CFT RR PEE Pr d c TR CR RE 276 404 DC Current Charactertstics cece ee eee e eme nated 276 405 Operating Condition Power Supply and Reference DC Characteristice 277 406 Active Signal DC Characteristics 00ocoocccccnconcononnanncnncononannconcn anna nn cnn rn
86. IO TRST B R2 M DQ 0 AK1 CMREF AG36 IOCMREF 334 M_DQ 1 AF1 COMPO 0 AJ30 IOCOMPO O0 N30 M DQ 10 ARA COMPO 1 AL34 IOCOMPO 1 L34 M DQ 11 AJA COMP1 0 AB35 IOCOMP1 0 T5 M DQ 12 AK5 COMP1 1 AB33 IOCOMP1 1 R6 M DQ 13 AP5 DLIOCMREF AC34 OGTLREF K33 M DQ 14 AM5 DLI OGTLREF AB37 LPC AD O D13 M DQ 15 AH5 GPE B N2 LPC AD 1 D3 M DQ 16 AU16 GPIO 0 E6 LPC_AD 2 G8 M_DQ 17 AU18 GPIO 1 CA LPC AD 3 G12 M DQ 18 AT17 GPIO 2 AG LPC CLKOUT 0 E12 M DQ 19 AT21 GPIO 3 D5 LPC_CLKOUT 1 D9 M_DQ 2 AJ2 GPIO 4 B5 LPC_CLKOUT 2 E10 M_DQ 20 AU22 GPIO SUS 0 L10 LPC_CLKRUN_B D7 M_DQ 21 AT23 GPIO SUS 1 N4 LPC_FRAME_B D11 M_DQ 22 AT19 GPIO SUS 2 P1 LPC_SERIRQ E8 M DQI 23 AU24 GPIO SUS 3 M3 LVD CLKN T37 M DQ 24 AN8 GPIO SUS 4 K11 LVD CLKP U36 M DQ 25 AP9 GPIO SUS 5 M1 LVD DATAN 0 U34 M DQ 26 AU12 GPIO SUS 6 L2 LVD DATAN 1 v31 M_DQ 27 AT11 GPIO_SUS 7 JA LVD DATAN 2 R36 M DQ 28 AP11 GPIO SUS 8 H1 LVD_DATAN_3 R34 M_DQ 29 AN10 GPIO B AP19 LVD DATAP 0 V33 M_DQ 3 AH1 GTLPREF AL30 LVD_DATAP_1 U30 M_DQ 30 AL10 GTLREF AH37 LVD_DATAP_2 P37 M DQI31 AT15 GTLVREF AP23 LVD DATAP 3 T33 M DQ 4 AG4 HDA CLK E36 LVD IBG R30 M DQ 5 AE4 HDA_DOCKEN_B F37 LVD_VBG T31 M DQ 6 AAA HDA DOCKRST B D35 LVD VREFH M37 M DQI7 ACA HDA RST B i P31 LVD VREFL N36 M DQI 8 AU6 HDA SDII 0 N32 M BS 0 AB5 M_DQ 9 AL4 HDA SDI 1 G36 M BS 1 AMI M DQS 0 Y5 HDA SDO J36 M_BS 2 AL2 M DQS 1 AT5 HDA SYNC F35 M CASB AP17 M DQS 2 AP15 M CKP AUS M DQS 3 AU14
87. L2 3 state the power management control logic will proceed with the entry into 3 S4 S5 Resuming from Suspended State The root port can detect a wake event through the WAKE B signal and wake the system When the root port detects WAKE B assertion an internal signal is sent to the processor power management controller to cause the system to wake up This internal message is not logged in any register nor is an interrupt GPE generated Device Initiated PM PME Message When the system has returned to SO a device requesting service sends PM PME messages until acknowledged by the processor If RSTS PS is cleared the root port sets RSTS PS and logs the PME Requester ID into RSTS RID If RSTS PS is set the root port sets RSTS PP and logs the PME Requester ID in a hidden register When RSTS PS is cleared the root port sets RSTS PS clears RSTS PP and moves the requester ID from the hidden register into RSTS RID Intel Atom Processor E6xx Series Datasheet 111 intel 8 1 2 4 8 1 3 8 1 3 1 8 2 8 2 1 Table 126 PCI Express If RCTL PIE is set an interrupt is generated If RCTL PIE is not set an SCI SMI_B may be set If RSTS PS is set and RCTL PIE is later written from a 0 to a 1 an interrupt is generated SMI SCI Generation To support power management on non PCI Express aware operating systems power management events can be routed to generate SCI by setting MPC PMCE In addition RTSTS PS and
88. Offset End Bit Range Default Access Acronym Description 07 0 RO CL Counter State When set OUT of the counter is set When cleared OUT of the counter is 0 Count Register When cleared indicates when the last count written to 06 Undef RO the Count Register CR has been loaded into the counting element CE and is available for reading The time this happens depends on the counter mode Read Write Selection These reflect the read write selection made through bits 5 4 of the control register The binary codes returned during the status read match the codes used to program the counter read write selection 05 04 Undef RO 00 Counter Latch Command 01 Read Write Least Significant Byte LSB 10 Read Write Most Significant Byte MSB 11 Read Write LSB then MSB Mode Returns the counter mode programming The binary code returned matches the code used to program the counter mode as listed under the bit function above Bits Mode Description 000 0 Out signal on end of count 20 03 01 Undef RO RSVD 001 1 Hardware retriggerable one shot x10 2 Rate generator divide by n counter x11 3 Square wave output 100 4 Software triggered strobe 101 5 Hardware triggered strobe 11 1 5 4 Offset 40h 41h 42h Counter Access Ports Register Table 302 40h 41h 42h Counter Access Ports Register Size 8 bit Default Undefined Power Well Core Access a m Offset Start 40h 41h 42h PCI Configuration B D F Offset End Bit Range Default Access Acro
89. Offset End 4Bh Bit Range Default Access Acronym Description 03 00 Oh RO RSVD Reserved 10 3 4 GPEOBLK GPEO BLK Base Address Register Table 286 Offset 4Ch GPEOBLK GPEO BLK Base Address Size 32 bit Default 00000000h Power Well Access D F X 31 Offset Start 4Ch PCI Configuration B D F X 31 0 Offset End 4Fh Bit Range Default Access Acronym Description Enable 31 0 RW EN 1 Decode of the IO range pointed to by the GPEOBASE BA is enabled 30 16 Oh RO RSVD Reserved S Base Address This field provides the 64 bytes of I O space for 15 06 Oh RW BA GPEO BLK 05 00 Oh RO RSVD Reserved 10 3 5 LPCS LPC Clock Strength Control Register The LPC Clock 2 and 1 are controlled via the SoftStrap software Table 287 Offset 54h LPCS LPC Clock Strength Control Sheet 1 of 2 Size 32 bit Default Power Well Access D F X 31 Offset Start 54h PCI Configuration B D F X 31 0 Offset End 57h Bit Range Default Access Acronym Description 31 19 Oh RO RSVD Reserved Clock 2 Enable 18 1b RW C2EN 1 Enabled 0 Disabled Clock 1 Enable 17 1b RW C1EN 1 Enabled 0 Disabled 16 06 Oh RO RSVD Reserved 05 1b RW C22M Clock 2 2m Strength Clock 2 2m Strength Control 04 1b RW C24M Clock 2 4m Strength Clock 2 4m Strength Control 03 1b RW C12M Clock 1 2m Strength Clock 1 2m Strength Control 02 1b RW C14M Clock 1 4m Strength Clock 1 4m Strength Control 01 1b RW CO2M Clock 0 2m Strength Clock 0 2m Strength Control
90. PMCES PME must be set and root port must be in D3hot power state by setting PMCS PS to generate SCI When set a power management event causes SMSCS PMCS to be set BIOS workarounds for power management are supported by setting MPC PMME When set power management events set SMSCS PMMS and SMI_B is generated This bit is set regardless of whether interrupts or SCI are enabled The SMI B may occur concurrently with an interrupt or SCI Additional Clarifications Non Snoop Cycles Are Not Supported The processor does not support No Snoop cycles on PCle DCTL ENS can never be set Platform BIOS must disable generation of these cycles in all installed PCle devices Generation of a No Snoop request by a PCle device may result in a protocol violation and lead to errors For example a no snoop read by a device may be returned by a snooped completion and this attribute difference a violation of the specification will cause the device to ignore the completion PCI Express Configuration Registers PCI Type 1 Bridge Header PCI Type 1 Bridge Header Sheet 1 of 2 Register Name Register Register Start Register End Default Value Access Symbol Vendor Identification VID 0 i 8086h RO Device Identification PIE 2 3 RO PCI Command CMD 4 5 0000h RO RW PCI Status PSTS 6 7 0010h RO RWC 01h for B 0 Revision Stepping Identification RID 3 3 02h for B 1 RO Stepping Class Code CC 060400h RO Cache
91. Power Well Memory Mapped IO BAR RCBA Offset 0010h 0013h Bit Range Default Access Acronym Description e Target Port Number Indicates that the target port number is 15 31 24 Fh RO PN Intel HD Audio Target Component ID This field returns the value of the ESD CID field 23 16 Variable RO TCID programmed by the platform BIOS since the root port is in the same component as the RCRB 15 02 0 RO RSVD Reserved 01 1 RO LT Link Type Indicates that the link points to a root port 00 1 RO LV Link Valid Link is always valid 5 5 1 4 Offset 0018h HDBA Intel High Definition Audio Base Address Table 46 0018h HDBA Intel High Definition Audio Base Address Size 64 bit Default Power Well Memory Mapped IO BAR RCBA Offset 0018h 008Fh Bit Range Default Access Acronym Description 63 32 Oh RO CBAU Config Space Base Address Upper Reserved 31 28 Oh RO CBAL Config Space Base Address Lower Reserved 27 20 Oh RO BN Bus Number Indicates Intel HD AudioP is on bus 0 19 15 1Bh RO DN Device Number Indicates Intel HD Audio is in device 27 14 12 Oh RO FN Function Number Indicates Intel HD Audio is in function 0 11 00 0 RO RSVD Reserved Intel Atom Processor E6xx Series Datasheet 61 Register and Memory Mapping 5 5 2 Interrupt Pin Configuration The following registers tell each
92. Registers c ccdessxcvdesstsonssekbencsieesscsasrdebesdedaeaane 157 10 0 LPC Interface D31 FO como edt Bae eet eerte eo La PEL ad KR PE 187 10 1 Functional Overview SEENEN RER ENNEN e SERES 187 10 1 1 Memory Cycle Notes eee eden enr ri teer reda eec ns er e pe ORE S 187 10 1 2 Intel Trusted Platform Module 1 2 Support 187 10 1 3 FWH Cycle Notes rece Head erm ee geg AAA Ed eben bim be er Vue iba FOR Seed 187 LO Lekt LPC Output COCKS curacion 187 10 2 PCI Configuration Registers cerner n creek Ad 188 10 2 1 ID CIdentiflers correre Poe Oe 188 10 2 2 CMD Device Command Register 189 10 2 3 STS Device Status Register 189 10 2 4 RID Revision ID Register 189 10 2 5 CC Class Code Register 190 10 2 6 HDTYPE Header Type Register 190 10 2 7 SS Subsystem Identifiers Register 190 10 3 ACPI Device CONF QUIALION crascio ee a re e ERR A A SNE ENEE A 191 10 3 1 SMBA SMBus Base Address Register 191 10 3 2 GBA GPIO Base Address Register 191 10 3 3 PMIBLK PMI BLK Base Address Register cceceeeeeeeeeeee teeta n 191 10 3 4 GPEOBLK GPEO BLK Base Address Register 192 10 3 5 LPCS LPC Clock Strength Control Register 192 10 3 6 ACTL ACPI Control Register 193 10 3 7 MC Miscellaneous Control Register 193 10 4 interrupt Control ict rese EEN A CR EIE E ERE tiers 195 10 4 1 PxRC PIRQx Routing Control Register 195 10 4 2 SCNT Serial IRQ Control Register 196 10 4 3
93. SMBus Interface Signals Signal Name Direction Reset Post Reset S3 S4 S5 SMB DATA 1 0 High Z High Z Off Off SMB_CLK 1 0 High Z High Z Off Off SMB_ALERT_B l High Z High Z off off SPI Interface Signals SPI Interface Signals Signal Name Direction Reset Post Reset S3 S4 S5 SPI MOSI O VOH VOH Off Off SPI_MISO l VIH VIH off off SPI_CS_B 1 0 VOH VOH Off Off SPI_SCK O VOL VOL Off Off Power Management Interface Signals Power Management I nterface Signals Sheet 1 of 2 Signal Name Direction Reset Post Reset S3 S4 S5 RESET B l VIH VIH VIL off PWROK l VIX unknown VIH VIL VIL RSMRST B l VIX unknown VIH VIH VIL RTCRST_B VIX unknown VIH VIH VIH SUSCLK O Running Running Running off WAKE_B l VIX unknown VIX unknown VIX unknown Off SLPMODE O VOL VOL VOL Off RSTWARN l VIH VIH VIH Off Intel Atom Processor E6xx Series Datasheet 48 Pin States Table 28 3 10 Table 29 3 11 Table 30 3 12 Table 31 Power Management I nterface Signals Sheet 2 of 2 Signal Name Direction Reset Post Reset S3 S4 S5 SLPRDY B O VOH VOH VOH Off RSTRDY_B O VOH VOH VOH Off GPE_B l VIX unknown VIX unknown VIX unknown off Real Time Clock I nterface Signals Real Time Clock Interface Signals Signal Name Direction Reset Post Reset S3 S4 S5 RTCX1 I Running Runnin
94. Series Datasheet 265 intel ACPI Devices 11 10 3 4 Offset 04h PV2RO Preload Value 2 Register O Table 391 04h PV2RO Preload Value 2 Register O Size 8 bit Default FFh Power Well Core Access gt m Offset Start 04h PCI Configuration B D F Offset End 04h IAF Base Address Base 10 Offset 04h Bit Range Default Access Acronym Description Preload Value 2 7 0 This register is used to hold the bits 0 through 7 of the preload value 2 for the WDT Timer The Value in the Preload Register is automatically transferred into the 35 bit down counter 07 00 FFh RW PLOAD2 7 0 The value loaded into the preload register needs to be one less than the intended period This is because the timer makes use of zero based counting i e zero is counted as part of the decrement Refer to Section 11 10 4 2 for details on how to change the value of this register 11 10 3 5 Offset 05h PV2R1 Preload Value 2 Register 1 Table 392 05h PV2R1 Preload Value 2 Register 1 Size 8 bit Default FFh Power Well Core MEUS PCI Configuration B D F SS 05h Offset End 05h IAF Base Address Base 10 Offset 05h Bit Range Default Access Acronym Description Preload Value 2 15 8 This register is used to hold the bits 8 through 15 of the preload value 2 for the WDT Timer The Value in the Preload Register is automatically transferred into the 35 bit down counter
95. Size 24 bit Default 060400h Power Well Core Access Offset Start 9h PCI Configuration B D F 0 23 26 0 Offset End Bh Bit Range Default Access Acronym Description Base Class Code This indicates the base class code for this device This 23 16 06h RO BCC code has the value 06h indicating a Bridge device Sub Class Code This indicates the sub class code for this device The 15 08 04h RO SUBCC code is 04h indicating a PCI to PCI bridge Programming Interface This indicates the programming interface of 07 00 00h RO Pl this device This value does not specify a particular register set layout and provides no practical use for this device Intel Atom Processor E6xx Series Datasheet 115 m e n tel PCI Express 8 2 1 7 CLS Cache Line Size Table 133 Offset OCh CLS Cache Line Size Size 8 bit Default 00h Power Well Core Access e Offset Start Ch PCI Configuration B D F 0 23 26 0 Offset End Ch Bit Range Default Access Acronym Description Cache Line Size Implemented by PCI Express devices as a read write 07 00 00h RW CLS field for legacy compatibility purposes but has no impact on any PCI Express device functionality 8 2 1 8 HTYPE Header Type This register identifies the header layout of the configuration space No physical register exists at this location Table 134 Offset OEh HTYPE Header Type
96. Supports partial writes through data mask pins Supports only soldered down DRAM configurations The memory controller does not support SODIMM or any type of DIMMs 1 3 3 Graphics The Intel Atom Processor E6xx Series provides integrated 2D 3D graphic engine that performs pixel shading and vertex shading within a single hardware accelerator The processing of pixels is deferred until they are determined to be visible which minimizes access to memory and improves render performance Intel Atom Processor E6xx Series Datasheet 27 1 3 5 1 3 6 1 3 6 1 1 3 6 2 1 3 7 1 3 8 intel DEN Video Decode The Intel Atom Processor E6xx Series supports MPEG2 MPEG4 VC1 WMV9 H 264 main baseline at L3 and high profile level 4 0 4 1 and Divx Video Encode The Intel Atom Processor E6xx Series supports MPEG4 H 264 baseline at L3 and VGA Display I nterfaces The Intel Atom Processor E6xx Series supports LVDS and Serial DVO display ports permitting simultaneous independent operation of two displays LVDS Interface The Intel Atom Processor E6xx Series supports a Low Voltage Differential Signaling interface that allows the Graphics and Video adaptor to communicate directly to an on board flat panel display The LVDS interface supports pixel color depths of 18 and 24 bits maximum resolution up to 1280x768 60 Hz Minimum pixel clock is 19 75 MHz Maximum pixel clock rate up to 80 MHz T
97. This field contains the current status of the delivery of 12 X RO DS this interrupt When set an interrupt is pending and not yet delivered When cleared there is no activity for this entry Destination Mode This field is used by the local APIC to determine 11 A RW DSM whether it is the destination of the message Delivery Mode This field specifies how the APICs listed in the destination field should act upon reception of this signal Certain Delivery Modes will only operate as intended when used in conjunction with a specific trigger mode These encodings are 000 Fixed 001 Lowest Priority 10 08 X RW DLM 010 SMI Not supported 011 Reserved 100 NMI Not supported 101 INIT Not supported 110 Reserved 111 ExtINT Vector This field contains the interrupt vector for this interrupt Values 07 00 RW VCT range between 10h and FEh Intel Atom Processor E6xx Series Datasheet 225 intel ge 11 4 3 11 4 4 11 4 4 1 11 4 4 2 11 4 4 3 11 4 4 4 Table 330 Unsupported Modes These delivery modes are not supported for the following reasons NMI INIT This cannot be delivered while the CPU is in the Stop Grant state In addition this is a break event for power management SMI There is no way to block the delivery of the SMI except through BIOS Virtual Wire Mode B The processor does not support the INTR of the 8259 routed to the I OxAPIC pin 0 Interrupt Delivery Theory of Operation Del
98. V Core Voltage 4 5 Ww 1 Notes 1 This spec is the Thermal Design Power and is the measured power generated in a component by a realistic application It does not represent the expected power generated by a power virus Studies by Intel indicate that no application will cause thermally significant power dissipation exceeding this specification although it is possible to concoct higher power synthetic workloads that write but never read Under realistic read write conditions this higher power workload can only be transient and is accounted in the AC max spec Table 404 DC Current Characteristics Symbol Parameter Signal Names Maxi Unit Notes luc Core Supply Voltage VCC 3500 mA 1 IVNN North Cluster Logic and Graphics Supply Voltage VNN 1600 mA 1 VCCP VCCF VCCPQ 1 05 V Supply Voltage DMI Fuses DDR digital VCCPDDR VCCPA VCCQ er mi VCCP Z i DPLL PCle 10 SDVO DPLL SDVO pads HPLL VCCA PEG VCCQHPLL VCCFHV lvccpsus 1 05 V Core Suspend Rail VCCDSUS 100 mA 1 livp VBG 1 25 V LVDS External Voltage Ref LVD_VBG 2 mA 1 1 5 V Sensors Core PLL Core Thermal Sensors lycca Voltages VCCA 120 mA 1 VCCD180 VCCA180 1 8 V Supply Voltage LVDS Digital Analog DDR VCC180 VCCSFR EXP 570 mA 1 VCCD180 1 O super filter regulators VCCSFRDPLL VCCSFRHPLL lvccp180SR 1 8V Supply Voltage DDR SR VCCD180SR 15 mA 1 eds or Supply Voltage Legacy IO SDVO pads RTC VCC
99. between AVos Complementary Output States 30 my lsg Short Circuit Current 24 mA 1 soc Short Circuit Common Current 24 mA Dynamic Offset 150 mV Ringback 50 70 90 mV Differential Clocks VswING Input swing 300 mV 7 8 VcRoss Crossing point 300 550 mV 7 H Vcross_var_ Vcross Variance 140 mv m Intel Atom Processor E6xx Series Datasheet 279 intel Table 406 Active Signal DC Characteristics Sheet 3 of 3 DC Characteristics Symbol Parameter Min Nom Max Unit Notes Vin Maximum input voltage 1 15 V 7 9 12 Vu Minimum input voltage 0 3 V 7 9 13 RTCRST PWROK RSMRST 2 0 BRE Vin Input high voltage E V 2 17 l Be i Stepping B1 0 78 Stepping Vu Input low voltage 0 5 V 0 68 BO i Stepping RTCX1 Vin Input high voltage 0 5 1 2 Vu Input low voltage 0 5 0 1 Notes 1 Vo lt Vpap lt Vit 2 For CMOS Open Drain signals defined in Table 406 Voy Voi and I_Eax DC specs are not applicable due to the pull up pull down resister that is required on the board 3 BSEL2 CFG 1 0 and TCK signals reference VCC not VTT 4 At VCC180 1 7 V 5 Specified at the measurement point into a timing and voltage compliance test load as shown in Transmitter compliance eye diagram of PCI Express specification and measured over any 250 consecutive TX Ul s Specified at the measurement point and measured over any 250 consecutive ULS The test load shown in receiv
100. bit to 1 when the SPI Cycle completes i e SCIP bit is O after software sets the GO bit This bit remains asserted until cleared by software writing a 1 or hardware reset When this bit is set and the SPI bit in Offset 02h SPIC SPI Control is 2 0 RWC CDS set an internal signal is asserted to the SMI generation block Software must make sure this bit is cleared prior to enabling the SPI SMI assertion for a new programmed access This bit gets set after the Status Register Polling sequence completes after reset deasserts It is cleared before and during that sequence 1 0 RV RSVD Reserved SPI Cycle In Progress Hardware sets this bit when software sets the SPI Cycle Go bit in the Offset 02h SPIC SPI Control This bit remains set until the cycle completes on the SPI interface Hardware automatically sets and clears this bit so that software can determine 0 1 RO SCIP when read data is valid and or when it is safe to begin programming the next command Software must only program the next command when this bit is O This bit reports 1b during the Status Register Polling sequence after reset deasserts it is cleared when that sequence completes Intel Atom Processor E6xx Series Datasheet 250 ACPI Devices 11 9 5 3 Table 374 Offset 02h SPIC SPI Control 02h SPIC SPI Control Size 16 bit Default 2005h Power Well Core Access PCI Configuration B D F 0 31 0 Offse
101. by the Processor Sheet 1 of 2 1 O Address Read Target Write Target Can be disabled 20h 3Ch 8259 Master 8259 Master No 40h 53h 8254 8254 No 61h 67h NMI Controller NMI Controller No 70h None NMI and RTC No 71h RTC RTC No 72h RTC NMI and RTC Yes with 73h 73h RTC RTC Yes with 72h Intel Atom Processor E6xx Series Datasheet 56 Register and Memory Mapping Table 37 5 3 1 2 Warning Table 38 5 3 2 Table 39 Fixed I O Range Decoded by the Processor Sheet 2 of 2 intel 1 O Address Read Target Write Target Can be disabled 74h RTC NMI and RTC No 75h RTC RTC No 76h RTC NMI and RTC No 77h RTC RTC No 84h 86h Internal Internal No 88h Internal Internal No 8Ch 8Eh Internal Internal No AOh ACh 8259 Slave 8259 Slave No BOh 8259 Slave 8259 Slave No B2h B3h Power Management Power Management No B4h BCh 8259 Slave 8259 Slave No 3B0h 3BBh VGA VGA Yes 3COh 3DFh VGA VGA Yes CF8h CFCh Internal Internal No CF9h Reset Generator Reset Generator No Variable I O Address Range Table 38 shows the variable I O decode ranges They are set using base address registers BARs or other configuration bits in various configuration spaces The PnP software PCI or ACPI can use their configuration mechanisms to set and adjust these values The variable I O ranges should not be set to conflict with the fixed I O ranges T
102. e programmed for output 11 7 2 6 Offset 34h RGGPE Resume Well GPI O GPE Enable Table 355 34h RGGPE Resume Well GPI O GPE Enable Size 32 bit Default 00000000h Power Well Resume Access D E 0 31 Offset Start 34h PCI Configuration B D F 0 31 0 Offset End 37h Memory Mapped IO BAR GPIO BAR 10 Offset Bit Range Default Access Acronym Description 31 09 0 RO RSVD Reserved 08 00 00 RW EN Sieg When set when RGTS TS n is set the ACPI GPEOS GPIO bit will Intel Atom Processor E6xx Series Datasheet 239 intel Series 11 7 2 7 Offset 38h RGSMI Resume Well GPI O SMI Enable Table 356 38h RGSMI Resume Well GPIO SMI Enable Size 32 bit Default 00000000h Power Well Resume Access PCI Configuration B D F 0 31 0 g A Memory Mapped IO BAR GPIO BAR 10 Offset Bit Range Default Access Acronym Description 31 09 0 RO RSVD Reserved 08 00 00 RW EN boo When set when RGTS TS n is set the ACPI SMIS GPIO bit will e set 11 7 2 8 Offset 3Ch RGTS Resume Well GPIO Trigger Status Table 357 3Ch RGTS Resume Well GPIO Trigger Status Size 32 bit Default 00000000h Power Well Resume Access D F 0 31 Offset Start 3Ch PCI Configuration B D F 0 31 0 Offset End 3Fh Memory Mapped IO BAR GPIO_BAR 10 Offset Bit Range Default Access Acronym Description 31 09 0 RO RSVD Reserved Trigger Status When set the corres
103. exact electrical level of that input is unknown Running The clock is toggling or the signal is transitioning because the function has not stopped Off The power plane for this signal is powered down The processor does not drive outputs and inputs should not be driven to the processor System Memory Signals System Memory Signals Sheet 1 of 2 Signal Name Direction Reset Post Reset S3 S4 S5 M ODT 1 0 High Z High Z High Z High Z M CKP O High Z Vou High Z High Z M CKN O High Z VoL High Z High Z M_CKE 1 0 O High Z VoL VoL VoL M CSB 1 0 Oo High Z Vou High Z High Z M_RASB O High Z Vou High Z High Z M_CASB O High Z Von High Z High Z M_WEB O High Z Vou High Z High Z M_BS 2 0 Oo High Z VoL High Z High Z M MA 14 0 O High Z VoL High Z High Z M DQ 31 0 1 0 High Z High Z High Z High Z M_DQS 3 0 1 0 High Z High Z High Z High Z Intel Atom Processor E6xx Series Datasheet 45 n tel j Pin States Table 20 System Memory Signals Sheet 2 of 2 Signal Name Direction Reset Post Reset S3 S4 S5 M DM 3 0 0 High Z High Z High Z High Z VIX VIX M_RCVENIN l VIX unknown VIX unknown Gnknowii nlknowti M RCVENOUT 0 High Z VoL High Z High Z VIX VIX M RCOMPOUT l VIX unknown VIX unknown nknowi nknown 3 3 Integrated Display Interfaces 3 3 1 LVDS Signals Table 21 LVDS Signals
104. except the SRST bit itself and FIFO s for the corresponding stream are reset After the stream hardware has completed sequencing into the reset state it will report a 1 in this bit Software must read a 1 from this bit to verify that the stream is in reset The RUN bit must be cleared before SRST is asserted 9 3 2 1 33 Offset 83h A3h C3h E3h ISDOSTS ISD1STS OSDOSTS OSDISTS I nput Output Stream Descriptor 0 1 Status Register Table 258 83h A3h C3h E3h ISDOSTS ISD1STS OSDOSTS OSD1STS Input Output Stream Descriptor 0 1 Status Register Size 8 bit Default 00h Power Well Core Access D F 0 27 Offset Start 83h A3h C3h E3h PCI Configuration B D F 0 27 0 Offset End 83h A3h C3h E3h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 07 06 0 RW RO Reserved FI FO Ready For output streams the Intel High Definition Audio controller hardware will set this bit to a 1 while the output DMA FIFO contains enough data to maintain the stream on then link This bit 05 0 RO RO defaults to O on reset because the FIFO is cleared on a reset For input streams the Intel High Definition AudioP controller hardware will set this bit to 1 when a valid descriptor is loaded and the engine is ready for the RUN bit to be set Descriptor Error When set this bit Indicates that a serious error occurred during the fetch of a descriptor This could be a r
105. executing either the RDMSR or WRMSR instruction The RDMSR instruction will place the 64 bits of the MSR in the EDX EAX register pair The WRMSR writes the contents of the EDX EAX register pair into the MSR PCI Express PCI Express PCle is a high speed serial interface The PCle configuration is software compatible with the existing PCI specifications Rank A unit of DRAM corresponding to a number of SDRAM devices in parallel such that a full 64 bit data bus is formed Intel Atom Processor E6xx Series Datasheet 24 Introduction intel Term Description SCI System Control Interrupt SCI is used in the ACPI protocol SDRAM Synchronous Dynamic Random Access Memory SDVO Serial Digital Video Out SDVO is a digital display channel that serially transmits digital display data to an external SDVO device The SDVO device accepts this serialized format and then translates the data into the appropriate display format i e TMDS LVDS TV Out SDVO Device Third party codec that uses SDVO as an input may have a variety of output formats including DVI LVDS HDMI TV Out etc SERR System Error SERR is an indication that an unrecoverable error has occurred on an I O bus SMC System Management Controller or External Controller refers to a separate system management controller that handles reset sequences sleep state transitions and other system management tas
106. field in Dword granularity The DMA engine fetches commands 07 00 0 RW CORBWP from the CORB until the Read Pointer matches the Write Pointer Supports 256 CORB entries 256 x 4B 1KB This field may be written while the DMA engine is running 9 3 2 1 18 Offset 4Ah CORBRP CORB Read Pointer Register Table 243 4Ah CORBRP CORB Read Pointer Register Sheet 1 of 2 Size 16 bit Default 0000h Power Well Core Access PCI Configuration B D F 0 27 0 Offset Start 4Ah Offset End 4Bh Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 15 0 RW RSVD CORB Read Pointer Reset Software writes a 1 to this bit to reset the CORB Read Pointer to 0 and clear any residual prefetched commands in the CORB hardware buffer within the Intel HD Audio controller The hardware will physically update this bit to 1 when the CORB Pointer reset is complete Software must read a 1 to verify that the reset completed correctly Software must clear this bit back to 0 and read back the 0 to verify that the clear completed correctly The CORB DMA engine must be stopped prior to resetting the Read Pointer or else DMA transfer may be corrupted 14 08 0 RO CORBWP Reserved Intel Atom Processor E6xx Series Datasheet 168 Intel High Definition Audio D27 FO Table 243 4Ah CORBRP CORB Re
107. i D F 0 27 Offset Start 04h PCI Configuration B D F 0 27 0 Offset End 05h Bit Range Default Access Acronym Description 00 0 RO RSVD Reserved 9 3 1 4 Offset 06h PCISTS PCI Status Register Table 181 06h PCISTS PCI Status Register Size 16 bit Default 0010h Power Well Core Access D FE 0 27 Offset Start 06h PCI Configuration B D F 0 27 0 Offset End 07h Bit Range Default Access Acronym Description 15 05 0 RO RSVD Reserved Capabilities List Exists Hardwired to 1 Indicates that the controller 04 1 RO CAP LIST contains a capabilities pointer list The first item is pointed to by looking at configuration offset 34h Interrupt Status 03 0 RO IS 0 This bit is O after the interrupt is cleared 1 This bit is 1 when the INTx B is asserted 02 00 0 RO RSVD Reserved 9 3 1 5 Offset 08h RID Revision Identification Register Table 182 08h RID Revision Identification Register Size 8 bit Default Refer to bit description Power Well Core Access D FE 0 27 Offset Start 08h PCI Configuration B D F 0 27 0 Offset End 08h Bit Range Default Access Acronym Description Refer to 07 00 bit RO RID Revision ID Indicates the device specific revision identifier For the B 0 descript Stepping this value is 01h For the B 1 Stepping this value is 02h ion 9 3 1 6 Offset 09h CC Class Codes Register Table 183 O9h CC Class Codes Register Sheet 1 of 2 Size 24 bit Defaul
108. lal lal lal Tal 8 s ol o Toi Jo o Toi Jo n 6 1 lt Rad lt G lt lt s s s s lt s s s z d I zE 7 z z z z z SE Oo ga on o z zZ KE z z o o c5 CCQHPLL z ATETSTZT T2TS TS T Bd BO B Rd bd d 5 o e lt CCD VSSSENS m CCD ICCA_PEG ICCD_DPL T lt CCA PEG CCA PEG CCA PEG CCSFR EXP Ri CIE RBIAS DVO STALLP DVO BLUEP DVO STALLN v DVO_INTP DVO_GREENN DVO_INTN DVO_GREENP l8 Sl 5 8 1S fal l j le fs lal ei ys VS le lal le ol o ol jo Jo Jo fo Jo Jol o 7 e ol s o xl Isl sl sl sl sl sl sl sl Ix xz o 5 e 2 2 2 2 2 2 sl jal al 7 o 9 2 2 I2 2 12 2 ol o N o lt v lt lt lt lt lt lt lt lt lt lt lt lt d I 9 o e O Q e e e e e fe S O o e o o o o o o o o o o 7 D D N N n o CCSFRDPLL SS DVO_BLUEN DVO_REDP lt lt n n Intel Atom Processor E6xx Series Datasheet 287 intel Ballout and Package Information Figure 16 Intel Atom Processor E6xx Series Ball Map Sheet 4 of 5 L aa par jJ pa bes ap am A INIA CO C C C E3 S al fal al lal lal lal lal lal lal lal lal al lal lal s Ol TH Jo Jo jot oj oj Fo Toi Fo To Jo Jo o m o lt v lt ixi isl isl isl ixl sl Isi isl Is lt e a Si l5 S S 1S lo lo l l l l ei o Jal
109. logic TRST B must be driven asserted CMOS low during CPU power on Reset l JTAG Test Data In TDI is used to serially shift data and Oc TDI CMOS Core instructions into the TAP O JTAG Test Data Out TDO is used to serially shift data out LO TDO CMOS OD Core oF the device I JTAG Test Mode Select This signal is used to control the os CMOS core state of the TAP controller IO TCK CH Core JTAG Test Clock Provides the clock input for TAP controller I JTAG Test Reset Asynchronously resets the Test Access IO TRST B CMOS Core Port TAP logic IO TRST B must be driven asserted low during power on Reset Intel Atom Processor E6xx Series Datasheet 38 Signal Description 2 11 Miscellaneous Signals and Clocks Table 15 Miscellaneous Signals and Clocks Sheet 1 of 4 Signal Name Direction Type Power Well Description Legacy North Complex CMREF Power Core Non Strobe Signals Reference Voltage for DMI Externally set via passive voltage divider 1 KQ to Vccp 1 KO to Vss GTLREF Power Core Strobe Signals Reference Voltage for DMI Externally set via passive voltage divider 1 KQ to Vccp 1 KO to Vss COMPO 1 0 Core RCOMP Connected to high precision resistors on the motherboard Used for compensating DMI pull up pull down impedances COMPO 0 externally connects to 27 4 Q 1 to Vss COMPO 1 externally connects to 54 9 Q 196 to Vss COMP1 1 0
110. memory is called the RIRB engine Every command sent to a codec yields a response from that codec Some commands are broadcast type commands in which case a response will be generated from each codec A codec may also be programmed to generate unsolicited responses which the RIRB engine also processes The processor also supports Programmed O based Immediate Command Response transport mechanism that can be used by BIOS for memory initialization Docking The processor controls an external switch that is used to either electrically connect or isolate a dock codec in the docking station from the processor and the Intel HD AudioP codec s on the motherboard Prior to and during the physical docking process the dock codec will be electrically isolated from the processor s Intel HD Audio interface When the physical docking occurs software will be notified via ACPI control methods Software then initiates the docking sequence in the Intel HD AudioP controller The Intel HD AudioP controller manages the external switch such that the electrical connection between the dock codec and the processor s Intel HD AudioP interface occurs during the proper time within the frame sequence and when the signals are not transitioning The processor also drives a dedicated reset signal to the dock codec s It sequences the switch control signal and dedicated reset signal correctly such that the dock codec experiences a normal reset as specified in the In
111. nczfwoh fus_GfxDevID_nczfwoh 3 0 15 0 8086h RO VID PCI standard identification for Intel Table 78 04h GVD PCI CMDSTS PCI Command and Status Register Sheet 1 of 2 Size 32 bit Default 00100000h Power Well Core Access DIE 0 2 Offset Start 04h PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 01h Bit Range Default Access Acronym Description 31 21 Oh RO RESERVED Reserved CAPABILITY LI CAP Indicates that the CAPPOINT register at 34h provides an offset into 20 1b RO ST 7 PCI Configuration Space containing a pointer to the location of the first item in the list INTERRUPT ST IS Reflects the state of the interrupt in the graphics device Is set to 1 if 19 Ob RO ATUS 7 the aggregate display gfx ved vpb vec interrupt as determined by IIR and IER memory interface registers is set to 1 Otherwise is set to 0 18 16 Oh RO RESERVED Reserved 15 11 0000b RO RESERVED Reserved INTERRUPT DI ID When 1 blocks the sending of a Message bus interrupt The interrupt 10 Ob RW status is not blocked from being reflected in PCICMDSTS IS When 0 SABLE permits the sending of a Message bus interrupt 9 3 KC RO RESERVED Reserved BUS MASTER BME Enables GVD to function as a PCI compliant master When 0 blocks 2 Ob RW ENABLE the sending of MSI interrupts When 1 permits the sending of MSI interrupts MSE When set accesses to this device s memory space is enabled When 1 the GVD will compare scldo
112. rra rn rra nn nr nnn nnn 278 407 CEET 290 Intel Atom Processor E6xx Series Datasheet 20 Revision History Revision History Date Revision Description April 2013 005 Updated Section 5 2 Introduction on page 53 Updated Tab Updated Tab e 96 C4h GVD FD Functional Disable on page 99 e 104 Offset 00h ID Identifiers on page 103 Updated Section 11 10 1 Overview on page 263 Updated Section 11 10 4 2 Register Unlocking Sequence on page 270 Updated Tab Updated Tab Updated Tab Updated Tab Updated Tab page 277 Updated Tab e 363 05h HCMD Command Register on page 243 e 364 06h HDO Host Data 0 on page 244 e 365 07h HD1 Host Data 1 on page 244 e 404 DC Current Characteristics on page 276 e 405 Operating Condition Power Supply and Reference DC Characteristics on e 406 Active Signal DC Characteristics on page 278 July 2011 004 Updated Sec Updated Tab Updated Tab Updated Tab Updated Tab Updated Tab Updated Tab Updated Tab Updated Sec Updated Tab Updated Tab Updated Tab Updated Tab Updated Tab Updated Sec Updated Tab Updated Tab Updated Tab Updated Tab Updated Tab Updated Sec Updated Sec Updated Tab Updated Tab Updated Tab Updated Tab Characteristi tion 1 3 11 General Purpose I O GPIO on page 29 e 2 Intel Atom Processor E6xx Series SKU for Different Segments on page 30 e 11 SPI Interface Signals
113. set SDS FRDY is asserted when there are one or more packets available in the FIFO 19 15 0 RO RSVD Reserved 48 KHz Enable When set the processor adds one extra bitclk to every 14 0 RW 48k_EN twelfth frame When cleared it will use the normal functionality and send 500 bitclks per frame Dock Enable Signal Transition Select When set HDA DOCK EN B 13 0 RW DETS transitions off the falling edge of BCLK phase C When cleared HDA DOCK EN B transitions 1 4 BCLK after the falling edge of BCLK phase D Intel Atom Processor E6xx Series Datasheet 182 Intel High Definition Audio D27 FO Table 267 1000h EM1 Extended Mode 1 Register Sheet 2 of 2 Size 32 bit Default 0000 0000h Power Well Core Access D IEQ 27 Offset Start 1000h PCI Configuration B D F 0 27 0 Offset End 1003h Memory Mapped IO BAR Offset Bit Range Default Access Acronym Description 12 11 0 RW RSVD Reserved 10 06 0 RO RSVD Reserved Input Repeat Count Resets Software writes a 1 to clear the respective Repeat Count to 00h Reads from these bits return 0 05 04 0 wo IRCR Bit 5 Input Stream 1 Repeat Count Reset Bit 4 Input Stream 0 Repeat Count Reset 03 02 0 RO RSVD Reserved Output Repeat Count Resets Software writes a 1 to clear the respective Repeat Count to 00h Reads from these bits return 0 01 00 0 WO ORCR Bit 1 Output Stream 1 Repeat Count Reset Bit 0 Output St
114. sets itself to the default value Software must read the bit field to test if the value is supported after setting the bit field Intel Atom Processor E6xx Series Datasheet 178 Intel High Definition Audio D27 FO intel 9 3 2 1 38 Offset 90h BOh ISDOFI FOS I SD1FI FOS Input Stream Descriptor 0 1 FI FO Size Register Table 263 90h BOh ISDOFIFOS I SD1FI FOS Input Stream Descriptor 0 1 FI FO Size Register Size 16 bit Default 0077h Power Well Core Access PCI Configuration B D F 0 27 0 Offset Start 90h BOh Offset End 91h B1h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 15 08 0 RO RSVD Reserved 07 00 77h RO FIFOS FI FO Size Indicates the maximum number of bytes that could be fetched by the controller at one time This is the maximum number of bytes that may have been DMA d into memory but not yet transmitted on the link and is also the maximum possible value that the PICB count will increase by at one time The value in this field is different for input and output streams It is also dependent on the Bits per Sample setting for the corresponding stream Following table shows the values read written from to this register for input and output streams and for non padded and padded bit formats For Output Stream FIFOS is a RW field The default after reset is BFh
115. the 8259 will automatically perform a Non Specific EOI operation at the trailing edge of the last interrupt acknowledge pulse From a system standpoint this mode should be used only when a nested multi level interrupt structure is not required within a single 8259 The AEOI mode can only be used in the master controller Masking I nterrupts Masking on an Individual I nterrupt Request Each interrupt request can be masked individually by the Interrupt Mask Register IMR This register is programmed through OCW1 Each bit in the IMR masks one interrupt channel Masking IRQ2 on the master controller will mask all requests for service from the slave controller Special Mask Mode Some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control For example the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion Intel Atom Processor E6xx Series Datasheet 222 ACPI Devices 11 3 9 11 4 11 4 1 Table 325 11 4 1 1 11 4 1 2 11 4 1 3 The Special Mask Mode enables all interrupts not masked by a bit set in the Mask Register Normally when an interrupt service routine acknowledges an interrupt without issuing an EOI to clear the ISR bit the interrupt controller inhibits all lower priority requests In the Special Mask Mode any interrupts may be selectively ena
116. to the final display format The vertex pixel shader engine is described in Section 7 2 5 The pixel processing operations also have their own data scheduling function that controls image processor functions and the texture and shader routines Hidden Surface Removal The image processor takes the floating point results of the vertex processing and further converts them to polygons for rasterization and depth processing During depth processing the relative positions of objects in a scene relative to the camera are determined The surfaces of objects hidden behind other objects are then removed from the scene thus preventing the processing of un seen pixels This improves the efficiency of subsequent pixel processing Applying Textures and Shading After hidden surfaces are removed textures and shading are applied Texture maps are fetched mipmaps calculated and either is applied to the polygons Complex pixel shader functions are also applied at this stage Final Pixel Formatting The pixel formatting module is the final stage of the pixel processing pipeline and controls the format of the final pixel data sent to the memory It supplies the unified shader with an address into the output buffer and the shader core returns the relevant pixel data The pixel formatting module also contains scaling functions as well as a dithering and data format packing function Unified Shader The unified shader engine contains a specialized pr
117. value written to TOCV During run time TOCV can be read to find out when the next periodic interrupt will be generated Software is expected to remember the last value written to TOCV Periodic Mode Timer O only Example if the value written to TOCV is 00000123h then An interrupt will be generated when the main counter reaches 00000123h TOCV will then be adjusted to 00000246h Another interrupt will be generated when the main counter reaches 00000246h TOCV will then be adjusted to 00000369h When the incremented value is greater than the maximum value possible for TnCV the value will wrap around through O For example if the current value in a 32 bit timer is FFFFOOOOh and the last value written to this register is 20000 then after the next interrupt the value will change to 00010000h If software wants to change the periodic rate it writes a new value to TOCV When the timer s comparator matches the new value is added to derive the next matching point If software resets the main counter the value in the comparator s value register must also be reset by setting TOC TVS To avoid race conditions this should be done with the main counter halted The following usage model is expected Software clears GC EN to prevent any interrupts Software clears the main counter by writing a value of OOh to it Software sets TOC TVS Software writes the new value in TOCV Software sets GC EN to enable interrupts pc re SES Interrupt
118. version as IOxAPIC 11 4 2 3 Offset 10 11h 3E 3Fh RTE O 23 Redirection Table Entry Offset vector 0 10h 11h vector 1 12h 13h vector 23 3Eh 3Fh vector N 10h Nx2 in Hex 11h Nx2 in Hex Table 329 10 11h 3E 3Fh RTE O 23 Redirection Table Entry Size 64 bit Default Power Well Core Access Offset Start 10h PCI Configuration B D F Offset End 11h Bit Range Default Access Acronym Description 63 56 X RW DID Destination I D Destination ID of the local APIC 55 48 X RW EDID Extended Destination I D Extended destination ID of the local APIC 47 17 0 RO RSVD Reserved Mask When set interrupts are not delivered nor held pending When 16 1 RW MSK cleared and edge or level on this interrupt results in the delivery of the interrupt Trigger Mode When cleared the interrupt is edge sensitive When set 15 x n TM the interrupt is level sensitive Remote IRR This is used for level triggered interrupts its meaning is undefined for edge triggered interrupts This bit is set when I OxAPIC 14 X RW RI RR sends the level interrupt message to the CPU This bit is cleared when an EOI message is received that matches the VCT field This bit is never set for SMI NMI INIT or ExtINT delivery modes 13 X RW POL Polarity This specifies the polarity of each interrupt input When cleared the signal is active high When set the signal is active low Delivery Status
119. which function each device is connected to Serial I nterrupt Overview The interrupt controller supports a serial IRQ scheme The signal used to transmit this information is shared between the interrupt controller and all peripherals that support serial interrupts The signal line SERIRQ is synchronous to LPC clock and follows the sustained tristate protocol that is used by LPC signals The serial IRQ protocol defines this sustained tristate signaling in the following fashion S Sample Phase Signal driven low R Recovery Phase Signal driven high T Turn around Phase Signal released The interrupt controller supports 21 serial interrupts These represent the 15 ISA interrupts IRQO 1 3 15 the four PCI interrupts and the control signals SMI and I OCHKZ Serial interrupt information is transferred using three types of frames Intel Atom Processor E6xx Series Datasheet 227 intel Series 11 5 2 11 5 3 11 5 4 Table 332 Start Frame SERIRQ line driven low by the interrupt controller to indicate the start of IRQ transmission Data Frames IRQ information transmitted by peripherals The interrupt controller supports 21 data frames Stop Frame SERIRQ line driven low by the interrupt controller to indicate end of transmission and next mode of operation Start Frame The serial IRQ protocol has two modes of operation which affect the start frame Continuous Mode The interrupt controller is
120. with the clock driven by the Master After selecting a Slave by asserting the SPI CS signal the Master generates eight clock pulses per byte on the SPI SCK wire one clock pulse per data bit Data flows from master to slave on the SPI MOSI wire and from slave to master on the SPI MISO wire Data is setup and sampled on opposite edges of the SPI SCK signal Master drives data off of the falling edge of the clock and slave samples on the rising edge of the clock Similarly Slave drives data off of the falling edge of the clock The master has more flexibility on sampling schemes since it controls the clock Note SPI SCK flight times and the device SPI MISO max valid times indicate that the rising edge is not feasible for sampling the SPI MISO input at the master for a 22 MHz clock period with 5096 duty cycle 1 SPI supports 8 or 16 bit words however all devices on the supported list only operate on 8 bit words 2 SPI specifies that data can be shifted MSB or LSB first however all devices on the supported list only operate MSB first Figure 9 Basic SPI Protocol CLK CS MOSI MISO CLK CSI MOSI MISO Intel Atom Processor E6xx Series Datasheet 247 intel 11 9 4 1 1 11 9 4 1 2 11 9 4 1 3 11 9 4 1 4 Table 370 ACPI Devices The processor only supports Mode 0 Commands Addresses and Data are shifted most significant bit MSB first For the 24 bit address this means bit 23 is sh
121. 0 00h RO HDR Header Code Indicates a type 0 header format 7 7 2 7 Offset 10h MMADR Memory Mapped Base Address This register requests allocation for the IGD registers and instruction ports The allocation is for 512 KB Table 110 Offset 10h MMADR Memory Mapped Base Address Size 32 bit Default 00000000h Power Well Core Access D F 0 3 Offset Start 10h PCI Configuration B D F 0 3 0 Offset End 13h Bit Range Default Access Acronym Description 31 19 0000h RW BA eee ress Set by the OS these bits correspond to address signals 18 01 0000h RO RSVD Reserved 00 0 RO RTE Resource Type Indicates a request for memory space Intel Atom Processor E6xx Series Datasheet 105 intel Graphics Video and Display 7 7 2 8 Offset 14h I OBAR I O Base Address This register provides the base offset of 8 bytes of I O registers within this device Access to I O space is allowed in the DO state when CMD IOSE is set Access is disallowed in states D1 D3 or if CMD IOSE is cleared Access to this space is independent of VGA functionality Table 111 Offset 14h I OBAR I O Base Address Size 32 bit Default 00000001h Power Well Core Access D F 0 3 Offset Start 14h PCI Configuration B D F 0 3 0 Offset End 17h Bit Range Default Access Acronym Description 31 16 0000h RO RSVD Reserved 15 03 0000h RW BA a S
122. 0 0000h RW AC AD ISD1LVI ISD1 Last Valid Index 0000h RW RO AE AF ISD1FI FOW ISD1 FIFO Watermark 0004h RW RO BO B1 ISD1FIFOS ISD1 FIFO Size 0077h RO B2 B3 ISD1FMT ISD1 Format 0000h RW RO B8 BB ISD1BDPL ISD1 Buffer Descriptor List Pointer 0000_0000h RW RO WO CO C2 OSDOCTL Output Stream Descriptor 0 OSDO Control 04 0000h RW RO C3 C3 OSDOSTS OSDO Status 00h RWC RO C4 C7 OSDOLPIB OSDO Link Position in Buffer 0000 0000h RO C8 CB OSDOCBL OSDO Cyclic Buffer Length 0000 0000h RW CC CD OSDOLVI OSDO Last Valid Index 0000h RW RO CE CF OSDOFIFOW OSDO FIFO Watermark 0004h RW RO DO D1 OSDOFIFOS OSDO FIFO Size OOBFh RW RO D2 D3 OSDOFMT OSDO Format 0000h RW RO D8 DB OSDOBDPL OSDO Buffer Descriptor List Pointer 0000_0000h RW RO WO EO E2 OSDICTL Output Stream Descriptor 1 OSD1 Control 04 0000h RW RO E3 E3 OSD1STS OSD1 Status 00h RWC RO E4 E7 OSDILPIB OSD1 Link Position in Buffer 0000 0000h RO E8 EB OSD1CBL OSD1 Cyclic Buffer Length 0000_0000h RW EC ED OSDILVI OSD1 Last Valid Index 0000h RW RO EE EF OSD1FIFOW OSD1 FIFO Watermark 0004h RW RO FO Fl OSDIFIFOS OSD1 FIFO Size OOBFh RW RO F2 F3 OSDIFMT OSD1 Format 0000h RW RO F8 FB OSD1BDPL OSD1 Buffer Descriptor List Pointer 0000_0000h RW RO WO Vendor Specific Memory Mapped Registers 1000 1003 EM1 Extended Mode 1 0C00_0000h RW RO 1004 1007 INRC Input Stream Repeat Count 0000_0000h RO 1008 100B OUTRC Output Stream Repeat Count 0000_0000h RO 100C 100F FIFOTRK FIFO Tracking 000F F800h RO RW 1010 10
123. 0 3 0 Offset End C7h Bit Range Default Access Acronym Description Disable When set the function is disabled configuration space is 00 Oh RW D disabled 7 7 2 19 Offset EOh SWSCI SMI Software SCI SMI Table 121 Offset EOh SWSCI SMI Software SCI SMI Size 16 bit Default 0000h Power Well Core Access D F 0 3 Offset Start EOh PCI Configuration B D F 0 3 0 Offset End Elh Bit Range Default Access Acronym Description SCI or SC Event Select When set SCI is selected When cleared SMI 15 0 RWO MCS is selected 14 01 Oh RW SS Software Scratch Bits Used by software No hardware functionality 00 Oh RW SWSCI Software SCI Event If MCS is set setting this bit causes an SCI 7 7 2 20 Offset E4h ASLE System Display Event Register Table 122 Offset E4h ASLE System Display Event Register Size 32 bit Default N A Power Well Core Access DF 0 3 Offset Start E4h PCI Configuration B D F 0 3 0 Offset End E7h Bit Range Default Access Acronym Description ASLE eraten indue Wren written this scratch byte triggers an interrupt when IER bit 0 is enabled and IMR bit 0 is unmasked If written 31 24 N A RW AST3 as part of a 16 bit or 32 bit write only one interrupt is generated in common 23 16 N A RW AST2 ASLE Scratch Trigger 2 Same definition as AST3 15 08 N A RW AST1 ASLE Scratch Trigger 1 Same definition as AST3 07 00 N A RW ASTO ASLE Scratch Trigger 0 Same definition as AST3 7 7 2 21 Offset FOh GCR Graphics Cloc
124. 00 0000h RO 114 117 VCOCTL VCO Resource Control 8000_00FFh RW RO 11A 11B VCOSTS VCO Resource Status 0000h RO 11C 11F VCICAP VC1 Resource Capability 0000 0000h RO 120 123 VCICTL VC1 Resource Control 0000_0000h RW RO 126 127 VC1STS VC1 Resource Status 0000h RO 130 133 RCCAP Root Complex Link Declaration Enhanced Capability Header 0001_0005h RO Intel Atom Processor E6xx Series Datasheet 141 intel Intel High Definition Audio D27 FO Table 177 Intel High Definition AudioP PCI Configuration Registers Sheet 3 of 3 Start End Symbol Register Name Reset Value Access 134 137 ESD Element Self Description OF00 0100h RO 140 143 LIDESC Link 1 Description 0000 0001 RO 148 14B LIADD Link 1 Address Register Variable RW RO 9 3 1 1 Offset 00h VI D Vendor Identification Table 178 00h VID Vendor Identification Size 16 bit Default 8086h Power Well Core Access D EO 27 Offset Start 00h PCI Configuration B D F 0 27 0 Offset End 01h Bit Range Default Access Acronym Description 15 00 8086h RO VID Vendor ID This is a 16 bit value assigned to Intel Intel VID 8086h 9 3 1 2 Offset 02h DID Device Identification Table 179 02h DID Device Identification Size 16 bit Default 811Bh Power Well Core Access D F 0 27 Offset Start 02h PCI Configuration B D F 0 27 0
125. 00 RW CHAN 0001 22 1111 16 9 3 2 1 41 Offset 98h B8h D8h F8h ISDOBDPL ISD1BDPL OSDOBDPL OSD1BDPL I nput Output Stream Descriptor 0 1 Buffer Descriptor List Pointer Register Table 266 98h B8h D8h F8h ISDOBDPL ISD1BDPL OSDOBDPL OSD1BDPL I nput Output Stream Descriptor 0 1 Buffer Descriptor List Pointer Register Sheet 1 of 2 Size 32 bit Default 0000 0000h Power Well Core Access DE 0 97 Offset Start 98h B8h D8h F8h PCI Configuration B D F 0 27 0 Offset End 9Bh BBh DBh FBh Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description Buffer Descriptor List Base Address Lower address of the Buffer 31 07 0 RW BDLBASE Descriptor List This value should only be modified when the RUN bit is 0 or DMA transfers may be corrupted Intel Atom Processor E6xx Series Datasheet 181 intel Intel High Definition Audio D27 FO Table 266 98h B8h D8h F8h ISDOBDPL ISD1BDPL OSDOBDPL OSD1BDPL I nput Output Stream Descriptor 0 1 Buffer Descriptor List Pointer Register Sheet 2 of 2 Size 32 bit Default 0000 0000h Power Well Core Access OmIE R39 Offset Start 98h B8h D8h F8h PCI Configuration B D F 0 27 0 Offset End 9Bh BBh DBh FBh Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 06 01 0 RO RSVD Reserved Protect When this b
126. 0100b indicates that the processor only supports 07 04 0100b RO CORBSZCAP CORB size of 256 CORB entries 1024B 03 02 0 RO RSVD Reserved 01 00 10b RO CORBSIZE irr eae Hardwired to 10b which sets the CORB size to 256 entries 9 3 2 1 22 Offset 50h RIRBBASE RIRB Base Address Register Table 247 50h RIRBBASE RIRB Base Address Register Size 32 bit Default 0000 0000h Power Well Core Access e D E 0 27 Offset Start 50h PCI Configuration B D F 0 27 0 Offset End 53h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description RI RB Base Address This field is the address of the Response Input Ring Buffer allowing the RIRB Base Address to be assigned on any 128 B 31 07 9 RW RIRBBASE boundary This register field must not be written when the DMA engine is running or the DMA transfer may be corrupted 06 00 0 RO RSVD Reserved 9 3 2 1 23 Offset 58h RIRBWP RIRB Write Pointer Register Table 248 58h RIRBWP RIRB Write Pointer Register Size 16 bit Default 0000h Power Well Core Access D E 0 27 Offset Start 58h PCI Configuration B D F 0 27 0 Offset End 59h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description RI RB Write Pointer Reset Software writes a 1 to this bit to reset the RIRB Write Pointer to 0 The RIRB DMA engine must be stopped prior to 15 0 WO IMRONWPRST resetting the Write Pointer or else DMA transfer may be corrupted This bit will always be read as 0 14 08 0 RO RSVD
127. 07 00 FFh RW PLOAD2_15_8 The value loaded into the preload register needs to be one less than the intended period This is because the timer makes use of zero based counting i e zero is counted as part of the decrement Refer to Section 11 10 4 2 for details on how to change the value of this register 11 10 3 6 Offset O6h PV2R2 Preload Value 2 Register 2 Table 393 06h PV2R2 Preload Value 2 Register 2 Sheet 1 of 2 Size 8 bit Default OFh Power Well Core Access PCI Configuration B D F Offset Start 06h Offset End 06h IAF Base Address Base 10 Offset 06h Bit Range Default Access Acronym Description 07 04 Oh Reserved Reserved Intel Atom Processor E6xx Series Datasheet 266 ACPI Devices Table 393 O6h PV2R2 Preload Value 2 Register 2 Sheet 2 of 2 Size 8 bit Default OFh Power Well Core Access PCI Configuration B D F Offset Start 06h Offset End 06h IAF Base Address Base 10 Offset 06h Bit Range Default Access Acronym Description Preload_Value_2 19 16 This register is used to hold the bits 16 through 19 of the preload value 2 for the WDT Timer The Value in the Preload Register is automatically transferred into the 35 bit down counter 03 00 Fh RW PLOAD2 19 16 The value loaded into the preload register needs to be one less than the intended period This is because the timer makes use of zero based counti
128. 0h D31IP Device 31 Interrupt Pin 62 5 5 2 2 Offset 3110h D27IP Device 27 Interrupt Pin 62 5 5 2 3 Offset 3118h DO2IP Device 2 Interrupt Pin 62 5 5 2 4 Offset 3120h D26IP Device 26 Interrupt Pin 63 5 5 2 5 Offset 3124h D25IP Device 25 Interrupt Pin 63 5 5 2 6 Offset 3128h D24IP Device 24 Interrupt Pin 63 5 5 2 7 Offset 312Ch D23IP Device 23 Interrupt Bin 63 5 5 2 8 Offset 3130h DO3IP Device 3 Interrupt Pin 64 5 5 3 Interrupt Route Conftouration nennen nens 64 5 5 3 1 Offset 3140h D31IR Device 31 Interrupt Route 64 5 5 3 2 Offset 3148h D27IR Device 27 Interrupt Route 65 5 5 3 3 Offset 314Ah D26IR Device 26 Interrupt Route 65 5 5 3 4 Offset 314Ch D25IR Device 25 Interrupt Route occccccccocncncconnno 65 5 5 3 5 Offset 314Eh D24IR Device 24 Interrupt Route 66 5 5 3 6 Offset 3150h D23IR Device 23 Interrupt Route 66 5 5 3 7 Offset 3160h DO2IR Device 2 Interrupt Route ccce 66 5 5 3 8 Offset 3162h DO3IR Device 3 Interrupt Route ccce 67 5 5 4 General Conftouration aa eee eee memes memes ens 67 5 5 4 1 Offset 3400h RC RTC Configuration ccc eee eee eneee 67 5 5 4 2 Offset 3410h BNT Boot Configuration cceceeeee ee ee eee teens 67 6 0 Memory Controller ri zen ter 69 61 COVE Visita pi 69 6 1 1 DRAM Frequencies and DatabRates nemen 69 6 2 DRAM Brengt ton 69 Intel Atom Processor E6xx Series Datasheet
129. 0h to BFFFFh If there is a match and MSE 1 and the SCL command is either MEMRD or MEMWR the GVD will initiate an RMdwvgamemen cr cycle on the RMbus If the RMbus returns a hit the 17 Ob RW VGA DISABLE GVD will select the command As well when 0 the GVD will check if scldown3_address 15 0 is one of the VGA IO register range The VGA IO range is 03BOh 03BBh and 03COh 03DFh If there is a match and IOSE 1 and the SCL command is either an IORD or IOWR the GVD will initiate a VGA register cycle on the RMbus If the RMbus returns a hit then the command will be claimed by the GVD When 1 the GVD will not check if the SCL address is in the VGA memory range or in the VGA IO register address range Also when the field is set 1 b1 and GMS 3 b000 then CC 15 8 is changed to 8 h80 from 8 h00 16 0 00000h RO RESERVED Reserved Intel Atom Processor E6xx Series Datasheet 96 Graphics Video and Display Table 89 5Ch GVD BSM Base of Stolen Memory Size 32 bit Default 00000000h Power Well Core Access D F 0 2 Offset Start 5Ch PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 17h Bit Range Default Access Acronym Description BSM This register contains bits 31 to 20 of the base address of stolen BASE OF STOU DRAM memory When the GVD receives a VGA memory
130. 1 2 1 1 Offset 000h GCID General Capabilities and ID 207 11 2 1 2 Offset 010h GC General Configuration sssssessssesese 207 11 2 1 3 Offset 020h GIS General Interrupt Status 208 11 2 1 4 Offset OFOh MCV Main Counter Value sees 208 11 2 1 5 Offset 100h 120h 140h T 0 2 C Timer 0 2 Config and jecur 208 11 2 1 6 Offset 108h 128h 148h T 0 2 CV Timer 0 2 Comparator Valll amp 2 5 rix Prix RA e Ie LIRE PM MENT P VERA INI I NE 209 11 2 2 Theory Of Operation aere rete mien ra eere end eor p YEA ERES Ee 210 11 2 2 1 Non Periodic Mode All Omer 210 11 2 2 2 Periodic Mode Timer O only 211 11 2 2 3 Interru pts EE 211 11 2 2 4 Mapping Option 2 Standard Option GC LRE cleared 212 11 3 8259 Interrupt Controller err rere mii ee ree t pec ane lA Fel Ee 212 AN CG Be e EE EE 212 SN Dee 213 11 3 2 1 Offset 20h AOh ICWI1 Initialization Command Word 1 213 11 3 2 2 Offset 21h A1h ICW2 Initialization Command Word 2 214 11 3 2 3 Offset 21h MICW3 Master Initialization Command Word 3 215 11 3 2 4 Offset Alh SICW3 Slave Initialization Command Word 3 215 11 3 2 5 Offset 21h Alh ICWA Initialization Command Word 4 Register 215 11 3 2 6 Offset 21h Alh OCW1 Operational Control Word 1 Interrupt MaSK C P 216 11 3 2 7 Offset 20h AOh OCW2 Operational Control Word 2
131. 10Dh Bit Range Default Access Acronym Description 15 00 0 RO RSVD Reserved 9 3 1 37 Offset 10Eh PVCSTS Port VC Status Register Table 214 10Eh PVCSTS Port VC Status Register Size 16 bit Default 0000h Power Well Core Access e D E 0 27 Offset Start 10Eh PCI Configuration B D F 0 27 0 Offset End 10Fh Bit Range Default Access Acronym Description 15 00 0 RO RSVD Reserved 9 3 1 38 Offset 110h VCOCAP VCO Resource Capability Register Table 215 110h VCOCAP VCO Resource Capability Register Size 32 bit Default 0000 0000h Power Well Core Access DE 0 97 Offset Start 110h PCI Configuration B D F 0 27 0 Offset End 113h Bit Range Default Access Acronym Description 31 00 0 RO RSVD Reserved Intel Atom Processor E6xx Series Datasheet 154 Intel High Definition Audio D27 FO j n tel 9 3 1 39 Offset 114h VCOCTL VCO Resource Control Register Table 216 114h VCOCTL VCO Resource Control Register Size 32 bit Default 8000 OOFFh Power Well Core Access D F 0 27 Offset Start 114h PCI Configuration B D F 0 27 0 Offset End 117h Bit Range Default Access Acronym Description 31 1 RO VCOEN VCO Enable Hardwired to 1 for VCO 30 08 0 RO RSVD Reserved TC VCO Map Bit 0 is hardwired to 1 since TCO is always mapped to 07 00 FFh RW RO VCOMAP VCO Bits 7 1 are impl
132. 13 IODPIB Input Stream 0 DMA Position in Buffer 0000 0000h RO 1014 1017 11DPIB Input Stream 1 DMA Position in Buffer 0000_0000h RO 1020 1023 OODPIB Output Stream 0 DMA Position in Buffer 0000_0000h RO 1024 1027 O1DPIB Output Stream 1 DMA Position in Buffer 0000_0000h RO 1030 1033 EM2 Extended Mode 2 0000_0000h RW RO 2030 2033 WLCLKA Wall Clock Counter Alias 0000_0000h RO 2084 2087 ISDOLPIBA ISDO Link Position in Buffer Alias 0000 0000h RO Intel Atom Processor E6xx Series Datasheet 159 tel Intel High Definition Audio D27 FO Table 225 Intel HD Audio Register Summary Sheet 3 of 3 Offset Offset Symbol Full Name Reset Value Access Start End 20A4 20A7 ISDILPIBA ISD1 Link Position in Buffer Alias 0000_0000h RO 2104 2107 OSDOLPIBA OSDO Link Position in Buffer Alias 0000_0000h RO 2124 2127 OSDILPIBA OSD1 Link Position in Buffer Alias 0000_0000h RO 9 3 2 1 1 Offset 00h GCAP Global Capabilities Register Table 226 00h GCAP Global Capabilities Register Size 16 bit Default 4401h Power Well Core Offset Start 00h Offset End 01h Access PCI Configuration B D F 0 27 0 Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description Number of Output Streams Supported 0010b indicates that the 15 12 0010 RO OSs processor Intel HD Audio controller supports two output streams Number of Input S
133. 173 256 70h DPBASE DMA Position Base Address Register 174 257 80h AOh COh EOh ISDOCTL ISD1CTL OSDOCTL OSDICTL Input Output Stream Descriptor 0 1 Control Register 175 258 83h A3h C3h E3h ISDOSTS ISD1STS OSDOSTS OSDISTS Input Output Stream Descriptor 0 1 Status Register 176 259 84h A4h C4h E4h ISDOLPIB ISDILPIB OSDOLPIB OSD1LPIB Input Output Stream Descriptor 0 1 Link Position in Buffer Register 177 260 88h A8h C8h E8h ISDOCBL ISD1CBL OSDOCBL OSD1CBL Input Output Stream Descriptor 0 1 Cyclic Buffer Length Register 177 261 8Ch ACh CCh ECh ISDOLVI ISD1LVI OSDOLVI OSD1LVI Input Output Stream Descriptor 0 1 Last Valid Index Register 177 262 8Eh AEh CEh EEh ISDOFIFOW ISDIFIFOW OSDOFIFOW OSD1FIFOW Input Output Stream Descriptor 0 1 FIFO Watermark Register 178 263 90h BOh ISDOFIFOS ISD1FIFOS Input Stream Descriptor 0 1 FIFO Size Register 179 264 DOh FOh OSDOFIFOS OSDIFIFOS Output Stream Descriptor 0 1 FIFO Size Register 179 265 92h B2h D2h F2h ISDOFMT ISDIFMT OSDOFMT OSDIFMT Input Output Stream Descriptor 0 1 Format Register 180 Intel Atom Processor E6xx Series Datasheet 17 inte Di 266 98h B8h D8h F8h ISDOBDPL ISD1BDPL OSDOBDPL OSD1BDPL Input Output Stream Descriptor 0 1 Buffer Descriptor List Pointer Register 181 267 1000h EM1 Extended Mode 1 Register 182 268 1004h INRC Input Stream Repeat Count Register
134. 2 and M3 PWRMODE states GTLVREF Core Voltage Reference for GPIO B 2 3 Vccp via external voltage divider 1 kQ to Vccp 2 KQ to vss BSEL 0 IERR CMOS Core Reference Frequency Select Internal Error Depending on PowerMode 2 0 PowerMode 2 0 BSEL I ERR Select MO INVALID M2 INVALID gt BSEL M3 M1 BSEL M5 IERR M7 M6 M4 Undef BSEL Combined with BSEL 1 and BSEL 2 Selects External Reference Clock and DDR frequencies 000 SKU_100 DDR 800 001 Reserved 010 Reserved 011 Reserved 100 Reserved 101 Reserved 110 Reserved 110 Reserved I ERR Internal Error indication debug Positively asserted Asserted when CPU has had an internal error and may have unexpectedly stopped executing Assertion of IERR is usually accompanied by a SHUTDOWN transaction internal to the processor which may result in assertion of NMI to the CPU The processor will keep IERR asserted until the POWERMODE pins take the processor to reset BSEL 2 1 CMOS Core Bus Frequency Select Like BSEL 0 IERR this pin reflects the processor External Reference Clock and DDR2 frequency PWRMODE 2 0 l CMOS Core Power Mode System management controller is expected to sequence the processor through various states using the POWERMODE pins to facilitate cold reset and warm reset BCLKP BLCKN Diff Core Reference Clock Differential 100 MHz
135. 2096 PCIE PERN 3 0 pull down 50 2096 SDVO REDP pull down 55 2096 SDVO REDN pull down 55 2096 SDVO GREENP pull down 55 2096 SDVO GREENN pull down 55 2096 SDVO BLUEP pull down 55 2096 SDVO BLUEN pull down 55 2096 SDVO TVCLKI NP pull down 50 2096 SDVO TVCLKI NN pull down 50 2096 SDVO INTP pull down 50 2096 SDVO INTN pull down 50 2096 SDVO CLKP pull down 55 2096 SDVO CLKN pull down 55 2096 SDVO STALLP pull down 50 2096 SDVO STALLN pull down 50 2096 Intel Atom Processor E6xx Series Datasheet 50 System Clock Domains 4 0 Table 34 System Clock Domains intel The Intel Atom Processor E6xx Series contains many clock frequency domains to support its various interfaces Table 34 summarizes these domains Intel Atom Processor E6xx Series Clock Domains Clock Domain Signal Name Frequency Source Usage Main clock Processor BCLKP BCLKN 100 MHz generator Processor reference clock HPLL REFCLK P Main clock Processor HPLL REFCLK N 100 MHz generator Processor reference clock Used by 8254 timers and HPET It Main clock runs at 14 31818 MHz This clock CIA SERIA 14 31818 MEE generator stops during S3 S4 and S5 states PCIE CLKINP Main clock PCI Express PCIE CLKINN 100 MHz generator PCI Express ports Primary clock source for display SDVO REFCLKP Display 96 MHz Main clock clocks and Intel High Definition reference clock SDVO_REFCLKN generator Audio RTCX1 RTC a
136. 24 Port 2 is device 25 and Port 3 is device 26 I nterrupt Generation The processor generates interrupts on behalf of hot plug and power management events when enabled These interrupts can either be pin based or can be MSIs When pin based the pin that is driven is based on the setting of the D23 24 25 261P and D23 24 25 26IR registers Table 125 summarizes interrupt behavior for Message Signal Interrupt MSI and wire modes In the table bits refers to the hot plug and PME interrupt bits MSI vs PCI IRQ Actions Interrupt Register Wire mode Action MSI Action All bits 0 Wire inactive No action One or more bits set to 1 Wire active Send message One or more bits set to 1 new bit gets set to 1 Wire active Send message One or more bits set to 1 software clears some but not all bits Wire active Send message One or more bits set to 1 software clears all bits Wire inactive No action pain clears one or more bits and one or more bits are set on Wire active Send message e same clock Power Management Sleep State Support Software initiates the transition to S3 S4 S5 by performing a write to PM1C SLPEN After the write completion has been returned to the CPU each root port will send a PME Turn Off message on its link The device attached to the link eventually responds with a PME TO Ack followed by a PM Enter L23 DLLP to enter L23 When all ports links are in the
137. 26 SECAP Slot eeler et 127 SLCTL Slot Control sre eee ia 127 KURT e TEE 128 RETL Ro0t CON Ol aiid ral EEGENEN 129 RCAP Root Capabilities cece cece cece r en En mmm memes 129 RSTS ROOY Status abere db eae ales tra ee e eet RAD 129 163 Offset 60h Intel Atom Processor E6xx Series Datasheet 15 ifte Di 164 PCI Bridge Vendor Capabilttv 0 teeta eaten nns 130 165 Offset 90h SVCAP Subsystem Vendor Capability sss 130 166 Offset 94h SVID Subsystem Vendor De 130 167 PCI Power Management Capability sssssssess meme enne 130 168 Offset AOh PMCAP Power Management Capability ID sse 131 169 Offset A2h PMC PCI Power Management Capabilities ssssseesn 131 170 Offset A4h PMCS PCI Power Management Control And Status 131 171 Port Configuratio sesonon eo IR ERROR X EMEN Ee PERI IUE E o 132 172 Offset D8h MPC Miscellaneous Port Configuration sss 133 173 Offset DCh SMSCS SMI SCI Status 2 0 een ee ener 134 174 Miscellaneous Conftouratton mm memes memes e mememe sis een 135 175 Offset FCh FD Functional Disable sss memes emen ene enne 135 17 6 External TE EE 140 177 Intel High Definition AudioP PCI Configuration Beglsters 140 178 00h VID Vendor Identification oocococcccocnccicoconnnnnnncnnnnnnnnnonnnnnr ememe sese enemies 142 179 02h DID Device Identtfcoetion enemi
138. 3 Values are exclusive of 5 tolerances 4 Battery Mode specification is the minimum voltage needed to maintain clock oscillation To start clock oscillation the device must first boot in normal mode Intel Atom Processor E6xx Series Datasheet 277 intel Table 406 Active Signal DC Characteristics Sheet 1 of 3 DC Characteristics Symbol Parameter Min Nom Max Unit Notes CMOS1 05 Vu Input Low Voltage 0 1 0 0 0 2 x Veco V Vin Input High Voltage 0 8 x Vccp VCCD Vccp 0 1 V VoL Output Low Voltage 0 1 0 0 1 x VCCD V Vou Output High Voltage 0 9 x Vccp VCCD VCCD 0 1 V lot Output Low Current 1 5 4 1 mA lou Output High Current 1 5 4 1 mA lu Input Low Current x 100 HA Cpad Pad Capacitance 0 95 1 2 1 45 pF CMOS1 05 Open Drain VoL Output Low Voltage 0 0 35 Vin Input High Voltage 0 8 x Vccp VCCD Vccp 0 1 V Vu Input Low Voltage 0 1 0 0 0 2 x Vccp lot Output Low Current 16 50 mA ligAK Input leakage Current 20 HA Cpad Pad Capacitance 1 9 2 2 2 45 pF CMOS3 3 CMOS3 3 Open Drain Vu Input Low Voltage 0 8 V Vin Input High Voltage 2 V VoL Output Low Voltage 0 4 V Vou Output High Voltage 2 4 V ees Output Low Current 8 mA loh Tor Output High Current 8 mA lo for CMOS3 3 Output Low Current 8 mA Open Drain ligAK Input Leakage Current 20 HA Cin Input Capacitance 1 3 5 pF Vccx Supply Voltage
139. 3 16 M DQS 1 matches M DQ 15 8 M DQS 0 matches M DQ 7 0 A 1 0 Data Mask One bit per byte indicating which bytes M_DM 3 0 CMOS1 8 Core should be written Receive Enable In active high Connects to M_RCVENIN CMOS1 8 Core M_RCVENOUT on the motherboard This input enables the M_DQS input buffers during reads o Receive Enable Out active high Connects to M_RCVENOUT CMOS1 8 Core M_RCVENIN on the motherboard Part of the feedback used to enable the M_DQS input buffers during reads l RCOMPOUT Connected to a reference resistor to M RCOMPOUT A Core dynamically calibrate the driver strengths Intel Atom Processor E6xx Series Datasheet 32 Signal Description 2 2 2 2 1 Table 5 Integrated Display Interfaces LVDS Signals LVDS Signals Signal Direction Type Power Well Description LVD DATAN O O Core Channel A Differential Data Output Negative LVDS Differential signal pair LVD DATAN 1 O Core Channel A Differential Data Output Negative LVDS Differential signal pair O Channel A Differential Data Output Negative LVD_DATAN_2 LVDS Core Differential signal pair LVD DATAN 3 O Core Channel A Differential Data Output Negative LVDS Differential signal pair LVD DATAP 0 O Core Channel A Differential Data Output Positive LVDS Differential signal pair O Channel A Differential Data Output Positive EVD DATARI LVDS Core Differ
140. 4 Contents i n tel 6 3 DRAM Partial WfriEGs iier beta d Ee nda dhl andar diecast din dudes ASS EEN AEN 69 6 4 DRAM Power Management 69 60 4 1 Powerdown MOdes erre ced tere densa sabe ve kr eer idan vedere een des 70 0 4 2 Self Refresh Mode nete ent LER Er e EL da ARR RR RR Rad Eh EN 70 6 4 3 Dynamic Self Refresh Mode ssssssssesessemen eene nee memes 70 6 4 4 Page Management 70 6 5 Refresh Mode coito 70 6 6 Supported DRAM Confiourations menses eene nens 71 6 7 Supported DRAM Devices ooocccccnccccnnncnnnnnnnnnnnnnnnnnnrnrnrnrnnnrnnrnr rre nenne nemen ene 72 6 8 Supported Rank Configurations sssssssssssss emnes eene eme enne 72 6 9 Address Mapping and Decodimg s emen 73 7 0 Graphics Video and Display 75 ZE Chapter Contents et ese 75 7 2 COMO Wisin ce ere ERE AMOR UE ID RO oa a 75 ZA 3D GFAphIES p 75 7 2 2 Shading Engine Key Features 76 7 2 3 Vertex Process aran tonta iaa 77 7 2 3 1 Vertex Transform Stages cccceee eee eee eee memes 77 7 2 3 2 Lighting Stages iis ori Eaei 77 7 2 4 Pixel Processing coc be e REOR E ERES YR ENEE LENA FE UR RENS 78 7 2 4 1 Hidden Surface Removal cnn nennnna ranas 78 7 2 4 2 Applying Textures and Shading sss 78 7 2 4 3 Final Pixel Formatting mmm memes 78 7 25 Unified SAA TEE 78 72226 Multi bevel Cache aiu ier te Etre tete t Rede LE Een m xen Rex XR E en 79 4 3 Video le 79 7 3 1 Supported Input F
141. 7h BDE BIOS Decode Enable FF000000h RO R W D8h DBh BC BIOS Control 00000100h RO R W FOh F3h RCBA Root Complex Base Address 00000000h R W RO 10 2 1 I D I dentifiers Table 276 Offset 00h ID Identifiers Sheet 1 of 2 Size 32 bit Default 81868086h Power Well Access ESA Offset Start 00h PCI Configuration B D F X 31 0 Offset End 03h Bit Range Default Access Acronym Description 31 16 8186h RO DID Device Identification PCI device ID for LPC Intel Atom Processor E6xx Series Datasheet 188 LPC Interface D31 F0 Table 276 Offset 00h ID Identifiers Sheet 2 of 2 Size 32 bit Default 81868086h Power Well Access E Offset Start 00h PCI Configuration B D F X 31 0 Offset End 03h Bit Range Default Access Acronym Description 15 00 8086h RO VID Vendor Identification This is a 16 bit value assigned to Intel 10 2 2 CMD Device Command Register Table 277 Offset 04h CMD Device Command Size 16 bit Default 0003h Power Well Access PR Offset Start 04h PCI Configuration B D F X 31 0 Offset End 05h Bit Range Default Access Acronym Description 15 02 0 RO RSVD Reserved 01 1 RO MSE Memory Space Enable Memory space cannot be disabled on LPC 10 2 3 STS Device Status Register Table 278 Offset O6h STS Device Status Size 16 bit Default 0000h Power Well Acce
142. AGTL Core Probe Mode Request Assertion is a Request for the CPU to enter probe mode CPU will response with PRDY_B assertion once it has entered PREQ B can be enabled to cause the CPU to break from C4 and C6 GTLPREF 1 0 Power Core Voltage Reference for GPIO B 2 3 Vccp via external voltage divider 1 kO to Vccp 2 KO to VSS PROCHOT B 1 0 I CMOS O OD Core Processor Hot CPU and optionally GMCH drives when it is throttling due to temperature Can also be an input which causes the CPU and optional GMCH to throttle External 22 1 1 Q resistor in series with 60 4 1 Q pull up to Vccp Intel Atom Processor E6xx Series Datasheet 39 intel Signal Description Table 15 Miscellaneous Signals and Clocks Sheet 2 of 4 Signal Name Direction Type Power Well Description GPIO B 1 0 AGTL Core General Purpose I O External Thermal Sensor Same pin type as BPM GPIO in this case is NOT the ACPI notion with lots of software configurability Instead this is essentially a spare pin that can be configured as a input or output which the microcontroller can respond to It can also be configured as an external thermal sensor input THERMTRIP_B 1 0 OD Core Catastrophic Thermal Trip The processor has reached an operating temperature that may damage the part Platform should immediately cut power to the processor THERMTRIP_B is not valid in MO M
143. AY Output Payload Capability Register 161 230 06h INPAY Input Payload Capability Register 161 231 08h GCTL Global Tu ge EE 162 232 OCh WAKEEN Wake Enable semen nee nenne memes 163 233 OEh STATESTS State Change Status sssssssssssessses nemen enemies 164 234 10h GSTS Global Status ote tH aaa 164 235 14h ECAP Extended Capabilities sss menm mmm 165 236 18h STRMPAY Stream Payload Capability Register 165 237 20h INTCTL Interrupt Control Register 165 238 24h INTSTS Interrupt Status Register 166 239 30h WALCLK Wall Clock Counter Register 167 240 38h SSYNC Stream Synchronization Register 167 241 40h CORBBASE CORB Base Address Register 168 242 48h CORBWP CORB Write Pointer Register 168 243 4Ah CORBRP CORB Read Pointer Register 168 244 4Ch CORBCTL CORB Control Register 169 245 4Dh CORBSTS CORB Status Register 169 246 4Eh CORBSIZE CORB Size Register 170 247 50h RIRBBASE RIRB Base Address Register 170 248 58h RIRBWP RIRB Write Pointer Register 170 249 5Ah RINTCNT Response Interrupt Count Register 171 250 5Ch RIRBCTL RIRB Control Register 171 251 5Dh RIRBSTS RIRB Status Register 172 252 5Eh RIRBSIZE RIRB Size Register 172 253 60h IC Immediate Command Reolster cece eee eee ee memes 173 254 64h IR Immediate Response Register 173 255 68h ICS Immediate Command Status sss emen eene
144. Access e g Offset Start 19h PCI Configuration B D F 0 23 26 0 Offset End 19h Bit Range Default Access Acronym Description e Secondary Bus Number This field is programmed by configuration 07 00 00h RW SCBN software with the bus number assigned to the PCI Express device 8 2 1 11 SBBN Subordinate Bus Number This register identifies the subordinate bus if any that resides at the level below the PCI Express device This number is programmed by the PCI configuration software to allow mapping of configuration cycles to the PCI Express device Table 137 Offset 1Ah SBBN Subordinate Bus Number Size 8 bit Default 00h Power Well Core Access e Offset Start 1Ah PCI Configuration B D F 0 23 26 0 Offset End 1Ah Bit Range Default Access Acronym Description Subordinate Bus Number This register is programmed by configuration software with the number of the highest subordinate bus 07 00 00h RW SBBN that lies behind the device bridge When only a single PCI device resides on the segment this register will contain the same value as the SCBN register 8 2 1 12 I OBASE I O Base Address This register controls the CPU to PCI Express I O access routing based on the following formula lO BASE lt address lt IO LIMIT Only the upper four bits are programmable For the purpose of address decode address bits A 11 0 are treated as O Thus the bottom of th
145. Atom Processor E6xx Series Datasheet 179 intel Intel High Definition Audio D27 FO Table 264 DOh FOh OSDOFIFOS OSD1FIFOS Output Stream Descriptor 0 1 FIFO Size Register Sheet 2 of 2 Size 16 bit Default OOBFh Power Well Core Access PCI Configuration B D F 0 27 0 Offset Start DOh FOh Offset End D1h F1h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 07 00 BFh RW FIFOS FI FO Size Indicates the maximum number of bytes that could be fetched by the controller at one time This is the maximum number of bytes that may have been DMA d into memory but not yet transmitted on the link and is also the maximum possible value that the PICB count will increase by at one time The value in this field is different for input and output streams It is also dependent on the Bits per Sample setting for the corresponding stream Following table shows the values read written from to this register for input and output streams and for non padded and padded bit formats For Output Stream FIFOS is a RW field The default after reset is BFh Value Output Streams OFh 16B 8 16 20 24 or 32 bit Output Streams 1Fh 32B 8 16 20 24 or 32 bit Output Streams 3Fh 64B 8 16 20 24 or 32 bit Output Streams 7Fh 128B 8 16 20 24 or 32 bit Output Streams BFh 192B 8 16 or 32 bit Output Streams FFh 256B 20 24 bit Output S
146. B signal independent of the state of the PME EN bit bit 8 in this register 14 09 0 RO RSVD Reserved PME Enable 08 0 RW pMEE 0 Disable d l 1 If corresponding PMES also set the Intel HD Audio controller sets the generates an internal power management event 07 02 0 RO RSVD Reserved Power State This field is uged both to determine the current power state of the Intel HD AudioP controller and to set a new power state The values are 00 DO state 11 D3HoT state Others Reserved Notes 01 00 00 RO PS If software attempts to write a value of 01b or 10b in to this field the write operation must complete normally however the data is discarded and no state change occurs When in the D3yo7 states the Intel HD Audio controller s configuration space is available but the I O and memory spaces are not Additionally interrupts are blocked When software changes this value from the D3 pop state to the DO state an internal warm soft reset is generated and software must re initialize the function Intel Atom Processor E6xx Series Datasheet 149 m n tel Intel High Definition Audio D27 FO 9 3 1 23 Offset 60h MSI CAPID MSI Capability ID Register Table 200 60h Mal CAPID MSI Capability I D Register Size 16 bit Default 0005h Power Well Core Access e D F 0 27 Offset Start 60h PCI Configuration B D F 0 27 0 Offset End 61h Bit Range Default Access Acronym Descriptio
147. CI Configuration B D F 0 27 0 RUE SH Bit Range Default Access Acronym Description 15 00 0000h RWO SID Subsystem ID These RWO bits have no functionality 9 3 1 14 Offset 34h CAP PTR Capabilities Pointer Register Table 191 34h CAP PTR Capabilities Pointer Register Size 8 bit Default 50h Power Well Core REESS PCI Configuration B D F 0 27 0 yero Sech Bit Range Default Access Acronym Description 07 00 50h RO TEE T ee IE 9 3 1 15 Offset 3Ch INTLN Interrupt Line Register Table 192 3Ch INTLN Interrupt Line Register Size 8 bit Default 00h Power Well Core Access PCI Configuration B D F 0 27 0 yc E a Bit Range Default Access Acronym Description Interrupt Line The processor does not use this field directly It is used 07 00 00h RW to communicate to software the interrupt line that the interrupt pin is connected to Intel Atom Processor E6xx Series Datasheet 146 Intel High Definition Audio D27 FO n tel 9 3 1 16 Offset 3Dh I NTPN I nterrupt Pin Register Table 193 3Dh INTPN Interrupt Pin Register Size 8 bit Default Variable Power Well Core Access D F 0 27 Offset Start 3Dh PCI Configuration B D F 0 27 0 Offset End 3Dh Bit Range Default Access Acronym Description 07 04 0 RO RSVD Reserved 03 00 0 RO Interrupt Pin This reflects the value of D271P ZIP Chipset Config a Registers Offset 3110h bits 3 0 9 3 1 17 Offs
148. CIECAP PCI Express Capabilities Register 151 206 74h DEVCAP Device Capabilities Register 151 207 78h DEVC Device Control iier eene ree aeree rci Nee ter le ed e n Re d 151 208 7Ah DEVS Device Status Register 152 209 FCh FD Function Disable Register 152 210 100h VCCAP Virtual Channel Enhanced Capability Header 153 211 104h PVCCAP1 Port VC Capability Register 1 sse 153 212 108h PVCCAP2 Port VC Capability Register 2 1 00 ccc eee eee mne 154 213 10Ch PVCCTL Port VC Control Register 154 214 10Eh PVCSTS Port VC Status Register 154 215 110h VCOCAP VCO Resource Capability Register 154 216 114h VCOCTL VCO Resource Control Register 155 217 11Ah VCOSTS VCO Resource Status Register 155 218 11Ch VCICAP VC1 Resource Capability Register 155 Intel Atom Processor E6xx Series Datasheet 16 Contents i n tel 219 120h VCICTL VC1 Resource Control Register 155 220 126h VC1STS VC1 Resource Status Register 156 221 130h RCCAP Root Complex Link Declaration Enhanced Capability Header Register 156 222 134h ESD Element Self Description Register 156 223 140h LIDESC Link 1 Description Register 157 224 148h L1ADD Link 1 Address Register 157 225 Intel HD AudioP Register Summary 158 226 00h GCAP Global Capabilities Register 160 227 02h VMIN Minor Version Register 160 228 03h VMAJ Major Version 161 229 04h OUTP
149. CR es ING i IN EE np e s L NL A Ic T Ne LL ieueevaee iss L las prora foo eon T Ne 3 DS CC Cc LL UCI Y 89 T L e S e T JN RER RRE Iv 9 T d L SIS O ET u T lwme SISI SS 1 r hwan s RR woms wowe S S EIDEL CA S S e proa LL fast C a ERR RRE FIA LIT m D sen Iesel SSES RTE RER KK e EE RR EECH DER EE TER RER Ro SS S R18 O CE s T EE s I TC F Moape SSAC T8 o 15 3 E ince Ride L1l free CS p ws Pexsecemsrs E O CU CN ws l spore Sie 1 ig O Een TESS _ YAA RO Fees Intel Atom Processor E6xx Series Datasheet 289 m e n tel Ballout and Package Information Table 407 Pin List Table 407 Pin List Table 407 Pin List Pin Name Ball Pin Name Ball Pin Name Ball BCLKP AT25 HIGHZ_B W2 M_CKN AT7 BCLKN AU26 HPLL_REFCLK_N WA M CKE 0 AK7 BPM BIO AP33 HPLL_REFCLK_P V5 M_CKE 1 AM7 BPM B 1 AP35 IO RX CVREF U4 M_CSB 0 AN14 BPM BI2 AN34 IO RX GVREF U2 M CSB 1 AJ12 BPM B 3 AN36 10_TCK T1 M_DM 0 AG2 BSEL O AM31 10_TDI AC2 M_DM 1 AF5 BSEL 1 AP21 10_TDO AD1 M_DM 2 AU20 BSEL 2 AP25 IO TMS AB1 M DM 3 AP13 CLK14 J8
150. Default Access Acronym Description 07 0 RO RSVD Reserved Timer Value Set This bit will return O when read Writes will only have 06 0 RO RW TVS an effect for Timer 0 if it is set to periodic mode Writes will have no effect for Timers 1 and 2 05 0 1 RO TS Timer Size 1 64 bits 0 32 bits Set for timer 0 Cleared for timers Periodic I nterrupt Capable When set hardware supports a periodic 04 0 1 RO PIC mode for this timer s interrupt This bit is set for timer 0 and cleared for timers 1 and 2 Timer Type If PIC is set this bit is read write and can be used to 03 0 RO RW TYP enable the timer to generate a periodic interrupt This bit is RW for timer 0 and RO for timers 1 and 2 Interrupt Enable When set enables the timer to cause an interrupt 02 0 RW IE when it times out When cleared the timer count and generates status bits but will not cause an interrupt Timer Interrupt Type When cleared interrupt is edge triggered When 01 0 RW IT set interrupt is level triggered and will be held active until it is cleared by writing 1 to GIS Tn If another interrupt occurs before the interrupt is cleared the interrupt remains active 00 0 RO RSVD Reserved 11 2 1 6 Offset 108h 128h 148h T 0 2 CV Timer 0 2 Comparator Value Reads to this register return the current value of the comparator The default value for each timer is all 1 s for the bits that are implemented Timer 0 is 64 bits wide Timers 1 and
151. EN EE sobs 45 20 System Memory Gionals ccc nemen memes deseen nenne nemen nnns 45 21 LVDS Signals ere Decet ae recie orta qe du new Re bella Orco Meta ew VR EDO gre 46 22 Serial Digital Video Output Signals cc memes emen nns 46 23 PCI Express Signals oe cho pee tid eccsteed es Sand iaa 47 24 Intel High Definition AudioP Interface Slonals eene 47 25 e an ee LEET 48 20 SMBus Interface Signals cree erbe ERR RE UR ERE TREE XX neha eee Ec FER Rd 48 27 SPI Interface Signals iaa ni Dti TT 48 28 Power Management Interface Glonals sse nene emnes 48 29 Real Time Clock Interface Gionals menm enemies 49 30 JTAG and Debug Interface Gionals mmm senem emnes 49 31 Miscellaneous Signals and Clocks sss emen memes 49 32 General Purpose I O Signals i ii ao eer iv eter Eege noc eer d err e dee 50 33 Integrated Termination Resistors cece memes nemen 50 34 Intel Atom Processor E6xx Series Clock Domaine 51 35 Register Access Types and Definitions csse memes 53 36 Memory Map MEET 55 37 Fixed I O Range Decoded by the brocessor mme enemies 56 38 Variable I O Range Decoded by the brocessor memes 57 39 PCI Devices and FUNCION Sucina AUS 57 40 PCI Configuration PORT CF8h Mapping 59 41 PCI Configuration Memory Bar Mapping ssssesnmmHmeHeemememe nens 60 42 PCI Express Capability List Structure 60 43 0000h RCTCL Root Complex Topology Capabilities Ust raros 60 44 0004h ESD E
152. ERN 1 E30 SDVO REFCLKN A10 VCC180 T13 PCIE PERN 2 B33 SDVO REFCLKP B11 VCC180 T15 PCIE PERN 3 C34 SDVO STALLN D19 VCC180 U14 PCIE PERP 0 A30 SDVO STALLP E20 VCC180 U16 PCIE PERP 1 D29 SDVO TVCLKINN A14 VCC180 W16 PCIE PERP 2 A32 SDVO TVCLKINP B15 VCC180 Y15 PCIE PERP 3 D33 SLPMODE M5 VCC180 AA16 PCIE PETN O0 E26 SLPRDY B K1 VCC180 AD15 PCIE PETN 1 E28 SMB ALERT B F7 VCC180 AG12 PCIE PETN 2 E32 SMB CLK E4 VCC180 AH9 PCIE PETN 3 G32 SMB DATA G14 VCC180 AH11 PCIE PETP 0 D25 SMI B H7 VCC180 AH13 Intel Atom Processor E6xx Series Datasheet 291 m e n tel Ballout and Package Information Table 407 Pin List Table 407 Pin List Table 407 Pin List Pin Name Ball Pin Name Ball Pin Name Ball VCC180 AH15 VCCPDDR W12 VSS C2 VCC180 AJ14 VCCPDDR AC12 VSS C6 VCC180 AK13 VCCPDDR AE12 vss C8 VCC180SR AB13 VCCPDDR AF13 VSS C10 VCC33RTC M13 VCCPQ AJ 16 VSS C12 VCCA AB25 VCCPSUS N12 VSS C14 VCCA AC14 VCCQ N26 VSS C16 VCCA AJ20 VCCQ P11 VSS C18 VCCA PEG H25 VCCQ AF27 VSS C20 VCCA PEG J18 VCCQHPLL N18 vss C22 VCCA_PEG J20 VCCRTCEXT L12 vss C24 VCCA_PEG IER VCCSENSE AJ 22 vss C26 VCCA_PEG j24 VCCSFR_EXP H19 vss C28 VCCA_PEG K21 VCCSFRDPLL H17 vss C30 VCCA_PEG K23 VCCSFRHPLL M15 vss C32 VCCA180 T27 VID O AU32 vss C36 VCCD L18 VID 1 AT29 vss D1 VCCD L20 VID 2 AL28 VSS D37 VCCD L22 VID 3 AP29 vss F3 VCCD L24 VID 4 AR34 vss F9 VCCD M25 VID 5 AT33 VSS F11 VCCD N22 VID 6 AT31 vss F13 VCCD N24 VIDEN O0 AK27 VSS F15
153. Embedded Intel Atom Processor E6xx Series Datasheet April 2013 Revision 005US Document Number 324208 005US INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILI TY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT A Mission Critical Application is any application in which failure of the Intel Product could result directly or indirectly in personal injury or death SHOULD YOU PURCHASE OR USE INTEL S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES SUBCONTRACTORS AND AFFILIATES AND THE DIRECTORS OFFICERS AND EMPLOYEES OF EACH HARMLESS AGAINST ALL CLAIMS COSTS DAMAGES AND EXPENSES AND REASONABLE ATTORNEYS FEES ARISING OUT OF DIRECTLY OR INDIRECTLY ANY CLAIM OF PRODUCT LIABILITY PERSONAL INJURY OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN MANUFACTURE OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS
154. F Enable Enables decoding of BIOS range FFF80000h FFFFFFFFh and FFB80000h FFBFFFFFh 31 1b RO EF8 0 Disable 1 Enable FO F8 Enable Enables decoding of BIOS range FFF00000h FFF7FFFFh and FFBOOOOOh FFB7FFFFh 30 1b RW EFO 0 Disable 1 Enable E8 EF Enable Enables decoding of BIOS range FFE80000h FFEFFFFFh and FFA80000h FFAFFFFFh 29 1b RW EE8 0 Disable 1 Enable EO E8 Enable Enables decoding of BIOS range FFE00000h FFE7FFFFh and FFA00000h FFA7FFFFh 28 1b RW EEO f 0 Disable 1 Enable Intel Atom Processor E6xx Series Datasheet 197 intel LPC Interface D31 FO Table 294 Offset D4h BDE BIOS Decode Enable Sheet 2 of 2 Size 32 bit Default FF000000h Power Well Access Se RAD mA Offset Start D4h PCI Configuration B D F X 31 0 Offset End D7h Bit Range Default Access Acronym Description D8 DF Enable Enables decoding of BIOS range FFD80000h FFDFFFFFh and FF980000h FF9FFFFFh 27 1b RW ED8 0 Disable 1 Enable DO D7 Enable Enables decoding of BIOS range FFD00000h FFD7FFFFh and FF900000h FF97FFFFh 26 1b RW EDO n 0 Disable 1 Enable C8 CF Enable Enables decoding of BIOS range FFC80000h FFCFFFFFh and FF880000h FF8FFFFFh 25 1b RW EC8 0 Disable 1 Enable CO C7 Enable Enables decoding of BIOS range FFC00000h FFC7FFFFh and FF800000h FF87FFFFh 24 1b RW ECO 0
155. For example if the current value in a 32 bit timer is FFFFOOOOh and the last value written to this register is 20000 then after the next interrupt the value will change to 00010000h Default value for each timer is all 1s for the bits that are implemented For example a 32 bit timer has a default value of 00000000FFFFFFFFh A 64 bit timer has a default value of FFFFFFFFFFFFFFFFh 11 2 2 Theory Of Operation 11 2 2 1 Non Periodic Mode All timers This mode can be thought of as creating a one shot When a timer is set up for non periodic mode it generates an interrupt when the value in the main counter matches the value in the timer s comparator register As timers 1 and 2 are 32 bit they will generate another interrupt when the main counter wraps TOCV cannot be programmed reliably by a single 64 bit write in a 32 bit environment unless only the periodic rate is being changed If TOCV needs to be reinitialized the following algorithm is performed 1 Set TOC TVS 2 Set the lower 32 bits of TOCV 3 Set TOC TVS 4 Set the upper 32 bits of TOCV Every timer is required to support the non periodic mode of operation Intel Atom Processor E6xx Series Datasheet 210 ACPI Devices 11 2 2 2 11 2 2 3 11 2 2 3 1 Table 310 intel When set up for periodic mode when the main counter value matches the value in TOCV an interrupt is generated if enabled Hardware then increases TOCV by the last
156. GRAPHICS_MO 110 DVMT UMA mode 48 MB of memory pre allocated for frame 22 20 Ollb RW DE SELECT buffer 111 DVMT UMA mode 64 MB of memory pre allocated for frame buffer When GMS not equal to 000 and VD 0 the GVD will check if the SCL address scldown3_address 31 0 is in the VGA memory range The VGA memory range is A0000h to BFFFFh If there is a match and MSE 1 and the SCL command is either a MEMRD or MEMWR the GVD will initiate an RMdwvgamemen cr cycle on the RMbus If the RMbus returns a hit the GVD will select the command As well when 0 the GVD will check if scldown3 address 15 0 is one of the VGA IO register range The VGA IO range is 03BOh 03BBh and 03COh 03DFh If there is a match and IOSE 1 and the SCL command is either an IORD or IOWR the GVD will initiate a VGA register cycle on the RMbus If the RMbus returns a hit the GVD will select the command When GMS is equal to 000 the GVD will not check if the SCL address is in the VGA memory range or in the VGA 10 register address range Also when GMS is set to 3 b000 then CC 15 8 is changed to 8 h80 from 8 h00 19 18 0 RO RESERVED Reserved VD When set VGA memory or I O cycles are not claimed and CC SCC is set to 80h When cleared VGA memory and I O cycles are enabled and CC SCC is set to 00h When 0 and GMS not equal to 000 the GVD will check if the SCL address scldown3_address 31 0 is in the VGA memory range The VGA memory range is A000
157. H 264 BP 128K QCIF 15 fps H 264 BP 192K QCIF 30 fps H 264 BP 384K CIF 15 fps or QVGA 20 fps H 264 BP 2M CIF 30 fps or QVGA 30 fps H 264 BP 10M Veh Gan ie fps 720x576 25 fps MPEG4 SP 64K QCIF 15 fps MPEG4 SP 128K QCIF 30 fps CIF 15 fps QVGA 15 fps MPEG4 SP 384K CIF 30 fps or QVGA 30 fps MPEG4 SP 128K QCIF 15 fps MPEG4 SP 384K QCIF 30 fps CIF 15 fps QVGA 15 fps MPEG4 SP 768K CIF 30 fps or QVGA 30 fps MPEG4 SP 8M T fps 720x576 25 fps H 263 BP 64K QCIF 15 fps H 263 BP 128K QCIF 30 fps CIF 15 fps QVGA 15 fps H 263 BP 384K CIF 30 fps QVGA 30 fps H 263 BP 2M CIF 30 fps QVGA 30 fps H 263 BP 128K QCIF 15 fps H 263 BP 4M CIF 60 fps H 263 BP 8M 720x240 60 fps 720x288 50 fps H 264 MP 14M 1280x720 30 fps MPEG4 SP 1280x720 30 fps H 263 BP 16M 720x480 60 fps 720x576 50 fps Encode Specifications Supported ITU T H 264 03 2005 Series H Audio visual and multimedia systems Infrastructure of audio visual services Coding of moving video Advanced video coding for generic audio visual services H 263 01 2005 Series H Audio visual and multimedia systems Infrastructure of audio visual services Coding of moving video Video coding for low bit rate communication MPEG4 06 2004 ISO IEC 14496 2 Second edition Information Technology Coding of audio visual objects Part 2 Visual Intel Atom Processor E6xx Series Datasheet 80
158. Host Block Data 244 11 8 3 e e 244 11 84 B s ArbitratiOn iode Fee RE gs EE E Ee a TE Roe TS RE SR QR RU red cg 245 11 8 5 BUS Eug e EE 245 11 8 5 1 Clock Stretching e EEN ANNE NEE Rea dne E RA RE ind 245 11 8 5 2 Bus TimeOout ern emen nnns 246 pas EEUU UTEM 246 11 9 Serial Peripheral Interface 246 11 9 1 Overview cr GO NEE AER ENEE ENEE DES E ENER AE 246 E TEE 246 11 9 3 External Interface 5 cerise eere c ela 246 119 4 WE e ee 247 11 9 4 1 SPI Pin Level Protocol eset eee ee nmn ne 247 11 9 5 Host Side Interface 249 11 9 5 1 SPI Host Interface Reoisters ccc eee eee e m 249 11 9 5 2 Offset 00h SPIS SPI Status 1 0 0 cece eee ee eae 250 11 9 5 3 Offset 02h SPIC SPI Control 251 11 9 5 4 Offset 04h SPIA SPI Address 252 11 9 5 5 Offset 08h SPIDO SPI Data 0 252 11 9 5 6 Offset 10h 18h 20h 28h 30h 38h 40h SPID 0 6 SPI Data N253 11 9 5 7 Offset 50h BBAR BIOS Base Address ssssssssesssses 253 11 9 5 8 Offset 54h PREOP Prefix Opcode Configuration 253 11 9 5 9 Offset 56h OPTYPE Opcode Type Configuration 254 11 9 5 100ffset 58h OPMENU Opcode Menu Configuration 254 11 9 5 110ffset 60h PBRO Protected BIOS Range 0 2 255 11 9 5 12Running SPI Cycles from the Host 256 11 9 5 13Generic Programmed Commande 258 11 9 5 14Flash Protecton me emen nn nnn nn 258 11 9 6 SP
159. I CIOCKIIDQ EE 260 11 9 7 BIOS Programming Considerations cssssssssseeen emm 260 11 9 7 1 Run Time Updates rtr a ENEE See EE 261 11 9 7 2 BIOS Sector Updates 261 11 9 7 3 SPI Initialization anii adi nns 262 11 10 Watchdog TIMET orent mesi tee ee mended eme stet ltda ace ane doe Torte Ra 263 Intel Atom Processor E6xx Series Datasheet 11 inte Di 11 10 LOVE Wii a paco 263 LT TO 2 Features ra eias una io E EA EAR PE 263 11 10 3Watchdog Timer Register Details 263 11 10 3 10ffset 00h PV1RO Preload Value 1 Register O sss 264 11 10 3 20ffset O1h PV1R1 Preload Value 1 Register 1 265 11 10 3 30ffset 02h PV1R2 Preload Value 1 Register 2 ssss 265 11 10 3 40ffset 04h PV2RO Preload Value 2 Register O sss 266 11 10 3 50ffset 05h PV2R1 Preload Value 2 Register 1 266 11 10 3 60ffset 06h PV2R2 Preload Value 2 Register 2 ssss 266 11 10 3 70ffset OCh RRO Reload Register 0 267 11 10 3 80ffset ODh RR1 Reload Register le 267 11 10 3 90ffset 10h WDTCR WDT Configuration Register 268 11 10 3 100ffset 14h DCRO Down Counter Register O ssssses 268 11 10 3 110ffset 15h DCR1 Down Counter Register 1 ssss 269 11 10 3 120ffset 16h DCR2 Down Counter Register 2 sss 269 11 10 3 130ffset 18h
160. IO 4 if OUTPUT is enabled Timer can be disabled default state or Locked Hard Reset required to disable WDT WDT Automatic Reload of Preload value when WDT Reload Sequence is performed In WDT mode users need to program the preload value 1 register to all 0 s Watchdog Timer Register Details All registers not mentioned are reserved Intel Atom Processor E6xx Series Datasheet 263 intel ACPI Devices Table 387 Watchdog Timer Register Summary IA F Base 10 View Offset Offset End Register D Description Default Start Value 00h 00h Offset 00h PV1RO Preload Value 1 Register 0 on page 264 FFh 01h 01h Offset O1h PV1R1 Preload Value 1 Register 1 on page 265 FFh 02h 02h Offset 02h PV1R2 Preload Value 1 Register 2 on page 265 OFh 04h 04h Offset 04h PV2RO Preload Value 2 Register 0 on page 266 FFh 05h 05h Offset 05h PV2R1 Preload Value 2 Register 1 on page 266 FFh 06h 06h Offset 06h PV2R2 Preload Value 2 Register 2 on page 266 OFh och och Offset OCh RRO Reload Register 0 on page 267 00h ODh ODh Offset ODh RR1 Reload Register 1 on page 267 00h 10h 10h Offset 10h WDTCR WDT Configuration Register on page 268 00h 14h 14h Offset 14h DCRO Down Counter Register 0 on page 268 00h 15h 15h Offset 15h DCR1 Down Counter Register 1 on page 269 00h 16h 16h Offset 16h DCR2 Down Counter Register
161. IOS and driver software Storage for up to 6 devices is 31 0 00h RW SCRATCH possible For each device the ASL control method requires two bits for DOD BIOS detectable yes or no VGA NonVGA one bit for DGS enable disable requested and two bits for DCS enabled now disabled now connected or not 7 7 2 D3 FO PCI Configuration Registers Table 103 PCI Header Sheet 1 of 2 Start End Symbol Register Name 00 03 ID Identifiers 04 05 CMD Command 06 07 STS Device Status 08 08 RID Revision Identification 09 0B cc Class Codes OE OE HTYPE Header Type 10 13 MMABR Memory Mapped Base Address 14 17 IOBAR I O Base Address 2C 2F SS Subsystem Identifiers Intel Atom Processor E6xx Series Datasheet 102 Graphics Video and Display Table 103 PCI Header Sheet 2 of 2 Start End Symbol Register Name 34 35 Ss Capabilities Pointer 3C 3D INTR Interrupt Information 58 5B SSRW Software Scratch Read Write 60 61 HSRW Hardware Scratch Read Write 90 91 MID Message Signaled Interrupts Capability 92 93 MC Message Control 94 97 MA Message Address 98 99 MD Message Data C4 C7 FD Functional Disable EO El PR Software SCI SMI SMI E4 E7 ASLE System Display Event Register FO Fl GCR Graphics Clock Ratio F4 F7 LBB Legacy Backlight Brightness 7 7 2 1
162. IRQ14 111 IRQ7 IRQ15 Intel Atom Processor E6xx Series Datasheet 214 ACPI Devices intel 11 3 2 3 Offset 21h MICW3 Master Initialization Command Word 3 Table 316 21h MICW3 Master Initialization Command Word 3 Size 8 bit Default Power Well Core Access GE Offset Start 21h PCI Configuration B D F Offset End Bit Range Default Access Acronym Description 07 03 Undef WO These bits must be programmed to zero Cascaded Controller Connection This bit must always be 02 Undef WO CCC programmed to a 1 to indicate the slave controller for interrupts 8 15 is cascaded on IRQ2 01 00 Undef WO These bits must be programmed to zero 11 3 2 4 Offset A1h SICW3 Slave Initialization Command Word 3 Table 317 Alh SICW3 Slave Initialization Command Word 3 Size 8 bit Default Power Well Core Access e Offset Start Alh PCI Configuration B D F Offset End Bit Range Default Access Acronym Description 07 03 X WO RSVD Reserved Must be 0 Slave I dentification Code This field must be programmed to 02h to 02 00 0 WO match the code broadcast by the master controller during the INTA sequence 11 3 2 5 Offset 21h Alh ICW4 Initialization Command Word 4 Register Table 318 21h A1h CW4 Initialization Command Word 4 Register Size 8 bit Default Power Well Core A
163. Identification This register combined with the Vendor Identification register uniquely identifies any PCI device Intel Atom Processor E6xx Series Datasheet 113 intel PCI Express Table 128 Offset 02h DID Device Identification Size 16 bit Default Power Well Core Access e Offset Start 2h PCI Configuration B D F 0 23 26 0 Offset End 3h Bit Range Default Access Acronym Description Device Identification Number Identifier assigned to the device virtual PCI to PCI bridge PCle Device 23 8184h 15 00 RO DID UB pCiex Device 24 8185h PCle Device 25 8180h PCle Device 26 8181h 8 2 1 3 CMD PCI Command Table 129 Offset 04h CMD PCI Command Size 16 bit Default 0000h Power Well Core Access g Offset Start 4h PCI Configuration B D F 0 23 26 0 Offset End 5h Bit Range Default Access Acronym Description 15 11 00h RO RSVD Reserved I nterrupt Disable This disables pin based INTx B interrupts on enabled hot plug and power management events When set internal INTx B messages will not be generated When cleared internal INTx B messages are generated if there is an interrupt for hot plug or power 10 Ob RW ID management This bit does not effect interrupt forwarding from devices connected to the root port Assert_INTx and Deassert_INTx messages will still be forwarded to the internal interrupt controllers if
164. KU and 1 6 GHz Premium SKU Macro operation execution support 2 wide instruction decode and in order execution On die 32 kB 4 way L1 Instruction Cache and 24 kB 6 way L1 Data Cache On die 512 kB 8 way L2 cache L2 Dynamic Cache Sizing 32 bit physical address 48 bit linear address size support Support for IA 32 bit architecture Supports Intel virtualization Technology Intel VT x Supports Intel Hyper Threading Technology two threads Advanced power management features including Enhanced Intel SpeedStep Technology Deep Power Down Technology C6 e Intel Streaming SI MD Extension 2 and 3 Intel SSE2 and Intel SSE3 and Supplemental Streaming SIMD Extensions 3 SSSE3 support 1 3 2 System Memory Controller Single channel DDR2 memory controller 32 bit data bus Supports DDR2 800 MT s data rates Supports 1 or 2 ranks Supports x8 or x16 DRAM chips Onerank two x16 or four x8 DRAM chips Two ranks two x16 DRAM chips per rank or four x8 DRAM chips per rank Supports up to 2 GB of extended memory Supports total memory size of 128 MB 256 MB 512 MB 1 GB and 2 GB Supports 256 Mb 512 Mb 1 Gb and 2 Gb chip densities for the x8 DRAM Supports 512 Mb 1 Gb and 2 Gb chip densities for the x16 DRAM Aggressive power management to reduce power consumption including shallow self refresh and a new deep self refresh support Proactive page closing policies to close unused pages
165. LBAR Offset Bit Range Default Access Acronym Description Last Valid I ndex The value written to this register indicates the index for the last valid Buffer Descriptor in the BDL After the controller has processed this descriptor it will wrap back to the first descriptor in the list 07 00 00h RW LVI and continue processing LVI must be at least 1 i e there must be at least two valid entries in the buffer descriptor list before DMA operations can begin This value should only be modified when the RUN bit is 0 9 3 2 1 37 Offset 8Eh AEh CEh EEh ISDOFI FOW I SD1FI FOW OSDOFI FOW OSD1FI FOW Input Output Stream Descriptor 0 1 FI FO Watermark Register Table 262 8Eh AEh CEh EEh ISDOFI FOW I SD1FI FOW OSDOFI FOW OSDIFI FOW Input Output Stream Descriptor 0 1 FIFO Watermark Register Size 16 bit Default 0004h Power Well Core Access e DE 0 97 Offset Start 8Eh AEh CEh EEh PCI Configuration B D F 0 27 0 Offset End 8Fh AEN CFh EFh Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 15 03 0 RO RSVD Reserved FI FO Watermark Indicates the minimum number of bytes accumulated free in the FIFO before the controller will start a fetch eviction of data 010 8B Supported 011 16B Supported 02 00 100b RW FIFOW 100 32B Supported Default other Unsupported Note When the bit field is programmed to an unsupported size the hardware
166. Line Size CLS C C 00h RW Header Type HTYPE E E 01h RO Primary Bus PBN 18 18 00h RW Number Secondary Bus SCBN 19 19 00h RW Number Intel Atom Processor E6xx Series Datasheet 112 PCI Express Table 126 intel PCI Type 1 Bridge Header Sheet 2 of 2 Register Name Register Register Start Register End Default Value Access Symbol Subordinate Bus Number SBBN 1A 1A 00h RW 110 Base IOBASE 1C 1C 00h RW RO Address 1O Limit IOLIMIT 1D 1D 00h RW RO Address Secondary S Status SSTS 1E 1F 0000h RWC RO Memory Base MB 20 21 0000h RW Address Memory Limit ML 22 23 0000h RW Address Prefetchable Memory Base PMB 24 25 0000h RW Address Prefetchable Memory Limit PML 26 27 0000h RW Address Capabilities CAPP 34 34 40h RO Pointer Interrupt Line ILINE 3C 3C 00h RW Interrupt Pin IPIN 3D 3D Olh RO Bridge Control BCTRL 3E 3F 0000h RO RW 8 2 1 1 VI D Vendor Identification This register combined with the Device Identification register uniquely identifies any PCI device Table 127 Offset 00h VI D Vendor Identification Size 16 bit Default 8086h Power Well Core Access Offset Start Oh PCI Configuration B D F 0 23 26 0 Offset End 1h Bit Range Default Access Acronym Description 15 00 8086h RO VID1 Vendor Identification PCI standard identification for Intel 8 2 1 2 DI D Device
167. MA Position in Buffer Register Size 32 bit Default 0000 0000h Power Well Core Access Offset Start 1010h 1014h 1020h i i D F 0 97 1024h PCI Configuration B D F 0 27 0 Offset End 1013h 1017h 1023h 1027h Memory Mapped IO BAR Offset Bit Range Default Access Acronym Description Position Indicates the number of bytes processed by the DMA engine 31 00 00h RO POS from the beginning of the BDL For output streams it is incremented when data is loaded into the FIFO Intel Atom Processor E6xx Series Datasheet 184 Intel High Definition Audio D27 FO 9 3 2 1 47 Offset 1030h EM2 Extended Mode 2 Register Table 272 1030h EM2 Extended Mode 2 Register Size 32 bit Default 0000_0000h Power Well Core Access DIE 0 27 Offset Start 1030h PCI Configuration B D F 0 27 0 Offset End 1033h Memory Mapped IO BAR Offset Bit Range Default Access Acronym Description 31 09 0 RO RSVD Reserved CORB Reset Pointer Change Disable When this bit is 0 the CORB Reset Pointer Reset works as described When this bit is set to 1 the 08 0 RW CORBRPDIS CORB FIFO is not reset and the CORB Reset Pointer Reset bit is Write Only and always read as 0 07 00 0 RO RSVD Reserved 9 3 2 1 48 Offset 2030h WLCLKA Wall Clock Alias Register Table 273 2030h WLCLKA Wall Clock Alias Register Size 32 bit Default 0000 0000h Power Well C
168. MMC Multiple Message Capable This device is only single message capable Intel Atom Processor E6xx Series Datasheet 107 Graphics Video and Display intel Table 117 Offset 92h MC Message Control Sheet 2 of 2 Size 16 bit Default 0000h Power Well Core Access D F 0 3 Offset Start 92h PCI Configuration B D F 0 3 0 Offset End 93h Bit Range Default Access Acronym Description MSI Enable If set MSI is enabled and traditional interrupts are not used to generate interrupts CMD BME must be set for an MSI to be generated Note Overall a MSI interrupt is sent when the expression IS amp ID amp 00 0 RW MSIE BME amp MSIE changes from 0 to 1 Overall a Message bus interrupt assert is sent when the expression IS amp ID MSIE changes from 0 to 1 The corresponding Message bus interrupt de assert is sent when the expression IS amp ID MSIE changes from 1 to 0 See IS description for conditions that cause IS bit to be set to 1 and cleared to 0 7 7 2 16 Offset 94h MA Message Address Table 118 Offset 94h MA Message Address Size 32 bit Default 00000000h Power Well Core Access D F 0 3 Offset Start 94h PCI Configuration B D F 0 3 0 Offset End 97h Bit Range Default Access Acronym Description Address Lower 32 bits of the system specified message address 31 02 0 RW ADDR always DW aligned 01 00 Oh R
169. MRST B O RX CVREF O RX GVREF on on OCOMP1 0 O TCK OCOMP 1 1 O TRST N PIO SUS 2 R P al lal lal lal lal Tal lal sl Tal Jal el OL Jo Jo jo Jo Jo o oO o al lal lal sl E 9 o fol z ls gt gt cop o e amp an Z ol z lo aj 16 o n c ul ISS Mes mes gt firmo A C ero sust RA LL Lm fosa y 7 js O aa RO ra RS RER RR ER RR EE CK 7 Res 1 Ews 1 fra 1 e feos ra e 222 RA Efes weems e fs gt gt e esma meu fea EC p Jero aro Jere amos oa Jen e e po Pp as gt dee 1 ws gt 34 JO sewer emos gt gt LI L eoa S 1 1 L Intel Atom Processor E6xx Series Datasheet 285 m e n tel Ballout and Package Information Figure 14 Intel Atom Processor E6xx Series Ball Map Sheet 2 of 5 LL AA wong Jesi 1 ar jw fs pa qe i Sid M CSB 0 M_ODT 1 vss RST_B Pp CC 180 Iwer vcctao VCCPDDR VCCPDDR e 7 ry c 5 al 8 fal lal lal 8 fal 8 Tal lal e lal Ja o o oi o Jol o Jol o o oi lu 9 dj ju s o oj e ei oj co m m Dl 2 e g al e SI lal lal lal lal lal lal lal la sl EI Ta 81 E 7 ol 8 e of e Joy joy o Oo n DQ 27 o DQ 28 lt n n CCP l
170. O OO COO OO OO OO OO OO OD OO OD OD OO OO OO 9 OO OO OO OD OO OD OD OO OC 8 OOO 0 090000000000 0 0 CO OO OO OO OO OD OOo OOOO OO OC OOO OD OD OD OD OOOO 0 OOOO oO 8 OO OO OO O00 0000 000 0 0 0 0 OOO OO OO OO 0 0 0 0 0 0 0 0 80 OOO 0 00 OOO OO OD OO 0 O00 8 OOO OOOO OOOO OOO OO oO 0 00000000000000000000 OO OO OOO OO OO OOo OO CO 8 O00 0000000000000 00 0 OO OO OO OO OO OD CO OO OO CO OO OO OO OO OO OD OD OD OO OD OO O OO DO OO OD OO OO OO OO OD CO 8 OO OO OO OD OO 00 OO OO 8 CO OD OO OO 000000 0000 0 O OQ OO OO OO OO COC OOO OO 8 QO OO OOOO OOOO OOO OO oO 8 OO OO OOOO OD OO 0000 0 0 0 0 O OO 00900 000000000 0 0 OO OO OOO OO oO OOO OO OO OOO 000 0 00 0000 OOO O 22 mm Intel Atom Processor E6xx Series Datasheet 284 Ballout and Package Information n tel Figure 13 Intel Atom Processor E6xx Series Ball Map Sheet 1 of 5 e BS 1 Nc T e meo moa mma e gt como waa mmm es M RCOMPOUT VSS momo MM M RCVENIN VSS M MA O0 N _Daro Ka El l m o o e o 2 sai La a S E a _DQ 3 LC DO N O TDO O TDI We 10 5 amp e Rod an o n O TMS TCRST B 8 8 5 o o o o o 2 2 2 9 9 l o a A o N _DOS 0 WROK al lal 8 nT o MA 7 PLL REFCLK N IGHZ B X o E D o o E A LEN gl Ol o o ol ls U m D PLL REFCLK P S
171. O PFE Phantom Functions Enable Not supported 08 Ob RO ETFE Extended Tag Field Enable Not supported Max Payload Size The root port only supports 128B payloads 07 05 000b RW MPS regardless of the programming of this field 04 Ob RO ERO Enable Relaxed Ordering Not supported 03 Ob RW URE Unsupported Request Reporting Enable When set the root port will generate errors when detecting an unsupported request Fatal Error Reporting Enable When set the root port will generate 02 Ob RW FEE errors when detecting a fatal error When cleared the root port will ignore fatal errors Non Fatal Error Reporting Enable When set the root port will 01 Ob RW NFE generate errors when detecting a non fatal error When cleared the root port will ignore non fatal errors Correctable Error Reporting Enable When set the root port will 00 Ob RW CEE generate errors when detecting a correctable error When cleared the root port will ignore correctable errors Intel Atom Processor E6xx Series Datasheet 124 PCI Express 8 2 2 5 DSTS Device Status Table 154 Offset 4Ah DSTS Device Status Size 16 bit Default 0010h Power Well Core Access Offset Start 4Ah PCI Configuration B D F 0 23 26 0 Offset End 4Bh Bit Range Default Access Acronym Description 15 06 0 RO RSVD Reserved Transactions Pending Thi
172. O RSVD Reserved 7 7 2 17 Offset 98h MD Message Data Table 119 Offset 98h MD Message Data Size 16 bit Default 0000h Power Well Core Access D F 0 3 Offset Start 98h PCI Configuration B D F 0 3 0 Offset End 99h Bit Range Default Access Acronym Description Data This 16 bit field is programmed by system software and is driven 15 00 0 RW DATA onto the lower word of data during the data phase of the MSI write transaction 7 7 2 18 Offset C4h FD Functional Disable Table 120 Offset C4h FD Functional Disable Sheet 1 of 2 Size 32 bit Default 00000000h Power Well Core Access 7 D F 0 3 Offset Start C4h PCI Configuration B D F 0 3 0 Offset End C7h Bit Range Default Access Acronym Description 31 02 0 RO RSVD Reserved MSI Disable When set the MSI capability pointer is not available the 01 Oh RW MD item which points to the MSI capability the power management capability will instead indicate that this is the last item in the list Intel Atom Processor E6xx Series Datasheet 108 Graphics Video and Display Table 120 Offset C4h FD Functional Disable Sheet 2 of 2 Size 32 bit Default 00000000h Power Well Core Access i D F 0 3 Offset Start C4h PCI Configuration B D F
173. O Registers The control for the general purpose I O signals is handled through an independent 64 byte I O space The base offset for this space is selected by the GPIO BAR register in D31 FO config space Note the Core Well GPIO registers are mapped to the GPIO pins and the resume well are mapped to the GPIOSUS n pins Table 340 GPIO I O Register Start End Name 00 03 CGEN Core Well GPIO Enable 04 07 CGIO Core Well GPIO Input Output Select 08 0B CGLV Core Well GPIO Level for Input or Output DC OF CGTPE Core Well GPIO Trigger Positive Edge Enable 10 13 CGTNE Core Well GPIO Trigger Negative Edge Enable 14 17 CGGPE Core Well GPIO GPE Enable 18 1B CGSMI Core Well GPIO SMI Enable 1C 1F CGTS Core Well GPIO Trigger Status If a bit is allocated for a GPIO that doesn t exist unless otherwise indicated the bit will always read as 0 and values written to that bit will have no effect All core well bits are reset by the standard conditions that assert RESET and all suspend well bits are reset by the standard conditions that clear internal suspend registers 11 7 1 1 Offset 00h CGEN Core Well GPIO Enable Table 341 00h CGEN Core Well GPI O Enable Size 32 bit Default 0000001Fh Power Well Core Access e EE Offset Start 00h PCI Configuration B D F 0 31 0 Offset End 03h Memory Mapped IO BAR GPIO_BAR 10 Offset Bit Range Default Access Acronym Description 31 05 0 RO RSVD Reserved Enable When set enables the pin as a G
174. OE OE HEADTYP Header Type 00h RO 10 13 LBAR Intel HD AudioP Lower Base Address Memory 00000004h RW RO 14 17 UBAR Intel HD Audio Upper Base Address Memory 00000000h RW 2C 2D SVID Subsystem Vendor Identifier 0000h RWO 2E 2F SID Subsystem Identifier 0000h RWO 34 34 CAP_PTR Capabilities Pointer 50h RO 3C 3C INTLN Interrupt Line 00h RW 3D 3D INTPN Interrupt Pin Variable RO 40 40 HDCTL Intel HD Audio Control 00h RW RO 4C 4C DCKCTL Docking Control 00h RW RO 4D 4D DCKSTS Docking Status 80h RWO RO 50 51 PM CAPID PCI Power Management Capability ID 01h RO 52 53 PM_CAP Power Management Capabilities C842h RO 54 57 PM_CTL_STS Power Management Control and Status 0000h RW RO RWC 60 61 MSI_CAPID MSI Capability 1D 0005h RO 62 63 MSI_CTL MSI Message Control 0080h RW RO 64 67 MSI_ADR MSI Message Address 0000 0000h RW RO 68 69 Mol DATA MSI Message Data 0000h RW 70 71 PCIE_CAPID PCI Express Capability Identifiers 10h RO 72 73 PCIECAP PCI Express Capabilities 0091h RO 74 77 DEVCAP Device Capabilities 0000_0000h RO 78 79 DEVC Device Control 0800h RW RO 7A 7B DEVS Device Status 0000h RO FC FF FD Function Disable 0000_0000h RW RO 100 103 VCCAP Virtual Channel Enhanced Capability Header 1301_0002h RO 104 107 PVCCAP1 Port VC Capability Register 1 0000 0001h RO 108 10B PVCCAP2 Port VC Capability Register 2 0000 0000h RO 10C 10D PVCCTL Port VC Control 0000h RO 10E 10F PVCSTS Port VC Status 0000h RO 110 113 VCOCAP VCO Resource Capability 00
175. OT gn uu 6118 26 ante 3 056 YO ven VINYS 81185 XOG Wi 931102 NOISSIN 0022 E NN av 18 wm SU3L3MITTIN NI UY SNOISNGNIO Luva30 av 18 aanois3a 03141934S S z OM Dt 2ISV8 881501 G ge 1W2S y vi ag n C O AO O C J A Sal NEE LVBLSONS 3900v4 DISVA sie 02 E N 28200 041 DR i sva se 1 ald UIS TNT Sn vo amor i ene fev Ort og DISVA 9LE OZ m KE soze sem g iix sua a A N ran so SH mn a a an a ER BR E I ji f mai sew Y t E Da Ty Psi m 18072 Y See V mg 33s mo NI e BEIER P tz M31A dOl 189138 ININOHOO Tino T XYK L0 je re sux LG DID gs MIIA WOLLOB IR Nid 3 3 3 9 9 von d T Ly i _A 0 0 0 0 0 00100000000 mt BT oun 8 ooo oo0o000400000000 o o0oO0000000 000000000 Ree 000000000 000006000 np O00 00000 0 0 00 0000 0 0 AN O0 000 000040000000 0 0 0 00000000 000000000 Xo o 0o 0 0 0 0 0 00 0 0 0 0 0 0 0 0 T oo0o000000J000000000 o O00 0000400000000700 00000000 000000000 A O OO 0 0 0 0 0 0 00 0 0 0 0 00 0 og 0 0 0 0 00 0 0 0 0 0 0 0 0000 0 O 00000000 000 0000 0 0 0 OOo0O0000000ji000000000 tt o
176. Offset 00h ID Identifiers Table 104 Offset 00h ID Identifiers Size 32 bit Default 81828086h Power Well Core Access DE 0 2 Offset Start 00h PCI Configuration B D F 0 3 0 Offset End 03h Bit Range Default Access Acronym Description Device Identification Number Identifier assigned to the processor 31 16 8182h RO DID core primary PCI device The lower 3 bits of this register are determined by a fuse 15 00 8086h RO VID Vendor Identification Number PCI standard identification for Intel 7 7 2 2 Offset 04h CMD PCI Command Table 105 Offset 04h CMD PCI Command Sheet 1 of 2 Size 16 bit Default 0000h Power Well Core Access D F 0 3 Offset Start 04h PCI Configuration B D F 0 3 0 Offset End 05h Bit Range Default Access Acronym Description 15 11 00h RSVD Reserved I nterrupt Disable This bit disables the device from asserting INTx B 10 0 RW ID When cleared enables the assertion of this device s INTx B signal When set disables the assertion of this device s INTx B signal 09 03 0 RSVD Reserved 02 0 RW BME Bus Master Enable Enables the IGD to function as a PCI compliant master Memory Space Enable When set accesses to this device s memory 01 0 RW MSE space is enabled Intel Atom Processor E6xx Series Datasheet 103 intel Graphics Video and Display T
177. Offset 50h BBAR BIOS Base Address This register is not writable when the SPI Configuration Lock Down bit in Offset 00h SPIS SPI Status register is set Table 378 50h BBAR BIOS Base Address Size 32 bit Default 00000000h Power Well Core RECESS PCI Configuration B D F 0 31 0 TM E Memory Mapped IO BAR RCBA Offset Bit Range Default Access Acronym Description 31 24 0 RV RSVD Reserved Bottom of System Flash This field determines the bottom of the System BIOS The processor will not run programmed commands nor memory reads whose address field is less than this value This field corresponds to bits 23 8 of the 3 byte address bits 7 0 are assumed to be 00h for this vector when comparing to a potential SPI address Software must always program 1 s into the upper Don t Care bits of this Tiele pasea on g flash slee Haraware does not Know the Re of the ash array and relies upon the correct programming by software The 23 08 0 RWS BSP default value of 0000h results in all cycles allowed Note The SPI Host Controller prevents any Programmed cycle using the Address Register with an address less than the value in this register Some flash devices specify that the Read ID command must have an address of 0000h or 0001h If this command must be supported with these devices it must be performed with the BBAR BIOS Base Address programmed to Oh Some of these devices have actually been observed to ignore the upper address bits of the Read ID command
178. Offset End 03h Bit Range Default Access Acronym Description Device I D This is a 16 bit value assigned to the Intel HD AudioP 15 00 811Bh RO DID controller 9 3 1 3 Offset O4h PCI CMD PCI Command Register Table 180 04h PCI CMD PCI Command Register Sheet 1 of 2 Size 16 bit Default 0000h Power Well Core Access D F 0 27 Offset Start 04h PCI Configuration B D F 0 27 0 Offset End 05h Bit Range Default Access Acronym Description 15 11 0 RO RSVD Reserved I nterrupt Disable Enables the device to assert an INTx B When set 10 0 RW ID the Intel HD Audio controller s INTx B signal will be de asserted When cleared the INTx B signal may be asserted Note that this bit does not affect the generation of MSI s 09 03 0 RO RSVD Reserved Bus Master Enable Controls standard PCI Express bus mastering capability for Memory and I O reads and writes Note that this bit also 02 0 RW BME controls MSI generation since MSI s are essentially Memory writes 0 Disable 1 Enable Memory Space Enable When set enables memory space accesses to 0 0 s the Intel HD Audio controller 5 RW ME 0 Disable 1 Enable Intel Atom Processor E6xx Series Datasheet 142 Intel High Definition Audio D27 FO n tel Table 180 04h PCICMD PCI Command Register Sheet 2 of 2 Size 16 bit Default 0000h Power Well Core Access
179. Offset Start D8h PCI Configuration B D F X 31 0 Offset End DBh Bit Range Default Access Acronym Description Write Protect When set access to BIOS is enabled for both read and 00 Ob RW WP write cycles When cleared only read cycles are permitted to BIOS When written from a 0 to a 1 and LE is also set an SMI B is generated This ensures that only SMM code can update BIOS 10 6 Root Complex Register Block Configuration 10 6 1 RCBA Root Complex Base Address Register Table 296 Offset FOh RCBA Root Complex Base Address Size 32 bit Default 00000000h Power Well Access D F X 31 Offset Start FOh PCI Configuration B D F X 31 0 Offset End F3h Bit Range Default Access Acronym Description Base Address Base Address for the root complex register block 31 14 Oh RW BA decode range This address is aligned on a 16KB boundary 13 01 Oh RO RSVD Reserved Enable 00 0 RW EN 1 Enables the range specified in BA to be claimed as the RCRB 88 Intel Atom Processor E6xx Series Datasheet 199 n tel LPC Interface D31 FO Intel Atom Processor E6xx Series Datasheet 200 ACPI Devices 11 0 11 1 11 1 1 11 1 2 11 1 3 11 1 4 Table 297 11 1 5 intel ACPI Devices 8254 Timer The 8254 contains three counters which have fixed uses All registers are in the core well and clocked by a 14 31818 MHz clock Counter 0 System Timer This counter functions as the system timer by controlli
180. P33 VCC33RTC 105 mA 1 vccp33SUS 3 3 V Supply Voltage Suspend Power supply VCCP33SUS VCCPSUS 20 mA 1 Lumm 1 05 V Supply Voltage VMM 5 mA 1 I cc DYN Core Dynamic Current in HFM 1200 mA dl cc dt Core power supply current slew rate 1 A ns I cC DYN North Cluster Logic Dynamic Current 500 mA dl cc dt Norik Cluster Logic power supply current slew 1 A ns Notes L These values are based on post silicon validated result 2 Iccmax is determined on a per interface basis and all cannot happen simultaneously Intel Atom Processor E6xx Series Datasheet 276 DC Characteristics ntel 13 3 General DC Characteristics Table 405 Operating Condition Power Supply and Reference DC Characteristics Symbol Parameter Min Typ Max Unit Notes Vcc HFM Vcc E Highest Frequency Mode AVID 1 15 V 1 2 3 Vcc LFM Vcc Lowest Frequency Mode 0 75 AVID V 1 2 3 Vcc C6 VID Vcc C6 CPU State 0 3 V 13 VCC BOOT Default VCC for initial power Vcc LFM V 1 2 3 VNN BOOT Default VNN for initial power VNN V 1 2 3 VNN VNN Supply Voltage 0 75 0 9875 V 1 2 3 Mente Wee ene 1 05 V Supply Voltage DMI Fuses y i DDR digital DPLL PCle 10 SDVO 0 9975 1 05 1 1025 V VCCD VCCD DPL VCCA PEG DPLL SDVO pads HPLL VCCQHPLL VCCFHV i pages VCCDSUS 1 05 V Core Suspend Rail 0 9975 1 05 1 1025 LVD VBG 1 25 V LVDS External Voltage Ref 1 1875 1 25 1 3125 VCCA 1 5 V Sensors C
181. PIO When cleared the pin if 04 00 1Fh RW EN muxed returns to its normal use This field has no effect on unmuxed GPI Os Bits 4 0 muxed between GPIO 4 0 Intel Atom Processor E6xx Series Datasheet 234 ACPI Devices 11 7 1 2 Offset 04h CGI O Core Well GPI O I nput Output Select Table 342 04h CGIO Core Well GPIO I nput Output Select Size 32 bit Default 0000001Fh Power Well Core Access Offset Start 04h PCI Configuration B D F 0 31 0 Offset End 07h Memory Mapped lO BAR GPIO BAR 10 Offset Bit Range Default Access Acronym Description 31 05 0 RO RSVD Reserved Input Output When set the GPIO signal if enabled is programmed 04 00 1Fh RW 10 as an input When cleared the GPIO signal is programmed as an output If the pin is muxed and not enabled writes to these bits have no effect 11 7 1 3 Offset 08h CGLVL Core Well GPI O Level for Input or Output Table 343 08h CGLVL Core Well GPIO Level for Input or Output Size 32 bit Default 00000000h Power Well Core Access DE 0 31 Offset Start 08h PCI Configuration B D F 0 31 0 Offset End OBh Memory Mapped IO BAR GPIO BAR 10 Offset Bit Range Default Access Acronym Description 31 05 0 RO RSVD Reserved Level If the GPIO is programmed to be an output GIO IO n cleared then this bit is used by software to drive a value on the pin 1 high 0 low If
182. R Offset as indicated in the following table Intel Atom Processor E6xx Series Datasheet 157 intel Intel High Definition Audio D27 FO These memory mapped registers must be accessed a byte word or Dword quantities Addresses not shown must be treated as reserved Table 225 Intel HD Audio Register Summary Sheet 1 of 3 Offset Offset Symbol Full Name Reset Value Access Start End 00 01 GCAP Global Capabilities 4401h RO 02 02 VMIN Minor Version 00h RO 03 03 VMAJ Major Version 01h RO 04 05 OUTPAY Output Payload Capability 003Ch RO 06 07 INPAY Input Payload Capability 001Dh RO 08 0B GCTL Global Control 0000h RO R W oc DC WAKEEN Wake Enable 0000h RO R W OE OE STATESTS State Change Status 0000h RO RWC 10 11 GSTS Global Status 0000h RO RWC 18 1B STRMPAY Stream Payload Capability Input and Output 0018_0030 RO 20 23 INTCTL Interrupt Control 0000_0000h RW RO 24 27 INTSTS Interrupt Status 0000_0000h RO 30 33 WALCLK Wall Clock Counter 0000_0000h RO 38 3B SSYNC Stream Synchronization 0000 0000h RW RO 40 43 CORBBASE CORB Base Address 0000 0000h RW RO 48 49 CORBWP CORB Write Pointer 0000h RW RO 4A 4B CORBRP CORB Read Pointer 0000h RW RO 4C 4C CORBCTL CORB Control 00h RW RO 4D 4D CORBSTS CORB Status 00h RW RO 4E 4E CORBSI ZE CORB Size 42h RO 50 53 RIRBBASE RIRB Base Address
183. RBSTS RIRB Status Register Table 251 5Dh RIRBSTS RIRB Status Register Size 8 bit Default 00h Power Well Core Access e cie te Offset Start 5Dh PCI Configuration B D F 0 27 0 Offset End 5Dh Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 07 03 0 RO RSVD Reserved Response Overrun Interrupt Status Hardware sets this bit to a 1 when the RIRB DMA engine is not able to write the incoming responses to memory before additional incoming responses overrun the internal FIFO 02 0 RWC RIRBOIS When the overrun occurs the hardware will drop the responses which overrun the buffer An interrupt may be generated if the Response Overrun Interrupt Control bit is set Note that this status bit is set even if an interrupt is not enabled for this event Software clears this flag by writing a 1 to this bit 01 0 RO RSVD Reserved Response Interrupt Hardware sets this bit to a 1 when an interrupt has been generated after N number of Responses are sent to the RIRB 00 0 RWC RINTFL buffer OR when an empty Response slot is encountered on all HDA SDI x inputs whichever occurs first Note that this status bit is set even if an interrupt is not enabled for this event Software clears this flag by writing a 1 to this bit 9 3 2 1 27 Offset 5Eh RIRBSIZE RIRB Size Register Table 252 5Eh RI RBSIZE RI RB Size Register Size 8 bit Default 42h Power We
184. RI RQ Stop Frame After the data frames a Stop Frame will be driven by the interrupt controller SERIRQ will be driven low for 2 or 3 LPC clocks The number of clocks is determined by the SCNT MD field in D31 FO configuration space The number of clocks determines the next mode Serial I nterrupt Mode Selection Stop Frame Width Next Mode 2 LPC clocks Quiet Mode Any SERIRQ device initiates a Start Frame 3 LPC clocks Continuous Mode Only the interrupt controller initiates a Start Frame Intel Atom Processor E6xx Series Datasheet 228 ACPI Devices 11 5 5 11 5 6 Table 333 intel There are 4 interrupts on the serial stream which are not supported by the interrupt controller These interrupts are generated internally and are not sharable with other devices within the system These interrupts are Serial I nterrupts Not Supported e IRQO Heartbeat interrupt generated off of the internal 8254 counter 0 e RQ8 RTC interrupt can only be generated internally e RQ13 This interrupt floating point error is not supported in the processor e RQ14 PATA interrupt can only be generated from the external P Device The interrupt controller will ignore the state of these interrupts in the stream Data Frame Format and Issues Table 333 shows the format of the data frames The decoded INT A D values are ANDed with the corresponding PCI Express input signals PIRQ A D This way the interrupt
185. RSVD Reserved 10 4 3 WDTBA WDT Base Address Table 292 Offset 84h WDTBA WDT Base Address Size 32 bit Default 00000000h Power Well Access DEN 31 Offset Start 84h PCI Configuration B D F X 31 0 Offset End 87h Bit Range Default Access Acronym Description 31 0 RW RW Enable When set decode of the IO range pointed to by the BA is enabled 30 16 Oh RO Reserved Always 0 15 06 Oh RW Base Address Provides the 64 bytes of I O space for WDT 05 00 Oh RO RO Reserved 10 5 FWH Configuration Registers 10 5 1 FS FWH ID Select Register This register contains the IDSEL fields the LPC Bridge uses for memory cycles going to the FWH Note The usage of FWH will not be validated or supported Table 293 Offset DOh FS FWH ID Select Sheet 1 of 2 Size 32 bit Default 00112233h Power Well Weer PCI Configuration B D F X 31 0 e E Bit Range Default Access Acronym Description F8 FF I DSEL IDSEL to use in FWH cycle for range enabled by 31 28 Oh RO 1F8 BDE EF8 The Address ranges are FFF80000h FFFFFFFFh FFB80000h FFBFFFFFh and 000E0000h OOOFFFFFh Intel Atom Processor E6xx Series Datasheet 196 LPC Interface D31 FO Table 293 Offset DOh FS FWH ID Select Sheet 2 of 2 Size 32 bit Default 00112233h Power Well Access TUM Offset
186. Reserved RI RB Write Pointer Indicates the last valid RIRB entry written by the DMA controller Software reads this field to determine how many 07 00 0 RO RIRBWP responses it can read from the RIRB The value read indicates the RIRB Write Pointer offset in 2 Dword RIRB entry units since each RIRB entry is 2 Dwords long Supports up to 256 RIRB entries 256 x 8B 2KB This field may be read while the DMA engine is running Intel Atom Processor E6xx Series Datasheet 170 Intel High Definition Audio D27 FO 9 3 2 1 24 Offset 5Ah RINTCNT Response Interrupt Count Register Table 249 5Ah RINTCNT Response Interrupt Count Register Size 16 bit Default 0000h Power Well Core Access D F 0 27 Offset Start 5Ah PCI Configuration B D F 0 27 0 Offset End 5Bh Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 15 08 0 RO RSVD Reserved N Response Interrupt Count 0000 0001b 1 Response sent to RIRB 1111 1111b 255 Responses sent to RIRB 0000 0000b 256 Responses sent to RIRB 07 00 00h RW RINTCNT The DMA engine should be stopped when changing this field or else an interrupt may be lost Note that each Response occupies 2 Dwords in the RIRB This is compared to the total number of responses that have been returned as opposed to the number of frames in which there were responses If more than one codec responds in one frame then
187. S AH19 VSS AR36 NC AF37 VSS AH23 VSS AT3 NC AG30 VSS AH25 VSS AT35 NC AG34 VSS AH27 VSS AUA NC AH31 VSS AH29 VSS AU34 NC AH33 VSS AH35 VCCD VSSSENSE M19 NC AJ34 VSS AJ6 VCC VSSSENSE AH21 NC AJ36 VSS AJ24 WAKE B H11 NC AK17 VSS AJ28 NC A8 NC AK19 VSS AJ32 NC A22 NC AK21 VSS AK3 NC A28 NC AK31 VSS AK9 NC B9 NC AK33 VSS AK29 NC B29 NC AK35 VSS AL6 NC D15 NC AK37 VSS AL12 NC D21 NC AL8 VSS AL32 NC D23 NC AL18 VSS AM3 NC E16 NC AL20 VSS AM9 NC E24 NC AL36 VSS AM11 NC AN24 VSS AM13 NC AN30 VSS AM15 NC AP31 88 Intel Atom Processor E6xx Series Datasheet 294
188. S NEE SAS EE RER 114 PSTS Primary Status ceni eee e ete ku sie to Redi a 115 RID Revision Identification cece eee mmm 115 CC Class Codi ins ri ARA ES 115 CES Cache Line Size eic ege SE EEN EE dE EAR EE ea 116 HTYPE Header KEE 116 PBN Primary Bus Number 116 SCBN Secondary Bus Number 117 SBBN Subordinate Bus Number 117 IOBASE I O Base Address 117 LOLI MIT 1 OsLimit Address coiere eret SERA EEN KEEN eds 118 SSTS Secondary EC e TEE 118 MB Memory Base Address 119 ML Memory Limit Address 119 PMB Prefetchable Memory Base Address 120 PML Prefetchable Memory Limit Address 120 CAPP Capabilities Pointer cc cceece cece inini renee reese e iai ENa ns 120 LINE Interrupt Line ierit ege AER EE SEA E 121 PUN Interrupt Picazo oro io er ene E a TER SEE Y RENE FERRE REGAT ota paar 121 BCTRI Bridge Control ce ter eR RR AR ERRAT A E ENEE ENN 121 149 Root Port Capability Structure mmm ee memes nne nnn 122 CEIST Capabllities List ee dad reda ed e i deed 123 XCAP PCI Express Capabilities cece eee e eee eee teeta anaes 123 DCAP Device Capabilities cece eee ee eee eee rete eee e eens eee nanan 123 DCTL Device Control eise cd 124 DSTS Device EE 125 LCAP Link Capabilities cece cece e eee eee memes 125 Je RL ee Lei EE 126 LSTS Pink Status ues rop vx RR NN EM ERU PF end FII E UM 1
189. Software Scratch Read Write Table 114 Offset 58h SSRW Software Scratch Read Write Size 32 bit Default 00000000h Power Well Core Access D F 0 3 Offset Start 58h PCI Configuration B D F 0 3 0 Offset End 5Bh Bit Range Default Access Acronym Description 31 00 00h RO S Scratch Scratchpad bits 7 7 2 13 Offset 60h HSRW Hardware Scratch Read Write Table 115 Offset 60h HSRW Hardware Scratch Read Write Size 16 bit Default 0000h Power Well Core Aene PCI Configuration B D F 0 3 0 pou rs eoh Bit Range Default Access Acronym Description 15 00 00h RW RSVD Reserved 7 7 2 14 Offset 90h MID Message Signaled Interrupts Capability Table 116 Offset 90h MID Message Signaled Interrupts Capability Size 16 bit Default 0005h Power Well Core oes PCI Configuration B D F 0 3 0 piis on Bit Range Default Access Acronym Description 15 08 00 RO NEXT Pointer to Next Capability Indicates this is the last item in the list 07 00 05h RO ID Capability I D Indicates an MSI capability 7 7 2 15 Offset 92h MC Message Control Table 117 Offset 92h MC Message Control Sheet 1 of 2 Size 16 bit Default 0000h Power Well Core PUES PCI Configuration B D F 0 3 0 UE i Bit Range Default Access Acronym Description 15 08 00h RO Reserved 07 000h RO C64 64 bit Address Capable 32 bit capable only Multiple Message Enable This field is RW for software compatibility 06 04 9006 RW MME but only a single message is ever generated 03 01 000 RO
190. Start DOh PCI Configuration B D F X 31 0 Offset End D3h Bit Range Default Access Acronym Description FO F7 IDSEL IDSEL to use in FWH cycle for range enabled by 27 24 Oh RW IFO BDE EFO The Address ranges are FFF00000h FFF7FFFFh FFBOOOOOh FFB7FFFFh E8 EF I DSEL IDSEL to use in FWH cycle for range enabled by 23 20 1h RW 1E8 BDE EE8 The Address ranges are FFE80000h FFEFFFFFh FFA80000h FFAFFFFFh EO E7 IDSEL IDSEL to use in FWH cycle for range enabled by 19 16 1h RW EO BDE EEO The Address ranges are FFE00000h FFE7FFFFh FFA00000h FFA7FFFFh D8 DF I DSEL IDSEL to use in FWH cycle for range enabled by 15 12 2h RW 1D8 BDE ED8 The Address ranges are FFD80000h FFDFFFFFh FF980000h FF9FFFFFh DO D7 IDSEL IDSEL to use in FWH cycle for range enabled by 11 08 2h RW IDO BDE EDO The Address ranges are FFD00000h FFD7FFFFh FF900000h FF97FFFFh C8 CF I DSEL IDSEL to use in FWH cycle for range enabled by 07 04 3h RW ICH BDE EC8 The Address ranges are FFC80000h FFCFFFFFh FF880000h FF8FFFFFh CO C7 I DSEL IDSEL to use in FWH cycle for range enabled by 03 00 3h RW ICO BDE ECO The Address ranges are FFC00000h FFC7FFFFh FF800000h FF87FFFFh 10 5 2 BDE BI OS Decode Enable Table 294 Offset D4h BDE BIOS Decode Enable Sheet 1 of 2 Size 32 bit Default FF000000h Power Well Access RR dU AA Offset Start D4h PCI Configuration B D F X 31 0 Offset End D7h Bit Range Default Access Acronym Description F8 F
191. U issues an EOI command immediately before returning from the service routine or if in AEOI mode on the trailing edge of the second INTA While the ISR bit is set all further interrupts of the same or lower priority are inhibited while higher levels will generate another interrupt Intel Atom Processor E6xx Series Datasheet 220 ACPI Devices 11 3 6 2 11 3 6 3 11 3 6 4 11 3 6 5 intel Interrupt priorities can be changed in the rotating priority mode Special Fully Nested Mode This mode will be used in the case of a system where cascading is used and the priority has to be conserved within each slave In this case the special fully nested mode will be programmed to the master controller This mode is similar to the fully nested mode with the following exceptions When an interrupt request from a certain slave is in service this slave is not locked out from the master s priority logic and further interrupt requests from higher priority interrupts within the slave will be recognized by the master and will initiate interrupts to the processor In the normal nested mode a slave is masked out when its request is in service When exiting the Interrupt Service routine software has to check whether the interrupt serviced was the only one from that slave This is done by sending a Non Specific EOI command to the slave and then reading its ISR If it is O a non specific EOI can also be sent to the master Automat
192. VSS L30 VSS U8 VSS AB21 VSS L32 VSS U10 VSS AB23 VSS M9 VSS U12 VSS AB27 VSS M11 VSS U28 VSS AB29 VSS M17 VSS U32 VSS AC6 VSS M21 VSS V3 VSS AC10 VSS M23 VSS V7 VSS AC16 VSS M27 VSS V9 VSS AC28 VSS M29 VSS V11 VSS AC32 VSS M31 VSS V15 vss AD3 vss M33 vss V17 VSS AD9 VSS M35 VSS V19 VSS AD11 VSS N6 VSS v21 vss AD13 vss N8 VSS V23 VSS AD17 VSS N10 VSS V25 VSS AD19 VSS N14 VSS V27 VSS AD21 VSS N16 VSS V29 VSS AD23 VSS N28 VSS W vss AD25 VSS W14 VSS AD27 Intel Atom Processor E6xx Series Datasheet 293 m e n tel Ballout and Package Information Table 407 Pin List Table 407 Pin List Table 407 Pin List Pin Name Ball Pin Name Ball Pin Name Ball VSS AD29 VSS AM17 NC E34 VSS AD35 VSS AM19 NC G4 VSS AE2 VSS AM21 NC K37 VSS AE6 vss AM23 NC L36 vss AE10 VSS AM27 NC R4 VSS AE14 VSS AM29 NC V35 VSS AE16 VSS AM35 NC V37 vss AE26 vss AN6 NC w30 VSS AE28 VSS AN20 NC W34 VSS AE32 VSS AN32 NC W36 VSS AF3 VSS AP1 NC Y31 vss AF9 vss AP3 NC Y33 VSS AF11 VSS AP37 NC Y37 VSS AF15 VSS AR2 NC AA30 VSS AF17 VSS AR6 NC AA34 VSS AF19 VSS AR8 NC AA36 VSS AF21 VSS AR10 NC AB31 VSS AF23 VSS AR12 NC AC30 VSS AF25 VSS AR14 NC AC36 VSS AF29 VSS AR16 NC AD31 VSS AG6 VSS AR18 NC AD33 VSS AG10 VSS AR20 NC AD37 VSS AG14 VSS AR22 NC AE30 VSS AG16 VSS AR24 NC AE34 VSS AG28 VSS AR26 NC AE36 VSS AG32 VSS AR28 NC AF31 VSS AH3 VSS AR30 NC AF33 VSS AH17 VSS AR32 NC AF35 VS
193. WDTBA WDT Base Address cece tented 196 10 5 FWH Configuration Register 196 10 5 1 FS FWH ID Select Register 196 10 5 2 BDE BIOS Decode Enables sss ennemi 197 10 5 3 BC BIOS Control Register 198 10 6 Root Complex Register Block Configuration esssssssesen He 199 10 6 1 RCBA Root Complex Base Address Register 199 Intel Atom Processor E6xx Series Datasheet Contents i n tel I1 0 ACPI Devices ooo OR REVO E ARR ERR ead UI RAP GR UU E edie dads 201 LLL 8254 TIME EE 201 11 1 1 Counter 0 System Timer iio ieee daa tede vena an et A ds 201 11 1 2 Counter 1 Refresh Request SGional Hs 201 11 1 3 Counter 2 Speaker Tone emen nememese nemen ens 201 11 1 4 Timer I O Registers niinen edaran I ena EEE EEn nns 201 11 1 5 Offset 43h TCW Timer Control Word Register 201 11 1 5 1 Read Back Commande 202 11 1 5 2 Counter Latch Commande 203 11 1 5 3 Offset 40h 41h 42h Interval Timer Status Byte Format Register 203 11 1 5 4 Offset 40h 41h 42h Counter Access Ports Register 204 11 1 6 Timer Progratmming oria Leere orca Pract EE tbv AEE Rea De EDEA 204 11 1 7 Reading from the Interval Timer cece eee eee mns 205 LEET Simple Read eire naan E REA A EE 205 11 1 7 2 Counter Latch Commande 205 11 1 7 3 Read Back Commande 206 11 2 High Precision Event Timer cece mI HesmHmememe sese emen nn 206 11 2 1 Reglstets eee eee erre eet re hed a edad e coste piv a Rb EE s 206 1
194. XXXXh Power Well Core Access PCI Configuration B D F 0 31 0 Offset Start 3024h Offset End 3027h Memory Mapped IO BAR RCBA Offset Bit Range Default Access Acronym Description 31 24 0 RV RSVD Reserved 23 00 0 RW SCA SPI Cycle Address This field is shifted out as the SPI Address MSB first 11 9 5 5 Offset 08h SPI DO SPI Data O Table 376 08h SPI DO SPI Data O Size 64 bit Default XXXXXXXXh Power Well Core Access PCI Configuration B D F 0 31 0 Offset Start 3028h Offset End 302Bh Memory Mapped IO BAR RCBA Offset Bit Range Default Access Acronym Description 63 00 0 RWO SCD SPI Cycle Data 0 SCDO This field is shifted out as the SPI Data on the Master Out Slave In Data pin SPI MOSI during the data portion of the SPI cycle This register also shifts in the data from the Master In Slave Out pin SPI MISO into this register during the data portion of the SPI cycle The data is always shifted starting with the least significant byte MSB to LSB followed by the next least significant byte MSB to LSB etc Specifically the shift order on SPI in terms of bits within this register is 7 6 5 4 3 2 1 0 15 14 13 8 23 22 16 31 24 39 32 etc Bit 56 is the last bit shifted out in There are no alignment assumptions byte 0 always represents the value specified by the cycle address Not
195. _PETn 3 0 PCle Ports 3 0 transmit pair P and N signals PCIE_PERp 3 0 l Core PCI Express Receive PCIE_PER 3 0 PCI Express Ports PCIE PERn 3 0 PCle 3 0receive pair P and N signals PCIE CLKINP I Core PCI Express Input Clock 100 MHz differential clock PCIE CLKINN PCle signals 1 0 PCI Express Compensation Pin Output compensation PCIE_ICOMPO A Core for both current and resistance PCIE ICOMPI 1 0 Core PCI Express Compensation Pin Input compensation for A current PCIE RCOMPO 1 0 Core PCI Express Compensation Pin PCI Express Resistance A Compensation 1 0 PCI Express Compensation Pin PCI Express Bias PCIE_RBIAS A Core control 2 4 Intel High Definition Audio Interface Signals Table 8 Intel High Definition Audio Interface Signals Direction Power m Signal Name Type Well Description O Intel HD Audio Reset This signal is the reset to external HDA RST B CMOS_HDA Core codecs o Intel HD Audio Sync This signal is an 48 kHz fixed rate HDA_SYNC Core sample sync to the codec s It is also used to encode the CMOS_HDA stream number Intel HD Audio Clock Output This signal is a 24 000 MHz serial data clock generated by the Intel HD Core Audio controller This signal contains an integrated pull down resistor so that it does not float when an Intel HD AudioP codec or no codec is connected 0 HDA CEK CMOS HDA o Intel HD Audio Serial Data Out This signal
196. a programmed read or Direct Memory Read is initiated at the top of flash such that the length exceeds the top of flash memory the read burst may wrap around to location 0 Decoding Memory Range for SPI The Boot BIOS Destination straps are sampled on the rising edge of PWROK The Feature space ranges are unique to the FWH flash However the feature space can be treated just like standard memory from an SPI perspective and therefore allow up to 16 MB of contiguous memory decode The processor forwards both data and feature space ranges to the SPI interface although the BIOS BAR may block the feature space accesses in situations where the flash size is less than 4 MB Of course in order to utilize 16 MB the single flash device would need to support 128 Mbits of data The Top Swap mechanism works in the same way that it does on LPC Address bit 16 is inverted when Top Swap is enabled for any accesses to the upper two 64 kB blocks Also like LPC the Top Swap functionality does not apply to accesses generated to the holes below 1 MB The SPI interface performs the address bit inversion on only the Direct Memory Read access method software can control the address directly with the programmed command access method The prefetching and caching logic consistently comprehends the address inversion to avoid delivering bad data Also the protection mechanisms described above observe the address after the inversion logic Memory writes to the BIOS memo
197. able 105 Offset 04h CMD PCI Command Sheet 2 of 2 Size 16 bit Default 0000h Power Well Core Access D F 0 3 Offset Start 04h PCI Configuration B D F 0 3 0 Offset End 05h Bit Range Default Access Acronym Description 00 0 RW IOSE 1 O Space Enable When set accesses to this device s UO space is enabled 7 7 2 3 Offset 06h STS PCI Status Table 106 Offset 06h STS PCI Status Size 16 bit Default 0010h Power Well Core Access D F 0 3 Offset Start 06h PCI Configuration B D F 0 3 0 Offset End 07h Bit Range Default Access Acronym Description 15 05 0 RO RSVD Reserved Capability List ndicates that the register at 34h provides an offset into 04 1 RO CAP PCI Configuration Space containing a pointer to the location of the first item in the list 03 0 RO IS Interrupt Status Reflects the state of the interrupt in the device in the graphics device 02 00 000b RO RSVD Reserved 7 7 2 4 Offset 08h RID Revision Identification This value matches the revision ID register of the LPC bridge Table 107 Offset O8h RID Revision Identification Size 8 bit Default Refer to bit description Power Well Core Access D F 0 3 Offset Start 08h PCI Configuration B D F 0 3 0 Offset End 08h Bit Range Default Access Acronym Description Ge to Revision D Refer to the Intel Atom Processor E6x5C Series 7 0 descript RO RID Specification Update for the value of the Revision ID Register For the B 0 jon p Stepping this value is 01h
198. ad Only In some cases if a register is read only writes to this register location have no effect However in other cases two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register See the I O and memory map tables for details WO Write Only In some cases if a register is write only reads to this register location have no effect However in other cases two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register See the I O and memory map tables for details R W Read Write A register with this attribute can be read and written R WC Read Write Clear A register bit with this attribute can be read and written However a write of 1 clears sets to 0 the corresponding bit and a write of 0 has no effect R WO Read Write Once A register bit with this attribute can be written only once after power up After the first write the bit becomes read only R WLO Read Write Lock Once A register bit with this attribute can be written to the non locked value multiple times but to the locked value only once After the locked value has been written the bit becomes read only Default Default When the processor is reset it sets its registers to predetermined default states The default state represents the minimum func
199. ad Pointer Register Sheet 2 of 2 Size 16 bit Default 0000h Power Well Core Access D F 0 27 Offset Start 4Ah PCI Configuration B D F 0 27 0 Offset End 4Bh Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description CORB Read Pointer Software reads this field to determine how many commands it can write to the CORB without over running The value read indicates the CORB Read Pointer offset in Dword granularity The offset 07 00 0 RO entry read from this field has been successfully fetched by the DMA controller and may be over written by software Supports 256 CORB entries 256 x 4B 1KB This field may be read while the DMA engine is running 9 3 2 1 19 Offset 4Ch CORBCTL CORB Control Register Table 244 4Ch CORBCTL CORB Control Register Size 8 bit Default 0000h Power Well Core Access y D F 0 27 Offset Start 4Ch PCI Configuration B D F 0 27 0 Offset End 4Ch Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 07 02 0 RO RSVD Reserved Enable CORB DMA Engine 0 DMA Stop 1 DMA Run 01 0 RW CORBRUN after software writes a 0 to this bit the hardware may not stop immediately The hardware will physically update the bit to a O when the DMA engine is truly stopped Software must read a 0 from this bit to verify that the DMA is truly stopped 00 0 RW CMEIE CORB Memory Error Interru
200. ad targeting the SPI flash is received while the host interface is already busy with either another Direct Memory Read or a Programmed Access then the SPI Host hardware will hold the new Direct Memory Read and the host processor pending until the preceding SPI access completes Note that it is possible for a second Direct Memory Read to be received while the prefetching continues for a first Direct Memory Read The SPI interface provides empty flash detection equivalent to FWH i e 1 s on the initial boot access It is possible that a Direct Memory Read targeting the SPI flash can be issued with noncontiguous byte enables While the CPU cannot create these cycles peer agents can The SPI interface handles these Direct Memory Read transactions in the following fashion Note that the byte enables in the table are active high and BE 3 is the most significant byte enable of the DWord Table 383 Byte Enable Handling on Direct Memory Reads DWords First DWord BE 3 0 Last DWord Action Taken Requested BE 3 0 1 0000 Don t Care Zero bytes read from SPI no SPI transaction started Bytes read from SPI bytes Don t Care requested starting from lowest requested byte 0001 0010 0100 1000 0011 0110 1100 0111 1110 1111 Full DW 4 bytes requested from 1 0101 1001 1010 1011 1101 Don t Care SPI gt 1 0000 Don t Care Undefined behavior Illegal protocol Bytes read from SPI 4 num DW 1 b
201. ample Chip Erase and Auto Address Increment Byte Program Table 380 56h OPTYPE Opcode Type Size 16 bit Default 0000h Power Well Core Access D F 0 31 Offset Start 3076h PCI Configuration B D F 0 31 0 Offset End 3077h Memory Mapped IO BAR RCBA Offset Bit Range Default Access Acronym Description 15 14 0 RWS OT7 Opcode Type 7 See the description for bits 1 0 13 12 0 RWS OT6 Opcode Type 6 See the description for bits 1 0 11 10 0 RWS OTS Opcode Type 5 See the description for bits 1 0 9 08 0 RWS OT4 Opcode Type 4 See the description for bits 1 0 7 06 0 RWS OT3 Opcode Type 3 See the description for bits 1 0 5 04 0 RWS OT2 Opcode Type 2 See the description for bits 1 0 3 02 0 RWS OT1 Opcode Type 1 See the description for bits 1 0 Opcode Type 0 This field specifies information about the corresponding Opcode 0 This information allows the hardware to 1 know whether to use the address field and 2 provide BIOS protection capabilities The hardware implementation also uses the read vs write information for modifying the behavior of the SPI interface logic The encoding of the two 1 00 0 RWS OTO bits is 00 No Address associated with this Opcode and Read Cycle type 01 No Address associated with this Opcode and Write Cycle type 10 Address required Read cycle type 11 Address required Write cycle type 11 9 5 10 Offset 58h OPMENU Opcode Menu Configuration This register is not writable when the SPI Configuration Lo
202. ange GVD will assert a hit on the SCL bus 19 1 0000h RO RESERVED Reserved 0 Ob RO RESOURCE TYPE RTE Indicates a request for memory space Table 82 14h GVD GFX IOBAR I O Base Address Size 32 bit Default 00000001h Power Well Core Access D F 0 2 Offset Start 14h PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 05h Bit Range Default Access Acronym Description 31 16 0000h RO RESERVED Reserved BA Set by the OS these bits correspond to address signals 15 3 The GVD will compare the SCL address scldown3 address 15 3 with GFX IOBAR 15 3 If there is a match and PCICMDSTS 0 IOSE 1 and the SCL command is either an IORD or IOWR the GVD will select the command i e issue a scldown3 hit The GFX IOBAR is to be used for 15 3 0000h RW BASE_ADDRESS register programming the GVD memory interface registers the display controller registers the graphics cluster GFX registers the video decode VED registers the video encode VEC registers and the video processing block VPB registers using the indirect register access method The GFX IOBAR is to be used for GTT write on SCL using the indirect access method 2 1 Oh RO RESERVED Reserved 0 1h RO RPE RTE Indicates a request for I O space Intel Atom Processor E6xx Series Datasheet 93 intel Graphics Video and Display Ta
203. antity of luma samples half as many vertically half as many horizontally See Table 74 and Table 75 for pixel formats Table 74 Pixel Format for the Luma Y Plane Bit Symbol Description 63 56 Y7 7 0 8 bit Y luma component 55 48 Y6 7 0 8 bit Y luma component 47 40 Y5 7 0 8 bit Y luma component 39 32 Y4 7 0 8 bit Y luma component 31 24 Y3 7 0 8 bit Y luma component 23 16 Y2 7 0 8 bit Y luma component 15 8 Y1 7 0 8 bit Y luma component Table 75 Pixel Formats for the Cr Cb V U Plane Bit Symbol Description Format 1 7 0 YO 7 0 8 bit Y luma component 63 56 U3 7 0 8 bit U Cb chroma component 55 48 V3 7 0 8 bit V Cr chroma component 47 40 U2 7 0 8 bit U Cb chroma component 39 32 V2 7 0 8 bit V Cr chroma component 31 24 U1 7 0 8 bit U Cb chroma component 23 16 V1 7 0 8 bit V Cr chroma component 15 8 UO 7 0 8 bit U Cb chroma component 7 0 V0 7 0 8 bit V Cr chroma component Format 2 Cr and Cb are reversed relative to Format 1 63 56 V3 7 0 8 bit U Cr chroma component 55 48 U3 7 0 8 bit V Cb chroma component 47 40 V2 7 0 8 bit U Cr chroma component 39 32 U2 7 0 8 bit V Cb chroma component 31 24 V1 7 0 8 bit U Cr chroma component 23 16 U1 7 0 8 bit V Cb chroma component 15 8 V0 7 0 8 bit U Cr chroma component 7 0 UO 7 0 8 bit V Cb chroma component 7 5 Display The Display
204. are SMI or SCI Sheet 2 of 2 Size 32 bit Default 00000000h Power Well Core Access D F 0 2 Offset Start EOh PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 38h Bit Range Default Access Acronym Description MCE If MCS 1 setting this bit causes an SCI If MCS 0 setting this bit 0 Ob RW SMI_OR_SCI_E causes an SMI A 1 to 0 0 to 0 or 1 to 1 transition of this bit does not VENT trigger any events The graphics driver writes to this register as a means to interrupt the SBIOS Table 100 E4h GVD ASLE System Display Event Register Size 32 bit Default 00000000h Power Well Core Access D F 0 2 Offset Start E4h PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 39h Bit Range Default Access Acronym Description AST3 The writing of this by field byte even if just writing back the ASLE SCRATCH original contents will trigger a display controller interrupt when the 31 24 00h RW TRIGGER 3 emory interface register bits IER O 1 and IMR O0 0 If written as part of a 16 bit or 32 bit write only one interrupt is generated in common AST2 The writing of this by field byte even if just writing back the ASLE SCRATCH original contents will trigger a display controller interrupt when the 23 16 00h RW TRIGGER 2 Memory interface register bits IER O 1 and IMR O0 0 If written as part of a 16 bit or 32 bit write only one interrupt is generated in
205. are within the ranges specified in this register and the ML register will be sent to the attached device if the Memory Space Enable bit of PCI CMD is set Accesses from the attached device that are outside the ranges specified will be forwarded to the internal processor if the Bus Master Enable bit of PCICMD is set Table 141 Offset 20h MB Memory Base Address Size 16 bit Default 0000h Power Well Core Access D F 0 Offset Start 20h PCI Configuration B D F 0 23 26 0 Offset End 21h Bit Range Default Access Acronym Description e Memory Base These bits are compared with bits 31 20 of the incoming 15 04 000h RW MB address to determine the lower 1 MB aligned value of the range 03 00 Oh RO RSVD Reserved 8 2 1 16 ML Memory Limit Address Table 142 Offset 22h ML Memory Limit Address Size 16 bit Default 0000h Power Well Core Access A REA Offset Start 22h PCI Configuration B D F 0 23 26 0 Offset End 23h Bit Range Default Access Acronym Description Memory Limit These bits are compared with bits 31 20 of the incoming 15 04 000h Bul ML address to determine the upper 1 MB aligned value of the range 03 00 Oh RO RSVD Reserved 8 2 1 17 PMB Prefetchable Memory Base Address This register controls the CPU to PCI Express prefetchable memory access routing based on the following formula PREFETCHABLE MEMORY BASE lt address lt PREFETCHABLE MEMORY LIMIT The upper 12 bits of this register are read write and correspon
206. at have been received off the link This register will count from 0 to the value in the Cyclic Buffer Length register and then wraps 88 Intel Atom Processor E6xx Series Datasheet 186 LPC Interface D31 FO i n tel 10 0 10 1 10 1 1 10 1 2 10 1 3 10 1 4 LPC Interface D31 FO Functional Overview The LPC controller implements a low pin count interface that supports the LPC 1 1 specification LSMI_B can be connected to any of the SMI capable GPIO signals The EC s PME B should connect it to GPE B e The LPC controller s SUS STAT B signal is connected directly to the LPCPD B signal The LPC controller does not implement DMA or bus mastering cycles The LPC bridge function resides in PCI Device 31 Function O This function contains many other functional units such as DMA and Interrupt controllers Timers Power Management System Management GPIO RTC and LPC Configuration Registers This section contains the PCI configuration registers for the primary LPC interface Power Management details are found in a separate chapter and other ACPI functions RTC SMBus GPIO Interrupt controllers Timers etc can be found in the ACPI chapter Memory Cycle Notes For cycles below 16M the LPC Controller will perform standard LPC memory cycles For cycles targeting firmware firmware memory cycles are used Only 8 bit transfers are performed If a larger transfer appears the LPC contr
207. ation B D F 0 23 26 0 Offset End 5Bh Bit Range Default Access Acronym Description 15 04 0 RO RSVD Reserved PME Interrupt Enable When set this enables interrupt generation 03 0 RW PIE when RSTS PS is in a set state either due to a 0 to 1 transition or due to this bit being set with RSTS PS already set SERR B on FE Enable When set SERR B is generated if a fatal error is 02 0 RW SFE reported on this port including fatal errors in this port This bit is not dependant on CMD SEE being set SERR B on NFE Enable When set SERR B is generated if a non fatal 01 0 RW SNE error iS reported on the port including non fatal errors in the port This bit is not dependant on CMD SEE being set SERR B on CE Enable When set SERR B is generated if a correctable 00 0 RW SCE error is reported on this port including correctable errors in this port This bit is not dependant on CMD SEE being set 8 2 2 13 RCAP Root Capabilities Table 162 Offset 5Eh RCAP Root Capabilities Size 16 bit Default 0000h Power Well Core Access gt ni 0 92 9R Offset Start 5Eh PCI Configuration B D F 0 23 26 0 Offset End 5Fh Bit Range Default Access Acronym Description 15 01 0 RO RSVD Reserved CRS Software Visibility This bit is not supported by the processor This 00 0 RO CSV bit when set indicates that the Root Port is capable of returning Configuration Request Retry Status CRS Completion Status to software 8 2 2 14 RSTS Root Status Tab
208. bit must be programmed to a 1 to 00 Undef WO IC indicate that ICW4 needs to be programmed 11 3 2 2 Offset 21h Alh ICW2 Initialization Command Word 2 ICW2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address The value programmed for bits 7 3 is used by the CPU to define the base address in the interrupt vector table for the interrupt routines associated with each IRQ on the controller Typical ISA ICW2 values are 08h for the master controller and 70h for the slave controller Table 315 21h A1lh ICW2 Initialization Command Word 2 Size 8 bit Default Power Well Core Access e Nm Offset Start 21h Alh PCI Configuration B D F Offset End Bit Range Default Access Acronym Description I nterrupt Vector Base Address Bits 7 3 define the base address in 07 03 Undef WO the interrupt vector table for the interrupt routines associated with each interrupt request level input Interrupt Request Level When writing I CW2 these bits should all be 0 During an interrupt acknowledge cycle these bits are programmed by the interrupt controller with the interrupt to be serviced This is combined with bits 7 3 to form the interrupt vector driven onto the data bus during the second I NTA cycle The code is a three bit binary code Code Master Interrupt Slave Interrupt 000 IRQO IRQ8 001 IRQ1 IRQ9 02 00 Undef WO 010 IRQ2 IRQ10 011 IRQ3 IRQ11 100 IRQ4 IRQ12 101 IRQ5 IRQ13 110 IRQ6
209. ble 83 18h GVD GMADR Graphics Memory Address Range Size 32 bit Default 00000000h Power Well Core Access RUE m ey Offset Start 18h PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 06h Bit Range Default Access Acronym Description BA Set by the OS these bits correspond to address signals 31 28 The GVD will compare the SCL address scldown3 address 31 29 28 or 27 with GMADR 31 29 28 or 27 respectively Whether the comparison is 31 29 31 28 or 31 27 depends on the value of MSAC 17 16 If there is 31 29 Oh BASE ADDRESS a match and MSE 1 and the SCL command is either a MEMRD or MEMWR the GVD will select the command i e issue a scldown3 hit The GMADR is to be used for the graphics cluster GFX tiled memory space M512M This bit is either part of the Memory Base Address RW or part 28 Ob RWL 512 MB ADDR of the Address Mask RO depending on the value of MSAC UAS If this ESS MASK bitis used in the address comparison the address space is limited to 256 MB M256M This bit is either part of the Memory Base Address RW or part 27 Ob RWL 256 MB ADDR of the Address Mask RO depending on the value of MSAC UAS If this ESS MASK bitis used in the address comparison the address space is limited to 128 MB 26 1 Oh RO RESERVED Reserved 0 Ob RO RYDE RTE Indicates a request for memory space Table 84 1Ch GVD GTTADR Graphics Translation Table Address Range Size 32 bit Default 00000000h P
210. ble bit and clearing the Prefetch Enable in Offset D8h BC BIOS Control Register This can serve as a way to flush the cache in software Even when prefetching is disabled the read buffer can act as a cache for Direct Memory Read Data This is a potentially valuable boot time optimization that leverages the basic caching mechanism that is needed for prefetching anyway The cache is loaded with the data received on every Direct Memory Read that runs on the SPI pins That data remains valid within the cache until any one of the conditions listed above occurs For the cache to work properly the Direct Memory Read must be fully contained within a 64 byte aligned range The following events result in a valid read buffer cache when the caching is enabled 1 A host read to the SPI BIOS with a length of 64 Bytes This cycle must be aligned to a 64B boundary 2 A host read to the SPI BIOS of any length with a 64B aligned address and prefetching is enabled Intel Atom Processor E6xx Series Datasheet 256 ACPI Devices intel Note that although the SPI interface may burst ahead for up to 64 bytes the Host Interface may still have to wait for prefetched data to arrive from the flash before generating the completion back to the processor The round trip delay for the platform to complete one DWord and run the host read for the next sequential DWord can be shorter than the SPI time to receive another 32 bits If a Direct Memory Re
211. bled by loading the Mask Register with the appropriate pattern The special Mask Mode is set by OCW3 SSMM and OCW3 SMM set and cleared when OCW3 SSMM and OCW3 SMM are cleared Steering of PCI Interrupts The processor can be programmed to allow PIRQ A H to be internally routed to interrupts 3 7 9 12 14 or 15 through the PARC PBRC PCRC PDRC PERC PFRC PGRC and PHRC registers in the chipset configuration section One or more PIRQx lines can be routed to the same IRQx input The PIRQx lines are defined as active low level sensitive When PIRQx is routed to specified IRQ line software must change the corresponding ELCR1 or ELCR2 register to level sensitive mode The processor will internally invert the PIRQx line to send an active high level to the 8259 When a PCI interrupt is routed onto the 8259 the selected IRQ can no longer be used by an ISA device Advanced Peripheral I nterrupt Controller API C Memory Registers The APIC is accessed via an indirect addressing scheme These registers are mapped into memory space The registers are shown below API C Registers Address Symbol Register FECO0000h IDX Index Register FECO0010h WDW Window Register FECO0040h EOI EOI Register Address FECOOOOOh I DX Index Register This 8 bit register selects which indirect register appears in the window register to be manipulated by software Software will program this register to select the desired APIC
212. can be shared The other interrupts decoded via SERIRQ are also ANDed with the corresponding internal interrupts For example if IRQ10 is set to be used as the SCI then it is ANDed with the decoded value for IRQ10 from the SERIRQ stream Data Frame Format Data Interrupt Clocks Past Comment Frame Start Frame 1 IRQO 2 Ignored Can only be generated via the internal 8254 2 IRQ1 5 Before port 60h latch 3 SMI 8 Causes SMI if low Sets bit 15 in the SMI_STS register 4 IRQ3 11 5 IRQ4 14 6 IRQ5 17 7 IRQ6 20 8 IRQ7 23 9 IRQ8 26 Ignored IRQ8 can only be generated internally 10 IRQ9 29 11 IRQ10 32 12 IRQ11 35 13 IRQ12 38 Before port 60h latch 14 IRQ13 41 Ignored 15 IRQ14 44 Ignored 16 IRQ15 47 17 OCHCK 50 Same as ISA IOCHCK going active 18 PCI INTA 53 19 PCI INTB 56 20 PCI INTC 59 21 PCI INTD 62 Intel Atom Processor E6xx Series Datasheet 229 intel Series 11 6 11 6 1 11 6 2 Table 334 Note 11 6 3 Real Time Clock Overview The Real Time Clock RTC module provides a battery backed up date and time keeping device Three interrupt features are available time of day alarm with once a second to once a month range periodic rates of 122 us to 500 ms and end of update cycle notification Seconds minutes hours days day of week month and year are counted The hour is represented in twelve or twenty four hour
213. ccess pm Offset Start 21h Alh PCI Configuration B D F Offset End Bit Range Default Access Acronym Description 07 05 0 WO RSVD Reserved Must be 0 04 0 wo SFNM Special Fully Nested Mode Should normally be disabled by writing a O to this bit If SFNM 1 the special fully nested mode is programmed Buffered Mode Must be cleared for non buffered mode Writing 1 will 03 0 wo BUF result in undefined behavior Master Slave in Buffered Mode Not used Should always be 02 9 WO MSBM programmed to 0 Automatic End of Interrupt This bit should normally be programmed 01 0 WO AEOI to 0 This is the normal end of interrupt If this bit is 1 the automatic end of interrupt mode is programmed Microprocessor Mode This bit must be written to 1 to indicate that the 00 1 WO MM controller is operating in an Intel architecture based system Writing 0 will result in undefined behavior Intel Atom Processor E6xx Series Datasheet 215 intel ACPI Devices 11 3 2 6 Offset 21h A1h OCW1 Operational Control Word 1 Interrupt Mask Table 319 21h Alh OCW1 Operational Control Word 1 Interrupt Mask Size 8 bit Default Power Well Core Access Im Offset Start 21h Alh PCI Configuration B D F Offset End Bit Range Default Access Acronym Description I nterrupt Request Mask When a 1 is written to any bit in this register the correspond
214. chronous transfers will use VCO 12 1 xd NANBEN 1 The Intel HD AudioP controller is permitted to set the No Snoop bit in the Requester Attributes of a bus master transaction In this case VCO or VC1 may be used for isochronous transfers Note This bit is not reset on D3yo7 to DO transition 10 04 0 RO RSVD Reserved Unsupported Request Reporting Enable Functionality not 03 0 R URREN implemented This bit is RW to pass PCle compliance testing Fatal Error Reporting Enable Functionality not implemented This bit 02 0 RW FEREN is RW to pass PCle compliance testing Non Fatal Error Reporting Enable Functionality not implemented 01 0 RW NFEREN This bit is RW to pass PCle compliance testing Correctable Error Reporting Enable Functionality not implemented 00 0 RW CEREN This bit is RW to pass PCle compliance testing 9 3 1 31 Offset 7Ah DEVS Device Status Register Table 208 7Ah DEVS Device Status Register Size 16 bit Default 0000h Power Well Core Access e VECES imi Offset Start 7Ah PCI Configuration B D F 0 27 0 Offset End 7Bh Bit Range Default Access Acronym Description 15 06 0 RO RSVD Reserved Transactions Pending 0 Completions for all Non Posted Requests have been received 05 0 RO TXP h 1 The Intel HD AudioP controller has issued Non Posted requests which have not been completed 04 00 0 RO RSVD Reserved 9 3 1 32 Offset FCh FD Function Disable Register Table 209 FCh FD Function Disable Regi
215. ck Down bit in Offset 00h SPIS SPI Status register is set Eight entries are available in this register to give BIOS a sufficient set of commands for communicating with the flash device while also restricting what malicious software can do This keeps the hardware flexible enough to operate with a wide variety of SPI devices Intel Atom Processor E6xx Series Datasheet 254 ACPI Devices i n tel It is recommended that BIOS avoid programming Write Enable opcodes in this menu Malicious software could then perform writes and erases to the SPI flash without using the atomic cycle mechanism Write Enable opcodes should only be programmed in the Offset 54h PREOP Prefix Opcode Configuration Table 381 58h OPMENU OPCODE Menu Configuration Size 64 bit Default 00000005h Power Well Core Access DIE 0 31 Offset Start 3078h PCI Configuration B D F 0 31 0 Offset End 307Fh Memory Mapped IO BAR RCBA Offset Bit Range Default Access Acronym Description 63 56 0 RWS AO7 Allowable Opcode 7 See the description for bits 7 0 55 48 0 RWS AO6 Allowable Opcode 6 See the description for bits 7 0 47 40 0 RWS AO5 Allowable Opcode 5 See the description for bits 7 0 39 32 0 RWS AO4 Allowable Opcode 4 See the description for bits 7 0 31 24 0 RWS AO3 Allowable Opcode 3 See the description for bits 7 0 23 16 0 RWS AO2 Allowable Opcode 2 See the description for bits 7 0 15 08 0 RWS AO1 Allowab
216. clock frequency The single LVDS channel can take 18 or 24 bits of RGB pixel data plus 3 bits of timing control HSYNC VSYNC DE and output them on four differential data pair outputs This display port is normally used in conjunction with the pipe functions of panel up scaling and 6 to 8 bit dither This display port is also used in conjunction with the panel power sequencing and additional associated functions When enabled the LVDS constant current drivers consume significant power Individual pairs or sets of pairs can be selected to be powered down when not being used However when disabled individual or sets of pairs will enter a low power state When the port is disabled all pairs enters a low power mode The panel power sequencing can be set to override the selected power state of the drivers during power sequencing LVDS Backlight Control To support LVDS Backlight Control the Intel Atom Processor E6xx Series will generate five types of messages to the display cluster The display cluster will in turn drive VDDEN and BKLTEN and modulate the duty cycle before driving it out through BKLTCTL These three signals are multiplexed with the normal GPIO pins under the LVDS CTL MODE address to be defined The DDC CLK and DDC DATA is emulated through software LVDS Control Signal Solution LVDS Signals lt LVD_DATAP_ 3 0 lt LVD_DATAN_ 3 0 4 LVD CLKP 4 LVD CLKN Control Intel Atom Signals GPIO Pr
217. col and timings to the desired display format and timings A maximum pixel clock of 160 MHz is supported on the SDVO interface Intel Atom Processor E6xx Series Datasheet 89 Graphics Video and Display intel 7 7 Configuration Registers 7 7 1 D2 FO PCI Configuration Registers Table 76 PCI Header for D2 Offset Register Description 00h GVD ID D2 PCI Device and Vendor ID Register 04h GVD PCICMDSTS PCI Command and Status Register 08h GVD RI DCC Revision Identification and Class Codes OCh GVD HDR Header Type Memory Mapped Address Range This is the base address for all 10h GVD MMADR memory mapped registers 1 O Base Address This is used only by SBIOS and is the base address Dn SR IUDA for the MMIO INDEX and MMIO DATA registers 18h GVD GMADR Graphics Memory Address Range 1Ch GVD GTTADR Graphics Translation Table Address Range 2Ch GVD SSID Subsystem Identifiers 34h GVD CAPPOI NT Capabilities Pointer 3Ch GVD INTR Interrupt This register is programmed by SBIOS It is not used by the graphics display driver 50h GVD MGGC Graphics Control 5Ch GVD BSM Base of Stolen Memory 60h GVD MSAC Multi Size Aperture Control 90h GVD MSI_CAPID Message Signaled Interrupts Capability ID and Control Register 94h GVD MA Message Address 98h GVD MD Message Data BOh GVD VCID Vendor Capability ID B4h GVD VC Vendor Capabilities C4h GVD FD Functional Disable This register is
218. common AST1 The writing of this by field byte even if just writing back the ASLE SCRATCH original contents will trigger a display controller interrupt when the 15 8 00h RW TRIGGER 1 Memory interface register bits IER O 1 and IMR O0 0 If written as x part of a 16 bit or 32 bit write only one interrupt is generated in common ASTO The writing of this by field byte even if just writing back the original contents will trigger a display controller interrupt when the A ASLE SCRATCH E a Ge 7 0 00h RW TRIGGER 0 memory interface register bits IER O 1 and IMR 0 0 If written as part of a 16 bit or 32 bit write only one interrupt is generated in common Table 101 F4h GVD LBB Legacy Backlight Brightness Sheet 1 of 2 Size 32 bit Default 00000000h Power Well Core Access d D F 0 2 Offset Start F4h PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 39h Bit Range Default Access Acronym Description Software scratch byte 3 Any write to this byte even writing back the 31 24 00h RW SCRATCH 3 same value read will trigger GVD to send the contents of LEGACY BACKLIGHT BRIGHTNESS byte to the VSunit Intel Atom Processor E6xx Series Datasheet 101 m e n tel Graphics Video and Display Table 101 F4h GVD LBB Legacy Backlight Brightness Sheet 2 of 2 Size 32 bit Default 00000000h Power Well Core Access e TS Offse
219. cture partitioning The new architecture partitioning integrates the 3D graphics engine memory controller and other blocks with the IA CPU core Please refer to subsequent chapters for a detailed description of functionality The processor departs from the proprietary chipset interfaces used by other IA CPUs to an open standard industry proven PCI Express v1 0 interface This allows it to be paired with customer defined IOH ASIC FPGA and off the shelf discrete components This provides utmost flexibility in IO solutions This is important for deeply embedded applications in which lOs differ from one application to another unlike traditional PC like applications Figure 1 shows an example system block diagram Section 1 3 provides an overview of the major features of the processor System Block Diagram Example Core Processor Intel Atom Processor E6xx Series Integrated Graphic and Video LPC SMBus 1 0 PCle 4x1 em em em pen pm pm pm eje ze en en mn pe pm m m Segment dependent PCI e devices M vn zm eee ee omm em rm omm omm omm omm omm Intel High Memory Controller Definition Audio pm rem rm mm ve Intel Atom Processor E6xx Series Datasheet 23 1 1 intel Introduction Technology Terminology Term Description ACPI Advanced Configuration and Power Interface ADD2 Ad
220. d location in the I O memory space 20h for the master controller and AOh for the slave controller ICWI1 A write to the master or slave controller base address with data bit 4 equal to 1 is interpreted as a write to CW1 Upon sensing this write 8259 expects three more byte writes to 21h for the master controller or A1h for the slave controller to complete the ICW sequence A write to ICW1 starts the initialization sequence during which the following automatically occur Intel Atom Processor E6xx Series Datasheet 219 intel Seniesa 11 3 4 2 11 3 4 3 11 3 4 4 11 3 5 11 3 6 11 3 6 1 Following initialization an interrupt request IRQ input must make a low to high transition to generate an interrupt The Interrupt Mask Register is cleared e RQ7 input is assigned priority 7 The slave mode address is set to 7 Special Mask Mode is cleared and Status Read is set to IRR I CW2 The second write in the sequence ICW2 is programmed to provide bits 7 3 of the interrupt vector that will be released during an interrupt acknowledge A different base is selected for each interrupt controller ICW3 The third write in the sequence CW3 has a different meaning for each controller For the master controller CW3 is used to indicate which IRQ input line is used to cascade the slave controller Within the processor IRQ2 is used Therefore bit 2 of ICW3 on the master controller is set to a 1 and
221. d to address bits A 31 20 of the 32 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be O Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary Intel Atom Processor E6xx Series Datasheet 119 m e n tel PCI Express Table 143 Offset 24h PMB Prefetchable Memory Base Address Size 16 bit Default 0000h Power Well Core Access e Offset Start 24h PCI Configuration B D F 0 23 26 0 Offset End 25h Bit Range Default Access Acronym Description Prefetchable Memory Base Address This corresponds to A 31 20 of 15 04 000h RW PMB the lower limit of the memory range that will be passed to PCI Express 03 00 Oh RW RSVD Reserved 8 2 1 18 PML Prefetchable Memory Limit Address This register controls the CPU to PCI Express prefetchable memory access routing based on the following formula PREFETCHABLE MEMORY BASE lt address lt PREFETCHABLE MEMORY LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 32 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Note that prefetchable memory range is
222. device which interrupt pint to report in the IPIN register of their configuration space as shown in Table 47 Table 47 I nterrupt Pin Configuration Bits Pin Bits Pin Oh No Interrupt 1h INTA B 2h INTB B 3h INTC B 4h INTD B 5h Fh Reserved 5 5 2 1 Offset 3100h D311P Device 31 Interrupt Pin Table 48 3100h D311P Device 31 Interrupt Pin Size 32 bit Default Power Well Access Memory Mapped IO BAR RCBA Offset 3100h Bit Range Default Access Acronym Description 31 04 0 RO RSVD Reserved 03 00 Oh RO LIP LPC Bridge Pin The LPC bridge does not generate an interrupt 5 5 2 2 Offset 3110h D271P Device 27 Interrupt Pin Table 49 3110h D271P Device 27 Interrupt Pin Size 32 bit Default Power Well Access Memory Mapped IO BAR RCBA Offset 3110h Bit Range Default Access Acronym Description 31 04 0 RO RSVD Reserved Y Intel HD Audio Pin Indicates which pin 03 00 n RW PRALE the Intel HD Audio controller uses d 5 5 2 3 Offset 3118h DO2IP Device 2 Interrupt Pin Table 50 3118h DO2IP Device 2 Interrupt Pin Size 32 bit Default Power Well Memory Mapped IO BAR RCBA Offset 3118h Bit Range Default Access Acronym Description 31 04 0 RO RSVD Reserved 2 Graphics Pin Indicates which pin the graphics controller uses for 03 00 1h RW GP interrupts Intel Atom Processor E6xx Series Datasheet 62 Register and Me mory Mapping Offset 3120h D261P Device 26 Interrupt Pin
223. dressable by the processor is 8 MB 8 MB is hardware allowed BIOS address decode range Data throughput of the SPI bus is 20 Mbps Note that the SPI does not provide support for very large BIOS sizes as easily as the FWH interface The processor SPI interface is restricted to one Chip Select pin The Serial Peripheral Interface SPI is a 4 pin interface that provides a potentially lower cost alternative for system flash versus the Firmware Hub interface that is available on the LPC pins External I nterface SPI Pin Interface Signal s Width Type 10 Type Description SPI_SCLK 1 O LVTTL 3 3V Serial bit rate clock 20 33 MHz SPI_CS 1 O LVTTL 3 3V CS for slave SPI_MOSI 1 O LVTTL 3 3V Master data out Slave In SPI_MISO 1 l LVTTL 3 3V Master data in Slave out Intel Atom Processor E6xx Series Datasheet 246 ACPI Devices i n tel Table 369 GPIO Boot Source Selection GPI O 0 Description 1 Boot from SPI 0 Boot from LPC 11 9 4 SPI Protocol Communication on the SPI bus is done with a Master Slave protocol Typical bus topologies call for a single SPI Master with a single SPI Slave The SPI interface consists of a four wire interface clock CLK master data out Master Out Slave In MOSI master data in Master In Slave Out MI SO and an active low chip select CS 11 9 4 1 SPI Pin Level Protocol SPI communicates utilizing a synchronous protocol
224. e BIOS in the SPI Control address data and opcode configuration registers in Section 11 9 5 1 The opcode type in Offset 56h OPTYPE Opcode Type Configuration and data byte count fields in Offset 54h PREOP Prefix Opcode Configuration determine how many clocks to run before deasserting the chip enable The flash data is always shifted in for the number of bytes specified and the BIOS out data is always shifted out for the number of data bytes specified Note that the hardware restricts the burst lengths that are allowed The status bit in Offset 00h SPIS SPI Status indicates when the cycle has completed on the SPI port allowing the host to know when read results can be checked and or when to initiate a new command The processor also provides the Atomic Cycle Sequence for performing erases and writes to the SPI flash in Offset 02h SPIC SPI Control When this bit is 1 and the SPI Cycle Go bit is written to 1 a sequence of cycles is performed on the SPI interface In this case the specified cycle is preceded by the Prefix Command 8 bit programmable opcode and followed by repeated reads to the Status Register opcode 05h until bit O indicates the cycle has completed The hardware does not attempt to check that the programmed cycle is a write or erase If a Programmed Access is initiated SPI Cycle Go written to 1 while the SPI host interface logic is already busy with a Direct Memory Read then the SPI Host hardware will ho
225. e DDRIO PHY circuits Both Self Refresh modes are transparent to the DRAM device and the entry and exit commands are the same Dynamic Self Refresh Mode The memory controller also supports Dynamic Self Refresh when the Intel Atom Processor E6xx Series is in C2 C6 idle states It wakes the memory from Self Refresh whenever memory access is needed then it re enters Self Refresh mode when no more requests are needed Both Deep and Shallow Self Refresh modes are supported for Dynamic Self Refresh selected by means of a configuration bit Page Management The memory controller is capable of closing pages after these pages have been idle for an optimized period of time This page management mechanism provides both power and performance benefits From a performance standpoint it helps since it can reduce the number of page misses encountered From a power perspective it allows the memory devices to reach the precharge power management state power down when all banks are closed which has better power saving characteristics on most memory devices than when the pages are left open and the device is in Active Power Down mode Refresh Mode The memory controller handles all DRAM refresh operations when the device is not in Self Refresh To reduce the performance impact of DRAM refreshes the memory controller can wait until eight refreshes are required and then issue all of these refreshes This provides some increase in efficiency overall low
226. e Enable 34 37 RGGPE Resume Well GPIO GPE Enable 38 3B RGSMI Resume Well GPIO SMI Enable 3C 3F RGTS Resume Well GPIO Trigger Status The format of these registers is the same as their core well counter parts see Section 11 7 1 the difference being these registers live in the resume well which range bitO to bit8 11 7 2 1 Offset 20h RGEN Resume Well GPIO Enable Table 350 20h RGEN Resume Well GPIO Enable Sheet 1 of 2 Size 32 bit Default 000001FFh Power Well Resume Access DF 0 31 Offset Start 20h PCI Configuration B D F 0 31 0 Offset End 23h Memory Mapped IO BAR GPIO BAR 10 Offset Bit Range Default Access Acronym Description 31 09 0 RO RSVD Reserved Intel Atom Processor E6xx Series Datasheet 237 intel ACPI Devices Table 350 20h RGEN Resume Well GPI O Enable Sheet 2 of 2 Size 32 bit Default 000001FFh Power Well Resume Access D F 0 31 Offset Start 20h PCI Configuration B D F 0 31 0 Offset End 23h Memory Mapped IO BAR GPIO BAR 10 Offset Bit Range Default Access Acronym Description Enable When set enables the pin as a GPIO When cleared the pin if 08 00 1FFh RW EN muxed returns to its normal use This field has no effect on unmuxed PIOs 11 7 2 2 Offset 24h RGIO Resume Well GPIO I nput Output Select Table 351 24h RGIO Resume Well GPIO Input Output Select Si
227. e Enable Table 353 2Ch RGTPE Resume Well GPIO Trigger Positive Edge Enable Size 32 bit Default 00000000h Power Well Resume Access Offset Start 2Ch PCI Configuration B D F 0 31 0 Offset End 2Fh Memory Mapped IO BAR GPIO BAR 10 Offset Bit Range Default Access Acronym Description 31 09 0 RO RSVD Reserved Trigger Enable When set the corresponding GPIO if enabled as input via RGIO IO n will case an SMI SCI when a 0 to 1 transition occurs 08 00 0 RW TE When cleared the GPIO is not enabled to trigger an SMI SCI on a 0 to 1 transition This bit has no meaning if GIO IO n is cleared i e programmed for output 11 7 2 5 Offset 30h RGTNE Resume Well GPI O Trigger Negative Edge Enable Table 354 30h RGTNE Resume Well GPI O Trigger Negative Edge Enable Size 32 bit Default 00000000h Power Well Resume Access DF 0 31 Offset Start 30h PCI Configuration B D F 0 31 0 Offset End 33h Memory Mapped IO BAR GPIO BAR 10 Offset Bit Range Default Access Acronym Description 31 09 0 RO RSVD Reserved Trigger Enable When set the corresponding GPIO if enabled as input via RGIO IO n will case an SMI SCI when a 1 to 0 transition occurs 08 00 0 RW TE When cleared the GPIO is not enabled to trigger an SMI SCI on a 1 to 0 transition This bit has no meaning if RGIO IO n is cleared i
228. e Time Device Write Time Description Worst Case Typical PMC PM25LV 41 8 s Atmel AT25F 1 7 s Two options for byte writes with this device byte write and byte write with auto address increment However only the standard byte write is SST SST25VF 13s supported by the processor The Worst Case time accounts for re transmission of Write Enable Write with Address Read Status and platform inter command delay total of 5 us NexFlash NX25P 41 16 s ST M25P80 4 11 71s ST M45P80 41 10s SPI Initialization This section provides a high level description of the steps that the BIOS should take upon coming out of RESET when using SPI Flash 1 Boot vector fetch and other initial BIOS reads using Direct Memory Reads some of which are 64 byte code reads Caching is enabled in hardware by default to improve performance on consecutive reads to the same line Turn on the SPI Prefetching policy in the LPC Bridge Configuration Space Offset D8h BC BIOS Control Register This policy bit is in configuration space to avoid requiring protected memory space early in the boot process Copy the various BIOS modules out of the SPI Flash using Direct Memory Reads It is assumed that these reads are shorter than 64 bytes and are targeted to consecutive addresses hence the prefetch mechanism improves the performance of this sequence 4 Turn off the SPI Prefetch policy Program opcode registe
229. e defined I O address range will be aligned to a 4 kB boundary Table 138 Offset 1Ch I OBASE 1 O Base Address Size 8 bit Default 00h Power Well Core Access y Offset Start 1Ch PCI Configuration B D F 0 23 26 0 Offset End 1Ch Bit Range Default Access Acronym Description 1 O Base Address O Base bits corresponding to address lines 15 12 for 4 kB alignment Bits 11 0 are assumed to be padded to 000h The 07 04 Oh RW IOBA BIOS must not set this register to 00h otherwise OCF8h OCFCh accesses will be forwarded to the PCI Express hierarchy associated with this device e 1 O Base Address Capability The bridge does not support 32 bit 1 0 03 00 Oh RO IOBC addressing Intel Atom Processor E6xx Series Datasheet 117 intel PCI Express 8 2 1 13 I OLI MIT 1 O Limit Address This register controls the CPU to PCI Express I O access routing based on the following formula lO BASE lt address lt IO LIMIT Only the upper four bits are programmable For the purpose of address decode address bits A 11 0 are assumed to be FFFh Thus the top of the defined I O address range will be at the top of a 4 kB aligned address block Table 139 Offset 1Dh I OLI MIT 1 O Limit Address Size 8 bit Default 00h Power Well Core Access i CE C Offset Start 1Dh PCI Configuration B D F 0 23 26 0 O
230. e power consumption Power Down mode and Self Refresh The memory controller manages these two power saving modes and in addition controls a number of its own components to further reduce power consumption The memory controller supports memory power management in the following conditions e CO C1 Power Down C2 C6 Dynamic Self Refresh S3 Self Refresh Intel Atom Processor E6xx Series Datasheet 69 m e n tel Memory Controller 6 4 2 6 4 3 6 4 4 6 5 Powerdown Modes The memory controller employs aggressive use of memory power management features When a rank is not being accessed the CKE for that rank is deasserted bringing the devices into a Power Down state The memory controller supports Fast Power Down for DDR2 DRAMs Self Refresh Mode Self Refresh can be used to retain data in the DRAM devices even if the remainder of the system is powered down When the memory is in Self Refresh the memory controller disables all output signals except the CKE signals The controller will enter Self Refresh as part of the S3 sequence and stay in Self Refresh until an exit sequence is initiated There are two Self Refresh modes that the memory controller provides Shallow and Deep Deep Self Refresh provides for additional power savings over Shallow Self Refresh but at the cost of increased exit latency The power savings for Deep Self Refresh are achieved by optimizations in power gating and clock gating for th
231. e standard ISA location for the real time clock Locations 72h and 73h are for accessing the extended RAM The extended RAM bank is also accessed using an indexed scheme I O address 72h is used as the address pointer and I O address 73h is used as the data register Index addresses above 127h are not valid 2 Writes to 72h 74h and 76h do not affect the NMI enable bit 7 of 70h Port 70h is not directly readable The only way to read this register is through Alt Access mode Although RTC Index bits 6 0 are readable from port 74h bit 7 will always return O If the NMI enable is not changed during normal operation software can alternatively read this bit once and then retain the value for all subsequent writes to port 70h Indexed Registers The RTC contains two sets of indexed registers that are accessed using the two separate Index and Target registers 70 71h or 72 73h as shown below Intel Atom Processor E6xx Series Datasheet 230 ACPI Devices Table 335 RTC Indexed Registers Start End Name 00h 00h Seconds 01h 01h Seconds Alarm 02h 02h Minutes 03h 03h Minutes Alarm 04h 04h Hours 05h 05h Hours Alarm 06h 06h Day of Week 07h 07h Day of Month 08h 08h Month 09h 09h Year OAh OAh Register A OBh OBh Register B OCh OCh Register C ODh ODh Register D OEh 7Fh 114 Bytes of User RAM 11 6 3 1 Offset OAh Register A This registe
232. e start of a 64B block Le address bits 5 0 are 00h If this is not the case then the processor only reads the length specified by the current read If the read is aligned to the start of the 64B block with the SPI Prefetch Enable bit set then the read burst continues on the SPI pins until 64 bytes have been received Note that the processor always performs the entire 64B burst when the conditions are met to perform the prefetch when the memory read request is received This policy can result in a large penalty if the read addresses are not sequential Software is allowed and encouraged to dynamically turn on prefetching only when the reads are sequential for example if shadowing the BIOS using consecutive DWord reads When prefetching is enabled the read buffer must be enabled for caching If the processor detects a read to the range that is currently in or being fetched for the read buffer it will not perform another read cycle on the SPI pins Instead the data is returned from the read buffer Note that the entire read request must be contained in the cache in order to avoid running the read on the SPI interface The following events invalidate the read buffer cache 1 A Programmed Access begins Note that if the cycle is blocked from running for protection or other reasons the cache is not flushed 2 A Memory read to a BIOS range that does not hit the range in the read buffer 3 System Reset 4 Software setting the Cache Disa
233. e that a timeout is not about to occur before disabling the timer A reload sequence is suggested 00 Oh Watchdog Timer Lock Setting this bit locks the values of this register until a hard reset occurs or power is cycled 0 Unlocked Default RWL WDT LOCK 1 Locked Note Writing a 0 has no effect on this bit Write is only allowed from 0 to 1 once It cannot be changed until either power is cycled or a hard reset occurs 11 10 4 11 10 4 1 11 10 4 2 Note Theory Of Operation RTC Well and WDT TOUT Functionality The WDT TI MEOUT bit is set to a 1 when the WDT 35 bit down counter reaches zero for the second time in a row Then the GPIO 4 pin is toggled HIGH by the WDT from the processor The board designer must attach the GPIO 4 to the appropriate external signal If WDT TOUT CNF is a 1 the WDT toggles WDT TOUT GPIO 4 again the next time a time out occurs Otherwise GPIO 4 is driven high until the system is reset or power is cycled Register Unlocking Sequence The register unlocking sequence is necessary whenever writing to the RELOAD register or either PRELOAD VALUE registers The host must write a sequence of two writes to offset WDTBA OCh before attempting to write to either the WDT RELOAD and WDT TI MEOUT bits of the RELOAD register or the PRELOAD VALUE registers The first writes are 80 and 86 in that order to offset WDTBA OCh The next write is to the pro
234. e that the data in this register may be modified by the hardware during any programmed SPI transaction Direct Memory Reads do not modify the contents of this register This last requirement is needed in order to properly handle the collision case described in Section 11 9 5 13 This register is initialized to O by the reset assertion However the least significant byte of this register is loaded with the first Status Register read of the Atomic Cycle Sequence that the hardware automatically runs out of reset Therefore bit O of this register can be read later to determine if the platform encountered the boundary case in which the SPI flash was busy with an internal instruction when the platform reset deasserted Intel Atom Processor E6xx Series Datasheet 252 ACPI Devices intel 11 9 5 6 Offset 10h 18h 20h 28h 30h 38h 40h SPID O 6 SPI Data N Table 377 10h 18h 20h 28h 30h 38h 40h SPI D O 6 SPI Data 0 6 Size 64 bit Default 00000000h Power Well Core Access D F 0 31 Offset Start 3030h at 4h PCI Configuration B D F 0 31 0 Offset End 306Ch at 4h Memory Mapped IO BAR RCBA Offset Bit Range Default Access Acronym Description SPI Cycle Data N SCD N Similar definition as SPI Cycle Data 0 63 00 0 RWO SCD However this register does not begin shifting until SPID N 1 has completely shifted in out 11 9 5 7
235. ed Master 8259 Input Mapping 8259 Input Connected Pin Function Internal Timer Counter O output or Multimedia Timer 0 IRQ1 via SERIRQ Slave Controller INTR output IRQ3 via SERIRQ PIRQx IRQ4 via SERIRQ PIRQx IRQ5 via SERIRQ PIRQx IRQ6 via SERIRQ PIRQx IRQ7 via SERIRQ PIRQx NX O U AJ U N H O Slave 8259 Input Mapping 8259 Input Connected Pin Function Inverted IRQ8 from internal RTC or HPET IRQ9 via SERIRQ SCI or PIRQx IRQ10 via SERIRQ SCI or PIRQx IRQ11 via SERIRQ SCI or PIRQx IRQ12 via SERIRQ SCI or PIRQx PIRQx IDEIRQ SERIRQ PIRQx PIRQx NL DO U B WwW N rR O The slave controller is cascaded onto the master controller through master controller interrupt input 2 Interrupts can individually be programmed to be edge or level except for IRQO IRQ2 IRQ8 Active low interrupt sources such as the PIRQ s are internally inverted before being sent to the 8259 In the following descriptions of the 8259 s the interrupt levels are in reference to the signals at the internal interface of the 8259 s after the required inversions have occurred Therefore the term high indicates active which means low on an originating PIRQ Intel Atom Processor E6xx Series Datasheet 212 ACPI Devices 11 3 2 Table 313 11 3 2 1 Table 314 intel 1 O Registers The interrupt controller registe
236. emen 229 Real Time Glock tu seas serge eec erre ee ne A TAE EEN 230 IM NNUS 230 11 6 2 MO Registers eic ELDER E VENDER ER ENEE EES RID 230 11 6 3 Indexed Registe Siaina eee tenet nnn 230 11 6 3 1 Offset OAh Register A 231 11 6 3 2 Offset OBh Register B General Configuration sss 232 11 6 3 3 Offset OCh Register C Flag Register RTC Well 232 11 6 3 4 Offset ODh Register D Flag Register RTC Well 233 11 6 4 Update Cycles corra eer tt ter AAA RE ERERSKNRRKA XRGURRAT NK KE REEF ME RA 233 11 6 5 lintert pts iicet etre xe e URRRE RR EROS omc Manian Rated VERRE RR AY VER E A RENE 233 General Purpose lO iia dai EE iate Ek d DC agin iia 234 11 7 1 Core Well GPIO I O Register 234 11 7 1 1 Offset 00h CGEN Core Well GPIO Enable oococccccccccccccnncccinnnos 234 11 7 1 2 Offset 04h CGIO Core Well GPIO Input Output Select 235 11 7 1 3 Offset 08h CGLVL Core Well GPIO Level for Input or Output 235 11 7 1 4 Offset OCh CGTPE Core Well GPIO Trigger Positive Edge Enable 235 11 7 1 5 Offset 10h CGTNE Core Well GPIO Trigger Negative Edge Enable236 11 7 1 6 Offset 14h CGGPE Core Well GPIO GPE Enable 236 11 7 1 7 Offset 18h CGSMI Core Well GPIO SMI Enable 236 11 7 1 8 Offset 1Ch CGTS Core Well GPIO Trigger Status 237 11 7 2 Resume Well GPIO 1 0 Registers
237. emented as RW bits 9 3 1 40 Offset 11Ah VCOSTS VCO Resource Status Register Table 217 11Ah VCOSTS VCO Resource Status Register Size 16 bit Default 0000h Power Well Core Access D F 0 27 Offset Start 11Ah PCI Configuration B D F 0 27 0 Offset End 11Bh Bit Range Default Access Acronym Description 15 00 0 RO RSVD Reserved 9 3 1 41 Offset 11Ch VC1CAP VC1 Resource Capability Register Table 218 11Ch VC1CAP VC1 Resource Capability Register Size 32 bit Default 0000 0000h Power Well Core Access d D F 0 27 Offset Start 11Ch PCI Configuration B D F 0 27 0 Offset End 11Fh Bit Range Default Access Acronym Description 31 00 0 RO RSVD Reserved 9 3 1 42 Offset 120h VCICTL VC1 Resource Control Register Table 219 120h VCICTL VC1 Resource Control Register Sheet 1 of 2 Size 32 bit Default 0000 0000h Power Well Core Access D F 0 27 Offset Start 120h PCI Configuration B D F 0 27 0 Offset End 123h Bit Range Default Access Acronym Description VC1 Enable 0 VCI is disabled at 9 RW VCIEN 1 VC1 is enabled Note This bit is not reset on D3yo7 to D1 transition 30 27 0 RO RSVD Reserved o VC1 ID This field assigns a VC ID to the VC1 resource This field is not 26 24 000 RW VEHI used by the processor but it is RW to avoid confusing software Intel Atom Processor E6
238. en the value reported in the Data Link Layer Link Active field of the Link Status register is 08 0 RWC LASC changed In response to a Data Link Layer State Changed event software must read the Data Link Layer Link Active field of the Link Status register to determine if the link is active before initiating configuration cycles to the hot plugged device 07 0 RO RSVD Reserved Presence Detect State f XCAP SI is set indicating that this root port 06 0 RO PDS spawns a slot this bit indicates whether a device is connected 1 or empty 0 If XCAP SI is cleared this bit is a 1 05 0 RO MS MRL Sensor State Reserved as the MRL sensor is not implemented 04 0 RO RSVD Reserved Presence Detect Changed This bit is set by the root port when the 03 0 RWC PDC PDS bit changes state 02 0 RO MSC MRL Sensor Changed Reserved as the MRL sensor is not implemented 01 0 RO PFD Power Fault Detected Reserved as a power controller is not implemented Attention Button Pressed Reserved as Attention Button Pressed is not 00 0 RO ABP implemented Intel Atom Processor E6xx Series Datasheet 128 PCI Express 8 2 2 12 RCTL Root Control Table 161 Offset 5Ch RCTL Root Control Size 16 bit Default 0000h Power Well Core Access NIE Offset Start 5Ch PCI Configur
239. eneratlon iisseiscieee e renis dere e aere ENEE Pe nda 112 8 1 3 Additional Clarifications 1 0 0 0 meme eem 112 8 1 3 1 Non Snoop Cycles Are Not Supported sssseseene 112 8 2 PCI Express Configuration Registers ccc ceee cette eee eee teeta mmm 112 8 2 1 PCI Type 1 Bridge Header 112 8 2 1 1 VID Vendor Identiflcation cece eeee mm 113 8 2 1 2 DID Device Identification cece eee eee m 113 8 2 1 3 CMD PCI Command rete ero endl sae ae teres Pe eterne seg 114 8 2 1 4 PSTS Primary Status 114 8 2 1 5 RID Revision Identification e 115 8 2 1 6 CC Class Code ioc e e Rp Rx E SEEN EH RENI 115 8 23 7 CES Cache Line SIZe ise eer rente EES E 116 8 2 1 8 HTYPE Header Type ioi ast vedere ve ea ebd da 116 8 2 1 9 PBN Primary Bus Number 116 8 2 1 10 SCBN Secondary Bus Number 116 8 2 1 11 SBBN Subordinate Bus Number 117 8 2 1 12 IOBASE I O Base Address 117 8 2 1 13 IOLIMIT I O Limit Address sssssssesenm ee een eaed 118 8 2 1 14 SSTS Secondary Status 118 8 2 1 15 MB Memory Base Address 119 8 2 1 16 ML Memory Limit Address 119 8 2 1 17 PMB Prefetchable Memory Base Address 119 8 2 1 18 PML Prefetchable Memory Limit Address 120 8 2 1 19 CAPP Capabilities Pointer ssseemm e 120 8 2 1 20 ILINE Interrupt Une 120 8 2 1 21 PIN Interrupt Pih sie en rk hrec ehe xxx RR Ent R
240. enner SEENEN EENS E RR Ee res 50 3 14 Integrated Termination Resistors cece een neta ene 50 4 0 System Clock Domaines 51 5 0 Register and Memory Mapping emen renes 53 E MEG 53 5 2 E nde e d Lu EE 53 5 3 Systemi Memory Map see n EA EE ease 54 5 3 dO Map EE 56 5 3 1 1 Fixed I O Address Range 56 5 3 1 2 Variable I O Address Range 57 5 3 2 PCI Devices and Functions 0coooocccccnnoncocnnnnnnnnnononnnnnnnrn nn nemen enemies 57 5 4 Register Access Method cos casse sese ent SEENEN ENEE ve ERR Fe deed d er ebd da 58 5 4 1 Direct Register Access 58 5 4 1 1 Hard Coded lO Access 58 FAL IO BAR EE 59 5 4 1 3 Hard Coded Memory Access mee 59 5 4 1 4 Memory BAR oerte ERKENNEN a ERR EXTA TERX RE ERE Ne 59 5 4 2 Indirect Register ACCess issssseseess sienne nene rene haee nn deme nen keen dune ANN 59 5 42 10 PCI Config SPACE Sarnin eri repete cede gener kn rd d eee etes 59 5 5 Bridging and Configuration sr deg kx ERROR ERG XERX AR P GR YR a GR KR 60 5 5 1 Root Complex Topology Capability Structure 60 5 5 1 1 Offset 0000h RCTCL Root Complex Topology Capabilities List 60 5 5 1 2 Offset 0004h ESD Element Self Description 61 5 5 1 3 Offset 0010h HDD Intel High Definition Audio DIESEHIpHOB buses 61 5 5 1 4 Offset 0018h HDBA Intel High Definition Audio Base Address 61 5 5 2 Interrupt Pin Configuration 00 cccc cece cece eee eee eee ne eee te eee 62 5 5 2 1 Offset 310
241. ential signal pair LVD DATAP 2 O Core Channel A Differential Data Output Positive LVDS Differential signal pair LVD DATAP 3 O Core Channel A Differential Data Output Positive LVDS Differential signal pair O Channel A Differential Clock Output Negative EMO CERN LVDS Core Differential signal pair O Channel A Differential Clock Output Positive ye LVDS Core Differential signal pair LVD IBG d Core Reference Current Resistor on motherboard l LVD_VBG Power Core External Voltage Ref BG 1 25 V 1 5 LVD_VREFL Core VREFL Needed for analog loop back LVD VREFH A Core VREFH Needed for analog loop back Intel Atom Processor E6xx Series Datasheet 33 intel Signal Description 2 2 2 Serial Digital Video Output SDVO Signals Table 6 Serial Digital Video Output Signals Signal Name Direction Type Power Well Description SDVO_REDP o SDVO_REDN PCle Core Serial Digital Video Red SDVO_RED is a differential data pair that provides red pixel data for the SDVO channel during Active periods During blanking periods it may provide additional such as sync information auxiliary configuration data etc This data pair must be sampled with respect to the SDVO_CLK signal pair SDVO_GREENP o SDVO_GREENN PCle Core Serial Digital Video Green SDVO_GREEN is a differential data pair that provides green pixel data for the SDVO channel during Active periods During blankin
242. er Registers messe sese eene nee memes 241 359 00h HCTL Host Control Register 241 360 O1h HSTS Host Status Register 242 361 02h HCLK Host Clock Divider o i0 ccc cece NEES NEEN EE teenth ene s 243 362 04h TSA Transmit Slave Address 1 0 00 memes emen nns 243 363 05h HCMD Command Register 243 364 06h HDO Host Data Den Eet t Hee dE ENEE EE FRA RE Ra XE E EUR ERN EE 244 365 07h EDT s Host Data EE 244 366 20h 3Fh HBD Host Block Data 244 367 SMBUS TIMINGS scri rent onkeskut t Mpix O NE A 245 368 SPI Pin Nterace entendu PUDE AE e ERE IE REC EUR X E d BEE NUMEN 246 369 GPIO Boot Source Gelection cece en meme seme memes 247 370 anale c 248 37 SPL Cycle TIMINGS ERE TT UL DUERME 249 372 Bus 0 Device 31 Function O PCI Register Mapped Through RCBA BAR 250 Intel Atom Processor E6xx Series Datasheet 19 ite Di 373 00h SPIS SPI TEE 250 374 02h SPICG SPI Te EE 251 375 04h SPIA SPI Address ec tee cp alere eese a ais 252 EREECHEN 252 377 10h 18h 20h 28h 30h 38h 40h SPID O 6 SPI Data 0 6 eect eee eee es 253 378 50h BBAR BIOS Base Address 253 379 54h PREOP Prefix Opcode Configuration sessssssssssssee nmm emnes 254 380 56h OPTYPE Opcode Type petere at 254 381 58h OPMENU OPCODE Menu Configuration sss mme 255 382 60h PBRO Protected BIOS Range 20 255 383 Byte Enable
243. er compliance eye diagram of PCI Express specification Should be used as the RX device when taking measurements 6 Applicable to the following signals PCIE CLKINN P 7 Measurement taken from differential waveform 8 Measurement taken from single ended waveform 9 Vcnoss is defined as the voltage where Clock Clock B 10 Only applies to the differential rising edge i e Clock rising and Clock B falling 11 The total variation of all Vcross measurements in any particular system This is a subset of VerossMIN VcrossMax Vcnoss absolute allowed The intent is to limit Vcross induced modulation by setting Vcnoss var to be smaller than Vcross absolute 12 The max voltage including overshoot 13 The min voltage including undershoot Intel Atom Processor E6xx Series Datasheet 280 m Ballout and Package Information i n tel 14 0 Ballout and Package I nformation The Intel Atom Processor E6xx Series comes in an 22 mm x 22 mm Flip Chip Ball Grid Array FCBGA package and consists of a silicon die mounted face down on an organic substrate populated with 676 solder balls on the bottom side Capacitors may be placed in the area surrounding the die Because the die side capacitors are electrically conductive and only slightly shorter than the die height care should be taken to avoid contacting the capacitors with electrically conductive materials Doing so may short the capacitors and possibly damage the device or render i
244. er percentage of impact to the available bandwidth but there will also be a longer period of time that the memory will be unavailable roughly 8 x tgrec refresh cycle time Intel Atom Processor E6xx Series Datasheet 70 m Memory Controller n tel 6 6 Table 68 Supported DRAM Configurations The memory controller supports a single 32 bit channel and up to eight soldered down DDR2 DRAM devices The memory controller does not support SODI MM or any type of DIMMs Table 68 shows the different supported memory configurationsIntel Atom Processor E6x5C Series based Platform Design Guide Supported Memory Configurations for DDR2 Total Rank O Rank 1 Memory Rank Density DRAM Chip Rank Density DRAM Chip Config Size Mem DRAM Chips Data Mem DRAM Chips Data Size Chip Rank Width Size Chip Rank Width 128 MB 128 MB 256 Mb 4 x8 2Top 2Bot 256 MB 256 MB 512 Mb 4 x8 2Top 2Bot 512 MB 512MB 16Gb 4 x8 2Top 2Bot 1 GB 1 GB 2 Gb 4 x8 2Top 2Bot 128 MB 128 MB 512 Mb 2 x16 KEE 256 MB 256MB 16Gb 2 x16 o 512 MB 512MB 26Gb 2 x16 ud 256 MB 128 MB 512 Mb 2 x16 128MB 512 Mb 2 x16 2Top 2Bot 512 MB 256 MB 16Gb 2 x16 256MB 16Gb 2 x16 2Top 2Bot 1GB 512MB 26Gb 2 x16 512MB 26Gb 2 x16 2Top 2Bot 1GB 512MB 16Gb 4 X8 512MB 16Gb 4 x8 4Top 4Bot 2 GB 1 GB 2 Gb 4 x8 1 GB 2 Gb 4 x8 4Top 4Bot Intel
245. erations for other counters may be inserted between the reads If a counter is latched once and then latched again before the count is read the second Counter Latch Command is ignored Table 300 43h CLC Counter Latch Command Size 8 bit Default XOh Power Well Core Fixed IO Address 43h Bit Range Default Access Acronym Description Counter Selection Selects the counter for latching If 11 is written then the write is interpreted as a read back command 07 06 00 RW CL 00 Counter 0 01 Counter 1 10 Counter 2 e Counter Latch Command Write 00 to select the Counter Latch 05 04 0 RW Command 03 00 0 RO RSVD Reserved Must be 0 11 1 5 3 Offset 40h 41h 42h Interval Timer Status Byte Format Register Each counter s status byte can be read following a Read Back Command If latch status is chosen bit 4 0 Read Back Command as a read back option for a given counter the next read from the counter s Counter Access Ports Register 40h for counter 0 41h for counter 1 and 42h for counter 2 returns the status byte The status byte returns the following Intel Atom Processor E6xx Series Datasheet 203 intel ACPI Devices Table 301 40h 41h 42h Interval Timer Status Byte Format Register Size 8 bit Default OXXXXXXXb Power Well Core Access e Offset Start 40h 41h 42h PCI Configuration B D F
246. erved Stream Interrupt Enable When set to 1 the individual Streams are enabled to generate an interrupt when the corresponding stream status INTSTS bits get set The streams are numbered and the SIE bits assigned sequentially based 03 00 Oh RW SIE on their order in the register set Bit 3 Output Stream 2 OS2 Bit 2 Output Stream 1 OS1 Bit 1 Input Stream 2 1S2 Bit 0 Input Stream 1 1S1 9 3 2 1 13 Offset 24h INTSTS Interrupt Status Register Table 238 24h INTSTS Interrupt Status Register Size 32 bit Default 0000 0000h Power Well Core Access D E 0 27 Offset Start 24h PCI Configuration B D F 0 27 0 Offset End 27h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description Global I nterrupt Status This bit is an OR of all of the interrupt status 31 0 RO GIS bits in this register Note This bit is not affected by the D3yor to DO transition Controller nterrupt Status Status of general controller interrupt 1 indicates that an interrupt condition occurred due to a Response Interrupt a Response Buffer Overrun Interrupt or a SDIN State Change event The exact cause can be determined by interrogating other registers This bit is an OR of all of the stated interrupt status bits for this 30 0 RO CIS register Note This bit is set regardless of the state of the corresponding interrupt enable bit but a hardware interrupt will not be generated unless the corresponding enable bit is set This bit is no
247. es Ball Map Sheet Loft 285 14 Intel Atom Processor E6xx Series Ball Map Sheet 2 ofbl mm 286 15 Intel Atom Processor E6xx Series Ball Map Sheet 3 of ai 287 16 Intel Atom Processor E6xx Series Ball Map Sheet 4 of ai 288 17 Intel Atom Processor E6xx Series Ball Map Sheet Bopi 289 Intel Atom Processor E6xx Series Datasheet 12 Contents i n tel Tables 1 PCI Devices and FUNCION Sois id aa de Kr Rd 26 2 Intel Atom Processor E6xx Series SKU for Different Segment 30 3 Bufer TYPOS UEM 31 4 System Memory Sigfials i iere eee riter eerte ka eer o ee Ca sire tes Cete d e e vele du 32 Be UN DS EE 325 eases LL 33 6 Serial Digital Video Output Signals cece eee nemen ene 34 Je PCI EXxpress Sigtials x iue temet Hei ERR EE 35 8 Intel High Definition AudioP Interface Slonals ees 35 9 APC Interface EE 36 10 SMBUS Interface Signals tert EE eror ii digas 36 11 SPI Interface Signals ooi e PR RR ELIT REEL RE ROMA Ir ia PT NUR LI RE dedit 36 12 Power Management Interface Gionals cc nemen eene enn 37 13 Real Time Clock Interface Gionals emnes een 38 14 JTAG and Debug Interface Gionals mnm eee nennen 38 15 Miscellaneous Signals and Clocks 2 0 ec tenet eene 39 16 General Purpose I O Gionals em eme semen eee see e senes 42 T7 Functional Straps gud ENEE ER AE EE 42 18 Power and Ground Signals eter ces RA EAN EE 43 19 Reset State Definitions oce eene antep beer emi ei uA ea VEL P E E
248. es a geed Ee 36 2 7 SPI Interrace Signals oe 36 2 8 Power Management Interface Gionals memes 37 2 9 Real Time Clock Interface Signals cect meme memes 38 2 10 JTAG and Debug Interface eee re oie oa re Pr PH d ed 38 2 11 Miscellaneous Signals and Cocke enses 39 2 12 General Purpose Il Os coi ertt sie eege Eeer a pia 42 2 13 Functional Straps EE 42 2 14 Power and Ground le EE 43 3 0 Pin States E 45 3 1 Pin States i Ons Genet eec Llerena bete a cnet bra Deere chal 45 3 2 System Memory Sigrials ore E AE EE SERERE ERAN MERI EST 45 3 3 Integrated Display Interfaces cece cece eee eee nmm senem ees 46 E Ae EE 46 3 3 2 Serial Digital Video Output SDVO Signals aseeseen rrenen 46 3 4 PCI Express Signals rate e AR EE EEN FER TRE dE 47 3 5 Intel High Definition AudioP Interface Signals csee e 47 3 6 LPC Interface Signals iier edere beber Ce sese rg ext eres prier usw dE 48 3 7 SMBus Interface SYNES iana iniaa e 48 Intel Atom Processor E6xx Series Datasheet 3 ifte Di 3 8 SPI Interface Signals eerta Rete Ra NEEN SSES REENEN NEES 48 3 9 Power Management Interface Signals sse nene 48 3 10 Real Time Clock Interface Signals oooocoocccccocncncnccononnnnnnnnnn nn nnnnnnn rr rnrnrnrnn nr memes 49 3 11 JTAG and Debug Interface 0c eee nen memes senes 49 3 12 Miscellaneous Signals and Clocks ccc ene eaters 49 3 13 General Purpose 70 iius R
249. es ees 142 180 04h PCICMD PCI Command Register 142 181 O6h PCISTS PCI Status Register 143 182 08h RID Revision Identification Register 143 183 09h CC Class Codes e EE 143 184 OCh CLS Cache Line Size Register sssssssssssss memes mener 144 185 ODh LT Latency Timer Register 144 186 OEh HEADTYP Header Type Register 144 187 10h LBAR Lower Base Address Register 145 188 14h UBAR Upper Base Address Register 145 189 2Ch SVID Subsystem Vendor Identifier emen 145 190 2Eh SID Subsystem Identifier 0 mnes enemies e ener 146 191 34h CAP PTR Capabilities Pointer Register 146 192 3Ch INTLN Interrupt Line Register 146 193 3Dh INTPN Interrupt Pin Register 147 194 40h HDCTL Intel High Definition Audio Control Register oooonoccccccccocononononononoss 147 195 4Ch DCKCTL Docking Control Register 147 196 4Dh DCKSTS Docking Status Register 148 197 50h PM CAPID PCI Power Management Capability ID Register 148 198 52h PM CAP Power Management Capabilities Register 148 199 54h PM CTL STS Power Management Control And Status Register 149 200 60h MSI CAPID MSI Capability ID Register 150 201 62h MSI CTL MSI Message Control Register 150 202 64h MSI ADR MSI Message Address Register 150 203 68h MSI DATA MSI Message Data Register 150 204 70h PCIE CAPID PCI Express Capability Identifiers Register 151 205 72h P
250. es that the I O aliases of the 04 Ob RW V16 VGA range see BCTRL VE definition below are not enabled and only the base I O ranges can be decoded VGA Enable When set the following ranges will be claimed off the backbone by the root port 03 Ob RW VE Memory ranges A0000h BFFFFh e Oranges 3BOh 3BBh and 3COh 3DFh and all aliases of bits 15 10 in any combination of 1s ISA Enable This bit only applies to O addresses that are enabled by the I O Base and I O Limit registers and are in the first 64 kB of PCI I O 02 Ob RW IE space If this bit is set the root port will block any forwarding from the backbone to the device of I O transactions addressing the last 768 bytes in each 1 kB block offsets 100h to 3FFh SERR B Enable When set ERR COR ERR NONFATAL and ERR FATAL 01 Ob RW SE messages received are forwarded to the backbone When cleared they are not 00 Ob RW PERE Parity Error Response Enable When set poisoned write TLPs and completions indicating poisoned TLPs will set the SSTS DPD 8 2 2 Root Port Capability Structure The following registers follow the PCI Express capability list structure as defined in the PCI Express specification to indicate the capabilities of the root interconnect Table 149 Root Port Capability Structure Start End Symbol Register Name 42 43 XCAP PCI Express Capabilities 44 47 DCAP Device Capabilities 48
251. escription 15 12 3h RW IDR inan D Pin Route Indicates which routing is used for INTD B of 11 08 2h RW ICR Interrupt C Pin Route Indicates which routing is used for INTC B of device 3 07 04 1h RW IBR ae B Pin Route Indicates which routing is used for INTB B of 03 00 Oh RW IAR TUE A Pin Route Indicates which routing is used for INTA B of 5 5 4 General Configuration 5 5 4 1 Offset 3400h RC RTC Configuration Table 65 3400h RC RTC Configuration Size 32 bit Default Power Well Memory Mapped IO BAR RCBA Offset 3400h Bit Range Default Access Acronym Description 31 03 0 RO RSVD Reserved 02 0 RWLO RSVD Reserved for future use Upper 128 byte Lock When set bytes 38h 3Fh in the upper 128 byte 01 0 RWLO UL bank of RTC RAM are locked Writes will be dropped and reads will not return any guaranteed data Lower 128 byte Lock When set bytes 38h 3Fh in the lower 128 byte 00 0 RWLO EL bank of RTC RAM are locked Writes will be dropped and reads will not return any guaranteed data 5 5 4 2 Offset 3410h BNT Boot Configuration Table 66 3410h BNT Boot Configuration Size 32 bit Default Power Well Memory Mapped IO BAR RCBA Offset 3410h Bit Range Default Access Acronym Description 31 02 0 RO RSVD Reserved Boot BI OS Strap Status 01 0 RWO UL 1 Boot with the LPC interface 0 Boot from the SPI interface 00 0 RO RSVD Reserved 88 Intel Atom Processor E6xx Series Datasheet 67 n tel Register and Memory Mapp
252. ess Frame hardware initialization sequence will now occur on the dock codecs HDA SDI signals A dock codec is detected when HDA SDI is high on the last HDA CLK cycle of the Frame Sync of a Connect Frame The appropriate bit s in the State Change Status STATESTS register will be set The Turnaround and Address Frame initialization sequence then occurs on the dock codecs HDA SDI s 8 After this hardware initialization sequence is complete approximately 32 frames the controller hardware sets the DCKSTS DM bit to 1 indicating that the dock is now mated ACPI BIOS polls the DCKSTS DM bit and when it detects it is set to 1 conveys this to the OS through a plug N play I RP This eventually invokes the Intel HD AudioP Bus Driver which then begins it s codec discovery enumeration and configuration process Intel HD AudioP Bus Driver software discovers the dock codecs by comparing the bits now set in the STATESTS register with the bits that were set prior to the docking event Intel Atom Processor E6xx Series Datasheet 138 m Intel High Definition Audio D27 FO n tel 9 2 2 9 2 3 Undock Sequence There are two possible undocking scenarios The first is the one that is initiated by the user that invokes software and gracefully shuts down the dock codecs before they are undocked The second is referred to as the surprise undock where the user undocks while the dock codec is running Both of these situations appea
253. essage Data 98 BOh GVD VCID Vendor Capability ID 99 B4h GVD VC Vendor Capabilties sss emen emen 99 C4h GVD FD Functional Disable 0c meses een nnn 99 DOh GVD PMCAP Power Management Capabilities sssesseesne 100 D4h GVD PMCS Power Management Control Status 100 EOh GVD SWSMISCI Software SMI or GC 100 E4h GVD ASLE System Display Event Register 101 F4h GVD LBB Legacy Backlight Brightness mee 101 ECh GVD ASES ASL ASL Storage ii eo dE SERA DEER SASSEL 102 uses PIT 102 Offset 00h ID Identifiers keen e er BREF ER ER NEE ENER ANNE d 103 Offset 04h CMD PCI Commande 103 Offset 06h STS PCI Status iiie eet otra dada 104 Offset 08h RID Revision Identification sssssssss n teens meme 104 Offset 09h CC Class Codes ineo recte Ve eet eid ebat Ree Knie rd Cen pd 104 Intel Atom Processor E6xx Series Datasheet 14 Contents 109 Offset OEh 110 Offset 10h 111 Offset 14h 112 Offset 34h 113 Offset 3Ch 114 Offset 58h 115 Offset 60h 116 Offset 90h 117 Offset 92h 118 Offset 94h 119 Offset 98h 120 Offset C4h 121 Offset EOh 122 Offset E4h 123 Offset FOh 124 Offset F4h 126 PCI Type 1 Bridge Header 127 Offset 00h 128 Offset 02h 129 Offset O4h 130 Offset 06h 131 Offset 08h 132 Offset 09h 133 Offset OCh 134 Offset OEh 135 Offset 18h 136 Offset 19h 137 Offset 1Ah 138 Offset 1Ch 139 Offset 1Dh 140 Offset 1Eh 141 Offset 20h
254. essor E6xx Series Datasheet 240 ACPI Devices intel 11 8 SMBus Controller 11 8 1 Overview The processor provides an SMBus 1 0 compliant host controller The host controller provides a mechanism for the CPU to initiate communications with SMB peripherals slaves 11 8 2 I O Registers Table 358 SMBus Controller Registers Start End Symbol Register Name Function 00 00 HCTL Host Control 01 01 HSTS Host Status 02 03 HCLK Host Clock Divider 04 04 TSA Transmit Slave Address 05 05 HCMD Host Command 06 06 HDO Host Data 0 07 07 HD1 Host Data 1 20 3F HBD Host Block Data 11 8 2 1 Offset 00h HCTL Host Control Register Table 359 00h HCTL Host Control Register Sheet 1 of 2 Size 8 bit Default 00h Power Well Core Access e ES Offset Start 00h PCI Configuration B D F Offset End 00h Bit Range Default Access Acronym Description SMI Enable Enable generation of an SMI upon completion of the 97 eid SE command 06 RO RSVD Reserved Alert Enable Software sets this bit to enable an interrupt SMI due to 05 RW AE SMBALERT Start Stop Initiates the command described in the CMD field This bit 04 RW ST always reads zero HSTS BSY identifies when the processor has finished the command 03 RO RSVD Reserved Intel Atom Processor E6xx Series Datasheet 241 intel ACPI Devices Table 359 00h HCTL Host Control Register Sheet 2 of 2
255. esult of a Master Abort a Parity or ECC error on the bus or any other error which renders the current Buffer Descriptor or Buffer Descriptor List useless This error is treated as a fatal stream error as the stream cannot continue running The RUN bit will be cleared and the stream will stop Software may attempt to restart the stream engine after addressing the cause of the error and writing a 1 to this bit to clear it 04 0 RO RWC FI FO Error This bit is set when a FIFO error occurs This bit is set even if an interrupt is not enabled For an input stream this indicates a FIFO overrun occurring while the 03 0 RO RWC RUN bit is set When this happens the FIFO pointers don t increment and the incoming data is not written into the FIFO thereby being lost For an output stream this indicates a FIFO under run when there are still buffers to send The hardware should not transmit anything on the link for the associated stream if there is not valid data to send Buffer Completion Interrupt Status This bit is set to 1 by the hardware after the last sample of a buffer has been processed AND if the 02 0 RO RWC Interrupt on Completion IOC bit is set in the command byte of the buffer descriptor It remains active until software clears it by writing a 1 to this bit position 01 00 0 RW RO Reserved Intel Atom Processor E6xx Series Datasheet 176 Intel High Definition Audio D27 FO intel
256. et 40h HDCTL Intel High Definition Audio Control Register Table 194 40h HDCTL Intel High Definition Audio Control Register Size 8 bit Default 00h Power Well Core Access D F 0 27 Offset Start 40h PCI Configuration B D F 0 27 0 Offset End 40h Bit Range Default Access Acronym Description 07 01 0 RO RSVD Reserved Low Voltage Mode Enable LVM is not supported 0 The Intel HD Audio controller operates in high voltage mode 1 The Intel HD Audio controller s AFE operates in low voltage mode 00 0 RO LMVE 9 3 1 18 Offset 4Ch DCKCTL Docking Control Register Table 195 4Ch DCKCTL Docking Control Register Size 8 bit Default 00h Power Well Core Access D F 0 27 Offset Start 4Ch PCI Configuration B D F 0 27 0 Offset End 4Ch Bit Range Default Access Acronym Description 07 01 0 RO RSVD Reserved Dock Attach Software writes a 1 to this bit to initiate the docking sequence on the HDA DOCK EN B and HDA DOCKRST B signals When the docking sequence is complete hardware will set the Dock Mated DCKSTS DM status bit to 1 Software writes a 0 to this bit to initiate the undocking sequence on the HDA DOCK EN B and HDA DOCKRST B signals When the undocking sequence is complete hardware will set the Dock Mated DCKSTS DM 00 0 RW RO DA status bit to 0 Note that software must check the state of the Dock Mated DCKSTS DM bit prior to wri
257. et 4D1h ELCR2 Slave Edge Level Control Table 323 4D1h ELCR2 Slave Edge Level Control Size 8 bit Default Power Well Core Access Offset Start 4D1h PCI Configuration B D F Offset End Bit Range Default Access Acronym Description Edge Level Control n edge mode bit cleared the interrupt is gt recognized by a low to high transition In level mode bit set the 07 06 0 RW ECL 15 14 interrupt is recognized by a high level Bit 7 applies to 1RQ15 and bit 6 to IRQ14 05 0 RO RSVD Reserved The FERR IRQ13 cannot be programmed for level mode Edge Level Control In edge mode bit cleared the interrupt is e recognized by a low to high transition In level mode bit set the 04 01 0 RW ECL 12 9 interrupt is recognized by a high level Bit 4 applies to IRQ12 bit 3 to IRQ11 bit 2 to IRQ10 and bit 1 to IRQ9 00 0 RO RSVD Mie dus The Real Time Clock 1RQ8 cannot be programmed for level 11 3 3 I nterrupt Handling 11 3 3 1 Generating The 8259 interrupt sequence involves three bits from the IRR ISR and IMR for each interrupt level These bits are used to determine the interrupt vector returned and status of any other pending interrupts These bits are defined as follows Interrupt Request Register IRR Set on a low to high transition of the interrupt line in edge mode and by an active high level in level mode Interrupt Service Register ISR Set
258. et 68h SCNT Serial IRQ Control 196 292 Offset 84h WDTBA WDT Base Address 196 293 Offset DOh FS FWH ID Select 196 294 Offset D4h BDE BIOS Decode Enable mmm nennen 197 295 Offset D8h BC BIOS Control cuina ex hk ERRARE RR RAT ERAN ERE TEREEME per AE 198 296 Offset FOh RCBA Root Complex Base Address 199 297 Timer I O Registers corretta tr EENS dE EE EE Pe APER IA 201 298 43h TCW Timer Control Word Register 202 299 43h RBC Read Back Commande 203 300 43h CLC Counter Latch Commande 203 301 40h 41h 42h Interval Timer Status Byte Format Register 204 302 40h 41h 42h Counter Access Ports Register 204 3039 HPET Register Smeren arg Aena haa Aa EEE EE EA AEN AEEA ENS 206 304 000h GCID General Capabilities and ID 207 305 010h GC General Configuration 0 2 0 0 eee eene eene 207 306 020h GIS General Interrupt Status 0 0 enemies 208 307 OFOh MCV Main Counter Value mmm seems e memem sie enn 208 308 100h 120h 140h T 0 2 C Timer 0 2 Config and Capabilities sssssssss 208 309 108h 128h 148h T 0 2 CV Timer 0 2 Comparator Value 210 310 Timer Interrupt Mapping Legacy Option 211 311 Master 8259 Input Mapping 0 ccc HH mme mememe se ne enis e ess nn nnn 212 312 Slave 8259 Input Mapping ririri sinsi nenii ankai EENAA NEEE REEE EEREN 212 313 8259 1 0 Register Mapping icono eme ts ete ee eters reb ecce ROLE rie de V PR od id 213 314 20h AOh ICW1 Initialization
259. et by the OS these bits correspond to address signals 02 01 00 RO RSVD Reserved 00 1 RO RTE Resource Type Indicates a request for I O space 7 7 2 9 Offset 2Ch SS Subsystem Identifiers This register matches the value written to the LPC bridge 7 7 2 10 Offset 34h CAP PTR Capabilities Pointer Table 112 Offset 34h CAP PTR Capabilities Pointer Size 8 bit Default DOh Power Well Core Access 1 D F 0 3 Offset Start 34h PCI Configuration B D F 0 3 0 Offset End 34h Bit Range Default Access Acronym Description 07 00 DOh RO PTR Pointer The first item in the capabilities list is at address DOh 7 7 2 11 Offset 3Ch INTR Interrupt I nformation Table 113 Offset 3Ch INTR Interrupt I nformation Size 16 bit Default xx00h Power Well Core Access D E 0 3 Offset Start 3Ch PCI Configuration B D F 0 3 0 Offset End 3Dh Bit Range Default Access Acronym Description Interrupt Pin This value reflects the value of DO21 P GP in the LPC 15 08 Variable RO IPIN configuration space Interrupt Line Software written value to indicate which interrupt line 07 00 00h RW ILIN vector the interrupt is connected to No hardware action is taken on this bit Intel Atom Processor E6xx Series Datasheet 106 Graphics Video and Display 7 7 2 12 Offset 58h SSRW
260. f the service routine uses the poll command Polled Mode can also be used to expand the number of interrupts The polling interrupt service routine can call the appropriate service routine instead of providing the interrupt vectors in the vector table In this mode the INTR output is not used and the microprocessor internal Interrupt Enable flip flop is reset disabling its interrupt input Service to devices is achieved by software using a Poll Command The Poll command is issued by setting P 1 in OCW3 The 8259 treats its next I O read as an interrupt acknowledge sets the appropriate ISR bit if there is a request and reads the priority level Interrupts are frozen from the OCW3 write to the I O read The byte returned during the I O read will contain a 1 in bit 7 if there is an interrupt and the binary code of the highest priority level in bits 2 0 Intel Atom Processor E6xx Series Datasheet 221 intel Series 11 3 6 6 11 3 7 11 3 7 1 11 3 7 2 11 3 8 11 3 8 1 11 3 8 2 Edge and Level Triggered Mode In ISA systems this mode is programmed using bit 3 in CW1 which sets level or edge for the entire controller In the processor this bit is disabled and a new register for edge and level triggered mode selection per interrupt input is included This is the Edge Level control Registers ELCR1 and ELCR2 If an ELCR bit is 0 an interrupt request will be recognized by a low to high transition on the correspo
261. fer These buffers can be configured as Stub Series Termination Logic SSTL1 8 CMOS3 3 CMOS3 3 OD 3 3 V CMOS buffer or CMOS 3 3 V open drain CMOS3 3 5 3 3 V CMOS buffer 5 V tolerant PCI e PCI Express interface signals These signals are compatible with PCI Express Base Specification Rev 1 0a Signaling Environment AC Specifications and are AC coupled The buffers are not 3 3 V tolerant SDVO Serial DVO differential buffers These signals are AC coupled These buffers are not 3 3 V tolerant LVDS Low Voltage Differential Signal output buffers These pure outputs should drive across a 100 resistor at the receiver when driving A Analog reference or output maybe used as a threshold voltage or for buffer compensation Intel Atom Processor E6xx Series Datasheet 31 m e n tel Signal Description 2 1 System Memory Signals Table 4 System Memory Signals Signal Direction Type Power Well Description O On Die Termination Enable active high One pin per M_ODT 1 0 CMOS1 8 Core rank 2 ranks supported o Differential DDR Clock The crossing of the positive edge M CKP CMOS1 8 Core of M CKP and the negative edge of M CKN is used to sample the address and control signals on memory M_CKN eee 8 Core Complementary Differential DDR Clock O Clock Enable active high M_CKE is used for power M_CKE 1 0 CMOS1 8 SUS contr
262. ffset End 1Dh Bit Range Default Access Acronym Description Ud o Address Limit I O pace bits corresponding to address lines 15 12 or 4 kB alignment Bits 11 0 are assumed to be padded to FFFh 97594 oh BW die Devices between this upper limit and IOBASE will be passed to the PCI Express hierarchy associated with this device Z 1 O Limit Address Capability Indicates that the bridge does not 03 00 Oh RO 1OLC support 32 bit I O addressing 8 2 1 14 SSTS Secondary Status SSTS is a 16 bit status register that reports the occurrence of error conditions associated with secondary side of the virtual PCI to PCI bridge embedded within the processor Table 140 Offset 1Eh SSTS Secondary Status Sheet 1 of 2 Size 16 bit Default 0000h Power Well Core Access a i PUN Offset Start 1Eh PCI Configuration B D F 0 23 26 0 Offset End 1Fh Bit Range Default Access Acronym Description Detected Parity Error This bit is set by the Secondary Side for a Type 15 Ob RWC DPE 1 Configuration Space header device whenever it receives a Poisoned TLP regardless of the state of the Parity Error Response Enable bit in the Bridge Control Register Received System Error This bit is set when the Secondary Side for a 14 Ob RWC RSE Type 1 configuration space header device receives an ERR FATAL or ERR NONFATAL Received Master Abort This bit is set when the Secondary Side for 13 Ob RWC RMA Type 1 Configuration Space Header Device for requests initiated by the Type
263. ffset OEh STATESTS State Change Status Table 233 OEh STATESTS State Change Status Size 16 bit Default 0000h Power Well Core Access sce nos Offset Start OEh PCI Configuration B D F 0 27 0 Offset End OFh Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 15 02 0 RO RSVD Reserved SDIN State Change Status Flags Flag bits that indicate which SDI signal s received a State Change event The bits are cleared by writing a 1 to them Bit O is for SDIO 01 00 0 RWC SDIWAKE Bit 1 is for SDI1 Bit 2 is for SDI2 These bits are in the suspend well and only cleared on a power on reset Software must not make assumptions about the reset state of these bits and must set them appropriately 9 3 2 1 9 Offset 10h GSTS Global Status Table 234 10h GSTS Global Status Size 16 bit Default 0000h Power Well Core Access PCI Configuration B D F 0 27 0 Offset Start 10h Offset End 11h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 15 04 0 RO RSVD Reserved 03 0 RWC DMIS Dock Mated Interrupt Status A 1 indicates that the dock mating or unmating process has completed For the docking process it indicates that dock is electrically isolated and that software may report to the user that physical undocking may commence This bit gets set to a 1 by hardware w
264. flected in the PCICMDSTS IS bit When 1 permits sending of a MSI interrupt and blocks the sending of a Message bus interrupt The interrupt status is not blocked from being reflected in the PCICMDSTS IS bit POINTER TO N 15 8 00h RO EXT CAPABILI T Indicates this is the last item in the list Y 7 0 05h RO CAPABILITY ID CAPID Indicates an MSI capability Table 92 94h GVD MA Message Address Size 32 bit Default 00000000h Power Well Core Access e TS Offset Start 94h PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 25h Bit Range Default Access Acronym Description 000000 MA Lower 32 bits of the system specified message address always DW 31 2 RW ADDRESS aligned When the GVD issues an MSI interrupt as a MEMWR on the SCL 00h es the memory address corresponds to the value of this field 1 0 00b RO RESERVED Reserved Table 93 98h GVD MD Message Data Size 32 bit Default 00000000h Power Well Core Access e m Offset Start 98h PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 26h Bit Range Default Access Acronym Description 31 16 0000h RO RESERVED Reserved MD This 16 bit field is programmed by system software and is driven 15 0 0000h RW DATA onto the lower word of data during the data phase of the MSI write transaction When the GVD issues an MSI interrupt as a MEMWR on the SCL the write data corresponds to the value of this field Intel Atom Proces
265. format and data can be represented in BCD or binary format The design is meant to be functionally compatible with the Motorola MS146818B The time keeping comes from a 32 768 kHz oscillating source which is divided to achieve an update every second The lower 14 bytes on the lower RAM block have very specific functions The first ten are for time and date information The next four OAh to ODh are registers which configure and report RTC functions A host initiated write takes precedence over a hardware update in the event of a collision I O Registers The RTC internal registers and RAM are organized as two banks of 128 bytes each called the standard and extended banks The first 14 bytes of the standard bank contain the RTC time and date information along with four registers A D that are used for configuration of the RTC The extended bank contains a full 128 bytes of battery backed SRAM All data movement between the host CPU and the RTC is done through registers mapped to the standard I O space The register map appears below RTC Registers I O Locations If U128E bit 0 Function 70h and 74h Also alias to 72h and 76h Real Time Clock Standard RAM Index Register 71h and 75h Also alias to 73h and 77h Real Time Clock Standard RAM Target Register 72h and 76h Extended RAM Index Register if enabled 73h and 77h Extended RAM Target Register if enabled Notes L 1 O locations 70h and 71h are th
266. formation I C is a two wire communications bus protocol developed by Philips SMBus is a subset of the 12C bus protocol and was developed by Intel Implementations of the 12C bus protocol may require licenses from various entities including Philips Electronics N V and North American Philips Corporation BunnyPeople Celeron Celeron Inside Centrino Centrino Inside Core Inside i960 Intel the Intel logo Intel AppUp Intel Atom Intel Atom Inside Intel Core Intel Inside the Intel Inside logo Intel NetBurst Intel NetMerge Intel NetStructure Intel SingleDriver Intel SpeedStep Intel Sponsors of Tomorrow the Intel Sponsors of Tomorrow logo Intel StrataFlash Intel Viiv Intel vPro Intel XScale InTru the InTru logo InTru soundmark Itanium Itanium Inside MCS MMX Moblin Pentium Pentium Inside skoool the skoool logo Sound Mark The Journey Inside vPro Inside VTune Xeon and Xeon Inside are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2013 Intel Corporation All rights reserved Intel Atom Processor E6xx Series Datasheet 2 Contents i n tel Contents 1 0 Introduction gange dee came tud EE eege 23 UNK ge ln ee VE 24 1 2 Reference Documents ccc e memes messe eese ene meme seen e sena 25 1 3 Components OVervlieW oiii cere a Eed EE EEN Renae dee 26 1 3 1 Low Power Intel Architecture Core
267. g Running Running RTCX2 I Running Running Running Running J TAG and Debug Interface The J TAG interface is accessible only after PWROK is asserted J TAG and Debug I nterface Signals Signal Name Direction Reset Post Reset S3 S4 S5 TCK l VIL VIL off off TDI l VIH VIH off off TDO O High Z High Z Off Off TMS l VIH VIH off off TRST_B l VIX known VIH off off IO TDI l VIL VIL off off 10_TDO O High Z High Z Off Off IO TMS l VIL VIL off off IO TCK I VIL VIL Off Off 10_TRST_B I VIH VIH Off Off Miscellaneous Signals and Clocks Miscellaneous Signals and Clocks Signal Name Direction Reset Post Reset S3 S4 S5 Thermal CLK14 l Running Running Off Off SPKR O VOL VOL Off Off SMI_B l VI X unknown VIX unknown Off Off THRM B l VIX unknown VIX unknown off off CRU PLL HPLL_REFCLK_P HPLL REFCLK N I Running Running Off Off Intel Atom Processor E6xx Series Datasheet 49 intel 3 13 Table 32 3 14 Table 33 Pin States General Purpose I O General Purpose I O Signals Signal Name Direction Reset Post Reset S3 S4 S5 GPIOSUS 8 0 1 0 High Z High Z Unknown Off GPIO 4 0 1 0 High Z High Z Off Off Integrated Termination Resistors Integrated Termination Resistors Signal Resistor Type s Value Tolerance PCIE PETP 3 0 pull down 50 2096 PCIE PETN 3 0 pull down 50 2096 PCIE PERP 3 0 pull down 50
268. g or the DMA transfer may be corrupted This same address is used by the Flush Control and must be programmed with a valid value before the FLCNRTL bit LBAR 08h bit 1 is set 06 01 0 RO RSVD Reserved DMA Position Buffer Enable When this bit is set to a 1 the controller 00 0 RW will write the DMA positions of each of the DMA engines to the buffer in main memory periodically typically once frame Software can use this value to know what data in memory is valid data Intel Atom Processor E6xx Series Datasheet 174 Intel High Definition Audio D27 FO intel 9 3 2 1 32 Offset 80h AOh COh EOh I SDOCTL ISD1CTL OSDOCTL OSDI1CTL I nput Output Stream Descriptor 0 1 Control Register Table 257 80h AOh COh EOh ISDOCTL ISD1CTL OSDOCTL OSDICTL Input Output Stream Descriptor 0 1 Control Register Sheet 1 of 2 Size 24 bit Default 04_0000h Power Well Core Access VENUES yy Offset Start 80h AOh COh EOh PCI Configuration B D F 0 27 0 Offset End 82h A2h C2h E2h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description Stream Number This value reflects the Tag associated with the data being transferred on the link When data controlled by this descriptor is sent out over the link it will have this stream number encoded on the HDA SYNC signal When an input stream is detected on any of the HDA SDI x signals that match this
269. g periods it may provide additional such as sync information auxiliary configuration data etc This data pair must be sampled with respect to the SDVO_CLK signal pair SDVO_BLUEP o SDVO_BLUEN PCle Core Serial Digital Video Blue SDVO_BLUE is a differential data pair that provides blue pixel data for the SDVO channel during Active periods During blanking periods it may provide additional such as sync information auxiliary configuration data etc This data pair must be sampled with respect to the SDVO_CLK signal pair SDVO_CLKP o SDVO_CLKN PCle Core Serial Digital Video Clock This differential clock signal pair is generated by the internal PLL and runs between 100 MHz and 200 MHz If TV out mode is used the SDVO_TVCLKIN clock input is used as the frequency reference for the PLL The SDVO_CLK output pair is then driven back to the SDVO device SDVO INTP SDVO INTN PCle Core Serial Digital Video nput I nterrupt Differential input pair that may be used as an interrupt notification from the SDVO device This signal pair can be used to monitor hot plug attach detach notifications for a monitor driven by an SDVO device SDVO TVCLKI NP SDVO TVCLKI NN PCle Core Serial Digital Video TV OUT Synchronization Clock Differential clock pair that is driven by the SDVO device If SDVO_TVCLKIN is used it becomes the frequency reference for the dot clock PLL but will be driven back to the
270. gnals HDA_SDI 1 0 one dedicated to each of the supported codecs Audio software renders outbound and processes inbound data to from buffers in system memory The location of the individual buffers is described by a Buffer Descriptor List BDL that is fetched and processed by the controller The data in the buffers is arranged in a pre defined format The output DMA engines fetch the digital data from memory and reformat it based on the programmed sample rate bits sample and number of channels The data from the output DMA engines is then combined and serially sent to the external codec s over the Intel HD Audio link The Input DMA engines receive data from the codec s over the Intel HD Audio link and format the data based on the programmable attributes for that stream The data is then written to memory in the pre defined format for software to process Each DMA engine moves one stream of data A single codec can accept or generate multiple streams of data one for each A D or D A converter in the codec Multiple codecs can accept the same output stream processed by a single DMA engine Codec commands and responses are also transported to and from the codec via DMA engines The DMA engine dedicated to transporting commands from the Command Output Ring Buffer CORB in memory to the codec s is called the CORB engine The DMA engine dedicated to transporting responses from the codec s to the Response Input Ring Buffer in
271. gs n tel 12 0 Absolute Maximum Ratings Table 401 specifies absolute maximum and minimum ratings Within functional operation limits functionality and long term reliability can be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Intel Atom Processor E6xx Series Datasheet 273 intel 12 1 Table 401 Absolute Maximum Rating Absolute Maximum Ratings Absolute Maximum Ratings
272. h 03BBh and 03COh 03DFh As well the GVD will check scldown3_address 15 3 with GFX IOBAR 15 3 If there 0 Ob RW IO SPACE ENA is a match with VGA IO address range or GFX IOBAR and if the SCL BLE command is either an IORD or IOWR the GVD will select the command i e issue a scldown3 hit Care should be taken in setting up GFX IOBAR that more than 1 match is not made as this will result in unpredictable behavior When 0 the GVD will not select a IORD or IOWR SCL command Table 79 08h GVD RI DCC Revision Identification and Class Code Size 32 bit Default Power Well Core Access e RAE a Offset Start 08h PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 02h Bit Range Default Access Acronym Description 31 24 03h RO BASE GASSO BCC Indicates a display controller 23 16 00h RO SUB CLASS C When MGGC 1 VD Ob default this value is 00h When MGGC 1 5 ODE VD 0b or when MGGC 6 4 GMS 000b this value is 80h 15 8 00h RO ERACE PI Indicates a display controller a to Revision Identification Number This is an 8 bit value that indicates 7 0 descript RO REVISION D the revision identification number for the device For the B 0 Stepping ion H this value is 03h For B 1 Stepping this value is 05h Table 80 OCh GVD HDR Header Type Size 32 bit Default 00000000h Power Well Core Access D F0 2 Offset Start PCI Configuration B D F 0 2 0 Offset End OCh Message Bus Port 06h Register Addres
273. h Power Well Core Access AIEO 3 Offset Start 68h PCI Configuration B D F 0 27 0 Offset End 69h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 00 0 RW ICB Immediate Command Busy When this bit as read as a 0 it indicates that a new command may be issued using the Immediate Command mechanism When this bit transitions from a O to a 1 via software writing a 1 the controller issues the command currently stored in the Immediate Command register to the codec over the link When the corresponding response is latched into the Immediate Response register the controller hardware sets the IRV flag and clears the ICB bit back to 0 Note that an Immediate Command must not be issued while the CORB RIRB mechanism is operating otherwise the responses conflict This must be enforced by software 9 3 2 1 31 Offset 70h DPBASE DMA Position Base Address Register Table 256 70h DPBASE DMA Position Base Address Register Size 32 bit Default 0000 0000h Power Well Core Access PCI Configuration B D F 0 27 0 Offset Start 70h Offset End 73h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description DMA Position Base Address This field is the 32 bits of the DMA Position Buffer Base Address This register field must not be written when 31 07 0 RW DPBASE any DMA engine is runnin
274. h at 4h Offset 10h 18h 20h 28h 30h 38h 40h SPI 0 6 SPI Data 0 6 00000000h 3070h 3073h Offset 50h BBAR BIOS Base Address 00000000h 3074h 3075h Offset 54h PREOP Prefix Opcode Configuration 0004h 3076h 3077h Offset 56h OPTYPE Op Code Type 0000h 3078h 307Fh Offset 58h OPMENU OPCODE Menu Configuration 00000005h 3080h at 4h 3083h at 4h Offset 60h PBRO Protected BIOS Range 0 00000000h 11 9 5 2 Offset 00h SPIS SPI Status Table 373 00h SPIS SPI Status Size 16 bit Default 0001h Power Well Core Access e i MEN Offset Start 3020h PCI Configuration B D F 0 31 0 Offset End 3021h Memory Mapped IO BAR RCBA Offset Bit Range Default Access Acronym Description SPI Configuration Lock Down When set to 1 the SPI Static 15 0 RWL SCL Configuration information in offsets 50h through 6Bh can not be overwritten Once set to 1 this bit can only be cleared by a hardware reset 14 4 0 RV RSVD Reserved Blocked Access Status Hardware sets this bit to 1 when an access is blocked from running on the SPI interface due to one of the protection 3 0 RWC BAS policies or when any of the programmed cycle registers are written while a programmed access is already in progress This bit is set for both programmed accesses and direct memory reads that get blocked This bit remains asserted until cleared by software writing a 1 or hardware reset Cycle Done Status The processor sets this
275. he processor does provides LVDS backlight control related signal in order to support LVDS panel backlight adjustment Serial DVO SDVO Display I nterface Digital display channel capable of driving SDVO adapters that provide interfaces to a variety of external display technologies e g DVI TV Out analog CRT Maximum resolution up to 1280x1024 85 Hz Maximum pixel clock rate up to 160 MHz SDVO lane reversal is not supported PCI Express The Intel Atom Processor E6xx Series has four x1 lane PCI Express PCle root ports supporting the PCI Express Base Specification Rev 1 0a The processor does not support the ganging of PCle ports The four x1 PCle ports operate as four independent PCle controllers Each root port supports up to 2 5 Gb s bandwidth in each direction per lane The PCle ports may be used to attach discrete I O components or a custom I O Hub for increased I O expansion LPC Interface The Intel Atom Processor E6xx Series implements an LPC interface as described in the LPC1 1 Specification The LPC interface has three PCI based clock outputs that may be provided to different O devices such as legacy I O chip The LPC_CLKOUT signals support a total of six loads two loads per clock pair with no external buffering Intel Atom Processor E6xx Series Datasheet 28 Introduction 1 3 9 1 3 10 1 3 11 1 3 12 1 3 13 intel Intel High Definition Audio Intel HD Audio
276. hen the DM bit transitions from a 0 to a 1 docking or from a mo a0 undocking Note that this bit is set regardless of the state of the DMIE bit Software clears this bit by writing a 1 to it Writing a O to this bit has no affect 02 0 RO DM Dock Mated This bit effectively communicates to software that an Intel HD Audio docked codec is physically and electrically attached Controller hardware sets this bit to 1 after the docking sequence triggered by writing a 1 to the Dock Attach GCTL DA bit is completed HDA_DOCKRST_B deassertion This bit indicates to software that the docked codec s may be discovered via the STATESTS register and then enumerated Controller hardware sets this bit to 0 after the undocking sequence triggered by writing a O to the Dock Attach GCTL DA bit is completed HDA DOCK EN B deasserted This bit indicates to software that the docked codec s may be physically undocked This bit is Read Only Writes to this bit have no effect 01 0 RWC FSTS Flush Status This bit is set to a 1 by the hardware to indicate that the flush cycle initiated when the FCNTRL bit LBAR 08h bit 1 was set has completed Software must write a 1 to clear this bit before the next time FCNTRL is set 00 0 RO RSVD Reserved Intel Atom Processor E6xx Series Datasheet 164 Intel High Definition Audio D27 FO 9 3 2 1 10 Offset 14h ECAP Extended Capabilities
277. here will be unpredictable results if the configuration software allows conflicts to occur The Intel Atom Processor E6xx Series does not check for conflicts Variable I O Range Decoded by the Processor Range Name Mappable Size bytes Target ACPI P BLK Anywhere in 64k I O space 16 Power Management SMBus Anywhere in 64k I O space 32 SMB Unit GPIO Anywhere in 64k I O space 64 GPIO PCI Devices and Functions The Intel Atom Processor E6xx Series incorporates a variety of PCI devices and functions as shown in Table 39 PCI Devices and Functions Sheet 1 of 2 Bus Device Function Functional Description Bus 0 Device 0 Function 0 Host Bridge Bus 0 Device 2 Function 0 Integrated Graphics and Video Device Bus 0 Device 3 Function 0 SDVO Display Unit Bus 0 Device 23 Function 0 PCI Express Port 0 Bus 0 Device 24 Function 0 PCI Express Port 1 Intel Atom Processor E6xx Series Datasheet 57 m e n tel Register and Memory Mapping Table 39 PCI Devices and Functions Sheet 2 of 2 Bus Device Function Functional Description Bus 0 Device 25 Function 0 PCI Express Port 2 Bus 0 Device 26 Function 0 PCI Express Port 3 Bus 0 Device 27 Function 0 Intel High Definition Audio Controller Bus 0 Device 31 Function 0 LPC Interface Figure 4 PCI Devices Intel Atom Processor E6xx Series PCI Bus 0
278. hich the following occurs The Interrupt Mask register is cleared IRQ7 input is assigned priority 7 The slave mode address is set to 7 Special Mask Mode is cleared and Status Read is set to IRR Once this write occurs the controller expects writes to ICW2 ICW3 and I CW4 to complete the initialization sequence 20h AOh ICW1 Initialization Command Word 1 Sheet 1 of 2 Size 8 bit Default Power Well Core Access Offset Start 20h AOh PCI Configuration B D F Offset End Bit Range Default Access Acronym Description 07 05 Undef WO to 000 These bits are MCS 85 specific and not needed Should be programmed 04 Undef WO I CW OCW select This bit must be a 1 to select ICW1 and enable the 1CW2 ICW3 and ICW4 sequence Intel Atom Processor E6xx Series Datasheet 213 intel ACPI Devices Table 314 20h AOh ICW1 Initialization Command Word 1 Sheet 2 of 2 Size 8 bit Default Power Well Core Access e S Offset Start 20h AOh PCI Configuration B D F Offset End Bit Range Default Access Acronym Description 03 Undef WO LTIM Edge Level Bank Select Disabled Replaced by ELCR1 and ELCR2 02 Undef WO Reserved set to 0 Single or Cascade Must be programmed to a 0 to indicate two 01 Undef wo SNGL controllers operating in cascade mode wl CW4 Write Required This
279. hod is to perform a simple read operation The counter is selected through port 40h counter 0 41h counter 1 or 42h counter 2 Note performing a direct read from the counter will not return a determinate value because the counting process is asynchronous to read operations However in the case of counter 2 the count can be stopped by writing to NSC TC2E Counter Latch Command The Counter Latch Command written to port 43h latches the count of a specific counter at the time the command is received This command is used to ensure that the count read from the counter is accurate particularly when reading a two byte count The count value is then read from each counter s Count Register as was programmed by the Control Register Intel Atom Processor E6xx Series Datasheet 205 intel Stee 11 1 7 3 11 2 11 2 1 Table 303 The count is held in the latch until it is read or the counter is reprogrammed The count is then unlatched This allows reading the contents of the counters on the fly without affecting counting in progress Multiple Counter Latch Commands may be used to latch more than one counter Counter Latch Commands do not affect the programmed mode of the counter in any way If a Counter is latched and then some time later latched again before the count is read the second Counter Latch Command is ignored The count read will be the count at the time the first Counter Latch Command was issued Read Back Com
280. ic Rotation Mode Equal Priority Devices In some applications there are a number of interrupting devices of equal priority Automatic rotation mode provides for a sequential 8 way rotation In this mode a device receives the lowest priority after being serviced In the worst case a device requesting an interrupt will have to wait until each of seven other devices are serviced at most once There are two ways to accomplish automatic rotation using OCW2 the Rotation on Non Specific EOI Command R 1 SL 0 EOI 21 and the Rotate in Automatic EOI Mode which is set by R21 SL 0 EOI 20 Specific Rotation Mode Specific Priority Software can change interrupt priorities by programming the bottom priority For example if IRQ5 is programmed as the bottom priority device then IRQ6 will be the highest priority device The Set Priority Command is issued in OCW2 to accomplish this where R 1 SL 1 and LO L2 is the binary priority level code of the bottom priority device In this mode internal status is updated by software control during OCW2 However it is independent of the EOI command Priority changes can be executed during an EOI command by using the Rotate on Specific EOI Command in OCW2 R 1 SL 1 EOI 1 and LO L2 IRQ level to receive bottom priority Poll Mode Poll Mode can be used to conserve space in the interrupt vector table Multiple interrupts that can be serviced by one interrupt service routine do not need separate vectors i
281. ic to PCI to PCI bridges The BCTRL provides additional control for the secondary interface as well as some bits that effect the overall behavior of the virtual Host PCI Express bridge embedded within the processor for example VGA compatible address ranges mapping Table 148 Offset 3bEh BCTRL Bridge Control Sheet 1 of 2 Size 16 bit Default 0000h Power Well Core Access e e Offset Start 3Eh PCI Configuration B D F 0 23 26 0 Offset End 3Fh Bit Range Default Access Acronym Description 15 12 Oh RO RSVD Reserved 11 Ob RO DTSE Discard Timer SERR_B Enable Reserved per PCI Express spec 10 Ob RO DTS Discard Timer Status Reserved per PCI Express spec 09 Ob RO SDT Secondary Discard Timer Reserved per PCI Express spec 08 Ob RO PDT Primary Discard Timer Reserved per PCI Express spec 07 Ob RO FBE Fast Back to Back Enable Reserved per PCI Express spec 06 Ob RW SBR rer ien Bus Reset This triggers a Hot Reset on the PCI Express Intel Atom Processor E6xx Series Datasheet 121 m e n tel PCI Express Table 148 Offset 3Eh BCTRL Bridge Control Sheet 2 of 2 Size 16 bit Default 0000h Power Well Core Access e Offset Start 3Eh PCI Configuration B D F 0 23 26 0 Offset End 3Fh Bit Range Default Access Acronym Description 05 Ob RO MAM Master Abort Mode Reserved per PCI Express spec VGA 16 Bit Decode When set this indicat
282. ically and electrically attached Controller hardware sets this bit to 1 after the docking sequence triggered by writing a 1 to the Dock Attach DCKCTL DA bit is completed HDA_DOCKRST_B deassertion This bit indicates to software that the docked codec s may be discovered via the STATESTS register and then enumerated 00 0 RO DM Controller hardware sets this bit to 0 after the undocking sequence triggered by writing a 0 to the Dock Attach DCKCTL DA bit is completed HDA_DOCK_EN_B deasserted This bit indicates to software that the docked codec s may be physically undocked Note that this bit is reset on RST_B It is not directly reset on CRST_B however because the dock state machine is reset on CRST_B and the dock will be electrically isolated this DM bit will be read as 0 reflecting the undocked state This bit is Read Only Writes to this bit have no effect 9 3 1 20 Offset 50h PM_CAPID PCI Power Management Capability I D Register Table 197 50h PM CAPID PCI Power Management Capability I D Register Size 16 bit Default 7001h Power Well Core Access D F 0 27 Offset Start 50h PCI Configuration B D F 0 27 0 Offset End 51h Bit Range Default Access Acronym Description 15 08 70h RO NEXT Next Capability Points to the next capability structure PCI Express 07 00 01h RO CAP Cap ID Indicates that this pointer is a PCI power management capability 9 3 1 21 Offset 52h PM_CAP Power Management Capabilities Register Table 198
283. ice 23 Interrupt Route Size 16 bit Default Power Well Memory Mapped IO BAR RCBA Offset 3150h Bit Range Default Access Acronym Description 15 12 3h RW IDR Interrupt D Pin Route Indicates which routing is used for INTD_B of 11 08 2h RW ICR peer C Pin Route Indicates which routing is used for INTC B of 07 04 1h RW IBR Interrupt B Pin Route Indicates which routing is used for INTB_B of 03 00 Oh RW IAR Interrupt A Pin Route Indicates which routing is used for INTA B of 5 5 3 7 Offset 3160h DO2IR Device 2 Interrupt Route Table 63 3160h DO2IR Device 2 Interrupt Route Size 16 bit Default Power Well Memory Mapped IO BAR RCBA Offset 3160h Bit Range Default Access Acronym Description 15 12 3h RW IDR Interrapt D Pin Route Indicates which routing is used for INTD_B of 11 08 2h RW ICR derbi C Pin Route Indicates which routing is used for INTC_B of 07 04 1h RW IBR Interrupt B Pin Route Indicates which routing is used for INTB_B of 03 00 Oh RW IAR Interrupt A Pin Route Indicates which routing is used for INTA_B of Intel Atom Processor E6xx Series Datasheet 66 Register and Memory Mapping 5 5 3 8 Offset 3162h DO3IR Device 3 Interrupt Route Table 64 3162h DO3IR Device 3 Interrupt Route Size 16 bit Default Power Well Memory Mapped IO BAR RCBA Offset 3162h Bit Range Default Access Acronym D
284. ifted first while bit O is shifted last However for data bursts bytes are shifted out from least significant byte to most significant byte where each byte is shifted MSB to LSB Addressing A Slave is targeted for a cycle when it s SPI CS pin is asserted Besides Slave addressing there is register addressing within the Slave itself The list of processor supported devices includes only FLASH devices See supported devices data sheets for more information Data Transaction All transactions on the SPI bus must be a multiple of 8 bits A frame consists of any number of 8 bit data packets To initiate a data transfer the SPI Master asserts high to low transition the SPI_CS signal informing the SPI Slave that it is being targeted for a cycle The Master will then shift out the 8 bit opcode followed by the Slave s internal address In the case of a Read transaction the Slave will interpret the Slave address and begin driving data out on the SPI MISO pin and ignore any transactions on the SPI MOSI pin The Master indicates Read complete by deasserting the SPI CS signal on an 8 bit boundary In the case of a Write transaction the Slave will continue to receive Master data on the SPI MOSI pin The Write transaction is completed upon deassertion of the SPI CS x signal on an 8 bit boundary The SPI bus does include a mechanism for flow control however some devices include the support of a HOLD signal See Slave documentation for more infor
285. ing Intel Atom Processor E6xx Series Datasheet 68 m Memory Controller 6 0 Memory Controller 6 1 Overview ntel The Intel Atom Processor E6xx Series contains an integrated 32 bit single channel memory controller that supports DDR2 memory in soldered down DRAM configurations only The memory controller supports data rates of 800 MT s There is no support for ECC in the memory controller 6 1 1 DRAM Frequencies and Data Rates The memory controller supports the clock frequencies and data rates for DRAM listed in Table 67 Table 67 Memory Controller Supported Frequencies and Data Rates Memory Clock DRAM Clock DRAM Data Rate DRAM Type Peak Bandwidth 200 MHz 400 MHz 800 MT s DDR2 6 2 DRAM Burst Length The memory controller only supports a DRAM burst length of four 32 bit data chunks For 32 byte read write transactions the memory controller performs two back to back 16 byte DRAM transactions For 64 byte read write transactions the memory controller performs four back to back 16 byte DRAM transactions 6 3 DRAM Partial Writes The memory controller has support for partial writes to DRAM There are four data mask pins M_DM 3 0 one pin per byte used to indicate which bytes should be written 6 4 DRAM Power Management Power Management involves managing and reducing the power consumed by both the memory controller and the DRAM devices The DRAM devices provide two ways to reduc
286. ing IRQ line is masked When a 0 is written to any bit in 07 00 00h RW IRM this register the corresponding IRQ mask bit is cleared and interrupt requests will again be accepted by the controller Masking IRQ2 on the master controller will also mask the interrupt requests from the slave controller 11 3 2 7 Offset 20h AOh OCW2 Operational Control Word 2 Following a part reset or ICW initialization the controller enters the fully nested mode of operation Non specific EOI without rotation is the default Both rotation mode and specific EOI mode are disabled following initialization Table 320 20h AOh OCW2 Operational Control Word 2 Size 8 bit Default Power Well Core Access e Tum Offset Start 20h AOh PCI Configuration B D F Offset End Bit Range Default Access Acronym Description Rotate and EOI Codes R SL EOI These three bits control the Rotate and End of Interrupt modes and combinations of the two 000 Rotate in Auto EOI Mode Clear 001 Non specific EOI command 010 No Operation 07 05 001 WO 011 Specific EOI Command 100 Rotate in Auto EOI Mode Set 101 Rotate on Non Specific EOI Command 110 Set Priority Command 111 Rotate on Specific EOI Command TLO L2 Are Used 04 03 Undef WO OCW2 Select When selecting OCW2 bits 4 3 00 Interrupt Level Select L2 L1 and LO determine the interrupt level acted upon when the SL bit is active A simple binary code selects the channel for the command to act upon Whe
287. interrupt will not occur Stream Run 0 The DMA engine associated with this input stream will be disabled Hardware will report a 0 in this bit when the DMA engine is actually stopped Software must read a 0 from this bit before modifying related 01 0 RW RUN control registers or restarting the DMA engine 1 The DMA engine associated with this input stream will be enabled to transfer data from the FIFO to main memory The SSYNC bit must also be cleared in order for the DMA engine to run For output streams the cadence generator is reset whenever the RUN bit is set Intel Atom Processor E6xx Series Datasheet 175 m n tel Intel High Definition Audio D27 FO Table 257 80h AOh COh EOh ISDOCTL ISD1CTL OSDOCTL OSDICTL I nput Output Stream Descriptor 0 1 Control Register Sheet 2 of 2 Size 24 bit Default 04 0000h Power Well Core Access D E 0 97 Offset Start 80h AOh COh EOh PCI Configuration B D F 0 27 0 Offset End 82h A2h C2h E2h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description Stream Reset 0 Writing a O causes the corresponding stream to exit reset When the stream hardware is ready to begin operation it will report a 0 in this bit Software must read a 0 from this bit before accessing any of the stream registers 00 0 RW SRST 1 Writing a 1 causes the corresponding stream to be reset The Stream Descriptor registers
288. is 9h for 33 MHz legacy backbone resulting in a frequency roughly equivalent to 1 MHz Software then sets up the host controller with an address command and for writes data and then tells the controller to start When the controller has finished transmitting data on writes or receiving data on reads it will generate an SMI if enabled Intel Atom Processor E6xx Series Datasheet 244 ACPI Devices 11 8 4 11 8 5 Table 367 11 8 5 1 intel The host controller supports eight command protocols of the SMB interface see the System Management Bus Specification Version 1 0 Quick Command Send Byte Receive Byte Write Byte Word Read Byte Word Process call Block Read Block Write and Block write block read process call The host controller requires the various data and command fields be setup for the type of command to be sent When software sets HCTL ST the host controller will perform the requested transaction and generate an SMI if enabled when finished Once started the values of the HCTL HCMD TSA HDO and HD1 should not be changed or read until HSTS BSY has been cleared The host controller will update all registers while completing the new command Bus Arbitration Several masters may attempt to get on the bus at the same time by driving SMBDATA low to signal a start condition When the processor releases SMBDATA and samples it low then some other master is driving the bus and the processor must stop t
289. is a serial HDA SDO CMOS HDA Core TDM data output to the codec s The serial output is double pumped for a bit rate of 48 MB s for Intel HD AudioP i Intel HD Audiof Serial Data In These serial inputs are HDA_SDI 1 0 CMOS HDA Core single pumped for a bit rate of 24 MB s They have integrated pull down resistors that are always enabled Intel HD Audio Dock Enable This active low signal controls the external Intel HD AudioP docking isolation logic O When deasserted the external docking switch is in isolate SEH CMOS_HDA Core mode When asserted the external docking switch electrically connects the Intel HD Audio dock signals to the corresponding processor signals Intel HD Audio Dock Reset This signal is a dedicated O reset signal for the codec s in the docking station It works HDA DOCKRST B CMOS_HDA Gore similar to but independent of the normal HDA_RST_B signal Intel Atom Processor E6xx Series Datasheet 35 Table 9 Note 2 6 Table 10 2 7 Table 11 LPC Interface Signals LPC Interface Signals Signal Description i Direction Power ER Signal Name Type Well Description LPC_AD 3 0 Sues 3 Core LPC Address Data Multiplexed Command Address Data O m LPC FRAME B CMOS3 3 Core LPC Frame This signal indicates the start of an LPC cycle 1 0 Serial Interrupt Request This signal conveys the serial LPC SERIRQ CMOS3 3 Core interrup
290. is selected as described above the range that it is implementing is mapped into the device s physical address as described in Table 71 DRAM Address Decoder Sheet 1 of 2 Tech DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 Rank Size 128 MB 128 MB 256 MB 256 MB 512 MB 512 MB 512 MB 1 GB Density 256 Mb 512 Mb 512 Mb 1 Gb 1 Gb 1 Gb 2 Gb 2 Gb Width x8 x16 x8 x16 x8 x8 x16 x8 Bank Bits 2 2 2 3 3 3 3 3 Row Bits 13 13 14 13 14 14 14 15 Column Bits 10 10 10 10 10 10 10 10 A 31 A 30 RS A 29 RS RS R14 A 28 RS RS R13 R13 R13 R13 A 27 RS RS R13 B2 B2 B2 B2 B2 A 26 R12 R12 R12 R12 R12 R12 R12 R12 A 25 R11 R11 R11 R11 R11 R11 R11 R11 A 24 R10 R10 R10 R10 R10 R10 R10 R10 A 23 R9 R9 R9 R9 R9 R9 R9 R9 A 22 R8 R8 R8 R8 R8 R8 R8 R8 A 21 R7 R7 R7 R7 R7 R7 R7 R7 A 20 Bl Bl Bl Bl Bl Bl Bl Bl A 19 R6 R6 R6 R6 R6 R6 R6 R6 A 18 R5 R5 R5 R5 R5 R5 R5 R5 A 17 R4 R4 R4 R4 R4 R4 R4 R4 A 16 R3 R3 R3 R3 R3 R3 R3 R3 A 15 R2 R2 R2 R2 R2 R2 R2 R2 A 14 R1 R1 R1 R1 R1 R1 R1 R1 Notes 1 R Row Address bit 2 C Column Address bit 3 B Bank Select bit M_BS 2 0 4 RS Rank select If RS 0 then Chip Select bit M_CS 0 If RS 1 the Chip Select bit M_CS 1 Intel Atom Processor E6xx Series Datasheet 73 m e n tel Memory Controller Table 71 DRAM Address Decoder Sheet 2 of 2
291. ism allows reads to the flash to be generated using posted writes The completion of the read can be determined by polling the SPI Status register in the processor or by receiving an SMI With either method the system is not encountering long delays for a single non postable cycle to complete on the front side bus Host software can read the data out of the data registers when the cycle completes 11 9 7 2 BIOS Sector Updates If a large sector of the Flash is to be updated external SPI bus master will need to be informed through the Future Reg protocol to avoid long transactions The process for updating a sector varies from device to device some devices will allow up to a 256 byte write while others only allow a byte write at a time From a processor point of view software should write up to 64 bytes at a time into the write posting buffer Data that needs to be preserved should be copied to scratch pad memory and copied in at the respective address Software needs to be aware of different sector write algorithms between Flash vendors For example SST Flash does not allow 64 byte writes it allows byte writes only Hardware does not split 64 byte writes from the posting buffer it is software s responsibility to write byte by byte Intel Atom Processor E6xx Series Datasheet 261 intel The following table shows the different device write times for doing a 512 kB sector write Table 386 11 9 7 3 ACPI Devices Flash Writ
292. isplay devices It operates by converting an input reference frequency into an output frequency The timing generators take their input from internal DPLL devices that are programmable to generate pixel clocks to a maximum pixel clock rate up to 80 MHz for LVDS and 160 MHz for SDVO Unused display PLLs can be disabled to save power Display Ports Display ports are the destination for the display pipe These are the places where the display data finally appears to devices outside the graphics device The Intel Atom Processor E6xx Series has one dedicated LVDS and one SDVO port Since two display ports available for its two pipes the processor can support up to two different images on two different display devices Timings and resolutions for these two images may be different Intel Atom Processor E6xx Series Datasheet 86 Graphics Video and Display em Figure 7 Display Resolutions sDVO LVDS Resolution Refresh Pixel Clock Freq support Suppor 640x480 640x480 848x480 848x480RB 640x480 800x600 848x480 640x480 800x600RB 800x600 848x480 848x480 800x600 1024x768 MHz 1024x768RB IMHz 800x600 85lHz_ 5675 MHz 1024x768 ol 635 MHz 1280x768 aan 6525 MHz 1280x768RB 60 Hz 6825 MHz 1280x768 om ce Max LVDS interface support 7 5 2 1 LVDS Port A single LVDS channel only is supported The single LVDS channel ca
293. ister Intel Atom Processor E6xx Series Datasheet 267 intel ACPI Devices 11 10 3 9 Offset 10h WDTCR WDT Configuration Register Table 396 10h WDTCR WDT Configuration Register Size 8 bit Default 00h Power Well Core Access e Offset Start 10h PCI Configuration B D F Offset End 10h IAF Base Address Base 10 Offset 10h Bit Range Default Access Acronym Description 07 06 00h RO Reserved Reserved WDT Timeout Output Enable This bit indicates whether or not the WDT toggles the external GPIO 4 pin if the WDT times out 05 0h RW WDT_TOUT_EN 0 Enabled Default 1 Disabled WDT Reset Enable When this bit is enable set to 1 it allows internal reset to be trigger when WDT timeout It either trigger COLD or WARM 04 0 RW WDT_RESET_E reset depend on WDT_RESET_SEL bit N O Disable internal reset Default 1 Enable internal COLD or WARM reset WDT Reset Select This determines which reset to be triggered when WDT RESET S WDT RESET EN is set 03 Oh RW EL 0 Cold Reset Default 1 Warm Reset WDT Prescaler Select The WDT provides two options for prescaling the main Down Counter The preload values are loaded into the main down counter right justified The prescaler adjusts the starting point of the 35 bit down counter 0 The 20 bit Preload Value is loaded into bits 34 15 of the main down 02 Oh RW WDT PRE SEL counter The res
294. it Default 00h Power Well Core Access PCI Configuration B D F Offset Start 15h Offset End 18h IAF Base Address Base 10 Offset 18h Bit Range Default Access Acronym Description 07 03 Oh Reserved Reserved WDT Timeout Configuration This register is used to choose the functionality of the timer 02 Oh RW An Watchdog Timer Mode When enabled i e WDT_ENABLE goes from 0 to 1 the timer reloads Preload Value 1 and start decrementing Default Upon reaching timeout the GPIO 4 is driven high once and does not change again until Power is cycled or a hard reset occurs Intel Atom Processor E6xx Series Datasheet 269 intel DN Table 400 18h WDTLR WDT Lock Register Sheet 2 of 2 Size 8 bit Default 00h Power Well Core Access Offset Start 18h PCI Configuration B D F Offset End 18h IAF Base Address Base 10 Offset 18h Bit Range Default Access Acronym Description 01 Oh Watchdog Timer Enable The following bit enables or disables the WDT O Disabled Default 1 Enabled Note This bit cannot be modified if WDT_LOCK has been set Note n WDT mode Preload Value 1 is reloaded every time RW WDT_ENABLE WDT_ENABLE goes from 0 to 1 or the WDT_RELOAD bit is written using the proper sequence of writes See Register Unlocking Sequence When the WDT timeout occurs a reset must happen Note Software must guarante
295. it is set to 1 bits 31 7 0 of this register are Write Only and will return 0 when read When this bit is cleared to 0 bits 00 0 RW WO PROT 31 7 0 are RW Tis bit can only be changed when all four bytes of this register are written in a single write operation If less than four bytes are written this bit retains its previous value 9 3 2 1 42 Offset 1000h EMIL Extended Mode 1 Register Table 267 1000h EMI Extended Mode 1 Register Sheet 1 of 2 Size 32 bit Default 0000 0000h Power Well Core Access e EP TEE Offset Start 1000h PCI Configuration B D F 0 27 0 Offset End 1003h Memory Mapped IO BAR Offset Bit Range Default Access Acronym Description 31 24 0 RO RSVD Reserved Loopback Enable When set output data is rerouted to the input Each 28 0 RW LPBKEN input has its own loopback enable Free Count Request This field determines the clock in which freecnt 27 26 0 RW FREECNTREQ EE the XFR layer BIOS or software must set Any other selection will cause RIRB failures Phase Select Sets the input data sample point within phyclk 25 0 RW PSEL 1 Phase C 0 Phase D Boundary Break Sets the break boundary for reads 24 1 RW 128_4K 0 4KB 1 128B CORB Pace Determines the rate at which CORB commands are issued on the link 000 Every Frame 23 21 000 RW CORBPACE 001 Every 2 Frames 111 Every 8 Frames FIFO Ready Select When cleared SDS FRDY is asserted when there 20 0 RW FRS are 2 or more packets available in the FIFO When
296. ith the write to the SID to create one 32 bit write This register is not affected by D3por to DO reset Table 189 2Ch SVI D Subsystem Vendor Identifier Size 16 bit Default 0000h Power Well Core Access D F 0 27 Offset Start 2Ch PCI Configuration B D F 0 27 0 Offset End 2Dh Bit Range Default Access Acronym Description 15 00 0000h RWO SVID Subsystem Vendor I D These RWO bits have no functionality Intel Atom Processor E6xx Series Datasheet 145 intel Intel High Definition Audio D27 FO 9 3 1 13 Offset 2Eh SI D Subsystem Identifier This register should be implemented for any function that could be instantiated more than once in a given system for example a system with 2 audio subsystems one down on the motherboard and the other plugged into a PCI expansion slot The SID register in combination with the Subsystem Vendor ID register make it possible for the operating environment to distinguish one audio subsystem from the other Software BIOS will write the value to this register After that the value can be read but writes to the register will have no effect The write to this register should be combined with the write to the SVID to create one 32 bit write This register is not affected by D3y07 to DO reset Table 190 2Eh SI D Subsystem Identifier Size 16 bit Default 0000h Power Well Core SES P
297. ivery of interrupts is done by writing to a fixed set of memory locations in CPU s The following sequence is used When the processor detects an interrupt event active edge for edge triggered mode or a change for level triggered mode it sets or resets the internal IRR bit associated with that interrupt The processor delivers the message by performing a write cycle to the appropriate address with the appropriate data The address and data formats are described in section below EOI The data of the EOI message is the vector This value is compared with all the vectors inside the IOxAPIC and any match causes RTE x RIRR to be cleared The EOI is a downstream 32 bit memory write cycle with byteO enabled sent from CPU to I OxAPIC Interrupt Message Format The processor writes the message to the backbone as a 32 bit memory write cycle It uses the following formats the Address and Data Interrupt Delivery Address Value Interrupt Delivery Address Value Bit Description 31 20 FEEh 19 12 Destination ID RTE x DID 11 04 Extended Destination ID RTE x EDID Redirection Hint f RTE x DLM Lowest Priority 001 this bit will be set Otherwise this bit 03 will be cleared 02 Destination Mode RTE x DSM 01 00 00 Intel Atom Processor E6xx Series Datasheet 226 ACPI Devices 11 4 4 5 Table 331 11 4 5 11 4 6 11 5 11 5 1 intel I nterrup
298. k Ratio Table 123 Offset FOh GCR Graphics Clock Ratio Sheet 1 of 2 Size 16 bit Default 0006h Power Well Core Access D F 0 3 Offset Start FOh PCI Configuration B D F 0 3 0 Offset End Fih Bit Range Default Access Acronym Description 15 04 0 RO RSVD Reserved Intel Atom Processor E6xx Series Datasheet 109 m e n tel Graphics Video and Display Table 123 Offset FOh GCR Graphics Clock Ratio Sheet 2 of 2 Size 16 bit Default 0006h Power Well Core Access D E 0 3 Offset Start FOh PCI Configuration B D F 0 3 0 Offset End F1h Bit Range Default Access Acronym Description graphics 2x Clock to Graphics Clock Ratio This field should be set by Software to correspond with the gfx2xclkp graphics 2x clock to gfxclkp graphics clock ratio The field is used to configure the graphics 2D processing engine 03 02 01 RW ri 00 gfx2xclkp to gfxclkp ratio is 1 1 01 gfx2xclkp to gfxclkp ratio is 2 1 10 Reserved 11 Reserved Graphics Clock to Core Clock Ratio Set by SW to correspond with the 01 00 10 RW GCCR graphics clock to core clock ratio 7 7 2 22 Offset F4h LBB Legacy Backlight Brightness Table 124 Offset F4h LBB Legacy Backlight Brightness Size 32 bit Default N A Power Well Core Access e ecm CH Offset Start F4h PCI Configuration B D F 0 3 0 Offset End F7h Bit Range Default Access Acro
299. ks SMI System Management Interrupt is used to indicate any of several system conditions such as thermal sensor events throttling activated access to System Management RAM chassis open or other system state related activity TDMA Time Division Multiple Access TEL Throttle Enforcement Limit TCC Thermal Control Circuit A feature of the Intel Atom Processor E6xx Series that is used to cool the processor should its temperature exceed a predetermined activation temperature TMDS Transition Minimized Differential Signaling TMDS is a signaling interface from Silicon Image that is used in DVI and HDMI TMDS is based on low voltage differential signaling and converts an 8 bit signal into a 10 bit transition minimized and DC balanced signal equal number of Os and 1s in order to reduce EMI generation and improve reliability VCO Voltage Controlled Oscillator Intel vT Intel virtualization Technology Warm Reset Warm reset is when both RESET B and PWROK are asserted 1 2 Reference Documents Document Document Number Location Advanced Configuration and Power Interface Version 3 0 ACPI http www acpi info spec htm 1 A PC HPET High Precision Event Timers Specification Revision 1 0 http www intel com hardwaredesign hpetspec_1 pdf Intel Atom Processor E6xx Series Specification http download intel com embedded processor specup
300. l S 5 o OL ol oP Jor jaj Toi jaj Toi jaj Jo Joy o o Nm oo Ul ju al lal lal lal fal lal fal lal lal la lal lal al lal Elk OL To Jo Jo o o Toi Jo Jo Jo Jo o o N y 1D 1 ID 3 RA DER o c Nc e KI YA NN EIA EI p poe Pp I ocoueato MI i vs KI DES Jes 3 EA a es LN ae S PCIE_PERP 0 lt CIE_PETN O PCIE PERP 1 lt v lt lt E lt lt lt lt lt v D n n n n n m o Pd peel lt z 0 lt lt lt CCD180 CCP33 CCA PEG CCA PEG T lt lt lt lt lt lt z lt z lt z lt lt o o e o o e o o D e o o e o oO o o 7 e a gt m m a CIE PETP 0 O ws 3 pocoo PCIE CLKINN PCIERCOMPO Intel Atom Processor E6xx Series Datasheet 288 m e Ballout and Package Information tel Figure 17 Intel Atom Processor E6xx Series Ball Map Sheet 5 of 5 ST SAA Iu T Y ps LL desi L 4 I T TL S T LTC Jes S Js L uos 1 d E Ie ss IE CITI O EI E NS 3 2 A O e CUM CESTAS AS CO AA PROVO CST eh or fr INMUNES GER CR ER EC BEER DEE EE RR CECR RER CN CS RER RR CE
301. ld the new Programmed Access pending until the preceding SPI access completes It will then begin to request the SPI bus for the Programmed Access Once the SPI Host hardware has committed to running a programmed access subsequent writes to the programmed cycle registers that occur before it has completed will not modify the original transaction and will result in the assertion of the Blocked Access Status bit in Offset 00h SPIS SPI Status Software should never purposely behave in this way and rely on this behavior However the Blocked Access Status bit provides basic error reporting in this situation Writes to the following registers causes the Blocked Access Status bit assertion in this situation Offset 02h SPIC SPI Control Offset 04h SPIA SPI Address Offset 08h SPIDO SPI Data O Flash Protection There are two types of Flash Protection mechanisms 1 BIOS Range Write Protection 2 SMI Based Global Write Protection The two mechanisms are conceptually ORed together such that if any of the mechanisms indicate that the access should be blocked then it is blocked Table 384 provides a summary of the two mechanisms Intel Atom Processor E6xx Series Datasheet 258 ACPI Devices Table 384 11 9 5 14 1 11 9 5 14 2 11 9 5 14 3 intel Flash Protection Summary Mechanism Accesses Range Reset Override or SMI Equivalent Function on FWH Blocked Specific Override BIOS Range Write Writes Ye
302. le 163 Offset 60h RSTS Root Status Size 32 bit Default 00000000h Power Well Core Access D FO Offset Start 60h PCI Configuration B D F 0 23 26 0 Offset End 63h Bit Range Default Access Acronym Description 31 18 0 RO RSVD Reserved 17 0 RO PP PME Pending This will never be set by the processor 16 0 RWC PS PME Status This indicates that PME was asserted by the requestor ID in RID Subsequent PMEs are kept pending until this bit is cleared PME Requestor ID This indicates the PCI requestor ID of the last PME requestor Valid only when PS is set Root ports are capable of storing the 15 00 0 RO RID requester ID for two PM PME messages with one active this register and a one deep pending queue Subsequent PM PME messages will be dropped Intel Atom Processor E6xx Series Datasheet 129 intel PCI Express 8 2 3 PCI Bridge Vendor Capability Table 164 PCI Bridge Vendor Capability Start End Symbol Register Name 90 91 SVCAP Subsystem Vendor Capability ID 94 97 SVID Subsystem Vendor IDs 8 2 3 1 SVCAP Subsystem Vendor Capability Table 165 Offset 90h SVCAP Subsystem Vendor Capability Size 16 bit Default 0000h Power Well Core Access PCI Configuration B D F 0 23 26 0 Offset Start 90h Offset End 91h Bit Range Default Access Acronym Description 15 08 A0h RO NEXT ie Capability This indicates the locati
303. le Opcode 1 See the description for bits 7 0 X Allowable Opcode 0 Software programs an SPI opcode into this field 7 00 05h RWS AO0 for use when initiating SPI commands through the Control Register 11 9 5 11 Offset 60h PBRO Protected BI OS Range 0 2 This register can not be written when the SPI Configuration Lock Down bit in Offset 00h SPIS SPI Status register is set to 1 Table 382 60h PBRO Protected BIOS Range 0 Size 32 bit Default 00000000h Power Well Core Access Offset Start 3080h at 4h PCI Configuration B D F 0 31 0 Offset End 3083h at 4h Memory Mapped IO BAR RCBA Offset Bit Range Default Access Acronym Description 31 Write Protection Enable When set this bit indicates that the Base and 0 RW Special WPE Limit fields in this register are valid and that writes directed to addresses p between them inclusive must be blocked by hardware The base and limit fields are ignored when this bit is cleared 30 24 0 RV Reserved Reserved 23 12 Protected Range Limit This field corresponds to SPI address bits 23 12 and specifies the upper limit of the protected range Address bits 000h RW Special PRL 11 0 are assumed to be FFFh for the limit comparison Any address greater than the value programmed in this field is unaffected by this protected range 11 00 Protected Range Base This field corresponds to SPI address bits 23 12 7 and specifies
304. lement Self Description 61 45 0010h HDD Intel High Definition AudioP Description 61 46 0018h HDBA Intel High Definition AudioP Base Address ssee 61 47 interrupt Pin ConfiguratiON uice srno ehh ene aa reales 62 48 3100h D31IP Device 31 Interrupt Bim 62 49 3110h D27IP Device 27 Interrupt Bim 62 50 3118h DO2IP Device 2 Interrupt Bin 62 51 3120h D26IP Device 26 Interrupt Pin 63 52 3124h D25IP Device 25 Interrupt Pin 63 53 3128h D24IP Device 24 Interrupt Pin 63 Intel Atom Processor E6xx Series Datasheet 13 inte Di 104 105 106 107 108 312Ch D23IP Device 23 Interrupt Pin 63 3130h DO3IP Device 3 Interrupt bim 64 linterrupt Route Configuration i iki nieces rir E rece reza tcs 64 3140h D31IR Device 31 Interrupt Route 64 3148h D27IR Device 27 Interrupt Route 65 314Ah D26IR Device 26 Interrupt Route 65 314Ch D25IR Device 25 Interrupt Route 65 314Eh D24IR Device 24 Interrupt Route 66 3150h D23IR Device 23 Interrupt Route 66 3160h DO2IR Device 2 Interrupt Route 66 3162h DO3IR Device 3 Interrupt Route 67 3400h RG RTC Gonfiguration ree e RR SEENEN GARA XX RARE ENEE 67 3410h BNT Boot ConfligUEati On EEN 67 Memory Controller Supported Frequencies and Data Rate 69 Supported Memory Configurations for DDR 71 Supported DDR2 DRAM Devices rete tee een nn 72 Memory Size Per Rank essien nnd Aian senem rr erre rn r
305. lities and ID Size 64 bit Default Undefined Power Well Core Access e SS Offset Start 000h PCI Configuration B D F Offset End 007h Bit Range Default Access Acronym Description 5 0429B1 Counter Tick Period Indicates a period of 69 841279ns 14 1318 MHz 63 32 7Fh RO CTP clock period 31 16 8086h RO VID Vendor I D Value of 8086h indicates Intel 15 1 RO LRC Legacy Rout Capable Indicates support for Legacy Interrupt Rout 14 0 RO RSVD Reserved 13 1 RO CS Counter Size This bit is set to indicate that the main counter is 64 bits 12 08 02h RO NT Number of Timers Indicates that 3 timers are supported Revision ID Indicates that revision 1 0 of the specification is 07 00 01h RO RID implemented 11 2 1 2 Offset 010h GC General Configuration Table 305 010h GC General Configuration Size 64 bit Default Power Well Core Access 3 T Offset Start 010h PCI Configuration B D F Offset End 017h Bit Range Default Access Acronym Description 63 02 0 RO RSVD Reserved Legacy Route Enable When set interrupts will be routed as follows Timer 0 will be routed to IRQO in 8259 or IRQ2 in the I O APIC 01 0 RW LRE e Timer 1 will be routed to IRQ8 in 8259 and I O APIC Timer 2 will be routed as per the routing in T2C When set the TNC IR will have no impact for timers 0 and 1 Overall Enable When set the timers can generate interrupts When 00 0 RW EN cleared the main counter will halt and no interrupts will be caused by any timer For level
306. ll Core Access D E 0 27 Offset Start 5Eh PCI Configuration B D F 0 27 0 Offset End 5Eh Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description d RI RB Size Capability 0100b indicates that the processor only supports BEST 70109 RO RIRBSZCAP 3 RIRB size of 256 RIRB entries 2048B 03 02 0 RO RSVD Reserved 01 00 10 RO RIRBSIZE RIRB Size Hardwired to 10b which sets the RIRB size to 256 entries 2048B Intel Atom Processor E6xx Series Datasheet 172 Intel High Definition Audio D27 FO 9 3 2 1 28 Offset 60h IC Immediate Command Register Table 253 60h IC Immediate Command Register Size 32 bit Default 0000 0000h Power Well Core Access D F 0 27 Offset Start 60h PCI Configuration B D F 0 27 0 Offset End 63h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description Immediate Command Write The command to be sent to the codec via 31 00 0 RW LC the Immediate Command mechanism is written to this register The d command stored in this register is sent out over the link during the next available frame after a 1 is written to the ICB bit LBAR 68h bit 0 9 3 2 1 29 Offset 64h IR Immediate Response Register Table 254 64h IR Immediate Response Register Size 32 bit Default 0000 0000h Power Well Core Access D F 0 27 Offset Start 64h PCI Configuration B D F 0 27 0 Offset E
307. load_Value_1 15 8 This register is used to hold the bits 8 through 15 of the preload value 1 for the WDT Timer The Value in the Preload Register is automatically transferred into the 35 bit down counter 07 00 FFh RW PLOAD1_15_8 The value loaded into the preload register needs to be one less than the intended period This is because the timer makes use of zero based counting i e zero is counted as part of the decrement Refer to Section 11 10 4 2 for details on how to change the value of this register 11 10 3 3 Offset 02h PV1R2 Preload Value 1 Register 2 Table 390 02h PV1R2 Preload Value 1 Register 2 Size 8 bit Default FFh Power Well Core Access Offset Start 02h PCI Configuration B D F Offset End 02h IA F Base Address Base 10 Offset 02h Bit Range Default Access Acronym Description 07 04 Oh Reserved Reserved Preload Value 1 19 16 This register is used to hold the bits 16 through 19 of the preload value 1 for the WDT Timer The Value in the Preload Register is automatically transferred into the 35 bit down counter 03 00 Fh RW PLOAD 19 16 The value loaded into the preload register needs to be one less than the intended period This is because the timer makes use of zero based counting i e zero is counted as part of the decrement Refer to Section 11 10 4 2 for details on how to change the value of this register Intel Atom Processor E6xx
308. mand The Read Back Command written to port 43h latches the count value programmed mode and current states of the OUT pin and Null Count flag of the selected counter or counters The value of the counter and its status may then be read by I O access to the counter address The Read Back Command may be used to latch multiple counter outputs at one time This single command is functionally equivalent to several counter latch commands one for each counter latched Each counter s latched count is held until it is read or reprogrammed Once read a counter is unlatched The other counters remain latched until they are read If multiple count Read Back Commands are issued to the same counter without reading the count all but the first are ignored The Read Back Command may additionally be used to latch status information of selected counters The status of a counter is accessed by a read from that counter s I O port address If multiple counter status latch operations are performed without reading the status all but the first are ignored Both count and status of the selected counters may be latched simultaneously This is functionally the same as issuing two consecutive separate Read Back Commands If multiple count and or status Read Back Commands are issued to the same counters without any intervening reads all but the first are ignored If both count and status of a counter are latched the first read operation from that counter will retu
309. mation If the Slave receives an un recognized or invalid opcode it should ignore the rest of the packet and wait for the deassertion of SPI CS Bus Errors If the first 8 bits specify an opcode which is not supported the slave will not respond and wait for the next high to low transition on SPI CS SPI hardware should automatically discard 8 bit words that were not completely received upon deassertion of the SPI CS signal Any other error correction or detection mechanisms must be implemented in firmware software Instructions Instructions Sheet 1 of 2 Instruction ST M25P80 ST M45P80 NexFlash NX25P SST 25V040 4 Mb 8 Mb 8 Mb SST 25VFO80 8 Mb Write Status 01 01 01 Data Program 02 02 02 02 Read Data 03 03 03 03 Write Disable 04 04 04 04 Read Status 05 05 05 05 Intel Atom Processor E6xx Series Datasheet 248 ACPI Devices Table 370 Note 11 9 4 1 5 Table 371 11 9 5 11 9 5 1 Warning Instructions Sheet 2 of 2 intel Instruction ST M25P80 ST M45P80 NexFlash NX25P SST 25V040 4 Mb 8 Mb 8 Mb SST 25VFO80 8 Mb Write Enable 06 06 06 06 Page Write 0A Fast Read 1 OB OB OB Ena Write Status 50 256B Erase DB 4 kByte Erase 20 64 kB Erase D8 D8 D8 52 Chip Erase C7 C7 60 Auto Add Inc 2 AF Power Down Up B9 AB B9 AB B9 Read ID 9F 90 AB or 90
310. me well memory mapped configuration registers not PCI Configuration Registers in the controller will be reset The Intel HD Audio link RESET B signal will be asserted and all other link signals will be driven to their default values After the hardware has completed sequencing into the reset state it will report a O in this bit Software must read a 0 from this bit to verify that the controller is in reset 1 Writing a 1 to this bit causes the controller to exit its reset state and deassert the Intel HD Audio link RESET B signal Software is responsible for setting clearing this bit such that the minimum Intel HD AudioP link RESET B signal assertion pulse width specification is met When the controller hardware is ready to begin operation it will report a 1 in this bit Software must read a 1 from this bit before accessing any controller registers This bit defaults to a O after hardware reset therefore software needs to write a 1 to this bit to begin 00 0 RW CRST B operation Notes The CORB RIRB RUN bits and all Stream RUN bits must be verified cleared to zero before writing a O to this bit in order to assure a clean restart When setting or clearing this bit software must ensure that minimum link timing requirements minimum RESET B assertion time etc are met When this bit is 0 indicating that the controller is in reset writes to all Intel HD AudioP memory mapped registers are ignored as if the device is not present
311. memory controller configuration IDO 04 Strap RO MEMI DO Defines the memory device width 0 x16 devices 1 x8 devices Disable RTC When set decodes to the RTC will be disabled and the 03 0 RW DRTC accesses instead will be sent to LPC This allows testing to determine whether these functions are needed for XP and Vista Intel Atom Processor E6xx Series Datasheet 194 LPC Interface D31 FO n tel j Table 289 Offset 5Ch MC Miscellaneous Control Sheet 3 of 3 Size 32 bit Default 00000000h Power Well Access EU Offset Start 5Ch PCI Configuration B D F X 31 0 Offset End 5Fh Bit Range Default Access Acronym Description Disable 8259 When set decodes to the 8259 will be disabled and 02 0 RW D8259 the accesses instead will be sent to LPC This allows testing to determine whether these functions are needed for XP and Vista Disable 8254 When set decodes to the 8254 will be disabled and 01 0 RW D8254 the accesses instead will be sent to LPC This allows testing to determine whether these functions are needed for XP and Vista 00 0 RW RSVD Reserved 10 4 Interrupt Control 10 4 1 PxRC PI RQx Routing Control Register Offset 60h routes PIRQA 61h routes PIRQB 62h routes PI RQC 63h routes PIRQD 64h routes PIRQE 65h routes PIRQF 66h routes PIRQG and 67h routes PIRQH Table 290 Offset 60h 67h PxRC PIRQ A H Routing Control
312. mer WDT The Intel Atom Processor E6xx Series supports a user configurable watchdog timer It contains selectable prescaler approximately 1 us to 10 min When the WDT triggers GPIO 4 is asserted Real Time Clock RTC The Intel Atom Processor E6xx Series supports a RTC that provides a battery backed up date and time keeping device The time keeping comes from a 32 768 kHz oscillating source Package The Intel Atom Processor E6xx Series comes in an Flip Chip Ball Grid Array FCBGA package and consists of a silicon die mounted face down on an organic substrate populated with 676 solder balls with 0 8 mm ball pitch on the bottom side The package dimensions are 22 mm x 22 mm Z height is 2 097 mm 2 35 mm Intel Atom Processor E6xx Series SKU Intel Atom Processor E6xx Series SKU for Different Segments SKU E620 E640 E660 E680 E620T E640T E660T E680T Core Frequency 0 6 1 0 1 3 1 6 0 6 1 0 1 3 1 6 GHz L2 Cache KB 512 512 512 512 512 512 512 512 Memory 800 800 800 800 800 800 800 800 Frequency MHz Maximum Memory Size GB 2 2 2 2 2 2 2 2 Gtx Frequency 320 320 400 400 320 320 400 400 MHz Video Decode 267 267 267 267 267 267 267 267 Frequency MHz Video Encode Disabled 267 267 267 Disabled 267 267 267 Frequency MHz PCle ports 4 4 4 4 4 4 4 4 Intel Hyper Threading Yes Yes Yes Yes Yes Yes Yes Yes Technology Intel
313. modifications to the base color and texture of vertices examples of different types of lighting are Ambient lighting is constant in all directions and the same color to all pixels of an object Ambient lighting calculations are fast but objects appear flat and unrealistic Diffuse lighting takes into account the light direction relative to the normal vector of the object s surface Calculating diffuse lighting effects takes more time because the light changes for each object vertex but objects appear shaded with more three dimensional depth Specular lighting identifies bright reflected highlights that occur when light hits an object surface and reflects toward the camera It is more intense than diffuse light and falls off more rapidly across the object surface Although it takes longer to Intel Atom Processor E6xx Series Datasheet 71 m e n tel Graphics Video and Display 7 2 4 7 2 4 1 7 2 4 2 7 2 4 3 7 2 5 calculate specular lighting than diffuse lighting it adds significant detail to the surface of some objects Emissive lighting is light that is emitted by an object such as a light bulb Pixel Processing After vertices are transformed and lit by the vertex processing pipeline the pixel processor takes the vertex information and generates the final rasterized pixels to be displayed The steps of this process include removing hidden surfaces applying textures and shading and converting pixels
314. n n Next Capability Points to the next item in the capability list Wired to 13398 00h RO NEXT 00h to indicate this is the last capability in the list 07 00 05h RO CAP Cap ID Indicates that this pointer is a MSI capability 9 3 1 24 Offset 62h MSI CTL MSI Message Control Register Table 201 62h MSI CTL MSI Message Control Register Size 16 bit Default Oh Power Well Core Access DE 0 97 Offset Start 62h PCI Configuration B D F 0 27 0 Offset End 63h Bit Range Default Access Acronym Description 15 01 0 RO RSVD Reserved MSI Enable 00 0 RW ME 0 An MSI may not be generated 1 An MSI will be generated instead of an INTx signal 9 3 1 25 Offset 64h MSI ADR MSI Message Address Register Table 202 64h MSI ADR MSI Message Address Register Size 32 bit Default 0000 0000h Power Well Core Access D F 0 27 Offset Start 64h PCI Configuration B D F 0 27 0 Offset End 67h Bit Range Default Access Acronym Description 31 02 0 RW MLA Message Lower Address Lower Address used for MSI Message 01 00 0 RO RSVD Reserved 9 3 1 26 Offset 68h MSI DATA MSI Message Data Register Table 203 68h MSI DATA MSI Message Data Register Size 16 bit Default 0000h Power Well Core Access D F 0 97 Offset Start 68h PCI Configuration B D F 0 27 0 Offset End 69h Bit Range Default Access Acronym Descri
315. n NR 121 8 2 1 22 BCTRL Bridge Control 121 8 2 2 Root Port Capability Structure 122 8 2 2 1 CLIST Capabilities List ooo ennt haee ien 123 8 2 2 2 XCAP PCI Express Capabilities sese 123 8 2 2 3 DCAP Device Capabilities sse 123 8 2 2 4 DCTL Device Control 124 8 2 2 5 DSTS Device Status 125 8 2 2 6 ECAP Link Capabilities error ee Error tere en terne nta 125 8 2 2 7 VL CTE Link Control veais toi cod Dae 126 8 2 2 8 STS Lirik Status canina radar P DR RAN 126 Intel Atom Processor E6xx Series Datasheet Contents 8 2 2 9 SLCAP Slot Capabilities teeter eee He 127 8 2 2 10 SLCTL Slot Control 127 8 2 2 11 SLSTS Slot Status deserere erena dr ones ga 128 8 2 2 12 RCTL Root Control 129 8 2 2 13 RCAP Root Capabilties mne 129 8 2 2 14 RSTS Root Status cr RR RR RR ORE RO ERA RUE REOR REC 129 8 2 3 PCI Bridge Vendor Capability sess 130 8 2 3 1 SVCAP Subsystem Vendor Capability oooccccccccccccccconnicnnnnnns 130 8 2 3 2 SVID Subsystem Vendor IDs sss He 130 8 2 4 PCI Power Management Capabiltv nmm 130 8 2 4 1 PMCAP Power Management Capability ID sess 131 8 2 4 2 PMC PCI Power Management Capabilties nenc 131 8 2 4 3 PMCS PCI Power Management Control And Status 131 8 2 5 Port E rd EEN 132 8 2 5 MPC Miscellaneous Por
316. n completion of link training 10 0 RO LTE Link Training Error Not supported Negotiated Link Width This may only take the value of a single link 09 04 00h RO NLW 01h The value of this register is undefined if the link has not successfully trained 03 00 1h RO LS Link Speed Link is 2 5 Gb s Intel Atom Processor E6xx Series Datasheet 126 PCI Express 8 2 2 9 SLCAP Slot Capabilities Table 158 Offset 54h SLCAP Slot Capabilities Size 32 bit Default 00000060h Power Well Core Access JEn Offset Start 54h PCI Configuration B D F 0 23 26 0 Offset End 57h Bit Range Default Access Acronym Description Physical Slot Number This is a value that is unique to the slot number 31 19 0000h RWO PSN The BIOS sets this field and it remains set until a platform reset 18 17 00b RO RSVD Reserved Slot Power Limit Scale This specifies the scale used for the slot power 16 15 00b RWO SLS limit value The BIOS sets this field and it remains set until a platform reset Slot Power Limit Value This specifies the upper limit in conjunction with SLS value on the upper limit on power supplied by the slot The 14 07 00h RWO SLV two values together indicate the amount of power in watts allowed for the slot The BIOS sets this field and it remains set until a platform reset 06 1b RO HPC Hot Plug Capable
317. n support clock frequency ranges up to a maximum pixel clock rate up to 80 MHz The graphics core is responsible to read the EDID ROM from the installed panel if present specifications through I C interface and the software driver uses it to program the pipe A timing registers The Intel Atom Processor E6xx Series supports a single LVDS channel with several modes and data formats The single LVDS channel consists of 4 data pairs and a clock pair The phase locked transmit clock is transmitted over the LVDS clock pair in parallel with the data being sent out over the data pairs The pixel serializer supports 8 bit or 6 bit per color channel The display data from the display pipe is sent to the LVDS Intel Atom Processor E6xx Series Datasheet 87 7 5 2 2 Figure 8 7 5 2 3 intel Graphics Video and Display transmitter port at the dot clock frequency which is determined by the panel timing requirements The serialized output of LVDS is running at the serial clock of 7x dot clock frequency The transmitter can operate in a variety of modes and supports several data formats The serializer supports 6 bit or 8 bit color per lane for 18 bit and 24 bit color respectively and single channel operating modes The display stream from the display pipe is sent to the LVDS transmitter port at the dot clock frequency which is determined by the panel timing requirements The output of LVDS is running at a fixed multiple of the dot
318. n the SL bit is inactive these bits do not have a defined function programming L2 L1 and LO to 0 is sufficient in this case Bits Interrupt Level Bits Interrupt Level 02 00 Undef WO L2 L1 LO 000 1RQO 8 100 1RQ4 12 001 IRQ1 9 101 IRQ5 13 010 IRQ2 10 110 IRQ6 14 011 IRQ3 11 111 IRQ7 15 Intel Atom Processor E6xx Series Datasheet 216 ACPI Devices Offset 20h AOh OCW3 Operational Control Word 3 Table 321 20h AOh OCW3 Operational Control Word 3 Size 8 bit Default Power Well Core Access 7 Offset Start 20h AOh PCI Configuration B D F Offset End Bit Range Default Access Acronym Description 07 X RO RSVD Reserved Must be 0 Special Mask Mode If this bit is set the Special Mask Mode can be used by an interrupt service routine to dynamically alter the system 06 0 WO SMM priority structure while the routine is executing through selective enabling disabling of the other channel s mask bits Bit 6 the ESMM bit must be set for this bit to have any meaning Enable Special Mask Mode When set the SMM bit is enabled to set or 05 1 WO ESMM reset the Special Mask Mode When cleared the SMM bit becomes a don t care 04 03 X WO 03S OCW3 Select When selecting OCW3 bits 4 3 01 Poll Mode Command When cleared poll command is not issued When 02 X WO PMC set the next I O read to the interrupt con
319. nal Disable 8 2 6 1 FD Functional Disable Table 175 Offset FCh FD Functional Disable Size 32 bit Default 00000000h Power Well Core Access i ae i Offset Start FCh PCI Configuration B D F 0 23 26 0 Offset End FFh Bit Range Default Access Acronym Description 31 03 RO RSVD Reserved 02 RW CGD Reserved 01 RO RSVD Reserved Disable When set the function is disabled configuration space is 00 oe D disabled 88 Intel Atom Processor E6xx Series Datasheet 135 l n tel PCI Express Intel Atom Processor E6xx Series Datasheet 136 m Intel High Definition Audio D27 FO I n tel 9 0 9 1 Intel High Definition Audio D27 FO Overview The Intel High Definition Audio controller consists of a set of DMA engines that are used to move samples of digitally encoded data between system memory and an external coder The controller communicates with the external codec s over the Intel HD Audio serial link The Intel Atom Processor E6xx Series implements two output DMA engines and two input DMA engines The Output DMA engines move digital data from system memory to a D A converter in a codec The processor implements a single Serial Data Output signal HDA_SDO that is connected to all external codecs The Input DMA engines move digital data from the A D converter in the codec to system memory The processor supports up to two external codecs by implementing two Serial Data Input si
320. nce BIOS has locked down the Protected BIOS Range registers this mechanism remains in place until the next system reset SMI Based Global Write Protection The processor provides a method for blocking writes to the SPI flash when the Write Protect bit is cleared i e protected in Offset D8h BC BIOS Control Register This is achieved by checking the Opcode type information which can be locked down by the initial Boot BIOS of the requested command The Write Protect and Lock Enable bits interact in the same manner for SPI BIOS as they do for the FWH BIOS SPI Flash Address Range Protection The System Flash BIOS occupies the top part of the SPI Flash Memory Device when sharing this space with the Manageability functions In order to prevent the system from illegally accessing or modifying information in the Manageability areas the processor checks outgoing addresses with the Offset 50h BBAR BIOS Base Address register and blocks any cycles with addresses below that value This includes Direct Memory Reads to the SPI flash In the case of Direct Memory Reads the processor must return all 1 s in the read completion Intel Atom Processor E6xx Series Datasheet 259 intel Series 11 9 5 14 4 11 9 6 11 9 7 Note that once BIOS has locked down the BIOS BAR this mechanism remains in place until the next system reset There is one exception where processor initiated reads may access data below the BIOS Base Address If
321. nd 67h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description Immediate Response Read This register contains the response received from a codec resulting from a command sent via the Immediate 31 00 0 RO IRR Command mechanism If multiple codecs responded in the same frame there is no guarantee as to which response will be latched Therefore broadcast type commands must not be issued via the Immediate Command mechanism 9 3 2 1 30 Offset 68h ICS Immediate Command Status Table 255 68h ICS Immediate Command Status Sheet 1 of 2 Size 16 bit Default 0000h Power Well Core Access D F 0 27 Offset Start 68h PCI Configuration B D F 0 27 0 Offset End 69h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 15 02 0 RO RSVD Reserved Immediate Result Valid This bit is set to a 1 by hardware when a new response is latched into the IRR register This is a status flag indicating that software may read the response from the Immediate 01 0 RWC IRV Response register Software must clear this bit by writing a one to it before issuing a new command so that the software may determine when a new response has arrived Intel Atom Processor E6xx Series Datasheet 173 intel Intel High Definition Audio D27 FO Table 255 68h ICS Immediate Command Status Sheet 2 of 2 Size 16 bit Default 0000
322. nd Capabilities Sheet 1 of 2 Size 64 bit Default Power Well Core Access VEN Offset Start 100h 120h 140h PCI Configuration RE Offset End 107h 127h 147h Bit Range Default Access Acronym Description Interrupt Rout Capability Indicates I OxAPIC interrupts the timer can See use 63 32 Desc RO IRC Timer 0 1 00f00000h Indicates support for IRQ20 21 22 23 Timer 2 00f00800h Indicates support for IRQ11 20 21 22 and 23 31 16 0 RO RSVD Reserved 15 0 RO FID FSB Interrupt Delivery Not supported 14 0 RO FE FSB Enable Not supported since FID is not supported Interrupt Rout Indicates the routing for the interrupt to the IOxAPIC 13 9 00h RW IR If the value is not supported by this particular timer the value read back j will not match what is written If GC LRE is set then Timers 0 and 1 have a fixed routing and this field has no effect Timer 32 bit Mode When set this bit forces a 64 bit timer to behave 08 0 RO RW T32M as a 32 bit timer For timer O this bit will be read write and default to 0 For timers 1 and 2 this bit is read only 0 Intel Atom Processor E6xx Series Datasheet 208 ACPI Devices intel Table 308 100h 120h 140h T O 2 C Timer 0 2 Config and Capabilities Sheet 2 of 2 Size 64 bit Default Power Well Core Access SIS Offset Start 100h 120h 140h PCI Contigurati n BDE Offset End 107h 127h 147h Bit Range
323. nd external codecs All controller registers including the memory mapped registers must be addressable as byte word and D word quantities The software must always make register accesses on natural boundaries i e D word accesses must be on D word boundaries word accesses on word boundaries etc Note that the Intel HD Audio memory mapped register space must not be accessed with the LOCK semantic exclusive access mechanism If software attempts exclusive access mechanisms to the Intel HD AudioP memory mapped register space the results are undefined 9 3 1 Registers Table 177 Intel High Definition Audio PCI Configuration Registers Sheet 1 of 3 Start End Symbol Register Name Reset Value Access 00 01 VID Vendor Identification 8086h RO 02 03 DID Device Identification 811Bh RO 04 05 PCICMD PCI Command 0000h RW RO 06 07 PCISTS PCI Device Status 0010h RO O1h for B 0 ae X Stepping 08 08 RID Revision Identification 02h for B 1 RO Stepping 09 0B CC Class Codes 040300h RO Intel Atom Processor E6xx Series Datasheet 140 Intel High Definition Audio D27 FO intel Table 177 Intel High Definition Audio PCI Configuration Registers Sheet 2 of 3 Start End Symbol Register Name Reset Value Access DC DC CLS Cache Line Size 00h RW 0D 0D LT Latency Timer 00h RO
324. nd power management RTC RTCX2 32 768 KHz Crystal oscillator Always running Derivative Clocks These are clock domains that are fractional multiples of existing clock freq uencies M CKP Drives SDRAM ranks 0 and 1 DDR2 M_CKN 200 MNZ From Most ELL Data Rate is 2x the clock rate LVD_CLKP LVDS LVD_CLKN A e From Display PLL LVDS display clock outputs SDVO CLKP SDVO SDVO CLKN den M From Display PLL SDVO display clock outputs LPC LPC CLKOUT 2 0 Up to 33 MHz From CRU Supplied for external devices i requiring PCI CLK Wf Hp HDA_CLK 24 MHz From CRU Drives external codecs SMBus SMB_CLK Up to 1 MHz From CRU Drives external SMBus device SPI SPI SCLK 20 33 MHz From CRU Drives external SPI flash device Intel Atom Processor E6xx Series Datasheet 51 n tel System Clock Domains Intel Atom Processor E6xx Series Datasheet 52 Register and Memory Mapping 5 0 intel Register and Memory Mapping This chapter describes the I O and memory map settings for the Intel Atom Processor E6xx Series in the MCP 5 1 Address Map The Intel Atom Processor E6xx Series contains registers that are located in the processor s memory and I O space It also contains sets of PCI configuration registers that are located in a separate configuration space Table 35 Register Access Types and Definitions Access Type Meaning Description RO Re
325. nding IRQ input The IRQ input can remain high without generating another interrupt If an ELCR bit is 1 an interrupt request will be recognized by a high level on the corresponding IRQ input and there is no need for an edge detection The interrupt request must be removed before the EOI command is issued to prevent a second interrupt from occurring In both the edge and level triggered modes the IRQ inputs must remain active until after the falling edge of the first internal INTA If the IRQ input goes inactive before this time a default IRQ7 vector will be returned End Of Interrupt EOI Normal EOI In Normal EOI software writes an EOI command before leaving the interrupt service routine to mark the interrupt as completed There are two forms of EOI commands Specific and Non Specific When a Non Specific EOI command is issued the 8259 will clear the highest ISR bit of those that are set to 1 Non Specific EOI is the normal mode of operation of the 8259 within the processor as the interrupt being serviced currently is the interrupt entered with the interrupt acknowledge When the 8259 is operated in modes which preserve the fully nested structure software can determine which ISR bit to clear by issuing a Specific EOI An ISR bit that is masked will not be cleared by a Non Specific EOI if the 8259 is in the Special Mask Mode An EOI command must be issued for both the master and slave controller Automatic EOI In this mode
326. ne of six modes of operation for the selected counter 000 Out signal on end of count 0 001 Hardware retriggerable one shot 03 01 Undef WO CMS x10 Rate generator divide by n counter x11 Square wave output 100 Software triggered strobe 101 Hardware triggered strobe Binary BCD Countdown Select 00 Undef WO BCS 0 Binary countdown is used The largest possible binary count is 216 1 Binary goded decimal BCD count is used The largest possible BCD count is 10 There are two special commands that can be issued to the counters through this register the Read Back Command and the Counter Latch Command When these commands are chosen several bits within this register are redefined These register formats are described below 11 1 5 1 Read Back Command This is used to determine the count value programmed mode and current states of the OUT pin and Null count flag of the selected counter or counters Status and or count may be latched in any or all of the counters by selecting the counter during the register write The count and status remain latched until read and further latch commands are ignored until the count is read Both count and status of the selected counters may be latched simultaneously by setting both bit 5 and bit 4 to O If both are latched the first read operation from that counter returns the latched status The next one or two reads depending on whether the counter is programmed for one or two byte counts ret
327. nfiguration space and is programmable by the BIOS OS I ndirect Register Access PCI Config Space Each PCI device as defined in Table 39 has a standard PCI header defined consisting of 256 bytes Access to PCI configuration space is through two methods I O indexed and memory mapped PCI Configuration Access I O Indexed Scheme Accesses to configuration space may be performed via the hard coded DWORD 1 0 ports CF8h and CFCh In this mode software uses CF8h as an index register indicating which configuration space to access and CFCh as the data register Accesses to CF8h will be captured internally and stored Upon a read or write access to CFCh a configuration cycle will be generated with the address specified from the data stored in CF8h The format of the address is as shown in Table 40 PCI Configuration PORT CF8h Mapping Field Configuration Cycle Bits 1 O CF8h Cycle Bits Bus Number 31 24 23 16 Device Number 23 19 15 11 Function Number 18 16 10 08 Register Number 07 02 07 02 Bit 31 of offset CF8h must be set for a configuration cycle to be generated PCI Config Access Memory Mapped Scheme A flat 256 MB memory space may also be allocated to perform configuration transactions This is enabled through a special register on the message network This sets a 4 bit base which is compared against bits 31 28 of the incoming memory address If these four bits match the cycle is turned into a config
328. ng i e zero is counted as part of the decrement Refer to Section 11 10 4 2 for details on how to change the value of this register 11 10 3 7 Offset OCh RRO Reload Register O Table 394 OCh RRO Reload Register 0 Size 8 bit Default 00h Power Well Core Access y Offset Start OCh PCI Configuration B D F Offset End OCh IA F Base Address Base 10 Offset OCh Bit Range Default Access Acronym Description 07 00 00h Reserved Reserved Must be programmed to 0 11 10 3 8 Offset ODh RR1 Reload Register 1 Table 395 ODh RR1 Reload Register 1 Size 8 bit Default 00h Power Well Core Access Offset Start ODh PCI Configuration B D F Offset End ODh IA F Base Address Base 10 Offset ODh Bit Range Default Access Acronym Description 07 02 00h Reserved Reserved WDT TI MEOUT This bit is located in the RTC Well and it s value is not lost if the host resets the system It is set to 1 if the host fails to reset the WDT before the 35 bit Down Counter reaches zero for the second 01 Oh RWC TOUT time in a row This bit is cleared by performing the Register Unlocking Sequence followed by a 1 to this bit 0 Normal Default 1 System has become unstable WDT RELOAD To prevent a timeout the host must perform the Register Unlocking Sequence followed by a 1 to this bit o9 Oh RW RELOAD Refer to Section 11 10 4 2 for details on how to change the value of this reg
329. ng the state of IRQO and is programmed for Mode 3 operation The counter produces a square wave with a period equal to the product of the counter period 838 ns and the initial count value The counter loads the initial count value one counter period after software writes the count value to the counter I O address The counter initially asserts IRQO and decrements the count value by two each counter period The counter negates IRQO when the count value reaches 0 It then reloads the initial count value and again decrements the initial count value by two each counter period The counter then asserts IRQO when the count value reaches 0 reloads the initial count value and repeats the cycle alternately asserting and negating IRQO Counter 1 Refresh Request Signal This counter is programmed for Mode 2 operation and impacts the period of the NSC RTS Programming the counter to anything other than Mode 2 results in undefined behavior Counter 2 Speaker Tone This counter provides the speaker tone and is typically programmed for Mode 3 operation Timer I O Registers Timer O Registers Port Register Name Function Default Value Type Counter 0 Interval Time Status Byte Format OXXXXXXXb Read Only oe Counter 0 Counter Access Port Register Undefined Read Write Counter 1 Interval Time Status Byte Format OXXXXXXXb Read Only X Counter 1 Counter Access Port Register Undefined Read Write Counter 2 Interval Time Stat
330. niques used in video codecs The entropy encoding module also performs the motion vector reconstruction using the motion vector predictors After entropy encoding the iDCT coefficients are extracted and inverse scan ordered Then inverse quantization rescaling and AC DC coefficient processing is performed The re scaled coefficients are passed to the Inverse Transform engine for processing The Hadamard transform is also supported and performed The inverse transformed data is connected to the output port of entropy coding module which provides the residual data to the motion compensation module Intel Atom Processor E6xx Series Datasheet 81 m e n tel Graphics Video and Display 7 4 1 1 7 4 1 2 7 4 1 3 Motion Compensation The entropy encoder or host can write a series of commands to define the type of motion predication used The motion predicated data is then combined with residual data and the resulting reconstructed data is passed to the de blocker The Motion Compensation module is made up of four sub modules The Module Control Unit module controls the overall motion compensation operation It parses the command stream to detect errors in the commands sent and extracts control parameters for use in later parts of the processing pipeline The Module Control Unit also accepts residual data either direct from VEC or by a system register and re orders the frame field format to match the predicted tile forma
331. nses from the codecs are not accepted 1 Unsolicited response from the codecs are accepted by the controller and placed into the Response Input Ring Buffer 07 02 0 RO RSVD Reserved Flush Control Writing a 1 to this bit initiates a flush When the flush completion is received by the controller hardware sets the Flush Status bit and clears this Flush Control bit Before a flush cycle is initiated the DMA Position Buffer must be programmed with a valid memory address by software but the DMA Position Buffer bit O need not be set to enable 01 0 RW FCNTRL the position reporting mechanism Also all streams must be stopped the associated RUN bit must be 0 When the flush is initiated the controller will flush pipelines to memory to guarantee that the hardware is ready to transition to a D3 state Setting this bit is not a critical step in the power state transition if the content of the FIFOs is not critical Intel Atom Processor E6xx Series Datasheet 162 Intel High Definition Audio D27 FO I n tel Table 231 O8h GCTL Global Control Sheet 2 of 2 Size 32 bit Default 0000 0000h Power Well Core Access i C Offset Start 08h PCI Configuration B D F 0 27 0 Offset End OBh Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description Controller Reset 0 Writing a 0 to this bit causes the Intel HD AudioP controller to be reset All state machines FIFO s and non resu
332. nterface D31 FO Note By default the LPC clocks are only active when LPC bus transfers occur Because of this behavior LPC clocks must be routed directly to the bus devices they cannot go through a clock buffer or other circuit that could delay the signal going to the end device 10 2 PCI Configuration Registers Note Address locations that are not shown should be treated as Reserved Table 275 LPC Interface PCI Register Address Map Offset Mnemonic Register Name Default Type 00h 03h ID Identifiers 81868086h RO 04h 05h CMD Device Command 0003h RO 06h 07h STS Device Status 0000h RO O1h for B 0 e E stepping 08h RID Revision Identification 02h for B 1 RO stepping 09h OBh cc Class Codes 060100h RO OEh HDTYPE Header Type 80h RO 2Ch 2Fh ss Subsystem Identifiers 00000000h R WO 40h 43h SMBA SMBus Base Address 00000000h RO R W 44h 47h GBA GPIO Base Address 00000000h R W RO 48h 4Bh PM1BLK PM1_BLK Base Address 00000000h RO R W 4Ch 4Fh GPEOBLK GPEO_BLK Base Address 00000000h RO R W 54h 57h LPCS LPC Clock Strength Control See description RO R W 58h 5Bh ACTL ACPI Control 00000003h RO R W 5Ch 5Fh MC Miscellaneous Control 00000000h RO R W 60h 67h PxRC PIRQ A H Routing Control 80h RO R W 68h 6Bhh SCNT Serial IRQ Control 00h R W RO 84h 87h WDTBA WDT Base Address 00000000h R W RO DOh D3h FS FWH ID Select 00112233h RO R W D4h D
333. nterrupt Enable CCE is not supported Intel Atom Processor E6xx Series Datasheet 127 m e n tel PCI Express Table 159 Offset 58h SLCTL Slot Control Sheet 2 of 2 Size 16 bit Default 0000h Power Well Core Access e TS Offset Start 58h PCI Configuration B D F 0 23 26 0 Offset End 59h Bit Range Default Access Acronym Description Presence Detect Changed Enable When set enables the generation 03 Ob RW PDE of a hot plug interrupt or wake message when the presence detect logic changes state MRL Sensor Changed Enable MSE is not supported but it is 02 Ob RO MSE read write for ease of implementation and to easily draft off of the PCI Express specification Power Fault Detected Enable PFE is not supported but is it is 01 Ob RW PFE read write for ease of implementation and to easily draft off of the PCI Express specification Attention Button Pressed Enable ABE is not supported but it is 00 Ob RW ABE read write for ease of implementation and to easily draft off of the PCI Express specification 8 2 2 11 SLSTS Slot Status Table 160 Offset 5Ah SLSTS Slot Status Size 16 bit Default 0000h Power Well Core Access e Ds 0292296 Offset Start 5Ah PCI Configuration B D F 0 23 26 0 Offset End 58h Bit Range Default Access Acronym Description 15 09 0 RO RSVD Reserved Link Active State Changed This bit is set wh
334. nterrupts Capability ID and Control Register Sheet 1 of 2 Size 32 bit Default 00000005h Power Well Core Access D F 0 2 Offset Start 90h PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 24h Bit Range Default Access Acronym Description 31 24 00h RO RESERVED Reserved 23 0 RO OE CAPABLE C64 32 bit capable only Intel Atom Processor E6xx Series Datasheet 97 intel Graphics Video and Display Table 91 90h GVD MSI_CAPID Message Signaled Interrupts Capability I D and Control Register Sheet 2 of 2 Size 32 bit Default 00000005h Power Well Core Access DEFE 0 2 Offset Start 90h PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 24h Bit Range Default Access Acronym Description MULTIPLE MES MME This field is RW for software compatibility but only a single 22 20 000b RW SAGE ENABLE message is ever generated 19 17 000b RO CAGE CAPABLE MMC This device is only single message capable MSIE If set MSI is enabled and traditional interrupts are not used to generate interrupts PCICMDSTS BME must be set for an MSI to be generated When 0 blocks the sending of a MSI interrupt and permits the sending of 16 Ob RW MSI_ENABLE a Message bus interrupt The interrupt status is not blocked from being re
335. nts on page 30 e 403 Thermal Design Power on page 276 e 405 Operating Condition Power Supply and Reference DC Characteristics on e 406 Active Signal DC Characteristics on page 278 Added missing information to register tables in Chapter 7 0 Graphics Video and Display Chapter 11 0 ACPI Devices Intel Atom Processor E6xx Series Datasheet 21 Revision History Date Revision Description Updated Table 2 Intel Atom Processor E6xx Series SKU for Different Segments on page 30 Updated Table 15 Added an additional step in WDT mode users need to program the preload value 1 register to all 0 s Added Overshoot Undershoot specs Updated Table 34 Intel Atom Processor E6xx Series Clock Domains on page 57 October 2010 002 Updated Section 5 3 System Memory Map on page 60 Corrected PCI E port number Section 8 1 Functional Description on page 131 Changed PCI Express G to PCI Express removed G Changed SDVO and Ref Clock Specs Added Premium SKU info Changed DC Characteristics Voltage Supply tolerance Changed SMB CLK specs September 2010 001 Initial release 88 Intel Atom Processor E6xx Series Datasheet 22 Introduction 1 0 Figure 1 Introduction intel The Intel Atom Processor E6xx Series is the next generation Intel architecture 1A CPU for the small form factor ultra low power embedded segments based on a new archite
336. nym Description LBPC Scratch Trigger 3 When written triggers an interrupt when LBEE is enabled in Pipe B Status register and the Display B Event is enabled in 31 24 N A RW LST3 ER and unmasked in IMR etc If written as part of a 16 bit or 32 bit write only one interrupt is generated in common 23 16 N A RW LST2 LBPC Scratch Trigger 2 Same definition as LST3 15 08 N A RW STA LBPC Scratch Trigger 1 Same definition as LST3 Legacy Backlight Brightness The value of zero is the lowest brightness setting and 255 is the brightest If field LBES is written as part of a 16 bit word or 32 bit dword write to LBB this will cause a flag to be set LBES in the PIPEBSTATUS register and cause an interrupt if Backlight event in the PIPEBSTATUS register and cause an interrupt if Backlight Event LBEE and Display B Event is enabled by software If field LBES is written as a one byte write to LBB i e if only least significant byte of LBB is written no flag or interrupt will be generated 07 00 N A RW LBES 88 Intel Atom Processor E6xx Series Datasheet 110 PCI Express 8 0 8 1 8 1 1 Table 125 8 1 2 8 1 2 1 8 1 2 2 8 1 2 3 intel PCI Express Functional Description There are four PCI Express root ports available in the Intel Atom Processor E6xx Series They reside in device 23 24 25 and 26 and all take function O Port 0 is device 23 Port 1 is device
337. nym Description Counter Port Each counter port address is used to program the 16 bit Count Register The order of programming either LSB only MSB only or 07 00 Undef RW LSB then MSB is defined with the Interval Counter Control Register at t port 43h The counter port is also used to read the current count from the Count Register and return the status of the counter programming following a Read Back Command 11 1 6 Timer Programming The counter timers are programmed in the following fashion 1 Write a control word to select a counter 2 Write an initial count for that counter Intel Atom Processor E6xx Series Datasheet 204 ACPI Devices 11 1 7 11 1 7 1 11 1 7 2 intel 3 Load the least and or most significant bytes as required by Control Word bits 5 4 of the 16 bit counter 4 Repeat with other counters Only two conventions need to be observed when programming the counters First for each counter the control word must be written before the initial count is written Second the initial count must follow the count format specified in the control word least significant byte only most significant byte only or least significant byte and then most significant byte A new initial count may be written to a counter at any time without affecting the counter s programmed mode Counting will be affected as described in the mode definitions The new count must follow the programmed count format If a counte
338. o 08 Ob RWO SI a slot Slot support is platform specific The BIOS programs this field and it is maintained until a platform reset 07 04 4h RO DT Device Port Type This indicates this is a PCI Express root port 03 00 1h RO CV Capability Version This indicates PCI Express 1 0a 8 2 2 3 DCAP Device Capabilities Table 152 Offset 44h DCAP Device Capabilities Sheet 1 of 2 Size 32 bit Default 00008FCOh Power Well Core Access e e A Offset Start 44h PCI Configuration B D F 0 23 26 0 Offset End 47h Bit Range Default Access Acronym Description 31 28 Oh RO RSVD Reserved 27 26 00b RO CSPS Captured Slot Power Limit Scale Not supported 25 18 Oh RO CSPV Captured Slot Power Limit Value Not supported 17 16 00b RO RSVD Reserved Role based Error Reporting Indicates that this device implements the 15 1b RO RBER functionality defined in the Error Reporting ECN for the PCI Express 1 0a specification Power Indicator Present This indicates that no power indicator is 14 Ob RO RIR present on the root port Attention I ndicator Present This indicates that no attention indicator 13 0b RO Alp is present on the root port Attention Button Present This indicates that no attention button is 12 0b RO ABR present on the root port Intel Atom Processor E6xx Series Datasheet 123 m e n tel PCI Express Table 152 Offset 44h DCAP Device Capabilities Sheet 2 of 2 Size 32 bit
339. o o o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a OO0O0000000J000000000 0 00 00 0000000000000 0 200 0 9 0 910 9 Ge 9006009000060 0960000600 0 0 9 e O OO 00000000000 0000 000000000 000000000 o 0 0 00000 0l000000000 GH 000000000 000000000 00000000 0 0 00000000 O00 0 0 OO O OQ OO O O OO OO O ia z 90000000 0 o 00000000 H 000000000 000000000 o0000oooooojoooooooo00 000000000 000000000 Es O OO 00000 0 000000000 oOo 000 00 00 000000000 00000000 OJO 00 0 0 0 0 0 0 4o00 0 0 0 0 0 0 0 0 0 00 0 0 0 0 1 Bailen een OO d OBS oOo o Oe Oe T Y 4 zm n T tme CP SC e Ny g g a 10 of g H 3 DU 3 mall aw 611193 PETI 2 9 L Intel Atom Processor E6xx Series Datasheet 283 Ballout and Package Information ntel Ballout Definition and Signal Locations 14 2 Figure 12 provides the ballout as viewed from the top of the package Table 407 lists the ballout alphabetically by signal name Intel Atom Processor E6xx Series Package Ball Pattern Figure 12 lt qo ee Om ch O 0 oO o0 EEN EEN DID D DID OO D NI OO OO OOO 0 0 00000 0 OO OOOO O90 0000 00 0000 0 COD 0 9 OO O00 0 OOO O00 0 OO 0 OOO OD OO OOOO OOO OO oO Oo OO OO OO OO OD OD OO 000 0 0 0 0 D OO OO OO OO OO OO 0 0 OD 8 OO OO OO OD OO OD OO OO 8 OO OO COCO OOOO OO OO OO Oo OO CDD OO OO OO OD CDD OO OO OO OO OO OD OO OO OO OO OD CO 8 OO O00 00 OO 0 OO 00 DO 0 0 0 80 OO OO OD OO OO OO CO OO OO CO OQ OQ OO OO O
340. ocessor E6xx Series Interface DDC_CLK 4 GPIO_SUS 3 DDC DATA 4 GPIO SUS 4 VDDEN lt GPIO SUS 0 BKLTEN lt GPIO SUS 1 BKLTCTL lt GPIO SUS 2 SDVO Digital Display Port Display Pipe B is configured to use the SDVO port The SDVO port can support a variety of display types VGA LVDS DVI TV Out etc by an external SDVO device SDVO devices translate SDVO protocol and timings to the desired display format and timings Intel Atom Processor E6xx Series Datasheet 88 Graphics Video and Display intel 7 5 2 4 7 5 2 4 1 7 5 2 4 2 7 5 2 4 3 7 6 A maximum pixel clock of 160 MHz is supported on the SDVO interface SDVO DVI HDMI DVI and HDMI a 3 3 V interface standard supporting the TMDS protocol is a prime candidate for SDVO The Intel Atom Processor E6xx Series provides an unscaled mode where the display data is centered within the attached display area Monitor Hot Plug functionality is supported SDVO LVDS The Intel Atom Processor E6xx Series can use the SDVO port to drive an LVDS transmitter Flat Panel is a fixed resolution display The processor supports panel fitting in the transmitter receiver or an external device but has no native panel fitting capabilities The processor provides an unscaled mode where the display data is centered within the attached display area Scaling in the LVDS transmitter through the SDVO stall input pair is also supported SDVO TV Out
341. ocessor E6xx Series Datasheet 132 PCI Express 8 2 5 1 MPC Miscellaneous Port Configuration Table 172 Offset D8h MPC Miscellaneous Port Configuration Size 32 bit Default 00110000h Power Well Core Access Offset Start D8h PCI Configuration B D F 0 23 26 0 Offset End DBh Bit Range Default Access Acronym Description Power Management SCI Enable This enables SCI for power 31 0 RW PMCE management events 30 0 RW HPCE Hot Plug SCI Enable This enables SCI for hot plug events 29 0 RW LHO Link Hold Off When set the port will not take any TLP It is used during loopback mode to fill the downstream queue Address Translator Enable This enables address translation via AT 28 0 RW ATE during loopback mode 27 21 0000000 RO RSVD Reserved 20 18 100 RW UCEL Unique Clock Exit Latency LOs Exit Latency when LCAP CCC is cleared 172 15 010 RW CCEL Common Clock Exit Latency LOs Exit Latency when LCAP CCC is set 14 12 000 RW RSVD Reserved Address Translator During loopback these bits are XORd with bits 11 08 0 RW AT 31 28 of the receive address when ATE is set 07 02 000000 RO RSVD Reserved Hot Plug SMI Enable This enables the port to generate SMI for hot 01 0 RW HPME plug events 00 0 RW PMME Power Management SMI Enable This enables the port to generate SMI for power management events Intel Atom Processor E6xx Series Datasheet 133 m e
342. ogrammable microcontroller with capabilities specifically suited for efficient processing of graphics geometries vertex shading graphics pixels pixel shading and general purpose video and image processing programs In addition to data processing operations the unified shader engine has a rich set of program control functions permitting complex branches subroutine calls tests etc for run time program execution The unified shader core also has a task and thread manager which tries to maintain maximum performance utilization by using a 16 deep task queue to keep the 16 threads full The unified store contains 16 banks of 128 registers These 32 bit registers contain all temporary and output data as well as attribute information The store employs features which reduce data collisions such as data forwarding pre fetching of a source argument from the subsequent instruction It also contains a write back queue Like the register store the arithmetic logic unit ALU pipelines are 32 bits wide For floating point instructions these correlate to IEEE floating point values However for integer instructions they can be considered as one 32 bit value two 16 bit values or Intel Atom Processor E6xx Series Datasheet 78 m e Graphics Video and Display n tel 7 2 6 7 3 7 3 1 7 3 1 1 four 8 bit values When considered as four 8 bit values the integer unit effectively acts like a four way SIMD ALU performing four o
343. ol of the DRAM devices There is one M_CKE per rank S3 Firewall Enable DDR in self refresh enable signal M_SRFWEN CMOS1 8 SUS Should be connected to VCC180SR with an external pull up resistor o Chip Select These signals determine whether a M_CSB 1 0 CMOS1 8 Core command is valid in a given cycle for the devices i connected to it There is one M CSB for each rank o Row Address Strobe active low This signal is used M RASB Core with M CASB and M WEB along with M CSB to define CMOS1 8 commands M CASB O Core Column Address Strobe active low This signal is used CMOS1 8 with M RASB M WEB and M CSB to define commands M WEB O Core Write Enable active low Used with M_CASB M_RASB CMOS1 8 and M_CSB to define commands o Bank Select active high Defines which banks are being M_BS 2 0 CMOS1 8 Core addressed within each rank Some call this Bank Address M_BA O Multiplexed Address Provides multiplexed row and M_MA 14 0 CMOS1 8 Core column address to memory 1 0 i M DQI 31 0 CMOS1 8 Core Data Lines M DQ signals interface to the DRAM data bus Data Strobes These signals are used during writes driven by the processor offset so as to be centered in the data phase During reads these signals are driven by memory devices edge aligned with data The following list 1 0 matches the data strobe with the data bytes M_DQS 3 0 Core CMOS1 8 M DQS 3 matches M DQ 31 24 M DQS 2 matches M DQ 2
344. oller will break it into multiple 8 bit transfers until the request is satisfied If the cycle is not claimed by any peripheral and subsequently aborted the LPC Controller will return a value of all 1 s to the processor Intel Trusted Platform Module 1 2 Support The LPC interface supports accessing Intel Trusted Platform Module Intel TPM 1 2 devices by LPC Intel TPM START encoding Memory addresses within the range FED40000h to FED4BFFFh will be accepted by the LPC bridge and sent on LPC as Intel TPME special cycles No additional checking of the memory cycle is performed FWH Cycle Notes If the LPC controller receives any SYNC returned from the device other than short wait 0101 long wait 0110 or ready 0000 when running a FWH cycle indeterminate results may occur A FWH device is not allowed to assert an Error SYNC The usage of FWH will not be validated or supported LPC Output Clocks The processor provides three output clocks to drive external LPC devices that may require a PCI like clock 33 MHz The LPC output clocks operate at 1 4th the frequency of H CLKI N P N LPC CLKOUTO is the first clock to be used in the system configuring its drive strength is done by a strapping option on the GPIO4 pin The buffer strengths of LPC_CLKOUT1 and LPC CLKOUT2 default to 2 loads per clock and can be reprogrammed through LPC configuration space Intel Atom Processor E6xx Series Datasheet 187 intel LPC I
345. on Oh Interrupt never toggles 8h 3 90625 ms 1h 3 90625 ms 9h 7 8125 ms 03 00 Undef RW RS 2h 7 8125 ms Ah 15 625 ms 3h 122 070 us Bh 31 25 ms 4h 244 141 us Ch 62 5 ms 5h 488 281 us Dh 125 ms 6h 976 5625us Eh 250 ms 7h 1 953125 ms Fh 500 ms 11 6 3 2 Offset OBh Register B General Configuration This register resides in the RTC well Bits are reset by RSMRST Table 337 OBh Register B General Configuration Size 8 bit Default Power Well RTC Access i m Offset Start OBh PCI Configuration B D F Offset End OBh Bit Range Default Access Acronym Description Update Cycle I nhibit When cleared an update cycle occurs once each 07 Undef RW SET second If set a current update cycle will abort and subsequent update cycles will not occur until SET is returned to zero When set SW may initialize time and calendar bytes safely Periodic I nterrupt Enable When set and C PF is set an interrupt is 06 0 RW RIE generated Alarm Interrupt Enable When set and C AF is set an interrupt is 05 Undef RW AIE generated Update ended Interrupt Enable When set and C UF is set an 04 0 RW UIE interrupt is generated 03 0 RW SQWE Square Wave Enable Not implemented Data Mode When set represents binary representation When cleared 02 Undef RW DM denotes BCD Hour Format When set twenty four hour mode is selected When 01 Undef RW HF clea
346. on Audio requires a system with an appropriate Intel chipset and a motherboard with an appropriate CODEC and the necessary drivers installed System sound quality will vary depending on actual implementation controller CODEC drivers and speakers For more information about Intel HD audio refer to http www intel com x 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 architecture Performance will vary depending on your hardware and software configurations Consult with your system vendor for more information 8 Intel virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain computer system software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor e The original equipment manufacturer must provide Intel Trusted Platform Module Intel TPM functionality which requires an Intel TPM supported BIOS Intel TPM functionality must be initialized and may not be available in all countries 9 For Enhanced Intel SpeedStep Technology see the http processorfinder intel com or contact your Intel representative for more in
347. on in Buffer LPIB will be reset when it reaches this value 31 00 0 RW CBL Software may only write to this register after Global Reset Controller Reset or Stream Reset has occurred This value should only be modified when the RUN bit is 0 Once the RUN bit has been set to enable the engine software must not write to this register until after the next reset is asserted or transfers may be corrupted 9 3 2 1 36 Offset 8Ch ACh CCh ECh ISDOLVI ISD1LVI OSDOLVI OSD1LVI I nput Output Stream Descriptor 0 1 Last Valid I ndex Register Table 261 8Ch ACh CCh ECh I SDOLVI ISD1LVI OSDOLVI OSDILVI Input Output Stream Descriptor 0 1 Last Valid Index Register Sheet 1 of 2 Size 16 bit Default 0000h Power Well Core Access Offset Start gch ACh PCI Configuration B D F 0 27 0 Offset End BON An CDh EDh Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 15 08 0 RO RSVD Reserved Intel Atom Processor E6xx Series Datasheet 177 m n tel Intel High Definition Audio D27 FO Table 261 8Ch ACh CCh ECh ISDOLVI ISD1LVI OSDOLVI OSDILVI Input Output Stream Descriptor 0 1 Last Valid Index Register Sheet 2 of 2 Size 16 bit Default 0000h Power Well Core Access Offset Start 8Ch ACh PCI Configuration B D F 0 27 0 EC ECH id Spa gt Offset End 8Dh ADh CDh EDh Memory Mapped IO BAR
348. on of the next pointer in the 07 00 ODh RO CID Capability Identifier The value of ODh indicates that this is a PCI bridge subsystem vendor capability 8 2 3 2 SVI D Subsystem Vendor I Ds Table 166 Offset 94h SVID Subsystem Vendor IDs Size 32 bit Default 0000h Power Well Core Access PCI Configuration B D F 0 23 26 0 Offset Start 94h Offset End 97h Bit Range Default Access Acronym Description 000000 Subsystem Vendor ID The value in this register matches the value of 31 00 90 RO SVID the S5 register in the LPC bridge 8 2 4 PCI Power Management Capability Table 167 PCI Power Management Capability Start End Symbol Register Name AO Al PMCAP Power Management Capability ID A2 A3 PMC Power Management Capabilities A4 A7 PMCS Power Management Control And Status Intel Atom Processor E6xx Series Datasheet 130 PCI Express 8 2 4 1 PMCAP Power Management Capability ID Table 168 Offset AOh PMCAP Power Management Capability I D Size 16 bit Default 0001h Power Well Core Access NIE Offset Start AOh PCI Configuration B D F 0 23 26 0 Offset End Alh Bit Range Default Access Acronym Description 15 08 00h RO NEXT Next Capability Last item in the list Capability I dentifier The value of 01h indicates
349. on page 36 e 15 Miscellaneous Signals and Clocks on page 39 e 16 General Purpose I O Signals on page 42 e 18 Power and Ground Signals on page 43 e 34 Intel Atom Processor E6xx Series Clock Domains on page 51 e 36 Memory Map on page 55 tion 5 4 2 1 PCI Config Space on page 59 e 71 DRAM Address Decoder on page 73 e 79 08h GVD RI DCC Revision Identification and Class Code on page 92 e 107 Offset 08h RID Revision Identification on page 104 e 108 Offset 09h CC Class Codes on page 104 e 126 PCI Type 1 Bridge Header on page 112 tion 8 1 2 4 SMI SCI Generation on page 112 e 131 Offset 08h RID Revision Identification on page 115 e 177 Intel High Definition Audiob PCI Configuration Registers on page 140 e 182 08h RID Revision Identification Register on page 143 e 275 LPC Interface PCI Register Address Map on page 188 e 279 Offset 08h RID Revision ID on page 189 tion 10 3 4 GPEOBLK GPEO BLK Base Address Register on page 192 tion 11 9 4 1 SPI Pin Level Protocol on page 247 e 368 SPI Pin Interface on page 246 e 371 SPI Cycle Timings on page 249 e 401 Absolute Maximum Ratings on page 274 e 403 Thermal Design Power on page 276 Table 406 Active Signal DC cs on page 278 January 2011 003 Updated Tab Updated Tab Updated Tab page 277 Updated Tab e 2 Intel Atom Processor E6xx Series SKU for Different Segme
350. or the C5 18 0 RW BTCA B Timer Ticks in C4 Same definition as BTC6 but for the C4 17 0 RW BTC3 Wee Timer Ticks in C3 Same definition as BTC6 but for the C3 16 0 RW BTC2 ee Timer Ticks in C2 Same definition as BTC6 but for the C2 15 13 Oh RO Reserved Block Interrupts in C6 When set interrupts will be blocked while 12 0 RW BIC6 the processor is in the C6 state until a timer tick occurs If not set interrupts will not be blocked in the C6 state Blocking may occur for NTT timer ticks if BTC6 is set 11 0 RW BICS Block Interrupts in C5 Same definition as BIC6 but for the C5 state Block Interrupts in C4 Same definition as BIC6 but for the C4 10 0 RW BIC4 state 09 0 RW BIC3 Block Interrupts in C3 Same definition as BIC6 but for the C3 state Block Interrupts in C2 Same definition as BIC6 but for the C2 08 0 RW BIC2 state Bootstrap MEMI D3 Bootstrap for memory controller configuration 1D3 07 Strap RO MEMID3 Defines the number of ranks enabled 1 1 Rank 0 2 Rank Bootstrap MEMI D2 Bootstrap for memory controller configuration 1D2 Defines the memory device densities that the processor is connected to 06 Strap RO MEMID2 MEMID2 MEMID1 11 2Gb 10 1 Gb 01 512 Mb 00 256 Mb Bootstrap MEMID1 Bootstrap for memory controller configuration 1D1 05 Strap RO MEMID1 Defines the memory device densities that the processor is connected to Please refer to MEMID2 Bootstrap MEMI DO Bootstrap for
351. ore Access DE 0 97 Offset Start 2030h PCI Configuration B D F 0 27 0 Offset End 2033h Memory Mapped IO BAR Offset Bit Range Default Access Acronym Description Wall Clock Counter Alias This is an alias of the WALCK register 32 bit counter that is incremented on each link Bit Clock period and rolls over from FFFF_FFFFh to 0000 0000h This counter will roll over to zero with a 31 00 0 RO CounterA period of approximately 179 seconds This counter is enabled while the Bit Clock bit is set to 1 Software uses this counter to synchronize between multiple controllers Will be reset on controller reset Intel Atom Processor E6xx Series Datasheet 185 El n tel Intel High Definition Audio D27 FO 9 3 2 1 49 Offset 2084h 20A4h 2104h 2124h I SDOLPI BA ISDILPI BA OSDOLPI BA OSDILPI BA Input Output Stream Descriptor 0 1 Link Position in Buffer Alias Register Table 274 2084h 20A4h 2104h 2124h ISDOLPI BA ISDILPI BA OSDOLPI BA OSDILPI BA Input Output Stream Descriptor 0 1 Link Position in Buffer Alias Register Size 32 bit Default 0000 0000h Power Well Core Access Offset Start 2084h 20A4h 2104h i i D F 0 27 2124h PCI Configuration B D F 0 27 0 Offset End 2087h 20A7h 2107h 2127h Memory Mapped IO BAR Offset Bit Range Default Access Acronym Description Position This is an alias of the corresponding LPIB register Indicates 31 00 0 RO POS the number of bytes th
352. ore PLL Core Thermal 1 425 15 1 575 V Sensors Voltages 3 j j VCCD180 VCCA180 VCC180 1 8 V Supply Voltage LVDS Digital VCCSFR EXP VCCSFRDPLL Analog DDR 1 0 super filter 1 71 1 8 1 89 V VCCSFRHPLL VCC180SR regulators VMM 1 05 V Supply Voltage 0 9975 1 05 1 1025 V VCC Maximum Overshoot Maximum overshoot voltage for VCC 5D mV VNN Maximum Overshoot Maximum overshoot voltage for VNN 50 mV VCCP33 VCCP33SUS 3 3 V Supply Voltage Legacy IO SDVO VCCPSUS pads Suspend Power supply RTC 3 135 3 3 3 465 V d suspend 3 135 4 3 3 V Supply Voltage RTC well 2 0 3 3 3 465 V icd j battery B1 Stepping mode VCC33RTC 2 755 4 2 9 V Supply Voltage RTC well 2 17 2 9 3 045 V battery BO Stepping mode BO Stepping only does not VCCRTCEXT 1 24 V Supply Voltage RTC well 1 178 1 24 1 302 V apply to B1 stepping Notes 1 Slew Rate for VCC is 8 75 mV us and slew rate for VNN is 10 mV us 2 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Typical AVI D voltage identification range is 0 75 1 15V for VCC excluding VCC C6 VID and 0 75V to 0 9875V for VNN The VID will change due to temperature changes and thermal management event in order to reduce the junction temperature of the part
353. ore thermal sensor and sensor LVDS Analog Supply Voltage Needed for LVDS display Requires a VCCA180 LE separate rail with noise isolation VCCD180 1 8V LVDS UO Supply Voltage Needed for LVDS display DDR2 Self Refresh Supply Voltage Powered during Active VEGEBUS AON Standby and Self Refresh states VCC180 18V DDR2 I O Supply Voltage Required for memory bus accesses Cannot be connected to VCC180SR during Standby or Self Refresh states VCCD 1 05 V Core supply voltage VCCDSUS 1 05 V Core suspend rail VCCP33 3 33 V Legacy I O and SDVO supply voltage VCCP33SUS 3 3 V 3 3 V suspend power supply VCCPSUS 3 3V RTC suspend well voltage supply VCC33RTC 3 3 V RTC well voltage supply Intel Atom Processor E6xx Series Datasheet 43 intel Table 18 Signal Description Power and Ground Signals Sheet 2 of 2 ae Nominal Voltage Description VCCD_DPL 1 05 V DPLL dedicated supply VCCA_PEG 1 05 V Used by PCle and SDVO VCCSFR EXP 1 8 V PCle superfilter regulator VCCSFRDPLL 1 8 V SDVO superfilter regulator VCCSFRHPLL 1 8 V HPLL superfilter regulator VCCQHPLL 1 05 V HPLL quiet supply VCCFHV 1 05 V Can be connected to VCCP VMM 1 05 V Connect to 1 05 V VSS DV Ground pin VCCSENSE Voltage sensing pins voltage regulator must connect feedback lines for VCCDSENSE NA VCC VCCD VNN and VSS to these pins on the package It appears that VNNSENSE random VCC VCCD VNN and VSS bumps were picked for
354. ormats iii ak SEET EA AANER ade a Xe Re XE e Fd ebd n 79 7 341 Encoding Pipeline e oer e pua x ER e Lone m on 79 7 3 1 2 Encode Codec Support 80 7 3 1 3 Encode Specifications Gupported sss 80 74 Mideo Decode i iei eere ree ipee dev e Pile bii e X Ee eod 81 1 4 1 Entropy Coding aoctor te oid i 81 7 4 1 1 Motion Compensation mem ene 82 7 4 1 2 Ree ne EE ER 7 4 1 3 Output Reference Frame Storage Format cccceeeeee tees ee ee eee eee 82 TAA Pixel ForTwo 83 T9 DiSplay MEE 83 7 5 1 Di T Output Stages sica 85 7 5 1 MEI CREME RET 85 7 5 1 gt Display PID S LEE 86 La z Display POS il a 86 BZ LVDS Poli ricas 87 7 5 2 2 LVDS Backlight Control 88 7 5 2 3 SDVO Digital Display Port 0 ce eee eee mmm 88 7 5 2 4 SDVO DVIJHDMI iie da RR REIR EUR EGER need Ra RR EROR CREER E 89 726 CONO EEN 89 7 7 Configuration Registers er AN Seege RENE hate Creer v exe ee ERE Ra ea deni ge Ed 90 7 7 1 D2 FO PCI Configuration Registers mener 90 7 7 2 D3 FO0 PCI Configuration Registers mne 102 7 7 2 1 Offset 00h ID Identifiers ssssssssssseeenm eee teeta 103 7 7 2 2 Offset 04h CMD PCI Command sss ee 103 7 7 2 3 Offset 06h STS PCI Status 104 7 7 2 4 Offset 08h RID Revision Identification sees 104 7 7 2 5 Offset 09h CC Class Codes eect m 104 7 7 2 6 Offset OEh HDR Header Type HH 105 7 7 2 7 Offset 10h MMADR Memory Mapped Base Address
355. orts O1h Port 1 04h reports 02h Port 2 reports 03h Port 3 reports 04h 23 21 Ob RO RSVD Reserved Link Active Reporting Capable This port supports the optional 20 1b RO LARC capability of reporting the DL_Active state of the Data Link Control and Management State Machine 19 Ob RO RSVD Reserved Clock Power Management This indicates that clock power 18 1b RO CPM management is supported 17 15 010b RO EL1 L1 Exit Latency This indicates an exit latency of 2 us to 4 us LOs Exit Latency This indicates an exit latency based on common clock 14 12 100h RO ELO configuration When cleared it uses MPC UCEL When set it uses MPC CCEL Active State Link PM Support This indicates that both LOs and L1 are 11 10 3h RO APMS supported 09 04 Olh RO MLW Maximum Link Width May only be a single lane 03 00 1h RO MLS Maximum Link Speed This indicates that the link speed is 2 5 Gb s Intel Atom Processor E6xx Series Datasheet 125 intel PCI Express 8 2 2 7 LCTL Link Control Table 156 Offset 50h LCTL Link Control Size 16 bit Default 0000h Power Well Core Access e Offset Start 50h PCI Configuration B D F 0 23 26 0 Offset End 51h Bit Range Default Access Acronym Description 15 0 RO RSVD Reserved 07 Ob RW ES Extended Synch When set this forces extended transmission of FTS ordered sets in FTS and extra TS2 at exi
356. ower Well Core Access D F 0 2 Offset Start 1Ch PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 07h Bit Range Default Access Acronym Description BA Set by the OS these bits correspond to address signals 31 19 The GVD will compare the SCL address scldown3 address 31 19 18 or 17 with GTTBAR 31 19 18 or 17 respectively Whether the comparison is 31 19 31 18 or 31 17 depends on the value of MSAC 17 16 If there is a match and MSE 1 and the SCL command is either a MEMRD or 31 19 Oh RW BASE_ADDRESS MEMWR the GVD will select the command i e issue a scldown3_hit The GVD will then issue a memory read write via the LP arbiter RequestGB1 interface with Bunit The address of the read write will be an offset from Page Table Base Address 31 1 defined in MMIO register 02020h M512K This bit is either part of the GTT Base Address RW or part of 18 Ob RWL 512 KB ADDRE the Address Mask RO depending on the value of MSAC UAS If this bit S MASK is used in the address comparison the address space is limited to 256 kB M256K This bit is either part of the GTT Base Address RW or part of 17 Ob RWL 256 KB ADDRE the Address Mask RO depending on the value of MSAC UAS If this bit S MASK is used in the address comparison the address space is limited to 128 kB 16 1 Oh RO RESERVED Reserved 0 Ob RO BASE ADDRESS RTE Indicates a request for memory space Intel Atom Processor
357. pecification 15 8 BOh RO NEXT POINTER Indicates the next item in the capabilities list 7 0 01h RO SEN ES_ CAPID SIG defines this ID is Olh for power management Table 98 D4h GVD PMCS Power Management Control Status Size 32 bit Default 00000000h Power Well Core Access D E 0 2 Offset Start D4h PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 35h Bit Range Default Access Acronym Description 31 2 Mie RO RESERVED Reserved In the processor power management is implemented by writing to 1 0 00b RW POWER STATE control registers in the Punit This field may be programmed by the software driver but no action is taken based on writing to this field Table 99 EOh GVD SWSMISCI Software SMI or SCI Sheet 1 of 2 Size 32 bit Default 00000000h Power Well Core Access e D E 0 2 Offset Start E0h PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 38h Bit Range Default Access Acronym Description 31 16 0000h RO RESERVED Reserved 15 Ob RW WENT SELECT MCS SMI or SCI event select 0 SMI 1 SCI 14 1 0000h RW SOFTWARE_SC Used by driver to communicate information to SBIOS No hardware RATCH BITS functionality Intel Atom Processor E6xx Series Datasheet 100 Graphics Video and Display Table 99 EOh GVD SWSMISCI Softw
358. per memory mapped register e g RELOAD PRELOAD VALUE 1 PRELOAD VALUE 2 Any deviation from the sequence writes to memory mapped registers causes the host to have to restart the sequence When performing register unlocking software must issue the cycles using byte access only Otherwise the unlocking sequence will not work properly The following is an example of how to prevent a timeout 1 Write 80 to offset WDTBA OCh 2 Write 86 to offset WDTBA OCh 3 Write a 1 to RELOAD 8 WDT RELOAD of the Reload Register Any subsequent writes require that this sequence be performed again Intel Atom Processor E6xx Series Datasheet 270 ACPI Devices i n tel 11 10 4 3 Reload Sequence To keep the timer from causing an interrupt or driving GPIO 4 the timer must be updated periodically Other timers refer to updating the timer as kicking the timer The frequency of updates required is dependent on the value of the Preload values To update the timer the Register Unlocking Sequence must be performed followed by writing a 1 to bit 8 at offset BARI OCh within the watchdog timer memory mapped space This sequence of events is referred to as the Reload Sequence 11 10 4 4 Low Power State The Watchdog Timer does not operate when PCICLK is stopped 88 Intel Atom Processor E6xx Series Datasheet 271 l n tel i ACPI Devices Intel Atom Processor E6xx Series Datasheet 272 e Absolute Maximum Ratin
359. perations per clock It is expected that in legacy applications pixel processing will be done on 8 bit integers roughly quadrupling the pixel throughput compared to processing on float formats Multi Level Cache The multi level cache is a three level cache system consisting of two modules the main cache module and a request management and formatting module The request management module also provides Level 0 caching for texture and unified shader core requests The request management module can accept requests from the data scheduler unified shaders and texture modules Arbitration is performed between the three data streams and the cache module also performs any texture decompression that may be required Video Encode The Intel Atom Processor E6xx Series supports full hardware video encode The video encode hardware accelerator improves video capture performance by providing dedicated hardware based acceleration Other benefits are low power consumption low host processor load and high picture quality The processor supports full hardware acceleration of the following video encode Permits 720P30 H 264 BP encode MPEG4 encode and H 263 video conferencing With integrated hardware encoding the host processor only needs to deal with higher level control code functions such as providing the image to encode and processing the video elementary stream The processor supports a standard definition video encoder that has as an in
360. ponding GPIO if enabled as input via RGIO IO n triggered an SMI SCI This will be set if a 0 to 1 transition occurred and RGTPE TE n was set or a 1 to 0 transition 08 00 0 RWC TS occurred and RGTNE TE n was set If both RGTPE TE n and RGTNE TE n are set then this bit will be set on both a 0 to 1 and a 1 to 0 transition This bit will not be set if the GPIO is configured as an output 11 7 3 Theory of Operation 11 7 3 1 Power Wells GPCO GPC4 are in the core well GPRO GPRS are in the resume well 11 7 3 2 SMI and SCI Routing If GPE EN n whether in the core well CGGPE or resume well RGGPE and GPEOE GPIO is set and the GPIO is configured as an input GPEOS GPIO will be set If SMI EN n for both core well CGSMI and resume well RGSMI and SMIE GPIO is set and the GPIO is configured as an input SMIS GPIO will be set 11 7 3 3 Triggering A GPIO whether in the core well or resume well can cause an wake event and SMI SCI on either its rising edge its falling edge or both These are controlled via the CGTPE and CGTNE registers for the core well GPIOs and RGTPE and RGTNE for the resume well GPIOs If the bit corresponding to the GPIO is set the transition will cause a wake event SMI SCI and the corresponding bit in the trigger status register CGTS for core well GPIOs RGTS for resume well GPI Os The event can be cleared by writing a 1 to the status bit position Intel Atom Proc
361. pt Enable If this bit is set the controller will generate an interrupt if the MEI status bit LBAR 4Dh bit 0 is set 9 3 2 1 20 Offset 4Dh CORBSTS CORB Status Register Table 245 4Dh CORBSTS CORB Status Register Size 8 bit Default 0000h Power Well Core Access D F 0 27 Offset Start 4Dh PCI Configuration B D F 0 27 0 Offset End 4Dh Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 07 01 0 RO RSVD Reserved CORB Memory Error Indication f this status bit is set the controller has detected an error in the pathway between the controller and 00 0 RW CMEI memory This may be an ECC bit error or any other type of detectable data error which renders the command data fetched invalid Software can clear this bit by writing a 1 to it However this type of error leaves the audio subsystem in an unviable state and typically requires a CRST B Intel Atom Processor E6xx Series Datasheet 169 intel Intel High Definition Audio D27 FO 9 3 2 1 21 Offset 4Eh CORBSIZE CORB Size Register Table 246 4Eh CORBSIZE CORB Size Register Size 8 bit Default 42h Power Well Core Access e VERS ten Offset Start 4Eh PCI Configuration B D F 0 27 0 Offset End 4Eh Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description P CORB Size Capability
362. ption 15 00 0 RW MD Message Data Data used for MSI Message Intel Atom Processor E6xx Series Datasheet 150 Intel High Definition Audio D27 FO intel 9 3 1 27 Offset 70h PCIE CAPID PCI Express Capability I dentifiers Register Table 204 70h PCIE CAPID PCI Express Capability I dentifiers Register Size 16 bit Default 10h Power Well Core Access D F 0 27 Offset Start 70h PCI Configuration B D F 0 27 0 Offset End 71h Bit Range Default Access Acronym Description Next Capability Defaults to 60h the address of the next capability 60h 00 structure in the list 15 08 h RO NEXT However if the FD MD bit is set the MSI capability will be disabled and this register will report 00h indicating this capability is the last capability in the list 07 00 10h RO CAP Cap ID Indicates that this pointer is a PCI Express capability structure 9 3 1 28 Offset 72h PCI ECAP PCI Express Capabilities Register Table 205 72h PCIECAP PCI Express Capabilities Register Size 16 bit Default 0091h Power Well Core Access D EO 27 Offset Start 72h PCI Configuration B D F 0 27 0 Offset End 73h Bit Range Default Access Acronym Description 15 08 00 RO RO Reserved Device Port Type Indicates that this is a Root Complex Integrated 07 04 1001 RO Endpoint Device
363. put a series of frames which are encoded to produce an elementary bit stream This section describes the top level interactions between all modules contained in encode hardware Supported Input Formats The following input formats are supported for the video input planar Luma and planar or interleaved Chroma 4 2 0 The following is a list of the formats YUV IMC2 Planar Pixel Format YUV YV12 Planar Pixel Format YUV PL8 Planar Pixel Format YUV PL12 Planar Pixel Format The first stage is to fetch the data in its original format UYVYUYVYUYVYUYVY and then translate this to the following format UVUVUVUV YYYYYYYY Only the Chroma data is TDMA d back to the EI OB and then TDMA d from the EI OB back into the ESB again to de interleave the chroma components Encoding Pipeline In general the encoding process is pipelined into a number of stages For MPEG 4 H 263 H 264 encoding the data is processed in macroblocks with a minimum of interaction from the embedded controller within each processing stage Intel Atom Processor E6xx Series Datasheet 79 intel 7 3 1 2 Table 72 7 3 1 3 Graphics Video and Display Encode Codec Support The Intel Atom Processor E6xx Series supports the following profiles and levels as shown in Table 72 Encode Profiles and Levels of Support Standard Profile Maximum Bit Rate Typical Picture and Frame Rate bps
364. r is in the RTC well and is used for general configuration of the RTC functions None of the bits are affected by RSMRST or any other reset signal Table 336 OAh Register A Sheet 1 of 2 Size 8 bit Default Power Well RTC Access Pi Offset Start 0Ah PCI Configuration B D F Offset End OAh Bit Range Default Access Acronym Description Update in progress When set an update is in progress When cleared 07 Undef RW UIP the update cycle will not start for at least 488 us The time calendar and alarm information in RAM is always available when this bit is cleared Division Chain Select Controls the divider chain for the oscillator and are not affected by RSMRST or any other reset signal Bits Function Bits Function Oh Invalid 4n Bypass 10 stages test mode only 06 04 Undef RW DV B Te ypass 15 stages 1h Invalid 5h test mode only 2h Normal Operation 6h Divider Reset 3h Bypass 5 stages 7h Divider Reset test mode only Intel Atom Processor E6xx Series Datasheet 231 intel ACPI Devices Table 336 OAh Register A Sheet 2 of 2 Size 8 bit Default Power Well RTC TUBES PCI Configuration B D F pide aie Hn Bit Range Default Access Acronym Description Rate Select Selects one of 13 taps of the 15 stage divider chain The selected tap can generate a periodic interrupt if B PIE bit is set Otherwise this tap will set C PF Bits Function Bits Functi
365. r is programmed to read write two byte counts the following precaution applies A program must not transfer control between writing the first and second byte to another routine which also writes into that same counter Otherwise the counter will be loaded with an incorrect count The Control Word Register at port 43h controls the operation of all three counters Several commands are available Control Word Command Specifies which counter to read or write the operating mode and the count format binary or BCD Counter Latch Command Latches the current count so that it can be read by the system The countdown process continues Read Back Command Reads the count value programmed mode the current state of the OUT pins and the state of the Null Count Flag of the selected counter Reading from the Interval Timer It is often desirable to read the value of a counter without disturbing the count in progress There are three methods for reading the counters a simple read operation counter Latch Command and the Read Back Command Each is explained below With the simple read and counter latch command methods the count must be read according to the programmed format specifically if the counter is programmed for two byte counts two bytes must be read The two bytes do not have to be read one right after the other Read write or programming operations for other counters may be inserted between them Simple Read The first met
366. r rr rr rra rr rr see re mememe sisse seas 72 DRAM Address Decodet ioter a EAR NEE E KEEA OE hl e aie rin rbd 73 Encode Profiles and Levels of Support 80 Hardware Accelerated Video Decoding Support 81 Pixel Format for the Luma Y BDlane HH emere enne nen nnn 83 Pixel Formats for the Cr Cb V U Dlane HH He nee ehe nene 83 PCI Header for D2 ass vids or ree stipe exe ters dU ELI RI EE EUR AE EES 90 00h GVD ID D2 PCI Device and Vendor ID Register 91 04h GVD PCICMDSTS PCI Command and Status Register 91 08h GVD RIDCC Revision Identification and Class Code 92 OCh GVD HDR Header Type 0 cece cece ee eee ne ener ne nee erem te nee eese ens 92 10h GVD MMADR Memory Mapped Address Range ee eee eeeeeeeeene nanan 93 14h GVD GFX_IOBAR I O Base Address mme nen 93 18h GVD GMADR Graphics Memory Address Range 94 1Ch GVD GTTADR Graphics Translation Table Address Range teens eaeae 94 2Ch GVD SSID Subsystem Identifiers 0 ee erent ened 95 34h GVD CAPPOINT Capabilities Pointer sss 95 3CM GVDUNTR a ele suene t huh tein teo er anten unctio Dudas edid e Ro tenet idit 95 50h GVD MGGC Graphics Control 96 5Ch GVD BSM Base of Stolen Memory sssssssssssrsssrssrrnsrrnttrrn memes eene 97 60h GVD MSAC Multi Size Aperture Control 97 90h GVD MSI CAPID Message Signaled Interrupts Capability ID and Control Register 97 94h GVD MA Message Address 98 98h GVD MD M
367. r secondary display Cursor Plane The cursor plane is one of the simplest display planes With a few exceptions the cursor plane supports sizes of 64 x 64 128 x 128 and 256 x 256 fixed Z order top In legacy modes cursor can cause the display data below it to be inverted VGA Plane VGA mode provides compatibility for pre existing software that set the display mode using the VGA CRTC registers VGA Timings are generated based on the VGA register values the hi resolution timing generator registers are not used Intel Atom Processor E6xx Series Datasheet 85 m e n tel Graphics Video and Display Note 7 5 1 2 Note 7 5 2 The Intel Atom Processor E6xx Series has limited support for a VGA Plane The VGA plane is suitable for usages such as BIOS boot screens pre OS splash screens etc Other usages of the VGA plane like DOS based games for example are not supported Display Pipes The display consists of two pipes Display Pipe A Display Pipe B A pipe consists of a set of combined planes and a timing generator The timing generators provide timing information for each of the display pipes The Intel Atom Processor E6xx Series has two independent display pipes that can allow for support of two independent display streams A port is the destination for the result of the pipe Pipe A can operate in a single wide mode The Clock Generator Units DPLLA provides a stable frequency for driving d
368. r the same to the controller as it is not cognizant of the surprise removal 1 In the docked quiescent state the Dock Attach DCKCTL DA bit and the Dock Mate DCKSTS DM bit are both asserted The HDA DOCK EN B signal is asserted and HDA DOCKRST B is de asserted 2 The user initiates an undock event through the GUI interface or by pushing a button This mechanism is outside the scope of this section of the document Either way ACPI BIOS software will be invoked to manage the undock process 3 ACPI BIOS will call the The Intel HD AudioP Bus Driver driver software in order to halt the stream to the dock codec s prior to electrical undocking If the Intel HD AudioP Bus Driver is not capable of halting the stream to the docked codec ACPI BIOS will initiate the hardware undocking sequence as described in the next step while the dock stream is still running From this standpoint the result is similar to the surprise undock scenario where an audio glitch may occur to the docked codec s during the undock process 4 The ACPI BIOS initiates the hardware undocking sequence by writing a O to the DCKCTL DA bit 5 The Intel HD AudioP controller asserts HDA DOCKRST B HDA DOCKRST B assertion shall be synchronous to HDA CLK HDA DOCKRST B assertion will occur a minimum of 4 HDA CLKs after the completion of the current frame Note that the Intel HD AudioP link reset specification requirement that the last Frame sync be skipped will not be met
369. rammable the processor supports flash devices that have different opcodes for enabling writes to the data space vs status register RW ACS Atomic Cycle Sequence When set to 1 along with the SCGO assertion the processor will execute a sequence of commands on the SPI interface The sequence is composed of Atomic Sequence Prefix Command 8 bit opcode only Primary Command specified by software can include address and data Polling the Flash Status Register opcode 05h until bit O becomes Ob The SPI Cycle in Progress bit remains set and the Cycle Done Status bit in Offset 00h SPIS SPI Status register remains unset until the Busy bit in the Flash Status Register returns 0 RWS SCGO SPI Cycle Go This bit always returns 0 on reads However a write to this register with a 1 in this bit starts the SPI cycle defined by the other bits of this register The SPI Cycle in Progress SCIP bit in Offset 00h SPIS SPI Status register gets set by this action Hardware must ignore writes to this bit while the SPI Cycle In Progress bit is set Hardware allows other bits in this register to be programmed for the same transaction when writing this bit to 1 This saves an additional memory write RSVD Reserved Intel Atom Processor E6xx Series Datasheet 251 intel ACPI Devices 11 9 5 4 Offset 04h SPIA SPI Address Table 375 04h SPIA SPI Address Size 32 bit Default OOX
370. ransferring data If the processor loses arbitration it sets HSTS BE and if enabled generates an interrupt or SMI The CPU is responsible for restarting the transaction Bus Timings The SMBus runs at between 10 100 kHz The processor SMBus runs off of the backbone clock SMBus Timings Timing Min AC Spec Name tiow 4 7 us Clock low period tuiGH 4 0 us Clock high period tsu DAT 250 ns Data setup to rising SMBCLK tub DAT Ons Data hold from falling SMBCLK tHD STA 4 0 us Repeat Start Condition generated from rising SMBCLK tsu STA 4 7 us First clock fall from start condition tsu sto 4 0 us Last clock rising edge to last data rising edge stop condition tgur 4 7 us Time between consecutive transactions The Min AC column indicates the minimum times required by the SMBus specification The processor tolerates these timings When the processor is sending address command or data bytes it will drive data relative to the clock it is also driving It will not start toggling the clock until the start or stop condition meets proper setup and hold The processor will also guarantee minimum time between SMBus transactions as a master Clock Stretching Devices may stretch the low time of the clock When the processor attempts to release the clock allowing the clock to go high the clock will remain low for an extended period of time The processor monitors SMBCLK after it releases the bus to determine
371. ream 0 Repeat Count Reset 9 3 2 1 43 Offset 1004h INRC Input Stream Repeat Count Register Table 268 1004h INRC Input Stream Repeat Count Register Size 32 bit Default 0000 0000h Power Well Core Access PCI Configuration B D F 0 27 0 pried cate nun Memory Mapped IO BAR Offset Bit Range Default Access Acronym Description 31 16 00h RO RSVD Reserved 15 08 ooh RO ee JEE 07 00 00h RO INORC Input Stream O Repeat Count This field reports the number of times a buffer descriptor list has been repeated 9 3 2 1 44 Offset 1008h OUTRC Output Stream Repeat Count Register Table 269 1008h OUTRC Output Stream Repeat Count Register Size 32 bit Default 0000_0000h Power Well Core oes PCI Configuration B D F 0 27 0 ta ee Memory Mapped IO BAR Offset Bit Range Default Access Acronym Description 31 16 00h RO RSVD Reserved 15 08 ooh RO T 07 00 00h RO OUTORC Output Stream 0 Repeat Count This field reports the number of times a buffer descriptor list has been repeated Intel Atom Processor E6xx Series Datasheet 183 intel Intel High Definition Audio D27 FO 9 3 2 1 45 Offset 100Ch FIFOTRK FIFO Tracking Register Table 270 100Ch FIFOTRK FIFO Tracking Register Size 32 bit Default 000F F800h Power Well Core Access D EO 27 Offse
372. red twelve hour mode is selected In twelve hour mode the seventh bit represents AM cleared and PM set 00 Undef RW DSE Daylight Savings Enable Not implemented 11 6 3 3 Offset OCh Register C Flag Register RTC Well All bits in this register are cleared when this register is read This register is cleared upon RSMRST Intel Atom Processor E6xx Series Datasheet 232 ACPI Devices I n tel Table 338 OCh Register C Flag Register Size 8 bit Default Power Well RTC Access e Offset Start OCh PCI Configuration B D F Offset End OCH Bit Range Default Access Acronym Description Interrupt Request Flag This bit is an AND of the flag with its 07 0 RO IRQF corresponding interrupt enable in register B and causes the RTC Interrupt to be asserted 06 0 RO PF Periodic nterrupt Flag Set when the tap as specified by A RS is one 05 Undef RO AF Alarm Flag Set after all Alarm values match the current time 04 0 RO UF pede ended Flag Set immediately following an update cycle for each 03 00 0 RO RSVD Reserved 11 6 3 4 Offset ODh Register D Flag Register RTC Well Table 339 ODh Register D Flag Register RTC Well Size 8 bit Default Power Well RTC Access PX Offset Start ODh PCI Configuration B D F Offset End 0Dh Bit Range Default Access Acronym Description 07 1 RW VRT Valid RAM and Time Bit This bit should al
373. reload register into the WDT s 35 bit Down Counter and starts counting down If the host fails to reload the WDT before the timeout the WDT drives the GPIO 4 pin high and sets the timeout bit WDT TI MEOUT This bit indicates that the System has become unstable The GPIO 4 pin is held high until the system is Reset or the WDT times out again Depends on TOUT CNF The process of reloading the WDT involves the following sequence of writes 1 Write 80 to offset WDTBA OCh 2 Write 86 to offset WDTBA OCh 3 Write 1 to WDT RELOAD in Reload Register The same process is used for setting the values in the preload registers The only difference exists in step 3 Instead of writing a 1 to the WDT RELOAD you write the desired preload value into the corresponding Preload register This value is not loaded into the 35 bit down counter until the next time the WDT reenters the stage For example if Preload Value 2 is changed it is not loaded into the 35 bit down counter until the next time the WDT enters the second stage GPIO 4 is used for WDT output WDT TOUT when it is not enabled for GPIO CGEN 4 0 Features Selectable Prescaler approximately 1 MHz 1 us to 1 s and approximately 1 KHz 1 ms to 10 min 33 MHz Clock 30 ns Clock Ticks WDT Mode Drives GPIO 4 high or inverts the previous value Used only after first timeout occurs Status bit preserved in RTC well for possible error detection and correction Drives GP
374. request 31 20 000h RW EN MEMORY address 19 5 from the vrdunit or vrhunit the GVD appends the base address BSM 31 20 to form the full physical address to send to the Bunit 19 0 00000h RO RESERVED Reserved Table 90 60h GVD MSAC Multi Size Aperture Control Size 32 bit Default 00020000h Power Well Core Access D F 0 2 Offset Start 60h PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 18h Bit Range Default Access Acronym Description 31 18 0000h RW SCRATCH Spare bits This register determines the size of the graphics memory aperture and untrusted space by default the aperture size is 256 MB Only BIOS writes this register based on address allocation efforts Drivers may read this register to determine the correct aperture size BIOS must restore this data upon S3 resume The value in this field affects the size of the UN TRUSTED GMADR and the size of the GTTBAR that is formed and used by the GVD 17 16 10b RW APERTURE SIZ 00 Reserved E UAS 01 512 MB Bits 28 and 27 of GMADR are read only allowing 512 MB of address space to be mapped The un trusted GTT is 512 kB 10 256 MB Bit 28 is read write and bit 27 of GMADR is read only limiting the address space to 256 MB The un trusted GTT is 256 KB 11 128 MB Bits 28 and 27 of GMADR are read write limiting the address space to 128 MB The un trusted GTT is 128 KB 15 0 0000h RW SCRATCH Spare bits Table 91 90h GVD MSI CAPID Message Signaled I
375. rn the latched status regardless of which was latched first The next one or two reads depending on whether the counter is programmed for one or two type counts return the latched count Subsequent reads return unlatched count High Precision Event Timer This function provides a set of timers to be used by the operating system for timing events One timer block is implemented containing one counter and 3 timers Registers The register space is memory mapped to a 1K block at address FEDOOOOON All registers are in the core well and reset by RESET Z Accesses that cross register boundaries result in undefined behavior HPET Registers Sheet 1 of 2 Start End Symbol Register 000 007 GCID General Capabilities and ID 010 017 GC General Configuration 020 027 GIS General Interrupt Status OFO OF7 MCV Main Counter Value Intel Atom Processor E6xx Series Datasheet 206 ACPI Devices Table 303 HPET Registers Sheet 2 of 2 Start End Symbol Register 100 107 TOC Timer 0 Config and Capabilities 108 10F TOCV Timer 0 Comparator Value 120 127 T1C Timer 1 Config and Capabilities 128 12F T1CV Timer 1 Comparator Value 140 147 T2C Timer 2 Config and Capabilities 148 14F T2CV Timer 2 Comparator Value 11 2 1 1 Offset 000h GCID General Capabilities and I D Table 304 000h GCID General Capabi
376. rol Register Sheet 1 of 2 Size 32 bit Default 0000 0000h Power Well Core Access D F 0 27 Offset Start 20h PCI Configuration B D F 0 27 0 Offset End 23h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description Global I nterrupt Enable Global bit to enable device interrupt generation When set to 1 the Intel HD Audio function is enabled to 31 0 RW GIE generate an interrupt This control is in addition to any bits in the bus specific address space such as the Interrupt Enable bit in the PCI Configuration Space Note This bit is not affected by the D3 97 to DO transition Controller Interrupt Enable Enables the general interrupt for controller functions When set to 1 the controller generates an interrupt 30 0 RW CIE when the corresponding status bit gets set due to a Response Interrupt a Response Buffer Overrun and State Change events Note This bit is not affected by the D3yo7 to DO transition Intel Atom Processor E6xx Series Datasheet 165 intel Intel High Definition Audio D27 FO Table 237 20h INTCTL Interrupt Control Register Sheet 2 of 2 Size 32 bit Default 0000_0000h Power Well Core Access e T Offset Start 20h PCI Configuration B D F 0 27 0 Offset End 23h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 29 04 0 RO RSVD Res
377. rs are located at 20h and 21h for the master controller IRQO 7 and at AOh and Alh for the slave controller IRQ8 13 These registers have multiple functions depending upon the data written to them Below is a description of the different register possibilities for each address 8259 I O Register Mapping Port Aliases Register Name Function Master 8259 ICW1 Init Cmd Word 1 Register 24h 28h 2Ch 30h 34h 20h 38h 3Ch Master 8259 OCW2 Op Ctrl Word 2 Register Master 8259 OCW3 Op Ctrl Word 3 Register Master 8259 ICW2 Init Cmd Word 2 Register Sah 25h 29h 2Dh 31h 35h Master 8259 ICW3 Init Cmd Word 3 Register 39h 3Dh Master 8259 ICWA Init Cmd Word 4 Register Master 8259 OCW1 Op Ctrl Word 1 Register ave 8259 ICW1 Init Cmd Word 1 Register A4h A8h ACh BOh B4h AUN 88h BCh ave 8259 OCW2 Op Ctrl Word 2 Register ave 8259 OCW3 Op Ctrl Word 3 Register ave 8259 ICW2 Init Cmd Word 2 Register Alh B9h BDh ave 8259 ICWA Init Cmd Word 4 Register ave 8259 OCW1 Op Ctrl Word 1 Register 4DOh aster 8259 Edge Level Triggered Register S S S S A5h A9h ADh B1h B5h Slave 8259 ICW3 Init Cmd Word 3 Register S S M S 4D1h ave 8259 Edge Level Triggered Register Offset 20h AOh I CW1 Initialization Command Word 1 A write to Initialization Command Word 1 starts the interrupt controller initialization sequence during w
378. rs in order to discover which Flash device is being used Four of the six supported Flash devices support the READ ID instruction Details of the discovery algorithm are outside the scope of this specification Disable Future Request Offset 02h SPIC SPI Control bit 0 Default state is Future Request enabled Re program opcode registers to support specific Flash vendor s commands If not using all of the Opcode Menu and Prefix Opcodes BIOS should program a safe value in the unused opcodes to minimize what malicious software can do A suggested safe value is to replicate one of the valid entries a Offset 54h PREOP Prefix Opcode Configuration b Offset 56h OPTYPE Opcode Type Configuration C Offset 58h OPMENU Opcode Menu Configuration Setup protection registers as needed a Offset 50h BBAR BIOS Base Address b Offset 60h PBRO Protected BIOS Range 0 2 C Offset 64h PBR1 Protected BIOS Range 1 d Offset 68h PBR2 Protected BIOS Range 2 Intel Atom Processor E6xx Series Datasheet 262 ACPI Devices 11 10 11 10 1 11 10 2 11 10 3 intel 9 Lock down the SPI registers Offset 00h SPIS SPI Status bit 15 10 Set Up SMI based write protection as needed same as FWH Watchdog Timer Overview This Watchdog timer provides a resolution that ranges from 1 ps to 10 minutes The timer uses a 35 bit down counter After the interrupt is generated the WDT loads the value from the P
379. ry range are dropped This simplifies the hardware architecture and forces all of these potentially harmful cycles to go through the Programmed Commands interface Note that Direct Memory Reads to the E0000h FFFFFh segments are remapped to top of flash as mentioned previously in Section 11 9 5 12 1 This range is not remapped when using Programmed Accesses SPI Clocking The SPI clock when driven by the processor is derived from the 100 MHz backbone clock The SPI Clock Selection fuse defaults to dividing the 100 MHz clock by 5 resulting in a clock frequency of 20 MHz 50 ns clock period Implementation Note The duty cycle is 40 and 60 Note that a DFT divide by 5 mode is added for determinism with the clock sets planned for the tester BIOS Programming Considerations In general any Flash update can be broken down into two steps 1 Erase 2 Write The Erase process initializes the addressed sector to FFh erase times for the supported Flash devices are shown below The atomic instructions that make up the Erase process are a Write enable instruction an Erase instruction and finally a status poll Intel Atom Processor E6xx Series Datasheet 260 ACPI Devices intel Table 385 Flash Erase Time Device Erase Time max Description PMC PM25LV 100 ms Same for block or sector Atmel AT25F l ls SST SST25VF 25 25 100 ms Sector block chip NexFlash NX25P 2 3 55 Sector chip
380. s If each timer has a unique interrupt and the timer has been configured for edge triggered mode then there are no specific steps required If configured to level triggered mode then its interrupt must be cleared by software by writing a 1 back to the bit position for the interrupt to be cleared Interrupts associated with the various timers have two interrupt mapping options Software should mask GC LRE when reprogramming HPET interrupt routing to avoid spurious interrupts Mapping Option 1 Legacy Option GC LRE set This forces the following mapping Timer Interrupt Mapping Legacy Option Timer 8259 Mapping APIC Mapping Comment 0 IRQO IRQ2 The 8254 timer will not cause any interrupts 1 IRQ8 IRQ8 RTC will not cause any interrupts 2 T2C IRQ T2C IRC Intel Atom Processor E6xx Series Datasheet 211 intel DEN 11 2 2 4 11 3 11 3 1 Table 311 Table 312 Mapping Option 2 Standard Option GC LRE cleared Each timer has its own routing control The interrupts can be routed to various interrupts in the I O APIC TnC IRC indicates which interrupts are valid options for routing If a timer is set for edge triggered mode the timers should not be shared with any other interrupts 8259 Interrupt Controller Overview The ISA compatible interrupt controller 8259 incorporates the functionality of two 8259 interrupt controllers The following table shows how the cores are connect
381. s 03h Bit Range Default Access Acronym Description 31 24 00h RO RESERVED Reserved 23 Ob RO MON STATUS MFUNC Integrated graphics is a single function 22 16 00h RO HEADER CODE HDR Indicates a type 0 header format 15 0 RO RESERVED Reserved Intel Atom Processor E6xx Series Datasheet 92 Graphics Video and Display Table 81 10h GVD MMADR Memory Mapped Address Range Size 32 bit Default 00000000h Power Well Core Access i READ Offset Start 10h PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register 04h 9 g Address Bit Range Default Access Acronym Description BA Set by the OS these bits correspond to address signals 31 20 The GVD will compare the SCL address scldown3_address 31 20 with MMADR 31 20 If there is a match and PCICMDSTS 1 MSE 1 and the SCL command is either a MEMRD or MEMWR the GVD will select the command and present it on the RMbus The MMADR is to be used for register programming the GVD memory interface registers the 31 20 000h RW BASE ADDRESS display controller registers the graphics cluster GFX registers the video decode VED registers the video encode VEC registers and the video processing block VPB registers If the display controller registers don t assert claim then GVD will report a miss on the SCL bus For all other register address that are part of this address r
382. s Reset Override FWH Sector Protection Protection MI Based f ed ene Writes No SMI Override Same as Write Protect in Global Write previous chipset for FWH Protection The processor provides these protections in hardware Note that it is critical that the hardware must not allow malicious software to modify the address or opcode pointers after determining that a cycle is allowed to run such that the actual cycle that runs on SPI should have been blocked If the command associated with an atomic cycle sequence is blocked according to the processor configuration the processor must not run any of the sequence A blocked command will appear to software to finish except that the Blocked Access Status bit in Offset 00h SPIS SPI Status register is set in this case BI OS Range Write Protection The processor provides a method for blocking writes to specific ranges in the SPI flash when the Protected BI OS Ranges are enabled This is achieved by checking the Opcode type information which can be locked down by the initial Boot BIOS and the address of the requested command against the base and limit fields of a Write Protected BIOS range In order to keep the hardware simple only the initial address is checked Since writes wrap within a page there should be no issue with writes illegally occurring in the next page assuming the BIOS has configured the Protection Limit to align with the edge of a page Note that o
383. s bit has no meaning for the root port since 05 0 RO TDP only one transaction may be pending to the processor A read of this cannot occur until it has already returned to 0 04 1 RO APD AUX Power Detected The root port contains AUX power for wake up Unsupported Request Detected This indicates that an unsupported 03 0 RWC URD request was detected Fatal Error Detected This indicates that a fatal error was detected It is 02 0 RWC FED set when a fatal error occurred on from a data link protocol error buffer overflow or malformed TLP Non Fatal Error Detected This indicates that a non fatal error was 01 0 RWC NFED detected It is set when an received a non fatal error occurred from a poisoned TLP unexpected completions unsupported requests completer abort or completer time out Correctable Error Detected This indicates that a correctable error was 00 0 RWC CED detected It is set when received an internal correctable error from receiver errors framing errors TLP CRC error DLLP CRC error replay num rollover or replay time out 8 2 2 6 LCAP Link Capabilities Table 155 Offset 4Ch LCAP Link Capabilities Size 32 bit Default XX154C11h Power Well Core Access e f Offset Start 4Ch PCI Configuration B D F 0 23 26 0 Offset End 4Fh Bit Range Default Access Acronym Description orh Port Number This indicates the port number for the root port This 31 24 03h or RO PN value is different for each implemented port Port O rep
384. s have no effect on the processor Registers that are marked as Intel Reserved must not be modified by system software Writes to Intel Reserved registers may cause system failure Reads from Intel Reserved registers may return a non zero value Upon a Cold Reset the processor sets all configuration registers to predetermined default states Some default register values are determined by external strapping options The default state represents the minimum functionality feature set required to successfully bring up the system it does not represent the optimal system configuration It is the responsibility of the system initialization software usually BIOS to properly determine the DRAM configurations and to program the system memory accordingly System Memory Map The Intel Atom Processor E6xx Series supports up to 2 GB of physical DDR2 memory space and 64 kB 3 of addressable I O space There is a programmable memory address space under the 1 MB region which is divided into regions that can be individually controlled with programmable attributes such as Disable Read Write Write Only or Read Only This section describes how the memory space is partitioned and how those partitions are used Top of Memory TOM is the highest address of physical memory actually installed in the system A TOM of greater than 2 GB is not supported Memory addresses above 2 GB will be routed to internal controllers or external 1 O devices Figure 3 represen
385. s use little endian ordering i e lower addresses contain the least significant parts of the field Registers which reside in bytes 256 through 4095 of each device may only be accessed using memory mapped transactions in DWord 32 bit quantities Some of the registers described in this section contain reserved bits These bits are labeled Reserved Software must deal correctly with fields that are reserved On reads software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value On writes software must ensure that the values of reserved bit positions are preserved That is the values of reserved bit positions must first be read merged with the new values for other bit positions and then written back Software does not need to perform read merge and write operations for the configuration address register Software must not generate configuration requests from memory mapped accesses that cross DWORD boundary as this will result in unpredictable behavior In addition to reserved bits within a register the processor contains address locations in the configuration space of the Host Bridge entity that are marked either Reserved or Intel Reserved The processor responds to accesses to Reserved address locations by completing the host cycle When a Reserved register location is read a zero value is returned Reserved registers can be 8 16 or 32 bits in size Writes to Reserved register
386. s used for INTA_B of Intel Atom Processor E6xx Series Datasheet 64 Register and Memory Mapping 5 5 3 2 Offset 3148h D27IR Device 27 Interrupt Route Table 58 3148h D27IR Device 27 Interrupt Route Size 16 bit Default Power Well Memory Mapped IO BAR RCBA Offset 3148h Bit Range Default Access Acronym Description Interrupt D Pin Route Indicates which routing is used for INTD B of 15 12 3h RW IDR device 27 I nterrupt C Pin Route Indicates which routing is used for INTC B of 11 08 2h RW ICR device 27 Interrupt B Pin Route Indicates which routing is used for INTB B of 07 04 1h RW IBR device 27 03 00 Oh RW IAR Interrupt A Pin Route Indicates which routing is used for INTA_B of device 27 5 5 3 3 Offset 314Ah D26IR Device 26 Interrupt Route Table 59 314Ah D26IR Device 26 Interrupt Route Size 16 bit Default Power Well Memory Mapped IO BAR RCBA Offset 314Ah Bit Range Default Access Acronym Description r Interrupt D Pin Route Indicates which routing is used for INTD B of 15 12 3h RW IDR device 26 Interrupt C Pin Route Indicates which routing is used for INTC B of 11 08 2h RW ICR device 26 p Interrupt B Pin Route ndicates which routing is used for INTB_B of 07 04 1h RW IBR device 26 03 00 Oh RW IAR Interrupt A Pin Route Indicates which routing is used for INTA_B of device 26
387. se of H 264 the Pixel Reconstruction Unit also implements weighted averaging The final reconstructed data is then passed to the VDEB for de blocking as well as being fed back to the reference cache so that intra boundary data can be extracted Deblocking The deblocking module is responsible for codec back end video filtering It is the last module within the high definition video decoder module pipeline The deblocking module performs overlap filtering and in loop de blocking of the reconstructed data generated by the motion compensation module The frames generated are used for display and for reference of subsequent decoded frames The deblocking module performs the following specific codec functions H 264 Deblocking including ASO modes VC 1 WMV9 overlap filter and in loop deblocking Range mapping Pass through of reconstructed data for codec modes that do not require deblocking MPEG2 MPEG4 Output Reference Frame Storage Format Interlaced pictures as opposed to progressive pictures are always stored in system memory as interlaced frames including interlaced field pictures Intel Atom Processor E6xx Series Datasheet 82 m e Graphics Video and Display n tel 7 4 1 4 Pixel Format The pixel format has the name 420PL12YUV8 This consists of a single plane of luma Y and a second plane consisting of interleaved Cr Cb V U components For 420PL12YUV8 the number of chroma samples is a quarter of the qu
388. solely responsible for generating the start frame Quiet Mode Peripheral initiates the start frame and the interrupt controller completes it These modes are entered via the length of the stop frame Continuous mode must be entered first to start the first frame This start frame width is 8 LPC clocks This is a polling mode In Quiet mode the SERIRQ line remains inactive and pulled up between the Stop and Start Frame until a peripheral drives SERIRQ low The interrupt controller senses the line low and drives it low for the remainder of the Start Frame Since the first LPC clock of the start frame was driven by the peripheral the interrupt controller drives SERIRQ low for 1 LPC clock less than in continuous mode This mode of operation allows for lower power operation Data Frames Once the Start frame has been initiated the SERIRQ peripherals start counting frames based on the rising edge of SERIRQ Each of the IRQ DATA frames has exactly 3 phases of 1 clock each Sample Phase During this phase a device drives SERIRQ low if its corresponding interrupt signal is low If its corresponding interrupt is high then the SERIRQ devices tristate SERIRQ SERIRQ remains high due to pull up resistors Recovery Phase During this phase a device drives SERIRQ high if it was driven low during the Sample Phase If it was not driven during the sample phase it remains tristated in this phase Turn around Phase The device tristates SE
389. sor E6xx Series Datasheet 98 Graphics Video and Display Table 94 BOh GVD VCI D Vendor Capability I D Size 32 bit Default 01070009h Power Well Core Recess PCI Configuration B D F 0 2 0 pics SEN Message Bus Port 06h Register Address 2Ch Bit Range Default Access Acronym Description 31 24 Olh RO VERSION VS Identifies this as the first revision of the CAPID register definition 23 16 07h RO LENGTH pr field has the value 07h to indicate the structure length 8 15 8 00h RO NEXT CAPABIL If FD MD is cleared this reports 90h MSI capability If FD MD is set this ITY POINTER reports OOh last item in the list 7 0 09h RO CAPABILITY D Identifies this as a vendor dependent capability pointers Table 95 B4h GVD VC Vendor Capabilities Size 32 bit Default 00000000h Power Well Core PECESS PCI Configuration B D F 0 2 0 pe B4h Message Bus Port 06h Register Address 2Dh Bit Range Default Access Acronym Description 31 0 Oh RO RESERVED Reserved Table 96 C4h GVD FD Functional Disable Size 32 bit Default C4h Power Well Core Access PCI Configuration B D F 0 2 0 SE C4h Message Bus Port 06h Register Address 31h Bit Range Default Access Acronym Description 31 2 pron RO RESERVED Reserved MD When set the MSI capability pointer is not available the item 1 Ob RW MSI DISABLE which points to the MSI capabilit
390. ss D E X31 Offset Start 06h PCI Configuration B D F X 31 0 Offset End 07h Bit Range Default Access Acronym Description 15 00 0 RO RSVD Reserved 10 2 4 RI D Revision I D Register Table 279 Offset O8h RID Revision ID Size 8 bit Default Refer to bit description Power Well Access i D F 0 31 Offset Start 08h PCI Configuration B D F 0 31 0 Offset End 08h Bit Range Default Access Acronym Description Refer to Revision I D Refer to the Intel Atom Processor E6x5C Series 07 00 bit RWO RID Specification Update for the value of the Revision ID Register For the t descript Ger Stepping this value is 01h For the B 1 Stepping this value is ion Intel Atom Processor E6xx Series Datasheet 189 intel LPC Interface D31 F0 10 2 5 CC Class Code Register Table 280 Offset 09h CC Class Code Size 24 bit Default 060100h Power Well Access D E X31 Offset Start 09h PCI Configuration B D F X 31 0 Offset End 0Bh Bit Range Default Access Acronym Description 23 16 06h RO BCC Base Class Code Indicates the device is a bridge device 15 08 01h RO SCC Sub Class Code Indicates the device a PCI to ISA bridge E Programming Interface The LPC bridge has no programming 07 00 00h RO PI interface 10 2 6 HDTYPE Header Type Register Table 281 Offset OEh HDTYPE Header Type Size 8 bit
391. ster Sheet 1 of 2 Size 32 bit Default 0000 0000h Power Well Core Access D E 0 27 Offset Start FCh PCI Configuration B D F 0 27 0 Offset End FFh Bit Range Default Access Acronym Description 31 03 0 RO RSVD Reserved Intel Atom Processor E6xx Series Datasheet 152 Intel High Definition Audio D27 FO i n tel Table 209 FCh FD Function Disable Register Sheet 2 of 2 Size 32 bit Default 0000 0000h Power Well Core Access D F 0 27 Offset Start FCh PCI Configuration B D F 0 27 0 Offset End FFh Bit Range Default Access Acronym Description Clock Gating Disable 02 0 RW GCD 0 Clock gating within the device is enabled Default 1 Clock gating within the device is disabled MSI Disable 01 0 RW MD 0 The MSI capability is visible The NXT_PTR2 register will contain 60h 1 The MSI capability is disabled The NXT_PTR2 register will contain 00h indicating it s the last capability in the list 00 0 RW D Disable 1 D27 FO is disabled 9 3 1 33 Offset 100h VCCAP Virtual Channel Enhanced Capability Header Table 210 100h VCCAP Virtual Channel Enhanced Capability Header Size 32 bit Default 1301 0002h Power Well Core Access D E 0 27 Offset Start 100h PCI Configuration B D F 0 27 0 Offset End 103h Bit Range Default Access Acronym Description Next Capability Offset Points to the nex
392. supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as USWC in other words prefetchable from the CPU perspective Table 144 Offset 26h PML Prefetchable Memory Limit Address Size 16 bit Default 0000h Power Well Core Access A Offset Start 26h PCI Configuration B D F 0 23 26 0 Offset End 27h Bit Range Default Access Acronym Description 15 04 000h RW PML Prefetchable Memory Address Limit This corresponds to A 31 20 of the upper limit of the address range passed to PCI Express 03 00 Oh RW RSVD Reserved 8 2 1 19 CAPP Capabilities Pointer The capabilities pointer provides the address offset to the location of the first entry in this device s linked list of capabilities Table 145 Offset 34h CAPP Capabilities Pointer Size 8 bit Default 40h Power Well Core Access e S Offset Start 34h PCI Configuration B D F 0 23 26 0 Offset End 34h Bit Range Default Access Acronym Description P First Capability The first capability in the list is the Subsystem ID and 07 00 40h RO PAR Subsystem Vendor ID Capability 8 2 1 20 ILINE Interrupt Line This register contains interrupt line routing information The device itself does not use this value rather it is used by device drivers and operating systems to determine priority and
393. t ODT 0 C180 jes ECN vss M d FE ho wem CSI es T L i T 8 fos x woo ies RE KI e Ts 1 lt ICC 180 lt lt o g o E uc lt X E o o 7 7 Pd Pad Pd ad Bd ed o r e r x z a lt EI o 9g 7 es Ko ooo w S RER DREES REES A lt o E oo o VCC180 wcesus CC33RTC Moom CCP33SUS S lt RE VCCSFRHPLL S lt u lt lt REES ICCP33 E DVO_REDN lt PIO SUS 4 lt lt AKE B Mm S 16 oi joj o o MB DATA LPC ADIS SDVO_CTRLCLK LPC_CLKOUTI0 Pp SDVO_TVCLKINN sbvo CLKN T lt a n g no amp 6 lt lt Ge o o lt Ra 10 n DVO_REFCLK an PC_FRAME_B SS DQ 29 PIO_SUS 0 T PC CLKOUT 2 lt SS DVO_REFCLKN Intel Atom Processor E6xx Series Datasheet 286 Ballout and Package Information Figure 15 Intel Atom Processor E6xx Series Ball Map Sheet 3 of 5 3 O a l DQ 20 DQ 17 DQ 21 GTLVREF K WRMODE O ICCA_PEG CIE_ICOMPI DO 19 DQ 22 2 5 i EE SEL 1 PIO_B SIS SIS 5 n CTDI v FR c ICCSENSE ICCA CC VSSSENSE NNSENSE EB mG S 5 Ol ofj o e 3 o ICCFHV ICCDSENSE ST fal al lal lal lal
394. t The Reference Cache module accepts the Inter Intra prediction commands along with the motion vectors and index to reference frame in the case of Inter prediction The module calculates the location of reference data in the frame store including out of bounds processing requirements The module includes cache memory which is checked before external system memory reads are requested the cache can significantly reduce system memory bandwidth requirements In H264 mode the module also extracts and stores Intra boundary data which is used in Intra prediction The output of the reference cache is passed to the 2D filter module The 2D filter module implements up to eight tap Vertical and Horizontal filters to generate predicted data for sub pixel motion vectors to a resolution of up to 1 8th of a pixel The 2D filter module also generates H 264 intra prediction tiles based on the intra prediction mode and boundary data extracted by the reference cache For VC1 and WMV9 the 2D filter module also implements Range scaling and Intensity Compensation on inter reference data prior to sub pixel filtering The Pixel Reconstruction Unit combines predicted data from the 2D filter with the re ordered residual data from the Module Control Unit In the case of bidirectional macroblocks with two motion vectors per tile the Pixel Reconstruction Unit combines the two tiles of predicted data prior to combining the result with residual data In the ca
395. t 040300h Power Well Core Access DE 0 97 Offset Start 09h PCI Configuration B D F 0 27 0 Offset End 0Bh Bit Range Default Access Acronym Description y Base Class Code This register indicates that the function implements a 23 16 04h RO BCC multimedia device Sub Class Code This indicates the device is an Intel HD Audio audio 15 08 03h RO SCC device in the context of a multimedia device Intel Atom Processor E6xx Series Datasheet 143 m n tel Intel High Definition Audio D27 FO Table 183 O9h CC Class Codes Register Sheet 2 of 2 Size 24 bit Default 040300h Power Well Core Access e D E 0 27 Offset Start 09h PCI Configuration B D F 0 27 0 Offset End OBh Bit Range Default Access Acronym Description 07 00 00h RO PI Programming Interface Indicates Intel HD Audio programming 9 3 1 7 Offset OCh CLS Cache Line Size Register Table 184 OCh CLS Cache Line Size Register Size 8 bit Default 00h Power Well Core Access D EO 27 Offset Start OCh PCI Configuration B D F 0 27 0 Offset End OCH Bit Range Default Access Acronym Description Cache Line Size Doesn t apply to PCI Express The PCI Express 07 00 00h RW CLS specification requires this to be implemented as a RW register but has no functional impact on the Intel HD Audio controller 9 3 1 8 Offset ODh LT Latency Timer Register
396. t Configuration cceceeeee este eee teens 133 8 2 5 gt SMSES SMI 7 SCI Status eio arras 134 8 2 6 Miscellaneous Confiouration mmm 135 8 2 6 1 FD Functional Disable mmn 135 9 0 Intel High Definition Audio Di 7FOo eene 137 EEMNEECOTIMIIE mm 137 9 2 DOCKING EE 137 9 2 1 DOCK Sequence rtr rre a Ras 138 9 2 2 Undock Sequence corone ebrietas ene bene al e br nr d Debe ss 139 9 2 s Relationship Between HDA DOCKRST B and HDA RST Bi 139 9 2 External Pull Ups Pull DOWNS Immer 140 9 3 PCI por alte Register Space secs de Z genge egene ge AE LEER e RA EFE 140 9 3 1 R glsters ostio gege AE ege Dn hed diea el ela dre Pod ehe kd 140 9 3 1 1 Offset 00h VID Vendor Identification cece cere 142 9 3 1 2 Offset 02h DID Device Identification eee eee eee 142 9 3 1 3 Offset 04h PCICMD PCI Command Register 142 9 3 1 4 Offset 06h PCISTS PCI Status Register 143 9 3 1 5 Offset 08h RID Revision Identification Register 143 9 3 1 6 Offset 09h CC Class Codes Register 143 9 3 1 7 Offset OCh CLS Cache Line Size Register 144 9 3 1 8 Offset ODh LT Latency Timer Register 144 9 3 1 9 Offset OEh HEADTYP Header Type Register 144 9 3 1 10 Offset 10h LBAR Lower Base Address Register 144 9 3 1 11 Offset 14h UBAR Upper Base Address Register 145 9 3 1 12 Offset 2Ch SVID Subsystem Vendor Identifier
397. t Delivery Data Value Interrupt Delivery Data Value Bit Description 31 16 0000h 15 Trigger Mode RTE x TM Delivery Status 1 Assert 0 Deassert Only Assert messages are sent This bit is always set to 14 1l 13 12 00 11 Destination Mode RTE x DSM 10 08 Delivery Mode RTE x DLM 07 00 Vector RTE x VCT PCI Express Interrupts When external devices through PCI Express generate an interrupt they will send the message defined in the PCI Express specification for generating INTA INTD These will be translated internal assertions de assertions of INTA INTD Routing of I nternal Device I nterrupts The internal devices on the processor drive PCI interrupts These interrupts can be routed internally to any of PIRQA PIRQH This is done utilizing the Device X Interrupt Pin and Device X Interrupt Route registers located in chipset configuration space For each device the Device X Interrupt Pin register exists which tells the functions which interrupt to report in their PCI header space in the Interrupt Pin register for the operating system These registers are named D24IP D23IP DO2IP etc Additionally the Device X Interrupt Route register tells the interrupt controller in conjunction with the Device X Interrupt Pin register which of the internal PIRQA PIRQH to drive the devices interrupt onto This requires the interrupt controller to know
398. t End 07h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 15 07 0 RO RSVD Reserved Intel Atom Processor E6xx Series Datasheet 161 intel Intel High Definition Audio D27 FO Table 230 06h INPAY Input Payload Capability Register Sheet 2 of 2 Size 16 bit Default 001Dh Power Well Core Access e Td Offset Start 06h PCI Configuration B D F 0 27 0 Offset End 07h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description Input Payload Capability Indicates the total input payload available on the link This does not include bandwidth used for response This measurement is in 16 bit word quantities per 48 kHz frame The default link clock speed of 24 000 MHz provides 500 bits per frame or 31 25 words in total 36 bits are used for response leaving 29 words for data 06 00 1Dh RO INPAY payload 00h 0 words O1h 1 word payload FFh 255h word payload 9 3 2 1 6 Offset 08h GCTL Global Control Table 231 O8h GCTL Global Control Sheet 1 of 2 Size 32 bit Default 0000 0000h Power Well Core Access PCI Configuration B D F 0 27 0 Offset Start 08h Offset End OBh Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 31 09 0 RO RSVD Reserved Accept Unsolicited Response Enable 08 0 RW UNSOL 0 Unsolicited respo
399. t PLL CLK Differential pair 100 MHz 2 12 General Purpose I O Table 16 General Purpose I O Signals Power S Signal Name Type Well Description General Purpose IO These signals are powered off of the suspend well power plane within the processor They are accessible during the S3 sleep state GPIO SUS 7 can be 1 0 used to wake the system from Suspend to RAM while GPIO SUS 8 0 sus GPIO_SUS 1 4 can be used to wake the system from CMOS3 3 Suspend to RAM provided LVDS is disabled on the platform GPIO_SUS 7 is required to strap to 1 during platform boot up for Intel Atom Processor E6xx Series B 1 Stepping 1 0 General Purpose IO These signals are powered off of the GPIO 4 0 CMOS3 3 Core core well power plane within the processor 2 13 Functional Straps The following signals are used to configure certain processor features Table 17 Functional Straps Sheet 1 of 2 Signal Name Strap Definition GPIO_SUS 0 STRAP_MEM_DEV_WIDTH Defines the memory device width 0 x16 devices 1 x8 devices GPIO_SUS 6 5 11 2 Gb 10 1 Gb 01 512 Mb 00 256 Mb STRAP MEM DEV 1 0 GPIO SUS 6 5 Defines the memory device densities connected GPIO SUS 8 STRAP MEM RANK Defines the number of ranks enabled 1 1 Rank 0 2 Rank Intel Atom Processor E6xx Series Datasheet 42 Signal Description Table 17 Functional Straps Sheet 2 of 2
400. t Start 100Ch PCI Configuration B D F 0 27 0 Offset End 100Fh Memory Mapped IO BAR Offset Bit Range Default Access Acronym Description 31 20 0 RO RSVD Reserved Minimum Status Tracks the minimum FIFO free count for inbound P engines and the minimum avail count for outbound engines when the EN 19 11 1FFh RO MSTS is set and the R is de asserted The FIFO of the DMA selected by the DMASEL will be tracked Error Count Increment each time a FIFO error occurs in the FIFO which 10 05 Oh RO EC the DMA select is pointing to when the enable bit is set and R is de t asserted When the EC reaches the max count of 1FFh 63 the count saturates and hold the max count until it is reset Select The MSTS and EC track the FIFO for the DMA select by this register The mapping is as follows 000 Output DMA 0 001 Output DMA 1 010 Reserved 04 02 Oh RW SEL 011 Reserved 100 Input DMA 0 101 Input DMA 1 110 Reserved 111 Reserved Enable When set to 1 the MSTS and the EC fields in this register track 01 0 RW EN the minimum FIFO status or error count When set to 0 the MSTS and the EC fields hold its previous value 00 0 RW R aan When set to 1 the MSTS and the EC are reset to their default 9 3 2 1 46 Offset 1010h 1014h 1020h 1024h I ODPIB I 1DPI B OODPI B O1DPIB I nput Output Stream Descriptor 0 1 DMA Position in Buffer Register Table 271 1010h 1014h 1020h 1024h I ODPIB I DPI B OODPIB O1DPIB Input Output Stream Descriptor 0 1 D
401. t Start 3022h Offset End 3023h Memory Mapped IO BAR RCBA Offset Bit Range Default Access Acronym Description 15 0 RW SSMIE SPI SMI 4 Enable When set to 1 the SPI asserts an SMI request whenever the Cycle Done Status bit is 1 14 RW DC Data Cycle When set to 1 there is data that corresponds to this transaction When 0 no data is delivered for this cycle and the DBC and data fields themselves are don t cares 13 08 RW DBC Data Byte Count This field specifies the number of bytes to shift in or out during the data portion of the SPI cycle The valid settings in decimal are any value from 0 to 63 The number of bytes transferred is the value of this field plus 1 Note that when this field is 00 0000b then there is 1 byte to transfer and that 11 1111b means there are 64 bytes to transfer RV RSVD Reserved RW COP Cycle Opcode Pointer This field selects one of the programmed opcodes in the Offset 58h OPMENU Opcode Menu Configuration to be used as the SPI Command Opcode In the case of an Atomic Cycle Sequence this determines the second command RW SPOP Sequence Prefix Opcode Pointer This field selects one of the two programmed prefix opcodes for use when performing an Atomic Cycle Sequence A value of 0 points to the opcode in the least significant byte of the Offset 54h PREOP Prefix Opcode Configuration register By making this prog
402. t Start F4h PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 39h Bit Range Default Access Acronym Description Software scratch byte 2 Any write to this byte even writing back the 23 16 00h RW SCRATCH 2 same value read will trigger GVD to send the contents of LEGACY BACKLIGHT BRIGHTNESS byte to the VSunit Software scratch byte 1 Any write to this byte even writing back the 15 8 00h RW SCRATCH 1 same value read will trigger GVD to send the contents of LEGACY BACKLIGHT BRIGHTNESS byte to the VSunit LBES The value of zero is the lowest brightness setting and the value of 255 is the brightest A write to this register will cause a flag to be set 1 0 00h RW LEGACY BACKI LBES in the PIPEBSTATUS register and cause an interrupt if Backlight ESS event in the PIPEBSTATUS register and cause an Interrupt if Backlight Event LBEE and Display B Event is enabled by software The field value byte is forwarded by the GVD to the Vsunit Table 102 FCh GVD ASLS ASL ASL Storage Size 32 bit Default 00000000h Power Well Core Access e L dica Offset Start FCh PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 3Fh Bit Range Default Access Acronym Description This register provides a means for the BIOS to communicate with the driver This definition of this scratch register is worked out in common 000000 between System B
403. t affected by the D uer to DO transition 29 04 0 RO RSVD Reserved Stream Interrupt Status A 1 indicates that an interrupt condition occurred on the corresponding Stream Note that a HW interrupt will not be generated unless the corresponding enable bit is set This bit is an OR of all of an individual stream s interrupt status bits The streams are numbered and the SIS bits assigned sequentially based 03 00 Oh RO SIS on their order in the register set Bit 3 Output Stream 2 OS2 Bit 2 Output Stream 1 OS1 Bit 1 Input Stream 2 1S2 Bit 0 Input Stream 1 1S1 9 3 2 1 14 Offset 30h WALCLK Wall Clock Counter Register The 32 bit monotonic counter provides a wall clock that can be used by system software to synchronize independent audio controllers The counter must be implemented Intel Atom Processor E6xx Series Datasheet 166 Intel High Definition Audio D27 FO Table 239 30h WALCLK Wall Clock Counter Register Size 32 bit Default 0000_0000h Power Well Core Access PCI Configuration B D F 0 27 0 Offset Start 30h Offset End 33h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 31 00 0000 0000h RO Counter Wall Clock Counter 32 bit counter that is incremented on each link Bit Clock period and rolls over from FFFF_FFFFh to 0000 0000h This counter will roll over to zero with a period of approximately
404. t capability header which is 31 20 130h RO NATCAR the Root Complex Link Declaration Enhanced Capability Header 19 16 1h RO Capability Version 15 00 0002h RO PCI Express Extended Capability 9 3 1 34 Offset 104h PVCCAP1 Port VC Capability Register 1 Table 211 104h PVCCAP1 Port VC Capability Register 1 Size 32 bit Default 0000 0001h Power Well Core Access D F 0 27 Offset Start 104h PCI Configuration B D F 0 27 0 Offset End 107h Bit Range Default Access Acronym Description 31 03 0 RO RSVD Reserved J Extended VC Count Indicates that one extended VC in addition to 02 00 001 RO VCCNT VCO is supported by the Intel HD Audio controller Intel Atom Processor E6xx Series Datasheet 153 m l n tel Intel High Definition Audio D27 FO 9 3 1 35 Offset 108h PVCCAP2 Port VC Capability Register 2 Table 212 108h PVCCAP2 Port VC Capability Register 2 Size 32 bit Default 0000 0000h Power Well Core Access e D FE 0 27 Offset Start 108h PCI Configuration B D F 0 27 0 Offset End 10Bh Bit Range Default Access Acronym Description 31 00 0 RO RSVD Reserved 9 3 1 36 Offset 10Ch PVCCTL Port VC Control Register Table 213 10Ch PVCCTL Port VC Control Register Size 16 bit Default 00000h Power Well Core Access D E 0 27 Offset Start 10Ch PCI Configuration B D F 0 27 0 Offset End
405. t data Effective geometry compression High order surface support External data access Permits reads from main memory by cache can be bypassed Permits writes to main memory Data fence facility provided Dependent texture reads Intel Atom Processor E6xx Series Datasheet 76 m e Graphics Video and Display n tel 7 2 3 7 2 3 1 7 2 3 2 Vertex Processing Modern graphics processors perform two main procedures to generate 3D graphics First vertex geometry information is transformed and lit to create a 2D representation in the screen space Those transformed and lit vertices are then processed to create display lists in memory The pixel processor then rasterizes these display lists on a regional basis to create the final image The integrated graphic processor supports DMA data accesses from main memory DMA accesses are controlled by a main scheduler and data sequencer engine This engine coordinates the data and instruction flow for the vertex processing pixel processing and general purpose operations Transform and lighting operations are performed by the vertex processing pipeline A 3D object is usually expressed in terms of triangles each of which is made up of three vertices defined by X Y Z coordinate space The transform and lighting process is performed by processing data through the unified shader core The results of this process are sent to the pixel processing function The steps to
406. t from L1 prior to entering LO Common Clock Configuration When set this indicates that the 06 Ob RW CCC processor and device are operating with a distributed common reference clock Retrain Link When set the root port will train its downstream link This 05 Ob RO W RL bit always returns 0 when read Software uses LSTS LT and LSTS LTE to check the status of training 04 Ob RW LD Link Disable When set the root port will disable the link 03 Ob RO RCBC Dee Completion Boundary Control Read completion boundary is 64 02 Ob RO RSVD Reserved Active State Link PM Control This indicates if the root port should enter LOs or L1 or both 00 Disabled The processor does not support disable mode writing 00 01 00 Oh RW APMC has no effect 01 LOs Entry Enabled 10 L1 Entry Enabled 11 LOs and L1 Entry Enabled 8 2 2 8 LSTS Link Status Table 157 Offset 52h LSTS Link Status Size 16 bit Default 1001h Power Well Core Access e INE 0 92 96 Offset Start 52h PCI Configuration B D F 0 23 26 0 Offset End 53h Bit Range Default Access Acronym Description 13 0 RO LA Link Active This is set to 1b when the Data Link Control and Management State Machine is in the DL Active state it is Ob otherwise 12 1 RO SCC Slot Clock Configuration The processor uses the same reference clock as on the platform and does not generate its own clock 11 0 RO LT Link Training The root port sets this bit whenever link training is occurring It clears the bit o
407. t inactive The use of an insulating material between the capacitors and any thermal solution should be considered to prevent capacitor shorting An exclusion or keep out zone surrounds the die and capacitors and identifies the contact area for the package Care should be taken to avoid contact with the package inside this area Refer to the Intel Atom Processor E6xx Series Thermal and Mechanical Design Guidelines for details on package mechanical dimensions and tolerance as well as other key package attributes Dimensions Package parameters 22 mm x 22 mm Ball Count 676 Land metal diameter 500 microns Solder resist opening 430 microns Tolerances e X 0 1 e XX 0 05 Angles 1 0 degrees Intel Atom Processor E6xx Series Datasheet 281 inte 14 1 Figure 10 Ballout and Package I nformation Package Diagrams Intel Atom Processor E6xx Series Silicon and Die Side Capacitor Top View e 22 mr 22mm 36 34 32 30 28 26 24 22 20 18 l 14 12 10 a 6 4 2 Intel Atom Processor E6xx Series Datasheet 282 intel Ballout and Package Information Imensions Intel Atom Processor E6xx Series Package D Figure 11 f 35 a onraven 395 LON 00 CELE t fei 611191 BRENDA mem asina ONIMVYC SLA ava avo mem 1 gen NOI L9arOwd 319NY QHIHI CLEEN L
408. t protocol Clock Run This signal gates the operation of the 1 0 LPC_CLKOUTx Once an interrupt sequence has started PESE CES CMOS3 3 Core LPC_CLKRUN_B should remain asserted to allow the LPC_CLKOUTXx to run LPC Clock These signals are the clocks driven by the o processor to LPC devices Each clock can support up to two LPC_CLKOUT 2 0 CMOS3 3 Core loads Note The primary boot device like SPI behind SMC should be connected to LPC_CLKOUT 0 Boot from LPC is not supported SMBus Interface Signals SMBus Interface Signals Signal Name a UI Description ITO EE eee ey E a D Ag tus SMS CUN eee Seana ane SPI Interface Signals SPI Interface Signals Signal Name a ait Description SPI_MOSI oe Core SPI Data Output Unidirectional output data for the SPI IF SPI_MISO ss Core SPI Data Input Unidirectional input data for the SPI IF ru NOME LE SPI SCK m Core SPI Clock Output Serial clock accompanying data Intel Atom Processor E6xx Series Datasheet 36 Signal Description 2 8 Power Management I nterface Signals Table 12 Power Management I nterface Signals Signal Name Direction Type Power Well Description RESET B l CMOS3 3 SUS System Reset Active Low Hard Reset for the processor When asserted the processor will immediately initialize itself and return to its default state This signal is driven by the
409. te details CMOS CMOS Open Drain 1 05 V CMOS buffer CMOS_HDA CMOS buffers for Intel HD Audio interface 3 3 V operation CMOS1 8 1 8 V CMOS buffer These buffers can be configured as Stub Series Termination 2 Logic SSTL1 8 CMOS3 3 CMOS3 3 Open Drain 2J CMOS ultr CMOS3 3 5 3 3 V CMOS buffer 5 V tolerant PCI Express interface signals These signals are compatible with PCI Express Base Specification Rev 1 0a Signaling Environment AC Specifications and are AC PCI e coupled The buffers are not 3 3 V tolerant Differential voltage specification D D x 2 1 2 Vmax Single ended maximum 1 5 V Single ended minimum 0 V SDVO Serial DVO differential output buffers These signals are AC coupled LVDS Low Voltage Differential Signal buffers These signals should drive across a 100 Ohm resistor at the receiver when driving Analog Analog reference or output Can be used as a threshold voltage or for buffer compensation Intel Atom Processor E6xx Series Datasheet 275 intel DC Characteristics 13 2 Power and Current Characteristics Table 403 Thermal Design Power Symbol Parameter Range Unit Notes Thermal Design Power Ultra Low SKU RS at 1 05 V Core Voltage 3 3 w 1 Thermal Design Power Entry SKU TDP_E at 1 05 V Core Voltage 3 6 w 1 Thermal Design Power Mainstream SKU TDELM at 1 05 V Core Voltage 3 6 Ww 1 Thermal Design Power Premium SKU IDE at 1 05
410. tel HD Audio specification Intel Atom Processor E6xx Series Datasheet 137 Bl n tel Intel High Definition Audio D27 FO 9 2 1 Note Prior to the physical undocking process the user normally requests undocking Software then gracefully halts the streams to the codecs in the docking station and then initiates the undocking sequence in the Intel HD Audio controller Intel HD Audio controller asserts dock reset and then manages the external switch to electrically isolate the dock codec from the processor s Intel HD AudioP interface prior to physical undocking Electrical isolation during surprise undocking is handled external to the Intel HD Audio controller and software invokes the undocking sequence in the Intel HD Audio controller as part of the clean up process simply to prepare for a subsequent docking event The Intel HD AudioP controller isn t aware that a surprise undock occurred Dock Sequence This sequence is followed when the system is running and a docking event occurs as well as when resuming from S3 RESET B asserted and Intel HD AudioP controller D3 1 Since the processor supports docking the Docking Supported DCKSTS DS bit defaults to a 1 Post BIOS and ACPI Software use this bit to determine if the Intel HD AudioP controller supports docking BIOS may write a 0 to this RWO bit during POST to effectively turn off the docking feature 2 After reset in the undocked quiescent state
411. that this is a PCI power 07 00 Olh RO CID management capability 8 2 4 2 PMC PCI Power Management Capabilities Table 169 Offset A2h PMC PCI Power Management Capabilities Size 16 bit Default C802h Power Well Core Access DE 0 23 26 Offset Start A2h PCI Configuration B D F 0 23 26 0 Offset End A3h Bit Range Default Access Acronym Description Ge Support This indicates that ee is supported for RE DO D3yot and D3co p The root port does not generate PME B but reporting 15 11 11001 RO PMES that it does is necessary for legacy Microsoft operating systems to enable PME_B in devices connected behind this root port 10 0 RO D2S D2 Support The D2 state is not supported 09 0 RO D1S D1 Support The D1 state is not supported N AUX Current This reports the 375 mA maximum suspend well current 08 06 000 RO AC when in the D3co p state Device Specific Initialization This indicates that no device specific 05 0 RO DSI initialization is required 04 0 RO RSVD Reserved 03 0 RO PMEC ag clock This indicates that the PCI clock is not required to generate A Version This indicates support for Revision 1 1 of the PCI Power 02 00 010 RO vS Management Specification 8 2 4 3 PMCS PCI Power Management Control And Status Table 170 Offset A4h PMCS PCI Power Management Control And Status Sheet 1 of 2 Size 32 bit Default 00000000h Power Well Core Access Offset Start A4h PCI Configuration B D F 0 23 26 0 Offset End A7h
412. the GPIO is programmed as an input then this bit reflects the 04 00 0 RW LVL e of the input signal 1 high 0 low and writes will have no effect ny value of this bit has no meaning if the GPIO is disabled GEN EN n 11 7 1 4 Offset OCh CGTPE Core Well GPI O Trigger Positive Edge Enable Table 344 OCh CGTPE Core Well GPIO Trigger Positive Edge Enable Size 32 bit Default 00000000h Power Well Core Access Offset Start OCh PCI Configuration B D F 0 31 0 Offset End OFh Memory Mapped IO BAR GPIO BAR 10 Offset Bit Range Default Access Acronym Description 31 05 0 RO RSVD Reserved Trigger Enable When set the corresponding GPIO if enabled as input via GIO IO n will case an SMI SCI when a 0 to 1 transition occurs 04 00 0 RW TE When cleared the GPIO is not enabled to trigger an SMI SCI on a 0 to 1 transition This bit has no meaning if GlO 1O n is cleared i e programmed for output Intel Atom Processor E6xx Series Datasheet 235 intel ACPI Devices 11 7 1 5 Offset 10h CGTNE Core Well GPI O Trigger Negative Edge Enable Table 345 10h CGTNE Core Well GPI O Trigger Negative Edge Enable Size 32 bit Default 00000000h Power Well Core Access Offset Start 10h PCI Configuration B D F 0 31 0 Offset End 13h
413. the SMBASE BA field is enabled 30 16 Oh RO RSVD Reserved 15 06 Oh RW BA Paca Address This field provides the 64 bytes of I O space for 05 00 Oh RO RSVD Reserved 10 3 2 GBA GPIO Base Address Register Table 284 Offset 44h GBA GPIO Base Address Size 32 bit Default 00000000h Power Well GEESS PCI Configuration B D F X 31 0 ee SCH Bit Range Default Access Acronym Description Enable 31 0 RW EN 1 Decode of the I O range pointed to by the GPIOBASE BA is enabled 30 16 Oh RO RSVD Reserved 15 06 Oh RW BA Base Address This field provides the 64 bytes of I O space for GPIO 05 00 Oh RO RSVD Reserved 10 3 3 PM1BLK PM1_ BLK Base Address Register Table 285 Offset 48h PM1BLK PM1 BLK Base Address Sheet 1 of 2 Size 32 bit Default 00000000h Power Well EES PCI Configuration B D F X 31 0 UE id Bit Range Default Access Acronym Description Enable am S RW EN 1 Decode of the I O range pointed to by the PM1BASE BA is enabled 30 16 Oh RO RSVD Reserved 15 04 Oh RW BA Base Address This field provides the 64 bytes of I O space for Intel Atom Processor E6xx Series Datasheet 191 intel LPC Interface D31 F0 Table 285 Offset 48h PM1BLK PM1_BLK Base Address Sheet 2 of 2 Size 32 bit Default 00000000h Power Well Access i M Offset Start 48h PCI Configuration B D F X 31 0
414. the count is increased by the number of responses received in the frame 9 3 2 1 25 Offset 5Ch RIRBCTL RI RB Control Register Table 250 5Ch RIRBCTL RIRB Control Register Size 8 bit Default 00h Power Well Core Access PCI Configuration B D F 0 27 0 Offset Start 5Ch Offset End 5Ch Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 07 03 0 RO RSVD Reserved 02 0 RW RIRBOIC Response Overrun Interrupt Control If this bit is set the hardware will generate an interrupt when the Response Overrun Interrupt Status bit LBAR 5Dh bit 2 is set 01 0 RW RIRBRUN Enable RI RB DMA Engine 0 DMA Stop 1 DMA Run After software writes a 0 to this bit the hardware may not stop immediately The hardware will physically update the bit to a 0 when the DMA engine is truly stopped Software must read a 0 from this bit to verify that the DMA is truly stopped 00 0 RW RINTCTL Response Interrupt Control O Disable Interrupt 1 Generate an interrupt after N number of Responses are sent to the RIRB buffer OR when an empty Response slot is encountered on all HDA SDI x inputs whichever occurs first The N counter is reset when the interrupt is generated Intel Atom Processor E6xx Series Datasheet 171 intel Intel High Definition Audio D27 FO 9 3 2 1 26 Offset 5Dh RI
415. the lower base of the protected range Address bits 11 0 000h RW Special PRB are assumed to be 000h for the base comparison Any address less than the value programmed in this field is unaffected by this protected range Intel Atom Processor E6xx Series Datasheet 255 11 9 5 12 11 9 5 12 1 Running SPI Cycles from the Host Memory Reads Memory Reads to the BIOS Range result in a READ command 03h with the lower 3 bytes of the address delivered in the SPI cycle By sending the entire 24 bits of address out to the SPI interface unchanged the processor hardware can support various flash memory sizes without having straps or automatic detection algorithms in hardware The flash memory device must ignore the upper address bits such that an address of FFFFFFh simply aliases to the top of the flash memory This is true for all supported flash devices When considering additional flash parts this behavior should be checked For compatibility with the FWH interface the SPI interface supports decoding the two 64 KB BIOS ranges at the E0000h and F0000h segments just below 1 MB These ranges must be re directed aliased to the ranges just below 4 GB by the processor This is done by forcing the upper address bits 23 20 to 1 s when performing the read on the SPI interface When the SPI Prefetch Enable bit in Offset D8h BC BIOS Control Register is set the processor checks if the starting address for a read is aligned to th
416. the other bits are set to 0 s For the slave controller ICW3 is the slave identification code used during an interrupt acknowledge cycle On interrupt acknowledge cycles the master controller broadcasts a code to the slave controller if the cascaded interrupt won arbitration on the master controller The slave controller compares this identification code to the value stored in its ICW3 and if it matches the slave controller assumes responsibility for broadcasting the interrupt vector ICWA The final write in the sequence I CW4 must be programmed in both controllers At the very least bit 0 must be set to a 1 to indicate that the controllers are operating in an Intel architecture based system Operation Command Words OCW These command words reprogram the Interrupt Controller to operate in various interrupt modes OCW1 masks and unmasks interrupt lines OCW2 controls the rotation of interrupt priorities when in rotating priority mode and controls the EOI function OCW3 is sets up ISR IRR reads enables disables the Special Mask Mode SMM and enables disables polled interrupt mode Modes of Operation Fully Nested Mode In this mode interrupt requests are ordered in priority from O through 7 with O being the highest When an interrupt is acknowledged the highest priority request is determined and its vector placed on the bus Additionally the ISR for the interrupt is set This ISR bit remains set until the CP
417. this not VSSSEMNSE adding to the total bump count Intel Atom Processor E6xx Series Datasheet 44 88 Pin States 3 0 3 1 Table 19 3 2 Table 20 intel Pin States This chapter describes the states of each Intel Atom Processor E6xx Series signal in and around reset It also documents what signals have internal pull up pull down series termination resistors and their values Pin Reset States Reset State Definitions Buffer Type Buffer Description Hiah Z The processor places this output in a high impedance state For lOs external drivers are 9 not expected The state of the input driven or tri stated does not affect the processor For IO it is Don t Care CH Nar assumed the output buffer is in a high impedance state Vou The processor drives this signal high VoL The processor drives this signal low VOX known The processor drives this signal to a level defined by internal function configuration VOX unknown The processor drives this signal but to an indeterminate value Vin The processor expects requires the signal to be driven high VIL The processor expects requires the signal to be driven low pull up This signal is pulled high by a pull up resistor internal or external pull down This signal is pulled low by a pull down resistor internal or external VIX unknown The processor expects the signal to be driven by an external source but the
418. this bit is set 09 Ob RO RSVD Reserved SERR_B Enable When set this enables the root port to generate 08 Ob RW SEE SERR B when PSTS SSE is set 07 03 00000b RO RSVD Reserved Bus Master Enable When set allows the root port to forward cycles 02 Ob RW BME onto the backbone from a PCI Express device When cleared all cycles from the device are master aborted Memory Space Enable When set memory cycles within the range 01 Ob RW MSE specified by the memory base and limit registers can be forwarded to the PCI Express device When cleared these memory cycles are master aborted on the backbone 1 O Space Enable When set I O cycles within the range specified by 00 Ob RW IOSE the I O base and limit registers can be forwarded to the PCI Express device When cleared these cycles are master aborted on the backbone 8 2 1 4 PSTS Primary Status This register reports the occurrence of error conditions associated with the primary side of the virtual Host PCI Express bridge embedded within the processor Intel Atom Processor E6xx Series Datasheet 114 PCI Express Table 130 Offset 06h PSTS Primary Status Size 16 bit Default 0010h Power Well Core Access e Offset Start 6h PCI Configuration B D F 0 23 26 0 Offset End 7h Bit Range Default Access Acronym Description 15 Ob RO RSVD Reserved Signaled System Error This bit is set when this device sends an SERR d
419. ting to the Dock Attach bit Software shall only change the DA bit from 0 to 1 when DM 0 Likewise software shall only change the DA bit rrom 1 to 0 when DM 1 If these rules are violated the results are undefined Note that this bit is reset on RESET_B This bit is not reset on CRST_B Note that this bit is Read Only when the DCKSTS DS bit 0 Intel Atom Processor E6xx Series Datasheet 147 intel Intel High Definition Audio D27 FO 9 3 1 19 Offset 4Dh DCKSTS Docking Status Register Table 196 4Dh DCKSTS Docking Status Register Size 8 bit Default 80h Power Well Core Access e Med Offset Start 4Dh PCI Configuration B D F 0 27 0 Offset End 4Dh Bit Range Default Access Acronym Description Docking Supported A 1 indicates that the processor supports Intel HD Audio Docking The DCKCTL DA bit is only writable when this DS bit is 1 Intel HD AudioP driver software should only branch to its docking routine when ni DS bit is 1 BIOS may clear this bit to 0 to prohibit the 07 1 RWO DS Intel HD Audio driver software from attempting to run the docking routines Note that this bit is reset to its default value only on a RESET B but not on a CRST B or D3hot to DO transition 06 01 0 RO RSVD Reserved Dock Mated This bit effectively communicates to software that an Intel HD Audio docked codec is phys
420. tionality feature set required to successfully bring up the system Hence it does not represent the optimal system configuration It is the responsibility of the system initialization software to determine configuration operating parameters and optional system features that are applicable and to program the processor registers accordingly 5 2 Introduction The Intel Atom Processor E6xx Series contains two sets of software accessible registers accessed via the host processor I O address space Control registers and internal configuration registers Intel Atom Processor E6xx Series Datasheet 53 a n tel Register and Memory Mapping Note 5 3 Control registers are I O mapped into the processor I O space that controls access to PCI and PCI Express configuration space e Internal configuration registers residing within the processor are partitioned into nine logical device register sets one for each PCI device listed in Table 39 These are logical devices because they reside within a single physical device The processor s internal registers I O Mapped Configuration and PCI Express Extended Configuration registers are accessible by the host processor The registers that reside within the lower 256 bytes of each device can be accessed as Byte Word 16 bit or DWord 32 bit quantities with the exception of CONFIG_ADDRESS which can only be accessed as a DWord All multi byte numeric field
421. transform and light a triangle or vertex are explained below Vertex Transform Stages Local space Relative to the model itself e g using the model center at the reference point Prior to being placed into a scene with other objects World space transform LOCAL to WORLD This is needed to bring all objects in the scene together into a common coordinate system Camera space transform WORLD to CAMERA also called EYE This is required to transform the world in order to align it with camera view In OpenGL the local to world and world to camera transformation matrix is combined into one called the ModelView matrix Clip space transform CAMERA to CLI P The projection matrix defines the viewing frustum onto which the scene will be projected Projection can be orthographic or perspective Clip is used because clipping occurs in clip space Perspective space transform CLI P to PERSPECTI VE The perspective divide is basically what enables 3D objects to be projected onto a 2D space A divide is necessary to represent distant objects as smaller on the screen Coordinates in perspective space are called normalized device coordinates 1 1 in each axis Screen space transform PERSPECTIVE to SCREEN This space is where 2D screen coordinates are finally computed by scaling and biasing the normalized device coordinates according to the required render resolution Lighting Stages Lighting is used to generate
422. treams Notes I All other values are Not Supported 2 When the output stream is programmed to an unsupported size the hardware sets itself to the default value BFh 3 Software must read the bit field to test if the value is supported after setting the bit field For Input Stream FIFOS is a RO field with the following value 8 16 32 bit Input Streams 120B 77h 20 24 bit Input Streams 160B 9Fh Note the default value is different for input and output streams and reflects the default state of the BITS fields in Stream Descriptor Format registers for the corresponding stream 9 3 2 1 40 Table 265 Offset 92h B2h D2h F2h ISDOFMT ISD1FMT OSDOFMT OSD1FMT I nput Output Stream Descriptor 0 1 Format Register 92h B2h D2h F2h ISDOFMT ISD1FMT OSDOFMT OSDIFMT Input Output Stream Descriptor 0 1 Format Register Sheet 1 of 2 Size 16 bit Default 0000h Power Well Core Access PCI Configuration B D F 0 27 0 Offset Start 92h B2h D2h F2h Offset End 93h B3h D3h F3h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 15 0 RO RSVD Reserved 14 RW BASE Sample Base Rate 0 48 kHz 1 44 1 kHz Intel Atom Processor E6xx Series Datasheet 180 Intel High Definition Audio D27 FO intel
423. treams Supported 0010b indicates that the 11 08 0010 RO ISS processor Intel HD Audio controller supports two output streams Number of Bidirec tional Streams Supported 00000b indicates that 07 03 00000 RO BSS the processor Intel HD Audio controller supports 0 bidirectional streams 02 0 RO RSVD Reserved mber of Serjal Data Out Signals 00b indicates that the processor 01 0 RO NSDO HD Audio controller supports one Serial Data Output signal face 64 Bit Address Supported A 1 indicates that the processor Intel HD 00 0 RO AudioP controller supports 64 bit addressing for BDL addresses data buffer addresses and command buffer addresses 9 3 2 1 2 Offset 02h VMI N Minor Version Register Table 227 02h VMIN Minor Version Register Size 8 bit Default 00h Power Well Core Access DE 0 97 Offset Start 02h PCI Configuration B D F 0 27 0 Offset End 02h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description Minor Version Indicates that the processor supports minor revision 07 00 00h RO MMIN number 00h of the Intel HD Audio specification Intel Atom Processor E6xx Series Datasheet 160 Intel High Definition Audio D27 FO j n tel 9 3 2 1 3 Offset 03h VMAJ Major Version Table 228 03h VMAJ
424. triggered interrupts if an interrupt is pending when this bit is cleared the GIS Tx will not be cleared Intel Atom Processor E6xx Series Datasheet 207 intel ACPI Devices 11 2 1 3 Offset 020h GIS General I nterrupt Status Table 306 020h GIS General Interrupt Status Size 64 bit Default Power Well Core Access gt T Offset Start 020h PCI Configuration B D F Offset End 027h Bit Range Default Access Acronym Description 63 03 0 RO RSVD Reserved 02 0 RWC T2 Timer 2 Status Same functionality as TO for timer 2 01 0 RWC Tl Timer 1 Status Same functionality as TO for timer 1 00 0 RWC TO Timer O Status n edge triggered mode this bit always reads as 0 In level triggered mode this bit is set when an interrupt is active 11 2 1 4 Offset OFOh MCV Main Counter Value Table 307 OFOh MCV Main Counter Value Size 64 bit Default Power Well Core Access T Offset Start OFOh PCI Configuration B D F Offset End OF7h Bit Range Default Access Acronym Description Counter Value Reads return the current value of the counter Writes 63 00 0 RW Cv load the new value to the counter Timers 1 and 2 return O for the upper 32 bits of this register 11 2 1 5 Offset 100h 120h 140h T 0 2 C Timer 0 2 Config and Capabilities Table 308 100h 120h 140h T 0 2 C Timer 0 2 Config a
425. troller is treated as an interrupt acknowledge cycle An encoded byte is driven onto the data bus representing the highest priority level requesting service Register Read Command These bits provide control for reading the ISR and Interrupt IRR When bit 1 0 bit O will not affect the register read selection Following ICW initialization the default OCW3 port address read will be read IRR To retain the current selection read ISR or read IRR always write a 0 to bit 1 when programming this register The selected register can be read repeatedly without reprogramming 01 00 10 WO RRC OCW3 To select a new status register OCW3 must be reprogrammed prior to attempting the read 00 No Action 01 No Action 10 Read IRQ Register 11 Read IS Register 11 3 2 8 Offset 4DOh ELCR1 Master Edge Level Control Table 322 4DOh ELCR1 Master Edge Level Control Size 8 bit Default Power Well Core Access Offset Start 4DOh PCI Configuration B D F Offset End Bit Range Default Access Acronym Description Edge Level Control In edge mode bit cleared the interrupt is 07 03 0 RW ECL 7 3 recognized by a low to high transition In level mode bit set the interrupt is recognized by a high level 02 00 0 RO RSVD Reserved The cascade channel IRQ2 heart beat timer IRQO and keyboard controller IRQ1 cannot be put into level mode Intel Atom Processor E6xx Series Datasheet 217 i n tel j ACPI Devices 11 3 2 9 Offs
426. ts the system memory address map in a simplified form Intel Atom Processor E6xx Series Datasheet 54 Register and Memory Mapping Figure 3 Table 36 System Address Map 4GB PCI Memory Address Range Top of Memory 2GB 1 MB Legacy Address Range 0 Memory Map Sheet 1 of 2 Device Start Address End Address Comments Legacy Address Range 0 to 1 MB DOS DRAM 00000000 0009FFFF Legacy Video VGA 000A0000 OOODFFFF PAM 000E0000 OOOEFFFF PAM 000F0000 OOOFFFFF BIOS LPC 000F0000 OOOFFFFF LPC 000E0000 OOOFFFFF Provided PAM is not enabled Main Memory 1 MB to TOM TSEG Variable Variable Graphics Variable Variable PCI Configuration Space 2 GB to 4 GB IOxAPIC FECO0000 FECO0040 HPET FEDOOOOOh FEDOO3FFh High Performance Event Timer Intel Trusted Platform Module 1 2 FED40000 FED4BFFF LPC Intel Atom Processor E6xx Series Datasheet 55 intel Table 36 Note Note 5 3 1 5 3 1 1 Table 37 Memory Map Sheet 2 of 2 Register and Memory Mapping Device Start Address End Address Comments The Chipset Microcode CMC base address lives within the LPC space High BIOS FFC00000 FFFFFFFF and consumes 64 kB of space Make sure to avoid using the same starting address for other LPC devices in the system Configurable Main Memory Configuration Spaces PCI Express Port 0 Anywhere in 32 bit range Configured
427. ts to cool the processor by first reducing the core toa specific bus ratio then stepping down the VID Intel Hyper Intel Hyper Threading Technology Intel HT Technology enables two logical processors Threading in a core Technology Intel HT Intel Thermal Monitor Intel Thermal Monitor is a feature of the Intel Atom Processor E6xx Series The Intel Thermal Monitor contains the Thermal Control Circuit TCC When the Monitor is enabled and active due to the die temperature reaching the pre determined activation temperature the TCC attempts to cool the processor by stopping the processor clocks for a period of time and then allowing them to run full speed for a period of time duty cycle 30 50 until the processor temperature drops below the activation temperature LCD Liquid Crystal Display LVDS Low Voltage Differential Signaling LVDS is a high speed low power data transmission standard used for display connections to LCD panels MPEG Moving Picture Experts Group MSI Message Signaled Interrupt MSI is a transaction initiated outside the host conveying interrupt information to the receiving agent through the same path that normally carries read and write commands MSR Model Specific Register as the name implies is model specific and may change from processor model number n to processor model number n 1 An MSR is accessed by setting ECX to the register number and
428. turned off during sleep mode S3 and higher Nine of these GPIOs are powered by the suspend power well and remained active during S3 Five of the GPIOs in suspend power well can be used to wake the system from the Suspend to RAM state provided that current OS will not clear the GPEOE register before entering S3 state The five GPIOs that can be use are GPIO SUS 1 GPIO SUS 2 GPIO SUS 3 GPIO SUS 4 and GPIO SUS 7 GPIO SUS 4 1 can be use to wake the system from Suspend to RAM state provided LVDS is disabled on the platform as these signals are being used by LVDS display The GPIOs are not 5 V tolerant Serial Peripheral I nterface SPI The Intel Atom Processor E6xx Series contains an SPI interface that supports boot from SPI flash This interface only supports BIOS boot Power Management The Intel Atom Processor E6xx Series contains a mechanism to allow flexible configuration of various device maintenance routines as well as power management functions including enhanced clock control and low power state transitions e g Suspend to RAM and Suspend to Disk A hardware based thermal management circuit permits software independent entrance to low power states The processor contains full support for the Advanced Configuration and Power Interface ACPI Specification Revision 3 0 Intel Atom Processor E6xx Series Datasheet 29 intel 1 3 14 1 3 15 1 3 16 1 3 17 Table 2 Introduction Watchdog Ti
429. ue to detecting an ERR_FATAL or ERR_NONFATAL condition and the 14 Ob RWC SSE SERR Enable bit in the Command register is 1 Both received if enabled by BCTRL1 1 and internally detected error messages do not effect this field 13 05 000000 RO RSVD Reserved 04 1b RO CLIST Capabilities List ndicates the presence of a capabilities list Interrupt Status Indicates status of hot plug and power management 03 Ob RO IS interrupts on the root port that result in INTx B message generation This bit is set regardless of the state of CMD ID 02 00 000b RO RSVD Reserved 8 2 1 5 RI D Revision Identification This register contains the revision number of the device These bits are read only and writes to this register have no effect Table 131 Offset O8h RI D Revision dentification Size 8 bit Default Refer to bit description Power Well Core Access Offset Start 8h PCI Configuration B D F 0 23 26 0 Offset End 8h Bit Range Default Access Acronym Description s ias Revision Identification Number This is an 8 bit value that indicates 07 00 descript RO RID1 the revision identification number for the device For the B 0 Stepping ion H this value is O1h For B 1 Stepping this value is 02h 8 2 1 6 CC Class Code This register identifies the basic function of the device a more specific sub class and a register specific programming interface Table 132 Offset 09h CC Class Code
430. ulting timer clock is the PCI Clock 33 MHz divided by 215 The approximate clock generated is 1 KHz 1 ms to 10 min Default 1 The 20 bit Preload Value is loaded into bits 24 05 of the main down counter The resulting timer clock is the PCI Clock 33 MHz divided by 25 The approximate clock generated is 1 MHz 1 us to 1 sec 01 00 00h RW RSVD Reserved 11 10 3 10 Offset 14h DCRO Down Counter Register 0 Table 397 14h DCRO Down Counter Register 0 Size 8 bit Default 00h Power Well Core PERSE PCI Configuration B D F Ofset start 14h Offset End 14h IAF Base Address Base 10 Offset 14h Bit Range Default Access Acronym Description Down Counter 7 0 The Down Counter register holds the bits 0 through 7 of upper 20 bits of the 35 bit down counter that is continuously decremented The values from Preload Registers are loaded 07 00 00h RO DCNT_7_0 into the Down Counter every time the WDT enters stage The down counter decrements using a 33 MHz clock Any reads to this register return an indeterminate value This register is to be indicated as reserved Intel Atom Processor E6xx Series Datasheet 268 ACPI Devices 11 10 3 11 Offset 15h DCR1 Down Counter Register 1 Table 398 15h DCR1 Down Counter Register 1 Size 8 bit Default 00h Power Well Core WE PCI Configuration B D F Offset Start 15h Offset End 15h
431. uration cycle with the fields shown in Table 41 Intel Atom Processor E6xx Series Datasheet 59 intel Register and Memory Mapping Table 41 PCI Configuration Memory Bar Mapping Field Configuration Cycle Bits Memory Cycle Bits Bus Number 31 24 27 20 Device Number 23 19 19 15 Function Number 18 16 14 12 Register Number 11 02 11 02 5 5 Bridging and Configuration This describes all registers and base functionality that is related to chipset configuration and not a specific interface It contains the root complex register block This block is mapped into memory space using RCBA Accesses in this space are limited to 32 bit quantities Burst accesses are not allowed 5 5 1 Root Complex Topology Capability Structure The following registers follow the PCI Express capability list structure as defined in the PCI Express specification to indicate the capabilities of the component Table 42 PCI Express Capability List Structure Start End Symbol Register Name 0000 0003 RCTCL Root Complex Topology Capability List 0004 0007 ESD Element Self Description 0010 0013 HDD Intel High Definition Audio Description port 15 0014 0017 Reserved Reserved 0018 008F HDBA Intel High Definition Audio Base Address port 15 5 5 1 1 Offset 0000h RCTCL Root Complex Topology Capabilities List Table 43 0000h RCTCL Root Complex Topology Capabilities List Size 32 bit
432. uration registers 16 Kbytes are requested by hardwiring bits 13 4 to O s 13 04 0 RO Hardwired to 0 03 0 RO PREF Prefetchable Indicates that this BAR is NOT pre fetchable e Address Range Indicates that this BAR can be located anywhere in 32 02 01 10 RO ADBRNG bit address space 00 0 RO RTE Resource Type Indicates that this BAR is located in memory space 9 3 1 11 Offset 14h UBAR Upper Base Address Register Table 188 14h UBAR Upper Base Address Register Size 32 bit Default 00000000h Power Well Core Access D F 0 27 Offset Start 14h PCI Configuration B D F 0 27 0 Offset End 17h Bit Range Default Access Acronym Description Upper Base Address Upper 32 bits of the Base address for the Intel 31 00 0 RW UBA HD Audio controller s memory mapped configuration registers 9 3 1 12 Offset 2Ch SVI D Subsystem Vendor Identifier This register should be implemented for any function that could be instantiated more than once in a given system for example a system with 2 audio subsystems one down on the motherboard and the other plugged into a PCI expansion slot should have the SVID register implemented The SVID register in combination with the Subsystem ID register enables the operating environment to distinguish one audio subsystem from the other Software BIOS will write the value to this register After that the value can be read but writes to the register will have no effect The write to this register should be combined w
433. urns the latched count Subsequent reads return an unlatched count Intel Atom Processor E6xx Series Datasheet 202 ACPI Devices Table 299 43h RBC Read Back Command Size 8 bit Default XXXXXXX0b Power Well Core Fixed IO Address 43h Bit Range Default Access Acronym Description 07 06 00 RW RBC Read Back Command Must be 11 to select the Read Back Command Latch Count When cleared the current count value of the selected 05 0 RW LC counters will be latched 04 0 RW LS Lateh Status When cleared the status of the selected counters will be 03 0 RW C2S countar 2 Select When set to 1 Counter 2 count and or status will be 02 0 RW C1S counter 1 Select When set to 1 Counter 1 count and or status will be 01 0 RW COS counter O Select When set to 1 Counter O count and or status will be 00 0 RO RSVD Reserved 11 1 5 2 Counter Latch Command This latches the current count value and is used to ensure the count read from the counter is accurate The count value is then read from each counter s count register through the Counter Ports Access Ports Register 40h for counter 0 41h for counter 1 and 42h for counter 2 The count must be read according to the programmed format i e if the counter is programmed for two byte counts two bytes must be read The two bytes do not have to be read one right after the other read write or programming op
434. us Byte Format OXXXXXXXb Read Only et Counter 2 Counter Access Port Register Undefined Read Write Timer Control Word Register Undefined Write Only 43h 53h Timer Control Word Register Read Back XXXXXXXOb Write Only Counter Latch Command XOh Write Only Offset 43h TCW Timer Control Word Register This register is programmed prior to any counter being accessed to specify counter modes Following reset the control words for each register are undefined and each counter output is 0 Each timer must be programmed to bring it into a known state Intel Atom Processor E6xx Series Datasheet 201 i n tel i ACPI Devices Table 298 43h TCW Timer Control Word Register Size 8 bit Default Undefined Power Well Core Fixed IO Address 43h Bit Range Default Access Acronym Description Counter Select The Counter Selection bits select the counter the control word acts upon as shown below The Read Back Command is selected when bits 7 6 are both 1 07 06 Undef WO CS 00 Counter 0 select 01 Counter 1 select 10 Counter 2 select 11 Read Back Command Read Write Select The counter programming is done through the SCH port 40h for counter 0 41h for counter 1 and 42h for counter 05 04 Undef wo RWS 00 Counter Latch Command 01 Read Write Least Significant Byte LSB 10 Read Write Most Significant Byte MSB 11 Read Write LSB then MSB Counter Mode Selection Selects o
435. us Control Register Table 289 Offset 5Ch MC Miscellaneous Control Sheet 1 of 3 Size 32 bit Default 00000000h Power Well Access Nath Offset Start 5Ch PCI Configuration B D F X 31 0 Offset End 5Fh Bit Range Default Access Acronym Description 31 29 Oh RW RSVD Reserved LPC Clock Frequency Select 0 1 2x of BB legacy clock 1 1x of 28 Oh RW LPCFS BB legacy clock This register value is only applicable when the LPC clock fuse is blown when the fuse bit is 0 the LPCCLK frequency is 1x irrespective of the value of this register Number of Timer Ticks to Count Indicates how many timer ticks 27 24 Oh RW NTT will be collected before a break event will be signalled to the power management controller Up to 16 timer ticks may be collected Intel Atom Processor E6xx Series Datasheet 193 i n tel S LPC Interface D31 FO Table 289 Offset 5Ch MC Miscellaneous Control Sheet 2 of 3 Size 32 bit Default 00000000h Power Well Access ay m Offset Start 5Ch PCI Configuration B D F X 31 0 Offset End 5Fh Bit Range Default Access Acronym Description 23 21 Oh RO RSVD Reserved Block Timer Ticks in C6 When set timer ticks will be blocked up to 20 0 RW BTC6 NTT while the processor is in the C6 state If not set timer ticks will not be blocked in the C6 state 31 29 Oh RW RSVD Reserved 19 0 RW BTC5 POK Timer Ticks in C5 Same definition as BTC6 but f
436. used by SBIOS not by driver DOh GVD PMCAP Power Management Capabilities Power Management Control Status Driver does not use this register Dahi GVD PMCS SBIOS doesn t use this register EOh GVD SWSMISCI Software SMI or SCI E4h GVD ASLE System Display Event Register SBIOS writes this register to generate an interrupt to the graphics display driver F4h GVD LBB Legacy Backlight Brightness The display driver in the processor does not use this register since ASLE is available GVD MANUFACTURI 1 F8h NG ID Manufacturing ID Storage The processor display driver does not need this register since FCh GVD ASLS ASL memory Operational Region OpRegion is available This register is kept for use as scratch space Intel Atom Processor E6xx Series Datasheet 90 Graphics Video and Display Table 77 00h GVD ID D2 PCI Device and Vendor ID Register Size 32 bit Default 41088086h Power Well Core Access e PRSE Offset Start 00h PCI Configuration B D F 0 2 0 Offset End 01h Message Bus Port 06h Register Address 00h Bit Range Default Access Acronym Description 1 DIDH Identifier assigned to the Device 2 Graphics PCI device 31 20 410h RO Bits 31 20 of this register are strapped at the processor top level DD DIDL Identifier assigned to the Device 2 Graphics PCI device 19 16 z RO Bits 19 16 of this register are determined by fuse
437. value the data samples are loaded into the FIFO associated with this descriptor 23 20 0 RW STRM Note that while a single HDA SDI x input may contain data from more than one stream number two different HDA SDI x inputs may not be configured with the same stream number 0000 Reserved Indicates Unused 0001 Stream 1 1110 Stream 14 1111 Stream 15 19 0 RO DIR Bidirectional Direction Control This bit is only meaningful for Bidirectional streams Therefore this bit is hardwired to 0 18 1 RO TP Traffic Priority Hardwired to 1 indicating that all streams will use VC1 if it is enabled throughout the PCI Express registers e Stripe Control This field is meaningless for input streams Therefore it 17 16 00 RO STRIPE is hardwired to O s 15 05 0 RO RSVD Reserved Descriptor Error Interrupt Enable 04 0 RW DEIE GE ca MR l 1 An interrupt is generated when the Descriptor Error Status DESE bit is set FI FO Error Interrupt Enable This bit controls whether the occurrence of a FIFO error overrun for input or underrun for output will cause an 03 0 RW FEIE interrupt or not If this bit is not set bit 3 in the Status register will be set but the interrupt will not occur Either way the samples will be dropped Interrupt On Completion Enable This bit controls whether or not an 02 0 RW IOCE interrupt occurs when a buffer completes with the I OC bit set in its descriptor If this bit is not set bit 2 in the Status register will be set but the
438. vanced Digital Display 2 An interface specification that accepts serial DVO inputs and translates them into different display outputs such as DVO TVOUT and LVDS Full reset is when PWROK is de asserted and all system rails except VCCRTC are powered Cold Reset d own Core A core is a processing unit that may include one or more logical processors with or without Intel Hyper Threading Technology Intel HT Technology CRT Cathode Ray Tube CRU Clock Reset Unit DDR2 A second generation Double Data Rate SDRAM memory technology DVI Digital Video Interface DVI is a specification that defines the connector and interface for digital displays EIOB Electronic In Out Board High Definition Multimedia Interface HDMI supports standard enhanced or high definition video plus multi channel digital audio on a single cable HDMI transmits all Advanced HDMI Television Systems Committee ATSC HDTV standards and supports 8 channel digital audio with bandwidth to spare for future requirements and enhancements additional details available at http www hdmi org IA Intel architecture IGD Internal Graphics Unit Intel Thermal Monitor 2 is a feature of the Intel Atom Processor E6xx Series The Intel Intel Thermal Monitor 2 contains the Enhanced Thermal Control Circuit TCC When the Monitor is Thermal enabled and active due to the die temperature reaching the pre determined activation Monitor 2 temperature the Enhanced TCC attemp
439. ve high to the CPU if an asserted interrupt is not masked 3 The CPU acknowledges the INTR and responds with an interrupt acknowledge cycle 4 Upon observing the special cycle 8259 converts it into the two cycles that the internal 8259 pair can respond to Each cycle appears as an interrupt acknowledge pulse on the internal INTA pin of the cascaded interrupt controllers 5 Upon receiving the first internally generated INTA pulse the highest priority ISR bit is set and the corresponding IRR bit is reset On the trailing edge of the first pulse a slave identification code is broadcast internally by the master 8259 to the slave 8259 The slave controller uses these bits to determine if it must respond with an interrupt vector during the second INTA pulse 6 Upon receiving the second internally generated INTA pulse the 8259 returns the interrupt vector If no interrupt request is present the 8259 will return vector 7 from the master controller 7 This completes the interrupt cycle In AEOI mode the ISR bit is reset at the end of the second INTA pulse Otherwise the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine Initialization Command Words I CW Before operation can begin each 8259 must be initialized In the Intel Atom Processor E6xx Series this is a four byte sequence to ICWI1 ICW2 ICW3 and ICWA4 The address for each 8259 initialization command word is a fixe
440. vector information Intel Atom Processor E6xx Series Datasheet 120 PCI Express n tel Table 146 Offset 3Ch ILINE Interrupt Line Size 8 bit Default 00h Power Well Core Access e g Offset Start 3Ch PCI Configuration B D F 0 23 26 0 Offset End 3Ch Bit Range Default Access Acronym Description I nterrupt Line This software written value indicates to which interrupt 07 00 00h RW ILINE line vector the interrupt is connected No hardware action is taken on this register 8 2 1 21 IPIN Interrupt Pin This register specifies which interrupt pin this device uses Table 147 Offset 3Dh IPIN Interrupt Pin Size 8 bit Default 01h Power Well Core Access e e g Offset Start 3Dh PCI Configuration B D F 0 23 26 0 Offset End 3Dh Bit Range Default Access Acronym Description I nterrupt Pin IPI N This indicates the interrupt pin driven by the root port At reset this register takes on the following values which reflect the reset state of the D23 24 25 261P register in chipset configuration Space Port Bits 15 12 Bits 11 08 07 00 Olh RO IPIN 0 Oh D231P P11P 1 Oh D24IP P1IP 2 Oh D25IP P1IP 3 Oh D26IP P1IP The value that is programmed into Interrupt Pin Configuration register is always reflected in this register 8 2 1 22 BCTRL Bridge Control This register provides extensions to the PCI CMD1 register that are specif
441. via D23 FO MB ML PCI Express Port 0 prefetchable Anywhere in 32 bit range Configured via D23 FO PMB PML PCI Express Port 1 Anywhere in 32 bit range Configured via D24 FO MB ML PCI Express Port 1 prefetchable Anywhere in 32 bit range Configured via D24 FO PMB PML PCI Express Port 2 Anywhere in 32 bit range Configured via D25 FO MB ML PCI Express Port 2 prefetchable Anywhere in 32 bit range Configured via D25 FO PMB PML PCI Express Port 3 Anywhere in 32 bit range Configured via D26 FO MB ML PCI Express Port 3 prefetchable Anywhere in 32 bit range Configured via D26 FO PMB PML Root Complex Base Register 16 kB anywhere in the 32 bit range Configured via D31 FO RCBA Intel High Definition AudioP 16 kB anywhere in 32 bit range Configured via D27 F0 LBAR UBAR Display 512 kB anywhere in 32 bit range Configured via D3 F0 MMBAR All accesses to addresses within the main memory range will be forwarded to the DRAM unless they fall into one of the optional ranges specified in this section Boot with the LPC interface is not validated I O Map The I O map is divided into separate types Fixed ranges cannot be moved but some may be disabled while variable ranges can be moved Fixed I O Address Range Table 37 shows the fixed I O decode ranges from the CPU perspective Fixed I O Range Decoded
442. w are specified in by applicable JEDEC standard and MAS document Non adherence may affect component reliability Tstorage applies to the unassembled component only and does not apply to the shipping media moisture barrier bags or desiccant Intel branded board products are certified to meet the following temperature and humidity limits that are given as an example only Non Operating Temperature Limit 40 C to 70 C amp Humidity 5096 to 90 non condensing with a maximum wet bulb of 28 C Post boatrd attach storage temperature limits are not specified for non Intel branded boards The J EDEC J JSTD 020 moisture level rating and associated handling practices apply to all moisture sensitive devices removed from the moisture barrier bag Nominal temperature and humidity conditions and durations are given and tested within the constraints imposed by Tsystainep and customer shelf life in applicable Intel box and bags 88 Intel Atom Processor E6xx Series Datasheet 274 DC Characteristics 13 0 13 1 Table 402 DC Characteristics Signal Groups The signal description includes the type of buffer used for the particular signal Please refer to the Chapter 2 0 for signals detail Memory Controller Buffer Types Buffer Type Description AGTL Assisted Gunning Transceiver Logic Plus Open Drain interface signals that require termination Refer to the AGTL I O Specification for comple
443. ware The streams are numbered and the SSYNC bits assigned sequentially based on their order in the register set Bit 3 Output Stream 2 OS2 Bit 2 Output Stream 1 OS1 Bit 1 Input Stream 2 1S2 Bit 0 Input Stream 1 IS1 Intel Atom Processor E6xx Series Datasheet 167 intel Intel High Definition Audio D27 FO 9 3 2 1 16 Offset 40h CORBBASE CORB Base Address Register Table 241 40h CORBBASE CORB Base Address Register Size 32 bit Default 0000_0000h Power Well Core Access e BEE Offset Start 40h PCI Configuration B D F 0 27 0 Offset End 43h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description CORB Base Address Thiis neid is the adaress or the command Output Ring Buffer allowing the RB Base Address to be assigned on any 128 31 07 0 RW CORBBASE B boundary This register field must not be written when the DMA engine is running or the DMA transfer may be corrupted 06 00 0 RO RSVD Reserved 9 3 2 1 17 Offset 48h CORBWP CORB Write Pointer Register Table 242 48h CORBWP CORB Write Pointer Register Size 16 bit Default 0000h Power Well Core Access e T eH Offset Start 48h PCI Configuration B D F 0 27 0 Offset End 49h Memory Mapped IO BAR LBAR Offset Bit Range Default Access Acronym Description 15 08 0 RO RSVD Reserved CORB Write Pointer Software writes the last valid CORB entry offset into this
444. ways be written as a O for write cycle however it will return a 1 for read cycles 06 X RW RSVD eg This bit always returns a O and should be set to O for write Date Alarm These bits store the date of month alarm value If set to 05 00 X RW DA 000000 then a don t care state is assumed If the date alarm is not R enabled these bits will return zeros to mimic the functionality of the Motorola 146818B These bits are not affected by any reset assertion 11 6 4 Update Cycles An update cycle occurs once a second if B SET bit is not asserted and the divide chain is properly configured During this procedure the stored time and date will be incremented overflow will be checked a matching alarm condition will be checked and the time and date will be rewritten to the RAM locations The update cycle will start at least 488us after A UIP is asserted and the entire cycle will not take more than 1984us to complete The time and date RAM locations 0 9 will be disconnected from the external bus during this time 11 6 5 Interrupts The RTC interrupt is internally routed to interrupt 8 and is not it shared with any other interrupt RQ8 from SERIRQ is ignored The HPET can also be mapped to IRQ8 in this case the RTC interrupt is blocked Intel Atom Processor E6xx Series Datasheet 233 intel ACPI Devices 11 7 General Purpose I O 11 7 1 Core Well GPIO 1
445. wer GND 1 0 GTL VREF IOGTLREF A Core 1kQz gt 1 pullup to VIPO5 S and 1 KQ 1 pull down to GND Connect to VCCP DLIOGTLREF P Core 1 kQ 1 pullup to VIPO5 S and 2 kQ 1 pull down to ower GND VNNSENSE Voltage sense Connects to Intel MVP 6 Voltage VCC_VSSSENSE X Core Regulator must connect feedback lines for VCC VSS VCCSENSE and VNN to these pins on the package Thermal THRMDA A Passiy Thermal Diode Anode THRMDC A a Thermal Diode Cathode Oscillator Clock This signal is used for 8254 timers and HPET It runs at 14 31818 MHz This clock stops and should CLK14 CMOS3 3 Core be low during S3 S4 and S5 states CLK14 must be accurate to within 500 ppm over 100 us and longer periods to meet HPET accuracy requirements Speaker The SPKR signal is the output of counter 2 and is o internally ANDed with Port 61h bit 1 to provide Speaker Data SPKR CMOS3 3 Core Enable This signal drives an external speaker driver device which in turn drives the system speaker Upon SLPMODE its output state is 0 SMI B l Core System Management I nterrupt This signal is generated CMOS3 3 by the external system management controller Intel Atom Processor E6xx Series Datasheet 41 intel Signal Description Table 15 Miscellaneous Signals and Clocks Sheet 4 of 4 Signal Name di sitet Description THRM B ss Core er N by external hardware to CRU PLL Eon MOS Core Reference clock Hos
446. whether to enable the counter for the high time of the clock While the bus is still low the high time counter must not be enabled The low period of the clock can be stretched by an SMBus master if it is not ready to send or receive data Intel Atom Processor E6xx Series Datasheet 245 intel DN 11 8 5 2 11 8 6 11 9 11 9 1 11 9 2 11 9 3 Table 368 Bus Time Out If there is an error in the transaction such that a device does not signal an acknowledge or holds the clock lower than the allowed time out time the transaction will time out The processor will discard the cycle and set HSTS DE The time out minimum is 25 ms The time out counter inside the processor will start when the first bit of data is transferred by the processor SMI The system can be set up to generate SMI by setting HCTL SE Serial Peripheral I nterface Overview The Serial Peripheral Interface SPI is a 4 pin interface that provides a potentially lower cost alternative for system flash versus the Firmware Hub interface that is available on the LPC pins Features Goals for the SPI Architecture in the Product Support for Multiple SPI Flash Vendors Simple Hardware Equivalence to LPC Based firmware hubs Provide write protection scheme Equivalent performance boot time resume time Top swap functionality Support for E amp F segments below 1 MB 64 kb granular protection Max SPI flash size ad
447. will be cleared to reflect this state When the CRST B bit is de asserted the dock state machine will detect that DCKCTL DA is set to 1 and will begin sequencing through the dock process Note that this does not require any software intervention Intel Atom Processor E6xx Series Datasheet 139 Intel High Definition Audio D27 FO 9 2 4 External Pull Ups Pull Downs The following table shows the resistors that should be mounted on the dock side of the isolation switch The resistors are used to discharge the signals to reduce the chance of getting charge sharing induced glitches when the switch is turned on via HDA_DOCK_EN_B assertion Pull downs have been specified to match the level of the signals when HDA_DOCK_EN_B is asserted as well as to not conflict with the internal resistors Table 176 External Resistors Signal Internal Resistors External Resistors on Dock Side of Isolation Switch HDA_CLK Weak Pull down None HDA_SYNC None Weak Pull Down HDA_SDO None Weak Pull Down HDA_SDI from docked Weak Pull down None codec s HDA RST B None NA HDA DOCK EN B None NA HDA DOCKRST B None Weak Pull Down Note 1 Weak Pull down is about 10 kO 9 3 PCI Configuration Register Space The Intel HD Audio controller resides in PCI Device 27 Function O on Bus 0 This function contains a set of DMA engines that are used to move samples of digitally encoded data between system memory a
448. wn3 address 31 20 with MMADR 31 20 As well GVD will compare the address scldown3 address 31 29 28 or 27 with GMADR 31 29 28 or 27 respectively Whether the comparison is 31 29 31 28 or 31 27 depends on the value of MSAC 17 16 As well the GVD will check if 1 Ob RW MEMORY SPAC scldown3 address 31 0 is in the VGA memory range The VGA memory E ENABLE range is A0000h to BFFFFh If there is a match with MMADR or GMADR or VGA memory address range and if the SCL command is either a MEMRD or MEMWR the GVD will select the command i e issue a scldown3 hit Care should be taken in setting up MMADR and GMADR that more than 1 match is not made as this will result in unpredictable behavior When 0 the GVD will not select a MEMRD or MEMWR SCL command Intel Atom Processor E6xx Series Datasheet 91 intel Graphics Video and Display Table 78 04h GVD PCI CMDSTS PCI Command and Status Register Sheet 2 of 2 Size 32 bit Default 00100000h Power Well Core Access e TS Offset Start 04h PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 01h Bit Range Default Access Acronym Description IOSE When set accesses to this device s I O space is enabled When 1 the GVD will check if scldown3 address 15 0 is in the VGA IO range The VGA IO range is 03BO
449. xx Series Datasheet 155 intel Intel High Definition Audio D27 FO Table 219 120h VC1CTL VC1 Resource Control Register Sheet 2 of 2 Size 32 bit Default 0000 0000h Power Well Core Access D FE 0 27 Offset Start 120h PCI Configuration B D F 0 27 0 Offset End 123h Bit Range Default Access Acronym Description 23 08 0 RO RSVD Reserved TC VC Map This field indicates the TCs that are mapped to the VC1 07 00 00h RW RO resource Bit 0 is hardwired to O indicating it can not be mapped to VC1 j Bits 7 1 are implemented as RW bits This field is not used by the processor but it is RW to avoid confusing software 9 3 1 43 Offset 126h VC1STS VC1 Resource Status Register Table 220 126h VC1STS VC1 Resource Status Register Size 16 bit Default 0000h Power Well Core Access D F 0 27 Offset Start 126h PCI Configuration B D F 0 27 0 Offset End 127h Bit Range Default Access Acronym Description 15 00 0 RO RSVD Reserved 9 3 1 44 Offset 130h RCCAP Root Complex Link Declaration Enhanced Capability Header Register Table 221 130h RCCAP Root Complex Link Declaration Enhanced Capability Header Register Size 32 bit Default 0001 0005h Power Well Core Access D F 0 27 Offset Start 130h PCI Configuration B D F 0 27 0 Offset End 133h Bit Range Default Access Acronym Description 31
450. y the power management capability will instead indicate that this is the last item in the list FUNCTION DIS FD When set the function is disabled configuration space is disabled 0 Ob RW When set the GVD stops accepting any new requests on the SCL bus ABLE nie including any new configuration cycle requests to clear this bit Intel Atom Processor E6xx Series Datasheet 99 intel Graphics Video and Display Table 97 DOh GVD PMCAP Power Management Capabilities Size 32 bit Default 0022B001h Power Well Core Access T Offset Start DOh PCI Configuration B D F 0 2 0 Offset End Message Bus Port 06h Register Address 34h Bit Range Default Access Acronym Description 31 27 00h RO PME SUPPORT PMES The graphics controller does not generate PME 26 Ob RO D2 SUPPORT D2S The D2 power management state is not supported 25 Ob RO D1 SUPPORT D1S The D1 power management state is not supported 24 22 000b RO RESERVED Reserved DEVICE SPECI indi ial initializati 21 1b RO FIC INITIALIZA Hardwired to 1 to indicate that special initialization of the graphics TION controller is required before generic class device driver is to use it 20 19 00b RO RESERVED Reserved 18 16 010b RO VERSION bd Indicates compliance with revision 1 1 of the PCI Power Management
451. ytes requested in first DW gt 1 1000 1100 1110 1111 Don t Care Address starts from lowest requested byte 0001 0010 0011 0100 0101 gt 1 0110 0111 1001 1010 1011 Don t Care Bytes read from SPI 4 num DW 1101 When coming out of a platform reset the SPI Host Controller must hold the initial Direct Memory Read from the processor pending until the SPI flash is no longer busy with an internal write or erase instruction In order to achieve this the host controller reads the Status Register opcode 05h of the flash device until bit 0 is cleared This is equivalent to the polling performed following an atomic cycle during which the Direct Memory Reads are held pending Depending on the type of flash and type of long instruction performed the delay could be long enough to cause a watchdog time out in the processor or chipset Although this error condition is deemed acceptable in response to this rare error scenario reset during flash update it can be avoided altogether by selecting flash instructions on SPI devices that complete in less than 1 second Note that in the typical boot case the status read on the SPI interface will complete well before the processor boot fetch due to the delay from reset deassertion to CPURST deassertion Intel Atom Processor E6xx Series Datasheet 257 11 9 5 13 11 9 5 14 Generic Programmed Commands All commands other than the standard memory reads must be programmed by th
452. ze 32 bit Default 000001FFh Power Well Resume Access D F 0 31 Offset Start 24h PCI Configuration B D F 0 31 0 Offset End 27h Memory Mapped IO BAR GPIO BAR 10 Offset Bit Range Default Access Acronym Description 31 09 0 RO RSVD Reserved I nput Output When set the GPIO signal if enabled is programmed 08 00 1FFh RW 10 as an input When cleared the GPIO signal is programmed as an output If the pin is muxed and not enabled writes to these bits have no effect 11 7 2 3 Offset 28h RGLVL Resume Well GPI O Level for Input or Output Table 352 28h RGLVL Resume Well GPIO Level for Input or Output Size 32 bit Default 00000000h Power Well Resume Access v Offset Start 28h PCI Configuration B D F 0 31 0 Offset End 2Bh Memory Mapped IO BAR GPIO BAR 10 Offset Bit Range Default Access Acronym Description 31 09 0 RO RSVD Reserved Level If the GPIO is programmed to be an output RGI O IO n cleared then this bit is used by software to drive a value on the pin 1 high 0 low If the GPIO is programmed as an input then this bit reflects the 08 00 0 RW LVL state of the input signal 1 high 0 low and writes will have no effect The value of this bit has no meaning if the GPIO is disabled RGEN EN n 0 Intel Atom Processor E6xx Series Datasheet 238 ACPI Devices intel 11 7 2 4 Offset 2Ch RGTPE Resume Well GPIO Trigger Positive Edg
453. ze 32 bit Default Power Well Core Access e i Offset Start 00h PCI Configuration B D F Offset End 00h Bit Range Default Access Acronym Description 31 28 0 RO RSVD Reserved 27 24 Oh RW AID APIC Identification Software must program this value before using the APIC 23 16 0 RO RSVD Reserved 15 0 RW Scratchpad 14 0 RW RSVD Reserved Writes to this bit have no effect 13 00 0 RO RSVD Reserved 11 4 2 2 Offset O1h VS Version Register Table 328 01h VS Version Register Sheet 1 of 2 Size 32 bit Default Power Well Core Access i SCH Offset Start 01h PCI Configuration B D F Offset End 01h Bit Range Default Access Acronym Description 31 24 0 RO RSVD Reserved Maximum Redirection Entries This is the entry number 0 being the 23 16 17h RO MRE lowest entry of the highest entry in the redirection table In the processor this field is hardwired to 17h to indicate 24 interrupts Pin Assertion Register Supported The IOxAPIC does not implement 15 0 RO PRQ the Pin Assertion Register Intel Atom Processor E6xx Series Datasheet 224 ACPI Devices Table 328 01h VS Version Register Sheet 2 of 2 Size 32 bit Default Power Well Core Access Offset Start 01h PCI Configuration B D F Offset End 01h Bit Range Default Access Acronym Description 14 08 0 RO RSVD Reserved 07 00 20h RO VS Version Identifies the implementation

Intel Atom E620

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