Home

Intel Pentium G6951

1. Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 SUSWARN D8 SMLOALERT F21 GSPIO MISO L36 SUSPWRDNACK GPIO60 GPIO85 GPIO30 SUS_STAT D25 GSPIO MOSI K33 ACPRESENT M17 GPIO61 GPIO86 GPIO31 SUSCLK GPIO62 B27 GSPI1_CS L34 CLKRUN GPIO32 B35 GPIO87 SLP S54 GPIO63 A18 DEVSLPO GPIO33 E30 GSPI1_CLK M31 SDIO_CLK N34 GPIO88 SATAOGP GPIO34 F29 GPIO64 GSPI1 MISO F37 SATA1GP H29 SDIO_CMD H40 GPI089 SATAPHY_PC GPIO65 GPIO35 GPIO9 D17 SDIO_D0 GPIO66 R40 SATA2GP GPIO36 D33 GSPI_MOSI H35 SDIO_D1 GPIO67 R38 GPIO90 SATA3GP GPIO37 L26 SDIO_D2 GPIO68 J39 UARTO_RXD M35 DEVSLP1 GPIO38 K31 GPIO91 SDIO D3 GPIO69 P31 DEVSLP2 GPIO39 J41 UARTO TXD F39 I2C1_SCL GPIO7 M33 GPIO92 I2C0_SDA GPIO4 N36 SDIO_POWER_EN R36 UARTO_RTS N43 OC0 GPIO40 E18 GPIO70 GPIO93 OC1 GPIO41 E22 HSIOPC D29 UARTO_CTS N41 PCIEPHY_PC GPIO94 OC2 GPIO42 H21 GPIO71 RSVD N18 OC34 GPIO43 D21 BATLOW H17 GPIO72 RSVD P33 GPIO44 L18 SML1ALERT H8 RSVD CK6 GPIO45 P23 PCHHOT GPIO73 RSVD CL8 GPIO46 L22 SML1DATA A14 RSVD AK25 GPIO47 B29 GPIO74 RSVD AL24 GPIO48 K29 SML1CLK GPIO75 C14 INTRUDER
2. Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 SATA_Rp1 T39 RSVD Y33 USB2n1 T9 PERp6_L2 RSVD W33 USB2n2 Y10 SATA_Rp2 W39 PERp6 L1 SPI CLK C26 USB2n3 AB10 SATA Rp3 Y36 SPI_CSO H27 USB2n4 w9 PERp6_LO SPI_CS1 M27 USB2n5 v8 SATA Tn0 W43 PETn6 L3 SPI CS2 K27 USB2n6 V6 SATA Tn1 T43 SPI IO2 F27 USB2n7 Y6 PETn6 L2 SPI 103 J26 USB2n8 v4 SATA_Tn2 T41 PETn6_L0 SRTCRST D6 USB2p1 v10 E AAAS RSVD H15 USB2p2 Y8 SATA _Tp1 V s 12S1_SCLK N9 USB2p3 AA9 PETp6_L2 SUSACK D19 USB2p4 W7 SATA_Tp2 W41 PEDE Li SYS_PWROK A22 USB2p5 T7 SATATI nar RAZI SYS_RESET E26 USB2p6 T5 PETp6 LO RSVD BT41 USB2p7 w5 SATALED C30 RSVD BT43 USB2p8 T3 SERIRQ E34 RSVD BJ40 USB2p9 W3 PROC DETECT CF41 BUD arr REVE Has SLP_A G18 TD_IREF L40 RSVD Fi3 SLP_LAN K19 vss AL26 RSVD CJ32 SLP_SO G22 vss AL28 RSVD CM33 SLP_S3 N22 THERMTRIP CG40 VCC1_05_PHY T31 SLP_S4 H19 USB3Rn1 AJ41 DCPSUS4 T21 SLP_SUS D27 USB3Rn2 AM43 VCCHDAPLL AK29 SMBCLK P21 USB3Rp1 AM41 VCCOPIPLL AK19 SMBDATA B21 USB3Rp2 AK42 VCCSATA3PLL T33 SMLOCLK P19 USB3Tn1 BG42 VCCASW Ni SMLODATA B19 USB3Tn2 BF41 VCCASW Ti RSVD CB11 USB3Tp1 BG40 VCCASW W14 RSVD AP3 USB3Tp2 BF43 VCCTS1_5 AJ32 RSVD W21 USBRBIAS B13 VCCUSB2PLL AK17 RSVD AJ34 USBRBIAS D13 VCCUSB3PLL T35 RSVD Y34 USB2n0 W12 VCC
3. Signal Name Ball Signal Name Ball Signal Name Ball DDR3 DDR3 DDR3 SA DQ44 AV54 SA DQ6 AK61 SA MA5 AR36 SA DQ45 AU54 SB DQ44 AV19 SA MA6 AV40 SA DQ3 AK62 SB DQ45 AU19 SA MA7 AW39 SA DQ46 AV52 SB DQ46 AV17 SA MA8 AY39 SA DQ47 AU52 SB DQ47 AU17 SA MA9 AU40 SB DQO AY31 SA DQ7 AK60 SA ODTO AP32 SB DQ1 AW31 SA DQ8 AM63 SA_RAS AY34 SB_DQ2 AY29 SA_DQ9 AM62 SA_WE AW34 SB_DQ3 AW29 SA_DQSNO AJ61 SATA_IREF A12 SB DQ4 AV31 SA DQSN1 AN62 SATA RCOMP C12 SB DQ5 AU31 SA DQSNA AV57 SATA Rn0 J5 PERn6 L3 SB DQ6 AV29 SA DQSN5 AV53 SATA_Rn1 J8 SB DQ7 AU29 SB DQSNO AW30 PERn6 12 SA DQ4 AH61 SB DQSN1 AV26 SATA Rn2 J6 PERn6 L1 SB DQ8 AY27 SB DQSNA AW22 SATA Rn3 F5 SB DQ9 AW27 SB DQSNS5 AV18 PERn6 LO SB DQ10 AY25 SA DQSPO AJ62 SATA RpO H5 PERp6 L3 SB DQ11 AW25 SA DQSP1 AN61 iie SATA Rp1 H8 SB DQ12 AV27 SA_DOSP4 AW57 PERp6 L2 SB DQ13 AU27 SA DQSP5 AW53 SATA_Rp2 H6 SB DQ14 AV25 SB DQSPO AV30 PERp6_L1 SATA_Rp3 E5 SB_DQ15 AU25 SB_DQSP1 AW26 PERp6_LO SB DQ32 AY23 SB_DOSP4 AV22 SATA TnO B15 SB DQ33 AW23 SB DQSP5 AW18 PETRO L3 SATA_Tn1 A17 SA_DQ5 AH60 SA_MAO AU36 PETn6 L2 SB DQ34 AY21 SA MA1 AY37 SATA Tn2 Bid SB_DQ35 AW21 SA_MA10 AP35 PETn6_L1 SB_DQ36 AV23 SA_MA11 AW41 SATA_Tn3 C17 PETn6 LO SB DQ37 AU23 SA MA12 AU41 SATA_Tp0 A15 SB_D038 AV21 SA_MA13 AR35 PETp6_L3 SB_D039 AU21 SA_MA14 AV4
4. Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 SB DQ7 AU29 SB DQSNO AW30 SATA Rn1 J8 PERn6 L2 SA DQ4 AH61 SB DQSN1 AV26 SATA Rn2 J6 SB DQ8 AY27 SB_DQSN4 AW22 PERn6_L1 SB_DQ9 AW27 SB_DQSN5 AV18 SATA_Rn3 F5 PERn6_LO SB DQ10 AY25 SA DQSPO AJ62 SATA_Rp0 H5 SB DQ11 AW25 SA DQSP1 AN61 PERpG 13 SB DQ12 AV27 SA_DOSP4 AW57 SATA Rp1 H8 PERp6 L2 SB DQ13 AU27 SA DQSP5 AW53 PES SATA Rp2 H6 SB DQ14 AV25 SB DQSPO AV30 PERp6_L1 SB DQ15 AU25 SB DQSP1 AW26 SATA Rp3 E5 SB_DQ32 AY23 SB_DQSP4 AV22 PERp6_LD0 SATA_Tn0 B15 SB DQ33 AW23 SB DQSP5 AW18 PETn6 L3 SA DQ5 AH60 SA CAB9 AU36 SATA Tn1 A17 SB DQ34 AY21 SA CAB8 AY37 PETS Ee SATA Tn2 B14 SB DQ35 AW21 SA CAB7 AP35 PETnG Li SB DQ36 AV23 SA_CAA7 AW41 SATA _Tn3 SB DQ37 AU23 SA CAA6 AU41 PETn6 LO SB DQ38 AV21 SA CABO AR35 SATA_Tp0 A15 PETp6_L3 SB DQ39 AU21 SA CAA9 AV42 SATA Tp1 B17 SB DQ40 AY19 SA CAA8 AU42 PETp6_L2 SB DQ41 AW19 SA CAB5 AR38 SATA Tp2 C15 PETp6 L1 SB DQ42 AY17 NOT USED AP36 SATA_Tp3 D17 SB DQ43 AW17 NOT USED AU39 PETp6 LO SA DQ6 AK61 SA CAAO0 AR36 SATAOGP GPIO34 vi SB_DQ44 AV19 SA_CAA2 AV40 SATA1GP GPIO35 Ui SB DQ45 AU19 SA CAA4 AW39 SATA2GP GPIO36 V6 SB DQ46 AV17 SA CAA3 AY39 SATA3GP GPIO37 AC1 SB DQ47 AU17 SA CAA1 AU40 SATALED U3 SA_DQ7 AK60 SA_ODTO AP32 SB_CAB4 AL35 SA DQ8 AM63 SA CAB3 AY34 SB_CAB6 AM36
5. Single ended GTL Input PROC TCK PROC TDI PROC TMS PROC TRST Single ended GTL PROC TDO Single ended GTL BPM 7 0 Single ended GTL PREQ Single ended GTL PRDY Control Sideband Single ended GTL Input Open PROCHOT Drain Output Single ended Asynchronous IVR_ERROR CMOS Output Single ended Open Drain Output THERMTRIP Single ended GTL CATERR Single ended Asynchronous RESET PROCPWRGD PWR_DEBUG VCCST_PWRGD CMOS Input Single ended Asynchronous Bi PECI directional Single ended GTL Bi directional CFG 19 0 Voltage Regulator Single ended VR Enable CMOS VR_EN Output Single ended CMOS Input VR_READY Single ended CMOS Input VIDALERT Single ended Open Drain Output VIDSCLK Single ended CMOS I O VIDSOUT Differential Analog Output VCC_SENSE VSS_SENSE Power Ground Other Single ended Power VCC VDDQ VCCST Ground VSS No Connect RSVD Test Point RSVD_TP Other DAISY CHAIN NCTF ball continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 86 March 2015 Order No 330834 004v1 m Electrical Specifications Processor n te Signal Group Type Signals Digital Display Interface Differential DDI Output DDIB_TXP 3 0 DDIB_TXN 3 0 DDIC_TXP 3 0 DDIC_TXN 3 0
6. Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 DDPB_CTRLCLK BP43 SA_CAA8 CG10 NOT USED AR6 DDPB_CTRLDATA BN42 SA_CAB5 CF5 NOT USED AT5 DDPC_CTRLCLK BP41 NOT USED CE10 SB CAAO AT3 DDPC CTRLDATA BR40 NOT USED CG8 SB_CAA2 BA8 SM PG CNTL1 BL14 SA CAAO0 CG6 SB CAA4 AY3 SM RCOMPO CV7 SA_CAA2 CH3 SB_CAA3 AW2 SM_RCOMP1 CP7 SA_CAA4 CE6 SB_CAA1 AY5 SM_RCOMP2 CT7 SA_CAA3 CB9 SB_ODTO AU10 SM VCCDDQG CC14 SA_CAA1 CC12 SB_CAB3 BA10 RSVD_TP BT15 SA_ODTO CA6 SB_CAB2 AW12 RSVD_TP BJ14 SA CAB3 CE2 SA DQO CT17 SM VREF CA AP13 SA CAB2 CE4 SA DQ1 CV17 SM VREF DQO AU14 SB_CAB4 AY11 SA DQ2 CN14 SM VREF DQ1 AT13 SB CAB6 BA12 SA DQ3 CP15 SA_CAB4 CB5 SB_CAA5 AU2 SA DQ4 CN16 SA CAB6 CC2 SB_CAB1 AW10 SA_DG5 CR16 SA_CAA5 CF11 SB CKEO BA2 SA DQ6 CM13 SA CAB1 CC8 SB CKE1 BA4 SA DQ7 CV15 SA CKEO CH11 SB CKE2 AR8 SA DQ8 CT13 SA CKE1 CH9 SB CKE3 AP5 SA DQ9 CP13 SA CKE2 CA12 SB CK 0 AW6 SA DQ10 CP10 SA CKE3 CA10 SB CK 1 AP11 SA DQ11 CM10 SA CLK 0 CG4 SB_CKO AW4 SA DQ12 CN12 SA CLK 1 CC4 SB CK1 AP9 SA DQ13 CV13 SA CLKO CG2 SB CS 0 AR10 SA DQ14 CV10 SA CLK1 CC6 SB CS 1 AT11 SA DQ15 CT10 SA_CS 0 CA4 SB_CAB9 AT9 SA_DQ32 BU2 SA_CS 1 CA2 SB_CAB8 AR4 SA DQ33 BW2 SA CAB9 CE8 SB CAB7 AY9 SA DQ34 BW6 SA CAB8 CE12 SB CAA7 AUA SA DQ35 BU4 SA_CAB7 CF3 SB_CAA6 AU6 SA DQ36 BW4 SA_CAA7 CG12 SB CABO AW8 SA DQ37 BT3 SA CAA6 CH5 SB CAA9 BA6 SA DQ38 BU6 SA CABO CB3 SB CAA8 AR2 SA DQ39 BT5 SA CAA9 CF9 SB CAB5 AU8 SA DQ40
7. Turbo Time Parameter Turbo Time Parameter is a mathematical parameter units in seconds that controls the Intel Turbo Boost Technology 2 0 algorithm using moving average of energy usage During a maximum power turbo event of about 1 25 x TDP the processor could sustain PL2 for up to approximately 1 5 times the Turbo Time Parameter If the power value and or Turbo Time Parameter is changed during runtime it may take approximately 3 to 5 times the Turbo Time Parameter for the algorithm to settle at the new control limits The time varies depending on the magnitude of the change and other factors There is an individual Turbo Time Parameter associated with Package Power Control Configurable TDP cTDP and Low Power Mode Configurable TDP cTDP and Low Power Mode LPM form a design vector where the processor s behavior and package TDP are dynamically adjusted to a desired system performance and power envelope Configurable TDP and Low Power Mode technologies offer opportunities to differentiate system design while running active workloads on select processor SKUs through scalability configuration and adaptability The scenarios or methods by which each technology is used are customizable but typically involve changes to PL1 and associated frequencies for the scenario with a resultant change in performance depending on system s usage Either technology can be triggered by but are not limited to changes in OS power policies or hardware
8. Notes 1 See Signal Description on page 72 for signal description details 2 SA and SB refer to DDR3L DDR3L RS LPDDR3 Channel A and DDR3L DDR3L RS LPDDR3 Channel B 7 6 Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic Intel recommends the processor be first in the TAP chain followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Two copies of each signal may be required with each driving a different voltage level The processor supports Boundary Scan JTAG IEEE 1149 1 2001 and IEEE 1149 6 2003 standards A few of the I O pins may support only one of those standards 7 7 DC Specifications The processor DC specifications in this section are defined at the processor pins unless noted otherwise See Signal Description on page 72 for the processor pin listings and signal definitions e The DC specifications for the DDR3L DDR3L RS LPDDR3 signals are listed in the Voltage and Current Specifications section e The Voltage and Current Specifications section lists the DC specifications for the processor and are valid only while meeting specifications for junction temperature clock frequency and input voltages Read all notes associated with each pa
9. 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 74 March 2015 Order No 330834 004v1 Signal Description Processor 6 4 Table 29 6 5 Table 30 6 6 Table 31 embedded DisplayPort eDP Signals embedded Display Port Signals intel Signal Name Description Direction Buffer Type eDP_DISP_UTIL eDP_TXP 3 0 embedded DisplayPort Transmit Differential Pair O eDP TXN 3 0 eDP eDP AUXP embedded DisplayPort Auxiliary Differential Pair O eDP_AUXN eDP eDP_RCOMP embedded DisplayPort Current Compensation I O A Low voltage multipurpose DISP_UTIL pin on the processor for backlight modulation control of embedded panels and S3D device control for active O shutter glasses This pin will co exist with functionality similar to existing BKLTCTL pin on the PCH Asynchronous CMOS VCOMP_OUT Internal processor power for eDP_RCOMP termination Display Interface Signals Display Interface Signals Signal Name Description Direction Buffer Type DDIB_TXP 3 0 Digital Display Interface Transmit Differential Pair O DDIB TXN 3 0 DP HDMI DDIC TXP 3 0 Digital Display Interface Transmit Differential Pair O DDIC_TXN 3 0 DP HDMI Testability Signals Testability Signals Sig
10. Full HW Acceleration for decode support e Advanced Scheduler 2 0 1 0 XPDM support e Wineows 8 1 Windows 8 Windows 7 OSX Linux operating system support e DirectX 11 1 DirectX 11 1 DirectX 11 DirectX 10 1 DirectX 10 DirectX 9 support e OpenGL 4 0 OpenGL 4 2 support Processor Graphics Controller GT The Graphics Engine Architecture includes 3D compute elements Multi format HW assisted decode encode pipeline and Mid Level Cache MLC for superior high definition playback video quality and improved 3D performance and media The Display Engine handles delivering the pixels to the screen GSA Graphics in System Agent is the primary channel interface for display memory accesses and PCI like traffic in and out 3D and Video Engines for Graphics Processing The Gen 8 3D engine provides the following performance and power management enhancements 3D Pipeline The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive All the cores are fully programmable increasing the versatility of the 3D Engine 3D Engine Execution Units e The EUs perform 128 bit wide execution per clock e Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel processing 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel
11. Signal Groups Signal Group Type Signals Reference Clocks Differential DDR3L DDR3L RS SA CK 3 0 SA CK 3 0 SB CK 3 0 SB CK2 3 0 Output LPDDR3 Output SA CK 1 0 SA CK 1 0 SB CK 1 0 SB CK2 1 0 Command and Address Signals Single ended DDR3L DDR3L RS SA_MA 15 0 SB MA 15 0 SA BS 2 0 SB BS 2 0 Output SA WE SB_WE SA RAS SB RAS SA_CAS SB_CAS LPDDR3 Output SA CAA 9 0 SA CAB 9 0 SB CAA 9 0 SB CAB 9 0 Control Signals Single ended DDR3L DDR3L RS SA_CKE 3 0 SB CKE 3 0 SA_CS 3 0 SB_CS 3 0 Output SA ODT 3 0 SB ODT 3 0 LPDDR3 Output SA CKE 3 0 SB CKE 3 0 SA CS 1 0 SB CS 1 0 SA ODTO SB ODTO Data Signals continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel Celeron9 Processor Family Datasheet Volume 1 of 2 Order No 330834 004v1 85 Processor Electrical Specifications Signal Group Type Signals Single ended DDR3L DDR3L RS LPDDR3 Bi directional SA_DQ 63 0 SB DQ 63 0 Differential DDR3L DDR3L RS LPDDR3 Bi directional SA DQSP 7 0 SA DQSN 7 0 SB DQSP 7 0 SB DQSN 7 0 Reference Voltage Signals Voltage DDR3L DDR3L RS LPDDR3 Output SM VREF CA SM VREF DQO SM VREF DQ1 Testability ITP XDP
12. The processors are designed for a one chip platform that includes a low power Platform Controller Hub PCH die in the same package as the processor die The PCH is referred to as the The Mobile 5th Generation Intel Core Processor Family I O Intel Core M processor family I O Mobile Intel Pentium Processor Family I O and Mobile Intel Celeron Processor Family I O Refer to the Related Documents section for PCH document information See the following figure for the processor platform block diagram Throughout this document the 5th Generation Intel Core processor fanily based on U Processor Line Intel Core M processor Mobile Intel Pentium processor family and Mobile Intel Celeron processor family may be referred to simply as processor Throughout this document the 5th Generation Intel Core processor family based on U Processor Line Mobile Intel Pentium processor family and Mobile Intel Celeron processor family may be referred to simply as U Processor Line Throughout this document the Intel Core M processor family refers to the 5Y71 5Y51 5Y31 5Y70 5Y10 5Y10C and 5Y10A processors Throughout this document the 5th Generation Intel Core processor family based on the U Processor Line refers to the i7 5600U i7 5500U i5 5300U i5 5200U i3 5020U i3 5015U i3 5010U i3 5005U i7 5650U i7 5550U i5 5350U i5 5250U i7 5557U i5 5287U i5 5257U i3 5157U processors Throughout this do
13. Added Section 4 2 6 Package C States and Display Resolutions Updated Section 5 5 Thermal and Power Specifications Updated Section 6 11 Ground and Non Critical to Function NCTF Signals Added package type to Signal Name Updated Section 6 12 Processor Internal Pull Up Pull Down Terminations Added table note Updated Table 36 Processor Core Active and Idle Mode DC Voltage and Current Specifications Added Chapter 9 Processor Ball and Signal Information January 2015 003 004 Updated Table 21 Thermal Design Power TDP Specifications Updated Table 40 Processor Core Active and Idle Mode DC Voltage and Current Specifications Note 3 is added to Operating voltage row and Idle voltage row Added 5th Generation Intel Core processors i3 5020U and i3 5015U Added Intel Pentium processor 3825U January 2015 March 2015 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 Order No 330834 004v1 9 m n tel Processor Introduction 1 0 Introduction The 5th Generation Intel Core processor family based on U Processor line Intel Core M processor family Mobile Intel Pentium processor family and Mobile Intel Celeron processor family are 64 bit multi core processors built on 14 nanometer process technology
14. C1 c3 CO C1 C3 C3 C3 C3 C3 C3 C6 CO C1 C3 C6 C6 C6 C6 C6 Core 0 C7 Co C1 C3 C6 C7 C7 C7 C7 C8 Co C1 C3 C6 C7 C8 C8 C8 co Co C1 C3 C6 C7 C8 C9 C9 C10 Co C1 C3 C6 C7 C8 C9 C10 Note 1 If enabled the package C state will be C1E if all cores have resolved a core C1 state or higher Figure 11 Package C State Entry and Exit Package CI Package CO State This is the normal operating state for the processor The processor remains in the normal state when at least one of its cores is in the CO or C1 state or when the platform has not granted permission to the processor to go into a low power state Individual cores may be in lower power idle states while the package is in CO state Package C1 C1E State No additional power reduction actions are taken in the package C1 state However if the C1E sub state is enabled the processor automatically transitions to the lowest supported core clock freguency followed by a reduction in voltage The package enters the C1 low power state when e At least one core is in the C1 state e The other cores are in a C1 or deeper power state The package enters the C1E state when e All cores have directly requested C1E using MWAIT C1 with a C1E sub state hint 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No
15. Lossless Blu Ray Disc Audio Format Yes res 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 28 March 2015 Order No 330834 004v1 Interfaces Processor Table 9 intel The processor will continue to support Silent stream Silent stream is an integrated audio feature that enables short audio streams such as system events to be heard over the HDMI and DisplayPort monitors The processor supports silent streams over the HDMI and DisplayPort interfaces at 44 1 kHz 48 kHz 88 2 kHz 96 kHz 176 4 kHz and 192 kHz sampling rates Multiple Display Configurations The following multiple display configuration modes are supported with appropriate driver software e Single Display is a mode with one display port activated to display the output to one display device If the external port is activated it should always use the physical port B e Intel Display Clone is a mode with up to three display ports activated to drive the display content of same color depth setting but potentially different refresh rate and resolution settings to all the active display devices connected e Extended Desktop is a mode with up to three display ports activated to drive the content with potentially different color depth refresh rate and resolution settings on each of the active
16. Order No 330834 004v1 Thermal Management Processor intel Table 21 Thermal Design Power TDP Specifications Segment and Processor IA Configuration Core Graphics Thermal Notes Package Cores Graphics Freguency Freguency Design Power Config and TDP TDP W 500 MHz to Pase 2 6 GHz 300 MHz up 15 Intel Core U Dual Core to Processor Line GT2 Configurable 600 MHz 950 MHz 75 t x iM BGA 1168 15W TDP Down i LPM 500 MHz 300 MHz 500 MHz to Base 1 9 GHz 300 MHz up 15 Intel Core U Dual Core to Processor Line GT1 Configurable 600 MHz 950 MHz 10 t 2 em BGA 1168 15W TDP Down LPM 500 MHz 300 MHz 500 MHz to Bose 3 1 GHz 300 MHz up 28 Intel Core U Dual Core to 1 2 5 12 Processor Line GT3 Configurable 600 MHz 1 1 GHz 23 13 14 f BGA 1168 28 W TDP Down LPM 500 MHz 300 MHz 500 MHz to Base 2 2 GHz 300 MHz up 15 Intel Core U Dual Core to 1 2 5 13 Processor Line GT3 Configurable 600 MHz 1 0 GHz 9 5 13 14 f BGA 1168 15W TDP Down LPM 500 MHz 300 MHz 500 MHz to Base 1 2 GHz 4 5 300 MHz up Intel Core M Dual Core Configurable 1 0 GHz to to 6 Processor GT2 TDP Up 1 4 GHz 900 MHz um rA BGA 1234 4 5 W Confi pv silt ks 600 MHz 3 5 TDP Down LPM 500 MHz 300 MHz Table 22 Junction Temperature Specification Processor Symbol Package Turbo Min Default Max Units Notes Parameter Intel8 Core U Processor Line
17. SDIO L10 CLKOUT PCIE P3 AD34 12S0_RXD DAISY_CHAIN_NCT H2 CLKOUT_PCIE_P4 AG29 F_H2 HDA_SDI1 L8 12S1_RXD CLKOUT PCIE P5 AE33 DAISY CHAIN NCT H44 F H44 HDA SDO N3 PROC TCK CM41 i 12S0_TXD DDI1_TXN 0 AD25 PROC_TDI CU36 HDA_SYNC L4 DDI1_TXN 1 AD26 I2S0 SFRM PROC TDO CU38 DDI1_TXN 2 AG25 DDI1_TXN 3 AG26 TESTLOW_AC33 AC33 PROC_TRST CR39 DDI1_TXP 0 AC25 TESTLOW_AD33 AD33 PROCPWRGD CG42 DDI1_TXP 1 AC26 TESTLOW_N14 N14 RSVD AJ22 DDI1_TXP 2 AE25 TESTLOW_M15 M15 RSVD AL20 DDI1_TXP 3 AE26 CLKOUT_ITPXDP_N AG34 DAISY_CHAIN_NCT A44 F_A44 DDI2_TXN 0 AD22 CLKOUT_ITPXDP_P AE34 DAISY_CHAIN_NCT C43 DDI2_TXN 1 AG22 CLKOUT_LPC_0 K15 F_C43 DDI2 TXN 2 AD21 CLKOUT LPC 1 L14 DAISY_CHAIN_NCT C45 F_C45 DDI2_TXN 3 AG21 CLKOUT_PCIE_NO AD29 DAISY_CHAIN_NCT F45 DDI2 TXP 0 AC22 CLKOUT PCIE Ni AD30 F_F45 DDI2_TXP 1 AE22 CLKOUT_PCIE_N2 AE30 DAISY_CHAIN_NCT D2 F_D2 DDI2 TXP 2 AC21 CLKOUT PCIE N3 AC34 DAISY CHAIN NCT D44 DDI2 TXP 3 AE21 CLKOUT PCIE N4 AE29 F D44 GROS continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 98 March 2015 Order No 330834 004v1 Processor Ball and Signal Information Processor ntel
18. The package C8 state is similar to package C7 state however in addition all internally generated voltage rails are turned off and the input Vcc is reduced to 1 15 V to 1 3 V Package C9 State The processor enters package C9 states when the core with the highest state is C9 The package C9 state is similar to package C8 state in addition the input Vcc is changed to 0 V Package C10 State The processor enters C10 states when the core with the highest state is C10 The package C10 state is similar to the package C9 state in addition the VR12 6 is in PS4 low power state which is near to shut off of the VR12 6 Dynamic L3 Cache Sizing When all cores request C7 or deeper C state internal heuristics dynamically flushes the L3 cache Once the cores enter a deep C state depending on their MWAIT sub state request the L3 cache is either gradually flushed N ways at a time or flushed all at once Upon the cores exiting to CO the L3 cache is gradually expanded based on internal heuristics Package C States and Display Resolutions Integrated graphics have their frame buffer located in system memory When the display is updated graphics fetches display data from system memory Different screen resolutions and refresh rates have different memory latency requirements These requirements may limit the deepest Package C state the processor may enter Other elements that may affect the deepest Package C state available are the following e
19. VCC G23 VCC1_05 J11 VCCST_PWRGD B59 VCC G25 VCC1_05 AG16 VCCSUS3_3 AH11 VCC G27 VCC1_05 AG17 VCCSUS3_3 AA9 VCC G29 VCC3_3 V8 VCCSUS3_3 AC9 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 130 March 2015 Order No 330834 004v1 Processor Ball and Signal Information Processor intel Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 VCCSUS3_3 AE20 VSS AA1 VSS AH28 VCCSUS3_3 AE21 VSS A44 VSS AH30 VCCTS1_5 J15 VSS AA58 VSS AH32 VCCUSB3PLL B18 VSS AB10 VSS AH34 VDDQ AH26 VSS AB20 VSS AH36 VDDQ AJ31 VSS AE5 VSS AH38 VDDQ A333 VSS AB22 VSS AH40 VDDQ A337 VSS AB7 VSS AH42 VDDQ AN33 VSS AC61 VSS AH44 VDDQ AP43 VSS AD3 VSS AH49 VDDQ AR48 VSS AD63 VSS AH51 VDDQ AY35 VSS AE10 VSS AH53 VDDQ AY40 VSS AD21 VSS AH55 VDDQ AY44 VSS AE58 VSS AH57 VDDQ AY50 VSS AR43 VSS AJ13 VIDALERT L62 VSS C39 VSS AJ14 VIDSCLK N63 VSS AF11 VSS AJ23 VIDSOUT L63 VSS AF12 VSS AJ25 VR_EN F60 VSS AF14 VSS AJ27 VR_READY C59 VSS AF15 VSS AJ29 VSS P62 VSS AF17 VSS AJ35 VSS D63 VSS AF18 VSS AJ39 VSS P22 VSS AG21 VSS AJ41 VSS N21 VSS AG23 VSS AJ43 VSS A11 VSS AG1 VSS AJ45 VSS A14 VSS AG11 VSS AJ47 VSS A18 VSS AG60 VSS AJ50 V
20. VSS AW33 VSS B44 VSS D49 VSS AW35 VSS C14 VSS D50 VSS AW37 VSS B48 VSS D51 VSS AW4 VSS B52 VSS D53 VSS AW40 VSS B56 VSS D54 VSS AW42 VSS B60 VSS D55 VSS AW44 VSS C11 VSS D57 VSS AW47 VSS C18 VSS D59 VSS AW50 VSS C20 VSS E11 VSS AW51 VSS C25 VSS E17 VSS AW59 VSS C27 VSS F42 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 330834 004v1 121 Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball DDR3 DDR3 VSS F20 VSS M22 VSS D5 VSS N10 VSS F26 VSS N3 VSS F30 VSS C57 VSS F34 VSS P59 VSS F38 VSS P63 VSS G6 VSS R10 VSS F46 VSS R8 VSS F50 VSS Ti VSS F54 VSS T58 VSS F58 VSS D8 VSS F61 VSS U20 VSS G18 VSS U22 VSS G22 VSS U61 VSS G3 VSS V10 VSS G5 VSS v3 VSS G8 VSS V7 VSS H13 VSS W20 VSS H17 VSS Y10 VSS H57 VSS U9 VSS J10 VSS Y59 VSS J22 VSS Y63 VSS J59 VSS W22 VSS J63 VSS V58 VSS K1 VSS AH46 VSS K12 VSS V23 VSS R22 VSS AH16 VSS L13 VSS SENSE E62 VSS L15 WAKE AJ5 VSS L17 XTAL24_IN A25 VSS L18 XTAL24 OUT B25 VSS L20 VSS L58 VSS L61 VSS L7 continued 5th Generation Intel Core Processor Family Intel Core M Processor Famil
21. e Power Limit 1 PL1 A threshold for average power that will not exceed recommend to set equal to TDP power PL1 should not be set higher than thermal solution cooling limits e Power Limit 2 PL2 A threshold that if exceeded the PL2 rapid power limiting algorithms will attempt to limit the spike above PL2 e Power Limit 3 PL3 A threshold that if exceeded the PL3 rapid power limiting algorithms will attempt to limit the duty cycle of spikes above PL3 by reactively limiting frequency This is an optional setting e Turbo Time Parameter Tau An averaging constant used for PL1 exponential weighted moving average EWMA power calculation 1 Implementation of Intel Turbo Boost Technology 2 0 only requires configuring PL1 PL1 Tau and PL2 2 PL3 is disabled by default 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 Order No 330834 004v1 61 n n tel Processor Thermal Management Figure 12 5 3 2 5 4 Note Package Power Control 4 up to 10ms x o a 2 5 e o o e a PL2 ada ri rs mt i Power could on caribe confib sustain here up to PL1Ta 7100s seconds Plies gs el mmm M M M M M Power could S sustain here p R forever 4 Average power Note1 Optional Feature default is disabled x
22. 0 1 11 011 3Bh 1 0800 0 0l 0 1 10 11 41 1Bh 0 7600 0 0 1 11 10 0J 3Ch 1 0900 0 0 0 1 1 J10 0 1Ch 0 7700 0 0 1 l111 011 3Dh 1 1000 0 0 0 1 1 1 0 1 1Dh 0 7800 0 0 1111110 3Eh 1 1100 0 0 0 1 1 J111 0 1Eh 0 7900 0 0 1 11 1 11 3Fh 1 1200 0 0 0 1 1 1 1 1 1Fh 0 8000 0 1 0 0 0 0 J 0l 0 40h 1 1300 0 0l 1 0 0 J 0 0l 0 20h 0 8100 0 1 0 0 0 0 0 11 41h 1 1400 continued LC continued 5th Generation Intel Core March 2015 Order No 330834 004v1 Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron9 Processor Family Datasheet Volume 1 of 2 81 Processor Electrical Specifications 3 rr o B B B B B B B B Hex Vec B B BIB B B B B Hex Vec i ijiji i i i i il i li i li Li Jii tjt tt tt t t t tt ttt t t 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 0 0 0 0 1 0 42h 1 1500 O 1 1 0 0 1 0 0 64h 1 4900 0 1 0 0 0 0 1 1 43h 1 1600 O 1 1 0 0 1 0 1 65h 1 5000 0 1 0 0 0 1 0 0 44h 1 1700 O 1 1 0 0 1 1 0 66h 1 5100 0 1 0 0 0 1 0 1 45h 1 1800 O 1 1 0 0 1 1 1 67h 1 5200 0 1 0 0 0 1 1l 0 46h 1 1900 0 110 1J 0 010 68h 1 5300 0 1 0 0 0 1 1 1 47h 1 2000 O 1 1 0 1 0 0 1 69h 1 5400 O 1 0 0 1 0 0 0
23. 0 1 seconds Refer to Turbo Time Parameter on page 62 for further information 8 Shown limit is a time averaged power based upon the Turbo Time Parameter Absolute product power may exceed the set limits for short durations or under virus or uncharacterized workloads Processor will be controlled to specified power limit as described in Intel Turbo Boost Technology 2 0 Power 9 Monitoring on page 61 If the power value and or Turbo Time Parameter is changed during runtime it may take a short period of time approximately 3 to 5 times the Turbo Time Parameter for the algorithm to settle at the new control limits 10 This is a hardware default setting and not a behavioral characteristic of the part 11 For controllable turbo workloads limit may be exceeded for up to 10 ms 12 Refer to Table 20 on page 63 for the definitions of base TDP Up and TDP Down 13 LPM power level is an opportunistic power and is not a guaranteed value as usages and implementations may vary 14 Power limits may vary depending on if the product supports the TDP up and or TDP down modes Default power limits can be found in the PKG PWR SKU MSR 614h 15 May vary based on SKU 16 Hardware default values might be overridden by the BIOS 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 64
24. 020 moisture level rating and associated handling practices apply to all moisture sensitive devices removed from the moisture barrier bag 6 Nominal temperature and humidity conditions and durations are given and tested within the constraints imposed by Tsystainep storaGe and customer shelf life in applicable Intel boxes and bags 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 330834 004v1 97 9 1 Table 55 Processor Processor Ball and Signal Information Processor Ball and Signal Information This chapter provides the processor Ball information Intel Core M Processor Family Ball Information BGA1234 This section contains ball information for the Intel Core M processor family Intel Core M Processor Family LP DDR3 Non Interleaved Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 APWROK J22 CLKOUT_PCIE_N5 AG33 DAISY_CHAIN_NCT F1 F_F1 HDA_BCLK L6 CLKOUT_PCIE_PO AC29 12S0_SCLK DAISY_CHAIN_NCT F3 CLKOUT_PCIE_P1 AC30 F_F3 HDA_RST J9 I2S MCLK CLKOUT PCIE P2 AG30 DAISY CHAIN NCT F43 F F43 HDA
25. 11 8 1N 2N RUBPESSDI LPDDR3 1333 10 12 12 7 0 5N 1600 12 15 15 8 0 5N Note tCL CAS Latency tRCD Activate Command to READ or WRITE Command delay tRP PRECHARGE Command Period tCWL CAS Write Latency tCK Clock Cycle Intel Fast Memory Access Intel FMA Just in Time Command Scheduling The system memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next The most efficient request is picked from all pending requests and issued to system memory Just in Time to make optimal use of Command Overlapping Thus instead of having all memory access requests go individually through an arbitration mechanism forcing requests to be executed one at a time the requests can be started without interfering with the current request allowing for concurrent issuing of requests This allows for optimized bandwidth and reduced latency while maintaining appropriate command spacing to meet system memory protocol Command Overlap Command Overlap allows the insertion of the DRAM commands between the Activate Pre charge and Read Write commands normally used as long as the inserted commands do not affect the currently executing command Multiple commands can be issued in an overlapping manner increasing the efficiency of system memory protocol 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pe
26. 2 0 eene nnne nnn nnns nasi nna nnn nnn 39 3 5 Intel Advanced Vector Extensions 2 0 Intel AVX2 isses nnn 39 3 6 Intel Advanced Encryption Standard New Instructions Intel AES NI 39 3 7 Intel 64 Architecture x2APIC 4 EbE asas 40 3 8 Power Aware Interrupt Routing PAIR aaa aaa 42 3 9 Execute Disable Bites yin ean nana d ye kann das up g aj 42 3 10 Intel Device Protection with Boot Guard iaaaa as 42 3 11 Supervisor Mode Execution Protection SMEP eceeeeeee este eee ee eee nemen 42 3 12 Supervisor Mode Access Protection SMAP aaa 43 3 13 Intel Transactional Synchronization Extensions New Instructions Intel TSX NI 43 4 0 Power Management c sseesseseeseesuneuuuuu un aea RR RR RR RR ER SR ku nnmnnn u aa u uu u aa au ua uu u aa nnna 44 4 1 Advanced Configuration and Power Interface ACPI States Supported 45 4 2 Processor Core Power Managemeht aaa 46 4 2 1 Enhanced Intel SpeedStep Technology Key Features eene 46 4 2 2 Low Power Idle States cipes sere asas sms dE ER Re dx AR ak 47 4 2 3 Requesting Low Power Idle States ssssssssssssssseeenemenee nemen 48 4 2 4 Core C State Rules erano eta acts n nan en k a kama weave a k kat kal ar era RAN AY REN Ea n 48 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pen
27. 24 9 B Ron Buffer on Resistance other GTL 12 28 9 _ Iu Input Leakage Current 150 HA 3 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The Vccsr referred to in these specifications refers to instantaneous Vccsr 3 For VIN between 0 V and Vccgr Measured when the driver is tri stated 4 V H4 and Voy may experience excursions above Vccsr However input signal drivers must comply with the signal quality specifications Table 49 VR Enable CMOS Signal Group DC Specification Symbol Parameter Min Max Units Notes RoN Buffer on Resistance 30 70 Q VHYSTERESIS Hysteresis Voltage 0 15 T v VCCsT Table 50 VCOMP OUT and VCCIO TERM Symbol Parameter Typ Max Units Notes VCOMP OUT Termination Voltage 1 0 V 1 3 4 VCCIO TERM Termination Voltage 1 0 V 2 Notes 1 VCOMP OUT may only be used to connect eDP RCOMP 2 Internal processor power for signal termination 7 8 1 Platform Environment Control Interface PECI DC Characteristics The PECI interface operates at a nominal voltage set by Vccs The set of DC electrical specifications shown in the following table is used with devices normally operating from a Vccgr interface supply Vccgr nominal levels will vary between processor families All PECI devices will operate at the Vccgr level determined by the processor installed in the system Table 51 Platform Environ
28. 330834 004v1 51 En e n tel Processor Power Management e All cores are in a power state deeper than C1 C1E state however the package low power state is limited to C1 C1E using the PMG_CST_CONFIG_CONTROL MSR e All cores have requested C1 state using HLT or MWAIT C1 and C1E auto promotion is enabled in IA32_MISC_ENABLES No notification to the system occurs upon entry to C1 C1E state Package C2 State Package C2 state is an internal processor state that cannot be explicitly requested by software A processor enters Package C2 state when e All cores and graphics have requested a C3 or deeper power state however constraints LTR programmed timer events in the near future and so on prevent entry to any state deeper than C 2 state Or e All cores and graphics are in the C3 or deeper power states and a memory access request is received Upon completion of all outstanding memory requests the processor transitions back into a deeper package C state Package C3 State A processor enters the package C3 low power state when e At least one core is in the C3 state e The other cores are in a C3 state or deeper power state and the processor has been granted permission by the platform e The platform has not granted a request to a package C6 C7 or deeper state however has allowed a package C6 state In package C3 state the L3 shared cache is valid Package C6 State A processor enters the package C6 low power state w
29. 35V e Two memory channels Single channel and dual channel memory organization modes e 64 bit wide channels e Data burst length of eight for all memory organization modes e Theoretical maximum memory bandwidth of 21 3 GB s in dual channel mode assuming 1333 MT s 25 6 GB s in dual channel mode assuming 1600 MT s 29 8 GB s in dual channel mode assuming 1866 MT s System Memory Technology Supported The Integrated Memory Controller IMC supports DDR3L DDR3L RS and LPDDR3 protocols with two independent 64 bit wide channels It supports unbuffered non ECC memory per channel allowing up to two device ranks per channel Processor DIMM Support Summary By Product Processor Type TDP W Graphics DIMM Per Memory Speed Configurat Channel ion DDR3L LPDDR3 DDR3L RS MT s MT s Intel Core M Processor 6 GT2 1 1333 1600 1333 1600 y e ME 28 GT3 1 1333 1600 1600 1866 y Von se 15 GT3 1 1333 1600 1600 1866 y s Cone kas bai 15 GT2 1 1333 1600 1333 1600 Intel Pentium P ee oe aig cd 15 GT1 1 1333 1600 1333 1600 Intel Celeron Processor 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 18 Order No 330834 004v1 Interfaces Processor Table 4 Table 5 Table 6 2 1 2
30. 4500 1000 010110 82h 1 7900 0 1 1 0 0 0 011 61h 1 4600 100001011 11 83h 1 8000 0 1 1 0 0 0 1 0 62h 1 4700 1000 01110 0 84h 1 8100 0 1 1 0 00 111 63h 1 4800 1010001110 11 85h 1 8200 continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 82 Order No 330834 004v1 Electrical Specifications Processor n tel B B B B B B B B Hex Vec B B B B B B B B Hex Vec il i Li li li Li J i ili li i li i Jii tjt t ttt t t tt t t ttt t 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1000 0111110 86h 1 8300 1 0 1 0 1 0 l0 0J A8h 2 1700 1010001111 41 87h 1 8400 1 0 1 0 1 0 0 1 AO9h 2 1800 1000 1 0100 88h 1 8500 1 0 1 0 1 01 0 AAh 2 1900 1000 1010 1 89h 1 8600 1 0 1 0 1 0 111 ABDh 2 2000 100 0 10 1 0J 8Ah 1 8700 1 0 1 0 1 1i 0 0J ACh 2 2100 1000 1011 8Bh 1 8800 1 0 J1 0 1 i 0 1 ADh 2 2200 1000 110 0 8Ch 1 8900 1 0 1 01 1i l1 0 AEh 2 2300 1010 0 i 10 1 8Dh 1 9000 1 0 10 1 1111 AFh 2 2400 1010011111 0 8Eh 1 9100 1 0 1 1 0 0 0 0J BOh 2 2500 1000 1111 1 8Fh 1 9200 1 0 1 1 0 0 0 1 Bih 2 2600 1001 0l 0100 90h 1 9300
31. Aie ba naran Dakak aa k D Ha an desa RR ib Hak a ay Ei dayk DOR a D aja 66 24 Signal Description Buffer Ty Saya kk kk vasa v sa al k ada Ew Walk aa a ak carana a k kd ara a k 72 25 DDR3L DDR3L RS Memory Down Channel A and B Memory Signals usus 72 26 LPDDR3 Memory Down Channel A and B Memory Signals aaa 73 27 LPDDR3 DDR3L DDR3L RS Reference and Compensation Signals sse 74 28 Reset and Miscellaneous Signals cece eee eee eee eee eee emen 74 29 embedded Display Port Signals issiria a ela De leka a dk cade duda W kk EE kala l 75 30 Display Interface Sigh lS isssse om svainis eskimosiem WE Ho ERAS 75 31 Testability Signals asas pereo bana kara Waran t j Kin Dank FR NEC ERE Dn Dav n kk Ka bar D a a Raj d k DA a h 75 32 Error and Thermal Protection S ga S L hk hkW kkkkk kk kk kk kk eee kk kk kk aaa kak kak k kaka 76 33 Power Sequencing Signals ciza la ts sasita a ta bak ala kla da da aia kan n k Eda kk dl k da k a haa d y 77 34 Processor Power Signals kaks iu erede Rey e bank na D ka W D a b sah wa dide xat gud aa daa da Dad xa 77 E CEEECT hCISEPITen Inm 78 36 Ground and Non Critical to Function NCTF Signals essem 78 37 Processor Internal Pull Up Pull Down Terminations ssseseseeemm teen teenies 79
32. Celeron Processor Family Datasheet Volume 1 of 2 Order No 330834 004v1 23 m n tel Processor Interfaces Vertex Fetch VF Stage The VF stage executes 3DPRIMITIVE commands Some enhancements have been included to better support legacy D3D APIs as well as SGI OpenGL Vertex Shader VS Stage The VS stage performs shading of vertices output by the VF function The VS unit produces an output vertex reference for every input vertex reference received from the VF unit in the order received Geometry Shader GS Stage The GS stage receives inputs from the VS stage Compiled application provided GS programs specifying an algorithm to convert the vertices of an input object into some output primitives For example a GS shader may convert lines of a line strip into polygons representing a corresponding segment of a blade of grass centered on the line Or it could use adjacency information to detect silhouette edges of triangles and output polygons extruding out from the edges Clip Stage The Clip stage performs general processing on incoming 3D objects However it also includes specialized logic to perform a Clip Test function on incoming objects The Clip Test optimizes generalized 3D Clipping The Clip unit examines the position of incoming vertices and accepts rejects 3D objects based on its Clip algorithm Strips and Fans SF Stage The SF stage performs setup operations required to rasterize 3D objects The outp
33. Devices are configured in each memory channel a number of different configurations can exist Single Channel Mode In this mode all memory cycles are directed to a single channel Single channel mode is used when either Channel A or Channel B are populated in any order but not both Dual Channel Mode Intel Flex Memory Technology Mode The system memory controller supports Intel Flex Memory Technology Mode where memory is divided into a symmetric and asymmetric zone The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached In this mode the system runs with one zone of dual channel mode and one zone of single channel mode simultaneously across the entire memory array This mode is used when both Channel A and Channel B are populated with memory but the total amount of memory in each channel is not the same Channels A and B can be mapped for Physical Channel 0 and 1 respectively or vice versa however the Channel A size must be greater or equal to the Channel B size 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 Order No 330834 004v1 21 intel Figure 2 2 1 6 2 2 Processor Interfaces Intel Flex Memory Technology Oper
34. Display is on or off e Single or multiple displays e Native or non native resolution e Video playback e Panel Self Refresh technology Display resolution is not the only factor influencing the deepest Package C state the processor can get into Device latencies interrupt response latencies core C states among other factors influence the final package C state the processor can go into 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 Order No 330834 004v1 53 m e n te Processor Power Management Table 18 Package C States and Display Resolutions PSR Number of Displays 1 Native Resolution 2 Deepest Available Package C State 3200x1800 60 Hz and Disabled Single lower resolutions with PC7_PLUS refresh rate 60 Hz or less Disabled Single 3200x2000 60 Hz PC7 PLUS or PC7 Disabled Single 3840x2160 30 Hz PC7 PLUS Disabled Single 4096x2160 24 Hz PC7 PLUS Disabled Single 3840x2160 60 Hz PC6 Disabled Single 4096x2304 60 Hz PC6 1920x1200 60 Hz and Disabled Multiple lower resolutions with PC7 PLUS refresh rate 60 Hz or less Disabled Multiple 2048x1536 60 Hz PC7 Disabled Multiple 2560x1600 60 Hz PC6 Disabled Multiple 2560x1920 60 Hz PC6 Disabled Multiple 2880x1620 60 Hz PC6 Disabled Multiple 3200x1800 60 Hz PC6 or
35. Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 330834 004v1 49 En e n tel Processor Power Management 4 2 5 This feature is disabled by default BIOS must enable it in the PMG_CST_CONFIG_CONTROL register The auto demotion policy is also configured by this register Package C States The processor supports CO C1 C1E C3 C6 C7 C8 C9 and C10 power states The following is a summary of the general rules for package C state entry These apply to all package C states unless specified otherwise e A package C state request is determined by the lowest numerical core C state amongst all cores e A package C state is automatically resolved by the processor depending on the core idle power states and the status of the platform components Each core can be at a lower idle power state than the package if the platform does not grant the processor permission to enter a requested package C state The platform may allow additional power savings to be realized in the processor For package C states the processor is not required to enter CO state before entering any other C state Entry into a package C state may be subject to auto demotion that is the processor may keep the package in a deeper package C state than requested by the operating system if the processor determines using heuristics that the deeper C state results in better power performance The processor exits a pac
36. J5 GPIO49 B31 BMBUSY J30 USB3PHY_PC INTVRMEN H6 I2C0_SCL GPIO5 R42 676 JTAGX CL16 GPIO50 F33 PIRQA GPIO77 K35 eDP BKLCTL BM41 GPIOS1 H33 PIRQB GPIO78 F31 eDP BKLEN BR42 GPIO52 L30 PIRQC GPIO79 234 eDP VDDEN BN40 GPIO53 C39 Bua n LADO P13 GPIO54 F35 PIRQD GPIO80 D38 LAD1 M13 GPIO55 M29 SPKR GPIO81 A34 LAD2 R14 GPIO56 F25 RCIN GPIO82 C34 LAD3 K13 GPIO57 F23 GSPIO_CS D40 a GPIO58 F15 GPIO83 gt GSPI0_CLK G34 LFRAME P15 GPIO59 D15 SOS RSVD CL34 I2C1 SDA GPIO6 J37 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 102 Order No 330834 004v1 Processor Ball and Signal Information Processor n te Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 RSVD CL28 RSVD AL18 PETp2 USB3Tp4 BC42 RSVD C5 PROC OPI RCOMP AB6 PETp3 AY43 BPM 0 CM39 PCH_OPI_RCOMP AB4 PETp4 AV43 BPM 1 CN38 PCH_PWROK F9 PETp5_LO AU42 BPM 2 CK36 PCH_TCK CK17 PETp5_L1 AW42 BPM 3 CM37 PCH_TDI CL20 PETp5_L2 BA40 BPM 4 CN36 PCH_TDO CL18 PETp5_L3 BB43 BPM 5 CR35 PCH_TMS CK15 RSVD AT41 BPM 6 CN34 PCH TRST CM7 RSVD A
37. Microsoft Windows operating systems The 128 bit BLT engine provides hardware acceleration of block transfers of pixel data for many common Windows operations The BLT engine can be used for the following e Move rectangular blocks of data between memory locations e Data alignment e To perform logical operations raster ops The rectangular block of data does not change as it is transferred between memory locations The allowable memory transfers are between cacheable system memory and frame buffer memory frame buffer memory and frame buffer memory and within system memory Data to be transferred can consist of regions of memory patterns or solid color fills A pattern is always 8 x 8 pixels wide and may be 8 16 or 32 bits per pixel The BLT engine expands monochrome data into a color depth of 8 16 or 32 bits BLTs can be either opaque or transparent Opaque transfers move the data specified to the destination Transparent transfers compare destination color to source color and write according to the mode of transparency selected Data is horizontally and vertically aligned at the destination If the destination for the BLT overlaps with the source memory location the BLT engine specifies which area in memory to begin the BLT transfer Hardware is included for all 256 raster operations source pattern and destination defined by Microsoft including transparent BLT The BLT engine has instructions to invoke BLT and stretch BLT ope
38. SA DQ9 AM62 SA CAB2 AW34 SB_CAA5 AU49 SA DQSNO AJ61 SATA IREF 12 SB CAB1 AM33 SA DQSN1 AN62 SATA RCOMP C12 SB CK 0 AM38 SA_DOSN4 AV57 SATA Rn0 J5 SB CK 1 AK38 PERn6 L3 SA DQSN5 AV53 SB CKO AN38 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Order No 330834 004v1 Mobile Intel Celeron9 Processor Family Datasheet Volume 1 of 2 127 Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 SB CK1 AL38 SB DQ18 AL28 SA DQ25 AR55 SB CKEO AY49 SB_D019 AK28 SA DQSN2 AM58 SB CKE1 AU50 SB_DQ20 AR29 SA_DQSN3 AM55 SB_CKE2 AW49 SB_D021 AN29 SA DQSN6 AL43 SB CKE3 AV50 SB DQ22 AR28 SA DQSN7 AL48 SB CS 0 AM32 SB DQ23 AP28 SB DQSN2 AN28 SB_CS 1 AK32 SA_D020 AL58 SB DQSN3 AN25 SA DQ16 AP58 SB DQ24 AN26 SB DQSN6 AN21 SA DQ17 AR58 SB_D025 AR26 SB DQSN7 AN18 SA DQ26 AM54 SB DQ26 AR25 SA DQSP2 AN58 SA_DQ27 AK54 SB_DQ27 AP25 SA_DQSP3 AN55 SA DQ28 AL55 SB DQ28 AK26 SA DQSP6 AL42 SA DQ29 AK55 SB DQ29 AM26 SA DQSP7 AL49 SA DQ30 AR54 SB DQ30 AK25 SB DQSP2 AM28 SA DQ31 AN54 SB DQ31 AL25 SB DQSP3 AM25 SA DQ48 AK40 SB DQ48 AR21 SB DQSP6 AM21 SA DQ49 AK42 SB DQ49 AR22 SB DQSP7 AM18 SA DQ50 AM43 SA D
39. SAC405 Ball Pin Count 1168 1234 Grid Array Pattern Balls Anywhere Balls Anywhere Package Yes Die Side Capacitors No No Die Configuration Multi Chip Package MCP 2 dies Multi Chip Package MCP 2 dies Package Dimension Nominal Package Size 40 mm x 24 mm x 1 284 mm 30 mm x 16 5 mm x 1 05 mm Min Ball Pin pitch 0 65 mm 0 5 mm 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 96 March 2015 Order No 330834 004v1 Package Specifications Processor n tel 8 2 Package Loading Specifications Table 53 Package Loading Specifications Maximum Static Normal Load Limit Notes U Processor Line 67 N 15 Ibf 12 3 Intel Core M Processor Family 44 N 10 Ibf 1 2 3 Notes 1 The thermal solution attach mechanism must not induce continuous stress to the package It may only apply a uniform load to the die to maintain a thermal interface 2 This specification applies to the uniform compressive load in the direction perpendicular to the dies top surface 3 This specification is based on limited testing for design characterization Assumes a motherboard thickness of 1 0 mm or greater 5 Assumes the use of a backing plate 8 3 Package Storage Specifications Table 54 Package Storage Specif
40. TMS specification supported signal used by debug tools GTL Processor Test Reset This signal resets the Test I PROC TRST Access Port TAP logic This signal must be driven low during power on Reset GTL 6 7 Table 32 Error and Thermal Protection Signals Error and Thermal Protection Signals Signal Name Description Direction Buffer Type CATERR Catastrophic Error This signal indicates that the system has experienced a catastrophic error and cannot continue to operate The processor will set this for non recoverable machine check errors or other unrecoverable internal errors CATERR is used for signaling the following types of errors Legacy MCERRs CATERR is asserted for 16 BCLKs Legacy IERRs CATERR remains asserted until warm or cold reset GTL PECI PROCHOT Platform Environment Control Interface A serial sideband interface to the processor it is used primarily for thermal power and error management Processor Hot PROCHOT goes active when the processor temperature monitoring sensor s detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled This signal can also be driven to the processor to activate the TCC I O Asynchronous GTL Input Open Drain Output THERMTRIP Thermal Trip The processor protects itself from catastrophic overheating by use of
41. VCC E53 VCC M23 VCCHSIO K9 VCC E55 VCC M57 VCCHSIO L10 VCC E57 VCC P57 VCCIO_OUT A59 VCC F24 VCC U57 VCOMP_OUT E20 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 118 Order No 330834 004v1 Processor Ball and Signal Information Processor intel Signal Name Ball Signal Name Ball Signal Name Ball DDR3 DDR3 DDR3 VCCRTC AG10 VSS N21 VSS AG23 VCCSATA3PLL B11 VSS A11 VSS AG1 VCCSDIO U8 VSS A14 VSS AG11 VCCSDIO T9 VSS A18 VSS AG60 VCCSPI Y8 VSS A24 VSS AG61 VCCST AC22 VSS A28 VSS AG62 VCCST AE22 VSS A32 VSS AG63 VCCST AE23 VSS A36 VSS AH17 VCCST_PWRGD B59 VSS A40 VSS AH19 VCCSUS3_3 AH11 VSS A48 VSS AH20 VCCSUS3_3 AA9 VSS A52 VSS AH22 VCCSUS3_3 AC9 VSS A56 VSS AH24 VCCSUS3_3 AE20 VSS AA1 VSS AH28 VCCSUS3_3 AE21 VSS A44 VSS AH30 VCCTS1_5 J15 VSS AA58 VSS AH32 VCCUSB3PLL B18 VSS AB10 VSS AH34 VDDQ AH26 VSS AB20 VSS AH36 VDDQ AJ31 VSS AE5 VSS AH38 VDDQ A333 VSS AB22 VSS AH40 VDDQ AJ37 VSS AB7 VSS AH42 VDDQ AN33 VSS AC61 VSS AH44 VDDQ AP43 VSS AD3 VSS AH49 VDDQ AR48 VSS AD63 VSS AH51 VDDQ AY35 VSS AE10 VSS AH53 VDDQ AY40 VSS AD21 VSS AH55 VDDQ AY44 VSS AE58 VSS AH57 VDDQ AY50 VSS AR43 VSS AJ1
42. VSS AJ39 VSS AR42 VSS BD15 VSS AK12 VSS AT1 VSS BD39 VSS AK15 VSS AT15 VSS BD7 VSS AK21 VSS AT39 VSS BE40 VSS AK27 VSS AT45 VSS BE42 VSS AK44 VSS AT7 VSS BE44 VSS AK6 VSS AU12 VSS BF13 VSS AM13 VSS AU44 VSS BF15 VSS AM17 VSS AV11 VSS BF39 VSS AM19 VSS AV13 VSS BF7 VSS AM21 VSS AV15 VSS BG14 VSS AM23 VSS AV3 VSS BG44 VSS AM25 VSS AV39 VSS BH1 VSS AM27 VSS AV5 VSS BH13 VSS AM29 VSS AV7 VSS BH15 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron9 Processor Family Datasheet Volume 1 of 2 March 2015 Order No 330834 004v1 107 Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 VSS BH39 VSS BU40 VSS CD15 VSS BH41 VSS BU42 VSS CD3 VSS BH43 VSS BU44 VSS CD39 VSS BH7 VSS BV13 VSS CD5 VSS BJ44 VSS BV15 VSS CD7 VSS BK13 VSS BV39 VSS CD9 VSS BK15 VSS BV7 VSS CE14 VSS BK39 VSS BW14 VSS CE44 VSS BK7 VSS BY1 VSS CF13 VSS BL10 VSS BY11 VSS CF15 VSS BL12 VSS BY13 VSS CF7 VSS BL2 VSS BY15 VSS CG14 VSS BL4 VSS BY3 VSS CG44 VSS BL40 VSS BY39 VSS CH1 VSS BL42 VSS BY5 VSS CH13 VSS BL44 VSS BY7 VSS CH15 VSS BL6 VSS BY9 VSS CH7 VSS BL8 VSS C16 VSS CJ18 VSS BM1 VSS C20 VSS CJ24 VSS BM13 VS
43. based fault recording only for single entry only and support for MSI interrupts for faults e Support for both leaf and non leaf caching e Support for boot protection of default page table e Support for non caching of invalid page table entries e Support for hardware based flushing of translated but pending writes and pending reads on IOTLB invalidation e Support for Global Domain specific and Page specific IOTLB invalidation e MSI cycles MemWr to address FEEx xxxxh not translated Translation faults result in cycle forwarding to VBIOS region byte enables masked for writes Returned data may be bogus for internal agents PEG DMI interfaces return unsupported request status e Interrupt remapping is supported e Queued invalidation is supported e Intel VT d translation bypass address range is supported Pass Through The processor supports the following added new Intel VT d features e Intel VT d superpage support of Intel VT d superpage 2 MB 1 GB for the default Intel VT d engine and Intel VT D IGD engine iGFX DMA remap engine e Support for LPSS device virtualization Intel VT d Technology may not be available on all SKUs Intel Trusted Execution Technology Intel TXT Intel Trusted Execution Technology Intel TXT defines platform level enhancements that provide the building blocks for creating trusted platforms The Intel TXT platform helps to provide the authenticity of the controlling environment such that
44. compatible measured aunched environment MLE Intel TXT also requires the system to contain a TPM v1 s For more information visit http www intel com technology security Requires a system with Intel Turbo Boost Technology Intel Turbo Boost Technology and Intel Turbo Boost Technology 2 0 are only available on select Intel processors Consult your PC manufacturer Performance varies depending on hardware software and system configuration For more information visit https www ssl intel com content www us en architecture and technology turbo boost turbo boost technology html Intel Advanced Vector Extensions Intel AVX are designed to achieve higher throughput to certain integer and floating point operations Due to varying processor power characteristics utilizing AVX instructions may cause a some parts to operate at less than the rated frequency and b some parts with Intel Turbo Boost Technology 2 0 to not achieve any or maximum turbo frequencies Performance varies depending on hardware software and system configuration and you should consult your system manufacturer for more information Intel Advanced Vector Extensions refers to Intel AVX Intel AVX2 or Intel AVX 512 For more information on Intel Turbo Boost Technology 2 0 visit https www ssl intel com content www us en architecture and technology turbo boost turbo boost technology html Intel Intel Core Celeron Pentium Intel SpeedStep and the Intel logo are tradem
45. demand modes in the event of a catastrophic cooling failure the package will automatically shut down when the silicon has reached an elevated temperature that risks physical damage to the product At this point the THERMTRIP signal will go active Critical Temperature Detection Critical Temperature detection is performed by monitoring the package temperature This feature is intended for graceful shutdown before the THERMTRIP is activated However the processor execution is not guaranteed between critical temperature and THERMTRIP If the Adaptive Thermal Monitor is triggered and the temperature remains high a critical temperature status and sticky bit are latched in the PACKAGE THERM STATUS MSR 1Bih and the condition also generates a thermal interrupt if enabled For more details on the interrupt mechanism refer to the Intel 64 and IA 32 Architectures Software Developer s Manual On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption using clock modulation This mechanism is referred to as On Demand mode and is distinct from Adaptive Thermal Monitor and bi directional PROCHOT The processor platforms must not rely on software usage of this mechanism to limit the processor temperature On Demand Mode can be accomplished using processor MSR or chipset I O emulation On Demand 5th Generation Intel Core Processor Family Intel Core M Proces
46. like Super I O SIO and Embedded Controllers EC to provide processor temperature Turbo Configurable TDP and memory throttling control mechanisms and many other services PECI is used for platform thermal management and real time control and configuration of processor features and performance PECI Bus Architecture The PECI architecture is based on a wired OR bus that the clients as processor PECI can pull up high with strong drive The idle state on the bus is near zero The following figure demonstrates PECI design and connectivity While the host originator can be a third party PECI host one of the PECI clients is a processor PECI device 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 Order No 330834 004v1 31 intel Figure 6 PECI Host Clients Connection Example Processor Interfaces Host Originator fx H gt j nX PECI Q2 nun Ceci 10pF Node Q3 nX PECI Client Additional PECI Clients 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 32 March 2015
47. mak ot s ta veeja 18 2 1 1 System Memory Technology Supported sss 18 2 1 2 System Memory Timing SUpDOF i sa d l yal daa dd a hena enne nennen nnns 19 2 1 3 Intel Fast Memory Access Intel FMA k nennen 20 2 1 4 System Memory Fr gU6en Cy i k kk l aaa 21 2 1 5 System Memory Organization Modes kk kk kk kk kak kk kk mne 21 2 1 6 Data S ramDIl i boit ka Ay tin a k y ANA W An ind ew le a me S d dank k a 22 2 2 Processor Graphics scam conan dens din kis Di nakan n ana ba ea b denne P lin nin dia a k e a n ej s MEAE 22 2 3 Processor Graphics Controller GT i ask dik ak aalak kaka kk alek eee etna kak alek la al k e ka lea kak aa aa 23 2 3 1 3D and Video Engines for Graphics Processing 23 2 4 Digital Display Interface DDI 5 a nik saimei ver s v era dene ca kal aiia kal Ru a RARE eseja 25 2 5 Platform Environmental Control Interface PECI s sssssssssssrssrrusnrnssrurnrnsrnnnrnnrnrnsrnnrnns 31 2 5 1 PECI B s Archit ct f sanesas zer LI ee Ee Ea np darda a eW ek nad dla y k WAYA 31 3 0 Technologies aaaa kak aaraa ra r a a la ak j daia 33 3 1 Intel Virtualization Technology Intel VT k klu aa 33 3 2 Intel Trusted Execution Technology Intel TXT aaa 37 3 3 Intel Hyper Threading Technology Intel HT Technology sscsscssecsseeeeeneeeeeeeeeaeees 38 3 4 Intel Turbo Boost Technology
48. operation and in low power ACPI Cx states 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 54 Order No 330834 004v1 Power Management Processor n tel 4 3 1 4 3 2 Disabling Unused System Memory Outputs Any system memory SM interface signal that goes to a memory in which it is not connected to any actual memory devices is tri stated The benefits of disabling unused SM signals are e Reduced power consumption e Reduced possible overshoot undershoot signal quality issues seen by the processor I O buffer receivers caused by reflections from potentially un terminated transmission lines When a given rank is not populated the corresponding chip select and CKE signals are not driven At reset all rows must be assumed to be populated until it can be determined that the rows are not populated This is due to the fact that when CKE is tri stated with DRAMs present the DRAMs are not ensured to maintain data integrity CKE tri state should be enabled by BIOS where appropriate since at reset all rows must be assumed to be populated CKE tri state should be enabled by BIOS where appropriate since at reset all rows must be assumed to be populated DRAM Power Management and Initialization The processor implements extensive support for power management on the me
49. power meter A per rank power is associated with the warm and hot thresholds that when exceeded may trigger memory thermal throttling 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 330834 004v1 71 Table 24 6 1 Table 25 Processor Signal Description Signal Description This chapter describes the processor signals The signals are arranged in functional groups according to the associated interface or category The following notations are used to describe the signal type Notation Signal Type I Input pin O Output pin I O Bi directional Input Output pin Signal Description Buffer Types The signal description also includes the type of buffer used for the particular signal see the following table Signal Description CMOS CMOS buffers 1 05V tolerant Diff Clk Differential clock DDR3L DDR3L DDR3L DDR3L RS buffers 1 35 V tolerant RS A Analog reference or output May be used as a threshold voltage or for buffer compensation GTL Gunning Transceiver Logic signaling technology Ref Voltage reference signal Asynchronous Signal has no timing relationship with any reference clock 1 Oualifier for a buffer type System Memory Interface Signals DDR3L DDR3L RS Memory Down Channel A and B
50. 0 0 1 0 1 25h 0 8600 0 0 0 0 0 1 0 1 05h 0 5400 0 0 1 0 0 1J1 1 0 26h 0 8700 0 0l 0 0 0 J 1J1 0 06h 0 5500 0 0 1 0 0 1J1 41 27h 0 8800 O 0 0 0 0 1 1 1 07h 0 5600 0 0 1 0 1 0 0l 0 28h 0 8900 0 0l 0 0 1 J 0 0l 0 08h 0 5700 0 0 1 0 10 011 29h 0 9000 0 0l 0 0 1 0 0 1 09h 0 5800 0 0 1 0 1 010 2Ah 0 9100 0 0l 0 0 1 010 0Ah 0 5900 0 0 1 0 1 011 2Bh 0 9200 0 0l 0 0 1 0111 0Bh 0 6000 0 0 1 0 1 1 0 0J 2Ch 0 9300 0 0 0 0 1 10 0 0Ch 0 6100 0 0 1011011 2Dh 0 9400 O 0 0 0 1 1 0 1 ODh 0 6200 0 0 1 0 1 1 1 0 2Eh 0 9500 O O0 0 0 1 1 1 0 OEh 0 6300 0 0 1 0 1 1 1 1 2Fh 0 9600 0 J 0l 0 0 1 1J 111 0Fh 0 6400 0 0 1 10 0 J 0 J 0 30h 0 9700 0 0l 0 1 0 J 0 0 0 10h 0 6500 0 0 1 10 0 0 11 31h 0 9800 0 0l 0 1 0 J 0J0 11 11h 0 6600 0 0 1 10 0 11 0 32h 0 9900 0 0l 0 1 0 J 0110 12h 0 6700 0 0 1 10 01 414 33h 1 0000 0 0l 0 1 0 J 0111 13h 0 6800 0 0 1 10 1 0l 0 34h 1 0100 0 0l 0 1 0 J1J 0l 0 14h 0 6900 0 0 1 10 1J 0 11 35h 1 0200 0 0 0 1 0 1 0 1 15h 0 7000 O O 1 1 0 1 1 0 36h 1 0300 O O0 0 1 0 1 1 0 16h 0 7100 O O 1 1 0 1 1 1 37h 1 0400 0 0l 0 1 0 J111 11 17h 0 7200 0 0 1 11 0 010 38h 1 0500 0 0l 0 1 1 0 0l 0 18h 0 7300 0 0 1 11 0 011 39h 1 0600 0 0l 0 1 1J 0011 19h 0 7400 0 0 1 11 010 3Ah 1 0700 0 0 0 1 10 110 1Ah 0 7500 0
51. 1 0 1 1 0 0 10 B2h 2 2700 1010101010 11 91h 1 9400 1 0 1 1 0 0 11 B3h 2 2800 10101010110 92h 1 9500 1 0 1 1 0 10 0 B4h 2 2900 1010101011 1 93h 1 9600 1 0 11 0 10 1 B5h 2 3000 1 0 j0 1 0 1 0 0 94h 1 9700 1 0 1 1 0 1 1 0 B6h 2 3100 1 0j0 1 0 1 0 1 95h 1 9800 1 0 1 1 0 1 1 1 B7h 2 3200 1 0j0 1 0 1 1 0 96h 1 9900 1 0 11 1 0 10 0 B8h 2 3300 10101101111 11 97h 2 0000 1 0 11 1 0 10 1 B9h 2 3400 1010 1 10 100 98h 2 0100 1 0 1 11 0 110 BAh 2 3500 1 0j0 1 1 0 0 1 99h 2 0200 1 0 11 1 0 1 1 BBh 2 3600 10 0 1 1 01 0 9Ah 2 0300 1 0 J11 1 1 0 0J BCh 2 3700 1010 1 10 1 1 9Bh 2 0400 1 0 1 11 1 0 1 BDh 2 3800 1010 1110 0 9Ch 2 0500 1 0 11 1 i l1 0 BEh 2 3900 1010 1 i 10 1 9Dh 2 0600 1 0 11 1 1111 BFh 2 4000 101011111110 9Eh 2 0700 1 i 0 0 0 0 0 0J COh 2 4100 1010 1111 1 9Fh 2 0800 1 i J 0 0 0 0 01 Cih 2 4200 101 0 000 0 J AOh 2 0900 1 i J 00 0 0 10J C2h 2 4300 10110 000 1 A1h 2 1000 1 i 0 0 0 0 11 C3h 2 4400 1011 0 001 0J A2h 2 1100 1 i J 00 0 1 0 0J C4h 2 4500 1011 0 010111 A3h 2 1200 1 i J 00 0 1 01 C5h 2 4600 1011 0 010 0J A4h 2 1300 1 i J 00 0 1 10 C6h 2 4700 1011 0 0110 1 A5h 2 1400 1 i J 00 0 1i 11 C7h 2 4800 1010 01110 A6h 2 1500 1 i J 00 1 0 10 0J C8h 2 4900 1011 0 01111 AZh 2 1600 1 i J 00 1 0 0 1 C9h 2 5000 continued continued 5th Generation Intel
52. 1 38 v transmitting device Aux peak to peak voltage at receiving Vaux Rx device 0 32 1 36 V eDP RCOMP COMP Resistance 24 75 25 25 25 Q Note 1 COMP resistance is to VCOMP_OUT CMOS Signal Group DC Specifications Symbol Parameter Min Max Units Notes VIL Input Low Voltage Vccsr 0 3 V 2 Vin Input High Voltage Vccsr 0 7 _ V 2 4 Ron Buffer on Resistance 30 70 Q s Input Leakage E lu Current 150 H 3 Notes 1 Unless otherwise noted all specifications in this table apply to all processor freguencies Symbol Parameter Min Max Units Notes Input Low Voltage TAP except _ x Vit PROC_TCK PROC_TRST Vccsr 0 6 d 2 Input High Voltage TAP except _ Vin PROC TCK PROC TRSTZ Vecsr 0 72 25 4 Input Low Voltage PROC_TCK n Vit PROC_TRST vsp M continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 Order No 330834 004v1 93 Processor Electrical Specifications Symbol Parameter Min Max Units Notes Vin Be ee a PROC TICK Vccsr 0 7 V 2 4 Vuysteresis Hysteresis Voltage Vccsr 0 2 V Ron Buffer on Resistance TDO 7 17 Q Vit Input Low Voltage other GTL Vccsr 0 6 V 2 Vin Input High Voltage other GTL Vccsr 0 72 V 2 4 Ron Buffer on Resistance CFG BPM 16
53. 1 AP51 UARTO_CTS G1 GPIO94 SB_MA3 AR42 SMBALERT AN2 GPIO11 UARTO_RTS J2 SB MA4 AR45 GPIO93 SMBCLK AP2 SB MA5 AP45 UARTO_RXD Ji SMBDATA AH1 GPIO91 SB MA6 AW46 SMLOALERT AL2 UARTO_TXD K3 SB_MA7 AY46 GPIO60 GPIO92 SB MA8 AY47 SMLOCLK AN1 UART1_CTS J4 GPIO3 SB_MA9 AU46 SMLODATA AK1 UART1_RST J3 SB ODTO AL32 SML1ALERT AUA GPIO2 PCHHOT GPIO73 SB_RAS AM35 UART1_RXD GPIOO K4 SML1CLK GPIO75 AU3 SB_WE AK35 UART1_TXD GPIO1 G2 SMLIDATA GPIO74 AH3 SDIO CLK GPIO64 E3 USB2n0 AN8 SPI_CLK AA3 SDIO CMD GPIO65 F4 USB2n1 AR7 SPI_CSO Y7 SDIO_DO GPIO66 D3 USB2n2 AR8 SPI_CS1 Y4 SDIO_D1 GPIO67 E4 USB2n3 AR10 SPI_CS2 AC2 SDIO_D2 GPIO68 C3 USB2n4 AM15 SPI IO2 Y6 SDIO D3 GPIO69 E2 USB2n5 AM13 SPI IO3 AF1 SDIO POWER EN C4 USB2n6 AP11 GPIO70 SPI MISO AAA USB2n7 AR13 SERIRQ T4 SPI_MOSI AA2 USB2p0 AM8 SLP_A AL5 SPKR GPIO81 v2 USB2p1 AT7 SLP LANs AJ7 SRTCRST AV6 USB2p2 AP8 SLP_SO AF3 SUS_STAT AG4 GPIO61 USB2p3 AT10 SLP_S3 AT4 SUSACK AK2 USB2p4 AL15 SLP_S4 AJ6 SUSCLK GPIO62 AE6 USB2p5 AN13 SLP_S5 GPIO63 AP5 SUSWARN AV4 USB2p6 AN11 SLP_SUS AP4 SUSPWRDNACK GPIO30 USB2p7 AP13 SLP_WLAN AM5 GPIO29 SYS PWROK AG2 USB3Rn1 G20 SM DRAMRST AV15 SYS_RESET AC3 USB3Rn2 E18 SM_PG_CNTL1 AV61 TD_IREF B12 USB3Rp1 H20 SM_RCOMPO AU60 TESTLOW_AK8 AK8 USB3Rp2 F18 SM_RCOMP1 AV60 TESTLOW_AL8 AL8 USB3Tn1 C33 SM_RCOMP2 AU61 TESTLOW_C34 C34 USB3Tn2 B33 SM_VREF_CA AP49 TESTLOW_C35 C3
54. 134 March 2015 Order No 330834 004v1
55. 15 Datasheet Volume 1 of 2 Order No 330834 004v1 47 En e n tel Processor Power Management 4 2 3 Note 4 2 4 While individual threads can request low power C states power saving actions only take place once the core C state is resolved Core C states are automatically resolved by the processor For thread and core C states a transition to and from CO is required before entering any other C state Requesting Low Power Idle States The primary software interfaces for requesting low power idle states are through the MWAIT instruction with sub state hints and the HLT instruction for C1 and C1E However software may make C state requests using the legacy method of I O reads from the ACPI defined processor clock control registers referred to as P LVLx This method of requesting C states provides legacy support for operating systems that initiate C state transitions using I O reads For legacy operating systems P LVLx I O reads are converted within the processor to the equivalent MWAIT C state request Therefore P LVLx reads do not directly result in I O reads to the system The feature known as I O MWAIT redirection must be enabled in the BIOS The BIOS can write to the C state range field of the PMG IO CAPTURE MSR to restrict the range of I O addresses that are trapped and emulate MWAIT like functionality Any P LVLx reads outside of this range do not cause an I O redirection to MWAIT Cx like request The reads fall
56. 2 Vcc Sustain Vccsr Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Units Notes Processor Vcc Sustain E 2 Vccsr supply voltage 5 1 05 5 V tos Maximum Current for _ 100 mA 1 Note 1 The maximum Iccmax specification is preliminary and based on initial silicon measurements and is subject to change Table 43 DDR3L DDR3L RS Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes 2 4 11 Vu Input Low Voltage Vppo 2 0 43 Vppo V 14 V Input High Voltage 0 57 V Vppo 2 V 3 11 IH DDQ DDQ 14 Input Low Voltage n cil Vit SM_DRAMPWROK 0 15 Vppo Y Input High Voltage Vin SM DRAMPWROK 0 45 Vppo 1 0 V 10 12 DDR3L DDR3L RS Data Ron_up DQ Buffer pull up 20 26 32 Q 5 11 Resistance DDR3L DDR3L RS Data RoN pN DQ Buffer pull down 20 26 32 Q 5 11 Resistance DDR3L DDR3L RS On 11 die termination RoDT D0 eguivalent resistance an d 62 9 for data signals DDR3L DDR3L RS On 11 die termination DC Vopr pc working point driver 0 45 Vppq 0 5 Vono 0 55 Vope i set to receive mode continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 Order No 330834 004v1 89 Processor Electrical Specifications Symbol Parameter Min Typ Max Units Notes DDR3
57. 2 Vg is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value 3 V His defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 Vy and Vou may experience excursions above Vppq However input signal drivers must comply with the signal quality specifications 5 This is the pull up down driver resistance 6 Rrterm is the termination on the DIMM and in not controlled by the processor 7 The minimum and maximum values for these signals are programmable by BIOS to one of the two sets 8 SM RCOMPx resistance must be provided on the system board with 1 resistors SM RCOMPx resistors are to Vss 9 SM DRAMPWROK rise and fall time must be lt 50 ns measured between Vppo 0 15 and Vppo 0 47 10 SM VREF is defined as Vppo 2 11 Maximum minimum range is correct however center point is subject to change during MRC boot training 12 Processor may be damaged if Vi exceeds the maximum voltage for extended periods 13 The MRC during boot training might optimize Roy outside the range specified 14 Ron tolerance is preliminary and might be subject to change Table 44 LPDDR3 Signal Group DC Specifications Symbol Parameter Min Typ Max Unit Note V Input Low Voltage 2 4 11 IL p g Vana 2 0 43 Vppq V b V I i 3 11 IH nput High Voltage 0 57 Vppo Vppo 2 V 12 Input Low
58. 2 SATA_Tp1 B17 PETp6_L2 SB_DQ40 AY19 SA_MA15 AU42 SATA_Tp2 C15 SB DQ41 AW19 SA MA2 AR38 PETp6 L1 SB DQ42 AY17 SA MA3 AP36 SATA Tp3 D17 PETp6 LO SB DQ43 AW17 SA MA4 AU39 SATAOGP GPIO34 V1 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 Order No 330834 004v1 115 Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball Signal Name Ball DDR3 DDR3 DDR3 SATA1GP GPIO35 U1 SA DQ56 AM46 SB DQ56 AN20 SATA2GP GPIO36 V6 SA DQ57 AK46 SB DQ57 AR20 SATA3GP GPIO37 AC1 SA DQ58 AM49 SB DQ58 AK18 SATALED U3 SA_DQ59 AK49 SB_DQ59 AL18 SB_BAO AL35 SA_DQ60 AM48 SA_DQ22 AR57 SB BA1 AM36 SA DQ61 AK48 SB DQ60 AK20 SB BA2 AU49 SA DQ19 AK57 SB DQ61 AM20 SB_CAS AM33 SA_DQ62 AM51 SB_DQ62 AR18 SB CK 0 AM38 SA_D063 AK51 SB DQ63 AP18 SB CK 1 AK38 SB DQ16 AM29 SA DQ23 AN57 SB CKO AN38 SB DQ17 AK29 SA DQ24 AP55 SB CK1 AL38 SB DQ18 AL28 SA DQ25 AR55 SB CKEO AY49 SB DQ19 AK28 SA DQSN2 AM58 SB CKE1 AU50 SB_DQ20 AR29 SA_DQSN3 AM55 SB_CKE2 AW49 SB_D021 AN29 SA DQSN6 AL43 SB CKE3 AV 50 SB DQ22 AR28 SA DQSN7 AL48 SB CS 0 AM32 SB DQ23 AP28 SB DQSN2 AN28 SB_CS 1 AK32 SA_D020 AL58
59. 3 VIDALERT L62 VSS C39 VSS AJ14 VIDSCLK N63 VSS AF11 VSS AJ23 VIDSOUT L63 VSS AF12 VSS AJ25 VR_EN F60 VSS AF14 VSS AJ27 VR_READY C59 VSS AF15 VSS AJ29 VSS P62 VSS AF17 VSS AJ35 VSS D63 VSS AF18 VSS AJ39 VSS P22 VSS AG21 VSS AJ41 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Order No 330834 004v1 Mobile Intel Celeron9 Processor Family Datasheet Volume 1 of 2 119 Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball Signal Name Ball DDR3 DDR3 DDR3 VSS AJ43 VSS AM17 VSS AP54 VSS AJ45 VSS AM23 VSS AP57 VSS AJ47 VSS AM31 VSS AR11 VSS AJ50 VSS AM52 VSS AR15 VSS AJ52 VSS AN17 VSS AR17 VSS AJ54 VSS AN23 VSS AR23 VSS AJ56 VSS AN31 VSS AR31 VSS AJ58 VSS AN32 VSS AR33 VSS AJ60 VSS AN35 VSS AR39 VSS AJ63 VSS AN36 VSS AP48 VSS AK23 VSS AN39 VSS AR49 VSS AK3 VSS AN40 VSS AR5 VSS AK52 VSS AN42 VSS AR52 VSS AL10 VSS AN43 VSS AT13 VSS AL13 VSS AN45 VSS AT35 VSS AL17 VSS AN46 VSS AT37 VSS AL20 VSS AN48 VSS AT40 VSS AL22 VSS AN49 VSS AT42 VSS AL23 VSS AN51 VSS AT43 VSS AL26 VSS AN52 VSS AT46 VSS AL29 VSS AN60 VSS AT49 VSS AL31 VSS AN63 VSS AT61 VSS AL33 VSS AN7 VSS AT62 VSS AL36 VSS AP10 VSS AT63 VSS AL39 VSS AP17 VSS
60. 38 Voltage Regulator VR 12 5 Voltage Identification aaa 81 39 NERIS rer E 85 40 Processor Core Active and Idle Mode DC Voltage and Current Specifications 87 41 Memory Controller Vppg Supply DC Voltage and Current Specifications 89 42 Vcc Sustain Vccgr Supply DC Voltage and Current Specifications aaa 89 43 DDR3L DDR3L RS Signal Group DC Specifications aaa 89 44 LPDDR3 Signal Group DC Specificat OS L k kKkW l kk aaa aaraa 91 45 Digital Display Interface Group DC Specifications aaa 93 46 Embedded DisplayPort eDP Group DC Specifications aaa 93 47 CMOS Signal Group DC Specifications ccc cece eee aaraa 93 48 GTL Signal Group and Open Drain Signal Group DC Specifications c eeeee eee eee 93 49 VR Enable CMOS Signal Group DC Specification aa aaa 94 50 VCOMP OUT and VCCIO TERM s recede e ska nra saknes skais a kn REIN ka W k a bela di 94 51 Platform Environment Control Interface PECI DC Electrical Limits aaa 94 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron9 Processor Family March 2015 Datasheet Volume 1 of 2 Order No 330834 004v1 7 m n tel Processor Tables Package Mechanical Attributes esssssseeseeseeseen kk kk kk kk a kaka kk kk kk kk ka kak ka kk ak nnn nens 96 Package Loa
61. 48h 1 2100 O 1 1 0 1 0 1 0 6Ah 1 5500 0 1 0 0 1 0 0 1 49h 1 2200 O 1 1 0 1 0 1 1 6Bh 1 5600 0 1 0 0 1 0 1 0J 4Ah 1 2300 0 110 11 0 0 6Ch 1 5700 0 1 0 01 0 1 1 4Bh 1 2400 O 1 1 0 1 1 0 1 6Dh 1 5800 0 1 0 0 1 1 0 0J 4Ch 1 2500 0 11011111 0 6Eh 1 5900 0 1 0 0 11 0 111 4Dh 1 2600 O 1i 1 0 1 1 1 1 6Fh 1 6000 0 1 0 0 11 1 0 4Eh 1 2700 0 1110 J 00l0 70h 1 6100 0 1 0 0 1 1 1 1 4Fh 1 2800 O 1 1 1 0 0 0 1 71h 1 6200 0 1 0 1 0 0 0 0 50h 1 2900 O 1 1 1 0 0 1 0 72h 1 6300 0 1 0 1 0 0 0 1 51h 1 3000 0 1 1 1 0 0 1 1 73h 1 6400 0 1 0 1 0 0 1 0 52h 1 3100 0 1 1 1 0 1 0 0 74h 1 6500 0 1 0 1 0 0 1 1 53h 1 3200 0 1 1 1 0 1 0 1 75h 1 6600 0 1 0 1 01 0l 0 54h 1 3300 O 1i 1 1 0 1 1 0 76h 1 6700 O 1 0 1 0 1 0 1 55h 1 3400 O 1i 1 1 0 1 1 1 77h 1 6800 0 1 0 1 0 1 1J 0 56h 1 3500 0 1111 0010 78h 1 6900 0 1 0 1 01111 57h 1 3600 O 1i 1 1 1 0 0 1 79h 1 7000 O 1i 0O 1 1 0 0 0 58h 1 3700 0 11110110 Z7Ah 1 7100 0 1 0 1 10 0J1 59h 1 3800 0 11110111 7Bh 1 7200 0 1 0 11 0 1 0J 5Ah 1 3900 0 111110 0 7Ch 1 7300 0 1 0 11 0 1 1 5Bh 1 4000 O i 1i 1 1 1 0 1 7Dh 1 7400 O 1ij O i 1i 1 0 0 5Ch 1 4100 O i 1i 1 1 1 1 0 7Eh 1 7500 O 1ij 0O 1i 1 1 0 1 5Dh 1 4200 O i i 1i 1i 1 1 1 7Fh 1 7600 O 1ijO i ij1i 1 O 5Eh 1 4300 100 0 0l 0100 80h 1 7700 0 1 0 1 1 1 1 1 5Fh 1 4400 10100 01010 11 81h 1 7800 0 1 1 0 l0 0 0 0 60h 1
62. 5 USB3Tp1 B34 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron9 Processor Family Datasheet Volume 1 of 2 March 2015 Order No 330834 004v1 117 n te Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball Signal Name Ball DDR3 DDR3 DDR3 USB3Tp2 A33 VCC F28 VCC W57 USBRBIAS AJ11 VCC F32 VCC_SENSE E63 USBRBIAS AJ10 VCC F36 VCC1_05 P9 VCC F59 VCC F40 VCC1_05 N8 VCC AB57 VCC F44 VCC1_05 AE8 VCC AD57 VCC F48 VCC1_05 AF22 VCC AG57 VCC F52 VCC1_05 Hil VCC C24 VCC F56 VCC1_05 H15 VCC C28 VCC G23 VCC1_05 Jii VCC C32 VCC G25 VCC1_05 AG16 VCC C36 VCC G27 VCC1_05 AG17 VCC C40 VCC G29 VCC3_3 v8 VCC C44 VCC G31 VCC3_3 w9 VCC C48 VCC G33 VCC3_3 K14 VCC C52 VCC G35 VCC3_3 K16 VCC C56 VCC G37 VCCACLKPLL A20 VCC E23 VCC G39 VCCAPLL AA21 VCC E25 VCC G41 VCCAPLL W21 VCC E27 VCC G43 VCCASW AE9 VCC E29 VCC G45 VCCASW AF9 VCC E31 VCC G47 VCCASW AG8 VCC E33 VCC G49 VCCASW AG13 VCC E35 VCC G51 VCCASW AG14 VCC E37 VCC G53 VCCCLK J18 VCC E39 VCC G55 VCCCLK K19 VCC E41 VCC G57 VCCCLK J17 VCC E43 VCC H23 VCCCLK T21 VCC E45 VCC J23 VCCCLK R21 VCC E47 VCC K23 VCCDSW3_3 AH10 VCC E49 VCC K57 VCCHDA AH14 VCC E51 VCC L22 VCCHSIO M9
63. 56 AG6 INTRUDER AU6 EDP_HPD D6 GPIO57 AP1 INTVRMEN AV7 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 124 Order No 330834 004v1 Processor Ball and Signal Information Processor intel Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 JTAGX AE63 PERn5 L1 F8 PROC DETECT D61 LADO AU14 PERn5 L2 H10 PROC OPI RCOMP AY15 LAD1 AW12 PERn5 L3 E6 PROC TCK E60 LAD2 AY12 PERp1 USB3Rp3 F17 PROC_TDI F63 LAD3 AW11 PERp2 USB3Rp4 G15 PROC_TDO F62 LAN_PHY_PWR_CTRL AM7 PERp3 F11 PROC_TMS E61 GPIO12 PERp4 G13 PROC_TRST E59 LFRAME AV12 PERp5 LO E10 PROCHOT K63 OCO GPIO40 AL3 PERp5 L1 E8 PROCPWRGD C61 OC1 GPIO41 AT1 PERp5 L2 G10 PWR_DEBUG H59 OC2 GPIO42 AH2 PERp5_L3 F6 PWRBTN AL7 OC3 GPIO43 AV3 PETn1 USB3Tn3 C30 RCIN GPIO82 V4 PCH OPI RCOMP AW15 PETn2 USB3Tn4 B31 RSMRST AW6 PCH_PWROK AY7 PETn3 C29 RSVD W23 PCH_TCK AE62 PETn4 B29 RSVD Y22 PCH TDI AD61 PETn5 LO C23 RSVD B43 PCH TDO AE61 PETn5 L1 B23 RSVD T59 PCH TMS AD62 P
64. 6 VSS D4 VSS N20 VSS CR37 VSS D42 VSS N24 VSS CR5 VSS E16 VSS N28 VSS CR8 VSS E20 VSS N32 VSS CT31 VSS E24 VSS P35 VSS CU1 VSS E28 VSS R10 VSS CU14 VSS E32 VSS Ri6 VSS CU18 VSS E36 VSS R18 VSS CU22 VSS F5 VSS R2 VSS CU26 VSS G16 VSS R20 VSS CU42 VSS G20 VSS R22 VSS CU5 VSS G24 VSS R24 VSS CU8 VSS G28 VSS R26 VSS CV3 VSS G32 VSS R28 VSS CV35 VSS H10 VSS R30 VSS CV37 VSS H36 VSS R4 VSS CV39 VSS H4 VSS R44 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron9 Processor Family Datasheet Volume 1 of 2 March 2015 Order No 330834 004v1 109 Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 VSS R6 VSS Y32 VSS R8 VSS Y40 VSS T13 VSS Y42 VSS TLS VSS Y44 VSS T19 VSS CA14 VSS T23 VSS AM33 VSS T29 VSS AJ13 VSS U14 VSS_SENSE CH43 VSS U20 WAKE F19 VSS U22 RSVD BK41 VSS U24 RSVD BK43 VSS U26 DIFFCLK_BIASREF A38 VSS U28 XTAL24_IN AR44 VSS U32 XTAL24_OUT AP45 VSS U34 VSS V17 VSS v2 VSS V40 VSS V44 VSS W16 VSS W18 VSS W19 VSS W24 VSS W28 VSS W30 VSS W32 VSS W34 VSS W35 VSS Y12 VSS Y14 VSS Y16 VSS Y19 VSS Y2 VSS Y24 VSS Y28 continued 5th Generation Intel Core Processor Family Int
65. 63 LAN_PHY_PWR_CTRL AM7 PERp2 USB3Rp4 G15 PROC_TDO F62 GPIO12 PERp3 F11 PROC_TMS E61 LFRAME AV12 PERp4 G13 PROC TRST E59 OCO4 GPIO40 AL3 PERp5 LO E10 PROCHOT K63 OC1 GPIO41 AT1 PERp5_L1 E8 PROCPWRGD C61 OC2 GPIO42 AH2 PERp5 L2 G10 PWR DEBUG H59 OC3 GPIO43 AV3 PERp5 L3 F6 PWRBTIN AL7 PCH_OPI_RCOMP AW15 PETn1 USB3Tn3 C30 RCIN GPIO82 V4 PCH_PWROK AY7 PETn2 USB3Tn4 B31 RSMRST AW6 PCH_TCK AE62 PETn3 C29 RSVD W23 PCH_TDI AD61 PETn4 B29 RSVD Y22 PCH TDO AE61 PETn5 LO C23 RSVD B43 PCH TMS AD62 PETn5 L1 B23 RSVD T59 PCH TRST AU62 PETn5 L2 B21 RSVD AD60 PCIE IREF B27 PETn5 L3 B22 RSVD AD59 PCIE RCOMP A27 PETp1 USB3Tp3 C31 RSVD AA59 PCIECLKRQO U2 GPIO18 PETp2 USB3Tp4 A31 RSVD AE60 PCIECLKRQ1 Y5 PETp3 B30 RSVD AC59 GPI019 a PETp4 A29 RSVD AG58 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Order No 330834 004v1 Mobile Intel Celeron9 Processor Family Datasheet Volume 1 of 2 113 Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball Signal Name Ball DDR3 DDR3 DDR3 RSVD v59 RSVD E1 SA BAO AU35 RSVD U59 RSVD D1 SA_BA1 AV35 RSVD AL1 RSVD J20 SA BA2 AY41 RSVD AP7 RSV
66. AJ11 SB DQ33 AH2 SA DQ52 BW8 SB DQ55 AH10 SB DQ34 AJ3 SA DQ53 BU8 SB DQ56 AE11 SB DQ35 AM5 SA DQ54 BU12 SB DQ57 AG7 SB DQ36 AM3 SA DQ55 BT9 SB DQ58 AE7 SB DQ37 AJi SA DQ56 BN8 SB DQ59 AE9 SB DQ38 AJ5 SA DQ57 BR8 SB DQ60 AG11 SB DQ39 AH4 SA DQ58 BN12 SB DQ61 AG9 SB DQ40 AG3 SA DQ59 BN10 SB DQ62 AD8 SB DQ41 AG1 SA DQ60 BR12 SB DQ63 AD10 SB DQ42 AD2 SA DQ61 BR10 SA DQSNO CU16 SB DQ43 AE3 SA DQ62 BM11 SA DQSN1 CR12 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 100 Order No March 2015 330834 004v1 Processor Ball and Signal Information Processor n te Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 SA_DQSN4 BV3 DDPC_HPD Y29 RSVD CJ16 SA DQSN5 BP3 EDP HPD w29 RSVD CK31 SB_DQSNO BH5 RSVD_TP AL32 vss CF39 SB_DQSN1 BD5 RSVD_TP AL34 UART1_RXD P29 GPIOO SB DQSNA AK2 HDA DOCK RST N7 1281 SFRM UART1_TXD H38 SB DQSN5 AF2 GPIO1 HDA DOCK EN N5 SA DQSN2 CR24 I2S1_TXD GPIO10 B17 SA DQSN3 CR20 DPWROK J7 SMBALERT K21 GPIO11 SA DQSN6 BV9
67. APIC architecture provides significantly increased processor addressability and some enhancements on interrupt delivery Increased range of processor addressability in x2APIC mode Physical xAPIC ID field increases from 8 bits to 32 bits allowing for interrupt processor addressability up to 4G 1 processors in physical destination mode A processor implementation of x2APIC architecture can support fewer than 32 bits in a software transparent fashion Logical xAPIC ID field increases from 8 bits to 32 bits The 32 bit logical x2APIC ID is partitioned into two sub fields a 16 bit cluster ID and a 16 bit logical ID within the cluster Consequently 2 20 16 processors can be addressed in logical destination mode Processor implementations can support fewer than 16 bits in the cluster ID sub field and logical ID sub field in a software agnostic fashion More efficient MSR interface to access APIC registers To enhance inter processor and self directed interrupt delivery as well as the ability to virtualize the local APIC the APIC register set can be accessed only through MSR based interfaces in x2APIC mode The Memory Mapped IO MMIO interface used by xAPIC is not supported in x2APIC mode The semantics for accessing APIC registers have been revised to simplify the programming of frequently used APIC registers by system software Specifically the software semantics for using the Interrupt Command Register ICR and End Of I
68. AU1 VSS AL40 VSS AP20 VSS AU16 VSS AL45 VSS AP22 VSS AU18 VSS AL46 VSS AP23 VSS AU20 VSS AL51 VSS AP26 VSS AU22 VSS AL52 VSS AP29 VSS AU24 VSS AL54 VSS AP3 VSS AU26 VSS AL57 VSS AP31 VSS AU28 VSS AL60 VSS AP38 VSS AU30 VSS AL61 VSS AP39 VSS AU33 VSS AM1 VSS AP52 VSS AU51 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 120 Order No March 2015 330834 004v1 1 e Processor Ball and Signal Information Processor n te Signal Name Ball Signal Name Ball Signal Name Ball DDR3 DDR3 DDR3 VSS AU53 VSS AW60 VSS D12 VSS AU55 VSS AY11 VSS D14 VSS AU57 VSS AY16 VSS D18 VSS AU59 VSS AY18 VSS D21 VSS AV14 VSS AY22 VSS D23 VSS D62 VSS AY24 VSS D25 VSS AV16 VSS AY26 VSS D26 VSS AV20 VSS AY30 VSS D27 VSS AV24 VSS AY33 VSS D29 VSS AV28 VSS AY51 VSS D2 VSS AV33 VSS AY53 VSS D30 VSS AV34 VSS AY57 VSS D31 VSS AV36 VSS AY59 VSS D33 VSS AV39 VSS AY6 VSS D34 VSS AV41 VSS AY4 VSS D35 VSS AV43 VSS B20 VSS D37 VSS AV46 VSS B24 VSS D38 VSS AV49 VSS B26 VSS D39 VSS AV51 VSS B28 VSS D41 VSS AV55 VSS B32 VSS D42 VSS AV59 VSS C38 VSS D43 VSS AV8 VSS B36 VSS D45 VSS AW16 VSS B4 VSS D46 VSS AW24 VSS B40 VSS D47
69. AU12 12S1_RXD continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 112 March 2015 Order No 330834 004v1 Processor Ball and Signal Information Processor intel Signal Name Ball Signal Name Ball Signal Name Ball DDR3 DDR3 DDR3 HDA_SDO AU11 PCIECLKRQ2 AD1 PETp5 LO C22 12S0_TXD GPIO20 PETp5 L1 A23 HDA_SYNC AV11 PCIECLKRQ3 Ni I2S0_SFRM GPIO21 PETp5 L2 C21 HSIOPC GPIO71 Y2 PCIECLKRQ4 U5 PETp5_L3 A21 GPIO22 I2CO SCL GPIO5 F3 PIRQA GPIO77 U6 PCIECLKRQ5 T2 I2CO SDA GPIO4 F2 GPIO23 PIRQB GPIO78 P4 I2C1_SCL GPIO7 Fi PECI N62 PIRQC GPIO79 N4 I2C1_SDA GPIO6 G4 PERn1 USB3Rn3 G17 PIRQD GPIO80 N2 12S1_SCLK AY8 PERn2 USB3Rn4 F15 PLTRST AG7 INTRUDER AU6 PERn3 G11 PME AD4 INTVRMEN AV7 PERn4 F13 PRDY J62 JTAGX AE63 PERn5 LO F10 PREQ K62 LADO AU14 PERn5 L1 F8 PROC DETECT D61 LAD1 AW12 PERn5 L2 H10 PROC OPI RCOMP AY15 LAD2 AY12 PERn5 L3 E6 PROC TCK E60 LAD3 AW11 PERp1 USB3Rp3 F17 PROC TDI F
70. BN2 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Order No 330834 004v1 Mobile Intel Celeron9 Processor Family Datasheet Volume 1 of 2 99 Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 SA DQ41 BR2 SB DQ44 AE1 SA DQ63 BM9 SA DQ42 BN6 SB DQ45 AG5 SB DQ16 BE10 SA DQ43 BN4 SB DQ46 AD4 SB DQ17 BC10 SA DQ44 BR6 SB DQ47 AE5 SB_D018 BE8 SA DQ45 BRA SA DQ16 CT25 SB DQ19 BC8 SA DQ46 BM5 SA DQ17 CP25 SB DQ20 BF11 SA DQ47 BM3 SA DQ18 CN22 SB DQ21 BC12 SB DQO BK3 SA DQ19 CP23 SB DQ22 BE12 SB DQ1 BK5 SA DQ20 CN24 SB DQ23 BF9 SB DQ2 BG6 SA DQ21 CV25 SB DQ24 BJ12 SB DQ3 BJ2 SA DQ22 CV23 SB DQ25 BG12 SB DQ4 BJ4 SA DQ23 CT23 SB DQ26 BJ8 SB DQ5 BJ6 SA DQ24 CN20 SB DQ27 BJ10 SB DQ6 BG2 SA DQ25 CN18 SB DQ28 BG8 SB DQ7 BG4 SA DQ26 CT21 SB DQ29 BG10 SB DQ8 BF3 SA DQ27 CT19 SB DQ30 BK9 SB DQ9 BF5 SA DQ28 CP19 SB DQ31 BK11 SB DQ10 BC6 SA DQ29 CP21 SB DQ48 AM9 SB DQ11 BE2 SA DQ30 CV19 SB DQ49 AM7 SB DQ12 BE4 SA DQ31 CV21 SB DQ50 AH8 SB DQ13 BE6 SA DQ48 BT11 SB DQ51 AJ9 SB DQ14 BC2 SA DQ49 BU10 SB DQ52 AM11 SB DQ15 BC4 SA DQ50 BW12 SB DQ53 AJ7 SB DQ32 AM1 SA DQ51 BW10 SB DQ54
71. CLK4 AL37 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 104 Order No 330834 004v1 Processor Ball and Signal Information Processor n te Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 VCCACLKPLL AK35 VCC AY45 VCC CY17 VCCCLK3 AJ28 VCC BB45 VCC CY19 VCCCLK1 AK23 VCC BD45 VCC CY21 VCC1_05 AG45 VCC BF45 VCC CY23 VCC1_05 AH36 VCC BH45 VCC CY25 VCC1_05 AJ16 VCC BK45 VCC CY27 VCC1_05 AJ45 VCC BM45 VCC CY29 VCC1_05 T17 VCC BP45 VCC CY31 VCC1_05 W22 VCC BT45 VCC CY33 VCC1_05 Y22 VCC BV41 VCC CY36 DCPSUSBYP AG13 VCC BV43 VCC CY38 VDDQ AP1 VCC BV45 VCC CY40 VDDQ AV1 VCC BW40 VCC CY42 VDDQ BA14 VCC BW42 VCC CY44 VDDQ BB1 VCC BW44 VCC_SENSE CH45 VDDQ BC14 VCC BY41 RSVD AL16 VDDQ BE14 VCC BY43 VCCIO OUT BM43 VDDQ BFi VCC BY45 VCOMP OUT AR40 VDDQ BK1 VCC CA40 VCCHDA AA13 VDDQ BP1 VCC CA42 VCCHDA W1 VDDQ BV1 VCC CA44 VCCPCIEPHY AA45 VDDQ CB1 VCC CB41 VCCPCIEPHY AB38 VDDQ CF1 VCC CB43 VCCPCIEPHY W45 VDDQ CL1 VCC CB45 VCC3_3 A26 VDDQ CM3 VCC CD45 VCC3_3 A28 VDDQ CR1 VCC CF45 VCC3_3 A30 VDDQ CT3 VCC CM45 VCC3_3 T27 VDDQ CW1 VCC CN44 VCCDSW3_3 AA1 VDDQ CY3 VCC CR43 VCCDS
72. CLKOUT_PCIE_P3 C37 B61 CFG 11 U60 CLKOUT PCIE P4 B39 DAISY CHAIN NCTF B62 CFG 12 T63 B62 CLKOUT PCIE P5 A37 CFG 13 T62 DAISY CHAIN NCTF B63 CLKRUN GPIO32 V5 _B63 CFG 14 T61 DAISY_CHAIN_NCTF A3 DAISY_CHAIN_NCTF C1 CFG 15 T60 _A3 _C1 CFG 16 AA62 DAISY_CHAIN_NCTF A4 DAISY_CHAIN_NCTF C2 _A4 _C2 CFG 17 AA61 DAISY_CHAIN_NCTF A60 DCPRTC AE7 CFG 18 U63 A60 DCPSUS1 AD10 CFG 19 U62 DAISY_CHAIN_NCTF A61 1 A61 gt DCPSUS1 AD8 CFG 2 AC63 DAISY_CHAIN_NCTF A62 DCPSUS2 AH13 CFG 3 AA63 A62 DCPSUS3 J13 CFG 4 AA60 4 DAISY_CHAIN_NCTF AV1 wem CFG 5 Y62 DAISY_CHAIN_NCTF AW1 DEPSUSBYP AGIS CFG 6 Y61 AW1 DCPSUSBYP AG20 CFG 7 Y60 7 PATEN OHAIN NCTE AW2 DDI1_TXN 0 hoa CEGIST vez E DDIi TXN 1 B58 DAISY CHAIN NCTF AW3 1XN 1 CFG 9 V61 ane DDI1_TXN 2 B55 CFG_RCOMP v63 continued ANNE continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Order No 330834 004v1 Mobile Intel Celeron9 Processor Family Datasheet Volume 1 of 2 123 n te Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 DDI1_T
73. Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 330834 004v1 11 m n tel Processor Introduction Note 1 2 1 3 e Intel Device Protection Technology with Intel Advanced Encryption Standard New Instructions Intel AES NI e PCLMULQDQ Instruction e Intel Device Protection Technology with Intel Secure Key e Intel Transactional Synchronization Extensions New Instructions Intel TSX NI e PAIR Power Aware Interrupt Routing e SMEP Supervisor Mode Execution Protection e SMAP Supervisor Mode Access Protection e Enhanced Intel Speedstep Technology e Intel Device Protection Technology with Boot Guard e DRAM Bit Error Recovery DBER The availability of the features may vary between processor SKUs Power Management Support Processor Core e Full support of ACPI C states as implemented by the following processor C states C0 Ci C1E C3 C6 C7 C8 C9 C10 e Enhanced Intel SpeedStep Technology System e S0 S3 S4 S5 Memory Controller e Conditional self refresh e Dynamic power down Processor Graphics Controller e Intel Rapid Memory Power Management Intel RMPM e Intel Smart 2D Display Technology Intel S2DDT e Graphics Render C state RC6 e Intel Seamless Display Refresh Rate Switching with eDP port e Intel Display Power Saving Technology Intel DPST Thermal Management Support e Digital Thermal Sensor e Adaptive Therma
74. Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron9 Processor Family March 2015 Datasheet Volume 1 of 2 Order No 330834 004v1 83 Processor Electrical Specifications 2 em D B B B B B B B B Hex Vec B B BIB B B B B Hex Vec i Li Li Li Ji f il i iJ i Li i li Li Jii tjt tt tt t t t tt ttt t t 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1J 0 0 1 0 1 0J CAh 2 5100 1111 0 110 0 ECh 2 8500 1 1 J 0 0 1 0 1 1 CBh 2 5200 1111 0 i 10 1 EDh 2 8600 1 1 J 0 0 1 1 0 0J CCh 2 5300 11111011111 0 EEh 2 8700 1 1 J 0 0 1 1 0 1 CDh 2 5400 111110111 1 EFh 2 8800 1 1 J 0 J 0 1 1 1 0J CEh 2 5500 1111 1 00 0 0J FOh 2 8900 1 i J 0 0 11 1 1 CFh 2 5600 111111 0100 1 F1h 2 9000 1 1 J 0 1 0 0 0 0 J DOh 2 5700 111111 001 0 F2h 2 9100 1 1 J 0 1 0 0 01 Dih 2 5800 111111 01011 F3h 2 9200 1 1 J 0 1 0 0 1 0J D2h 2 5900 111111 010 0 F4h 2 9300 1 1 J 0 1 0 0 1 1 D3h 2 6000 111111 0110 1 F5h 2 9400 1 1 J 0 1 0 1 0 0J D4h 2 6100 111111 011 0 F6h 2 9500 1 1 J 0 1 0 1 0 1 D5h 2 6200 11111101111 FZh 2 9600 1 1 J 0 1 0 1 1 0J D6h 2 6300 11111110 0 0J F8h 2 9700 1 1 J 0 1 0 1 1 1
75. D H18 SA_CAS AU34 RSVD AM11 RSVD AN10 SA CKEO AU43 RSVD AV62 RSVD AM10 SA CKE1 AW43 RSVD D58 RSVD L59 SA_CKE2 AY42 RSVD P20 RSVD J58 SA CKE3 AY43 RSVD R20 RSVD Y20 SA_CLK 0 AU37 RSVD N60 RSVD AC20 SA_CLK 1 AW36 RSVD AV2 RSVD V21 SA_CLKO AV37 RSVD AF20 RSVD N58 SA_CLK1 AY36 RSVD AB21 RSVD AC58 SA_CS 0 AP33 RSVD AY14 RSVD AB23 SA_CS 1 AR32 RSVD AW14 RSVD AD23 SA DQO AH63 RSVD E15 RSVD AA23 SA DQ1 AH62 RSVD E13 RSVD AE59 SA DQ10 AP63 RSVD AL11 RSVD K18 SA DQ11 AP62 RSVD ACA RSVD M20 SA DQ12 AM61 RSVD A5 RSVD K21 SA DQ13 AM60 RSVD N23 RSVD M21 SA DQ14 AP61 RSVD T23 RSVD TP AV63 SA DQ15 AP60 RSVD U10 RSVD TP AU63 SA DQ32 AY58 RSVD R23 RSVD TP C63 SA DQ33 AW58 RSVD L11 RSVD_TP C62 SA DQ34 AY56 RSVD K10 RSVD TP A51 SA DQ35 AW56 RSVD F22 RSVD_TP B51 SA DQ2 AK63 RSVD H22 RSVD TP P60 SA DQ36 AV58 RSVD J21 RSVD_TP P61 SA DQ37 AU58 RSVD AT2 IVR_ERROR N59 SA_D038 AV56 RSVD AU44 IST_TRIGGER N61 SA DQ39 AU56 RSVD AV44 RSVD_TP L60 SA DQ40 AY54 RSVD D15 RTCRST AU7 SA_DQ41 AW54 RSVD AU10 RTCX1 AW5 SA_DQ42 AY52 RSVD AU15 RTCX2 AY5 SA DQ43 AW52 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 114 Order No March 2015 330834 004v1 Processor Ball and Signal Information Processor intel
76. DR are pre charged when de asserting CKE Power saving in this mode is intermediate better than APD but less than DLL off Power consumption is defined by IDD2P1 Exiting this mode is defined by tXP The difference from APD mode is that when 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 Order No 330834 004v1 55 m e n tel Processor Power Management 4 3 2 1 4 3 2 2 waking up all page buffers are empty The LPDDR does not have a DLL As a result the power savings are as good as PPD DLL off but will have lower exit latency and higher performance The CKE is determined per rank whenever it is inactive Each rank has an idle counter The idle counter starts counting as soon as the rank has no accesses and if it expires the rank may enter power down while no new transactions to the rank arrives to queues The idle counter begins counting at the last incoming transaction arrival It is important to understand that since the power down decision is per rank the IMC can find many opportunities to power down ranks even while running memory intensive applications the savings are significant may be few Watts according to the DDR specification This is significant when each channel is populated with more ranks Selection of power modes should be according to pow
77. DTS indicates that it has reached the TCC activation a reading of Oh except when the TCC activation offset is changed the TCC will activate and indicate an Adaptive Thermal Monitor event A TCC activation will lower both IA core and graphics core frequency voltage or both Changes to the temperature can be detected using two programmable thresholds located in the processor thermal MSRs These thresholds have the capability of generating interrupts using the core s local APIC Refer to the Intel 64 and IA 32 Architectures Software Developer s Manual for specific register and programming details 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 68 Order No 330834 004v1 m e Thermal Management Processor n tel 5 6 2 1 5 6 2 2 5 6 3 5 6 3 1 Note 5 6 3 2 Digital Thermal Sensor Accuracy Taccuracy The DTS is expected to work within x5 C over the operating range Fan Speed Control with Digital Thermal Sensor Digital Thermal Sensor based fan speed control Tran is a recommended feature to achieve optimal thermal performance At the Tran temperature Intel recommends full cooling capability well before the DTS reading reaches Tjmax PROCHOT Signal PROCHOT processor hot is asserted when the processor temperature has reached its maximum operating tempera
78. DZh 2 6400 11111110 0 1 F9h 2 9800 1 1 J 0 1 1 0 0 0J D8h 2 6500 11111110110 FAh 2 9900 1 1i J 0 11 0 01J D9h 2 6600 1111111011 1 FBh 3 0000 1 1J 01 1 0 1 0J DAh 2 6700 1111111110 0 FCh 3 0100 1 1 J 0 1 1 0 1 1 DBh 2 6800 1111111110 1 FDh 3 0200 1 1 J 0 1 1 1 0 0J DCh 2 6900 111111111 0 FEh 3 0300 1 1J 01 1 1 01 DDh 2 7000 11111111 111 1 FFh 3 0400 1 1i J 0 1 1 1 J1 0J DEh 2 7100 1 1iJ 0 1 1 1 1 1 DFh 2 7200 1 1 J 1 0 0 0 0 0J EOh 2 7300 1 1iJ 1 0 0 0 0 1J Eth 2 7400 1 i J 1 0 0 0 1 0J E2h 2 7500 1 1 J 1 0 0 0 1 1 E3h 2 7600 1 1i J 1 0 0 1 0 0J E4h 2 7700 1 1i J 1 0 0 1 0 1J E5h 2 7800 1 i J 1 0 0 1 1 0J E6h 2 7900 1 1 1 0 0 1 1 1 E7h 2 8000 1 1i J 1 0 1 0 0 0J E8h 2 8100 1 i J 1 0 1 0 0 1J E9h 2 8200 1 1i J1J 0 1 0 1 0J EAh 2 8300 1 i J1J 0 1 0 1 1 EBh 2 8400 continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 84 Order No 330834 004v1 m Electrical Specifications Processor n te 7 4 7 5 Note Table 39 Reserved or Unused Signals The following are the general types of reserved RSVD signals and connection guidelines e RSVD these signals should not be connected e RSVD_TP these signals shou
79. Datasheet The 5th Generation Intel Core Processor Family I O Intel Core M Processor 330838 Family I O Mobile Intel Pentium Processor Family I O and Mobile Intel Celeron Processor Family I O Specification Update Advanced Configuration and Power Interface 3 0 http www acpi info continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 16 March 2015 Order No 330834 004v1 m Introduction Processor n tel Document Document Number Location DDR3 SDRAM Specification http www jedec org DisplayPort Specification http www vesa org Intel 64 and IA 32 Architectures Software Developer s Manuals http www intel com products processor manuals index htm 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 330834 004v1 17 m n tel Processor Interfaces 2 1 2 1 1 Table 3 Interfaces System Memory Interface e LPDDR3 down or DDR3L DDR3L RS Non ECC Unbuffered Small Outline Dual In Line Memory Modules with a maximum of one DIMM per channel or down e LPDDR3 memory I O Voltage of 1 2V DDR3L DDR3L RS I O Voltage of 1
80. ETn5 L2 B21 RSVD AD60 PCH TRST AU62 PETn5 L3 B22 RSVD AD59 PCIE IREF B27 PETp1 USB3Tp3 C31 RSVD AA59 PCIE_RCOMP A27 PETp2 USB3Tp4 A31 RSVD AE60 PCIECLKRQO U2 GPIO18 PETp3 B30 RSVD AC59 PCIECLKRQ1 Y5 PETp4 A29 RSVD AG58 GPI019 PETp5 LO C22 RSVD V59 PCIECLKRQ2 AD1 GPIO20 PETp5 L1 A23 RSVD U59 PCIECLKRQ3 N1 PETp5_L2 C21 RSVD AL1 GPIO21 PETp5 L3 A21 RSVD AP7 PCIECLKRQ4 U5 GPIO22 PIRQA GPIO77 U6 RSVD AM11 PCIECLKRQS T PIROB GPIO78 P4 RSVD AV62 ene PIRQC GPIO79 N4 RSVD D58 PECI Nee PIRQD GPIO80 N2 RSVD P20 PERNT USB3RNJ S17 PLTRST AG7 RSVD R20 PERn2 USB3Rn4 F15 PME AD4 RSVD N60 PERDS Sil PRDY J62 RSVD AV2 PERDA F13 PREQ K62 RSVD AF20 PERn5 LO F10 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron9 Processor Family March 2015 Order No 330834 004v1 Datasheet Volume 1 of 2 125 Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 RSVD AB21 RSVD AC58 SA_CS 0 AP33 RSVD AY14 RSVD AB23 SA_CS 1 AR32 RSVD AW14 RSVD AD23 SA DQO AH63 RSVD E15 RSVD AA23 SA DQ1 AH62 RSVD E13 RSVD AE59 SA DQ10 AP63 RSVD AL11 RSVD K18 SA DQ11 AP62 RSVD ACA RS
81. Enforcing manufacture provided Boot Policy using Intel architectural components Benefits of this protection is that Intel Device Protection with Boot Guard can help maintain platform integrity by preventing re purposing of the manufacturer s hardware to run an unauthorized software stack Intel Device Protection with Boot Guard technology availability may vary between the different SKUs Supervisor Mode Execution Protection SMEP Supervisor Mode Execution Protection provides the next level of system protection by blocking malicious software attacks from user mode code when the system is running in the highest privilege level This technology helps to protect from virus attacks and unwanted code from harming the system For more information refer to Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A at http www intel com Assets PDF manual 253668 pdf 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 42 Order No 330834 004v1 Bi Technologies Processor n tel 3 12 3 13 Supervisor Mode Access Protection SMAP Supervisor Mode Access Protection provides the next level of system protection by blocking a malicious user from tricking the operating system into branching off user data This technology shuts down very popular attack vectors against o
82. Junction temperature Ti nen 0 105 ec 4 Dual Core GT3 28 W TDP J imit 3 Intel Core U Processor Line Junction temperature b Dual Core GT3 15 W TDP Tj imit 0 C 105 c 3 4 Intel Core U Processor Line Junction temperature Dual Core GT2 15 W TDP Ti imit 0 C 105 c 3 4 Intel Pentium Processor T Junction temperature 0 R 105 oC 3 4 Intel Celeron Processor imit Intel Core M Processor T5 m temperature 0 95 oc 3 4 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 Order No 330834 004v1 65 intel Processor Thermal Management Table 23 Idle Power Specification Symbol Parameter Min Typical Max Unit Note PPACKAGE C6 Package power in Package C6 state 0 6 W 1 2 PPACKAGE C7 Package power in Package C7 state 0 4 WwW 1 2 PPACKAGE C9 Package power in Package C9 state 0 03 Ww 1 2 PPACKAGE C10 Package power in Package C10 state 0 03 W 1 2 5 6 5 6 1 Note Notes 1 Package power includes both components in the processor package processor and PCH 2 The power specification based on pre silicon estimations and may be subject to change 3 Measured at Tj 35 C 4 The idle power specifications are not 100 tested These power specifications are determined by
83. L DDR3L RS Clock 5 11 Ron_up ck Buffer pull up 20 26 32 Q 13 Resistance DDR3L DDR3L RS Clock 5 11 Row pN CK Buffer pull down 20 26 32 Q 13 Resistance DDR3L DDR3L RS 5 11 Ron_uP CMD Command Buffer pull 15 20 25 Q 13 up Resistance DDR3L DDR3L RS 5 11 Ron_DN CMD Command Buffer pull 15 20 25 Q 13 d down Resistance DDR3L DDR3L RS 5 11 Ron_UP CTL Control Buffer pull up 19 25 31 Q 13 d Resistance DDR3L DDR3L RS 5 11 RoN pN CTL Control Buffer pull down 19 25 31 Q 13 Resistance System Memory Power Ron_UP SM_PG_CNTL1 Gate Control Buffer 40 80 130 9 13 Pull Up Resistance System Memory Power RON_DN SM_PG_CNTL1 Gate Control Buffer 40 80 130 Q 13 Pull Down Resistance Input Leakage Current DQ CK Ii 0V zu 0 7 mA 0 2 Vppo 0 8 Vppo Input Leakage Current CMD CTL Iu 0V _ _ 1 0 mA _ 0 2 Vppo 0 8 Vppo SM RCOMPO command V 198 200 202 s i esistance continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 90 March 2015 Order No 330834 004v1 Electrical Specifications Processor n te Symbol Parameter Min Typ Max Units Notes SM_RCOMP1 Data COMP Resistance 118 8 120 121 2 Q 8 SM_RCOMP2 ODT COMP Resistance 99 100 101 Q 8 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies
84. Memory Signals Signal Name Description Direction Buffer Type SA CK 0 SA CK 0 Clocks CK and its complement CK signal make up a differential clock pair The crossing of the positive edge of CK SB_CK 0 SB_CK 0 and the negative edge of its complement CK are used to sample the command and control signals SA_MA 15 0 Memory Address These signals are used to provide the O SB_MA 15 0 multiplexed row and column address SA_BS 2 0 SB_BS 2 0 Bank Select Signals used to define which bank a command o is being applied to SA_WE SB_WE Write Enable These signals are used with RAS and CAS o to define the command being entered continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 72 March 2015 Order No 330834 004v1 Signal Description Processor Table 26 intel Signal Name Description Direction Buffer Type RAS These signals are used with CAS4 and WEZ to define SAGA SB RASS the command being entered 2 SA_CAS SB_CAS CAS These signals are used with RAS and WE to define o the command being entered SA_DQS 7 0 Data Strobes DQS and its complement DQS signal make SA_DQS 7 0 up a differential strobe pair The data is captured at the yo SB_DQS 7 0 cro
85. NCTF B62 e DAISY CHAIN NCTF B63 to DAISY CHAIN NCTF A60 Package AY1 Corner e DAISY CHAIN NCTF AW1 to DAISY CHAIN NCTF AW3 e DAISY CHAIN NCTF AY3 to DAISY CHAIN NCTF AW2 e DAISY CHAIN NCTF AY2 to DAISY CHAIN NCTF AV1i Package AY63 Corner e DAISY CHAIN NCTF AY60 to DAISY CHAIN NCTF AW61 e DAISY CHAIN NCTF AY61 to DAISY CHAIN NCTF AW62 e DAISY CHAIN NCTF AY62 to DAISY CHAIN NCTF AW63 GND DAISY CHAIN NCTF Ball BGA 1234 package Daisy Chain Non Critical to Function These signals are for BGA solder joint reliability testing and are non critical to function These signals are connected on the processor package as follows Package A1 Corner e DAISY CHAIN NCTF F1 to DAISY CHAIN NCTF H2 e DAISY CHAIN NCTF F3 to DAISY CHAIN NCTF D2 Package A45 Corner e DAISY CHAIN NCTF A44 to DAISY CHAIN NCTF C43 e DAISY CHAIN NCTF D44 to DAISY CHAIN NCTF F43 e DAISY CHAIN NCTF F45 to DAISY CHAIN NCTF C45 Note Daisy Chain NCTF H44 is not connected in package 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 78 March 2015 Order No 330834 004v1 Signal Description Processor intel 6 12 Processor Internal Pull Up Pull Down Terminations Table 37 Processor Internal Pull Up Pull Down Terminations Signal Na
86. Order No 330834 004v1 Technologies Processor n tel 3 0 3 1 Technologies This chapter provides a high level description of Intel technologies implemented in the processor The implementation of the features may vary between the processor SKUs Details on the different technologies of Intel processors and other relevant external notes are located at the Intel technology web site http www intel com technology Intel Virtualization Technology Intel VT Intel virtualization Technology Intel VT makes a single system appear as multiple independent systems to software This allows multiple independent operating systems to run simultaneously on a single system Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets Intel Virtualization Technology Intel VT for IA 32 Intel 64 and Intel Architecture Intel VT x added hardware support in the processor to improve the virtualization performance and robustness Intel Virtualization Technology for Directed I O Intel VT d extends Intel VT x by adding hardware assisted support to improve I O device virtualization performance Intel VT x specifications and functional descriptions are included in the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B and is available at http www intel com products processor manuals index htm The Intel VT d speci
87. P Thermal Solution Design and PROCHOTZ Behavior With a properly designed and characterized thermal solution it is anticipated that PROCHOT will only be asserted for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable However an under designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may e Cause a noticeable performance loss e Result in prolonged operation at or above the specified maximum junction temperature and affect the long term reliability of the processor e May be incapable of cooling the processor even when the TCC is active continuously in extreme situations Low Power States and PROCHOT Behavior Depending on package power levels during package C states outbound PROCHOT may de assert while the processor is idle as power is removed from the signal Upon wakeup if the processor is still hot the PROCHOT will re assert although typically package idle state residency should resolve any thermal issues The PECI interface is fully operational during all C states and it is expected that the platform continues to manage processor core and package thermals even during idle states by regularly polling for thermal data over PECI THERMTRIP Signal Regardless of enabling the automatic or on
88. PC3 Disabled Multiple 3200x2000 60 Hz PC3 Disabled Multiple 3840x2160 30 Hz PC6 Disabled Multiple 4096x2160 24 Hz PC6 Disabled Multiple 3840x2160 60 Hz PC3 Disabled Multiple 4096x2304 60 Hz 1 PC3 or PC2 Enabled Single Any resolution PC7 PLUS Notes 1 For multiple display cases the resolution listed is the highest native resolution of all enabled displays that is dual display with one 1920x1200 60 Hz display and one 3200x2000 60 Hz display will result in a deepest available package C state of PC3 2 For non native resolutions the deepest available package C State will be somewhere between that of the native resolution and the non native resolution that is a non PSR single display native 4096x2304 60 Hz panel using non native 1920x1080 60 Hz resolution will result in a deepest available package C State between PC6 and PC7 PLUS 3 PSRis internally disabled when multiple displays are enabled Thus the result for multiple displays with PSR enabled is the same as with PSR disabled 4 Resolution not supported by Intel Core M processor family These screen resolutions are examples using common values for blanking and pixel rate Actual results will vary This information shows the deepest possible Package C state System workload system idle and AC or DC power also affect the deepest possible Package C state 4 3 Integrated Memory Controller IMC Power Management The main memory is power managed during normal
89. PIO64 E3 SPI CLK AA3 USB2n1 AR7 SDIO_CMD GPIO65 F4 SPI CSO Y7 USB2n2 AR8 SDIO_D0 GPIO66 D3 SPI CS1 Y4 USB2n3 AR10 SDIO D1 GPIO67 E4 SPI CS2 AC2 USB2n4 AM15 SDIO D2 GPIO68 C3 SPI IO2 Y6 USB2n5 AM13 SDIO_D3 GPIO69 E2 SPI IO3 AF1 USB2n6 AP11 SDIO_POWER_EN C4 SPI MISO AA4 USB2n7 AR13 GPIO70 SPI MOSI AA2 USB2pO AM8 SERIRO T4 SPKR GPIO81 V2 USB2p1 AT7 SLP_A AL5 SRTCRST AV6 USB2p2 AP8 SLP_LAN AJ7 SUS_STAT AG4 USB2p3 AT10 SLP SO AF3 GPIO61 USB2p4 AL15 SLP_S3 AT4 SUSACK AK2 USB2p5 AN13 SLP_S4 AJ6 SUSCLK GPIO62 AE6 USB2p6 AN11 SLP_S5 GPIO63 AP5 SUSWARN AV4 SUSPWRDNACK USB2p7 AP13 SLP_SUS AP4 GPIO30 USB3Rn1 G20 SLP_WLAN AM5 SYS PWROK AG2 GPIO29 USB3Rn2 E18 SYS RESET AC3 SM DRAMRST AV15 USB3Rp1 H20 TD IREF B12 SM PG CNTL1 AV61 USB3Rp2 F18 TESTLOW AK8 AK8 SM RCOMPO AU60 USB3Tn1 C33 TESTLOW_AL8 AL8 SM_RCOMP1 AV60 USB3Tn2 B33 TESTLOW_C34 C34 SM_RCOMP2 AU61 USB3Tp1 B34 TESTLOW C35 C35 SM VREF CA AP49 USB3Tp2 A33 THERMTRIP D60 SM_VREF_DQO AR51 USBRBIAS AJ11 UARTO_CTS G1 SM VREF DQ1 AP51 GPIO94 USBRBIAS AJ10 SMBALERT AN2 UARTO_RTS J2 VCC F59 GPIO11 GPIO93 VCC AB57 SMBCLK AP2 UARTO_RXD Ji GPIO91 VCC AD57 SMBDATA AH1 SMLOALERT AL2 Ep AD is GPIO60 ve VCC C24 UART1_CTS J4 SMLOCLK AN1 GPIO3 VCC C28 SMLODATA AK1 UART1_RST J3 VCC C32 GPIO2 SML1ALERT AU4 VCC C36 PCHHOT GPIO73 UART1_RXD GPIOO K4 VCC C40 SML1CLK GPIO75 AU3 UART1_TXD GPIO1 G2 continu
90. Page Tables EPT EPT is hardware assisted page table virtualization It eliminates VM exits from the guest operating system to the VMM for shadow page table maintenance e Virtual Processor IDs VPID Ability to assign a VM ID to tag processor core hardware structures such as TLBs This avoids flushes on VM transitions to give a lower cost VM transition time and an overall reduction in virtualization overhead e Guest Preemption Timer Mechanism for a VMM to preempt the execution of a guest operating system after an amount of time specified by the VMM The VMM sets a timer value before entering a guest The feature aids VMM developers in flexibility and Quality of Service QoS guarantees 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 34 Order No 330834 004v1 En e Technologies Processor n tel e Descriptor Table Exiting Descriptor table exiting allows a VMM to protect a guest operating system from an internal malicious software based attack by preventing relocation of key system data structures like IDT interrupt descriptor table GDT global descriptor table LDT local descriptor table and TSS task segment selector AVMM using this feature can intercept by a VM exit attempts to relocate these data structures and pre
91. Q21 AK58 SB CAB9 AP40 SA DQ51 AM45 SB DQ50 AL21 SB CAB8 AR40 SA_DQ18 AM57 SB DQ51 AM22 SB CAB7 AK36 SA DQ52 AK45 SB DQ52 AN22 SB CAA7 AV47 SA DQ53 AK43 SB_D053 AP21 SB_CAA6 AU47 SA DQ54 AM40 SB_D054 AK21 SB CABO AK33 SA DQ55 AM42 SB DQ55 AK22 SB CAA9 AR46 SA DQ56 AM46 SB DQ56 AN20 SB CAA8 AP46 SA DQ57 AK46 SB DQ57 AR20 SB CAB5 AP42 SA DQ58 AM49 SB DQ58 AK18 NOT USED AR42 SA DQ59 AK49 SB DQ59 AL18 NOT USED AR45 SA DQ60 AM48 SA DQ22 AR57 SB CAAO0 AP45 SA DQ61 AK48 SB DQ60 AK20 SB CAA2 AW46 SA DQ19 AK57 SB DQ61 AM20 SB CAA4 AY46 SA DQ62 AM51 SB DQ62 AR18 SB CAA3 AY47 SA DQ63 AK51 SB DQ63 AP18 SB CAA1 AU46 SB DQ16 AM29 SA DQ23 AN57 SB ODTO AL32 SB DQ17 AK29 SA DQ24 AP55 SB CAB3 AM35 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 128 Order No March 2015 330834 004v1 Processor Ball and Signal Information Processor intel Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 SB CAB2 AK35 SMLIDATA GPIO74 AH3 USB2nO AN8 SDIO CLK G
92. R11 VSS AU57 VSS AM52 VSS AR15 VSS AU59 VSS AN17 VSS AR17 VSS AV14 VSS AN23 VSS AR23 VSS D62 VSS AN31 VSS AR31 VSS AV16 VSS AN32 VSS AR33 VSS AV20 VSS AN35 VSS AR39 VSS AV24 VSS AN36 VSS AP48 VSS AV28 VSS AN39 VSS AR49 VSS AV33 VSS AN40 VSS AR5 VSS AV34 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 132 Order No March 2015 330834 004v1 Processor Ball and Signal Information Processor intel Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 VSS AV36 VSS AY59 VSS D33 VSS AV39 VSS AY6 VSS D34 VSS AV41 VSS AY4 VSS D35 VSS AV43 VSS B20 VSS D37 VSS AV46 VSS B24 VSS D38 VSS AV49 VSS B26 VSS D39 VSS AV51 VSS B28 VSS D41 VSS AV55 VSS B32 VSS D42 VSS AV59 VSS C38 VSS D43 VSS AV8 VSS B36 VSS D45 VSS AW16 VSS B4 VSS D46 VSS AW24 VSS B40 VSS D47 VSS AW33 VSS B44 VSS D49 VSS AW35 VSS C14 VSS D50 VSS AW37 VSS B48 VSS D51 VSS AW4 VSS B52 VSS D53 VSS AW40 VSS B56 VSS D54 VSS AW42 VSS B60 VSS D55 VSS AW44 VSS C11 VSS D57 VSS AW47 VSS C18 VSS D59 VSS AW50 VSS C20 VSS E11 VSS AW51 VSS C25 VSS E17 VSS AW59 VSS C27 VSS F42 VSS AW60 VSS D12 VSS F20 VSS AY11 VSS D14 V
93. RTC AE7 DEVSLP1 GPIO38 L2 GPIO47 AB6 DCPSUS1 AD10 DEVSLP2 GPIO39 N5 GPIO48 U4 DCPSUS1 AD8 DIFFCLK_BIASREF C26 GPIO49 Y3 DCPSUS2 AH13 DPWROK AV5 GPIO50 P3 DCPSUS3 J13 DSWVRMEN AW7 GPIO51 R5 DCPSUS4 AB8 EDP_AUXN A45 GPIO52 L1 DCPSUSBYP AG19 EDP AUXP B45 GPIO53 L4 DCPSUSBYP AG20 eDP BKLCTL B8 GPIO54 L3 DDI1_TXN 0 C54 eDP_BKLEN A9 GPIO55 U7 DDI1_TXN 1 B58 EDP_DISP_UTIL A43 GPIO56 AG6 DDI1 TXN 2 B55 EDP HPD D6 GPIO57 AP1 DDI1 TXN 3 A57 EDP RCOMP D20 GPIO58 AL4 DDI1_TXP 0 C55 EDP TXNO C45 GPIO59 AT5 DDI1 TXP 1 C58 EDP TXN1 A47 GPIO8 AU2 DDI1_TXP 2 A55 EDP_TXN2 C47 GPIO9 AM3 DDI1_TXP 3 B57 EDP_TXN3 A49 GSPI_MOSI K2 GPIO90 DDI2_TXN 0 C51 EDP TXPO B46 GSPIO CLK GPIO84 L6 DDI2 TXN 1 C53 EDP TXP1 B47 GSPIO CS R6 DDI2 TXN 2 C49 EDP TXP2 C46 GPIO83 DDI2 TXN 3 A53 EDP TXP3 B49 GSPIO MISO N6 GPIO85 DDI2 TXP 0 C50 eDP VDDEN C6 GSPIO MOSI L8 DDI2 TXP 1 B54 GPIO10 AM2 GPIO86 DDI2 TXP 2 B50 GPIO13 AT3 GSPI1_CLK GPIO88 L5 DDI2 TXP 3 B53 GPIO14 AH4 GSPI1_CS R7 GPIO87 DDPB AUXN C5 GPIO15 AD6 GSPI1 MISO N7 DDPB AUXP B5 GPIO16 Yi GPIO89 DDPB CTRLCLK B9 GPIO17 T3 HDA BCLK AW8 DDPB_CTRLDATA C9 GPIO24 AD5 I250_SCLK HDA_DOCK_EN AW10 DDPB_HPD C8 GPIO25 AM4 I2S1_TXD DDPC_AUXN B6 GPIO26 AN3 HDA DOCK RST AV10 DDPC AUXP A6 GPIO27 AN5 I251_SFRM HDA_RST AU8 DDPC_CTRLCLK D9 GPIO28 AD7 125 MCLK DDPC CTRLDATA D11 GPIO44 AK4 HDA SDIO AY10 DDPC_HPD A8 GPIO45 AG5 12S0_RXD DEVSLPO GPIO33 P2 GPIO46 AG3 HDA_SDI1
94. R_READY CF43 VSS AC13 VSS AG19 VSS A10 VSS AC19 VSS AG24 VSS A16 VSS AC24 VSS AG28 VSS A20 VSS AC28 VSS AG32 VSS A36 VSS AC3 VSS AG35 VSS A40 VSS AC32 VSS AG37 VSS A42 VSS AC35 VSS AG39 VSS A6 VSS AC37 VSS AH12 VSS AA11 VSS AC41 VSS AH14 VSS AA19 VSS AC43 VSS AH15 VSS AA21 VSS AC5 VSS AH16 VSS AA22 VSS AC7 VSS AH17 VSS AA24 VSS AC9 VSS AH19 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 106 Order No March 2015 330834 004v1 Processor Ball and Signal Information Processor ntel Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 VSS AH20 VSS AM31 VSS AV9 VSS AH21 VSS AM35 VSS AW14 VSS AH22 VSS AM39 VSS AW44 VSS AH23 VSS AM45 VSS AY1 VSS AH25 VSS AN10 VSS AY13 VSS AH26 VSS AN12 VSS AY15 VSS AH27 VSS AN14 VSS AY39 VSS AH28 VSS AN2 VSS AY7 VSS AH29 VSS AN4 VSS BA44 VSS AH30 VSS AN40 VSS BB11 VSS AH31 VSS AN42 VSS BB13 VSS AH32 VSS AN44 VSS BB15 VSS AH33 VSS AN6 VSS BB3 VSS AH34 VSS AN8 VSS BB39 VSS AH44 VSS AP15 VSS BB5 VSS AH6 VSS AP39 VSS BB7 VSS AJ18 VSS AP43 VSS BB9 VSS AJ24 VSS AP7 VSS BC44 VSS AJ30 VSS AR12 VSS BD1 VSS AJ37 VSS AR14 VSS BD13
95. S C24 VSS CJ26 VSS BM15 VSS C28 VSS CJ30 VSS BM39 VSS C32 VSS CJ34 VSS BM7 VSS C36 VSS CK10 VSS BN14 VSS CA8 VSS CK29 VSS BN44 VSS CB13 VSS CK3 VSS BP13 VSS CB15 VSS CK33 VSS BP15 VSS CB39 VSS CK38 VSS BP39 VSS CB7 VSS CK44 VSS BP7 VSS CC10 VSS CL12 VSS BR14 VSS CC40 VSS CL24 VSS BR44 VSS CC42 VSS CL30 VSS BT1 VSS CC44 VSS CL32 VSS BT13 VSS CD1 VSS CL5 VSS BT39 VSS CD11 VSS CM15 VSS BT7 VSS CD13 VSS CM17 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 108 Order No March 2015 330834 004v1 Processor Ball and Signal Information Processor Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 VSS CM19 VSS CV41 VSS H42 VSS CM21 VSS CW12 VSS Ji VSS CM23 VSS CW14 VSS J16 VSS CM25 VSS CW16 VSS J20 VSS CM31 VSS CW18 VSS J24 VSS CM35 VSS CW20 VSS J28 VSS CM43 VSS CW22 VSS J3 VSS CN1 VSS CW24 VSS J32 VSS CN26 VSS CW26 VSS J43 VSS CN42 VSS CW28 VSS J45 VSS CN5 VSS CW30 VSS L16 VSS CN8 VSS CW32 VSS L2 VSS CP17 VSS CW34 VSS L20 VSS CP29 VSS CW5 VSS L24 VSS CP3 VSS CW8 VSS L28 VSS CR14 VSS CY10 VSS L32 VSS CR18 VSS CY7 VSS L38 VSS CR22 VSS D10 VSS N16 VSS CR2
96. SB DQSN3 AN25 SA DQ16 AP58 SB DQ24 AN26 SB DQSN6 AN21 SA DQ17 AR58 SB_D025 AR26 SB DQSN7 AN18 SA DQ26 AM54 SB DQ26 AR25 SA DQSP2 AN58 SA_DQ27 AK54 SB DQ27 AP25 SA DQSP3 AN55 SA DQ28 AL55 SB DQ28 AK26 SA DQSP6 AL42 SA DQ29 AK55 SB DQ29 AM26 SA DQSP7 AL49 SA DQ30 AR54 SB DQ30 AK25 SB DQSP2 AM28 SA DQ31 AN54 SB DQ31 AL25 SB DQSP3 AM25 SA DQ48 AK40 SB DQ48 AR21 SB DQSP6 AM21 SA DQ49 AK42 SB DQ49 AR22 SB DQSP7 AM18 SA DQ50 AM43 SA_D021 AK58 SB MAO AP40 SA DQ51 AM45 SB DQ50 AL21 SB MA1 AR40 SA DQ18 AM57 SB DQ51 AM22 SB MA10 AK36 SA DQ52 AK45 SB DQ52 AN22 SB MA11 AV47 SA DQ53 AK43 SB_D053 AP21 SB_MA12 AU47 SA DQ54 AM40 SB DQ54 AK21 SB MA13 AK33 SA DQ55 AM42 SB DQ55 AK22 SB MA14 AR46 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 116 Order No March 2015 330834 004v1 Processor Ball and Signal Information Processor intel Signal Name Ball Signal Name Ball Signal Name Ball DDR3 DDR3 DDR3 SB_MA15 AP46 SM_VREF_D00 AR51 THERMTRIP D60 SB_MA2 AP42 SM VREF DQ
97. SM DRAMRST AB2 LAN_PHY_PWR_CT Ji4 SA_DOSN7 BP9 DSWVRMEN G14 RL GPIO12 SB_DOSN2 BD11 EDP_AUXN AG16 GPIO13 E14 SB DQSN3 BH11 EDP AUXP AE17 GPIO14 M19 SB DQSN6 AK8 EDP DISP UTIL Y21 GPIO15 K25 SB DQSN7 AF8 EDP RCOMP AP41 GPIO16 N26 SA DQSPO CT15 EDP TXNO AD17 GPIO17 H31 SA_DOSP1 CU12 EDP_TXN1 AG18 PCIECLKRQO B33 GPIO18 SA_DQSP4 BV5 EDP TXPO AC17 PCIECLKRQ1 H25 SA DQSP5 BP5 EDP_TXP1 AE18 GPIO19 SB DQSPO BH3 PWR_DEBUG CK40 UART1_RST N39 SB_DQSP1 BD3 vss CJ20 niis PCIECLKRQ2 P25 SB_DQSP4 AK4 EDP_TXN2 AD18 GPIO20 SB DQSP5 AF4 EDP_TXN3 AA17 PCIECLKRQ3 P27 SA DQSP2 CU24 EDP TXP2 AC18 kane PCIECLKRQ4 D35 SA_DQSP3 CU20 EDP_TXP3 W17 GELTO SA_DQSP6 pud RSVD TP AA18 PCIECLKRO5 G30 SA DQSP7 BP11 RSVD TP Y18 GPIO23 SB_DQSP2 BD9 RSVD_TP CJ22 GO 2 r SB_DQSP3 BH9 RSVD_TP CK23 onon dd SB DQSP6 AK10 IVR ERROR CK27 GOZ BES SB_DQSP7 AF10 IST_TRIGGER CL26 GROE mU DDPB AUXN Y26 RSVD CK21 GEIO28 es SLP_WLAN J18 DDPC_AUXN Y25 E RSVD CL22 io DDPB_AUXP W26 RSVD CK25 UART1_CTS N30 DDPC_AUXP w25 RSVD CM27 GPIO3 continued DDPB_HPD Y30 RSVD CK19 continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 330834 004v1 101 Processor Processor Ball and Signal Information
98. SS A24 VSS AG61 VSS AJ52 VSS A28 VSS AG62 VSS AJ54 VSS A32 VSS AG63 VSS AJ56 VSS A36 VSS AH17 VSS AJ58 VSS A40 VSS AH19 VSS AJ60 VSS A48 VSS AH20 VSS AJ63 VSS A52 VSS AH22 VSS AK23 VSS A56 VSS AH24 VSS AK3 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron9 Processor Family Datasheet Volume 1 of 2 March 2015 Order No 330834 004v1 131 Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 VSS AK52 VSS AN42 VSS AR52 VSS AL10 VSS AN43 VSS AT13 VSS AL13 VSS AN45 VSS AT35 VSS AL17 VSS AN46 VSS AT37 VSS AL20 VSS AN48 VSS AT40 VSS AL22 VSS AN49 VSS AT42 VSS AL23 VSS AN51 VSS AT43 VSS AL26 VSS AN52 VSS AT46 VSS AL29 VSS AN60 VSS AT49 VSS AL31 VSS AN63 VSS AT61 VSS AL33 VSS AN7 VSS AT62 VSS AL36 VSS AP10 VSS AT63 VSS AL39 VSS AP17 VSS AU1 VSS AL40 VSS AP20 VSS AU16 VSS AL45 VSS AP22 VSS AU18 VSS AL46 VSS AP23 VSS AU20 VSS AL51 VSS AP26 VSS AU22 VSS AL52 VSS AP29 VSS AU24 VSS AL54 VSS AP3 VSS AU26 VSS AL57 VSS AP31 VSS AU28 VSS AL60 VSS AP38 VSS AU30 VSS AL61 VSS AP39 VSS AU33 VSS AM1 VSS AP52 VSS AU51 VSS AM17 VSS AP54 VSS AU53 VSS AM23 VSS AP57 VSS AU55 VSS AM31 VSS A
99. SS D5 VSS AY16 VSS D18 VSS F26 VSS AY18 VSS D21 VSS F30 VSS AY22 VSS D23 VSS F34 VSS AY24 VSS D25 VSS F38 VSS AY26 VSS D26 VSS G6 VSS AY30 VSS D27 VSS F46 VSS AY33 VSS D29 VSS F50 VSS AY51 VSS D2 VSS F54 VSS AY53 VSS D30 VSS F58 VSS AY57 VSS D31 VSS F61 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron9 Processor Family Datasheet Volume 1 of 2 March 2015 Order No 330834 004v1 133 Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 VSS G18 VSS U22 VSS G22 VSS U61 VSS G3 VSS V10 VSS G5 VSS V3 VSS G8 VSS V7 VSS H13 VSS W20 VSS H17 VSS Y10 VSS H57 VSS U9 VSS J10 VSS Y59 VSS J22 VSS Y63 VSS J59 VSS W22 VSS J63 VSS V58 VSS K1 VSS AH46 VSS K12 VSS V23 VSS R22 VSS AH16 VSS L13 VSS SENSE E62 VSS L15 WAKE AJ5 VSS L17 XTAL24_IN A25 VSS L18 XTAL24_OUT B25 VSS L20 VSS L58 VSS L61 VSS L7 VSS M22 VSS N10 VSS N3 VSS C57 VSS P59 VSS P63 VSS R10 VSS R8 VSS Ti VSS T58 VSS D8 VSS U20 continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2
100. T43 BPM 7 CR34 PCIE_IREF C41 PCIE_RCOMP F41 CL_CLK D23 PERn1 USB3Rn3 AF38 PECI CK42 CL DATA H23 PERn2 USB3Rn4 AH42 RSVD P17 CL RST K23 PERn3 AD38 PLTRST M23 CFG 0 CV27 PERn4 AH38 PME B25 CFG 1 CT27 PERn5 LO AF40 PMTEST_RST G26 CFG 10 CP31 PERn5 L1 AD40 PRDY CU40 CFG 11 CN32 PERn5_L2 AE43 PREQ CR41 CFG 12 CV33 PERn5 L3 AF42 PROCHOT CH41 CFG 13 CU34 PERp1 USB3Rp3 AE39 PWRBTN M21 CFG 14 CT33 PERp2 USB3Rp4 AJ43 RSMRST F7 CFG 15 CP33 PERp3 AC39 RTCX1 C9 CFG 2 CP27 PERp4 AH40 RTCX2 C7 CFG 3 CU28 PERp5 LO AG41 RTCRST A8 CFG 4 Cv29 PERp5_L1 AE41 SATA_IREF L42 CFG 5 CT29 PERp5 L2 AD42 RSVD R34 CFG 6 CM29 PERp5 L3 AG43 RSVD R32 CFG 7 CU30 PETn1 USB3Tn3 BD41 SATA_RCOMP L44 CFG 8 CN30 PETn2 USB3Tn4 BC40 SATA Rn0 V36 PERn6_L3 CFG 9 CV31 PETn3 AY41 SATA_Rn1 T37 CFG_RCOMP CR30 PETn4 AV41 PERn6_L2 CFG 16 CR28 PETn5 LO AU40 SATA_Rn2 Y38 PERn6 L1 CFG 18 CR32 PETn5 L1 AWAO SATA Rn3 W37 CFG 17 CN28 PETn5 L2 BA42 PERn6 LO CFG 19 CU32 PETn5_L3 BB41 SATA_Rp0 v38 T PERp6 L3 RSVD AJ14 PETp1 USB3Tp3 BD43 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 330834 004v1 103 n te Processor Processor Ball and Signal Information
101. VD M20 SA DQ12 AM61 RSVD A5 RSVD K21 SA DQ13 AM60 RSVD N23 RSVD M21 SA DQ14 AP61 RSVD T23 RSVD TP AV63 SA DQ15 AP60 RSVD U10 RSVD TP AU63 SA DQ32 AY58 RSVD R23 RSVD TP C63 SA DQ33 AW58 RSVD L11 RSVD_TP C62 SA_D034 AY56 RSVD K10 RSVD_TP A51 SA DQ35 AW56 RSVD F22 RSVD_TP B51 SA DQ2 AK63 RSVD H22 RSVD TP P60 SA DQ36 AV58 RSVD J21 RSVD TP P61 SA DQ37 AU58 RSVD AT2 IVR_ERROR N59 SA_D038 AV56 RSVD AU44 IST_TRIGGER N61 SA DQ39 AU56 RSVD AV44 RSVD_TP L60 SA_DQ40 AY54 RSVD D15 RTCRST AU7 SA_DQ41 AW54 RSVD AU10 RTCX1 AW5 SA DQ42 AY52 RSVD AU15 RTCX2 AY5 SA DQ43 AW52 RSVD El SA_CAB4 AU35 SA_DQ44 AV54 RSVD D1 SA_CAB6 AV35 SA DQ45 AU54 RSVD J20 SA_CAA5 AY41 SA_DQ3 AK62 RSVD H18 SA_CAB1 AU34 SA_DQ46 AV52 RSVD AN10 SA CKEO AU43 SA DQ47 AU52 RSVD AM10 SA CKE1 AW43 SB DQO AY31 RSVD L59 SA CKE2 AY42 SB DQ1 AW31 RSVD J58 SA_CKE3 AY43 SB DQ2 AY29 RSVD Y20 SA_CLK 0 AU37 SB_DQ3 AW29 RSVD AC20 SA_CLK 1 AW36 SB_DQ4 AV31 RSVD V21 SA_CLKO AV37 SB DQ5 AU31 RSVD N58 SA CLK1 AY36 SB DQ6 AV29 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 126 Order No March 2015 330834 004v1 Processor Ball and Signal Information Processor intel
102. VR to be designed to electrically support this current 5 Processor core VR to be designed to thermally support this current indefinitely 6 Long term reliability cannot be assured if tolerance ripple and core noise parameters are violated 7 Long term reliability cannot be assured in conditions above or below Maximum Minimum functional limits 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 88 Order No 330834 004v1 Electrical Specifications Processor intel Table 41 Memory Controller Vppo Supply DC Voltage and Current Specifications Parameter Min Typ Max Unit Note Processor I O supply VDD0 DDR3L DDR3L Rs voltage for DDR3L DDR3L 1 35 V 2 3 RS Processor I O supply VDDQ LPDDR3 voltage for LPDDR3 E 1 20 E y a TOLppo VDDQ Tolerance AC DC 5 _ 5 2 3 CCMAx_vDDO DDR3L Max Current for VDDQ Rail 1 4 A 1 DDR3L RS DDR3L DDR3L RS Max Current for Vppq Rail 1 1 A 1 ICCMAX_VDDQ LPDDR3 LPDDR3 Notes 1 The current supplied to the DIMM modules is not included in this specification Includes AC and DC error where the AC noise is bandwidth limited to under 20 MHz 3 No requirement on the breakdown of AC versus DC noise Table 4
103. Voltage i _ Vi SM_DRAMPWROK 0 15 Vppo V Input High Voltage _ Vin SM DRAMPWROK 0 45 Vppo 1 0 Vppo V 10 13 LPDDR3 Data Buffer pull RoN ur bQ up Resistance 30 40 50 9 5 12 LPDDR3 Data Buffer pull RoN_DN DQ down Resistance 30 0 50 v 512 LPDDR3 On die RoDT DQ termination equivalent 150 200 250 Q 12 resistance for data signals LPDDR3 On die termination DC working Re Vopr bo point driver set to receive 0 45 Vppo 0 5 Vppo 0 55 Vppo v 12 mode LPDDR3 Clock Buffer pull Ron_UP CK up Resistance 30 40 50 a 5 12 LPDDR3 Clock Buffer pull RON_DN CK down Resistance d ne 99 Q 5 12 LPDDR3 Command Buffer RON_UP CMD pull up Resistance d a 31 Q 5 12 continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Order No 330834 004v1 Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 91 Processor Electrical Specifications Symbol Parameter Min Typ Max Unit Note LPDDR3 Command Buffer RON_DN CMD pull down Resistance 13 2n 31 9 apie LPDDR3 Control Buffer Ron_up cTL pull up Resistance 13 25 31 i 3 12 LPDDR3 Control Buffer RON_DN CTL pull down Resistance 19 25 31 2 5 12 LPDDR3 Reset Buffer pull RON_UP RST up Resistance i 40 90 130 9 B LPDDR3 Reset Buffer pull Row DN RST up Resistance i 4 a 130 9 z Input Leakage Current DQ CK Iu 0V
104. W3_3 AB14 VCC1_05_USB AE13 VCC CR45 VCCRTC AA15 VCCCLK6 AL30 VCC CU44 VCCSUS3_3_RTC AC15 VCCCLK2 AK31 VCC CV43 VCCSDIO A32 VCCASW AE15 VCC CV45 VCCSPI A24 VCC AV45 VCC CY13 VCCSPI T25 RSVD CJ28 VCC CY15 VCCSUS3_3 U18 continued continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron9 Processor Family March 2015 Datasheet Volume 1 of 2 Order No 330834 004v1 105 Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 VCCTS3 3 AB36 VSS AA25 VSS AD12 RSVD AL22 VSS AA26 VSS AD14 DCPRTC V15 VSS AA28 VSS AD16 RSVD AK33 VSS AA29 VSS AD19 VCCSATAPHY N45 VSS AA3 VSS AD24 VCCSATAPHY T45 VSS AA30 VSS AD28 RSVD CL14 VSS AA32 VSS AD32 VCCCLK7 AJ26 VSS AA33 VSS AD44 VCCCLK5 AL39 VSS AA34 VSS AD6 VCCST AJ20 VSS AA35 VSS AE16 VCCST_PWRGD BU14 VSS AA37 VSS AE19 DCPSUS1 U16 VSS AA39 VSS AE24 DCPSUS2 AG14 VSS AA5 VSS AE28 VCCUSB3PHY AC45 VSS AA7 VSS AE32 VCCUSB3PHY AD36 VSS AB12 VSS AE35 VCCUSB3PHY AE45 VSS AB15 VSS AE37 DCPSUS3 U30 VSS AB16 VSS AF12 VCCSUS3_3 AL14 VSS AB40 VSS AF14 VIDALERT CD43 VSS AB44 VSS AF16 VIDSCLK CD41 VSS AB8 VSS AF36 VIDSOUT CE40 VSS AC1 VSS AF44 VR_EN CE42 VSS AC11 VSS AF6 V
105. XN 3 A57 EDP_RCOMP D20 GPIO58 ALA DDI1_TXP 0 C55 EDP TXNO C45 GPIO59 AT5 DDI1_TXP 1 C58 EDP TXN1 A47 GPI08 AU2 DDI1_TXP 2 A55 EDP_TXN2 C47 GPIO9 AM3 DDI1_TXP 3 B57 EDP_TXN3 A49 GSPI_MOSI GPIO90 K2 DDI2_TXN 0 C51 EDP TXPO B46 GSPIO CLK GPIO84 L6 DDI2 TXN 1 C53 EDP_TXP1 B47 GSPIO_CS R6 GPIO83 DDI2 TXN 2 C49 EDP TXP2 C46 GSPIO_MISO N6 DDI2 TXN 3 A53 EDP TXP3 B49 GPIO85 DDI2_TXP 0 C50 eDP VDDEN C6 GSPI0_MOSI L8 GPIO86 DDI2 TXP 1 B54 GPIO10 AM2 GSPI1_CLK GPIO88 L5 DDI2 TXP 2 B50 GPIO13 AT3 GSPI1_CS R7 DDI2 TXP 3 B53 GPIO14 AH4 GPIOS87 DDPB AUXN C5 GPIO15 AD6 GSPI1_MISO N7 GPIO89 DDPB AUXP B5 GPIO16 Yi HDA BCLK AW8 DDPB_CTRLCLK B9 GPIO17 T3 12S0 SCLK DDPB CTRLDATA C9 GPIO24 AD5 HDA DOCK EN AW10 DDPB HPD C8 GPIO25 AM4 I251 TXD HDA DOCK RST AV10 DDPC AUXN B6 GPIO26 AN3 I251 SFRM DDPC AUXP A6 GPIO27 AN5 HDA_RST AUS DDPC CTRLCLK D9 GPIO28 AD7 I25_MCLK HDA SDIO AY10 DDPC CTRLDATA Dii GPIO44 AK4 368 RAD DDPC HPD A8 GPIO45 AG5 HDA SDI1 Ae DEVSLPO GPIO33 P2 GPIO46 AG3 I251 RXD DEVSLP1 GPIO38 12 GPIO47 AB6 HDA SDO AU11 I2S0 TXD DEVSLP2 GPIO39 N5 GPIO48 U4 HDA_SYNC AV11 DIFFCLK_BIASREF C26 GPI049 Y3 I2S0_SFRM DPWROK AV5 GPIO50 P3 HSIOPC GPIO71 Y2 DSWVRMEN AW7 GPIO51 R5 I2CO0 SCL GPIOS F3 EDP_AUXN A45 GPIO52 L1 I2CO SDA GPIO4 F2 EDP AUXP B45 GPIO53 L4 I2C1_SCL GPIO7 F1 eDP_BKLCTL B8 GPIO54 L3 I2C1 SDA GPIO6 G4 eDP_BKLEN A9 GPIO55 U7 12S1_SCLK AY8 EDP_DISP_UTIL A43 GPIO
106. Y2 CLKOUT_PCIE_N2 C41 CFG 0 AC60 CLKOUT_PCIE_N3 B38 pu i AYG CFG 1 AC62 CIKOUT PCIE NA A33 DAISY_CHAIN_NCTF AY60 CFG 10 v60 AYGO CLKOUT PCIE N5 B37 CFG 11 U60 CLKOUT PCIE PO C42 DAISY CHAIN NCTF AY61 CFG 12 T63 AY61 CLKOUT PCIE P1 A41 CFG 13 162 DAISY CHAIN NCTF AY62 CLKOUT PCIE P2 B42 _AY62 CFG 14 T61 14 CLKOUT_PCIE_P3 C37 DAISY_CHAIN_NCTF B2 CFG 15 T60 _B2 CLKOUT_PCIE_P4 B39 CFG 16 AA62 uni DAISY_CHAIN_NCTF B3 CLKOUT_PCIE_P5 A37 _B3 CFG 17 AA61 CLKRUN GPIO32 V5 DAISY CHAIN NCTF B61 CFG 18 U63 B61 DAISY CHAIN NCTF A3 CFG 19 U62 _A3 DAISY_CHAIN_NCTF B62 _B62 CFG 2 AC63 DAISY_CHAIN_NCTF A4 _A4 DAISY_CHAIN_NCTF B63 CFG 3 AA63 _B63 DAISY_CHAIN_NCTF A60 CFG 4 AA60 _A60 DAISY CHAIN NCTF C1 _Ci CFG 5 Y62 DAISY CHAIN NCTF A61 _A61 DAISY_CHAIN_NCTF C2 rele k s continued C2 continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Order No 330834 004v1 Mobile Intel Celeron9 Processor Family Datasheet Volume 1 of 2 111 Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball Signal Name Ball DDR3 DDR3 DDR3 DCP
107. _ _ 0 4 mA 0 2 VDDQ 0 8 Vppo Input Leakage Current CMD CTL Ii 0V 0 6 mA F 0 2 VDDQ 0 8 VDDQ SM_RCOMPO ODT COMP Resistance 198 200 202 8 SM_RCOMP1 Data COMP Resistance 118 8 120 121 2 8 sM_RCOMP2 Command COMP 99 100 101 Q 8 Resistance Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 V is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value 9 3 Vr is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value Vin and Vou may experience excursions above Vppo However input signal drivers must comply with the signal quality specifications This is the pull up down driver resistance RTERM is the termination on the DIMM and in not controlled by the processor The minimum and maximum values for these signals are programmable by BIOS to one of the two sets SM RCOMPx resistance must be provided on the system board with 1 resistors SM RCOMPx resistors are to VSS SM DRAMPWROK must have a maximum of 15 ns rise or fall time over Vppo 0 30 100 mV and the edge must be monotonic 10 SM VREF is defined as Vppo 2 11 Ron tolerance is preliminary and might be subject to change 12 Maximum minimum range is correct however center point is subject to change during MRC boot training 13 Processor may be damaged if Vj exceeds the ma
108. a a b man a daa A be aaa K a ka ra v nea b a n xa d 80 7 3 Vec Voltage Identification VID saadi 80 7 4 Reserved or Unused Sign ls sisina a j j 85 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 4 Order No 330834 004v1 m Contents Processor n tel j 79 SiGhal GFOUpS sis i js dd Mess j nes gg 85 7 6 Test Access Port TAP Connection scies xo ence aa Kol kena walk a as ga PER aa 87 7 7 DC Specifications iiie ten ze eet k bun dal k Kala Qa iet el Ra FREE ka a is 87 7 8 Voltage and Current Specifications a ayk kl kalak ka alal kal kala na kak Ek ka aaraa 87 7 8 1 Platform Environment Control Interface PECI DC Characteristics 94 7 8 2 Input Device Hiy Ste r S S s ks s l klklaelk dlke kalk la b b ka ke nga ganan Re nh uk e ma tres aa Rae nes 95 8 0 Package Specifications aa aa sasn asas rasa kk kaka nak kak anku kaka a an uan u nana un u ua ua au uan u uu uu a au kaka aa 96 8 1 Package Mechanical AttriDUL6S s k ks aseklilkak a keya kak kalak la ka lake ak ara a aian an nun hann 96 8 2 Package Loading Sp cifiGati 0S s lt i sik kd AME ka WW k l dala b k k kal dalal ka ana kak a a kl k ra kak 97 8 3 Package Storage Specifications ay aaa aa
109. ackage inductance and on die capacitances As a result the system memory controller uses a data scrambling feature to create pseudo random patterns on the system memory data bus to reduce the impact of any excessive di dt Processor Graphics The processor graphics contains a generation 8 graphics core architecture This enables substantial gains in performance and lower power consumption over previous generations 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 22 Order No 330834 004v1 m Interfaces Processor n tel j 2 3 2 3 1 e Next Generation Intel Clear Video Technology HD Support is a collection of video playback and enhancement features that improve the end user s viewing experience Encode transcode HD content Playback of high definition content including Blu ray Disc Superior image quality with sharper more colorful images Playback of Blu ray disc S3D content using HDMI 1 4a specification compliant with 3D e DirectX Video Acceleration DXVA support for accelerating video processing Full AVC VC1 MPEG2 HW Decode e Scalable Video Codec SVC Decode Encode HW Acceleration Extension of H 264 format Single video stream with multiple subset bit streams or enhancement layers e VP8 Decode HW Acceleration Open Source Codec
110. an internal thermal sensor This sensor is set well above the normal operating temperature to ensure that there are no false trips The processor will stop all execution when the junction temperature exceeds approximately 130 C This is signaled to the system by the THERMTRIP pin O Asynchronous OD 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 76 March 2015 Order No 330834 004v1 Signal Description Processor 6 8 Table 33 6 9 Table 34 Power Seguencing Signals Power Seguencing Signals intel Signal Name Description Direction Buffer Type PROCPWRGD The processor reguires this input signal to be a clean indication that the Vcc and Vppo power supplies are stable and within specifications This requirement applies regardless of the S state of the processor of sinking leakage current without glitches from the time that the power supplies are turned on until the supplies come within specification The signal must then transition monotonically to a high state Clean implies that the signal will remain low capable I Asynchronous CMOS VCCST PWRGD The processor requires this input signal to be a clean indication that the Vccsr and Vppo power supplies are a valid level during both SO and S3 power states of sinking leakag
111. and Current Specifications section The specifications are set so that one voltage regulator can operate with all supported frequencies Individual processor VID values may be set during manufacturing so that two devices at the same core frequency may have different default VID settings This is shown in the VID range values in the Voltage and Current Specifications section The processor provides the ability to operate while transitioning to an adjacent VID and its associated voltage This will represent a DC shift in the loadline 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 80 Order No 330834 004v1 Electrical Specifications Processor n tel Table 38 Voltage Regulator VR 12 5 Voltage Identification SB 888 88 8 Hex Vec 88 B 8 8 8 Hex Vec I I I I I I tjt ttt t t t tt t t ttt t 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 O 0 0 0 0 0 0 0 00h 0 0000 0 0 1 0 0 0 0 1 21h 0 8200 0 0 l 0 0 0 J 0 J 0l 1 01h 0 5000 0 0 1 0 0 0 11 0 22h 0 8300 O 0 0 0 0 0 1 0 02h 0 5100 0 0 1 0 0 0 1 1 23h 0 8400 O 0 0 0 0 0O 1 1 03h 0 5200 O 0 1 0 0 1 0 0 24h 0 8500 O 0 0 0 0 1 0 0 04h 0 5300 O 0 1
112. arks of Intel Corporation in the U S and or other countries Other names and brands may be claimed as the property of others Copyright 9 2014 2015 Intel Corporation All rights reserved 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 2 Order No 330834 004v1 m Contents Processor n tel j Contents Revision HistOfyY aa lk a 9 1 0 nini 10 1 1 Supported Technologies ss uinea iren et errata a kaxik dk ka ka a b a k ERN d k d rda 11 1 2 Power Management Su pport eiae rra hik W ae ra kt aua kak ya ak da na gans ak eaae s ka Q 12 1 3 Thermal Management S ppoFt 5 si sanes naya k xwan kane dla ala rece Aa nee ae sitaaa ke Ya ARENA 12 1 4 Package Support iiti sinisin ninaa exo nina na A ha ta a a a K d rgu ins d a na OE REA XA EUR TA m 13 1 5 Processor Testability iiie to retener cade eee de at W kn W n na na u Ae k a ka ERR ka An k E kan 13 1 6 FERMUINOIOGY E eee cr 13 1 7 Related Docutrnents ierant hal onere Raha h n xwana jams Bak deyne sii a ae a ara REA EE 16 2 0 Interfaces aaraa eee 18 2 1 System Memory Interface oci eere prepa team rk xke cea a
113. as sa an nan 60 5 1 Thermal Considerations si akil o daran niba baran Pen b d d k mija go k nA sa sagaida 60 5 2 Intel Turbo Boost Technology 2 0 Power Monitoring aa aaa 61 5 3 Intel Turbo Boost Technology 2 0 Power Control esses enn 61 5 3 1 Package Power Control z 5 san nanina banka 4da nad dabin Re L Sah A da RR RE Ra EMI ad 2 yad 61 5 3 2 Turbo Time Parameter ss o kiy esee pros acs sen ite ie ban n kaka d ya Pr aj s kay D ka n a da 62 5 4 Configurable TDP CTDP and Low Power MOde M MKh K A Wkk kk kk kk kk nemen 62 5 4 1 Configurable TDP 3 44 4iysk y iatbiy ana b ada h bat ca baba beway yA Da h dha d Wa y sag des gi d k a 63 5 4 2 LoW POWBF MO d zer icd ende gas ais kad a Pakas D A n ka 63 5 5 Thermal and Power Specifications aaraa 64 5 6 Thermal Management Fea t S sci Ac d la h ka wl kulak adn aa bal k k dodat cede das d k E ER XN RARE E 66 5 6 1 Adaptive Thermal Monitor aaa 66 5 6 2 Digital Th rm l S ns0f saa k anek an da kaa aene che n nan nea a n aa ata mada ked DOKN MEE 68 5 6 3 PROCHOT4 Sign l s asswsosae otra e denn in taga ente RARE entm ura n na RD ERE E RA 69 5 6 4 O Demand MOQ 70 5 6 5 Intel Memory Thermal Management k k k k k kk kk kk nnns 71 6 0 Signal DescriDt Okkkkkklllllkklklkkkkkkkkkkkkkk kaka aka kaka anka kaka kan nana au uan nu nuna an nanna uu nau
114. atform Environmental Control Interface PECI on page 31 When temperature is retrieved by the processor MSR it is the instantaneous temperature of the given core When temperature is retrieved using PECI it is the average of the highest DTS temperature in the package over a 256 ms time window Intel recommends using the PECI reported temperature for platform thermal control that benefits from averaging such as fan speed control The average DTS temperature may not be a good indicator of package Adaptive Thermal Monitor activation or rapid increases in temperature that triggers the Out of Specification status bit within the PACKAGE THERM STATUS MSR 1Bih and IA32 THERM STATUS MSR 19Ch Code execution is halted in C1 or deeper C states Package temperature can still be monitored through PECI in lower C states Unlike traditional thermal devices the DTS outputs a temperature relative to the maximum supported operating temperature of the processor Tjmax regardless of TCC activation offset It is the responsibility of software to convert the relative temperature to an absolute temperature The absolute reference temperature is readable in the TEMPERATURE TARGET MSR 1A2h The temperature returned by the DTS is an implied negative integer indicating the relative offset from Tjmax The DTS does not report temperatures greater than Tjmax The DTS relative temperature readout directly impacts the Adaptive Thermal Monitor trigger point When a package
115. ations TOM Non interleaved access B m o Dual channel interleaved access B B B CHA CH B CH A and CH B can be configured to be physical channels 0 or 1 B The largest physical memory amount of the smaller size memory module C The remaining physical memory amount of the larger size memory module Dual Channel Symmetric Mode Dual Channel Symmetric mode also known as interleaved mode provides maximum performance on real world applications Addresses are ping ponged between the channels after each cache line 64 byte boundary If there are two requests and the second request is to an address on the opposite channel from the first that request can be sent before data from the first request has returned If two consecutive cache lines are requested both may be retrieved simultaneously since they are ensured to be on opposite channels This mode is used when both Channel A and Channel B are populated with the same amount of total memory Data Scrambling The system memory controller incorporates a Data Scrambling feature to minimize the impact of excessive di dt on the platform system memory VRs due to successive 1s and Os on the data bus Past experience has demonstrated that traffic on the data bus is not random and can have energy concentrated at specific spectral harmonics creating high di dt which is generally limited by data patterns that excite resonance between the p
116. cessor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 Order No 330834 004v1 45 Table 15 Table 16 4 2 4 2 1 Processor Power Management Power down State Description Execution cores in this state behave similarly to the C6 state If all execution cores C7 reguest C7 state L3 cache ways are flushed until it is cleared If the entire L3 cache is flushed voltage will be removed from the L3 cache Power removal to SA Cores and L3 will reduce power consumption C8 C7 state plus voltage is removed from all power domains after reguired state is saved PLL is powered down C9 C8 state plus processor Vcc input voltage at 0 V C10 C9 state plus VR12 6 is set to low power state near shut off Integrated Memory Controller States State Description Power up CKE asserted Active mode Pre charge CKE de asserted not self refresh with all banks closed down Active Power CKE de asserted not self refresh with minimum one bank active Self Refresh CKE de asserted using device self refresh G S and C Interface State Combinations Global Sleep S Processor Processor System Clocks Description G State Package C State State State GO so CO Full On On Full On GO so C1 C1E Auto Halt On Auto Halt GO so C3 Deep S
117. chnology 2 0 operation since ACPI passive throttling states will pull the processor out of turbo mode operation when triggered An offset in degrees Celsius can be written to the TEMPERATURE TARGET 0x1A2 MSR bits 29 24 This value will be subtracted from the value found in bits 23 16 The default offset is 0 C TCC activation will occur at Tjmax The offset should be set lower than any other protection such as ACPI _ PSV trip points Frequency Voltage Control Upon Adaptive Thermal Monitor activation the processor core attempts to dynamically reduce processor core power by lowering the frequency and voltage operating point The operating points are automatically calculated by the processor core itself and do not require the BIOS to program them as with previous generations of Intel processors The processor core will scale the operating points such that e The voltage will be optimized according to the temperature the core bus ratio and number of cores in deep C states e The core power and temperature are reduced while minimizing performance degradation Once the temperature has dropped below the maximum operating temperature the operating frequency and voltage will transition back to the normal system operating point Once a target frequency bus ratio is resolved the processor core will transition to the new target automatically e Onan upward operating point transition the voltage transition precedes the frequency tran
118. clocks are stopped Core halted most core clocks stopped and voltage reduced to Pn gt Core halted most core clocks stopped J Core is executing code Possible combination of core package states EJ Impossible combination of core package states Note The core state relates to the core which is in the HIGHEST power state in the package most active Advanced Configuration and Power Interface ACPI States Supported This section describes the ACPI states supported by the processor System States State Description G0 SO Full On Mode Display On G0 SO Connected Standby Mode Display Off G1 S3 Cold Suspend to RAM STR Context saved to memory S3 Hot state is not supported by the processor G1 S4 Suspend to Disk STD All power lost except wakeup on PCH G2 S5 Soft off All power lost except wakeup on PCH Total reboot G3 Mechanical off All power removed from system Processor Core Package State Support State Description CO Active mode processor executing code C1 AutoHALT state C1E AutoHALT state with lowest freguency and voltage operating point C3 Execution cores in C3 state flush their L1 instruction cache L1 data cache and L2 cache to the L3 shared cache Clocks are shut off to each core C6 Execution cores in this state save their architectural state before removing core voltage continued 5th Generation Intel Core Pro
119. components float DQ and DQS during power up CKE signals remain LOW while any reset is active until the BIOS writes to a configuration register Using this method CKE is ensured to remain inactive for much longer than the specified 200 micro seconds after power and clocks to SDRAM devices are stable Conditional Self Refresh During SO idle state system memory may be conditionally placed into self refresh state when the processor is in package C3 or deeper power state Refer to Intel Rapid Memory Power Management Intel RMPM for more details on conditional self refresh with Intel HD Graphics enabled 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 56 Order No 330834 004v1 Power Management Processor Table 19 intel When entering the S3 Suspend to RAM STR state or SO conditional self refresh the processor core flushes pending cycles and then enters SDRAM ranks that are not used by Intel graphics memory into self refresh The CKE signals remain LOW so the SDRAM devices perform self refresh The target behavior is to enter self refresh for package C3 or deeper power states as long as there are no memory reguests to service The target usage is shown in the following table Targeted Memory State Conditions Mode Memory State with Processor Graphics Memor
120. cument the Mobile Intel Pentium processor family refers to the 3825U 3805U processor Throughout this document the Mobile Intel Celeron processor family refers to the 3755U and 3205U processors Refer to the processor Specification Update document for additional SKU details 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 10 Order No 330834 004v1 m Introduction Processor n te Figure 1 Processor Platform Block Diagram DDR3L LPDDR3 DDR Ch A Digital Display DDIx2 Interface x 2 eDP embedded Display Port i USB 2 0 3 0 HDA I2S JB Ul IEC UART or USB PCI Express 2 0 x8 d C 3 Accelometer 1 1 Supported Technologies e Intel Virtualization Technology Intel VT e Intel Active Management Technology 10 0 Intel AMT 10 e Intel Trusted Execution Technology Intel TXT e Intel Streaming SIMD Extensions 4 2 Intel SSE4 2 e Intel Hyper Threading Technology Intel HT Technology e Intel 64 Architecture e Execute Disable Bit e Intel Turbo Boost Technology 2 0 e Intel Advanced Vector Extensions 2 0 Intel AVX2 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel
121. ding Specifications iaire anir og aita i D kun 97 Package Storage Specif Cat OS hLh hKkNkkkkk kk kk kk kk kk kk kk kk kk kk kk kk kk nnne nnns 97 Intel Core M Processor Family LP DDR3 Non Interleaved k lk kh kl ez 98 U Processor Ball Information DDR3 Non Interleaved aaa 111 U Processor Ball Information LP DDR3 Non Interleaved kk kk 123 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 8 Order No 330834 004v1 Revision History Processor Revision History Revision Description Date 001 Initial Release September 2014 002 Added Intel Transactional Synchronization Extensions New Instructions Intel TSX NI Minor Updates throughout for clarity Added 5th Generation Intel Core Processor Family Added Intel Pentium processor family Added Intel Celeron processor family AddedIntel Core M processor 5Y71 5Y51 5Y31 and 5Y10C processors Updated Section 2 1 System Memory Interface Updated Section 2 1 1 System Memory Technology Supported Added Section 2 1 2 System Memory Timing Support Added Section 2 1 4 System Memory Frequency Updated Table 9 Multiple Display Configuration for Intel Core M Processor Updated Section 4 3 4 Package C States Added sentence to Package C7 State sub section
122. display devices connected The digital ports on the processor can be configured to support DisplayPort HDMI The following table shows examples of valid three display configurations through the processor Multiple Display Configuration for 5th Generation Intel Core Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Display 1 Display 2 Display 3 Maximum Maximum Maximum Notes Resolution Resolution Resolution Display 1 Display 2 Display 3 HDMI with HDMI with Active Level Active Level eDP 4096x2304 24 Hz i Shifter Shifter 3840x2160 HDMI HDMI eDP 2560x1600 60 Hz 60 Hz 3840x2160 DP DP eDP 3840x2160 60 Hz 60 Hz HDMI with i 4096x2304 3840x2160 3840x2160 Active Level DP eDP Shifter 24 Hz 60 Hz 60 Hz 2560x1600 3840x2160 3840x2160 nem Br Pee 60 Hz 60 Hz 60 Hz Note DP and eDP resolutions in this table are supported for 4 pixel bpp and single stream mode of operation anes with link data rate HBR2 at 24 bits per 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 Order No 330834 004v1 29 intel Processor Interfaces Table 10 Multiple Display Configuration for Intel Core M Processor Family D
123. e intel 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 Order No 330834 004v1 You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein You agree to grant Intel a non exclusive royalty free license to any patent claim thereafter drafted which includes subject matter disclosed herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document All information provided here is subject to change without notice Contact your Intel representative to obtain the latest Intel product specifications and roadmaps The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Copies of documents which have an order number and are referenced in this document may be obtained by calling 1 800 548 4725 or visit http www intel com design literature htm Intel technologies features and benefits depend on system configuration and may require enabled hardware software or service activation Learn more at http www intel com or from the OEM or retailer No computer system can be absolutely
124. e C States c ccccesscsceeeeeceececeneaeeseaeateeeeeneeeeeeeeaeeeeaeaensneneees 45 10 Idle Power Management Breakdown of the Processor Cores aaa 47 11 Package C State Entry and Exit cccccete adas r rr rer reer reaseseresrraare e ras 51 12 Package Power Control erii cesta tani tener a b ka da d gst aa daa ba RR ka h ke wla b n 62 13 Input Device Hyst re is isssisss suga ainas h ke ka d k xeu Ea FARBE dal kk aka ARA dera na AW aS 95 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 6 Order No 330834 004v1 m Tables Processor n tel Tables 1 TerminolOodY xi U m 13 2 Related DOCUMENTS sall nakin ea ken pete n ka hekar k n D ka Wak k na ana Diana hek ben n a k n DE ae e Eya a a ij 16 3 Processor DIMM Support Summary By Product h khk Kh C kk kkkkkkk kk kk kk eee ee nemen 18 4 Supported DDR3L DDR3L RS SO DIMM Module Configurations Per Channel 19 5 Supported DDR3L DDR3L RS Memory Down Configurations Per Channel 19 6 Supported LPDDR3 Memory Down Configurations Per Channel eese 19 7 DRAM System Memory Timing SUPPOFt cic aaa 20 8 Processor Supported Aud
125. e Command to READ or WRITE Command delay e tRP PRECHARGE Command Period e tCWL CAS Write Latency e Command Signal modes 1N indicates a new command may be issued every clock and 2N indicates a new command may be issued every 2 clocks Command launch mode programming depends on the transfer rate and memory configuration 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 Order No 330834 004v1 19 intel Table 7 2 1 3 Processor Interfaces DRAM System Memory Timing Support Processor DRAM Transfer tCL tRCD tRP tCWL Command Device Rate tCK tCK tCK tCK Mode MT s Intel Core M DDR3L 1333 8 9 8 9 8 9 7 1N 2N Processor DDR3L RS 1600 10 11 10 11 10 11 8 1N 2N LPDDR3 1333 10 12 12 7 0 5N 1600 12 15 15 8 0 5N Intel8 Core U DDR3L 1333 8 9 8 9 8 9 7 1N 2N Processor Line DDR3L RS Dual Core GT3 28W 1600 10 11 10 11 10 11 8 1N 2N IBP LPDDR3 1600 12 15 15 8 0 5N Dual Core GT3 15W TDP 1866 14 17 17 11 0 5N Intel Core U DDR3L 1333 8 9 8 9 8 9 7 1N 2N Processor Line DDR3L RS Dual Core GT2 15W 1600 10 11 10 11 10 11 8 1N 2N TRE LPDDR3 1333 10 12 12 7 0 5N 1600 12 15 15 8 0 5N Intel Pentium DDR3L 1333 8 9 8 9 8 9 7 1N 2N Processor DDR3L RS Intel Celeron 1600 10 11 10 11 10
126. e DDR does not go through training mode and will restore the previous training information Graphics Power Management Intel Rapid Memory Power Management Intel RMPM Intel Rapid Memory Power Management Intel RMPM conditionally places memory into self refresh when the processor is in package C3 or deeper power state to allow the system to remain in the lower power states longer for memory not reserved for graphics memory Intel RMPM functionality depends on graphics display state relevant only when processor graphics is being used as well as memory traffic patterns generated by other connected I O devices Graphics Render C State Render C state RC6 is a technique designed to optimize the average power to the graphics render engine during times of idleness RC6 is entered when the graphics render engine blitter engine and the video engine have no workload being currently worked on and no outstanding graphics memory transactions When the idleness condition is met the processor graphics will program the graphics render engine internal power rail into a low voltage state Intel Smart 2D Display Technology Intel S2DDT Intel S2DDT reduces display refresh memory traffic by reducing memory reads required for display refresh Power consumption is reduced by less accesses to the IMC Intel S2DDT is only enabled in single pipe mode Intel S2DDT is most effective with e Display images well suited to compression such as text windo
127. e Hysteresis The input buffers in both client and host models must use a Schmitt triggered input design for improved noise immunity Use the following figure as a guide for input buffer design Input Device Hysteresis Vino Maximum Vp Minimum Vp Maximum Vyn Minimum Vy PECI Ground PECI High Range jme pev PECI Low Range pev Minimum J Valid Input Hysteresis Signal Range 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family March 2015 Order No 330834 004v1 Datasheet Volume 1 of 2 95 8 1 Processor Package Specifications Package Specifications Package Mechanical Attributes The processors use a Flip Chip technology and Multi Chip package MCP available in a Ball Grid Array BGA package The following table provides an overview of the mechanical attributes of this package Table 52 Package Mechanical Attributes Parameter Intel Core U Processor Intel Pentium Processor Intel Celeron Processor Intel Core M Processor Package Type Flip Chip Ball Grid Array Flip Chip Ball Grid Array Configuration Land Side Capacitors Yes Interconnect Ball Grid Array BGA Ball Grid Array BGA Package Technology Lead Free Yes Yes Halogenated Flame Yes Yes Retardant Free Solder Ball Composition SAC405
128. e between performance and power savings The processor Vcc rail will remain a VID based voltage with a loadline similar to the core voltage rail also called Vcc in previous processors Power and Ground Pins The processor has VCC VDDQ and VSS ground pins for on chip power distribution All power pins must be connected to their respective processor power planes all VSS pins must be connected to the system ground plane Use of multiple power and ground planes is recommended to reduce I R drop The VCC pins must be supplied with the voltage determined by the processor Serial Voltage IDentification SVID interface Table 38 on page 81 specifies the voltage level for the various VIDs Vcc Voltage Identification VID The processor uses three signals for the serial voltage identification interface to support automatic selection of voltages The following table specifies the voltage level corresponding to the 8 bit VID value transmitted over serial VID A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the voltage regulation circuit cannot supply the voltage that is requested the voltage regulator must disable itself VID signals are CMOS push pull drivers See the Voltage and Current Specifications section for the DC specifications for these signals The VID codes will change due to temperature and or current load changes to minimize the power of the part A voltage range is provided in the Vo tage
129. e chipset PROC CNT Thermal throttling using this method will modulate all processor cores simultaneously 5 6 5 Intel Memory Thermal Management The processor provides thermal protection for system memory by throttling memory traffic when using either DIMM modules or a memory down implementation Two levels of throttling are supported by the processor either a warm threshold or hot threshold that is customizable through memory mapped I O registers Throttling based on the warm threshold should be an intermediate level of throttling Throttling based on the hot threshold should be the most severe The amount of throttling is dynamically controlled by the processor Memory temperature can be acquired through an on board thermal sensor TS on Board retrieved by an embedded controller and reported to the processor through the PECI 3 0 interface This methodology is known as PECI injected temperatures and is a method of Closed Loop Thermal Management CLTM CLTM requires the use of a physical thermal sensor EXTTS is another method of CLTM however it is only capable of reporting memory thermal status to the processor EXTTS consists of two GPIO pins on the PCH where the state of the pins is communicated internally to the processor When a physical thermal sensor is not available to report temperature the processor supports Open Loop Thermal Management OLTM that estimates the power consumed per rank of the memory using the processor DRAM
130. e current without glitches from the time that the power supplies are turned on until the supplies come within specification The signal must then transition monotonically to a high state stable and within specifications This single must have Clean implies that the signal will remain low capable I Asynchronous CMOS PROC DETECT Processor Detect This signal is pulled down directly 0 Ohms on the processor package to ground There System board designers may use this signal to determine if the processor is present is no connection to the processor silicon for this signal Processor Power Signals Processor Power Signals Signal Name Description Direction Buffer Type VCC Processor main power rail Ref Processor I O supply voltage for DDR3L DDR3L RS VDDQ LPDDR3 Bef VCCST Sustain voltage for the processor in standby modes Ref VIDSOUT VIDALERT VIDSCLK and VIDSCLK comprise a three I O CMOS VIDSCLK signal serial synchronous interface used to transfer O CMOS power management information between the VIDALERT processor and the voltage regulator controllers I CMOS Sideband output from the processor which controls disabling of the VR when the processor is in the C10 o VR_EN state This signal will be used to disable the VR only if the processor is configured to support VR disabling VR Enable CMOS using VR_CURRENT_CONFIG MSR 601h Sideband signal which indicates to the proce
131. ear worst case commercially available workload as specified by Intel for the SKU segment TDP may be exceeded for short periods of time or if running a power virus workload The processor integrates multiple processing and graphics cores and PCH on a single package This may result in differences in the power distribution across the die and must be considered when designing the thermal solution Intel Turbo Boost Technology 2 0 allows processor cores and processor graphics cores to run faster than the guaranteed frequency It is invoked opportunistically and automatically as long as the processor is conforming to its temperature power delivery and current specification limits When Intel Turbo Boost Technology 2 0 is enabled e Applications are expected to run closer to TDP more often as the processor will attempt to maximize performance by taking advantage of available TDP headroom in the processor package e The processor may exceed the TDP for short durations to use any available thermal capacitance within the thermal solution The duration and time of such operation can be limited by platform runtime configurable registers within the processor e Thermal solutions and platform cooling that are designed to less than thermal design guidance may experience thermal and performance issues since more applications will tend to run at or near TDP for significant periods of time Intel Turbo Boost Technology 2 0 availability may vary between t
132. ed continued continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Order No 330834 004v1 Mobile Intel Celeron9 Processor Family Datasheet Volume 1 of 2 129 Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 VCC C44 VCC G31 VCC3_3 w9 VCC C48 VCC G33 VCC3_3 K14 VCC C52 VCC G35 VCC3_3 K16 VCC C56 VCC G37 VCCACLKPLL A20 VCC E23 VCC G39 VCCAPLL AA21 VCC E25 VCC G41 VCCAPLL W21 VCC E27 VCC G43 VCCASW AE9 VCC E29 VCC G45 VCCASW AF9 VCC E31 VCC G47 VCCASW AG8 VCC E33 VCC G49 VCCASW AG13 VCC E35 VCC G51 VCCASW AG14 VCC E37 VCC G53 VCCCLK J18 VCC E39 VCC G55 VCCCLK K19 VCC E41 VCC G57 VCCCLK J17 VCC E43 VCC H23 VCCCLK T21 VCC E45 VCC J23 VCCCLK R21 VCC E47 VCC K23 VCCDSW3_3 AH10 VCC E49 VCC K57 VCCHDA AH14 VCC E51 VCC L22 VCCHSIO M9 VCC E53 VCC M23 VCCHSIO K9 VCC E55 VCC M57 VCCHSIO L10 VCC E57 VCC P57 VCCIO_OUT A59 VCC F24 VCC U57 VCOMP_OUT E20 VCC F28 VCC W57 VCCRTC AG10 VCC F32 VCC_SENSE E63 VCCSATA3PLL B11 VCC F36 VCC1_05 P9 VCCSDIO U8 VCC F40 VCC1_05 N8 VCCSDIO T9 VCC F44 VCC1_05 AE8 VCCSPI Y8 VCC F48 VCC1_05 AF22 VCCST AC22 VCC F52 VCC1_05 H11 VCCST AE22 VCC F56 VCC1_05 H15 VCCST AE23
133. ed in the ACPI protocol SDP Scenario Design Power SF Strips and Fans SMM System Management Mode SMX Safer Mode Extensions Storage Conditions A non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor landings should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air that is unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material SVID Serial Voltage Identification TAC Thermal Averaging Constant TAP Test Access Point on The case temperature of the processor measured at the geometric center of the top side of the TTV IHS TCC Thermal Control Circuit continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Order No 330834 004v1 Mobile Intel Celeron9 Processor Family Datasheet Volume 1 of 2 15 Processor Introduction Term Description TcoNrRo is a static value that is below the TCC activation temperature and used as a TconrRoL trigger point for fan speed control When DTS gt TconrRoL the processor mus
134. el Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 110 March 2015 Order No 330834 004v1 Processor Ball and Signal Information Processor intel 9 2 U Processor Ball Information BGA1168 This section contains ball information for the 5th Generation Intel Core processor family based on U Processor Line Mobile Intel Pentium processor family and Mobile Intel Celeron processor family Table 56 U Processor Ball Information DDR3 Non Interleaved Signal Name Ball Signal Name Ball Signal Name Ball DDR3 DDR3 DDR3 ACPRESENT AJ8 CFG 7 Y60 DAISY CHAIN NCTF A62 GPIO31 _A62 CFG 8 v62 APWROK AB5 DAISY_CHAIN_NCTF AV1 CFG 9 v61 _AV1 BATLOW GPIO72 AN4 CFG_RCOMP V63 DAISY CHAIN NCTF AW1 BMBUSY GPIO76 P1 _AW1 CL_CLK AF2 BPM 0 J60 DAISY_CHAIN_NCTF AW2 CL_DATA AD2 AW2 BPM 1 H60 CL_RST AF4 DAISY_CHAIN_NCTF AW3 BPM 2 H61 AW3 CLKOUT_ITPXDP_N B35 BPM 3 H62 DAISY_CHAIN_NCTF AW61 CLKOUT_ITPXDP_P A35 AW61 BPM 4 K59 CLKOUT_LPC 0 ANIS DAISY_CHAIN_NCTF AW62 BPM 5 H63 AW62 CLKOUT_LPC_1 AP15 BPM46 K60 CLKOUT PCIE NO C43 Be ade AMIS BPM 7 J61 CLKOUT_PCIE_N1 B41 CAYEBRE ker DATY CHAIN NCTE A
135. ency LSF at the LFM voltage has been made available for use under LPM for further reduction in active power beyond LFM capability to enable cooler and guieter modes of operation 5 5 Thermal and Power Specifications The following notes apply to Table 22 on page 65 Note Definition The TDP and Configurable TDP values are the average power dissipation in junction temperature operating 1 condition limit for the SKU Segment and Configuration for which the processor is validated during manufacturing when executing an associated Intel specified high complexity workload at the processor IA core frequency corresponding to the configuration and SKU 2 TDP workload may consist of a combination of processor core intensive and graphics core intensive applications 3 The thermal solution needs to ensure that the processor temperature does not exceed the maximum junction temperature Tjmax limit as measured by the DTS and the critical temperature bit 4 The processor junction temperature is monitored by Digital Temperature Sensors DTS For DTS accuracy refer to Digital Thermal Sensor Accuracy Taccuracy on page 69 5 At Tj of Timax 6 Can be modified at runtime by MSR writes with MMIO and with PECI commands Turbo Time Parameter is a mathematical parameter unit in seconds that controls the processor turbo algorithm 7 using a moving average of energy usage Do not set the Turbo Time Parameter to a value less than
136. er performance or thermal trade offs of a given system e When trying to achieve maximum performance and power or thermal consideration is not an issue use no power down e Ina system which tries to minimize power consumption try using the deepest power down mode possible PPD DLL off with a low idle timer value e In high performance systems with dense packaging that is tricky thermal design the power down mode should be considered in order to reduce the heating and avoid DDR throttling caused by the heating The default value that BIOS configures in PM PDWN config O0 0 0 MCHBAR is 6080h that is PPD DLL off mode with idle timer of 80h or 128 DCLKs This is a balanced setting with deep power down mode and moderate idle timer value The idle timer expiration count defines the number of DCKLs that a rank is idle that causes entry to the selected power mode As this timer is set to a shorter time the IMC will have more opportunities to put DDR in power down There is no BIOS hook to set this register Customers choosing to change the value of this register can do it by changing it in the BIOS For experiments this register can be modified in real time if BIOS does not lock the IMC registers Initialization Role of CKE During power up CKE is the only input to the SDRAM that has its level recognized other than the DDR3L DDR3L RS reset pin once power is applied It must be driven LOW by the DDR controller to make sure the SDRAM
137. events such as docking a system flipping a switch or pressing a button cTDP and LPM are designed to be configured dynamically and do not require an operating system reboot Configurable TDP and Low Power Mode technologies are not battery life improvement technologies 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 62 Order No 330834 004v1 Thermal Management Processor n tel 5 4 1 Note Table 20 5 4 2 Configurable TDP Configurable TDP availability may vary between the different SKUs With cTDP the processor is now capable of altering the maximum sustained power with an alternate IA core base frequency Configurable TDP allows operation in situations where extra cooling is available or situations where a cooler and quieter mode of operation is desired Configurable TDP can be enabled using Intel s DPTF driver or through HW EC firmware Enabling cTDP using the DPTF driver is recommended as Intel does not provide specific application or EC source code CTDP consists of three modes as shown in the following table Configurable TDP Modes Mode Description The average power dissipation and junction temperature operating condition limit for which the processor is validated during manufacturing when executing an associated Intel specified high compl
138. exity workload at the processor IA core frequency corresponding to the configuration and SKU Base The SKU specific processor IA core frequency where manufacturing confirms logical functionality within the set of operating condition limits specified for the SKU segment TDP Up and Configurable TDP Up configuration The Configurable TDP Up Frequency and corresponding TDP is higher than the processor IA core Base Frequency and SKU Segment Base TDP The processor IA core frequency where manufacturing confirms logical functionality within the set of operating condition limits specified for the SKU segment and TDP Down Configurable TDP Down configuration The Configurable TDP Down Frequency and corresponding TDP is lower than the processor IA core Base Frequency and SKU Segment Base TDP In each mode the Intel Turbo Boost Technology 2 0 power and frequency ranges are reprogrammed and the OS is given a new effective HFM operating point The Intel DPTF driver assists in all these operations The cTDP mode does not change the max per core turbo frequency Low Power Mode Low Power Mode LPM can provide cooler and quieter system operation By combining several active power limiting techniques the processor can consume less power while running at equivalent low frequencies Active power is defined as processor power consumed while a workload is running and does not refer to the power consumed during idle modes of operation LPM is on
139. f DQS and DQS during read and write SB_DQS 7 0 transactions SA_DQ 63 0 Data Bus Read and Write Input Output data signals yo SB_DQ 63 0 SA_CS 1 0 Chip Select These signals are used to select components SB _CS 1 0 during the active state There is one Chip Select for each O B DRAM rank SA_CKE 3 0 Clock Enable These signals are used to initialize and power o SB_CKE 3 0 state components There is one CKE for each DRAM rank SA_ODT 0 SB_ODT 0 On Die Termination Active Termination Control VREF_DQ_A VREF_DQ_B Data Reference Voltage Data Signal Reference Voltage VREF_CA Command Address Reference Voltage Command and o Address Signal Reference Voltage 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 Order No 330834 004v1 73 intel 6 2 Table 27 6 3 Table 28 Processor Signal Description Memory Compensation and Miscellaneous Signals LPDDR3 DDR3L DDR3L RS Reference and Compensation Signals Signal Name Description Direction Buffer Type SM_RCOMP 2 0 System Memory Impedance Compensation I SM PG CNTL1 System Memory Power Gate Control This signal disables the platform memory VTT regulator in C8 and deeper and S3 states CMOS OUTPUT Reset and Miscellaneous Sig
140. fication and other Intel VT documents can be referenced at http www intel com technology virtualization index htm https sharedspaces intel com sites PCDC SitePages Ingredients ingredient aspx ing VT Intel VT x Objectives Intel VT x provides hardware acceleration for virtualization of IA platforms Virtual Machine Monitor VMM can use Intel VT x features to provide an improved reliable virtualized platform By using Intel VT x a VMM is e Robust VMMs no longer need to use paravirtualization or binary translation This means that off the shelf operating systems and applications can be run without any special steps e Enhanced Intel VT enables VMMs to run 64 bit guest operating systems on IA x86 processors 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 Order No 330834 004v1 33 m n tel Processor Technologies e More reliable Due to the hardware support VMMs can now be smaller less complex and more efficient This improves reliability and availability and reduces the potential for software conflicts e More secure The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system Intel VT x Features The processor supports the following Intel VT x featu
141. gnals should be disabled to save power and reduce electromagnetic interference This includes all signals associated with an unused memory channel Clocks CKE ODE and CS signals are controlled per DIMM rank and will be powered down for unused ranks The I O buffer for an unused signal should be tri stated output driver disabled the input receiver differential sense amp should be disabled and any DLL circuitry related ONLY to unused signals should be disabled The input path must be gated to prevent spurious results due to noise on the unused signals typically handled automatically when input receiver is disabled DDR Electrical Power Gating EPG The DDR I O of the processor supports Electrical Power Gating DDR EPG while the processor is at C3 or deeper power state 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Order No 330834 004v1 Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 57 m n tel Processor Power Management 4 4 4 4 1 4 4 2 4 4 3 4 4 4 In C3 or deeper power state the processor internally gates Vppo for the majority of the logic to reduce idle power while keeping all critical DDR pins such as CKE and VREF in the appropriate state In C7 or deeper power state the processor internally gates Vccsr for all non critical state to reduce idle power In S3 or C state transitions th
142. gst active cores the processor takes the following into consideration e The number of cores operating in the CO state e The estimated core current consumption e The estimated package prior and present power consumption e The package temperature Any of these factors can affect the maximum frequency for a given workload If the power current or thermal limit is reached the processor will automatically reduce the frequency to stay within its TDP limit Turbo processor frequencies are only active if the operating system is requesting the PO state For more information on P states and C states see Power Management on page 44 Intel Advanced Vector Extensions 2 0 Intel AVX2 Intel Advanced Vector Extensions 2 0 Intel AVX2 is the latest expansion of the Intel instruction set Intel AVX2 extends the Intel Advanced Vector Extensions Intel AVX with 256 bit integer instructions floating point fused multiply add FMA instructions and gather operations The 256 bit integer vectors benefit math codec image and digital signal processing software FMA improves performance in face detection professional imaging and high performance computing Gather operations increase vectorization opportunities for many applications In addition to the vector extensions this generation of Intel processors adds new bit manipulation instructions useful in compression encryption and general purpose software For more information on Intel AVX see htt
143. hange SetMode method 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 Order No 330834 004v1 59 En e n tel Processor Thermal Management 5 1 Note Thermal Management The thermal solution provides both component level and system level thermal management To allow for the optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed so that the processor e Remains below the maximum junction temperature Tjmax specification at the maximum thermal design power TDP e Conforms to system constraints such as system acoustics system skin temperatures and exhaust temperature requirements Caution Thermal specifications given in this chapter are on the component and package level and apply specifically to the processor Operating the processor outside the specified limits may result in permanent damage to the processor and potentially other components in the system Thermal Considerations The processor TDP is the maximum sustained power that should be used for design of the processor thermal solution TDP is a power dissipation and junction temperature operating condition limit specified in this document that is validated during manufacturing for the base configuration when executing a n
144. he different SKUs 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 60 Order No 330834 004v1 e Thermal Management Processor n tel 5 2 5 3 5 3 1 Notes Intel Turbo Boost Technology 2 0 Power Monitoring When operating in turbo mode the processor monitors its own power and adjusts the turbo frequencies to maintain the average power within limits over a thermally significant time period The processor calculates the package power that consists of the processor core power and graphics core power In the event that a workload causes the power to exceed program power limits the processor will protect itself using the Adaptive Thermal Monitor Intel Turbo Boost Technology 2 0 Power Control Illustration of Intel Turbo Boost Technology 2 0 power control is shown in the following sections and figures Multiple controls operate simultaneously allowing for customization for multiple system thermal and power limitations These controls allow for turbo optimizations within system constraints and are accessible using MSR MMIO or PECI interfaces Package Power Control The package power control settings of PL1 PL2 and PL3 Tau allow the designer to configure Intel Turbo Boost Technology 2 0 to match the platform power delivery and package thermal solution limitations
145. hen e At least one core is in the C6 state e The other cores are in a C6 or deeper power state and the processor has been granted permission by the platform e The platform has not granted a package C7 state or deeper request however has allowed a package C6 state e Ifthe cores are requesting C7 state but the platform is limiting to a package C6 state the last level cache in this case can be flushed In package C6 state all cores have saved their architectural state and have had their core voltages reduced to zero volts It is possible the L3 shared cache is flushed and turned off in package C6 state If at least one core is requesting C6 state the L3 cache will not be flushed Package C7 State The processor enters the package C7 low power state when all cores are in the C7 state In package C7 the processor will take action to remove power from portions of the system agent The processor may enter a lower voltage package C7 state called Package C7 Plus operating at 1 3 V 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 52 Order No 330834 004v1 m Power Management Processor n tel 4 2 6 Note Core break events are handled the same way as in package C3 or C6 state Package C8 State The processor enters C8 states when the core with the highest state is C8
146. high interrupt scenarios like Gigabit LAN WLAN peripherals and so on Execute Disable Bit The Execute Disable Bit allows memory to be marked as executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system See the Inte 64 and IA 32 Architectures Software Developer s Manuals for more detailed information Intel Device Protection with Boot Guard Intel Device Protection with Boot Guard can help protect the platform boot integrity by preventing execution of unauthorized boot blocks With Intel Device Protection with Boot Guard platform manufacturers can create boot policies such that invocation of an unauthorized or untrusted boot block will trigger the platform protection per the manufacturer s defined policy With verification based in the hardware Intel Device Protection with Boot Guard extends the trust boundary of the platform boot process down to the hardware level Intel Device Protection with Boot Guard accomplishes this by e Providing hardware based Static Root of Trust for Measurement S RTM and the Root of Trust for Verification RTV using Intel architectural components e Providing architectural definition for platform manufacturer Boot Policy e
147. ications Parameter Description Min Max Notes The non operating device storage temperature Damage latent or otherwise may occur when subjected to this temperature for any length of time TABSOLUTE STORAGE 25 C 125 C 1 2 3 The ambient storage temperature limit in 5 9 o shipping media for a sustained period of time SUM 30d wa TSUSTAINED STORAGE The maximum device storage relative humidity for 0 o RHSUSTAINED STORAGE a sustained period of time 603010 224 6 nd TIME A prolonged or extended period of time typically 0 6 6 SUSTAINED STORAGE F associated with customer shelf life months months Notes 1 Refers to a component device that is not assembled in a board or socket that is not to be electrically connected to a voltage reference or I O signals 2 Specified temperatures are based on data collected Exceptions for surface mount reflow are specified by applicable JEDEC standards 3 TABSOLUTE srORAGE applies to the unassembled component only and does not apply to the shipping media moisture barrier bags or desiccant 4 Intel branded board products are certified to meet the following temperature and humidity limits that are given as an example only Non Operating Temperature Limit 40 C to 70 C Humidity 50 to 90 non condensing with a maximum wet bulb of 28 C Post board attach storage temperature limits are not specified for non Intel branded boards 5 The JEDEC J JSTD
148. intel Supported DDR3L DDR3L RS SO DIMM Module Configurations Per Channel Raw so SDRAM SDRAM of of of of Page Size Card DIMM Organizati Density SDRAM Ranks Row Col SDRAM Version Capacity on Devices Address Banks Bits A 2 GB 128 Mx 16 2 Gb 8 2 14 10 8 8 KB A 4 GB 256 Mx 16 4 Gb 8 2 15 10 8 8 KB B 2 GB 256 Mx8 2 Gb 8 1 15 10 8 8 KB B 4 GB 512 Mx8 4 Gb 8 1 16 10 8 8 KB C 1 GB 128 M x16 2 Gb 4 1 14 10 8 8 KB C 2 GB 256 M x16 4 Gb 4 1 15 10 8 8 KB F 4 GB 256 M x8 2 Gb 16 2 15 10 8 8 KB F 8 GB 512 Mx8 4 Gb 16 2 16 10 8 8 KB Supported DDR3L DDR3L RS Memory Down Configurations Per Channel Memory SDRAM SDRAM of of of of Page Size Capacity Organization Density SDRAM Ranks Row Col SDRAM Devices Address Banks Bits 1 GB 128 Mx 16 2 Gb 4 1 14 10 8 8 KB 2 GB 256 Mx 16 4 Gb 4 1 15 10 8 8 KB 256 Mx16 4 GB DDP 8 Gb 4 2 15 10 8 8 KB Note DDP Stacked Dual Die Package Supported LPDDR3 Memory Down Configurations Per Channel Memory DRAM DRAM DRAM of of of of Page Capacity Organiza Die Package DRAM Ranks Row Col DRAM Size tion Density Density Devices Address Banks Bits 2 GB SDP x 32 4 Gb 4 Gb 2 1 14 10 8 8 KB 4 GB DDP x 32 4 Gb 8 Gb 2 1 15 10 8 8 KB Note SDP Singl Die Package DDP Stacked Dual Die Package System Memory Timing Support e tCL CAS Latency e tRCD Activat
149. io Formats over HDMI and DisplayPort ssseseseessss 28 9 Multiple Display Configuration for 5th Generation Intel Core Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family 29 10 Multiple Display Configuration for Intel Core M Processor Family 30 11 DisplayPort and embedded DisplayPort Resolutions for 1 2 4 Lanes Link Data Rate of RBR HBR and HBR2 for U Processor Line sssssssssseeee nnnm 30 12 DisplayPort and embedded DisplayPort Resolutions for 1 2 4 Lanes Link Data Rate of RBR HBR and HBR2 for Intel Core M Processor Family 31 13 System States icio We edt ped usui cae ied nck ea ne eee ae Decet AE p eode 45 14 Processor Core Package State SUpport c sis i aa sna aaraa 45 15 Integrated Memory Controller States aaa aaraa 46 16 G S and C Interface State Combinations esses nnn 46 17 Coordination of Core Power States at the Package Level aaa 51 18 Package C States and Display Resolutions kk kk kk kak kaka aaa 54 19 Targeted Memory State Conditions aaa 57 20 Configurable TDP MOd Ss sc sadan nak sd ra na kk em tint am Rr a EX ca ka a dai aa CREER a k k ray kek raisa CHEER En R 63 21 Thermal Design Power TDP Specificat OS hk khkklkl kk kk kk nemen 65 22 Junction Temperature Spedificati0n ik kla kalik aaraa 65 23 ldl P Wer Sp GIfi Ca tO sis sav bi kane seve ka
150. ion NCTF locations are typically redundant ground or non critical NCTF reserved so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality ODT On Die Termination OLTM Open Loop Thermal Management PCG Platform Compatibility Guide PCG previously known as FMB provides a design target for meeting all planned processor freguency reguirements Platform Controller Hub The chipset with centralized platform capabilities including PCH the main I O interfaces along with display connectivity audio features power management manageability security and storage features The Platform Environment Control Interface PECI is a one wire interface that PECI provides a communication channel between Intel processor and chipset components to external monitoring devices PLi PL2 Power Limit 1 and Power Limit 2 PPD Pre charge Power down Processor The 64 bit multi core component package Processor Core The term processor core refers to Si die itself which can contain multiple execution cores Each execution core has an instruction cache data cache and 256 KB L2 cache All execution cores share the L3 cache Processor Graphics Intel Processor Graphics A unit of DRAM corresponding to four to eight devices in parallel ignoring ECC These nak devices are usually but not always mounted on a single side of a SO DIMM SCI System Control Interrupt SCI is us
151. ion mechanisms that allow the MLE to control attempts to modify itself The processor also offers additional enhancements to System Management Mode SMM architecture for enhanced security and performance The processor provides new MSRs to e Enable a second SMM range e Enable SMM code execution range checking e Select whether SMM Save State is to be written to legacy SMRAM or to MSRs e Determine if a thread is going to be delayed entering SMM e Determine if a thread is blocked from entering SMM e Targeted SMI enable disable threads from responding to SMIs both VLWs and IPI For the above features BIOS must test the associated capability bit before attempting to access any of the above registers For more information refer to the Intel Trusted Execution Technology Measured Launched Environment Programming Guide Intel Hyper Threading Technology Intel HT Technology The processor supports Intel Hyper Threading Technology Intel HT Technology that allows an execution core to function as two logical processors While some execution resources such as caches execution units and buses are shared each logical processor has its own architectural state with its own set of general purpose registers and control registers This feature must be enabled using the BIOS and requires operating system support Intel recommends enabling Intel HT Technology with Microsoft Windows 8 Windows 8 1 and Microsoft Windows 7 and disabling I
152. isplay 1 Display 2 Display 3 Maximum Maximum Maximum Notes Resolution Resolution Resolution Display 1 Display 2 Display 3 Additional MEME WI EMIL 3200x2000 100 mW Active Level Active Level eDP 4096x2304 24 Hz 60 Hz coolin Shifter Shifter ng required Additional 3200x2000 100 mw HDMI HDMI eDP 2560x1600 60 Hz 60 Hz cooling required Additional 3200x2000 100 mw DP DP eDP 3200x2000 60 Hz 60 Hz cooling required m Additional Pete E m 4096x2304 3200x2000 3200x2000 100 mw Q 24 Hz 60 Hz 60 Hz cooling Shifter k required Additional 2560x1600 3200x2000 3200x2000 100 mW ne DP SDE Q 60 Hz 60 Hz 60Hz cooling required Maximum HEMI wih 4096x2304 2560x1600 2560x1600 esolution for Active Level DP eDP Q 24 Hz 60 Hz 60 Hz clone or Shifter duplicate screen mode Maximum resolution for 2560x1600 2560x1600 2560x1600 HDMI DP eDP clone or 60 Hz 60 Hz 60 Hz duplicate screen mode Additional 2560x1600 3840x2160 100 mw DE eDP N A 60 Hz 60 Hz N A cooling required Note DP and eDP resolutions in this table are supported for 4 lanes with link data rate HBR2 at 24 bits per pixel bpp and single stream mode of operation The following table shows the DisplayPort embedded DisplayPort resolutions supported for 1 2 or 4 lanes depending on link data rate of RBR HBR HBR2 Table 11 DisplayPort and embedded DisplayPort Resolutions for 1 2 4 Lanes Link Data Rate of RBR HBR and HBR2 for U Pr
153. kage C state when a break event is detected Depending on the type of break event the processor does the following e Ifa core break event is received the target core is activated and the break event message is forwarded to the target core Ifthe break event is not masked the target core enters the core CO state and the processor enters package CO state If the break event is masked the processor attempts to re enter its previous package state e If the break event was due to a memory access or snoop request But the platform did not request to keep the processor in a higher package C state the package returns to its previous C state And the platform requests a higher power C state the memory access or snoop request is serviced and the package remains in the higher power C state The following table shows package C state resolution for a dual core processor The following figure summarizes package C state transitions 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 50 Order No 330834 004v1 Power Management Processor n te Table 17 Coordination of Core Power States at the Package Level Package C State Core 1 co C1 C3 C6 C7 cs co C10 co CO CO CO CO CO Co Co Co C1 Co C1 C1 C1 C1 C1 C1
154. l Monitor e THERMTRIP and PROCHOT support e On Demand Mode 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 12 Order No 330834 004v1 Introduction Processor n tel 1 4 1 5 1 6 Table 1 e Memory Open and Closed Loop Throttling e Memory Thermal Throttling e External Thermal Sensor TS on DIMM and TS on Board e Render Thermal Throttling e Fan speed control with DTS Package Support The 5th Generation Intel Core processor family based on U Processor Line Mobile Intel Pentium processor family and Mobile Intel Celeron processor family are available in the following package e 40mm x 24 mm x 1 284 mm BGA package BGA1168 The Intel Core M processor is available in the following package e 30mm x 16 5 mm x 1 05 mm BGA package BGA1234 Processor Testability The processor includes boundary scan for board and system level testability Terminology Terminology Term Description APD Active Power down B D F Bus Device Function BGA Ball Grid Array BLC Backlight Compensation BLT Block Level Transfer BMP Binary Modification Program BPP Bits per pixel CKE Clock Enable CLTM Closed Loop Thermal Management DDI Digital Display Interface DDR3 Third generation Double Data Rate SDRAM memor
155. lay Brightness The Intel Automatic Display Brightness feature dynamically adjusts the backlight brightness based upon the current ambient light environment This feature requires an additional sensor to be on the panel front The sensor receives the changing ambient light conditions and sends the interrupts to the Intel Graphics driver As per the change in Lux current ambient light illuminance the new backlight setting can be adjusted through BLC The converse applies for a brightly lit environment Intel Automatic Display Brightness increases the backlight setting Intel Seamless Display Refresh Rate Technology Intel SDRRS Technology When a Local Flat Panel LFP supports multiple refresh rates the Intel Display Refresh Rate Switching power conservation feature can be enabled The higher refresh rate will be used when plugged in with an AC power adaptor or when the end user has not selected enabled this feature The graphics software will automatically switch to a lower refresh rate for maximum battery life when the notebook is on battery power and when the user has selected enabled this feature There are two distinct implementations of Intel DRRS static and seamless The static Intel DRRS method uses a mode change to assign the new refresh rate The seamless Intel DRRS method is able to accomplish the refresh rate assignment without a mode change and therefore does not experience some of the visual artifacts associated with the mode c
156. ld be routed to a test point Arbitrary connection of these signals to VCC VDDQ VSS or to any other signal including each other may result in component malfunction or incompatibility with future processors See Signal Description on page 72 for a pin listing of the processor and the location of all reserved signals For reliable operation always connect unused inputs or bi directional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground VSS Unused outputs maybe left unconnected however this may interfere with some Test Access Port TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bi directional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Signal Groups Signals are grouped by buffer type and similar characteristics as listed in the following table The buffer type indicates which signaling technology and specifications apply to the signals All the differential signals and selected DDR3L DDR3L RS LPDDR3 and Control Sideband signals have On Die Termination ODT resistors Some signals do not have ODT and need to be terminated on the board All Control Sideband Asynchronous signals are required to be asserted de asserted for at least 10 BCLKs with maximum Trise Tfall of 6 ns in order for the processor to recognize the proper signal state
157. leep On Deep Sleep GO so C6 C7 Deep Power On Deep Power down down GO SO C8 C9 C10 On Deeper Powers down G1 S3 Power off Off except RTC Suspend to RAM G1 S4 Power off Off except RTC Suspend to Disk G2 S5 Power off Off except RTC Soft Off G3 NA Power off Power off Hard off Processor Core Power Management While executing code Enhanced Intel SpeedStep Technology optimizes the processor s frequency and core voltage based on workload Each frequency and voltage operating point is defined by ACPI as a P state When the processor is not executing code it is idle A low power idle state is defined by ACPI as a C state In general deeper power C states have longer entry and exit latencies Enhanced Intel SpeedStep Technology Key Features The following are the key features of Enhanced Intel SpeedStep Technology 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 46 March 2015 Order No 330834 004v1 Bi e Power Management Processor n tel e Multiple frequency and voltage points for optimal performance and power efficiency These operating points are known as P states e Frequency selection is software controlled by writing to processor MSRs The voltage is optimized based on the selected frequency and the number of active processor cores Once the voltage is e
158. ltage removal from all power domains C9 C8 VCC input to OV C10 C9 VR12 6 shut off or PS4 S3 cold Sleep Suspend To Ram STR S4 Hibernate Suspend To Disk STD Wakeup on PCH S5 Soft Off no power Wakeup on PCH Note Power states availability may vary between the different SKUs 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 44 Order No 330834 004v1 Power Management Processor n te Figure 9 4 1 Table 13 Table 14 Processor Package and Core C States CORE STATE gt One or more cores or GT executing instructions All cores and GT in C3 or deeper L3 may be flushed and turned off memory in self refresh some Uncore clocks stopped some Uncore voltages reduced All cores and GT in C6 or deeper L3 may be flushed and turned off memory in self refresh all Uncore clocks stopped some Uncore voltages reduced gt Package C6 L3 flushed and turned off additional Uncore voltages reduced Package C7 most Uncore voltages reduced to OV PACKAGE STATE gt Package C8 VR12 6 in low power state Package C9 VR12 6 turned off Ly Core behaves the same as Core C6 state All core clocks are stopped core state saved and voltage reduce to OV Cores flush L1 L2 into L3 all core
159. ly available using the Intel DPTF driver Through the DPTF driver LPM can be configured to use each of the following methods to reduce active power e Restricting Intel Turbo Boost Power limits and IA core Turbo Boost availability e Off Lining core activity Move processor traffic to a subset of cores e Placing an IA Core at LFM or LSF Lowest Supported Frequency e Utilizing IA clock modulation e Reducing number of active EUs to GT2 equivalent Applicable for GT3 SKUs Only e LPM power as listed in the TDP Specifications table is defined at a point which IA cores working at MFM GT RPn and 1 core active 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel Celeron9 Processor Family Datasheet Volume 1 of 2 Order No 330834 004v1 63 e n tel Processor Thermal Management Off lining core activity is the ability to dynamically scale a workload to a limited subset of cores in conjunction with a lower turbo power limit It is one of the main vectors available to reduce active power However not all processor activity is ensured to be able to shift to a subset of cores Shifting a workload to a limited subset of cores allows other cores to remain idle and save power Therefore when LPM is enabled less power is consumed at eguivalent freguencies Minimum Freguency Mode MFM of operation which is the lowest supported fregu
160. m Al mV 6 8 _ _ 20 _ _ 15 r 15 Ripple Rippe All mV 6 8 olerance _ _ 50 15 PS3 60 15 Loadline slope within the R DC LL VR regulation loop A 2 0 mQ capability Loadline slope in R_AC_LL response to dynamic load A 7 0 mQ increase events T_OVS_Max Maximum Overshoot time A 500 us V OVS Maximum Overshoot A 200 mV Notes 1 Unless otherwise noted all specifications in this table are based on estimates and simulations or empirical data These specifications will be updated with characterized data from silicon measurements at a later date 2 Each processor is programmed with a maximum valid voltage identification value VID that is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Adaptive Thermal Monitor Enhanced Intel SpeedStep Technology or Low Power States 3 The voltage specification requirements are measured across VCC SENSE and VSS SENSE lands at the socket with a 20 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe 4 Processor core
161. me Pull Up Pull Down Rail Value BPM 7 0 Pull Up Veco 40 60 Q PREQ Pull Up Veco 40 60 Q PROC_TDI Pull Up VccsTr 30 70 Q PROC_TMS Pull Up VCCs 30 70 Q CFG 19 0 Pull Up VCCs 5 8 ka CATERR Pull Up Vccsr 30 70 Q Note The oe Signals CFG should be be pulled to a stable logic value up to PLTRST de assertion 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 Order No 330834 004v1 79 En e n tel Processor Electrical Specifications 7 1 7 2 7 3 Electrical Specifications This chapter provides the processor electrical specifications including integrated voltage regulator VR Vcc Voltage Identification VID reserved and unused signals signal groups Test Access Points TAP and DC specifications Integrated Voltage Regulator A feature to the processor is the integration of platform voltage regulators into the processor Due to this integration the processor has one main voltage rail Vcc and a voltage rail for the memory interface Vppo compared to six voltage rails on previous processors The Vcc voltage rail will supply the integrated voltage regulators which in turn will regulate to the appropriate voltages for the cores cache system agent and graphics This integration allows the processor to better control on die voltages to optimiz
162. ment Control Interface PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Rup Internal pull up resistance 15 45 Vin Input Voltage Range 0 15 Vccsr 0 15 Vhysteresis Hysteresis 0 1 VCCsT N A continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 94 March 2015 Order No 330834 004v1 Electrical Specifications Processor 7 8 2 Figure 13 specifications 2 The leakage specification applies to powered devices on the PECI bus 3 The PECI buffer internal pull up resistance measured at 0 75 Vccgr Symbol Definition and Conditions Min Max Units Notes Negative Edge Threshold x _ Vn Voltage 0 275 VCCsT 0 525 VcCst V Positive Edge Threshold _ Vp Voltage 0 550 Vccst 0 725 Vccst V Chus Bus Capacitance per Node N A 10 pF Cpad Pad Capacitance 0 7 1 8 pF Ileak000 eakage current at 0 V 0 6 mA Ileak025 eakage current at 0 25 _ 0 4 mA 2 VCCsT Ileak050 eakage current at 0 50 0 2 mA _ VCCsT Ileak075 eakage current at 0 75 0 13 mA VCCsT Ileak100 eakage current at Vccsr 0 10 mA Notes 1 Vccgr supplies the PECI interface PECI behavior does not affect Vccgr minimum maximum Input Devic
163. mory interface The processor drives four CKE pins one per rank The CKE is one of the power save means When CKE is off the internal DDR clock is disabled and the DDR power is reduced The power saving differs according to the selected mode and the DDR type used For more information refer to the IDD table in the DDR specification The processor supports four different types of power down modes in package CO The different power down modes can be enabled through configuring PM PDWN config 0 0 0 MCHBAR The type of CKE power down can be configured through PDWN mode bits 15 12 and the idle timer can be configured through PDWN idle counter bits 11 0 The different power down modes supported are e No power down CKE disable e Active power down APD This mode is entered if there are open pages when de asserting CKE In this mode the open pages are retained Power saving in this mode is the lowest Power consumption of DDR is defined by IDD3P Exiting this mode is defined by tXP small number of cycles For this mode DRAM DLL must be on e PPD DLL off In this mode the data in DLLs on DDR are off Power saving in this mode is the best among all power modes Power consumption is defined by IDD2P1 Exiting this mode is defined by tXP but also tXPDLL 10 20 according to DDR type cycles until first data transfer is allowed For this mode DRAM DLL must be off e Pre charged power down PPD This mode is entered if all banks in D
164. n when used in conjunction Intel VT with Virtual Machine Monitor software enables multiple robust independent software environments inside a single platform Intel Virtualization Technology Intel VT for Directed I O Intel VT d is a hardware Intel VT d assist under system software Virtual Machine Manager or OS control for enabling I O device virtualization Intel VT d also brings robust security by providing protection from errant DMAs by using DMA remapping a key feature of Intel VT d IOV I O Virtualization ISI Inter Symbol Interference ITPM Integrated Trusted Platform Module Low Frequency Mode LFM is Pn in the P state table It can be read at MSR CEh LFM 47 40 LFP Local Flat Panel LPDDR3 Low Power Third generation Double Data Rate SDRAM memory technology MCP Multi Chip Package MFM Minimum Freguency Mode MFM is the minimum ratio supported by the processor and can be read from MSR CEh 55 48 MLE Measured Launched Environment continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 14 Order No 330834 004v1 Introduction Processor Term Description MLC Mid Level Cache MSI Message Signaled Interrupt MSL Moisture Sensitive Labeling MSR Model Specific Registers Non Critical to Funct
165. n rate is slower than the system PROCHOT response of lt 100 us The processor thermal control is staged in smaller increments over many milliseconds This may cause several milliseconds of delay to a system assertion of PROCHOT while the output function is asserted Voltage Regulator Protection using PROCHOT PROCHOT may be used for thermal protection of voltage regulators VR System designers can create a circuit to monitor the VR temperature and assert PROCHOT and if enabled activate the TCC when the temperature limit of the VR is reached When PROCHOT is configured as a bi directional or input only signal if the system assertion of PROCHOT is recognized by the processor it will result in an immediate transition to the lowest P State Pn supported by the processor and graphics cores Systems should still provide proper cooling for the VR and rely on bi directional 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 Order No 330834 004v1 69 n n tel Processor Thermal Management 5 6 3 3 5 6 3 4 5 6 3 5 5 6 3 6 5 6 4 PROCHOT only as a backup in case of system cooling failure Overall the system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TD
166. nal Name Description Direction Buffer Type Breakpoint and Performance Monitor Signals BPM 7 0 Outputs from the processor that indicate the status of I O breakpoints and programmable counters used for GTL monitoring processor performance Processor Ready This signal is a processor output o PRDY used by debug tools to determine processor debug readiness GTL Processor Request This signal is used by debug tools I PREQ to request debug operation of the processor GTL Test Clock This signal provides the clock input for the PROC TCK processor Test Bus also known as the Test Access I Port This signal must be driven low or allowed to float GTL during power on Reset continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Order No 330834 004v1 Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 75 Processor Signal Description Signal Name Description Direction Buffer Type Processor Test Data In This signal transfers serial I PROC TDI test data into the processor This signal provides the GTL serial input needed for JTAG specification support Processor Test Data Out This signal transfers serial O PROC_TDO test data out of the processor This signal provides the serial output needed for JTAG specification support Open Drain Processor Test Mode Select This is a JTAG I PROC
167. nals Reset and Miscellaneous Signals Signal Name Description Direction Buffer Type Configuration Signals The CFG signals have a default value of 1 if not terminated on the board e CFG 2 0 Reserved configuration lane A test point may be placed on the board for these lanes e CFG 3 MSR Privacy Bit Feature 1 Debug capability is determined by CFGI19 0 IA32_Debug_Interface_MSR C80h bit 0 setting Vo 13 0 0 IA32_Debug_Interface_MSR C80h bit 0 default GTL setting overridden e CFG 4 eDP enable 1 Disabled 0 Enabled e CFG 19 5 Reserved configuration lanes A test point may be placed on the board for these lands CFG RCOMP Configuration resistance compensation Use a 49 9 Q 1 us resistor to ground FC Future Compatibility signals are signals that are available for FC x compatibility with other processors A test point may be placed on the board for these lands Signal is for IFDIM testing only I IST_TRIGGER CMOS Signal is for debug If both THERMTRIP and this signal are IVR ERROR simultaneously asserted the processor has encountered an O unrecoverable power delivery fault and has engaged automatic CMOS shutdown as a result RSVD RESERVED All signals that are RSVD must be Ieft unconnected No Connect on the board Intel recommends that all RSVD TP signals have RSVD_TP via test points Test Point TESTLO x rien should be individually connected to Vss through a _
168. ntel 64 Architecture x2APIC The x2APIC architecture extends the xAPIC architecture that provides key mechanisms for interrupt delivery This extension is primarily intended to increase processor addressability Specifically x2APIC e Retains all key elements of compatibility to the xAPIC architecture Delivery modes Interrupt and processor priorities Interrupt sources Interrupt destination types 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 40 Order No 330834 004v1 Technologies Processor n tel Note Provides extensions to scale processor addressability for both the logical and physical destination modes Adds new features to enhance performance of interrupt delivery Reduces complexity of logical destination mode interrupt delivery on link based architectures The key enhancements provided by the x2APIC architecture over xAPIC are the following Support for two modes of operation to provide backward compatibility and extensibility for future platform innovations In xAPIC compatibility mode APIC registers are accessed through memory mapped interface to a 4K Byte page identical to the xAPIC architecture In x2APIC mode APIC registers are accessed through Model Specific Register MSR interfaces In this mode the x2
169. ntel HT Technology using the BIOS for all previous versions of Windows operating systems For more information on Intel HT Technology see http www intel com technology platform technology hyper threading 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 38 Order No 330834 004v1 m e Technologies Processor n tel 3 4 Note 3 5 3 6 Intel Turbo Boost Technology 2 0 The Intel Turbo Boost Technology 2 0 allows the processor core to opportunistically and automatically run faster than its rated operating frequency render clock if it is operating below power temperature and current limits The Intel Turbo Boost Technology 2 0 feature is designed to increase performance of both multi threaded and single threaded workloads Compared with previous generation products Intel Turbo Boost Technology 2 0 will increase the ratio of application power to TDP Thus thermal solutions and platform cooling that are designed to less than thermal design guidance might experience thermal and performance issues since more applications will tend to run at the maximum power limit for significant periods of time Intel Turbo Boost Technology 2 0 may not be available on all SKUs Intel Turbo Boost Technology 2 0 Frequency To determine the highest performance frequency amon
170. nterrupt EOI registers have been modified to allow for more efficient delivery and dispatching of interrupts The x2APIC extensions are made available to system software by enabling the local x2APIC unit in the x2APIC mode To benefit from x2APIC capabilities a new operating system and a new BIOS are both needed with special support for x2APIC mode The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendible for future Intel platform innovations Intel x2APIC Technology may not be available on all SKUs For more information see the Intel 64 Architecture x2APIC Specification at http www intel com products processor manuals 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 Order No 330834 004v1 41 m n tel Processor Technologies 3 8 3 9 3 10 Note 3 11 Power Aware Interrupt Routing PAIR The processor includes enhanced power performance technology that routes interrupts to threads or cores based on their sleep states As an example for energy savings it routes the interrupt to the active cores without waking the deep idle cores For performance it routes the interrupt to the idle C1 cores without interrupting the already heavily loaded cores This enhancement is mostly beneficial for
171. ntium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 20 Order No 330834 004v1 m Interfaces Processor n tel j 2 1 4 2 1 5 Note Out of Order Scheduling While leveraging the Just in Time Scheduling and Command Overlap enhancements the system memory controller continuously monitors pending requests to system memory for the best use of bandwidth and reduction of latency If there are multiple requests to the same open page these requests would be launched in a back to back manner to make optimum use of the open memory page This ability to reorder requests on the fly allows the system memory controller to further reduce latency and increase bandwidth efficiency System Memory Frequency In all modes the frequency of system memory is the lowest frequency of all memory placed in the system as determined through the SPD registers for the memory For systems using DDR3L DDR3L RS SO DIMM modules with different latency populated across the channels the BIOS will use the slower of the two latencies for both channels For dual channel mode both channels must have the SO DIMM connector populated For single channel mode only a single channel can have the SO DIMM connector be populated System Memory Organization Modes The system memory controller supports two memory organization modes single channel and dual channel Depending on how the DIMM Modules or DRAM Down
172. nvert the AC coupled signals to the HDMI compliant digital signals The processor HDMI interface is designed in accordance with the High Definition Multimedia Interface with 3D 4K Deep Color and x v Color 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 Order No 330834 004v1 27 intel Figure 5 HDMI Overview Processor Interfaces HDMI Sourc HDMI T Hot Plug Detect CEC Line optional HDMI Sink HDMI R embedded DisplayPort The embedded DisplayPort eDP is an embedded version of the DisplayPort standard oriented towards applications such as notebook and All In One PCs Like DisplayPort embedded DisplayPort also consists of a Main Link Auxiliary channel and an optional Hot Plug Detect signal Integrated Audio e HDMI and display port interfaces carry audio along with video e Processor supports two DMA controllers to output two High Definition audio streams on two digital ports simultaneously e Supports only the internal HDMI and DP CODECs Table 8 Processor Supported Audio Formats over HDMI and DisplayPort Audio Formats HDMI DisplayPort AC 3 Dolby Digital Yes Yes Dolby Digital Plus Yes Yes DTS HD Yes Yes LPCM 192 kHz 24 bit 8 Channel Yes Yes Dolby TrueHD DTS HD Master Audio
173. ocessor Line Link Data Rate Lane Count 1 2 4 RBR 1064x600 1400x1050 2240x1400 HBR 1280x960 1920x1200 2880x1800 HBR2 1920x1200 2880x1800 3840x2160 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 30 March 2015 Order No 330834 004v1 1 e Interfaces Processor n tel Table 12 2 5 2 5 1 DisplayPort and embedded DisplayPort Resolutions for 1 2 4 Lanes Link Data Rate of RBR HBR and HBR2 for Intel Core M Processor Family Link Data Rate Lane Count 1 2 4 RBR 1064x600 1400x1050 2240x1400 HBR 1280x960 1920x1200 2560x1600 HBR2 1920x1200 2880x1800 3200x2000 High bandwidth Digital Content Protection HDCP HDCP is the technology for protecting high definition content against unauthorized copy or unreceptive between a source computer digital set top boxes and so on and the sink panels monitor and TVs The processor supports HDCP 1 4 for content protection over wired displays HDMI and DisplayPort The HDCP 1 4 keys are integrated into the processor and customers are not required to physically configure or handle the keys Platform Environmental Control Interface PECI PECI is an Intel proprietary interface that provides a communication channel between Intel processors and external components
174. on Processor Family March 2015 Datasheet Volume 1 of 2 Order No 330834 004v1 25 n tel Processor Interfaces e The processor supports streaming any 3 independent and simultaneous display combination of DisplayPort HDMI eDP monitors In the case of 3 simultaneous displays two High Definition Audio streams over the digital display interfaces are supported e Each digital port is capable of driving resolutions up to 3840x2160 at 60 Hz using 4 lanes at link data rate HBR2 through DisplayPort and 4096x2304 at 24 Hz using HDMI Use of active level shifter is required to obtain maximum HDMI resolution e DisplayPort Aux CH DDC channel Panel power sequencing and HPD are supported through the PCH Figure 3 Processor Display Architecture Display Transcoder A Pipe A DP HDMI Timing VDIP Display i Transcoder B Pipe B DP HDMI Timing VDIP Transcoder eDP DP encoder Timing VDIP DPT SRID Panel Fitting Port Mux DDI Ports B and C Transcoder C DP HDMI Timing VDIP PCH Display Control Signals o o S o 2 2 c 9 O gt 2 e E o Display Pipe C eee Controller Display is the presentation stage of graphics This involves e Pulling rendered data from memory e Converting raw data into pixels e Blending surfaces into a frame e Organizing pixels into frames e Optionally scaling the image to the desired size e Re timing data for the intended ta
175. on and its architectural state is restored Core C7 C10 States Individual threads of a core can enter the C7 C8 C9 or C10 state by initiating a P LVL4 P LVL5 P LVL6 P LVL7 I O read respectively to the P BLK or by an MWAIT C7 C8 C9 C10 instruction The core C7 C10 state exhibits the same behavior as the core C6 state C State Auto Demotion In general deeper C states such as C6 or C7 state have long latencies and have higher energy entry exit costs The resulting performance and energy penalties become significant when the entry exit frequency of a deeper C state is high Therefore incorrect or inefficient usage of deeper C states have a negative impact on battery life and idle power To increase residency and improve battery life and idle power in deeper C states the processor supports C state auto demotion There are two C state auto demotion options e C7 C6 to C3 state e C7 C6 C3 To C1 state The decision to demote a core from C6 C7 to C3 or C3 C6 C7 to C1 state is based on each core s immediate residency history and interrupt rate If the interrupt rate experienced on a core is high and the residence in a deep C state between such interrupts is low the core can be demoted to a C3 or C1 state A higher interrupt pattern is required to demote a core to C1 state as compared to C3 state 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile
176. on to search for an Intel VT d translation table In doing so it uses the B D F number to traverse the data structure shown in the above figure If it finds a valid Intel VT d table in this data structure it uses that table to translate the address provided on the PCI Express bus If it does not find a valid translation table for a given translation this results in an Intel VT d fault If Intel VT d translation is required the Intel VT d engine performs an N level table walk For more information refer to Inte Virtualization Technology for Directed I O Architecture Specification http download intel com technology computing vptech Intel r VT for Direct IO pdf Intel VT d Features The processor supports the following Intel VT d features 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 36 Order No 330834 004v1 Technologies Processor n tel Note 3 2 e Memory controller and processor graphics comply with the Intel VT d 1 2 Specification e Two Intel VT d DMA remap engines iGFX DMA remap engine Default DMA remap engine covers all devices except iGFX e Support for root entry context entry and default context e 39 bit guest physical address and host physical address widths e Support for 4 KB 2 MB and 1 GB page sizes e Support for register
177. or Family Datasheet Volume 1 of 2 March 2015 48 Order No 330834 004v1 m e Power Management Processor n tel Core C1 C1E State C1 C1E is a low power state entered when all threads within a core execute a HLT or MWAIT C1 C1E instruction A System Management Interrupt SMI handler returns execution to either Normal state or the C1 C1E state See the Inte 64 and IA 32 Architectures Software Developer s Manual for more information While a core is in C1 C1E state it processes bus snoops and snoops from other threads For more information on C1E state see Package C States on page 50 Core C3 State Individual threads of a core can enter the C3 state by initiating a P LVL2 I O read to the P BLK or an MWAIT C3 instruction A core in C3 state flushes the contents of its L1 instruction cache L1 data cache and L2 cache to the shared L3 cache while maintaining its architectural state All core clocks are stopped at this point Because the core s caches are flushed the processor does not wake any core that is in the C3 state when either a snoop is detected or when another core accesses cacheable memory Core C6 State Individual threads of a core can enter the C6 state by initiating a P LVL3 I O read or an MWAIT C6 instruction Before entering core C6 state the core will save its architectural state to a dedicated SRAM Once complete a core will have its voltage reduced to zero volts During exit the core is powered
178. p www intel com software avx Intel Advanced Encryption Standard New Instructions Intel AES NI The processor supports Intel Advanced Encryption Standard New Instructions Intel AES NI that are a set of Single Instruction Multiple Data SIMD instructions that enable fast and secure data encryption and decryption based on the Advanced Encryption Standard AES Intel AES NI are valuable for a wide range of 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 Order No 330834 004v1 39 n n tel Processor Technologies 3 7 cryptographic applications such as applications that perform bulk encryption decryption authentication random number generation and authenticated encryption AES is broadly accepted as the standard for both government and industry applications and is widely deployed in various protocols Intel AES NI consists of six Intel SSE instructions Four instructions AESENC AESENCLAST AESDEC and AESDELAST facilitate high performance AES encryption and decryption The other two AESIMC and AESKEYGENASSIST support the AES key expansion procedure Together these instructions provide a full hardware for supporting AES offering security high performance and a great deal of flexibility PCLMULQDQ Instruction The processor supports the carry less mul
179. perating systems For more information refer to the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A Intel Transactional Synchronization Extensions New Instructions Intel TSX NI The processor supports Intel Transactional Synchronization Extensions New Instructions Intel TSX NI Intel TSX NI provides a set of instruction extensions that allow programmers to specify regions of code for transactional synchronization Programmers can use these extensions to achieve the performance of fine grain locking while actually programming using coarse grain locks Details on Intel TSX NI are in the Inte Architecture Instruction Set Extensions Programming Reference 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 Order No 330834 004v1 43 n te Processor Power Management 4 0 Power Management This chapter provides information on the following power management topics e Advanced Configuration and Power Interface ACPI States e Processor Core e Integrated Memory Controller IMC e Processor Graphics Controller Figure 8 Processor Power States C1 Auto halt C1E Auto halt low freq low voltage C3 L1 L2 caches flush clocks off C6 save core states before shutdown and PLL off C7 C6 L3 cache flush C8 C7 internal vo
180. pt Request High Definition Multimedia Interface HDMI The High Definition Multimedia Interface HDMI is provided for transmitting uncompressed digital audio and video signals from DVD players set top boxes and other audiovisual sources to television sets projectors and other video displays It can carry high quality multi channel audio data and all standard and high definition consumer electronics video formats The HDMI display interface connecting the processor and display devices uses transition minimized differential signaling TMDS to carry audiovisual information through the same HDMI cable HDMI includes three separate communications channels TMDS DDC and the optional CEC consumer electronics control CEC is not supported on the processor As shown in the following figure the HDMI cable carries four differential pairs that make up the TMDS data and clock channels These channels are used to carry video audio and auxiliary data In addition HDMI carries a VESA DDC The DDC is used by an HDMI Source to determine the capabilities and characteristics of the Sink Audio video and auxiliary control status data is transmitted across the three TMDS data channels The video pixel clock is transmitted on the TMDS clock channel and is used by the receiver for data recovery on the three data channels The digital display data signals driven natively through the PCH are AC coupled and needs level shifting to co
181. r PC manufacturer For more information visit http www intel com go virtualization The original equipment manufacturer must provide TPM functionality which requires a TPM supported BIOS TPM functionality must be initialized and may not be available in all countries For Enhanced Intel SpeedStep Technology see the Processor Spec Finder at http ark intel com or contact your Intel representative for more information ntel AES NI requires a computer system with an AES NI enabled processor as well as non Intel software to execute the instructions in the correct sequence AES NI is available on select Intel processors For availability consult your reseller or system manufacturer For more information see http software intel com en us articles intel advanced encryption standard instructions aes ni ntel Active Management Technology Intel AMT should be used by a knowledgeable IT administrator and requires enabled systems software activation and connection to a corporate network Intel AMT functionality on mobile systems may be limited in some situations Your results will depend on your specific implementation Learn more by visiting Intel Active Management Technology No computer system can provide absolute security under all conditions Intel Trusted Execution Technology Intel TXT requires a computer with ntel Virtualization Technology an Intel TXT enabled processor chipset BIOS Authenticated Code Modules and an Intel TXT
182. raa an ka Da k kana 97 9 0 Processor Ball and Signal Inform at O k kK k kllldllkdllklkkclkkkkkkkkkkkkkkkkk kaka kak anak kaka aka kuna nuk una nu ua ku aa 98 9 1 Intel Core M Processor Family Ball Information BGA1234 aaa 98 9 2 U Processor Ball Information BGA1168 K1 aaraa 111 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron9 Processor Family March 2015 Datasheet Volume 1 of 2 Order No 330834 004v1 5 a n tel Processor Figures Figures 1 Processor Platform Block Dia lalll 345 ci xuyani calan na xana nan nha na k e k y s a W H Zad 11 2 Intel Flex Memory Technology OperationS k ll lk kk kk kkk emnes 22 3 Processor Display Architecture 4 is sk kaka l lladl kal a akla kall kal ka lk aa kk kal d k senem a al a a adara a 26 4 DisplayPort OVefVieWi saatsin eest m taj s n n b n Di W saa bind bank Wla dak n K ted Aba ya na k bank ek b ban 27 5 HDMI OVErview s ni dian nand an sials DERG aa bA DUM A k adan ai aja b d k 28 6 PECI Host Clients Connection Exam pl s ga as az sxk aska da naa aa kala ak ne nnn nan nna kara ej ah n nua 32 7 Device to Domain Mapping StrU ct 68 xx xi kk aaa kay nnn nnn 36 8 Brocessor Power States n euius adu dainas as s DEV DAN bul kak dat 44 9 Processor Package and Cor
183. rameter e AC tolerances for all DC rails include dynamic load currents at switching frequencies up to 1 MHz 7 8 Voltage and Current Specifications Table 40 Processor Core Active and Idle Mode DC Voltage and Current Specifications Symbol Parameter Segment Min Typ Max Unit Note Voltage Range for VU die Processor Active All 1 57 z 1 85 V 1 2 3 7 omage Operating Mode Voltage Range for Processor Idle Mode All 1 56 Package C6 Idle Voltage V 1 2 3 7 Voltage Range for Processor Idle Mode All 1 56 Package C7 continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 Order No 330834 004v1 87 n tel Processor Electrical Specifications Symbol Parameter Segment Min Typ Max Unit Note Voltage Range for Processor Idle Mode All 1 3 Package C7 Plus Voltage Range for Processor Idle Mode All 1 3 Package C8 Voltage Range for Processor Idle Mode All 0 Package C9 C10 Intel Core U Processor Line 40 28W Intel Core U Processor Line 32 15W ies pen Processor Core A 4 6 7 ee Intel Pentium P rocessor _ _ 32 Intel Celeron Processor Intel Core M _ _ 18 Processor Family 20 TOLvcc a
184. rations permitting software to set up instruction buffers and use batch processing The BLT engine can perform hardware clipping during BLTs 2 4 Digital Display Interface DDI e The processor supports Two Digital Display x4 DDI interfaces that can be configured as DisplayPort HDMI The DisplayPort can be configured to use 1 2 or 4 lanes depending on the bandwidth requirements and link data rate of RBR 1 62 GT s HBR 2 97 GT s and HBR2 5 4 GT s When configured as HDMI the DDIx4 port can support 2 97 GT s One dedicated x4 embedded DisplayPort eDP Built in displays are only supported on eDP e The HDMI interface supports HDMI with 3D 4K Deep Color and x v Color The DisplayPort interface supports the VESA DisplayPort Standard Version 1 Revision 2 e The processor supports High bandwidth Digital Content Protection HDCP for high definition content playback over digital interfaces e The processor also integrates dedicated a Mini HD audio controller to drive audio on integrated digital display interfaces such as HDMI and DisplayPort The HD audio controller on the PCH would continue to support down CODECs and so on The processor Mini HD audio controller supports two High Definition Audio streams simultaneously on any of the three digital ports 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celer
185. rcuit TCC causes both the processor core and graphics core to reduce frequency and voltage adaptively The Adaptive Thermal Monitor will remain active as long as the package temperature exceeds its specified limit Therefore the Adaptive Thermal Monitor will continue to reduce the package frequency and voltage until the TCC is de activated Tjmax is factory calibrated and is not user configurable The default value is software visible in the TEMPERATURE TARGET 0x1A2 MSR bits 23 16 The TEMPERATURE TARGET value stays the same when TCC Activation offset is enabled The Adaptive Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines It is not intended as a mechanism to maintain processor TDP The system design should provide a thermal solution that can maintain TDP within its intended usage range Adaptive Thermal Monitor protection is always enabled 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 66 Order No 330834 004v1 E e Thermal Management Processor n tel 5 6 1 1 5 6 1 2 5 6 1 3 Thermal Control Circuit TCC Activation Offset TCC Activation Offset can be used to activate the Adaptive Thermal Monitor at temperatures lower than Tjmax It is the preferred thermal protection mechanism for Intel Turbo Boost Te
186. res e Extended Page Table EPT Accessed and Dirty Bits EPT A D bits enabled VMMs to efficiently implement memory management and page classification algorithms to optimize VM memory operations such as de fragmentation paging live migration and check pointing Without hardware support for EPT A D bits VMMs may need to emulate A D bits by marking EPT paging structures as not present or read only and incur the overhead of EPT page fault VM exits and associated software processing e Extended Page Table Pointer EPTP switching EPTP switching is a specific VM function EPTP switching allows guest software in VMX non root operation supported by EPT to request a different EPT paging structure hierarchy This is a feature by which software in VMX non root operation can request a change of EPTP without a VM exit Software can choose among a set of potential EPTP values determined in advance by software in VMX root operation e Pause loop exiting Support VMM schedulers seeking to determine when a virtual processor of a multiprocessor virtual machine is not performing useful work This situation may occur when not all virtual processors of the virtual machine are currently scheduled and when the virtual processor in question is in a loop involving the PAUSE instruction The new feature allows detection of such loops and is thus called PAUSE loop exiting The processor core supports the following Intel VT x features e Extended
187. rget e Formatting data according to the port output standard DisplayPort DisplayPort is a digital communication interface that uses differential signaling to achieve a high bandwidth bus interface designed to support connections between PCs and monitors projectors and TV displays 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 26 Order No 330834 004v1 m e Interfaces Processor n te j Figure 4 A DisplayPort consists of a Main Link Auxiliary channel and a Hot Plug Detect signal The Main Link is a unidirectional high bandwidth and low latency channel used for transport of isochronous data streams such as uncompressed video and audio The Auxiliary Channel AUX CH is a half duplex bidirectional channel used for link management and device control The Hot Plug Detect HPD signal serves as an interrupt request for the sink device The processor is designed in accordance with the VESA DisplayPort Standard Version 1 2a The processor supports VESA DisplayPort PHY Compliance Test Specification 1 2a and VESA DisplayPort Link Layer Compliance Test Specification 1 2a DisplayPort Overview Source Device Main Link Sink Device i Isochronous Streams j DisplayP DisplayP AUX CH Link Device Managemet Hot Plug Detect Interru
188. ry to place the graphics engine in the most energy efficient P state Intel Display Power Saving Technology Intel DPST The Intel DPST technique achieves backlight power savings while maintaining a good visual experience This is accomplished by adaptively enhancing the displayed image while decreasing the backlight brightness simultaneously The goal of this technique is to provide equivalent end user perceived image quality at a decreased backlight power level 1 The original input image produced by the operating system or application is analyzed by the Intel DPST subsystem An interrupt to Intel DPST software is generated whenever a meaningful change in the image attributes is detected A meaningful change is when the Intel DPST software algorithm determines that enough brightness contrast or color change has occurred to the displaying images that the image enhancement and backlight control needs to be altered 2 Intel DPST subsystem applies an image specific enhancement to increase image contrast brightness and other attributes 3 A corresponding decrease to the backlight brightness is applied simultaneously to produce an image with similar user perceived quality such as brightness as the original image Intel DPST 6 0 has improved the software algorithms and has minor hardware changes to better handle backlight phase in and ensures the documented and validated method to interrupt hardware phase in Intel Automatic Disp
189. secure Intel Hyper Threading Technology Intel HT Technology is available on select Intel Core processors It requires an Intel HT Technology enabled system Consult your PC manufacturer Performance will vary depending on the specific hardware and software used Not available on Intel Core i5 750 For more information including details on which processors support Intel HT Technology visit http www intel com info hyperthreading Intel High Definition Audio Intel HD Audio requires an Intel HD Audio enabled system Consult your PC manufacturer for more information Sound quality will depend on equipment and actual implementation For more information about Intel HD Audio refer to http www intel com design chipsets hdaudio htm Intel 64 architecture requires a system with a 64 bit enabled processor chipset BIOS and software Performance will vary depending on the specific hardware and software you use Consult your PC manufacturer for more information For more information visit http www intel com content www us en architecture and technology microarchitecture intel 64 architecture general html Intel Virtualization Technology Intel VT requires a computer system with an enabled Intel processor BIOS and virtual machine monitor VMM Functionality performance or other benefits will vary depending on hardware and software configurations Software applications may not be compatible with all operating systems Consult you
190. sition e On a downward transition the frequency transition precedes the voltage transition e The processor continues to execute instructions However the processor will halt instruction execution for frequency transitions If a processor load based Enhanced Intel SpeedStep Technology P state transition through MSR write is initiated while the Adaptive Thermal Monitor is active there are two possible outcomes e Ifthe P state target frequency is higher than the processor core optimized target frequency the P state transition will be deferred until the thermal event has been completed e If the P state target frequency is lower than the processor core optimized target frequency the processor will transition to the P state operating point Clock Modulation If the frequency voltage changes are unable to end an Adaptive Thermal Monitor event the Adaptive Thermal Monitor will utilize clock modulation Clock modulation is done by alternately turning the clocks off and on at a duty cycle ratio between clock on time and total time specific to the processor The duty cycle is factory configured to 25 on and 75 off and cannot be modified The period of the duty cycle is configured to 32 microseconds when the Adaptive Thermal Monitor is active Cycle 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel Celeron Processor Family Da
191. sor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 70 Order No 330834 004v1 a Thermal Management Processor n tel Mode may be used in conjunction with the Adaptive Thermal Monitor However if the system software tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode If the I O based and MSR based On Demand modes are in conflict the duty cycle selected by the I O emulation based On Demand mode will take precedence over the MSR based On Demand Mode 5 6 4 1 MSR Based On Demand Mode If Bit 4 of the IA32 CLOCK MODULATION MSR is set to a 1 the processor will immediately reduce its power consumption using modulation of the internal core clock independent of the processor temperature The duty cycle of the clock modulation is programmable using bits 3 1 of the same IA32 CLOCK MODULATION MSR In this mode the duty cycle can be programmed in either 12 5 or 6 25 increments discoverable using CPUID Thermal throttling using this method will modulate each processor core s clock independently 5 6 4 2 I O Emulation Based On Demand Mode I O emulation based clock modulation provides legacy support for operating system software that initiates clock modulation through I O writes to ACPI defined processor clock control registers on th
192. ssing point of DQS and DQS during read and write SB_DQS 7 0 transactions SA_DQ 63 0 Data Bus Read and Write Input Output data signals yo SB_DQ 63 0 SA_CS 1 0 Chip Select These signals are used to select components SB CS 1 0 during the active state There is one Chip Select for each O DRAM rank SA_CKE 1 0 Clock Enable These signals are used to initialize and power o SB_CKE 1 0 state components There is one CKE for each DRAM rank SA_ODT 0 SB_ODT 0 On Die Termination Active Termination Control O SM DRAMRRST DRAM RESET System Memory DRAM Device Reset VREF DQ A VREF DQ B Data Reference Voltage Data Signal Reference Voltage VREF CA Command Address Reference Voltage Command and o Address Signal Reference Voltage LPDDR3 Memory Down Channel A and B Memory Signals Signal Name Description Direction Buffer Type SA CK 1 0 SA CK 1 0 Clocks CK and its complement CK signal make up a differential clock pair The crossing of the positive edge of CK SB CK 1 0 SB CK 1 0 and the negative edge of its complement CK are used to sample the command and control signals SA_CAA 9 0 Command Address These signals are used to provide the SA_CAB 9 0 multiplexed command and address o SB_CAA 9 0 SB_CAB 9 0 SA_DQS 7 0 Data Strobes DQS and its complement DQS signal make SA_DQS 7 0 up a differential strobe pair The data is captured at the yo SB_DQS 7 0 crossing point o
193. ssor that I VR_READY the external voltage regulator for the Vcc power rail is valid CMOS 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 330834 004v1 77 intel 6 10 Table 35 6 11 Table 36 Processor Signal Description Sense Signals Sense Signals voltage near the silicon Signal Name Description Direction Buffer Type VCC SENSE and VSS SENSE provide an isolated low VCC SENSE impedance connection to the processor input Vcc voltage O VSS_SENSE and ground The signals can be used to sense or measure A Ground and Non Critical to Function NCTF Signals Ground and Non Critical to Function NCTF Signals Signal Name Description Direction Buffer Type VSS DAISY_CHAIN_NCTF Ball BGA 1168 package Processor ground node Daisy Chain Non Critical to Function These signals are for BGA solder joint reliability testing and are non critical to function These signals are connected on the processor package as follows Package A1 Corner e DAISY CHAIN NCTF B2 to DAISY CHAIN NCTF C1 e DAISY CHAIN NCTF C2 to DAISY CHAIN NCTF B3 e DAISY CHAIN NCTF A3 to DAISY CHAIN NCTF A4 Package A63 Corner e DAISY CHAIN NCTF A62 to DAISY CHAIN NCTF A61 e DAISY CHAIN NCTF B61 to DAISY CHAIN
194. stablished the PLL locks on to the target frequency All active processor cores share the same frequency and voltage In a multi core processor the highest frequency P state requested among all active cores is selected Software reguested transitions are accepted at any time If a previous transition is in progress the new transition is deferred until the previous transition is completed e The processor controls voltage ramp rates internally to ensure glitch free transitions e Because there is low transition latency between P states a significant number of transitions per second are possible 4 2 2 Low Power Idle States When the processor is idle low power idle states C states are used to save power More power savings actions are taken for numerically higher C states However higher C states have longer exit and entry latencies Resolution of C states occur at the thread processor core and processor package level Thread level C states are available if Intel Hyper Threading Technology is enabled Caution Long term reliability cannot be assured unless all the Low Power Idle States are enabled Figure 10 Idle Power Management Breakdown of the Processor Cores Core 0 State Core N State Processor Package State 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family March 20
195. t comply to the TTV thermal profile Thermal Design Power Thermal solution should be designed to dissipate this target TDP i ST power level TDP is not the maximum power that the processor can dissipate TLB Translation Look aside Buffer TTV Thermal Test Vehicle A mechanically eguivalent package that contains a resistive heater in the die to evaluate thermal solutions TM Thermal Monitor A power reduction feature designed to decrease temperature after the processor has reached its maximum operating temperature Vcc Processor core power supply VDDQ DDR3L and LPDDR3 power supply VF Vertex Fetch VID Voltage Identification VS Vertex Shader VLD Variable Length Decoding VMM Virtual Machine Monitor VR Voltage Regulator Vss Processor ground 1 7 Related Documents Table 2 Related Documents Document Document Number Location The 5th Generation Intel Core Processor Family Intel Core M Processor Family 330835 Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 2 of 2 The 5th Generation Intel Core Processor Family Intel Core M Processor Family 330836 Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Specification Update The 5th Generation Intel Core Processor Family I O Intel Core M Processor 330837 Family I O Mobile Intel Pentium Processor Family I O and Mobile Intel Celeron Processor Family I O
196. tables in accordance with the device assignment restrictions above and to include a multi level translation table VT d Table that contains Guest specific address translations 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 330834 004v1 35 m n tel Processor Technologies Figure 7 Device to Domain Mapping Structures Dev 31 Func 7 Context entry 255 Dev 0 Func 1 Dev 0 Func 0 Context entry 0 gt Context entry Table For bus N Address Translation Bus 255 Root entry 255 Structures for Domain A Bus N Root entry N Bus 0 Root entry O Root entry table Context entry 255 Context entry 0 Address Translation Context entry Table Structures for Domain B For bus 0 Intel VT d functionality often referred to as an Intel VT d Engine has typically been implemented at or near a PCI Express host bridge component of a computer system This might be in a chipset component or in the PCI Express functionality of a processor with integrated I O When one such Intel VT d engine receives a PCI Express transaction from a PCI Express bus it uses the B D F number associated with the transacti
197. tasheet Volume 1 of 2 Order No 330834 004v1 67 En e n tel Processor Thermal Management 5 6 2 times are independent of processor freguency A small amount of hysteresis has been included to prevent excessive clock modulation when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the Adaptive Thermal Monitor goes inactive and clock modulation ceases Clock modulation is automatically engaged as part of the Adaptive Thermal Monitor activation when the freguency voltage targets are at their minimum settings Processor performance will be decreased by the same amount as the duty cycle when clock modulation is active Snooping and interrupt processing are performed in the normal manner while the Adaptive Thermal Monitor is active Digital Thermal Sensor Each processor execution core has an on die Digital Thermal Sensor DTS that detects the core s instantaneous temperature The DTS is the preferred method of monitoring processor die temperature because e Itis located near the hottest portions of the die e It can accurately track the die temperature and ensure that the Adaptive Thermal Monitor is not excessively activated Temperature values from the DTS can be retrieved through e A software interface using processor Model Specific Register MSR e A processor hardware interface as described in Pl
198. the characterization at higher temperatures and extrapolating the values for the junction temperature indicated Thermal Management Features Occasionally the processor may operate in conditions that are near to its maximum operating temperature This can be due to internal overheating or overheating within the platform To protect the processor and the platform from thermal failure several thermal management features exist to reduce package power consumption and thereby temperature in order to remain within normal operating limits Furthermore the processor supports several methods to reduce memory power Adaptive Thermal Monitor The purpose of the Adaptive Thermal Monitor is to reduce processor core power consumption and temperature until it operates at or below its maximum operating temperature Processor core power reduction is achieved by e Adjusting the operating frequency using the core ratio multiplier and voltage e Modulating starting and stopping the internal processor core clocks duty cycle The Adaptive Thermal Monitor can be activated when the package temperature monitored by any digital thermal sensor DTS meets or exceeds its maximum operating temperature The maximum operating temperature implies either maximum junction temperature Tjyax Or Tjmax minus TCC Activation offset Exceeding the maximum operating temperature activates the thermal control circuit TCC if enabled When activated the thermal control ci
199. those wishing to rely on the platform can make an appropriate trust decision The Intel TXT platform determines the identity of the controlling environment by accurately measuring and verifying the controlling software Another aspect of the trust decision is the ability of the platform to resist attempts to change the controlling environment The Intel TXT platform will resist attempts by software processes to change the controlling environment or bypass the bounds set by the controlling environment 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 Order No 330834 004v1 37 n n tel Processor Technologies 3 3 Intel TXT is a set of extensions designed to provide a measured and controlled launch of system software that will then establish a protected environment for itself and any additional software that it may execute These extensions enhance two areas e The launching of the Measured Launched Environment MLE e The protection of the MLE from potential corruption The enhanced platform provides these launch and control interfaces using Safer Mode Extensions SMX The SMX interface includes the following functions e Measured Verified launch of the MLE e Mechanisms to ensure the above measurement is protected and stored in a secure location e Protect
200. through like a normal I O instruction When P LVLx I O instructions are used MWAIT sub states cannot be defined The MWAIT sub state is always zero if I O MWAIT redirection is used By default P LVLx I O redirections enable the MWAIT break on EFLAGS IF feature that triggers a wakeup on an interrupt even if interrupts are masked by EFLAGS IF Core C State Rules The following are general rules for all core C states unless specified otherwise e A core C state is determined by the lowest numerical thread state such as Thread 0 requests C1E state while Thread 1 requests C3 state resulting in a core C1E state See the G S and C Interface State Combinations table e A core transitions to CO state when An interrupt occurs There is an access to the monitored address if the state was entered using an MWAIT Timed MWAIT instruction The deadline corresponding to the Timed MWAIT instruction expires e An interrupt directed toward a single thread wakes only that thread e If any thread in a core is in active in CO state the core s C state will resolve to CO state e Any interrupt coming into the processor package may wake any core e A system reset re initializes all processor cores Core CO State The normal operating state of a core where code is being executed 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Process
201. tiplication instruction PCLMULQDQ PCLMULQDQ is a Single Instruction Multiple Data SIMD instruction that computes the 128 bit carry less multiplication of two 64 bit operands without generating and propagating carries Carry less multiplication is an essential processing component of several cryptographic systems and standards Hence accelerating carry less multiplication can significantly contribute to achieving high speed secure computing and communication Intel Secure Key The processor supports Intel Secure Key formerly known as Digital Random Number Generator DRNG a software visible random number generation mechanism supported by a high quality entropy source This capability is available to programmers through the RDRAND instruction The resultant random number generation capability is designed to comply with existing industry standards in this regard ANSI X9 82 and NIST SP 800 90 Some possible usages of the RDRAND instruction include cryptographic key generation as used in a variety of applications including communication digital signatures secure storage and so on The processor has a RDSEED instruction that enables system software and security vendors who need to seed or reseed a software PRNG The RDSEED instruction will be a companion to the RDRAND instruction RDSEED along with RDRAND fills out Intel s standards compliant such as NIST SP800 90 A B and C Hardware based Random Number Generator portfolio I
202. tium Processor Family and Mobile Intel Celeron9 Processor Family March 2015 Datasheet Volume 1 of 2 Order No 330834 004v1 3 m n tel Processor Contents 4 2 5 Package C States sis indeed ecc ken Wa cd n VA kadas gals 50 4 2 6 Package C States and Display Resolutions kk kk eee kk kk ka 53 4 3 Integrated Memory Controller IMC Power Management aaa 54 4 3 1 Disabling Unused System Memory Outputs a aaraa 55 4 3 2 DRAM Power Management and Initialization a aaa 55 4 3 3 DDR Electrical Power Gating EPG eceeeceee eect eee sees teeta eee ee eee kk kak kak kak 57 4 4 Graphics Power Management 2 nein ects aea aeta ra dada XA RA RD kala kak eki kak b kk a a 58 4 4 1 Intel Rapid Memory Power Management Intel RMPM kEE kez 58 4 4 2 Graphics Render C S tak sa xa sas kck kula lk k na a kk evan a pkk kaya a kk kawa lk a ala kk retas a a te s 58 4 4 3 Intel Smart 2D Display Technology Intel S2DDT EE 58 4 4 4 Intel Graphics Dynamic FrequenCy LLlk lhk k lk k lll nennen nnne nnn nns 58 4 4 5 Intel Display Power Saving Technology Intel DPST eccsseceesaeeceeeeeeaes 59 4 4 6 Intel Automatic Display Brightness cceeseseeee memes 59 4 4 7 Intel Seamless Display Refresh Rate Technology Intel SDRRS Esel ELM 59 5 0 Thermal Management aa aaa aa ananass are akan kak kaka nana kann kun ua una u uan u uan asas asas nanna nu asa as
203. ture Tjmax Only a single PROCHOT Z pin exists at a package level When any core arrives at the TCC activation point the PROCHOT signal will be asserted PROCHOT assertion policies are independent of Adaptive Thermal Monitor enabling Bi Directional PROCHOT By default the PROCHOT signal is set to bi directional However it is recommended to configure the signal as an input only When configured as an input or bi directional signal PROCHOT can be used for thermally protecting other platform components in case the components overheat as well When PROCHOT is driven by an external device e The package will immediately transition to the lowest P State Pn supported by the processor and graphics cores This is contrary to the internally generated Adaptive Thermal Monitor response e Clock modulation is not activated The processor package will remain at the lowest supported P state until the system de asserts PROCHOT The processor can be configured to generate an interrupt upon assertion and de assertion of the PROCHOT signal When PROCHOT is configured as a bi directional signal and PROCHOT is asserted by the processor it is impossible for the processor to detect a system assertion of PROCHOT The system assertion will have to wait until the processor de asserts PROCHOT before PROCHOT action can occur due to the system assertion While the processor is hot and asserting PROCHOT the power is reduced however the reductio
204. u uan nanna uu usua sana 72 6 1 System Memory Interface Signals 1 aaa lak kak a kaka 72 6 2 Memory Compensation and Miscellaneous S gna S LL hk llkkll kk kk 74 6 3 Reset and Miscellaneous Signals kk kk eee kk kk kk kk kk kaka emnes 74 6 4 embedded DisplayPort eDP Signals csssssssssssse nmn meme nene 75 6 5 Display Interface Signals eese d kal aa taj ners s kx ke Forte IRE Ra SR Ra wa nad a aa a aca aja i a e ah 75 6 6 Testability Signals xri niana dain s CURRERE da Kaa VERI canada M REBATE ER 75 6 7 Error and Thermal Protection Signals sss eene 76 6 8 Power Sequencing Signals eei nedan k rka a n ak ada n Dakak haa wan bh na LA da waa dik w wla aa 77 6 9 Processor Power Signals ku lae sest dken ka d saa nakin ninin ina mea da Kab mee aa ERE n k s A ERE 77 6 10 Sense Sign ls sanesu recette n teh ete s n dab n ka cadena kaka a Saka daa Da a gets n ks g ja 78 6 11 Ground and Non Critical to Function NCTF S gna S L LhK h llll kk kk kk 78 6 12 Processor Internal Pull Up Pull Down Terminations esee 79 7 0 Electrical Specifications a aaa ananass nas kk aka kaka kk ka asas nasus n uan uan u uan nau se sana usua aaa 80 7 1 Integrated Voltage Re gQUl Os ss d s k sa ka nas arda k lan kan doves a ea a kaya D a ay zir a had 80 7 2 Power and Ground Pins sus aka kl dala takas n
205. uts from the SF stage to the Windower stage contain implementation specific information required for the rasterization of objects and also supports clipping of primitives to some extent Windower IZ WIZ Stage The WIZ unit performs an early depth test which removes failing pixels and eliminates unnecessary processing overhead The Windower uses the parameters provided by the SF unit in the object specific rasterization algorithms The WIZ unit rasterizes objects into the corresponding set of pixels The Windower is also capable of performing dithering whereby the illusion of a higher resolution when using low bpp channels in color buffers is possible Color dithering diffuses the sharp color bands seen on smooth shaded objects Video Engine The Video Engine handles the non 3D media video applications It includes support for VLD and MPEG2 decode in hardware 2D Engine The 2D Engine contains BLT Block Level Transfer functionality and an extensive set of 2D instructions To take advantage of the 3D during engine s functionality some BLT functions make use of the 3D renderer 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 24 Order No 330834 004v1 m Interfaces Processor n tel j Logical 128 Bit Fixed BLT and 256 Fill Engine This BLT engine accelerates the GUI of
206. vent them from being tampered by malicious software Intel VT d Objectives The key Intel VT d objectives are domain based isolation and hardware based virtualization A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated Intel VT d provides accelerated I O performance for a virtualized platform and provides software with the following capabilities e I O device assignment and security for flexibly assigning I O devices to VMs and extending the protection and isolation properties of VMs for I O operations e DMA remapping for supporting independent address translations for Direct Memory Accesses DMA from devices e Interrupt remapping for supporting isolation and routing of interrupts from devices and external interrupt controllers to appropriate VMs e Reliability for recording and reporting to system software DMA and interrupt errors that may otherwise corrupt memory or impact VM isolation Intel VT d accomplishes address translation by associating a transaction from a given I O device to a translation table associated with the Guest to which the device is assigned It does this by means of the data structure in the following illustration This table creates an association between the device s PCI Express Bus Device Function B D F number and the base address of a translation table This data structure is populated by a VMM to map devices to translation
207. ws slide shows and so on Poor examples are 3D games e Static screens such as screens with significant portions of the background showing 2D applications processor benchmarks and so on or conditions when the processor is idle Poor examples are full screen 3D games and benchmarks that flip the display image at or near display refresh rates Intel Graphics Dynamic Frequency Intel Graphics Dynamic Frequency Technology is the ability of the processor and graphics cores to opportunistically increase frequency and or voltage above the guaranteed processor and graphics frequency for the given part Intel Graphics Dynamic Frequency Technology is a performance feature that makes use of unused package power and thermals to increase application performance The increase in frequency is determined by how much power and thermal budget is available in the package and the application demand for additional processor or graphics 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 58 Order No 330834 004v1 m Power Management Processor n tel 4 4 5 4 4 6 4 4 7 performance The processor core control is maintained by an embedded controller The graphics driver dynamically adjusts between P States to maintain optimal performance power and thermals The graphics driver will always t
208. ximum voltage for extended periods 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 92 March 2015 Order No 330834 004v1 Electrical Specifications Processor Table 45 Table 46 Table 47 Table 48 Digital Display Interface Group DC Specifications 2 The Vccgr referred to in these specifications refers to instantaneous VCCIO OUT 3 For VIN between 0 V and Vccsr Measured when the driver is tri stated 4 V H and Voy may experience excursions above Vccsr However input signal drivers must comply with the signal quality specifications GTL Signal Group and Open Drain Signal Group DC Specifications Symbol Parameter Min Typ Max Units Vit HPD Input Low Voltage 0 8 Vin HPD Input High Voltage 2 25 _ 3 6 Vaux Tx Aux peak to peak voltage at transmitting 0 39 _ 1 38 device Aux peak to peak voltage at receiving m Vaux Rx device 0 32 1 36 Embedded DisplayPort eDP Group DC Specifications Symbol Parameter Min Typ Max Units VoL eDP DISP UTIL Output Low Voltage 0 0 1 VCC V VoH eDP_DISP_UTIL Output High Voltage 0 9 VCC VCC V Rup eDP DISP UTIL Internal pull up 100 Q Rpown eDP_DISP_UTIL Internal pull down 100 Q Vaux Tx Aux peak to peak voltage at 0 39 _
209. y Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 122 March 2015 Order No 330834 004v1 Processor Ball and Signal Information Processor Table 57 U Processor Ball Information LP DDR3 Non Interleaved intel Signal Name Ball Signal Name Ball Signal Name Ball LP DDR3 LP DDR3 LP DDR3 ACPRESENT AJ8 CL_CLK AF2 DAISY_CHAIN_NCTF AW61 GPIO31 _AW61 CL_DATA AD2 APWROK AB5 DAISY_CHAIN_NCTF AW62 CL RST AF4 _AW62 BATLOW GPIO72 AN4 CLKOUT_ITPXDP_N B35 DAISY_CHAIN_NCTF AW63 BMBUSY GPIO76 P1 _AW63 CLKOUT ITPXDP P A35 BPM 0 J60 a 3 we DAISY CHAIN NCTF AY2 _LPC_ AY2 BPM 1 H60 AV i CLKOUT_LPC_1 AP15 DAISY_CHAIN_NCTF AY3 AY3 CLKOUT_PCIE_NO C43 BPM 3 H62 DAISY_CHAIN_NCTF AY60 CLKOUT_PCIE_N1 B41 AY60 BPM 4 K59 BB EREN CLKOUT_PCIE_N2 C41 DAISY_CHAIN_NCTF AY61 CLKOUT_PCIE_N3 B38 AY61 BPM 6 K60 CLKOUT_PCIE_N4 A39 E ME ANGE BPM 7 J61 ae Mes CLKOUT PCIE N5 B37 DAISY_CHAIN_NCTF B2 CLKOUT PCIE PO C42 Be CFG 0 AC60 CLKOUT PCIE P1 A41 K aac acd B3 CFG 1 AC62 CFG 10 ved CLKOUT PCIE P2 Be DAISY_CHAIN_NCTF B61 2
210. y State with External Graphics CO C1 C1E Dynamic memory rank power down based on idle conditions Dynamic memory rank power down based on idle conditions C3 C6 C7 If the processor graphics engine is idle and there are no pending display reguests then enter self refresh Otherwise use dynamic If there are no memory reguests then enter self refresh Otherwise use dynamic memory rank power down based on idle conditions 4 3 2 3 4 3 2 4 4 3 3 memory rank power down based on idle conditions S3 Self Refresh Mode Self Refresh Mode S4 Memory power down contents lost Memory power down contents lost Dynamic Power Down Dynamic power down of memory is employed during normal operation Based on idle conditions a given memory rank may be powered down The IMC implements aggressive CKE control to dynamically put the DRAM devices in a power down state The processor core controller can be configured to put the devices in active power down CKE de assertion with open pages or pre charge power down CKE de assertion with all pages closed Pre charge power down provides greater power savings but has a bigger performance impact since all pages will first be closed before putting the devices in power down mode If dynamic power down is enabled all ranks are powered up before doing a refresh cycle and all ranks are powered down at the end of refresh DRAM I O Power Management Unused si
211. y technology DDR3L DDR3 Low Voltage DDR3L RS DDR3 Low Voltage Reduced Standby Power DLL Delay Locked Loop DMA Direct Memory Access DP DisplayPort DTS Digital Thermal Sensor continued 5th Generation Intel Core Processor Family Intel Core M Processor Family Mobile Intel Pentium Processor Family and March 2015 Mobile Intel Celeron Processor Family Datasheet Volume 1 of 2 Order No 330834 004v1 13 Processor Introduction Term Description DVI Digital Visual Interface DVI is the interface specified by the DDWG Digital Display Working Group EC Embedded Controller ECC Error Correction Code eDP embedded DisplayPort EPG Electrical Power Gating EU Execution Unit FMA Floating point fused Multiply Add instructions FSC Fan Speed Control HDCP High bandwidth Digital Content Protection HDMI High Definition Multimedia Interface HFM High Frequency Mode iDCT Inverse Discrete Cosine Transform IHS Integrated Heat Spreader GFX Graphics GUI Graphical User Interface IMC Integrated Memory Controller Intel 64 64 bit memory extensions to the IA 32 architecture Technology Intel DPST Intel Display Power Saving Technology Intel TSX NI Intel Transactional Synchronization Extensions New Instructions Intel TXT Intel Trusted Execution Technology Intel Virtualization Technology Processor virtualizatio

Intel Pentium G6951

Contents

Download Pdf Manuals

Related Search

Related Contents