Goodram 4GB DDR2-800
Contents
1. tCKmax 0x80 128 44 SDRAM Device Maximum skew between DQS and DQ signals tDQSQ 0x14 20 45 DDR SDRAM Device Maximum Read Data Hold Skew Factor tQHS Ox1E 30 46 Reserved for future use 0x00 0 47 SDRAM Device Attributes DDR SDRAM DIMM Height 0x00 0 48 Reserved for future use 0x00 0 49 Reserved for future use 0x00 0 50 Reserved for future use 0x00 0 5 Reserved for future use 0x00 0 52 Reserved for future use 0x00 0 53 Reserved for future use 0x00 0 54 Reserved for future use 0x00 0 55 Reserved for future use 0x00 0 56 Reserved for future use 0x00 0 57 Reserved for future use 0x00 0 58 Reserved for future use 0x00 0 59 Reserved for future use 0x00 0 60 Reserved for future use 0x00 0 61 Reserved for future use 0x00 0 62 SPD Revision 0x11 17 63 Checksum for Bytes 0 62 0x2B 43 64 255 Manufacturer s specific data GOODRAM logo and GOODDRIVE logo are registered trademarks of Wilk Elektronik S A Wilk Elektronik S A All other trademarks and logos are the property of their respective owners Poland 43 174 aziska G rne ul Mikolowska 42 WILK All products and specifications are subject to change without notice tel 0 32 736 90 00 fax 0 32 736 90 01 ELEKTRONIK SA www Wilk com pl e www goodram com ae Rev 04 12 2007 Wilk Elektronik S A 20072. SDRAM Device Attributes Burst Lengths Supported 0x0C 12 17 SDRAM Device Attributes Number of Banks on SDRAM Device 0x08 8 18 SDRAM Device Attributes CAS Latency 0x70 112 19 SDRAM Device Attributes CS Latency 0x00 0 20 SDRAM Device Attributes Write Latency DIMM Type Information 0x02 2 21 SDRAM Module Attributes 0x00 0 22 SDRAM Device Attributes General 0x07 7 23 Minimum Clock Cycle at CL X 0 5 0x25 37 24 Maximum Data Access Time tAC from Clock at CL X 0 5 0x40 64 25 Minimum Clock Cycle at CL X 1 0x3D 61 26 Maximum Data Access Time tAC from Clock at CL X 1 0x50 80 27 Minimum Row Precharge Time tRP 0x32 50 28 Minimum Row Active to Row Active delay tRRD Ox1E 30 29 Minimum RAS to CAS delay tRCD 0x32 50 30 Minimum Active to Precharge Time tRAS 0x2D 45 31 Module Bank Density 0x01 1 32 Address and Command Input Setup Time Before Clock 0x17 23 33 Address and Command Input Hold Time After Clock 0x25 37 34 Data Input Setup Time Before Clock 0x05 5 35 Data Input Hold Time After Clock 0x12 18 36 Write recovery time tWR 0x3C 60 37 Internal write to read command delay tWTR Ox1E 30 38 Internal read to precharge command delay tRTP Ox1E 30 39 Memory Analysis Probe Characteristics 0x00 0 40 Extension of Byte 41 tRC and Byte 42 tRFC 0x36 54 4 SDRAM Device Minimum Active to Active Auto Refresh Time tRC 0x3C 60 42 SDRAM Device Minimum Auto Refresh to Active Auto Refresh tRFC Ox7F 127 43 SDRAM Device Maximum device cycle time
3. Www goodram com GR 800 D2 64 GOODRAM SPEED DATA TRANSFER 800MHz PC2 6400 MODULETYPE DDR2 SDRAM DIMM MODULE DATAWIDTH 64 CAS LATENCY 5 MODULE DENSITY 4GB Dual Channel L5 4GDC FEATURES PART NUMBER MODULETYPE MODULE DENSITY MODULE DATA WIDTH DRAM CHIP ORAGNIZATION NUMBER OF DRAM CHIPS NUMBER OF MODULE RANKS NUMBER OF MODULE SIDES REGISTERED ECC SUPPORT PIN COUNT SUPPLY VOLTAGE SSTL_18 COMPATIBLE PROGRAMMED SPD MEMORY MAX AVG PERIODIC REFRESH INTERVAL GR800D264L5 4GDC DDR2 SDRAM DIMM 2x2GB 64 128Mx8 16 2 2 NO NO 240 PIN 1 8V YES 128 BYTES 7 8 us OVC NId OTI Nid OPERATING FREQUENCY 800MHz 2x400MHz PC2 6400 800MHz 2x400MHz PC2 6400 533MHz 2x266MHz PC2 4200 CAS Latency 6 5 4 DYNAMIC PARAMETERS FOR 800MHz RAS TO CAS DELAY tRCD ROW PRECHARGE TIME tRP ROW ACTIVE TO ROW ACTIVE DELAY tRRD ACTIVE TO PRECHARGE TIME tRAS ACTIVE TO ACTIVE AUTO REFRESH TIME tRC AUTO REFRESH TO ACTIVE AUTO REFRESH tRFC DEVICE CYCLE TIME tCK MAX 12 ns 12 ns ns 45 ns 60 ns 127 ns 8 PCB DETAILS PCB TYPE BOARD DIMENSIONS BOARD THICKNESS DRAM PACKAGE INFORMATION CONTACT PADS PIN DDR2 SDRAM DIMM 133 35 x 30mm 0 1mm 1 27mm 0 13mm FBGA x8bit GOLD PLATED GOODRAM logo and GOODDRIVE logo are registered trademarks of Wilk Elektronik S A All other trademarks and logos are the property of their respective owners All products and specificati
4. ons are subject to change without notice Rev 04 12 2007 DDR II MODULE PART NUMBERING SYSTEM MEMORY MODULE SPECIFICATION professional memory for everyone ICI Nid I Nid Wilk Elektronik S A Poland 43 174 aziska G rne ul Mikolowska 42 tel 0 32 736 90 00 fax 0 32 736 90 01 www Wilk com pl www goodram com Wilk Elektronik S A 2007 Y9 Nid TELETTLELETTIT os SEEEL WILK ELEKTRONIK SA M T E c Wwww goodram com MEMORY MODULE SPECIFICATION SPD CONFIGURATION GOOD BYTE DESCRIPTION HEX DEC E y AN II professional memory for everyone 0 Number of Serial PD Bytes written during module production 0x80 128 1 Total number of Bytes in Serial PD device 0x08 8 2 Fundamental Memory Type FPM EDO SDRAM 0x08 8 3 Number of Row Addresses on this assembly Ox0E 14 4 Number of Column Addresses on this assembly 0x0A 10 5 Number of DIMM Banks 0xA1 161 6 Data Width of this assembly 0x40 64 7 Data Width of this assembly 0x00 0 8 Voltage Interface Level of this assembly 0x05 5 9 SDRAM Cycle time at Maximum Supported CAS Latency CL CL X 0x25 37 10 SDRAM Access from Clock 0x40 64 11 DIMM configuration type Non parity Parity or ECC 0x00 0 12 Refresh Rate Type 0x82 130 13 Primary SDRAM Width 0x08 8 14 Error Checking SDRAM Width 0x00 0 15 SDRAM Device Attributes Minimum Clock Delay Back to Back RCA 0x00 0 16
Download Pdf Manuals
Related Search