Samsung 2GB DDR3-1333
Contents
1. 55h 17h 23h 70h 127 Cyclical Redundancy Code 60h C9h 16h 1Eh 128 Module Part Number M 4Dh 129 Module Part Number 33h 130 Module Part Number 7 37h 131 Module Part Number 8 38h 132 Module Part Number B 42h 133 Module Part Number 5 35h 134 Module Part Number 6 36h 135 Module Part Number 7 37h 136 Module Part Number 3 33h 137 Module Part Number G die 47h 138 Module Part Number B 42h 139 Module Part Number 0 30h 140 Module Part Number 2Dh 141 Module Part Number Cc 43h 142 Module Part Number F K M 46h 48h 4Bh 4Dh 143 Module Part Number 8 0 38h 39h 30h 4th 144 Module Part Number Blank 20h 145 Module Part Number Blank 20h 146 147 Module Revision Code 00h 148 SDRAM Manufacturer s JEDEC ID Code Samsung 80h 149 SDRAM Manufacturer s JEDEC ID Code Samsung CEh 150 175 Manufacturer s Specific Data x 00h 176 255 Open for customer use 00h Page 2 2 JAN 20112. SERIAL PRESENCE DETECT M378B5673GB0 CF8 CH9 CK0 CMA Organization 256M x 64 Composition 128M x 8 16ea Used component part K4B1G0846G BCF8 BCH9 BCK0 BCMA of rows in module 2 Row of banks in component 8 Banks Feature 30mm height amp double sided component Refresh 8K 64ms Bin Sort F8 DDR3 1066 CL 7 H9 DDR3 1333 CL 9 KO DDR3 1600 CL 11 MA DDR3 1866 CL 13 Samsona ELECTRONICS Byte unai Function Supported Hex Value A cre cho cko cma cre cHo cKO cma Number of Serial PD Bytes Written SPD Device Size CRC Coverage CRC coverage 0 116Byte SPD Byte 0 Total 256Byte SPD Byte Use 92h 176Byte j SPD Revision Version 1 1 11h 2 Key Byte DRAM Device Type DDR3 SDRAM OBh 3 Key Byte Module Type Unbuffered DIMM 02h 4 SDRAM Density and Banks 1Gb 8banks 02h 5 SDRAM Addressing Row 14 Column 10 11h 6 Module Nominal Voltage VDD 1 5V only 00h 7 Module Organization 2Rank x8 09h 8 Module Memory Bus Width Non ECC 64bit 03h 9 Fine Timebase Dividend and Divisor 1ps 1th 10 Medium Timebase Dividend 1 8 0 125ns Oth 11 Medium Timebase Divisor 1 8 0 125ns 08h 12 SDRAM Minimum Cycle Time tCKmin 1 875ns 1 5ns 1 25ns 1 071ns OFh OCh OAh 09h 13 Reserved Reserved 00h CAS Latencies Support
3. Type Standard Monolithic DRAM Device 00h 34 Fine Offset for SDRAM Minimum Cycle Time tCKmin 1 875ns 1 5ns 1 25ns 1 071ns 00h 00h 00h CAh 35 Fine Offset for Minimum CAS Latency Time tAAmin 13 125ns 00h 36 Fine Offset for Minimum RAS to CAS Delay Time tRCDmin 13 125ns 00h Page 1 2 JAN 2011 SERIAL PRESENCE DETECT Samsona ELECTRONICS Byte f Function Supported Hex Value Function Described Note CF8 CH9 CKO CMA CF8 CH9 CKO CMA 37 Fine Offset for Minimum Row Precharge Delay Time tRPmin 13 125ns 00h 38 Fine Offset for Minimum Active to Active Refresh Delay Time tRCmin 50 625ns 49 125ns 48 125ns 47 125ns 00h 39 59 Reserved General Section Reserved 00h 60 Module Nominal Height 30mm OFh 61 Module Maximum Thickness Planar Double sides 11h 62 Reference Raw Card Used R C B 1 0 2th 63 Address Mapping from Edge Connector to DRAM Mirrored Oth 64 116 Reserved 5 00h 117 Module Manufacturer ID Code Least Significant Byte Samsung 80h 118 Module Manufacturer ID Code Most Significant Byte Samsung CEh 119 Module ID Module Manufacturing Location Onyang Korea Oth 120 Module ID Module Manufacturing Date 00h 121 Module ID Module Manufacturing Date 00h 122 125 Module ID Module Serial Number 00h 126 Cyclical Redundancy Code
4. ed Least Significant Byte 6 7 8 6 7 8 6 7 8 14 6 7 8 g 9 10 9 10 1Ch 3Ch FCh FCh 11 11 13 CAS Latencies Supported Most Significant Byte 6 7 8 6 7 8 6 7 8 15 6 7 8 g 9 9 10 9 10 00h 00h 00h 02h 11 11 13 16 Minimum CAS Latency Time tAAmin 13 125ns 69h 7 Minimum Write Recovery Time tWRmin 15ns 78h 18 Minimum RAS to CAS Delay Time tRCDmin 13 125ns 69h 19 Minimum Row Active to Row Active Delay Time tRRDmin 7 5ns 6ns 6ns 5ns 3Ch 30h 30h 28h 20 Minimum Row Precharge Delay Time tRPmin 13 125ns 69h 21 Upper Nibbles for tRAS and tRC 11h 22 Minimum Active to Precharge Time tRASmin Least Significant Byte 37 5ns 36ns 35ns 34ns 2Ch 20h 18h 10h 23 Minimum Active to Active Refresh Time tRCmin Least Significatn Byte 50 625ns 49 125ns 48 125ns 47 125ns 95h 89h 81h 79h 24 Minimum Refresh Recovery Time tRFCmin Least Significant Byte 110ns 70h 25 Minimum Refresh Recovery Time tRFCmin Most Significant Byte 110ns 03h 26 Minimum Internal Write to Read Command Delay Time tWTRmin 7 5ns 3Ch 27 Minimum Internal Read to Precharge Command Delay Time tRTPmin 7 5ns 3Ch 28 Upper Nibble for tFAW 37 5ns 30ns 30ns 27ns Oth 00h 00h 00h 29 Minimum Four Activate Window Delay Time tFAWmin Least Significant Byte 37 5ns 30ns 30ns 27ns 2Ch FOh FOh D8h 30 SDRAM Optional Features DLL off Mode RZQ 6 RZQ 7 83h 31 SDRAM Thermal and Refresh Options No ODTS No ASR Oih 32 Module Thermal Sensor without TS 00h 33 SDRAM Device
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