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Intel Pentium III Xeon 600 MHz

1. A161 VSS Ground B161 SMBDAT SMBus Data A164 VSS Ground B164 RESERVED _B164 DO NOT CONNECT A165 PWR ENO Short to RESERVED B165 DO NOT CONNECT PWR_EN 1 67 ss zamm o mow w mw w wee m ws em ee e R K eee r n R R e MECHANICAL SPECIFICATIONS Table 45 Signal Listing in Order by Pin Name A144 ADS A145 AP 0 B146 APH 1 BCLK BINITA A127 BNR BPH BPM Signal Buffer Type AGTL I O AGTL I O AGTL I O OCVR Analog Output AGTL I O AGTL I O A124 A 04 AGTL UO B121 A 08 AGTL UO B119 AR 12 AGTL VO A115 AR 16 AGTL VO A112 AH 19 AGTL UO A110 AH 23 AGTL UO A107 AR 27 AGTL VO A106 AR 31 AGTL VO A103 AR 34 AGTL VO A13 anoo 68 om eS oe cee we ewww Se oe we ew ee AA MECHANICAL SPECIFICATIONS A92 D 05 AGTL VO A89 D 09 AGTL VO A80 D 13 AGTL VO A79 D 16 AGTL UO 397 AGTL VO DAITE AGTL VO DAT AGTL VO B81 D 20 AGTL UO AGTL I O B71 D 28 AGTL UO A70 D 31 AGTL UO AGTL I O A61 D 39 AGTL VO AGTL I O B60 D 47 AGTL VO B49 DH 50 AGTL VO B51 D 54 AGTL VO AGTL I O AGTL I O AGTL I O AGTL I O AGTL I O 69 mw eS oe cee we ewww Se oe we ew ee AA MECHANICAL SPECIFICATIONS A132 DEFER AGTL Input A39 DEP 3 AGTL I O B42 DEP4 7 AGTL I O B10 FLUSH CMOS Input B3 e 2 O HV_EN OPEN 2 8V Pentium lll Xeon processor SHORT 5 12
2. Overshoot Undershoot Magnitude levels must also observe the Absolute Maximum Specifications These specifications must not be violated at any time regardless of bus activity or system state Within these specifications are threshold levels that define different allowed Pulse Durations Provided that the magnitude of the Overshoot Undershoot is within the Absolute Maximum Specifications the impact of the Overshoot Undershoot Magnitude may be determined based upon the Pulse Duration and Activity Factor 4 2 2 2 Overshoot Undershoot Pulse Duration Overshoot Undershoot Pulse Duration describes the total time that an Overshoot Undershoot event exceeds the Overshoot Undershoot Reference Voltage Vos_ref 1 635V This total time could encompass several oscillations above the Overshoot Undershoot Reference Voltage Thus multiple Overshoot Undershoot pulses within a single Overshoot Undershoot event must be measured to determine the total Pulse Duration Note Oscillations below the Reference Voltage cannot be subtracted from the total Overshoot Undershoot Pulse Duration Note Multiple Overshoot Undershoot events occurring within the same clock cycle must be considered together as one event Using the worst case Overshoot Undershoot Magnitude sum together the individual Pulse Durations to determine the total Overshoot Undershoot Pulse Duration for that total event 4 2 2 3 Overshoot Undershoot Activity Factor Activity Factor AF describes the freq
3. V V Oou Input Leakage Current Output Leakage 2 Current Con UO Pin Capacitance NOTES 1 0 lt Vin lt 2 625V 2 0 lt Vout lt 2 625V 3 Total capacitance of processor core and voltage clamp device Does not include cartridge trace capacitance Applies to all CMOS TAP Clock and APIC signals except BCLK PICCLK and PWRGOOD This parameter applies to PICCLK This parameter applies to PWRDG Maximum VL at the processor core pin is specified as 2 3 Vit 0 2V Minimum Vi at the processor core pin is specified as 2 3 Vrt 0 2V OL OH L Lo Con NDA 20 msu s svenn nn sammen we ewww ww o A A RR S KRSR ew eee AI ELECTRICAL SPECIFICATIONS Table 9 SMBus Signal S DC S at the R aa fingers Input Low Voltage a 3x VCC_SMB Vin Input High Voltage 0 7 x 3 465 3 3V 5 maximum VCCsmB A pepe R T cones o m _ ETE ez owon 6 H ae mantengo are PT to omaan w a NOTES 1 SMBALERT is an open drain signal Table 10 OCVR Control Signals DC Specifications at the processor edge fingers Symbol Parameter Min Max Unt Notes Input Low Voltage A nl O E A Vin Input High Voltage 3 E E A re VoL Output Low Voltage 0 4 V 1 5mA max PA Bis IN A A VoH Output High Voltage V 1 Pai AAA S NOTES 1 Driver configured as open drain connected to 3 3V Vcc_SMB through a 10K ohm resistor 2 Vih_max absolute 5 25VDC when the OCVR is powered 3 If the OCVR o
4. and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level The term system bus refers to the interface between the processor system core logic and other bus agents The system bus is a multiprocessing interface to processors memory and I O Cache coherency is maintained with other agents on the system bus through the MESI cache protocol as supported by the HIT and HITM bus signals The term Pentium III Xeon processor at 600 MHz refers to the cartridge package that interfaces to a host system board through the SC330 1 connector The Pentium lll Xeon processor at 600 MHz includes the processor core with integrated L2 cache an On Cartridge Voltage Regulator OCVR system bus termination and various system management features In addition the Pentium III Xeon processor at 600 MHz includes a thermal plate for cooling solution attachment and a protective cover The Pentium III Xeon processor at 600 MHz system bus operates using GTL signaling levels with a new type of buffer utilizing active negation and multiple terminations This bus logic is called Assisted Gunning Transistor Logic or AGTL This document provides information to allow the user to design a system using Pentium Ill Xeon processor at 600 MHz 2 1 S E C CARTRIDGE TERMINOLOGY The following terms are used in this document and are defined here for clarification e Cover The processor casing on the opposite side of the thermal pla
5. 1 OEM EEPROM Present 1 Present 0 Not Present L Core VID present 1 Present 0 Not Present L2 Cache VID present Always Zero Number of Devices in TAP One 4 bit hex digit lt a Reseved Resemedforfutureuse for future use NOTES 1 OCVR Output Voltage not tested Programmed per design target 45 msu Sm RRR oe cee we ewww Se oe A A e ee A PROCESSOR FEATURES 5 2 2 SCRATCH EEPROM Also available on the SMBus is an EEPROM that may be used for other data at the system or processor Vendors discretion This device has a pull down on the WP control pin through a 10K Q resistor as implemented on all previous Pentium Il Xeon and Pentium III Xeon processors This will allow the OEM EEPROM to be programmed in systems with no manipulation of this signal Once programmed the data in this OEM EEPROM can be write protected by asserting the active high WP signal The Scratch EEPROM is a 1024 bit part 5 2 3 PROCESSOR INFORMATION ROM AND SCRATCH EEPROM SUPPORTED SMBUS TRANSACTIONS Four SMBus packet types are associated with the PIROM and Scratch EEPROM Each of these packet transfers provides a device select address and read write bit The remaining parts of the transfer vary Two of the packets Send Byte and Receive Byte transfer one additional byte after the device select The other two packets Write Byte and Read Byte transfer two additional bytes after the device select By using these four transfer types complete access
6. 8 2 1 LAI and Trace Capture tool Mechanical Keep Outs Please contact your third party tools vendor for mechanical keep out restrictions for the Pentium Ill Xeon processor at 600 MHz 81 mw eS oe cee we ewww Se oe ew eee AI BOXED PROCESSOR SPECIFICATIONS 9 BOXED PROCESSOR SPECIFICATIONS 9 1 Introduction The Pentium Ill Xeon processor at 600 MHz is also offered as an Intel boxed processor Intel boxed processors are intended for system integrators who build systems from baseboards and off the shelf components The boxed Pentium lll Xeon processor at 600 MHz is supplied with an attached passive heat sink This section documents baseboard and system requirements for the heat sink that will be supplied with the boxed Pentium Ill Xeon processor at 600 MHz This section is particularly important for OEMs that manufacture baseboards for system integrators Unless otherwise noted all figures in this chapter are dimensioned in inches Figure 33 shows a mechanical representation of the boxed Pentium III Xeon processor at 600 MHz DN D My A N O W X Y N V U N y N N U NA N N IN AN AN U L VC T NN NN W W Y Ny Y Zz U N N N N WAN U U U X U N N U A N N W N l HI NN NN NON W NV T Al IN N AN A N V ON N N l U l O N y V UL L 7 N N ON U l CET SES CL EEES fe OI LA A
7. Processor at 600 MHz to 1 GHz with 256KB L2 Cache hereafter referred to as the Pentium Ill Xeon processor at 600 MHz provides the best performance available for applications running on advanced operating systems such as Windows 98 Windows NT and UNIX The Pentium Ill Xeon processor at 600 MHz is scalable to two processors in a multiprocessor system and extends the power of the Pentium Pro processor with new features designed to make this processor the right choice for powerful workstation advanced server management and mission critical applications 600 MHz Pentium Ill Xeon Processor based workstations offer the memory architecture required by the most demanding workstation applications and workloads Specific features of the 600 MHz Pentium Ill Xeon Processor address platform manageability to meet the needs of a robust IT environment maximize system up time and ensure optimal configuration and operation of servers Pentium Ill Xeon processor at 600 MHz enhances the ability of server platforms to monitor protect and service the processor and its environment Order Number 245305 004 August 2000 Information in this document is provided solely to enable the use of Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel s Terms and Conditions of Sale for such products Information contained herein supersedes previously published
8. e SC 330 processor refers to the Pentium Il Xeon processor Pentium Ill Xeon processor or 600 MHz Pentium III Xeon processor e C330 1 refers to the 600 MHz Pentium Ill Xeon processors added cartridge pin functionality The SC 330 1 interface is an electrical enhancement of the SC 330 interface and supports up to four processors utilizing a 100 MHz system bus or up to two processors utilizing a 133MHz system bus The SC 330 1 interface adds the required flexibility to accommodate control and monitoring signals for the OCVR e Retention mechanism A mechanical component designed to hold the processor in a SC330 connector 2 2 References The reader of this specification should also be familiar with material and concepts presented in the following documents available from either the Intel document center or http developer intel com e Intel Processor Identification and the CPUID Instruction Order Number 241618 e Pentium IlI Xeon processor Signal Integrity Models Viewlogic XTK Format s Pentium III Xeon processor Specification Update Order Number 244460 e C330 Processor Enabling Technology Vendor List e Intel Architecture Software Developers Manual Order Number 243193 Volume l Basic Architecture Order Number 243190 Volume II Instruction Set Reference Order Number 243191 Volume III System Programming Guide Order Number 243192 e 330 Contact Slot Connector SC330 Design Guidelines e VRM 8 3 DC DC co
9. which helps reduce overshoot levels at the processor core All CMOS TAP Clock and APIC signals interface with the 16 AS r R s sew r p m m r R R e K S Pus seen sw ew ee r n R R e ELECTRICAL SPECIFICATIONS voltage clamp with the exception of BCLK PICCLK and PWRGOOD The DC specifications for these pins are listed in Table 8 and Table 9 NOTE Unless otherwise noted each specification applies to all Pentium III Xeon processors at 600 MHz Specifications are only valid while meeting specifications for case temperature clock frequency and input voltages Care should be taken to read all notes associated with each parameter Table 5 Voltage Specifications 1 Parameter Vcc 2 8V Pentium IIl Xeon processor Voc 5 12V Pentium lll Xeon processor NGC CORE Tolerance Core voltage static tolerance at edge Static fingers 2 8v Pentium III Xeon processor NGC CORE Processor core voltage transient Tolerance tolerance at edge fingers Transient 2 8V Pentium III Xeon processor AGTL Bus Termination voltage SMBus supply voltage TAP supply voltage NOTES go N Unless otherwise noted all specifications in this table apply to all processor frequencies FMB is a suggested design guideline for flexible motherboard design Failure to adhere to the FMB guidelines may impact system upgradeability VCC_CORE supplies the processor core FMB refers to the range of set points for all Pentium III X
10. Magnitude 2 25 m Y N X N N o m wo Activity Factor based on period equal to 30 nS Overshoot Undershoot Magnitude 2 3V is an Absolute value and should never be exceeded Overshoot is measured relative to VSS Undershoot is measured relative to VTT Overshoot Undershoot Pulse Duration is measured relative to 1 635V Rinback below VTT cannot be subtracted from Overshoots Undershoots Lesser Undershoot does not allocate longer or larger Overshoot OEM s are encouraged to follow Intel provided layout guidelines All values specified by design characterization 1 2 3 4 5 6 7 8 9 4 3 2 BCLK Overshoot Undershoot Guidelines and Specifications Unlike AGTL or CMOS signals BCLK Specifications do not provide for any relaxation due to activity factor System designers should ensure that their platforms meet the BCLK specifications even under worst case conditions 36 s es eS nn rr r R s sem r p m m r R K e KR e KRSR Kee K R g Kee RR S KRSR m R Ker ANI SIGNAL QUALITY Intel recommends that platforms meet the Absolute Maximum Specifications for Overshoot and Undershoot on BCLK This ensures that the BCLK I O Buffer will meet specifications regardless of Overshoot or Undershoot Pulse Duration within a Clock cycle with 50 Duty Cycle For all Pentium III Xeon processors at 600 MHz the maximum Overshoot level is 3 3V The Absolute maximum Undershoot is 0 7V where maximum is defined as the la
11. Signal Integrity issues may require this circuit to be modified 2 Current Intel 840 chipsets do not implement the CRESET signal 3 4 2 MIXING PROCESSORS OF DIFFERENT FREQUENCIES Mixing components of different internal clock frequencies is not supported and has not been validated by Intel Operating system support for multi processing with mixed frequency components should also be considered Also Intel does not support or validate operation of processors with different cache sizes Intel only supports and validates multi processor configurations where all processors operate with the same system bus and core frequencies and have the same L1 and L2 cache sizes Similarly Intel does not support or validate the mixing of Pentium III Xeon processor at 600 MHz Pentium IlI Xeon processor and Pentium Il Xeon processors on the same system bus regardless of frequency or L2 cache sizes 3 5 Voltage Identification To provide power delivery flexibility the Pentium III Xeon processor at 600 MHz is available in two different input voltage versions one version operates at 2 8 Volts and the other at 5 Volts or 12 Volts As in previous versions of Pentium II Xeon and Pentium Ill Xeon processors the Pentium Ill Xeon processor at 600 MHz contains five voltage identification VID pins these pins are used on Pentium III Xeon processor at 600 MHz for OCVR voltage selection in combination with pin A3 which incorporates added functionality f
12. 1 6 CLOCK CONTROL During Auto HALT Power Down and Stop Grant states the processor will continue to process the snoop phase of a system bus cycle The PICCLK signal should not be removed during the Auto HALT Power Down or Stop Grant states When the processor is in the Sleep state it will not respond to interrupts or snoop transactions PICCLK can be removed during the Sleep state The processor will not enter any low power states until all internal queues for the second level cache are empty When re entering Normal state the processor will resume processing external cache requests as soon as new requests are encountered 5 2 System Management Bus SMBus Interface The Pentium III Xeon processor at 600 MHz includes an SMBus interface that allows access to several processor features including two memory components referred to as the processor Information ROM and the Scratch EEPROM and a thermal sensor on the Pentium lll Xeon processor at 600 MHz substrate These devices and their features are described below The Pentium Ill Xeon processor at 600 MHz SMBus implementation uses the clock and data signals of the SMBus specification It does not implement the SMBSUS signals 41 om eS oe cee we ewww Se oe K o g Kee RR S KRSR m R eee AI PROCESSOR FEATURES SA1 SDA SCL yp SAO SMB_V SA2 SMBALERT Figure 16 Logical Schematic of SMBus Circuitry NOTES 1 Actual implementation may vary For use in general understanding of the a
13. 2 Termination should include series 240 ohm and AGTL termination connected to 1 5V resistors Figure 30A 3 Signal should be at end of daisy chain and the boundary scan chain should be partitioned into two distinct sections to assist in debugging the system one partition with only the processor s for system debug i e used with the ITP and another with all other components for manufacturing or system test 8 1 6 DEBUG PORT SIGNAL NOTES In general all open drain AGTL outputs from the system must be retained at a proper logic level whether or not the debug port is installed RESET from the processor system should be terminated at the debug port as shown Figure 30 Rt should be a 1504 on RESET PRDYn should have a similar layout however Rt should be 50Q to match board impedance rather than the normal 150Q since there are only 2 loads on this signal 1 5 Volts RESET Source Rs 240 Ohm Figure 30A AGTL Signal Termination 8 1 6 1 General Signal Quality Notes Signals from the debug port are fed to the system from the ITP via a buffer board and a cable If system signals routed to the debug port i e TDO PRDYn and RESET are used elsewhere in the system then dedicated drivers should be used to isolate the signals from reflections coming from the end of this cable If the Pentium III Xeon processor at 600 MHz boundary scan signals are used elsewhere in the system then the TDI TMS TCK and
14. 2 7 10 1 47 SELFSBO I SELFSB1 O The Pentium III Xeon processor at 600 MHz adds a new definition to the SELFSB 1 0 pins that is shown below 98 PENTIUMO III XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX Functionality A7 SELFSB1 Output Pentium III Xeon Saan processor at 600 MHz Detect A9 SELFSBO Input Frequency Selection SELFSB1 Output Frequency Detect 133Mhz N C SELFSBO Pentium Ill Xeon processor at 600 MHz Input Frequency Select 133MHz Pull up to 2 5V Table 52 Description of SELFSB pins 10 1 48 SLPH I The SLP Sleep signal when asserted in Stop Grant state causes processors to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PLL still operating processors in this state will not recognize snoops or interrupts The processor will recognize only assertions of the SLP STPCLK and RESET signals while in Sleep state If SLP is deasserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and APIC processor core units 10 1 49 SMBALERT 0 SMBALERT is an asynchronous interrupt line associated with the SMBus Thermal Sensor device 10 1 50 SMBCLK I The SMBCLK SMBus Clock signal is an input clock to the system management logic that is required for operation of the system management features o
15. A RR S KRSR ew eee ANI ELECTRICAL SPECIFICATIONS recommended range of values to support for the processor core A 1 in this table refers to an open pin and 0 refers to a short to ground The definition provided below is a superset of the definition previously defined for the Pentium Pro processor VID4 was not used by the Pentium Pro processor and is common to the Pentium Ill Xeon processor at 600 MHz for VCC_CORE only The power supply must supply the voltage that is requested or it must disable itself Table 2 Voltage Identification VIDA VID3 VID2 VID1 VIDO VCC_CORE 00110b 01111b 0 0 1 0 1 NOTES 1 0 processor pin connected to VSS 1 Open on processor may be pulled up to TTL VH on baseboard See the VRM 8 3 DC DC Converter Design Guidelines and or the VRM 8 3 DC DC Converter Design Guidelines 2 VRM output should be disabled for VCC_CORE values less than 1 80V Required for 2 8V Pentium IIl Xeon processors 4 The Pentium III Xeon processor at 600 MHz does not require an L2 voltage supply When installing Pentium IIl Xeon processor at 600 MHz the VCC_L2 and VID_L2 lines will be open on the cartridge 5 This VID setting can be used in combination with HV_EN pin A3 for differentiating 2 8V Pentium Xeon processor from 5 12V Pentium III Xeon processor cartridges 6 The 5 12V Pentium IIl Xeon processor does not require a VRM When installing a 5 12V Pentium III Xeon processor
16. NOTES 1 VCC_CORE must be applied to the OCVR input before OCVR_OK can become valid even though it could be pulled high if the VCC_SMB supply is turned on see figure 41 2 The OCVR_OK signal is not guaranteed to be valid until 0 5 mS max after Vin to the OCVR reaches 90 of it s nominal value 3 Vin is the input to the OCVR VCC_CORE Vout is the output from the OCVR VCC_CPU 96 PENTIUMO III XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX up for Pentium III Xeon Processor i E eee buffer 5V 3 3V E 45V VRM OUTEN PWRGD i i OCVR_EN OCVR_OK RV A TL Ered Other PS s PWR_GD_PS VRMs OCVRs with open drain PWR_GDs Reset Logic Figure 42 PWRGD Implementation 10 1 41 REQ 4 0 1 0 The REQ 4 0 Request Command signals must connect the appropriate pins of all Pentium Ill Xeon processor at 600 MHz system bus agents They are asserted by the current bus owner over two clock cycles to define the currently active transaction type 10 1 42 RESET I Asserting the RESET signal resets all processors to known states and invalidates their L1 and L2 caches without writing back any of their contents RESET must remain active for one microsecond for a warm reset for a power on reset RESET must stay active for at least one millisecond after the PWRGOOD input to the processor has asserted until this de assertion of RESET occurs all outpu
17. Pentium II Pentium III Pentium Il Xeon and Pentium Ill Xeon processor s implements a Dynamic Execution micro architecture a unique combination of multiple branch prediction data flow analysis and speculative execution The Pentium Ill Xeon processor at 600 MHz is available in a 256K cache size The Pentium Ill Xeon processor improves upon previous generations of Intel 32 bit processors by adding Streaming SIMD Extensions The Single Instruction Multiple Data SIMD extensions significantly accelerate performance of 3D graphics Besides 3D graphics improvements the extensions also include additional integer and cacheability instructions that improve other aspects of performance In addition the Pentium Ill Xeon processor at 600 MHz utilizes a variation of the S E C Single Edge Contact package technology first introduced on the Pentium II processor The SEC packaging technology allows the Pentium Ill Xeon processor at 600 MHz to implement the Dual Independent Bus Architecture and has 256KB of level 2 cache Level 2 cache is integrated in the processing unit and communication occurs at the full speed of the processor core As with previous members of the Pentium III Xeon processor family the Pentium III Xeon processor at 600 MHz features built in direct multiprocessing support For systems with up to two processors it is important to consider the additional power burdens and signal integrity issues of supporting multiple loa
18. R 8 w SIGNAL QUALITY 4 3 5 2 5V TOLERANT BUFFER SETTLING LIMIT GUIDELINE Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach before its next transition The amount allowed is 10 of the total signal swing VHI VLO above and below its final value A signal should be within the settling limits of its final value when either in its high state or low state before it transitions again Violation of the settling limit guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of the ringing increasing in the subsequent transitions 38 mw eS oe cee we ewww Se oe A A e ee A PROCESSOR FEATURES 5 PROCESSOR FEATURES 5 1 Low Power States and Clock Control The Pentium III Xeon processor at 600 MHz allows the use of Auto HALT Stop Grant and Sleep states to reduce power consumption by stopping the clock to specific internal sections of the processor depending on each particular state There is no Deep Sleep state on the Pentium III Xeon processor at 600 MHz Refer to for the following sections on low power states for the Pentium III Xeon processor at 600 MHz For the processor to fully realize the low current consumption of the Stop Grant and Sleep states an MSR bit must be set For the MSR at 02AH Hex bit 26 must be set to a 1 power on default is a 0 for the processor to stop all internal clocks during these modes For more inf
19. TDI I The TDI Test Data In signal transfers serial test data into the Pentium III Xeon processor at 600 MHz TDI provides the serial input needed for TAP support 10 1 56 TDO O The TDO Test Data Out signal transfers serial test data out of the Pentium Ill Xeon processor at 600 MHz TDO provides the serial output needed for TAP support 10 1 57 TEST_2 5 A23 A62 B27 I The TEST_2 5_A62 signal must be connected to a 2 5V power source through a 1 10K ohm resistor for proper processor operation 10 1 58 THERMTRIP O This pin indicates a thermal overload condition thermal trip The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating temperature to ensure that there are no false trips The processor will immediately stop all execution when the junction temperature exceeds approximately 135 C This is signaled to the system by the THERMTRIP pin Once activated the signal remains latched and the processor stopped until RESET goes active There is no hysteresis built into the thermal sensor itself Once the die temperature drops below the trip level a RESET pulse will reinitialize the processor and execution will continue at the reset vector If the temperature has not dropped below the trip level the processor will continue to drive THERMTRIP and remain stopped regardless of the state of RESET The system designer should not act
20. after reset operation of these pins as LINT 1 0 is the default configuration During active RESET the Pentium Ill Xeon processor at 600 MHz begins sampling the A20M IGNNE and LINT 1 0 values to determine the ratio of core clock frequency to bus clock frequency See Table 1 On the active to inactive transition of RESET the Pentium Ill Xeon processor at 600 MHz samples these signals and latches the frequency ratio internally System logic must then release these signals for normal operation 10 1 30 LOCK I O The LOCK signal indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of all Pentium Ill Xeon processor at 600 MHz system bus agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the Pentium lll Xeon processor at 600 MHz system bus it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the Pentium III Xeon processor at 600 MHz system bus throughout the bus locked operation and ensure the atomicity of lock 10 1 31 L2_SENSE On Pentium III Xeon cartridges L2_SENSE is routed from the edge of the connector pin B57 to the VL2 power plane It allows monitoring the delivery of VCC_L2 voltage at the L2 array device for the Pentium III Xeon processor This line is NOT specifie
21. area and interface agent selections will be determined by system issues in meeting the TPLATE requirements 0 400 2 135 2 658 2XD 1 904 10 INTERFACE AGENT DISPENSING AREAS 6 SEE TABLE FOR pi wy 2 THERMOCOUPLE ATTACH POINTS 2 015 Figure 19 Interface Agent Dispensing Areas and Thermal Plate Temperature Measurement Points NOTES 6 Interface agent suggestions ShinEtsu G749 or Thermoset TC330 Dispense volume adequate to ensure required minimum area of coverage when cooling solution is attached Areas A and B are suggested for processor core and OCVR products Recommended cooling solution mating surface flatness is no greater than 0 007 or flatter 7 Temperature of the entire thermal plate surface not to exceed 55 C for the Pentium IIl Xeon processor at 600 MHz Use any combination of interface agent cooling solution flatness condition etc to ensure this condition is met Thermocouple measurement locations are the expected high temperature locations without external heat source influence Ensure that external heat sources do not cause a violation of TPLATE requirements 56 mw eS oe cee we ewww Sw ew ew ee r n R 8 w THERMAL SPECIFICATIONS 6 2 3 MEASUREMENTS FOR THERMAL SPECIFICATIONS 6 2 3 1 Plate Temperature Measurement To ensure functional and reliable processor operation the processor s thermal plate temperature TPLATE must be maintained at or below the maximum TPLATE and at o
22. bus agents if routed properly Open drain output from ITP to the target system It will be held asserted for 100 ms capacitance needs to be small enough to recognize assert The pull up resistor should be picked to 1 meet VIL of target system and 2 meet specified rise time Poor routing can cause multiple clocking problems Should be routed to all components in the boundary scan chain3 Simulations should be run to determine the proper value for series termination or Bessel filter see figure 31 Operates synchronously with TCK Should be routed to all components in the boundary scan chains Simulations should be run to determine the proper value for series termination Operates synchronously with TCK If no power is applied the ITP will not drive any signals isolation provided using isolation gates Voltage applied is internally used to set AGTL threshold or reference at 2 3 Vr 76 AS r u ewe w mwn et vvv mu sw wns viv mw R Kr m w R R e INTEGRATION TOOLS Table 46 Debug Port Pinout Description and Requirements 1 Test data output signal Add 150 ohm pull up resistor Operates synchronously with TCK from last component in to VCC_TAP Each Pentium III XeonTM boundary scan chain of processor at 600 MHz hasa 25 MP cluster to ITP test Design pull ups to route around ohm driver output is read serially empty processor sockets so resistors are not in parallel DBINST Indicates to tar
23. each unit to dissipate its maximum power which can vary from unit to unit while at the same time maintaining the thermal plate at its maximum specified operating temperature Correctly used this feature permits an efficient thermal solution while preserving data integrity The thermal byte reading can be used in conjunction with the Thermal Reference Byte in the processor Information ROM Byte 9 of the processor Information ROM contains the address in the ROM of this byte described in more detail in Section 5 2 5 The thermal byte reading from the thermal sensor can be compared to this Thermal Reference Byte to provide an indication of the difference between the temperature of the processor core at the instant of the thermal byte reading and the temperature of the processor core under the steady state conditions of high power and maximum TPLATE specifications The nominal precision of the least significant bit of a thermal byte is 1 C Reading the thermal sensor is explained in Section 5 2 6 See the Pentium III Xeon processor SMBus Thermal Reference Guidelines for more details and further recommendations on the use of this feature in Pentium Ill Xeon processor at 600 MHz based systems The thermal sensor feature in the processor cannot be used to measure TpLATE The TpLATE specification in Chapter 6 must be met regardless of the reading of the processor s thermal sensor in order to ensure adequate cooling for the entire Pentium Ill Xeon p
24. event it will roll over to the first byte of the device Table 29 Write Byte SMBus Packet NE e B actress P Address w Address al A o ems o IE Table 29 diagrams the Write Byte packet This is effectively a Random Address Write function The device select address data offset address and write data are provided within the packet The device address is followed by a write flag The EEPROM device drives each of the three acknowledge pulses After the Write Byte packet is received the Scratch EEPROM device enters a timed writing mode during which it will not respond to further transfers This timed writing mode will be approximately 10 milliseconds in duration Table 30 Read Byte SMBus Packet Device Data Device Address Address Address 5 2 4Table 30 illustrates the Read Byte packet This is effectively a Random Address Read function This is actually two consecutive SMBus transfers an address write followed by a current address read from the same device In the address write portion both device address and data address are acknowledged by the EEPROM A second start condition then occurs followed by a receive byte read such as diagrammed above From the programming perspective this may be treated as two separate transfers THERMAL SENSO The Pentium Ill Xeon processor at 600 MHz thermal sensor provides a means of acquiring thermal data from the processor with an exceptional degree of precision The thermal
25. ewww Se oe we ew ee AA MECHANICAL SPECIFICATIONS A55 VSS Ground A63 VSS Ground PAS TAT VT Supply PAG AT VT Supply B Amy 73 mw eS oe cee we ewww Sw oe A ew ee AI INTEGRATION TOOLS 8 INTEGRATION TOOLS The integration tool set for Pentium III Xeon processor at 600 MHz system designs will include an In Target Probe ITP for program execution control register memory IO access and breakpoint control This tool provides functionality commonly associated with debuggers and emulators The ITP uses the on chip debug features of the Pentium Ill Xeon processor at 600 MHz to provide program execution control Use of the ITP will not affect the high speed operations of the processor signals ensuring the system can operate at full speed with the ITP attached This document describes the ITP as well as a number of technical issues that must be taken into account when including the ITP and logic analyzer interconnect tools in a debug strategy Although the tool description that follows is specific to early tools available from Intel similar tools may also be provided in the future by third party vendors Thus the tools mentioned should not be considered as Intel s tools but as debug tools in the generic sense In general the information in this chapter may be used as a basis for including integration tools in any Pentium Ill Xeon processor at 600 MHz based system design The logic analyzer interconnect tool keep out zones d
26. in systems that do not support the SMBus or only support a partial implementation The Z bit is the read write bit for the serial bus transaction The thermal sensor internally decodes 1 of 3 upper address patterns from the bus of the form 0011XXXZDb 1001XXXZb or O101XXXZb The devices addressing as implemented uses SA2 and SA1 and includes a Hi Z state for the SA2 address pin Therefore the thermal sensor supports 6 unique resulting address ranges To set the Hi Z state for SA2 the pin must be left floating The system should drive SA1 and SAO and will be pulled low if not driven by the 10K ohm pull down resistor on the processor substrate Attempting to drive either of these signals to a Hi Z state would cause ambiguity in the memory device address decode possibly resulting in the devices not responding thus timing out or hanging the SMBus As before the Z bit is the read write bit for the serial bus transaction Note that addresses of the form OOOOXXXXb are reserved and should not be generated by an SMBus master 51 mw eS oe cee we ewww Se oe A A e ee A PROCESSOR FEATURES The thermal sensor latches the SA1 and SA2 signals at power up System designers should ensure that these signals are at valid input levels before the thermal sensor powers up This should be done by pulling the pins to VCCsMB or VSS via a 1K ohm or smaller resistor Additionally SA2 may be left unconnected to achieve the tri s
27. interconnected in a rotating manner to other processors BR 3 0 pins Table 49 gives the interconnect between the processor and bus signals for a 2 way system Table 49 BR 3 0 Signals Rotating Interconnect 2 Way system Bus Signal Agent 0 Pins Agent 1 Pins BREQO BRO BR3 BREQ1 BR14 BRO During power up configuration the central agent must assert its BRO signal All symmetric agents sample their BR 3 0 pins on active to inactive transition of RESET The pin on which the agent samples an active level determines its agent ID All agents then configure their BREQ 3 0 signals to match the appropriate bus signal protocol as shown in Table 50 Table 50 Agent ID Configuration 10 1 14 BRO 1 0 BR 3 1 1 The Pentium Ill Xeon processor at 600 MHz uses a reduced set of signals The Pentium III Xeon processor at 600 MHz supports 2 Way configurations only On a Pentium III Xeon processor at 600 MHz cartridge only BRO BR1 and BR3 Bus Request pins drive the BREQ 3 0 signals on the system An assertion to BR2 has no effect since it is not seen at the processor The BR 3 and BR 1 0 pins are interconnected in a rotating manner to other processors BR 3 and BR 1 0 pins The following table gives the rotating interconnect between the processor and bus signals for 2 way systems 91 PENTIUMO III XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX Table 51 BR 3 and BR 1 0 Signals Ro
28. listing of all Pentium IIl Xeon processor at 600 MHz signals and tables that summarize the signals by direction output input and I O 10 1 Alphabetical Signals Reference This section provides an alphabetical listing of all Pentium IIl Xeon processor at 600 MHz signals 10 1 1 A 35 03 I O The A 35 3 Address signals define a amp 6 byte physical memory address space When ADS is active these pins transmit the address of a transaction when ADS is inactive these pins transmit transaction type information These signals must connect the appropriate pins of all agents on the Pentium III Xeon processor at 600 MHz system bus The A 35 24 signals are parity protected by the AP1 parity signal and the A 23 03 signals are parity protected by the APO parity signal On the active to inactive transition of RESET the processors sample the A 35 03 pins to determine their power on configuration See the Pentium II processor Developer s Manual for details 10 1 2 A20M 1 If the A2ZOM Address 20 Mask input signal is asserted the Pentium IIl Xeon processor at 600 MHz masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A2OM emulates the 8086 processor s address wrap around at the 1 Mbyte boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal fol
29. measurement the thermocouple should be attached at a 0 angle refer to Figure 20 e The thermocouple should be attached at a 90 angle if a heat sink is attached to the thermal plate and the heat sink covers the location specified for TPLATE measurement refer to Figure 21 e The hole size through the heat sink base to route the thermocouple wires out should be smaller than 0 150 in diameter Make sure there is no contact between the thermocouple cement and heat sink base This contact will affect the thermocouple reading RA A Figure 20 Technique for Measuring TrLate with 0 Angle Attachment 000899 000900 Figure 21 Technique for Measuring TrLate with 90 Angle Attachment 57 A bd we A III A Kee A A ew ee r n R 8 w MECHANICAL SPECIFICATIONS 7 MECHANICAL SPECIFICATIONS Pentium IlI Xeon processor at 600 MHz uses S E C cartridge package technology The S E C cartridge contains the processor core OCVR and other components The S E C cartridge package connects to the baseboard through an edge connector Mechanical specifications for the processor are given in this section See Section 1 1 1 for a complete terminology listing Figure 22 shows the thermal plate side view and the cover side view of the Pentium III Xeon processor at 600 MHz Figure 23 shows the Pentium Ill Xeon processor at 600 MHz S E C cartridge cooling solution attachment feature details on the thermal plate and depict package form fac
30. read write transaction is driven on the bus The system can generate a STPCLK while the processor is in the Auto HALT Power Down state The processor will generate a Stop Grant bus cycle when it enters the Stop Grant state from the HALT state If the processor enters the Stop Grant state from the Auto HALT state the STPCLK signal must be deasserted before any interrupts are serviced see below When the system deasserts the STPCLK interrupt signal the processor will return execution to the HALT state The processor will not generate a new HALT bus cycle when it re enters the HALT state from the Stop Grant state 39 msu eS oe cee we ewww Se re A A ew ee r n R 8 w PROCESSOR FEATURES HALT Instruction and HALT Bus Cycle Generated 2 Auto HALT Power Down State 1 Normal State BCLK running Snoops and interrupts allowed Ss Snoop STp Event LRS 6 Serviced Sertey Snoop Event Occurs INIT BINIT INTR NMI SMI RESET Normal execution STPCLK Asserted STPCLK De asserted Snoop Event Occurs 3 Stop Grant State BCLK running Snoops and interrupts allowed 4 HALT Grant Snoop State BCLK running Service snoops to caches Snoop Event Serviced SLP Asserted SLP De asserted Sleep State BCLK running No snoops or interrupts allowed P6CB757a P6CB757b Figure 15 Stop Clock State Machine 5 1 3 STOP GRANT STATE STATE 3 The
31. share these configuration signals The component used as the multiplexer must not have outputs that drive higher than 2 5V in order to meet the processor s 2 5V tolerant buffer specifications As shown in Figure 2 the pull up resistors between the multiplexer and the processor 1K ohm force a safe ratio into the processor in the event that the processor powers up before the multiplexer and or core logic This prevents the processor from ever seeing a ratio higher than the final ratio If the multiplexer were powered by VCC gt 5 a pull down resistor could be used on CRESET instead of the four pull up resistors between the multiplexer and the Pentium III Xeon processor at 600 MHz In this case the multiplexer must be designed such that the compatibility inputs are truly ignored as their state is unknown In any case the compatibility inputs to the multiplexer must meet the input specifications of the multiplexer This may require a level translation before the multiplexer inputs unless the inputs and the signals driving them are already compatible RESET CRESET Ratio Pins lt Final Ratio Final Ratio Compatibility 000917 Figure 1 Timing Diagram of Clock Ratio Signals 11 s es eS oe cee we ewww Se oe A A RR S KRSR ew eee r n R 8 w ELECTRICAL SPECIFICATIONS 1 4 A20M L Processors IGNNE LINT1 NMI LINTO INTR Set Ratio Figure 2 Logicall Schematic for Clock Ratio Pin Sharing NOTES 1
32. specifications on these devices from Intel PENTIUMO III XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Pentium Ill Xeon processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest
33. specified voltage regulator module VRM 8 3 Contact Intel for testing details of these parameters Not 100 tested Specified by design characterization 5 12V Pentium III Xeon processor version is to be operated by 5V or 12V 5V and 12V are specified at 5 This parameter includes both static noise amp ripple and transient tolerances at the edge fingers VCC_SMB must be connected to 3 3V power supply even if the SMBus features are not used in order for the Pentium III Xeon processor at 600 MHz to function properly 17 s es eS oe cee we ewww Se oe ee ew ee r n R 8 w ELECTRICAL SPECIFICATIONS Table 6 Current Specifications 1 10 lec_core 600 MHz O 2 74V VCC_CORE 667 MHz 733 MHz 800 MHz 866 MHz 933 MHz 1 GHz lec_core 600 MHz O 4 75V VCC_CORE 667 MHz 733 MHz 800 MHz 866 MHz 933 MHz 1 GHz Icc_core 600 MHz 11 4V VC_CORE 667 MHz 733 MHz 800 MHz 866 MHz 933 MHz Icc_core ICC Stop Grant for processor core at ICC Sleep for processor core at Dicccore dt Current slew rate DICCV TT at Termination current slew rate AS r R s sew r p m m r R R e K S Pus seen sw ew ee r n R R e ELECTRICAL SPECIFICATIONS Table 6 Current Specifications 1 10 O Seo parameter o ry max nt nores 3 SH A A al Ga supply ee ee upply NOTES ty Unless otherwise noted all specifications in this table apply to all processor frequencies FMB is a suggested design guide
34. the VID_CORE lines will be open on the cartridge w The VID pins should be pulled up to a TTL compatible level with external resistors to the power source of the regulator only if required by the regulator or external logic monitoring the VID 4 0 signals The power source chosen to drive pull up VIDs must be guaranteed to be stable whenever the supply to the voltage regulator is non zero and the OCVR is enabled An invalid VID while the output is coming up could lead to and incorrect voltage above VCC_CORE max This will prevent the possibility of the processor supply going above VCC_CORE in the event of a failure in the supply for the VID lines In the case of a DC to DC converter this can be accomplished by using the input voltage to the converter for the VID line pull ups A resistor of greater than or equal to 10K ohms may be used to connect the VID signals to the converter input See the VRM 8 3 DC DC Converter Design Guidelines for further information 13 s es eS oe cee we A Sw o Kee K A RR S KRSR ew eee ANI ELECTRICAL SPECIFICATIONS 3 6 System Bus Unused Pins and Test Pins Unless otherwise specified All RESERVED_XXX pins must remain unconnected Note that pins that are newly marked as RESERVED in this document may be tied to a power rail in existing baseboards Connection of RESERVED_XXX pins to VCC_CORE VSS or VTT lo each other or to any other signal can result in component malfunction or incompatibility with future members o
35. the need of high precision regulation from the flexible baseboard Note that the Pentium IIl Xeon processor at 600 MHz does not require a dedicated L2 supply and that VID logic will assume L2 supply is not required Please refer to the VRM 8 3 Guidelines for details A 2 8V Pentium IIl Xeon processor relies on the VID identification pins for the VCC_CORE required voltage level ONLY and does not require a separate L2 voltage supply A 5 12V Pentium III Xeon processor does not require a VRM and therefore the VID_CORE lines will be open on the cartridge requesting NO CPU For signal integrity improvement and clean power distribution within the S E C package the Pentium Ill Xeon processor at 600 MHz has 65 VCC power and 55 V SS ground inputs see section 7 3 for a complete edge finger signal listing The 65 VCC pins are further divided to provide the different voltage levels to the components VCC_CORE inputs for the processor core account for 35 of the VCC pins while 8 VTT inputs 1 5V are used to provide an AGTL termination voltage to the processor One VCC_SMB pin is provided for use by the SMBus and one VCC_TAP The VCC_SMB VCC_TAP and VCC_CORE must remain electrically separated from each other VCC_SMB must be connected to a 3 3V power supply even if the SMBus features are not used in order for the Pentium Ill Xeon processor at 600 MHz to function properly On the baseboard all VCC_CORE pins must be connected t
36. the voltage input seen at the input of the OCVR device which may be 2 8V for one product version or 5V or 12V for another product version 3 Please contact Intel for storage requirements in excess of one year a aii elo ES 3 10 Processor DC Specifications The voltage and current specifications provided Table 6 are defined at the processor edge fingers The processor signal DC specifications in Tables 7 8 and 9 are defined at the Pentium III Xeon processor at 600 MHz core Each signal trace between the processor edge finger and the processor core carries a small amount of current and has a finite resistance The current produces a voltage drop between the processor edge finger and the core Simulations should therefore be run versus these specifications to the processor core See Chapter 1 for the processor edge finger signal definitions and Table 3 for the signal grouping Most of the signals on the Pentium III Xeon processor at 600 MHz system bus are in the AGTL signal group These signals are specified to be terminated to VTT The DC specifications for these signals are listed in Table 7 To ease connection with other devices the Clock CMOS APIC SMBus and TAP signals are designed to interface at non AGTL levels Pentium Ill Xeon processor at 600 MHz contain a voltage clamp device on the cartridge substrate between the core and edge fingers This device clamps the 2 5V level CMOS TAP and APIC signals to 1 5V levels
37. timings specified in this section are defined at the Pentium Ill Xeon processor at 600 MHz core pins unless otherwise noted Timings are tested at the processor core during manufacturing NOTE Timing specifications T45 T49 are reserved for future use All system bus AC specifications for the AGTL signal group are relative to the rising edge of the BCLK input All AGTL timings are referenced to 2 3 V TT for both 0 and 1 logic levels unless otherwise specified 22 AS r u ewe w mwn et www m sw wns riv ew ee w R e ELECTRICAL SPECIFICATIONS Table 12 System Bus AC Specifications Clock at the processor Ea Pins 1 2 3 System Bus Frequency 132 29 125 NOTES 1 2 Unless otherwise noted all specifications in this table apply to all Pentium III Xeon processor at 600 MHz frequencies All AC timings for the AGTL signals are referenced to the BCLK rising edge at 1 25V at the processor core pin All AGTL signal timings address bus data bus etc are referenced at 1 00V at the processor core pins All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1 25V at the processor core pin All CMOS signal timings compatibility signals etc are referenced at 1 25V at the processor core pins The internal core clock frequency is derived from the processor system bus clock The system bus clock to core clock ratio is determined during initialization as described in 6 2 Table 1 shows the s
38. to the EEPROMs is possible Send Byte loads an address into the memory device that is used for subsequent access Send Byte does not change the contents of the EEPROM just the address pointer within it See Table 27 and explanation below Receive Byte gets a byte of data from the memory device It uses an address already loaded into the EEPROM device and returns the byte at that address Repetitive use of Receive Byte to access an address range is possible See Table 28 and explanation below Write Byte transfers both an address and data byte into the memory device It is a stand alone write cycle See Table 29 Read Byte transfers an address and gets a byte of data from the memory device It is a stand alone read cycle See Table 30 Both ROMs respond to SMBus packet types Send Byte Receive Byte and Read Byte The Scratch EEPROM additionally responds to the packet type Write Byte The EEPROM devices perform sequential read and page write modes that are not covered by the SMBus specification However by use of the four transfers described above all transfer requirements to these devices can be achieved NOTE In Tables 27 30 below S indicates a start condition SDA falling while SCK high P indicates a stop condition SDA rising while SCK high R W indicates a read write not signal 1 read 0 write A indicates an acknowledge signal 0 acknowledge 1 not acknowledge The shaded portions of the following Tables indicate th
39. 1 03 Heat sink Height above baseboard 0 485 Fatales Jos Heat sink Total Height at Base see front view Po 42385 Heat sink Width see front view aa ee 9 2 2 BOXED PROCESSOR HEATSINK WEIGHT The boxed processor heat sink will not weigh more than 350 grams without auxiliary fan 9 2 3 BOXED PROCESSOR RETENTION MECHANISM The boxed Pentium Ill Xeon processor at 600 MHz requires a retention mechanism that supports and secures the Single Edge Contact Cartridge S E C C in the 330 contact slot connector An S E C C retention mechanism is not provided with the boxed processor Baseboards designed for use by system integrators should include a retention mechanism and appropriate installation instructions The boxed Pentium IIl Xeon processor at 600 MHz does not require additional heat sink supports Heat sink supports are not shipped with the boxed Pentium III Xeon processor at 600 MHz 84 mw eS oe cee we ewww Se oe A A m R Ker ee AS BOXED PROCESSOR SPECIFICATIONS 9 3 Thermal Specifications This section describes the cooling requirements of the heat sink solution utilized by the boxed processor 9 3 1 Boxed Processor Cooling Requirements The boxed processor passive heat sink requires airflow horizontally across the heat sink to cool the processor The boxed processor heat sink will keep the processor thermal plate temperature Tpiate within the specification provided adequate airflow is directed into the sy
40. 1 24 HV_EN O 10 1 25 IERR 0O 10 1 26 IGNNE 1 q 10 1 27 INIT D n 10 1 28 INTR see LINT O 10 1 29 LINT 1 0 Decio 10 1 30 LOCK 1 0 n 10 1 31 L2_SENSE 10 1 32 OCVR_EN D 10 1 33 OCVR_OK O coe a S R q WOE SAIN MAD Ni adi 8 Oo N Co Co Oo Oo Co Co PENTIUMO Ill XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache A O AR Re VEROS RON ARA RN NN ds VOS EO dt arto eo 10 1 38 PREQH IIT VO O a N TO TAOP WIG ODDIE NANI ARE UNE eos eee oar atl AURA E 10 141 REQ A4 O rO VO TAD RESET oo ex ccna ahd oe eee EA E 10 143 TPH roce lets TO TAA RA A e cdas 10 145 IND H ALA AN RAN le RR NAAA e DOT AG SAL 2ST E NS E E EU AE SELPSBO O RETER OD a es AU ca elie ale e ll a ELE E LIE En OR ARO ar OR ose a eee fis hah cantar SRA NA VOTA A A ese adios 101 50 SMB HI tags ccns cowie VOT SE OMB DA e id ATTE oes ee E E ee A O tte ss 10 1 53 STPCLK 1 G 10 1 54 TCK 1 1 HOT STII AIN NARRAR NN incite R ME 1 HOE DO O ad a see ec as ak ioe dol tes eee esse 1 10 157 TEST 3 5 A A A lora nado 1 VOD O sa ead bea de ados ata 1 A ii 1 A a o 1 TD ET HRS LI O RA ARAN IAE EN CAER IR 1 10 1 62 VID_L2 4 0 VID CORE 4 0 O aman 10 1 63 VIN SENSE nrnna 10 1 64 WPL escoria 10 2 SIGNAL SUMMARIES PENTIUMO III XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache 1 INTRODUCTION The Pentium IlI Xeon processor at 600 MHz like the Pentium Pro
41. 1 5 V or 2 5 V tolerant buffers if the potential is large enough i e if the overshoot undershoot is great enough Determining the impact of an overshoot undershoot condition requires knowledge of the Magnitude the Pulse Duration and the Activity Factor 32 s es eS nn rr r R s sem r p m m r R K e KR e KRSR Kee K R g Kee RR S KRSR m R Ker ANI SIGNAL QUALITY 4 2 2 1 Overshoot Undershoot Magnitude Overshoot magnitude describes the maximum potential difference between a signal and its reference voltage level Vss Undershoot Magnitude describes the maximum potential difference between a signal and Vr undershoot While overshoot can be measured relative to VSS using one probe probe on signal and ground lead on VSS Undershoot must be measured relative to Vir This can be accomplished by simultaneously measuring the V tr plane while measuring the signal undershoot The true waveform can then be calculated by the oscilloscope itself or by the following oscilloscope data file analysis Converted Undershoot Waveform Vr Signal Note This Converted Undershoot Waveform appears as a positive overshoot signal Note Overshoot rising edge and Undershoot falling edge conditions are separate and their impact must be determined independently After the conversion the Overshoot Undershoot Specifications can be applied to the Converted Undershoot Waveform using the Overshoot Undershoot Magnitude and Pulse Duration Specifications in Table 22
42. 3 or equivalent 000888 Figure 40 Boxed Processor s Standard Fan Heat sink Power Cable Connector Description Table 48 Fan Heatsink Power and Signal Specifications 12V 12 volt fan power supply IC Fan current draw SENSE SENSE frequency baseboard should pull 2 pulses per this pin up to appropriate Vcc with resistor typically fan revolution 10 to 12 KO 9 3 2 3 Thermal evaluation for auxiliary fan Given the complex and unique nature of baseboard layouts and the special chassis required to support them thermal performance may vary greatly with each baseboard chassis combination Baseboard manufacturers must evaluate and recommend effective thermal solutions for their specific designs particularly designs that are proprietary or have non standard layouts Such thermal solutions must take all system components into account The power requirements of all processors that will be supported by the baseboard should be accommodated The boxed Pentium IIl Xeon processor at 600 MHz is designed to provide a flexible cooling solution by incorporating features by which an auxiliary fan may be attached Should the system thermal evaluation warrant the requirement for an auxiliary fan an auxiliary fan must be included with the baseboard to allow the thermal requirements of the system to be met 88 PENTIUMO III XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX 10 APPENDIX This appendix provides an alphabetical
43. 3 KEEP OUT CONCERNS Two keep out concerns need to be taken into account when designing a system that will support an ITP First system designers need to be aware that in order for the ITP cabling to egress the system under test they must either remove the skins of the system under test or when this is not possible design an aperture into the system Secondly keep out regions will be required around the debug port connector See Figure 30 for the keep out region required for the Pentium III Xeon processor at 600 MHz system designs OMPONEINT KEJEPOUT ARDA SHE OTHER VIEWS TO N DOF INE CONPONENT 419 284 100 TYP i HEIGHT RESTRICTIONS TOP VIEW OF DEBUG PORT CONNECTOR MPONENT KEEP OUT AREA Figure 30 Debug Port Connector Keep Out Region 8 1 4 ADDITIONAL INTEGRATION TOOL MECHANICAL KEEP OUTS Please contact your Integration Tools vendor for any additional mechanical keep out restrictions for the Pentium III Xeon processor at 600 MHz system design 75 8 1 5 DEBUG PORT SIGNAL DESCRIPTIONS Table 46 describes the debug port signals and provides the pin assignment mew ee ANS INTEGRATION TOOLS Table 46 Debug Port Pinout Description and Requirements 1 RESET DBRESET Reset signal from MP cluster to ITP Allows ITP to reset entire target system The TAP Test Access Port clock from ITP to MP cluster Test mode select signal from ITP to MP cluster controls the TAP finite state machine T
44. AND SCRATCH EEPROM SUPPORTED SMBUS SAC TIONS A a EE EA tates THERMAL SENS OR cosida V A AREE ENEKE as THERMAL SENSOR SUPPORTED SMBUS TRANSACTIONS THERMAL SENSOR REGISTERS eee va SMBUS Device Address ii Asi 6 THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS cssssssssssssssssssessesssssessesnsesen 6 1 EHERMAL SPECIFICATIONS ie sisseessessssacsesadenesnsucsonscvescaeedasestncduaaacshacencregevaveveessdiessbis osha ceseyepesanveteasedegnandaanale 1 POWER DISSIPATION essen eee 2 PLATE FLATNESS SPECIFICATION PROCESSOR THERMAL ANALYSIS eee 1 2 NNN ARARNAR MYN L a Gn 6 NNNNANt AS LAK Ea HAL THERMAL SOLUTION PERFORMANCE 6 6 6 2 6 6 3 PENTIUMO Ill XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache 6 2 3 MEASUREMENTS FOR THERMAL SPECIFICATIONS c ssssssssssssssssseseseseseseseseseseseseseseseseaes 57 7 MECHANICAL SPECIFICATIONS scssssssssssseeees RO A ALE S i ci 7 2 CARTRIDGE TO CONNECTOR MATING DETAILS AE deis 7 3 SUBSTRATE EDGE FINGER SIGNAL LISTING sese sese eee eee 8 INTEGRATION TOOLG ccssssssscssssssssssssessssnssnsesensoes A ean eee ala E ANA 8 1 1 PRIMARY FUNCTION ocn 1 2 DEBUG PORT CONNECTOR DESCRIPTION E a EES KEEP OUT CON CERN E ad 1 4 ADDITIONAL INTEGRATION TOOL MECHANICAL KEEP OUTS 1 5 DEBUG PORT SIGNAL DESCRIPTIO NS r 1 6 a 1 7 DEBUG PORT SIGNAL NOTES Using the TAP to Communicate to the processor LOGIC ANALYZER INT
45. DI TDO and TMS These timings correspond to the response of these signals due to TAP operations During Debug Port operation use the normal specified timings rather than the TAP signal timings 26 s es eS oe cee we ewww Se oe A A RR S KRSR ew eee r n R 8 w ELECTRICAL SPECIFICATIONS Table 18 SMBus Signal Group AC Specifications at the Edge Fingers el Fave Figure 4 T59 Bus Free Time c TT A NOTES 1 Minimum time allowed between request cycles NOTES 1 OCVR_OK output with 5pf load and 10K ohm external pull up to 3 3V Figure 3 through Figure 10 are to be used in conjunction with the DC specification and AC timings tables Tr T5 T25 T34 Rise Time Tt T6 T26 T36 Fall Time Th T3 T23 T32 High Time Ti T4 T24 T33 Low Time Tp T1 T22 T31 BCLK PICCLK TCK Period P6CB761z Figure3 BCLK PICCLK TCK Generic Clock Waveform 27 AS r u ewe w mwn R e K S www seen sw wns riv ew ee dd ELECTRICAL SPECIFICATIONS SCLK T T54 T T55 Th T52 T T53 SMBUSCLK Figure 4 SMBCLK Clock Waveform Clock Signal Tpw Tx T7 T29 Valid Delay Taw 114 T15 Pulse Wdith V 2 3 V TT for GTL signal group 1 25V for CMOS and APIC signal groups Figure 5 Valid Delay Timings T8 T27 Setup Time T9 T28 Hold Time 2 3 Vr for the GTL signal group 1 25V for the CMOS and APIC signal groups 1 25V for BCLK and PICCLK 000763
46. ERCONNECT LAI AND TRACE CAPTURE TOOL CONSIDER ATIONS 81 2 1 LAI and Trace Capture Tool System Design Consideration 81 8 2 1 LAI and Trace Capture tool Mechanical Keep QUIS sss essen 8l 9 BOXED PROCESSOR SPECIFICATIONS uuu sssssssssscssssssssssssssssessssesessssessssssesssssssessnsesessssesesssssssessseseess OZ 9 INTRODUCTION aida 9 2 MECHANICAL SPECIFICATIONS cccsccsssscsesscseesesecseeseseceesesaeeeeseseeesseseesees 9 2 1 BOXED PROCESSOR HEATSINK DIMENSIONS sees 9 2 2 BOXED PROCESSOR HEATSINK WEIGHT aes 9 2 3 BOXED PROCESSOR RETENTION MECHANISM 9 3 THERMAL SPECIFIC ATIONS asees eee 9 3 1 Boxed Processor Cooling Requirements 9 3 2 Boxed Processor Passive Heatsink Performance 9 3 2 Optional auxiliary fan drrachnmient sese WITT O AAA II 10 1 ALPHABETICAL SIGNALS REFERENCE 10 1 1 A 35 03 1 0 10 1 2 A20M D oan 10 1 3 ADS I O H 10 1 4 AERR I O cocccccccccnnnso 10 1 5 AP 1 0 EO 10 1 6 BCLK I ts 10 1 7 BERR I O 10 1 8 BINIT I O Dee 10 1 9 BNR I O cocos 10 1 10 BP 3 2 1 0 10 1 11 BPM 1 0 1 0 ve 10 1 12 BPRI nn 10 1 13 BRO I O BR 3 1 1 10 1 14 BRO I O BR 3 1 1 10 1 15 CORE_AN_SENSE 0 10 1 16 D 63 00 1 0 co q 10 1 17 DBSY W O conc 10 1 18 DEFER I cose 10 1 19 DEP 7 0 1 0 10 1 20 DRDY 1 0 10 1 21 FERR O ves T 10 1 22 FLUSH TH 10 1 23 HIT I O HITM 1 0 10
47. FMB specification is applicable to 2 8V OCVR processors where a VRM is used as the power source Table 7 AGTL Signal S a DC a at the TA E Smeal Parameter Input Low Voltage a 150 2 3 E a 2V V input High Voltage High Voltage 2 3 213 Vir 02V 0 x vr 147 4 7 nMOS On Resistance 1887 Output High Voltage Tri state a Leakage current for the Inputs 15 3 Outputs and I O NOTES 1 Processor core parameter correlated into a 50 ohm resistor to a VTT of 1 5V for Pentium III Xeon processor at 600 MHz 2 O lt Vin lt 1 5 3 3 0 lt Vout lt 2 5 4 The processor core drives high for only one clock cycle It then drives low or tri states its outputs VTT is specified in Table 5 5 Not 100 tested Specified by design characterization 6 This RON specification corresponds to a VOL_MAX of 0 3V when taken into an effective 50 ohm load to VTT of 1 5V for Pentium III Xeon processor at 600 MHz 7 Vil Vih are not guaranteed with respect to AC parameters 8 Specified under no load conditions at an l V operating point of zero current and V VTT conditions 19 s es eS oe cee we A Sw o Kee K A RR S KRSR ew eee ANI ELECTRICAL SPECIFICATIONS Table 8 CMOS TAP Clock and APIC Signal Groups DC Specifications at the processor edge fingers Vit Vin Input High Voltage 1 7 2 625 V 2 5V 5 maximum 7 PICCLK amp 2 5V 5 maximum 4 5 PWRGD only Output High Voltage All outputs are open drain to 2 5V 5
48. H Tras tw ECN T H dS Prove tw sox TT SSCS we om IEC ise CS E Table 55 I O Signals Single Driver Pw o o osos os tw ocx OO oo O w aas tw ee eno oseo serso amn ene A 35 03 BRO BP 3 2 BPM 1 0 DBSY DEP 7 0 sas tw sox acne wsos pjesooy Low BCLK AGTL I O DRDY Low Low Low TBD Low Low Low Low Low Low Low Low Low 102 PENTIUMO III XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX Table 55 I O Signals Single Driver Name Active Level Signal Group Qualified RP Low BCLK AGTL VO ADS ADS 1 Table 56 I O Signals Multiple Driver C heme seg cock T StnalGroup Tans oaz 103
49. Ill Xeon processor at 600 MHz system bus agents 10 1 18 DEFER I The DEFER signal is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of all Pentium III Xeon processor at 600 MHz system bus agents 10 1 19 DEP 7 0 1 0 The DEP 7 0 Data Bus ECC Protection signals provide optional ECC protection for the data bus They are driven by the agent responsible for driving D 63 00 and must connect the appropriate pins of all Pentium Ill Xeon processor at 600 MHz system bus agents which use them The DEP 7 0 signals are enabled or disabled for ECC protection during power on configuration 10 1 20 DRDY 1 0 The DRDY Data Ready signal is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi cycle data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of all Pentium Ill Xeon processor at 600 MHz system bus agents 92 PENTIUMO III XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX 10 1 21 FERR O The FERR Floating point Error signal is asserted when the processor detects an unmasked floating point error FERR is similar to the ERROR signal on the Intel887 coprocessor and is included for compatibility with systems using DOS type floating point error reporting 10 1 22 FLUSH 1 When the FLUSH input s
50. O D Cartridge VOC asa Da AGTL VO EEN VSS Ground B55 D 52 AGTL I O ass VN SENSE emos es voc cone Garba VOC cmosro A59 D 45 AGTL VO B59 D M AGTL UO A63 VSS Ground B63 D 36 AGTL I O A67 D 33 AGTL I O B67 VCC_CORE Cartridge VCC A71 D 30 AGTL UO B71 D 28 AGTL UO AGTL TO Cartridge VOC A74 DA 24 AGTL VO B74 D 26 AGTL UO aeo i REL B76 __ Cars voo A78 VSS Ground B78 D 19 AGTL I O A83 RESERVED A83 DO NOT B83 CORE_AN_VSENSE OCVR Analog Output CONNECT vss Ground A87 VSS Ground B87 D 15 AGTL I O A91 D 08 AGTL I O B91 VCC_CORE Cartridge VCC AGTL VO AGTL VO __ DA O3 AGTL VO VCC CORE Cartridge VCC D 01 AGTL I O D 02 AGTL UO ss samm mr p s w w p m m r R R wee m Kee ew ot om mms MECHANICAL Table 44 Signal Listing in Order by Pin Number mew ee we SPECIFICATIONS Signal Buffer Type DADO AGTL I O A97 BCLK System Bus Clock B97 VCC_CORE Cartridge VCC B99 NC gt AAN A100 BERR AGTL I O B100 VCC_CORE Cartridge VCC A101 AR 33 AGTL VO B101 ART AGTL I O A104 A 30 AGTL VO B104 A 29 AGTL VO A107 A 27 AGTL UO B107 AH 24 AGTL UO A109 AF22 AGIL VO A110 AR 23 AGTL VO A112 ARNO AGIL VO A115 A 16 AGTL UO A119 VSS Ground A122 VSS Ground A123 AR O9 AGTL VO A124 A 04 AGTL VO A125 B111 A 21 B115 VCC_L2 B119 AT 2 B109 VCC_L2 L2 C
51. Outputs Valid Delay T42 All Non Test Outputs Float Delay Figure 9 Test Timings Boundary Scan Ty T36 TRST Pulse Width Figure 10 Test Reset Timings 30 s es eS nn rr r R s sem r p m m r R K e KR e KRSR Kee K R g Kee RR S KRSR m R Ker ANI SIGNAL QUALITY 4 SIGNAL QUALITY Signals driven on the Pentium III Xeon processor at 600 MHz system bus should meet signal quality specifications to ensure that the components read data properly and to ensure that incoming signals do not affect the long term reliability of the component Specifications are provided for simulation at the processor core Meeting the specifications at the processor core in Table 20 through Table 25 ensures that signal quality effects will not adversely affect processor operation 4 1 Bus Clock Signal Quality Specifications Table 20 describes the signal quality specifications at the processor core pad for the Pentium III Xeon processor at 600 MHz system bus clock BCLK signal Figure 11 shows the signal quality waveform for the system bus clock at the processor core pads Table 20 BCLK Signal Quality Specifications for Simulation at the processor Core 1 e i n Mom Mox Umt Las Las V3 Vin Absolute Voltage Range 20 7 V4 Rising Edge Ringback Laan V5 Falling Edge Ringback Poe NOTES 1 Unless otherwise noted all specifications in this table apply to all Pentium III Xeon processor at 600 MHz frequencies 2 The ris
52. PICD 1 0 Valid Delay 1 5 12 0 nS Figure 5 Falling Edge NOTES 1 These specifications are tested during manufacturing 2 Referenced to PICCLK rising edge 3 For open drain signals valid delay is synonymous with float delay 4 Valid delay timings for these signals are specified to 2 5V 25 mew oe cee we A Sw o Kee K A RR S KRSR ew eee ANI ELECTRICAL SPECIFICATIONS Table 17 System Bus AC Specifications TAP Connection at the processor Core 1 T30 TCK Frequency 16867 MHz 7 PE T32 TOK High Time 250 ns Figures 1 7V 2 T33 TOK Low Time 250 nS 1 Figures 0 7V 2 T34 TCK Rise Time f 50 ns Figures 0 7V 17V 23 T35 TOK Fall Time 50o ns Figures 1 7V 0 7v 2 3 T39 TDO Valid Delay 5 6 T40 TDO Float Delay T41 All Non Test Outputs Valid Delay T42 All Non Test Inputs Setup 25 0 nS Figure 9 2 5 7 8 Time T43 All Non Test Inputs Setup 5 0 nS Figure 9 4 7 8 Time T44 All Non Test Inputs Hold 13 0 AAA 4 7 8 Time NOTES NOOR WON gt Unless otherwise noted these specifications are tested during manufacturing Not 100 tested Specified by design characterization 1 nS can be added to the maximum TCK rise and fall times for every 1 MHz below 16 667 MHz Referenced to TCK rising edge Referenced to TCK falling edge Valid delay timing for this signal is specified to 2 5V Non Test Outputs and Inputs are the normal output or input signals besides TCK TRST T
53. Product Features Binary compatible with applications running on previous members of the Intel microprocessor family Optimized for 32 bit applications running on advanced 32 bit operating systems Dynamic Independent Bus architecture separate dedicated external 133 MHz System Bus and dedicated internal cache bus operating at full processor core speed Power Management capabilities System Management mode Multiple low power states Single Edge Contact S E C cartridge packaging the S E C cartridge delivers high performance processing and bus technology to mid range to PENTIUMO Ill XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache Datasheet Supports the SC330 Interface 133 MHz system bus speeds data transfer between the processor and the system Integrated high performance 16KB instruction and 16KB data non blocking level one cache Available in 256KB unified non blocking 8 way set associative level two cache Enables systems which are scaleable up to two processors and 64GB of physical memory SMBus interface to advanced manageability features Streaming SIMD Extensions for enhanced video sound and 3D performance high end servers and workstations The Intel Pentium Ill Xeon Processor at 600 MHz to 1 GHz with 256KB L2 Cache is designed for mid range to high end servers and workstations and is binary compatible with previous 32 bit Intel Architecture processors The Intel Pentium lll Xeon
54. RDY2 26 PRDY2 signal from ITP to Terminate signal properly at Connected to high speed P2 the debug port comparator biased at 2 3 of the Debug port must be at the end level found at the POWERON pin of the signal trace on the ITP buffer board Additional load does not change timing calculations for the processor bus agents if routed properly PREQ3 PREQ3 R from ITP to Add 150 to 330 ohm pull up resistor to VCC_TAP PRDY3 PRDY3 signal from ITP to Terminate signal properly at Connected to high speed P3 the debug port comparator biased at 2 3 of the Debug port must be at the end level found at the POWERON pin of the signal trace on the ITP buffer board Additional load does not change timing calculations for the processor bus agents if routed properly BCLK 29 Bus clock from the MP Use a separate driver to drive A separate driver should be used to cluster signal to the debug port avoid loading issues associated with having the ITP either installed or not Must be connected to support installed future steppings of the 77 msu Sm RRR oe cee we ewww Se oe K o g Kee RR S KRSR m R ee AI INTEGRATION TOOLS Table 46 Debug Port Pinout Description and Requirements 1 Pentium IIl Xeon processor at 600 MHz Signal ground Connect all pins to signal NOTES 1 Resistor values with preceding them can vary from the specified value use resistor as close as possible to the value specified
55. ROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX 10 1 36 PICD 1 0 1 0 The PICD 1 0 APIC Data signals are used for bi directional serial message passing on the APIC bus and must connect the appropriate pins of all processors and core logic or I O APIC components on the APIC bus 10 1 37 PRDY O The PRDY Probe Ready signal is a processor output used by debug tools to determine processor debug readiness 10 1 38 PREQ I The PREQ Probe Request signal is used by debug tools to request debug operation of the processors 10 1 39 PWREN 1 0 1 These 2 pins are tied directly together on the processor They can be used to detect processor presence by applying a voltage to one pin and observing it at the other See 3 9 for the maximum rating for this signal 10 1 40 PWRGOOD 1 The Power Good signal is a 2 5V tolerant processor input The processor requires this signal to be a clean indication that the clocks and power supplies VCC_CORE VCC_L2 VCC_TAP VCC_SMB VCCo 5 are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high 2 5V state Figure 41 illustrates the relationship of PWRGD to other system signals PWRGD can be driven inactive at any time but clocks and power must again be s
56. Stop Grant state on the Pentium Ill Xeon processor at 600 MHz is entered when the STPCLK signal is asserted The Pentium Ill Xeon processor at 600 MHz will issue a Stop Grant Transaction Cycle Exit latency from this mode is 10 BLCK periods after the STPCLK signal is deasserted Since the AGTL signal pins receive power from the system bus these pins should not be driven allowing the level to return to VTT for minimum power drawn by the termination resistors in this state In addition all other input pins on the system bus should be driven to the inactive state BINIT will not be serviced while the processor is in Stop Grant state The event will be latched and can be serviced by software upon exit from Stop Grant state FLUSH will not be serviced during Stop Grant state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the deassertion of the STPCLK signal A transition to the HALT Grant Snoop state will occur when the processor detects a snoop phase on the system bus A transition to the Sleep state will occur with the assertion of the SLP signal While in the Stop Grant State all other interrupts will be latched by the Pentium Ill Xeon processor at 600 MHZ and only serviced when the processor returns to the Normal State 5 1 4 HALT GRANT SNOOP STATE STATE 4 The Pentium III Xeon processor at 600 MHz
57. TRST signals from the debug port should be isolated from the system signals In general no signals should be left floating Thus signals going from the debug port to the processor system should not be left floating If they are left floating there may be problems when the ITP is not plugged into the connector 8 1 6 2 Signal Note DBRESET 78 mw eS oe cee we ewww Sw oe A ew ee AI INTEGRATION TOOLS The DBRESET output signal from the ITP is an open drain with about 5 ohms of RDS The usual implementation is to connect it to the PWROK open drain signal on the PClset components as an OR input to initiate a system reset In order for the DBRESET signal to work properly it must actually reset the entire target system The signal should be pulled up Intel recommends a 240 ohm resistor but system designers will need to fine tune specific system designs to meet two considerations 1 the signal must be able to meet VIL of the system and 2 it must allow the signal to meet the specified rise time When asserted by the ITP the DBRESET signal will remain asserted for 100 mS A large capacitance should not be present on this signal as it may prevent a full charge from building up within 100 mS 8 1 6 3 Signal Note TDO and TDI The TDO signal of each processor has a 2 5V Tolerant open drain driver The TDI signal of each processor contains a 150 ohm pull up to VCCraP When connecting one Pentium III Xeon processor at 600 MHz to the next o
58. TY 4 1 BUS CLOCK SIGNAL QUALITY SPECIFICATIONS ccccsssscssssssscsesscsecsesecsesseseceesssaeceesesaesesseseesesaeseesesacseeaesseessaes 4 2 AGTL SIGNAL QUALITY SPECIFICATIONG 4 2 1 AGTL Ringback Tolerance Specifications 4 2 2 AGTL OVERSHOOT UNDERSHOOT GUIDELINES 3 NON GTL SIGNAL QUALITY SPRCIFICATIONSR 4 3 1 2 5V Signal Overshoot Undershoot Guidelines sss eee 4 3 2 BCLK Overshoot Undershoot Guidelines and Specifications feo Measuring BCLK Overshoot Undershoot scsccsecesececeserererererereteseens 4 3 4 3 5 1 2 3 3 3 1 3 3 2 2 i A 3 3 SYSTEM BUS AGTL DECOUPLING QQ cece 3 3 4 2 3 5 3 6 3 7 3 3 8 3 9 3 3 3 1 1 1 gt 4 N 5V TOLERANT BUFFER RINGBACK SPECIFICATION 2 5V TOLERANT BUFFER SETTLING LIMIT GUIDELINE PROCESSOR FEATURES eoononccccaononooononsocononoroncononononcocononcrnononononconononenonononcrnononenencoononorsononononcononononiorononorsrnononos 5 1 Low POWER STATES AND CLOCK CONTROL 5 1 1 NORMAL STATE STATE 1 2 AUTO HALT POWER DOWN STATE STATE 2 0 4 3 STOP GRANT STATE STATES eee 4 HALT GRANT SNOOP STATE STATE 4 Ro 6 Ln SLEEP STATE STATE 5 fs CLOCK CONTR a ROE i ase eNe E R SYSTEM MANAGEMENT BUS SMBUS INTERFACE ccoccocccnninninninnos PROCESSOR INFORMATION KOM SCRATCH EEPROM ssctecsssccesvessescavenssattencascsesvneeestusuavets OREORE REE RE PROCESSOR INFORMATION ROM
59. V Pentium lll Xeon processor ERRA CMOS Output A17 IGNNE CMOS Input B133 LOCK AGTL I O B3 OCVROK Open Drain Output A26 OCVR_EN CMOS INPUT B36 PRDY AGTL Output A21 PWRGOOD CMOS Input A135 REQ 3 AGTL I O Aa RESERVEDA1 DONOTCONNECT Anm o RESERVEDAN DONOTCONNECT A126 RESERVED_A126 DO NOT CONNECT B165 RESERVED_B165 DO NOT CONNECT B34 RESERVED _B34 DO NOT CONNECT B9 RESERVED B9 DONOT CONNECT AGTL I O B145 RSP AGTL Input 70 mw eS oe cee we ewww Se oe we ew ee AA MECHANICAL SPECIFICATIONS AQ SELFSBO CMOS Input SELFSBI CMOS Output SMBus Clock B16 TCK TAP Clock A23 TEST_2 5 A23 Pull up to 2 5V A130 TRDY AGTL Input B103 VCC_CORE Cartridge VCC B2 VCC_CORE Cartridge VCC B29 VCC_CORE Cartridge VCC B41 VCC_CORE Cartridge VCC B5 VCC_CORE Cartridge VCC B58 VCC_CORE Cartridge VCC B70 VCC_CORE Cartridge VCC B8 VCC_CORE Cartridge VCC B88 VCC_CORE Cartridge VCC B106 VCC_L2 N C L2 Cache VCC VCC_L2 N C L2 Cache VCC 71 mw eS oe cee we ewww Se oe we ew ee AA MECHANICAL SPECIFICATIONS B118 VCC_L2 N C L2 Cache VCC VCC 2 NC vec L2 NC B129 VCC_L2 N C L2 Cache VCC BIH VCC_L2 N C L2 Cache VCC B150 VCC_L2 N C L2 Cache VCC oaao B162 VCC_L2 N C L2 Cache VCC ASS VIN SENSE CMOSWO SSCS A122 VSS Ground A13 VSS Ground A161 VSS Ground A22 VSS Ground 72 mw eS oe cee we
60. ache VCC AGTL I O AGTL I O L2 Cache VCC AGTL I O L2 Cache VCC L2 Cache VCC AGTL I O B120 VCC L2 L2 Cache VCC B121 AR O8 AGIL VO B122 A 07 AGTL UO B124 A 03 B125 A 06 B126 VCC_L2 A126 RESERVED_A126 DO NOT CONNECT A127 BNR AGTL I O A128 A129 BPRI AGTL Input A130 TRDY AGTL Input A137 A132 DEFER AGTL Input AGTL I O B129 VCC_L2 B123 VCC_L2 2 Cache VCC AGTL I O AGTL I O L2 Cache VCC L2 Cache VCC AGTL I O A137 VSS Ground A140 VSS Ground A141 BR2 AGTL Input A142 BRO AGTL I O B137 HIT B138 VCC_L2 9592 B140 RP B141 VCC_L2 B142 BR3 AGTL I O L2 Cache VCC AGTL Input AGTL I O A144 ADS AGTL UO AP 0 AGTL VO VSS VSS A147 VID_CORE 2 A148 VID_CORE 1 Open or Short to VSS A149 A150 VID_CORE 4 Open or Short to B144 VCC_L2 B147 VCC_L2 Open or Short to VSS B148 WP B149 VID_CORE B B150 VCC 12 AGTL Input L2 Cache VCC AGTL Input AGTL I O L2 Cache VCC SMBus Input Open or Short to VSS L2 Cache VCC 66 mw eS oe cee we ewww Sw ee ew ee r n R 8 w MECHANICAL SPECIFICATIONS Table 44 Signal Listing in Order by Pin Number ss 8a i A E eee eee A151 SMBALERT SMBus Alert B151 VID_CORE 0 Open or Short to VSS A152 8152 VID_L2 0 Open or Short to VSS A153 VID_L2 2 Open or Short to B153 VCC_L2 L2 Cache VCC VSS A154 VID_L2 1 Open or Short to B154 VID_L2 4 Open or Short to VSS VSS
61. alues specified by design characterization 4 Please see Table 21 for maximum allowable overshoot 5 Ringback between Vref 100mV and Vref 200mV or Vref 200mV and Vref 100mV requires the flight time measurements to be adjusted as described in the Intel AGTL Specification Pentium II Developers Manual Ringback below Vref 100mV or above Vref 100mV is not supported 6 Intel recommends not exceeding a ringback value of 2 3 Vrt 120mV to allow margin for other sources of system noise 7 A negative value ofp indicates that the amplitude of ringback is above 2 3 VTT i e p 100mV specifies the signal cannot ringback below 2 3 VTT 100mV 8 pand are q measured relative to 2 3 Vrt is measured relative to2 3 Vit 200mV 2 3V 55 AY A A A ARA A A A T A 2 3V 2 3V 55 0 2 kh 5 I 1 25V Clk Note High to Low case is analogous 000914a 000914a Figure 12 Low to High AGTL Receiver Ringback Tolerance 4 2 2 AGTL OVERSHOOT UNDERSHOOT GUIDELINES Overshoot guidelines based on magnitude and duration of an overshoot undershoot pulse illustrated in Figure 13 are given in Table 22 Overshoot Undershoot is the absolute value of the maximum voltage differential across the input buffer relative to the termination voltage Vir The overshoot undershoot guideline limits transitions beyond VTT or VSS due to the fast signal edge rates The processor can be damaged by repeated Overshoot Undershoot events on
62. are specified for up to 50 insertion extraction cycles 4 995 036 4 10 FULLY INSTALLED o D491 028 Figure 26 Side View of Connector Mating Details NOTES 4 Dimensional variation when cartridge is fully installed and the substrate is bottomed in the connector Actual system installed height and tolerance is subject to users manufacturing tolerance of SC330 connector to baseboard 5 Retention devices for this cartridge must accommodate this cartridge Float relative to connector without preload to the edge contacts in X and Y axes see figure 22 for axis orientation 10 Fully installed dimensions must be maintained by the user s retention device Cartridge backout from fully installed position may not exceed 0 020 3 000 a p 3 302 7h OCATIONS FOR CARTRIDGE INSERTION PRESSURE 3 Figure 27 Top View of Cartridge Insertion Pressure Points 62 mru eS oe cee we A m r R K e KR Sw KRSR See K o g Kee mew ee r n R 8 we MECHANICAL SPECIFICATIONS AAA Ls Figure 28 Front View of Connector Mating Details NOTES Retention devices for this cartridge must accommodate this cartridge Float relative to connector without preload to the edge contacts in X and Y axes 63 mw eS oe cee we ewww Sw ee ew ee r n R 8 w MECHANICAL SPECIFICATIONS 7 3 Substrate Edge Finger Signal Listing Table 44 is the Pentium Ill Xeon processor at 600 MHz substrat
63. at the SMBus slave device is driving the bus while the clear portions indicate that the SMBus master device under control of the hostis driving the bus Table 27 Send Byte SMBus Packet Device R Address W gt Table 27 outlines the Send Byte packet which provides an address to the device for later use The start condition is followed by a device select field and a write bit which are acknowledged by the device The following data byte is really an address which is also acknowledged by the device Finally the stop condition is signaled 46 mw eS oe cee we ewww Se oe A A e ee A PROCESSOR FEATURES Table 28 Receive Byte SMBus Packet le Adare gt oo Address W gt o ab 1 7 bits 8 bits 1 1 i 7bts ews 1 1 Table 28 diagrams the Receive Byte packet that performs as a current address read The start condition is followed by a device select address field and a read flag The device decodes its address and drives acknowledge low The data is returned by the device and the transfer is terminated by the controller providing negative acknowledge and a stop Note that there is no data address provided only the device address The EEPROM internal address counter keeps track of the address accessed during the last read or write operation incremented by one Repeated current address reads will receive data from consecutive addresses Address roll over will occur when the last byte of the device has been read In this
64. at the output of each buffer The values shown in Figure 31 are only examples The designer should determine the LC values appropriate for their particular application If it is desired to ship production systems without the 2 5V buffers installed then pull up resistors should be placed at the outputs to prevent TCK from floating 79 mw eS oe cee we ewww Sw oe A ew ee AI INTEGRATION TOOLS processor 1 processor 2 2 5V Buffers 74LVQ244 Pull up Resistor TCK nH To each device other f E JTAG Figure 31 TCK with individual buffering scheme The ITP buffer board drives the TCK signal through the debug port to the buffered device s NOTE The buffer rise and fall edge rates should NOT be FASTER than 3nS Edge rates faster than this in the system can contribute to signal reflections that endanger ITP compatibility with the target system A low voltage buffer capable of driving 2 5V outputs such as a 74LVQ244 is suggested to eliminate the need for attenuation Simulation should be performed to verify that the edge rates of the buffer chosen are not too fast The pull up resistor to 2 5V keeps the TCK signal from floating when the ITP is not connected The value of this resistor should be such that the ITP can still drive the signal low 1K The trace lengths from the buffer to each of the agents should also be kept at a minimum to ensure good signal integrity 8 1 7 Using the TAP to Communicate to t
65. ccessful read to the status register will clear any alarm bits that may have been set unless the alarm condition persists Table 37 Thermal Sensor Status Register 7 MSB BUSY A one indicates that the device s analog to digital converter is busy converting oe RESERVED Reserved for future use RESERVED Reserved for future use RHIGH A one indicates that the processor core thermal diode high temperature alarm has activated RESERVED Reserved for future use 0 LSB RESERVED Reserved for future use 5 2 6 4 Configuration Register 3 RLOW A one indicates that the processor core thermal diode low temperature alarm has activated OPEN A one indicates an open fault in the connection to the processor core diode The configuration register controls the operating mode standby vs auto convert of the thermal sensor Table 38 shows the format of the configuration register If the RUN STOP bit is set high then the thermal sensor immediately stops converting and enters standby mode The thermal sensor will still perform analog to digital conversions in standby mode when it receives a one shot command If the RUN STOP bit is clear low then the thermal sensor enters auto conversion mode 50 msu eS oe cee we A we Se re we ew eee AI PROCESSOR FEATURES Table 38 Thermal Sensor Configuration Register 7 MSB RESERVED lo Reserved for future use RUN STOP Standby mode control bit If high the device immediately stops conv
66. cessor or termination card installed to complete the chain between TDI and TDO or the system must support a method to bypass the empty connectors SC330 terminator substrates should tie TDI directly to TDO See Chapter 8 for more details 3 9 Maximum Ratings Functional operation at the absolute maximum and minimum is not implied nor guaranteed The processor should not receive a clock while subjected to these conditions Functional operating conditions are given in the AC and DC tables Extended exposure to the maximum ratings may affect device reliability Furthermore although the processor contains protective circuitry to resist damage from static electric discharge one should always take precautions to avoid high static voltages or electric fields Table 4 Absolute Maximum Ratings VCC_CORE Supply voltage with respect to 0 5 Operating Vss seen at the input of the voltage 1 0 OCVR V SMBus Any processor SM supply 0 3 Operating voltage with respect to Vss voltage 1 0 Voctap Any processor TAP supply 0 3 3 3 V 1 voltage with respect to Vss VinGTL AGTL buffer DC input voltage 0 3 1 65 with respect to V ss Vincmos CMOS amp APIC buffer DC input 0 3 3 3 voltage with respect to Vss VinSMBus SMBus buffer DC input voltage 0 1 7 0 with respect to Vss NOTES 1 Operating voltage is the voltage to which the component is designed to operate See Table 5 2 VCC_CORE in the case of Pentium II Xeon processor at 600 MHz is
67. d in legacy systems and is not recommended to be connected in Pentium Ill Xeon processor at 600 MHz only systems Systems that rely on remote sensing of VCC_L2 need to guarantee this requirement is met at the VRM sense line regardless of core feedback 10 1 32 OCVR_EN I This signal is the output enable for the internal cartridge voltage regulator Driving this Low will inactivate the outputs of the OCVR This is an open drain signal referenced high to 5V through a 10K ohm resistor within the cartridge to activate the VRM when not driven low this to satisfy legacy requirements Refer to Figure 41 and Figure 42 For PWRGD relationships at Power up 10 1 33 OCVR_OK O This is an open drain compatible output from the On Cartridge Voltage Regulator Module OCVR indicating that its outputs are enabled and operating within specifications This signal is referenced to VCC_SMB 3 3V through a 10K ohm resistor and should be used in conjunction with an equivalent signal from the host power system to generate the CORE_PWRGD signals for the processor cores Refer to Figure 41 and Figure for PWRGD relationships at Power up PWRGD assertion must lag OCVR_OK assertion 10 1 34 NMI See LINT 1 10 1 35 PICCLK I The PICCLK APIC Clock signal is a 2 5V tolerant input clock to the processor and core logic or I O APIC that is required for operation of all processors core logic and I O APIC components on the APIC bus 94 PENTIUMO III XEON P
68. ds on a high speed bus The Pentium Ill Xeon processor at 600 MHz supports both uni processor and multiprocessor implementations with support for two processing units on each local processor bus or system bus The Pentium III Xeon processor at 600 MHz system bus operates using GTL signaling levels with a new type of buffer utilizing active negation and multiple terminations This new bus logic is called Assisted Gunning Transistor Logic or AGTL The Pentium Ill Xeon processor at 600 MHz uses the S E C cartridge package supported by the SC330 Connector See Chapter 7 for the processor mechanical specifications The Pentium Ill Xeon processor at 600 MHz includes an SMBus interface that allows access to several processor features including two memory components referred to as the processor Information ROM and the Scratch EEPROM and a thermal sensor on the Pentium Ill Xeon processor at 600 MHz substrate The Pentium III Xeon processor at 600 MHz system bus definition uses the SC330 1 interface The SC330 1 interface is an electrical only enhancement to the SC330 interface that allows supporting a dual Pentium Ill Xeon processor at 600 MHz system running at 133Mhz system bus The SC330 1 specification adds the required flexibility to accommodate control and monitoring signals for an OCVR On Cartridge Voltage Regulator The OCVR provides the necessary high precision regulation used by Intel s latest silicon technology This document provides in
69. e edge finger listing in order by pin number Table 45 is the Pentium III Xeon processor at 600 MHz substrate edge connector listing in order by pin name These tables reflect the new SC330 1 pin definition new or changed pins definitions are shown in bold Table 44 Signal Listing in Order by Pin Number ETETEA RS pinnamoe signatarios DO NOT La PWR poo Short to PWR_EN O CONNECT ree Fer EA ON Es HV_EN OPEN 2 8V OCVR_OK Open Drain Output Pentium Ill Xeon IA a e SHORT 5 12V Pentium Ill Xeon processor A4 VSS Cd Ground BT PulldowntoVss B6 E EA CUE ACTI CMOS Output 87 SELFSBO CMOS Input RESERVED B9 DO NOT CONNECT RE CONNECT A12 IERR CMOS Output B12 SMI CMOS Input TAP Input A20 TDO TAP Output B20 VCC_CORE Cartridge VCC TAP Input A23 TEST 2 5 A22 Pull up to 2 5V B23 VCC_CORE Cartridge VCC B24 RESERVED B24 DONOT CONNECT Ground DO NOT CONNECT NOT CONNECT A26 OCVREN CMOSINPUT A27 LINT 0 CMOS Input B27 TEST 2 5_B27 Pull up to 2 5V A31 VSS Ground B31 PICD 1 CMOS UO A35 BINIT AGTL I O B35 VCC_CORE Cartridge VCC 64 mw eS oe cee we ewww Sw ee ew ee r n R 8 w MECHANICAL SPECIFICATIONS Table 44 Signal Listing in Order by Pin Number Signal Buffer Type Signal Buffer Type A40 VSS Ground B40 DEP 4 AGTL I O A44 D 61 AGTL I O B44 VCC_CORE Cartridge VCC A48 DA 53 AGTL VO B48 DH56 AGTL VO AGTL VO Le VSS Ground B52 D 59 AGTL I
70. e that sent the alert will respond to the ARA Packet with its address in the seven most significant bits The least significant bit is undefined and may return as a 1 or 0 See Section 5 2 5 for details on the Thermal Sensor Device addressing Table 36 Command Byte Bit Assignments 02h N A Read status byte flags busy signal RRHL 07h Read processor core thermal diode Tuan limit RRLL 08h Read processor core thermal diode TLow limit ___ Read processor core thermal diode Tinon limit _Read processor core thermal diode Tuow imit OSHT OFh N A One shot command use send byte packet RESERVED 10h FFh N A Reserved for future use All of the commands are for reading or writing registers in the thermal sensor except the one shot command OSHT The one shot command forces the immediate start of a new conversion cycle If a conversion is in progress when the one shot command is received then the command is ignored If the thermal sensor is in standby mode when the one shot command is received a conversion is performed and the sensor returns to standby mode The one shot command is not supported when the thermal sensor is in auto convert mode If the thermal sensor is in auto convert mode and is between conversions then the conversion rate timer resets and the next automatic conversion takes place after a full delay elapses The default command after reset is to a reserved value 00h After reset receive byte packets will retu
71. eon processors at 600 MHz These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See section 3 5 for more information Pentium Ill Xeon processor at 600 MHz does not require a separate VCC_ 2 voltage Use the Typical Voltage specification along with the tolerance specifications to provide correct voltage regulation to the processor Vit is 1 5 2 AC 8 DC for Pentium lll Xeon processor at 600 MHz when the measurement is bandwidth limited to 20MHz and measured at the SC 330 connector pin on the back solder tail side of the baseboard This parameter is measured at the processor edge fingers The SC330 connector is specified to have a pin self inductance of 6 0 nH maximum a pin to pin capacitance of 2 pF maximum at 1 MHz and an average contact resistance over the 6 VTT pins of 15 m ohms maximum Z These are the tolerance requirements across a 20MHz bandwidth at the processor edge fingers The requirements at the processor edge fingers account for voltage drops and impedance discontinuities at the processor edge fingers and to the processor core Voltage must return to within the static voltage specification within 100 us after the transient event The SC330 connector is specified to have a pin self inductance of 6 0 nH maximum a pin to pin capacitance of 2 pF maximum at 1 MHz and an average contact resistance of 15m ohms maximum in order to function with the Intel
72. er Distribution amp Control for Pentium III Xeon Processors Order Number 245245 3 3 2 LEVEL 2 CACHE DECOUPLING The Pentium Ill Xeon processor at 600 MHz does not require the VCC_L2 pins for power 3 3 3 SYSTEM BUS AGTL DECOUPLING The Pentium Ill Xeon processor at 600 MHz contains high frequency decoupling capacitance on the processor substrate bulk decoupling on the system baseboard must be provided to assure proper AGTL bus operation High frequency decoupling may be necessary at the SC330 connector to further improve signal integrity if noise is picked up at the connector interface 3 4 Clock Frequencies and System Bus Clock Ratios The Pentium III Xeon processor at 600 MHz uses a clock ratio design in which the bus clock is multiplied by a ratio to produce the processors internal core clock The Pentium Ill Xeon processor at 600 MHz begins sampling A20M IGNNE LINT O and LINT 1 on the inactive to active transition of RESET to determine the core frequency to bus frequency relationship and the PLL immediately begins to lock on to the input clock On the active to inactive transition of RESET the Pentium Ill Xeon processor at 600 MHz internally latches the inputs to allow the pins to be used for normal functionality Effectively these pins must meet a large setup time 1mS to the active to inactive transition of RESET see RESET and PWRGD relationship in figure 41 These pins should then be held static for a
73. erting and enters standby mode If low the device converts in either one shot mode or automatically updates on a timed basis RESERVED fo Reserved for future use 5 2 6 5 Conversion Rate Register The contents of the conversion rate register determine the nominal rate at which analog to digital conversions happen when the thermal sensor is in auto convert mode Table 39 shows the mapping between conversion rate register values and the conversion rate As indicated in Table 39 the conversion rate register is set to its default state of 02h 0 25 Hz nominally when the thermal sensor is powered up There is a 25 error tolerance between the conversion rate indicated in the conversion rate register and the actual conversion rate Table 39 Thermal Sensor Conversion Rate Register Register Contents Conversion Rate Hz 0 0625 08h to FFh Reserved for future use 5 2 7 SMBus Device Addressing Of the addresses broadcast across the SMBus the memory components claim those of the form 1010XXYZb The XX and Y bits are used to enable the devices on the cartridge at adjacent addresses The Y bit is hard wired on the cartridge to V SS 0 for the Scratch EEPROM and pulled to VCC_sp 1 for the processor Information ROM The XX bits are defined by the processor slot via the SAO and SA1 pins on the SC330 connector These address pins are pulled down 1K ohm to ensure that the memory components are in a known state
74. escribed in this chapter should be used as general guidelines for Pentium lll Xeon processor at 600 MHz system design 8 1 In Target Probe ITP An In Target Probe ITP for Pentium III Xeon processor at 600 MHz is a debug tool that allows access to on chip debug features via a small port on the system board called the debug port The ITP communicates to the processor through the debug port using a combination of hardware and software The software is a Windows NT 4 0 based application running on a host PC The hardware consists of a PCI board in the host PC connected to the signals that make up the Pentium IIl Xeon processor at 600 MHz debug interface Due to the nature of the ITP the processor may be controlled without affecting any high speed signals This ensures that the system can operate at full speed with the ITP attached Intel will use an ITP for internal debug and system validation and recommends that all Pentium Ill Xeon processor at 600 MHz based system designs include a debug port This is especially important if Intel assistance is required in debugging a system processor interrelationship issue 8 1 1 PRIMARY FUNCTION The primary function of an ITP is to provide a control and query interface for one or more processors With an ITP one can control program execution and have the ability to access processor registers system memory and l O Thus one can start and stop program execution using a variety of breakpoints single step
75. est data input signal from ITP to first component in boundary scan chain of MP cluster inputs test instructions and data serially Used by ITP to determine when target system power is ON and once target system is ON enables all debug port electrical interface activity From target Vrr to ITP Terminate signal properly at the debug port Debug port must be at the end of the signal trace Tie signal to target system reset recommendation PWR_OK signal on PClset as an ORed input Pulled up signal with the proper resistor see Signal Notes section following Add 1 0K ohm pull up resistor to VCC_TAP near driver For MP systems each processor should receive a separately buffered TCK Add a series termination resistor or a Bessel filter on each output Add 1 0K ohm pull up resistor to VCC_TAP near driver For MP systems each processor should receive a separately buffered TMS Add a series termination resistor on each output This signal is open drain from the ITP However TDI is pulled up to VCC_TAP with 150 ohm on the Pentium III Xeon processor at 600 MHz Add a 150 to 330 ohm pull up resistor to VCC_TAP if TDI will not be connected directly to a processor Add 1K ohm pull up resistor to Vir Connected to high speed comparator biased at 2 3 of the level found at the POWERON pin on the ITP buffer board Additional load does not change timing calculations for the processor
76. f the Pentium III Xeon processor at 600 MHz family See Chapter 7 for a pin listing of the processor edge connector for the location of each reserved pin The TEST_2 5_A62 pin must be connected to 2 5 Volts via a pull up resistor between 1K and 10K ohms For the 5 12V Pentium lll Xeon processor only it is recommended that pins that were previously specified as TEST_VCC_CORE_XX now specified TEST 2 5 XX be connected to the VCC_2 5 supply through separate 10K ohm resistors on the baseboard However there will be no damage to cartridges if existing platforms provide 2 8 Volts to the pull up resistors All TEST VTT pins must be connected to the Vr supply through individual 150 ohm resistors All TEST_VSS pins must be connected individually to the VSS supply through individual 1K ohm resistors PICCLK must always be driven with a valid clock input and the PICD 1 0 lines must be pulled up to 2 5V even when the APIC will not be used A separate pull up resistor to 2 5V keep trace short is required for each PICD line For reliable operation always connect unused inputs to an appropriate signal level Unused AGTL inputs should be left as no connects AGTL termination on the processor provides a high level Unused active low CMOS inputs should be connected to 2 5V with a 10K ohm resistor Unused active high CMOS inputs should be connected to ground VSS Unused outputs may be left unconnected A resistor must be used when tying bi directional si
77. f the Pentium III Xeon processor at 600 MHz This clock is asynchronous to other clocks to the processor 10 1 51 SMBDAT 1 0 The SMBDAT SMBus DATa signal is the data signal for the SMBus This signal provides the single bit mechanism for transferring data between SMBus devices 10 1 52 SMI 1 The SMI System Management Interrupt signal is asserted asynchronously by system logic On accepting a System Management Interrupt processors save the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler 10 1 53 STPCLK 1 99 PENTIUMO III XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX The STPCLK Stop Clock signal when asserted causes processors to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the bus and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input 10 1 54 TCK I The TCK Test Clock signal provides the clock input for the Pentium III Xeon processor at 600 MHz Test Bus also known as the Test Access Port 10 1 55
78. for up to 4 way MP systems more processors can be supported by using a multiplexed or separate SMBus implementation fet lt x x x x lt 52 msu eS oe cee oe ewww Se oe K A A e eee r n R 8 w THERMAL SPECIFICATIONS 6 THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS The Pentium Ill Xeon processor at 600 MHz will use a thermal plate for heat sink attachment The thermal plate interface is intended to provide for multiple types of thermal solutions This chapter will provide the necessary data for a thermal solution to be developed See Figure 17 for thermal plate location THERMAL PLATE Figure 17 Thermal Plate View 6 1 Thermal Specifications This section provides power dissipation specifications for each variation of the Pentium III Xeon processor at 600 MHz The thermal plate flatness is also specified for the S E C cartridge 6 1 1 POWER DISSIPATION Table 42 provides the thermal design power dissipation for Pentium Ill Xeon processor at 600 MHz While the processor core dissipates the majority of the thermal power the system designer should also be aware of the thermal power dissipated by the OCVR Systems should design for the highest possible thermal power even if a processor with lower frequency is planned The thermal plate is the attach location for all thermal solutions The maximum temperature for the entire thermal plate surface is shown in Table 42 The processor power is dissipated thr
79. formation regarding the design of a system using the Pentium IIl Xeon processor at 600 MHz with the new SC330 1 interface Certain versions of the Pentium III Xeon processor at 600 MHz are designed to be compatible with the existing VRM 8 3 Guidelines allowing an easy transition for Flexible Mother Board designs The 2 8V Pentium Ill Xeon processor regardless of frequency is designed for compatibility with the VRM 8 3 Guidelines The 5 12V Pentium Ill Xeon processor adds flexibility to operate at either 5 Volts or 12 Volts The new flexible motherboard specification that incorporates SC330 1 uses the same form factor and pin definition of the existing SC330 processors but adds signals to control an OCVR and remote sensing capabilities The SC330 1 enhancement is electrically and mechanically compatible with existing baseboards msu Sm RRR nn cee we ewww oe A A ew ee r n R 8 w TERMINOLOGY 2 TERMINOLOGY In this document a symbol after a signal name refers to an active low signal This means that a signal is in the active state based on the name of the signal when driven to a low level For example when FLUSH is low a flush has been requested When NMI is high a non maskable interrupt has occurred In the case of lines where the name does not imply an active state but describes part of a binary sequence such as address or data the T symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A
80. get system Add 10K ohm pull up resistor Not required if boundary scan is not that the ITP is installed used in target system TRST Test reset signal from ITP Add 680 ohm pull down Asynchronous input signal to MP cluster used to l Z reset TAP logic To disable TAP reset if ITP not installed BSEN 14 Informs target system that Not required if boundary scan is not ITP is using boundary used in target system scan PREQO 16 PREQO signal driven by Add 150 to 330 ohm pull up ITP makes requests to PO resistor to VCC_TAP to enter debug PRDYO 18 PRDYO signal driven by Terminate signal properly at Connected to high speed PO informs ITP that PO is the debug port comparator biased at 2 3 of the ready for debug level found at the POWERON pin Debug port must be at the end on the ITP buffer board Additional of the signal trace load does not change timing calculations for the processor bus agents if routed properly PREQI 20 PREQ1 signal from ITP to Add 150 to 330 ohm pull up P4 resistor to VCC_TAP PRDY1 22 PRDY1 signal from P1 to Terminate signal properly at Connected to high speed ITP the debug port comparator biased at 2 3 of the Debug port must be at the end level found at the POWERON pin of the signal trace on the ITP buffer board Additional load does not change timing calculations for the processor bus agents PREQ2 PREQ2 p from ITP to Add 150 to 330 ohm pull up resistor to VCC_TAP P
81. gnals to power or ground When tying any signal to power or ground a resistor will also allow for system testability For correct operation when using a logic analyzer interface refer to Chapter 8 for design considerations 3 7 System Bus Signal Groups In order to simplify the following discussion the system bus signals have been combined into groups by buffer type All system bus outputs should be treated as open drainand require a high level source provided externally by the termination or pull up resistor AGTL input signals have differential input buffers which use 2 3 V TT as a reference level AGTL output signals require termination to 1 5V In this document the term AGTL Input refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the AGTL I O group when driving The AGTL buffers employ active negation for one clock cycle after assertion to improve rise times The CMOS Clock APIC and TAP inputs can each be driven from ground to 2 5V The CMOS APIC and TAP outputs are open drain and should be pulled high to 2 5V This ensures not only correct operation for Pentium III Xeon processor at 600 MHz but compatibility with future Pentium III Xeon processors at 600 MHz Timings are specified into the load resistance as defined in the AC timing tables See Chapter 8 for design considerations for debug equipment The SMBus signals should be dr
82. he processor An ITP communicates to the Pentium IIl Xeon processor at 600 MHz by stopping its execution and sending receiving messages over boundary scan pins As long as each processor is tied into the system boundary scan chain the ITP can communicate with it In the simplest case the processors are back to back in the scan chain with the boundary scan input TDI of the first processor connected up directly to the pin labeled TDI on the debug port and the boundary scan output of the last processor connected up to the pin labeled TDO on the debug port as shown in Figure 32 80 s ses eS oe cee we r p m m r R K e KR Se re A A ew ee AI INTEGRATION TOOLS TDO TDI SC 330 1 SC 330 1 Processor Processor TDO TDI Note See previous table for recommended PCIset pull up resistor values Component Debug Port ITP 000799c 0007990 Figure 32 System Preferred Debug Port Layout 8 2 Logic Analyzer Interconnect LAI and Trace Capture Tool Considerations 8 2 1 LAl and Trace Capture Tool System Design Considerations System Designers must contact their third party tools vendors for Logic Analyzer Interface design considerations for the Pentium Ill Xeon processor at 600 MHz including electrical load models for system simulations At this time Hewlett Packard Tektronix and American Arium are currently investigating Logic Analyzer Interconnect or trace capture tools for the Pentium Ill Xeon processor at 600 MHz
83. hese signals 10 1 63 VIN_SENSE VIN_SENSE formerly called CPU_SENSE is routed from edge connector pin A56 to the VCC_CORE power plane VIN_SENSE provides remote sensing capabilities for the voltage seen at the input of the OCVR NOTE Pentium lll Xeon processors at 600 MHz support either 2 8V 5V or 12V VCC_CORE voltages depending on the version of OCVR Therefore any sensing logic must be capable of tolerating the selected VCC_CORE voltage 2 8 5V 12V 10 1 64 WP I WP Write Protect can be used to write protect the scratch EEPROM A high level write protects the scratch EEPROM 10 2 Signal Summaries The following tables list attributes of the Pentium Ill Xeon processor at 600 MHz output input and I O signals Table 53 Output Signals rene ter 00 ao FERR Low CMOS Output IERR Low CMOS Output PRDY Low AGTL Output SMBALERTH Low SMBus Output TDO TCK TAP Output THERMTRIP Low CMOS Output VID_CORE 4 0 Power Other VID_L2 4 0 Power Other CPU_SENSE Power Other L2 SENSE Power Other OCVR_OK Power Other Table 54 Input Signals tine Tas cos Stora croup Tana ere oo INTR APIC disabled mode 101 PENTIUMO III XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX Table 54 Input Signals time acivetesel Goce Strat Group ovale 9 Paco om weon mwe Ceneo on sea pean CS ama omn TC mw MONETA tow ION TT esas tow romen TT SCS HH ICI we
84. hoot events each of which will have their own set of parameters duration AF and magnitude While each overshoot on its own may meet the overshoot specification when you add the total impact of all overshoot events the system may fail A guideline to ensure a system passes the overshoot and undershoot specifications is shown below e Insure no signal CMOS or AGTL ever exceed the 1 635V e If only one overshoot undershoot event magnitude occurs ensure it meets the over undershoot specifications in the following tables This means that whenever the over undershoot event occurs it always over undershoots to the same level 33 AS r R s sew r p m m r R R e K S www seen sw ee ew ee dd SIGNAL QUALITY e If multiple overshoots and or multiple undershoots occur measure the worst case pulse duration for each magnitude and compare the results against the AF 1 specifications note multiple overshoot undershoot events within one clock cycle must have their pulse durations summed together to determine the total pulse duration If all of these worst case overshoot or undershoot events meet the specifications measured time lt specifications in the table where AF 1 then the system passes Table 22 AGTL Signal Overshoot Undershoot Limits at the Processor Core 1 2 3 4 5 6 7 8 9 Overshoot Undershoot Magnitude Max Pulse Duration nS NOTES Unless otherwise noted all guidelines in this table apply to all Pentium II
85. iate to the Machine Check Architecture MCA of the system 10 1 5 AP 1 0 1 0 The AP 1 0 Address Parity signals are driven by the request initiator along with ADS A 35 03 REQ 4 0 t and RP AP1 covers A 35 24 and APO covers A 23 03 A correct parity signal is high if an even number of covered signals is low and low if an odd number of covered signals are low This allows parity to be high when all the covered signals are high AP 1 0 should connect the appropriate pins of all Pentium IlI Xeon processor at 600 MHz system bus agents 89 PENTIUMO III XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX 10 1 6 BCLK I The BCLK Bus Clock is a 2 5V tolerant signal that determines the bus frequency All Pentium III Xeon processor at 600 MHz system bus agents must receive this signal to drive their outputs and latch their inputs on the BCLK rising edge All external timing parameters are specified with respect to the BCLK signal 10 1 7 BERR 1 0 The BERR Bus Error signal is asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by all Pentium Ill Xeon processor at 600 MHz system bus agents and must connect the appropriate pins of all such agents if used However Pentium IIl Xeon processor at 600 MHz do not observe assertions of the BERR signal BERR assertion conditions are configurable at a system level Assertion options are defined by the follo
86. ignal is asserted processors write back all data in the Modified state from their internal caches and invalidate all internal cache lines At the completion of this operation the processor issues a Flush Acknowledge transaction The processor does not cache any new data while the FLUSH signal remains asserted FLUSH is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding I O Write bus transaction On the active to inactive transition of RESET each processor samples FLUSH to determine its power on configuration See Pentium II processor Developer s Manualfor details 10 1 23 HIT 1 0 HITM 1 0 The HIT Snoop Hit and HITM Hit Modified signals convey transaction snoop operation results and must connect the appropriate pins of all Pentium III Xeon processor at 600 MHz system bus agents Any such agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together 10 1 24 HV_EN O The HV_EN signal is used as a way of differentiating a 5 12V Pentium Ill Xeon processor cartridge from a 2 8V Pentium Ill Xeon processor HV_EN is tied to VSS ground on the 5 12V Pentium Ill Xeon processor and is high impedance floating on the 2 8V Pentium III Xeon processor This is a reserved no connect pin on Pentium IIl Xeon process
87. in Table 42 TLA is a function of the system design Table 43 provides the example of a resultant thermal solution performance for Pentium lll Xeon processor at 600 MHz at different ambient air temperatures around the processor Table 43 Example Thermal Solution Performance Thermal Solution Performance Local Ambient Temperature Ta Pentium Ill Xeon processor at 600 MHz FMB 37 watts thermal plate to ambient C watt Theta thermal plate to ambient value is made up of two primary components the thermal resistance between the thermal plate and heat sink theta thermal plate to heat sink and the thermal resistance between the heat sink and ambient air around the processor theta0 heat sink to air A critical but controllable factor to decrease the resultant value of theta thermal plate to heat sink is management of the thermal interface 55 sess s sw ng ew eee r n R R e THERMAL SPECIFICATIONS between the thermal plate and heat sink The other controllable factor theta heat sink to air is determined by the design of the heat sink and airflow around the heat sink General Information on thermal interfaces and heat sink design constraints can be found in AP 586 Pentium II Processor Thermal Design Guidelines Order Number 243331 6 2 2 THERMAL PLATE TO HEAT SINK INTERFACE MANAGEMENT GUIDE Figure 19 shows suggested interface agent dispensing areas when using either Intel suggested interface agent Actual user
88. ing and falling edge ringback voltage specified is the minimum rising or maximum falling absolute voltage the BCLK signal can dip back to after passing the Vi rising or V L falling voltage limits This specification is an absolute value Figure 11 BCLK TCK PICCLK Generic Clock Waveform at the processor Core Pins 4 2 AGTL Signal Quality Specifications Refer to the Pentium II processor Developer s Manual Order Number 243341 for the specification for AGTL 31 s es eS nn rr r R s sem r p m m r R K e KR e KRSR Kee K R g Kee RR S KRSR m R Ker ANI SIGNAL QUALITY 4 2 1 AGTL Ringback Tolerance Specifications Table 21 provides the AGTL signal quality specifications for Pentium lll Xeon processors at 600 MHz for use in simulating signal quality at the processor core pads Figure 12 describes the signal quality waveform for AGTL signals at the processor core pads For more information on the AGTL interface see the Pentium II processor Developers Manual Order Number 243341 Table 21 AGTL Signal Groups Ringback Tolerance Specifications at the processor Core 1 2 3 Amplitude of Ringback Figure 12 5 7 8 S Final Settling Voltage 200 Figure 12 a l Duration of Squarewave Ringback N A Figure 12 P NOTES 1 Unless otherwise noted all guidelines in this table apply to all Pentium III Xeon processor at 600 MHz frequencies and cache sizes 2 Specifications are for the edge rate of 0 3 0 8 V nS 3 All v
89. issipated by the processor L2 cache and the OCVR It is not possible for the AGTL bus and the processor core to all be at full power simultaneously 4 Thermal power which should be used for thermal designs indicates the worst case power that can be dissipated by the processor L2 cache and 50 of the OCVR since the OCVR does not contact the Thermal Plate De rating the thermal design power may result in exceeding the Tplate maximum temperature specification which may result in immediate system failure or degradation of the processor s functional lifetime AGTL power is the worst case power dissipated in the termination resistors for the AGTL bus 5 FMB is a suggested design guideline for a flexible motherboard design 6 A disabled Pentium III Xeon processor at 600 MHz OCVR draws approximately 46 mA load at 2 8V VCC core from the motherboard VRM If your system needs to maintain VRM regulation with a disabled Pentium lll Xeon processor at 600 MHz OCVR_EN inactive the VRM output minimum load specification should be 46 mA or less 7 The Thermal Power specifications have been recently redefined These values are based on device characterization and do not reflect any silicon design changes to lower processor power consumption Absolute power consumption has not changed however the maximum thermal power specifications are being updated to reflect actual silicon performance The Thermal Power values represent the thermal design point req
90. iven using standard 3 3V CMOS logic levels 14 msu s svenn nn sammen we ewww ww o A A RR S KRSR ew eee AI ELECTRICAL SPECIFICATIONS Table 3 Processor pin Groups MTI Sms AGTL Input BPRI BR 3 1 41 DEFER RESET RS 2 0 t RSP TRDY AGTL Output PRDY AGTL I O A 35 03 ADS AERR AP 1 0 BERR BINIT BNR BP 3 2 BPM 1 0 BRO 1 D 63 00 DBSY DEP 7 0 DRDY HIT HITM LOCK REQ 4 0 RP CMOS Input A20M FLUSH IGNNE INIT LINTO INTR LINT1 NMI PREQ PWRGD2 SMI SLP 2 STPCLK Power Other4 VCC_CORE VCC_TAP VCC_SMB VTT VSS RESERVED XXX SA 2 1 SELFSB 0 1 OCVR_EN OCVR_OK VIN_SENSE CORE_AN_VSENSE HV_EN NOTES 1 The BRO pin is the only BREQ signal that is bi directional The internal BREQ signals are mapped onto BR pins based on a processor s agent ID See Chapter 10 for more information 2 For information on these signals see Chapter 10 3 These signals are specified for 2 5V operation 4 VTT is used for the AGTL termination VSS is system ground VCC_TAP is the TAP supply VCC_SMB is the SM bus supply Reserved pins must be left unconnected Do not connect to each other 3 7 2 ASYNCHRONOUS VS SYNCHRONOUS FOR SYSTEM BUS SIGNALS All AGTL signals are synchronous to BCLK All of the CMOS Clock APIC and TAP signals can be applied asynchronously to BCLK All APIC signals are synchronous to PICCLK All TAP signals are synchronous to TCK All SMBus signa
91. k The Y axis in Figure 36 represents the thermal resistance pa and the X axis represents the airflow speed in linear feet per minute lfm ea can be calculated as the difference between the thermal plate temperature and ambient air temperature within the chassis divided by the processor s maximum power specification T pate 7 T ambient 6 A Purax To determine if your airflow is adequate determine the airflow speed and direction and identify the appropriate curve in Figure 36 Calculate Opa and determine if it falls below the graphed line at the appropriate airflow speed Horizontal Normal Top Down Aux Fan 50mm 300 Airflow Speed lfm Figure 36 Boxed Processor Heat sink Performance Figure 36 also shows the performance of the boxed processor heat sink with an attached auxiliary fan 60mm X 50mm X 15mm In this case the temperature of the air entering the fan is used as Tawpient Tamient iS measured just outside the fan s air intake The presence of the auxiliary fan allows the cooling solution to 85 mw eS oe cee we ewww Se oe A A m R Ker ee AS BOXED PROCESSOR SPECIFICATIONS perform with very little local airflow Therefore Ora is virtually constant and independent of the speed and direction of airflow across the heat sink 9 3 2 Optional auxiliary fan attachment The boxed processor s passive heat sink includes features that allow for attachment of a standard auxiliary fan to improve ai
92. l V Ni Y U fi IN i K i l N y Y U Y W N y Nt U A l y V Q l i U P l 10 NN X D y S U U G U I N YN IN 1 IN N G Al i N N LU N Y N U Y L INNNI NN N EE 1 1 ei M T N CO U Figure 33 Boxed Pentium Ill Xeon processor at 600 MHZ 9 2 Mechanical Specifications This section documents the mechanical specifications of the boxed Pentium Ill Xeon processor at 600 MHz heat sink The boxed processor ships with an attached passive heatsink Clearance is required around the heat sink to ensure proper installation of the processor and unimpeded airflow for proper cooling The space requirements and dimensions for the boxed processor are shown in Figure 34 Side View Figure 35 Front View and Table 47 All dimensions are in inches 82 om eS oe cee we ewww Se oe A A ew ee AI BOXED PROCESSOR SPECIFICATIONS Figure 34 Side View Space Requirements for the Boxed Processor 83 msu Sm RRR oe cee we mew we Se ee ew eee r n R 8 w BOXED PROCESSOR SPECIFICATIONS E a A i i O L 9 G G GGO GOGO GO G G WF Figure 35 Front View Space Requirements for the Boxed Processor 9 2 1 BOXED PROCESSOR HEATSINK DIMENSIONS Table 47 Boxed Processor Heat sink Dimensions Fig Ref Dimensions Inches Typ Label A Heat sink Depth off heat sink attach point ES
93. l Xeon processor at 600 MHz frequencies Overshoot Magnitude and Undershoot Magnitude are absolute values and should never exceed 2 3V under any circumstances Overshoot is measured relative to VSS Undershoot is measured relative to VTT Overshoot Undershoot Pulse Duration is measured relative to 1 635V Rinback below VTT cannot be subtracted from Overshoots Undershoots Lesser Undershoot does not allocate longer or larger Overshoot Lesser Overshoot does not allocate longer or larger Undershoot OEM s are encouraged to follow Intel provided layout guidelines All values specified by design characterization DO ND BOPI 34 AS r u s sew w mwn K e K S ue mma sw ng ew ee r n R R e SIGNAL QUALITY Time Dependent Converted Overshoot Undershoot Waveform Overshoot Magnitude Undershoot Magnitude Overshoot Magnitude Signal Vss Undershoot _ Magnitude NU Signal lt Time Dependent Undershoot Figure 13 Maximum Acceptable Overshoot Undershoot Waveform1 2 3 4 5 6 7 8 NOTES Overshoot Magnitude and Undershoot Magnitude are absolute values and should never exceed 2 3V under any circumstances Overshoot is measured relative to Vss Undershoot is measured relative to Vr Overshoot Undershoot Pulse Duration is measured relative to 1 635V Rinback below Vrt cannot be subtracted from Overshoots Undershoots Lesser Undershoot does not allocate longer or larger Overshoot Lesser Overshoot does no
94. line for flexible motherboard design 2 VCC_core Icc_core supplies the processor core integrated L2 cache and OCVR 3 Max Icc measurements are measured at Vcc minimum voltage under maximum signal loading conditions 4 This is the current required for a single Pentium IlI Xeon processor at 600 MHz A similar current is drawn through the termination resistors of each load on the AGTL bus VTT is decoupled on the SC330 cartridge such that negative current flow due to the active pull up to VCC_CORE in the Pentium III Xeon processor at 600 MHz will not be seen at the processor fingers 5 The current specified is also for AutoHALT state 6 These maximum values are specified by design characterization at nominal Vcc and at the SC330 edge fingers 7 Based on simulation and averaged over the duration of any change in current Use to compute the maximum inductance tolerable and reaction time of the voltage regulator This parameter is not tested 8 VCC_SMB must be connected to 3 3V power supply even if the SMBus features are not used in order for the Pentium III Xeon processor at 600 MHz to function properly 9 A disabled Pentium III Xeon processor at 600 MHz OCVR draws approximately 46 mA load at 2 8V VCC core from the motherboard VRM If your system needs to maintain VRM regulation with a disabled Pentium lll Xeon processor at 600 MHz OCVR_EN inactive the VRM output minimum load specification should be 46 mA or less 10 The
95. lowing an l O write instruction it must be valid along with the TRDY assertion of the corresponding I O Write bus transaction During active RESET each processor begins sampling the A20M IGNNE and LINT 1 0 values to determine the ratio of core clock frequency to bus clock frequency See Figure 1 On the active to inactive transition of RESET each processor latches these signals and freezes the frequency ratio internally System logic must then release these signals for normal operation 10 1 3 ADS I O The ADS Address Strobe signal is asserted to indicate the validity of the transaction address on the A 35 03 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction This signal must connect the appropriate pins on all Pentium Ill Xeon processor at 600 MHz system bus agents 10 1 4 AERR I O The AERR Address Parity Error signal is observed and driven by all Pentium Ill Xeon processor at 600 MHz system bus agents and if used must connect the appropriate pins on all Pentium Ill Xeon processor at 600 MHz system bus agents AERR observation is optionally enabled during power on configuration if enabled a valid assertion of AERR aborts the current transaction If AERR observation is disabled during power on configuration a central agent may handle an assertion of AERR as appropr
96. ls are synchronous to SMBCLK TCK and SMBCLK can be asynchronous to all other clocks 3 8 Access Port TAP Connection Depending on the voltage levels supported by other components in the Test Access Port TAP logic it is recommended that the Pentium III Xeon processor at 600 MHz be first in the TAP chain and followed by any other components within the system A voltage translation buffer should be used to drive the next device in the chain unless a component is used that is capable of accepting a 2 5V input Similar considerations must be made for TCK TMS and TRST Multiple copies of each TAP signal may be required if multiple voltage levels are needed within a system NOTE TDI is pulled up to VCCTAp with 150 ohms on the Pentium Ill Xeon processor at 600 MHz cartridge An open drain signal driving this pin must be able to deliver sufficient current to drive the signal low Also no resistor should exist in the system design on this pin as it would be in parallel with this resistor 15 s es s wenn nn sammen we w mwn Sw o Kee K A RR S KRSR ew eee ANI ELECTRICAL SPECIFICATIONS A Debug Port is described in Chapter 8 The Debug Port must be placed at the start and end of the TAP chain with TDI to the first component coming from the Debug Port and TDO from the last component going to the Debug Port In an MP system be cautious when including an empty SC330 connector in the scan chain All connectors in the scan chain must have a pro
97. manufacturer Consult your fan manufacturer and or fan documentation for specifications 86 msu eS oe cee we mew we Se re A A RR S KRSR ew ee r n R 8 w BOXED PROCESSOR SPECIFICATIONS Figure 39 Front View Space Recommendation for the Auxiliary Fan 9 3 2 2 Fan power recommendations for auxiliary fan To facilitate power to the auxiliary fan and provide fan monitoring a fan sense capable power header may be provided on the baseboard near every processor that may need an auxiliary fan Although the boxed processor does not ship with an auxiliary fan it is highly recommended that a power header be provided It is 87 mw eS oe cee we ewww Se oe A A m R Ker ee AS BOXED PROCESSOR SPECIFICATIONS also recommended that the power header be consistent with the power header for other boxed processors that feature a fan sense capable fan heat sink Figure 40 shows the boxed processor s standard fan heat sink power cable connector Table 48 shows the boxed processor s standard fan power cable connector requirements The actual requirements for the auxiliary fan power may vary Consult your fan manufacturer and or fan documentation for specifications Straight square pin 3 pin terminal housing with polarizing ribs and friction locking ramp 0 100 pin pitch 0 025 square pin width Waldom Molex P N 22 01 3037 or equivalent Match with straight pin friction lock header on motherboard Waldom Molex P N 22 23 2031 AMP P N 640456
98. meter mn mex na s as Cr Woes lt T10 RESET Pulse Width NOTES 3 These specifications are tested during manufacturing Valid delay timings for these signals at the processor core assume a 50 ohms termination to 1 5V A minimum of 3 clocks must be guaranteed between two active to inactive transitions of TRDY RESET can be asserted active asynchronously but must be deasserted synchronously to the bus clock After the bus ratio on A20M IGNNE and LINT 1 0 are stable VCC_CORE and BCLK are within specification and PWRGD is asserted See Figure 8 40 amp 41 6 Specification is for a minimum 0 40V swing from Vref 200 mV to Vref 200 mV This assumes an edge rate of 3V ns aaron gt Table 14 CMOS TAP Clock and APIC Signal Groups AC Specifications at the processor Core 1 2 Max Unit Figure Notes 7 T14 CMOS Input Pulse Width 2 BCLKs Figure 5 Active and Inactive except PWRGD and states LINT 1 0 T15 PWRGD Inactive Pulse 10 BCLKs Figure 5 4 Width Figure 9 NOTES 1 These specifications are tested during manufacturing 2 Valid delay timings for these signals are specified into 100 ohms to 2 5V 3 When driven inactive or after VCC_CORE and BCLK become stable PWRGD must remain below VIL MAX from Table 8 until all the voltage planes meet the voltage tolerance specifications in Table 5 and BCLK has met the BCLK AC specifications in Table 11 for at least 10 clock cycles PWRGD mus
99. n the processor is not operating such as at initial system power up or if there is no power input to the processor the input should be driven in such a way that no more than 20 mA can flow into the input assuming it is connected to ground This is equivalent to using a 270 ohm or higher pull up resistor tied to a typical 5V supply as the only source for driving the input high 3 11 AGTL System Bus Specifications Table 11 below lists parameters controlled within the Pentium Ill Xeon processor at 600 MHz to be taken into consideration during simulation The input buffers determine valid high and low levels by using a reference voltage VREF that is generated internally on the processor cartridge from VTT VREF should be set to the same level for other AGTL logic using a voltage divider on the baseboard It is important that the baseboard impedance be held as tight as possible and that the intrinsic trace capacitance for the AGTL signal group traces is known and well controlled See Layout Guidelines section 2 4 for impedance recommendations 21 em o we A III A K A RR S KRSR ew eee ANI ELECTRICAL SPECIFICATIONS ae 11 a Parameters for the AGTL Bus Jemio a Reference Voltage ViT 23V1rT 129 Vr V 2 50mV 50mV 1 The Pentium IIl Xeon processor at 600 MHz contains AGTL termination resistors on the processor NOTES 2 VREF is generated on the processor substrate 3 12 System Bus AC Specifications The system bus
100. nabling Details Notes follow 60 12 wenn nnn sammen we www r R K e KR w oe K o A e ee AS MECHANICAL SPECIFICATIONS 277 009 174 215 D10 4 8402 032 FRONTSIDE HEIGHT 4 777 036 4 836 008 BACKSIDE HEIGHT 297 016 cd LS Figure 25 SEC Cartridge Retention Enabling Details Maximum protrusions of the mechanical heat sink attach media into cartridge during assembly or in an installed condition not to exceed 0 160 from external face of thermal plate Specified cover retention indent dimension is at the external end of the indent Indent walls have 1 0 degree draft with the wider section on the external end Clip extension on internal surface of retention slots should be as little as possible and not to exceed 0 040 Tapped holes for cooling solution attach Max torque recommendation for a screw in tapped hole is 8 1 inch lb 61 mru eS oe cee we A m r R K e KR Sw ew ew ee AI MECHANICAL SPECIFICATIONS 7 1 Weight The maximum weight of a Pentium III Xeon processor at 600 MHz and thermal solution is approximately 500 grams 7 2 Cartridge to Connector Mating Details The staggered edge connector layout of the Pentium lll Xeon processor at 600 MHz makes the processor susceptible to damage from cartridge insertion while power is applied to the connector Extra care should be taken to ensure that this does not occur The electrical and mechanical integrity of the processor edge fingers
101. nse agent the agent responsible for completion of the current transaction and must connect the appropriate pins of all Pentium Ill Xeon processor at 600 MHz system bus agents 10 1 45 RSP I The RSP Response Parity signal is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection It must connect the appropriate pins of all Pentium Ill Xeon processor at 600 MHz system bus agents A correct parity signal is high if an even number of covered signals is low and low if an odd number of covered signals are low While RS 2 0 000 RSP is also high since this indicates it is not being driven by any agent guaranteeing correct parity 10 1 46 SA 2 0 1 The SA Select Address pins are decoded on the SMBus in conjunction with the upper address bits in order to maintain unique addresses on the SMBus in a system with multiple Pentium Ill Xeon processors at 600 MHz To set an SA line high a pull up resistor should be used that is no larger than 1KQ To set an SA line as low the pin can be left unconnected SA2 can also be tri stated to define additional addresses for the thermal sensor A tri state or Z state on this pin is achieved by leaving this pin unconnected Of the addresses broadcast across the SMBus the memory components claim those of the form 1010XXYZb The XX and Y bits are used
102. nverter Guidelines s Pentium II Xeon processor Intel 450NX PCIset AGTL Layout Guidelines Order Number 243790 e Pentium IlI Xeon Processor System Compatibility Guidelines Order Number 245248 e Flexible Motherboard Power Distribution amp Control for Pentium II Xeon Processors Order Number 245245 e Pentium III Xeon Processor at 600 MHz Thermal Solutions Guidelines Order Number 245246 s Pentium III Xeon Processor at 600 MHz EMI Guidelines Order Number 245250 s es eS oe cee we ewww Se o A A ew ee AI ELECTRICAL SPECIFICATIONS 3 ELECTRICAL SPECIFICATIONS 3 1 System Bus and VREF The Pentium Ill Xeon processor at 600MHz signals uses a variation of the Pentium Pro processor GTL signaling technology The Pentium Ill Xeon processor at 600 MHz differs from the Pentium Il processor and Pentium Pro processor in its output buffer implementation The buffers that drive most of the system bus signals on the Pentium III Xeon processor at 600 MHz are actively driven to V 7 for one clock cycle after the low to high transition to improve rise times and reduce noise These signals should still be considered open drain and require termination to a supply that provides the high signal level Because this specification is different from the standard GTL specification it is referred to as Assisted Gunning Transistor Logic AGTL in this document AGTL logic and GTL logic are compatible with each other and may both be u
103. o HALT States Snoop events that occur during a transition into or out of Sleep state will cause unpredictable behavior Therefore transactions should be blocked by system logic during these transitions In the Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals immediately after the assertion of the SLP pin one exception is RESET which causes the processor to re initialize itself The system core logic must detect these events and deassert the SLP signal and subsequently deassert the STPCLK signal for interrupts for the processor to correctly interpret any bus transaction or signal transition Once in the Sleep state the SLP pin can be deasserted if another asynchronous event occurs No transitions or assertions of signals are allowed on the system bus while the Pentium III Xeon processor at 600 MHz is in Sleep state Any transition on an input signal with the exception of SLP or RESET before the processor has returned to Stop Grant state will result in unpredictable behavior If RESET is driven active while the processor is in the Sleep state and held active as specified in the RESET pin specification then the processor will reset itself ignoring the transition through Stop Grant State If RESET is driven active while the processor is in the Sleep State and normal operation is desired the SLP and STPCLK should be deasserted immediately after RESET is asserted 5
104. o a voltage plane Similarly all VSS pins must be connected to a system ground plane s es eS oe cee we A Sw o Kee K A RR S KRSR ew eee ANI ELECTRICAL SPECIFICATIONS 3 3 Decoupling Guidelines Due to the large number of transistors and high internal clock speeds the Pentium III Xeon processor at 600 MHz is capable of generating large average current swings between low and full power states This causes voltages on power planes to sag below their nominal values if bulk decoupling is not adequate Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 5 Failure to do so can result in timing violations or a reduced lifetime of the component 3 3 1 VCC_CORE The power input should provide bulk capacitance with a low Effective Series Resistance ESR and the system designer must also control the interconnect resistance from the regulator or VRM pins to the SC330 connector Simulation is required for first and second order characterization Bulk decoupling for the large current swings when the part is powering on or entering exiting low power states is provided on the voltage regulation module VRM defined in the VRM 8 3 DC DC Converter Design Guidelines The input to VCC_CORE should be capable of delivering a recommended minimum dICCCORE4t while maintaining the required tolerances each of which is defined in Table 6 See the Flexible Motherboard Pow
105. olute Maximum Specifications then the Worst Case Undershoot Magnitude must be measured and the Pulse Duration of the Undershoot must be accounted for Pulse Duration measurements determine the total amount of time that the BCLK signal spends below GND Measuring from the earliest Falling Edge GND crossover to the latest Rising Edge GND crossover provides the worst case Undershoot Pulse Duration When compared to the Specification Table the Pulse Duration and the Worst Case Undershoot Magnitude then determines if the system meets the BCLK Overshoot Undershoot Specifications Note the measured Pulse Duration must be less than or equal to the Specified Max Pulse Duration for a given Worst Case Undershoot Magnitude 4 3 4 2 5V TOLERANT BUFFER RINGBACK SPECIFICATION The ringback specification is the voltage at a receiving pin that a signal rings back to after achieving its maximum absolute value See Figure 14 for an for an illustration of ringback Excessive ringback can cause false signal detection or extend the propagation delay Violations of the signal ringback specification are not allowed for 2 5V tolerant signals Table 25 shows signal ringback specifications for the 2 5V tolerant signals to be used for simulations at the processor core Table 25 Signal Ringback Specifications for 2 5V Tolerant Signal Simulation at the processor Core Maximum Ringback Input Signal Group Transition with Input Diodes Present rm w we ewww oe A A ew ee r n
106. om se care paa Actress Byte pointer comi resent a rre Date pes Bye poiner oon not present A EN A R Address pm eat pases Bve poner Donna presen 2 ERA dd el processor Core Family From CPUID Ie ee processor Core Model From CPUID A TD processor Core Stepping From CPUID Reserved AAA ES AAN AAA OCVR option 2 Voltage in mV OCVR option 2 Edge finger tolerance in mV A ee AE NT Maximum Core Frequency 16 bit binary number in MHz L OCVR option 1 Voltage in mV A A OCVR option 1 Edge finger tolerance in mV reci ans pe sees E ss O e teen L2 CACHE 25h 32 Reserved Reserved CORE 16h processor Core Type From CPUID 44 msu eS oe cee s sew ewww Se oe K S g Kee RR ew eee AI PROCESSOR FEATURES a i 0 L2 Cache Size 16 Bit binary number in Kbytes a eses H Po 16 OCVR Output Voltage ID Voltage in mV OCVR Output Voltage Edge finger tolerance in mV Tolerance High OCVR Output Voltage Edge finger tolerance in mV Tolerance Low Oooo EEC H A EEC ION ENCINA IONES ATT ree Stare Sane O sees severas HH H OA TT HT HTH HT Pe resorts seot ereton number SS esencias A a HT METEO o ECC sereo O sees rene A a HT e res H A oone O ro na ren Sera signature Preset 0 Na Present ae H t Preset 0 Not Present 1 Thermal Sense Device 1 Present 0 Not Present Present 1 Thermal Reference Byte 1 Present 0 Not Present Present
107. on processor at 600 MHz that can be powered with either 5 0 or 12 0 volts applied to its VCC_CORE pins e HV_EN pin added to the SC330 1 definition as a way of differentiating a 5 12V Pentium Ill Xeon processor from a 2 8V Pentium Ill Xeon processor HV_EN is tied to VSS ground on the 5 12V Pentium Ill Xeon processor and is high impedance floating on the 2 8V Pentium IIl Xeon processor This is a reserved no connect pin on Pentium Ill Xeon processors e Processor substrate The structure on which components are mounted inside the S E C cartridge with or without components attached e Processor core The processor s execution engine e S E C cartridge The processor packaging technology used for the Pentium II Xeon processor family S E C is short for Single Edge Contact cartridge e Streaming SIMD Extensions A new set of instructions supported by Intel processors beginning with the Pentium Ill Xeon processor Single Instruction Multiple Data SIMD extensions significantly accelerate performance of 3D graphics Besides 3D graphics improvements the extensions also include additional integer and cacheability instructions that improve other aspects of performance e Thermal plate The surface used to connect a heat sink or other thermal solution to the processor Additional terms referred to in this and other related documentation msu Sm RRR nn cee we ewww oe A A ew ee r n R 8 w TERMINOLOGY
108. or power delivery schemes Further details of this implementation is described in the Flexible Motherboard Power Distribution amp Control for Pentium IlI Xeon Processors Order Number 245245 The Pentium III Xeon processor at 600 MHz incorporates a new pin A3 HV_EN as a method to identify its ability to be powered by a 5V or 12V power supply The HV_EN signal is used as a way of differentiating a 5 12V Pentium Ill Xeon processor cartridge from a 2 8V Pentium Ill Xeon processor HV_EN is tied to VSS ground on the 5 12V Pentium lll Xeon processor and is high impedance floating on the 2 8V Pentium Ill Xeon processor This is a reserved no connect pin on Pentium III Xeon processors Since the L2 Cache is integrated in the core the Pentium III Xeon processor at 600 MHz does not require a VID code to specify cache voltage the VID_L2 lines on the Pentium IIl Xeon processor at 600 MHz are all left open on the cartridge VID_CORE 4 0 controls the voltage supply to the processor as shown in Table 2 They are not driven signals but are either an open circuit or a short circuit to VSS The combination of opens and shorts defines the voltage required by the processor the VID CORE lines on the 5 12V Pentium III Xeon processor are all left open on the cartridge The VID pins support variations in processor core voltages among processors in the SC330 processor family Table 2 shows the 12 s es eS oe cee we A Sw o Kee K
109. ormation see the Pentium II processor Developers Manual Order Number 243502 Due to not being able to recognize bus transactions during Sleep state SMP systems are not allowed to have one or more processors in Sleep state and other processors in Normal or Stop Grant states simultaneously 5 1 1 NORMAL STATE STATE 1 This is the normal operating state for the processor 5 1 2 AUTO HALT POWER DOWN STATE STATE 2 Auto HALT is a low power state entered when the Pentium Ill Xeon processor at 600 MHz executes the HALT instruction The processor will issue a normal HALT bus cycle on BE 7 0 and REQ 4 0 when entering this state The processor will transition to the Normal state upon the occurrence of SMI BINIT INIT or LINT 1 0 NMI INTR RESET will cause the processor to immediately initialize itself SMI will cause the processor to execute the SMI handler The return from the SMI handler can be to either Normal Mode or the Auto HALT Power Down state See Chapter 11 in the Intel Architecture Software Developer s Manual Volume 3 System Programming FLUSH will be serviced during Auto HALT state The on chip first level caches and external second level cache will be flushed and the processor will return to the Auto HALT state A20M will be serviced during Auto HALT state the processor will mask physical address bit 20 A20 before any look up in either the on chip first level caches or external second level cache and before a
110. ors 10 1 25 IERR O The IERR Internal Error signal is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the Pentium Ill Xeon processor at 600 MHz system bus This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until it is handled in software or with the assertion of RESET BINIT or INIT 10 1 26 IGNNE 1 The IGNNE Ignore Numeric Error signal is asserted to force the processor to ignore a numeric error and continue to execute non control floating point instructions If IGNNE is deasserted the processor generates an exception on a non control floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 is set IGNNE is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding I O Write bus transaction During active RESET the Pentium Ill Xeon processor at 600 MHz begins sampling the A20M IGNNE and LINT 1 0 values to determine the ratio of core clock frequency to bus clock frequency See Table 1 On the active to inactive transition of RESET the Pentium Ill Xeon processor at 600 MHz latches these signals and freezes the frequency ratio internally Sys
111. ough the thermal plate and other paths The power dissipation is a combination of power from the OCVR the processor core with integrated L2 Cache and the AGTL bus termination resistors The overall system thermal design must comprehend the Max Thermal power The combined power from the processor core including the second level cache and the OCVR that dissipates through the thermal plate is the Max Thermal power The heat sink should be designed to dissipate the Max Thermal power The thermal sensor feature of the processor cannot be used to measure TpLATE The TpLATE specification must be met regardless of the reading of the processor s thermal sensor in order to ensure adequate cooling for the entire Pentium III Xeon processor at 600 MHz 53 msu Sm RRR oe cee ewe w mwn vvv mu sw wn ew m w R R e THERMAL SPECIFICATIONS Table 42 Power Dissipation Frequency 5 12V Cartridge Cartridge Thermal Thermal Power W Power W Power 4 7 W sm 165 35 8 es 25 woo 192 5 2 6 3 800 MHz 22 2 2 ss miz 259 f e Prove 270 CO ems gt E AAA e NOTES 1 These values are specified at nominal VCC_CORE for the processor core with integrated L2 cache 2 Core power indicates the combined worst case power that can be dissipated by the processor 8 L2 cache This value will be determined after the product has been characterized 3 Cartridge power indicates the worst case power that can be d
112. r above the minimum TPLATE specified in Table 42 Power from the processor core is transferred to the thermal plate at 2 locations on all Pentium Ill Xeon processor at 600 MHz products Figure 20 and 21 shows the locations for PLATE measurement directly above these transfer locations Thermocouples are used to measure PLATE and special care is required to ensure an accurate temperature measurement Before taking any temperature measurements the thermocouples must be calibrated When measuring the temperature of a surface errors can be introduced in the measurement if not handled properly Such measurement errors can be due to a poor thermal contact between the thermocouple junction and the measured surface conduction through thermocouple leads heat loss by radiation and convection or by contact between the thermocouple cement and the heat sink base To minimize these errors the following approach is recommended e Use 36 gauge or finer diameter K T or J type thermocouples Intel s laboratory testing was done using a thermocouple made by Omega part number 5TC TTK 36 36 e Attach each thermocouple bead or junction to the top surface of the thermal plate at the locations specified in Figure 19 using high thermal conductivity cements e A thermocouple should be attached at a 0 angle if no heat sink is attached to the thermal plate If a heat sink is attached to the thermal plate but the heat sink does not cover the location specified for TPLATE
113. r connecting to the TDI of the first processor no external pull up is required However the last processor of the chain does require a 150 ohm pull up resistor to VCCtap at TDO before passing the TAP signal to the next device in the chain 8 1 6 4 Signal Note TCK and TMS WARNING A significant number of target systems have had signal integrity issues with the TCK signal TCK is a critical clock signal and must be routed accordingly make sure to observe power and ground plane integrity for this signal Follow the guidelines below and assure the quality of the signal when beginning use of an ITP to debug your target Due to the number of loads on the TCK signal special care should be taken when routing this Poor routing can lead to multiple clocking of some agents on the debug chain usually on the falling edge of TCK This causes information to be lost through the chain and can result in bad commands being issued to some agents on the chain Systems using other TCK routing schemes particularly those with T or Y configurations where the trace from the source to the T is long could have signal integrity problems The suggested routing scheme is to drive each of the agent TCK signals individually from a buffer device Figure 31 shows how the TCK signal should be routed to the agents in a 2 way Pentium Ill Xeon processor at 600 MHz system incorporating the Intel 840 PClset A Bessel filter is recommended over a series termination
114. rchitecture 5 2 1 PROCESSOR INFORMATION ROM The Pentium Ill Xeon processor at 600 MHz implements previously defined fields in the processor information ROM PI ROM to allow visibility of core and On Cartridge Voltage Regulation OCVR voltage requirements These features are present in SC330 products but are used in a different way in the Pentium Ill Xeon processor at 600 MHz The Pentium Ill Xeon processor at 600 MHz implements the OCVR device This provides the flexibility to accommodate products with voltage input of 2 8V for one product version and 5V or 12V for a different product version The 2 8V or 5V version is indicated in the PI ROM OCVR option 1 Input Voltage ID field while the 12V version is indicated in the OCVR option 2 Input Voltage ID PI ROM field The implementation of the PI ROM in Pentium lll Xeon processor at 600 MHz allows software to view the desired voltage outputs of the power source VRM or Power Supply feeding the OCVR and of the OCVR itself Software could compare those values to actual power source OCVR outputs using an A D converter and determine if the power source and OCVR are operating correctly The implementation of the PI ROM gives system designers a means of determining the proper OCVR Output Voltage requirements Without these fields the baseboard has no way of determining the OCVR Output Voltage requirements The fields defined for the Pentium Ill Xeon processor at 600 MHz coincide a
115. rflow over the passive heat sink A standard 40mm 50mm or 60mm fan can be attached System integrators must evaluate the thermal performance of their system see above and consider the baseboard manufacturers recommendations for thermal management before deciding if an auxiliary fan is warranted If an auxiliary fan is needed e g for the front processor in a multiprocessor system it may be attached to the face of the boxed processors passive heat sink To facilitate this the boxed processor s passive heat sink will include features in the heat sink fins onto which fan mounting hardware can be attached The appropriate fan attach hardware will be included with the boxed Pentium III Xeon processor at 600 MHZ if necessary The boxed Pentium Ill Xeon processor at 600 MHz does not ship with an auxiliary fan Figure 37 Conceptual Views of the Boxed Processor with Attached 40mm and 50mm Auxiliary Fan fan not included with the Boxed Processor 9 3 2 1 Clearance recommendations for auxiliary fan If an auxiliary fan is used clearance must be provided in front of the boxed processor passive heat sink to accommodate the mechanical and airflow clearance requirements of the fan and mounting hardware Baseboard mounted components and chassis members should not violate the clearance requirements for the auxiliary fan Figure 38 and Figure 39 show the clearance recommended for the fan and air inlet Required airspace clearance for fans may vary by
116. rgest voltage potential below ground However the Absolute Maximum Specifications can be relaxed for BCLK Undershoot if the Pulse Duration is accounted for under worst case conditions Thus a system with BCLK Undershoot below 0 7V must ensure that the worst case Pulse Duration is less than or equal to the allowed Max Pulse Duration for the Worst Case Undershoot Magnitude See the Table 24 Table 24 BCLK Overshoot Undershoot Specifications 1 2 3 4 5 6 7 Undershoot Magnitude Max Pulse Duration nS NOTES Overshoot is measured relative to VSS Undershoot is measured relative to VTT Overshoot Undershoot Pulse Duration is measured relative to 1 635V Rinback below VTT cannot be subtracted from Overshoots Undershoots Lesser Undershoot does not allocate longer or larger Overshoot OEM s are encouraged to follow Intel provided layout guidelines All values specified by design characterization NOOR WON gt 4 3 3 Measuring BCLK Overshoot Undershoot Overshoot on BCLK is measured relative to GND By probing BCLK with an oscilloscope where the probe GND lead makes good contact to a processor GND pin BCLK Overshoot can be accurately measured to determine if the system meets BCLK Overshoot Absolute Maximum Specifications Undershoot on BCLK is also measured relative to GND again by probing BCLK with an oscilloscope where the probe GND lead makes good contact to a processor GND pin If the system does not meet the BCLK Undershoot Abs
117. rn invalid data until another command is sent to the thermal sensor This one shot feature is currently susceptible to failure and should not be used i e don t issue one shot commands when in auto convert mode 5 2 6 THERMAL SENSOR REGISTERS 5 2 6 1 Thermal Reference Registers The processor core and thermal sensor internal thermal reference registers contain the thermal reference value of the thermal sensor and the processor core thermal diodes This value ranges from 127 to 128 decimal and is expressed as a two s complement eight bit number These registers are saturating i e values above 127 are represented at 127 decimal and values below 128 are represented as 128 decimal 5 2 6 2 Thermal Limit Registers The thermal sensor has two thermal limit registers they define high and low limits for the processor core thermal diode The encoding for these registers is the same as for the thermal reference registers If the diode thermal value equals or exceeds one of its limits then its alarm bit in the Status Register is triggered 49 mw eS oe cee we ewww Se oe A A e ee A PROCESSOR FEATURES 5 2 6 3 Status Register The status register shown in Table 37 indicates which if any thermal value thresholds have been exceeded It also indicates if a conversion is in progress or if an open circuit has been detected in the processor core thermal diode connection A status register read is required to clear any alarm bits that are set A su
118. rocessor at 600 MHz The thermal sensor feature is only available while VCC_CORE and VCC_SMB are at valid levels and the processor is not in a low power state 5 2 5 THERMAL SENSOR SUPPORTED SMBUS TRANSACTIONS The thermal sensor responds to five of the SMBus packet types write byte read byte send byte receive byte and ARA Alert Response Address The send byte packet is used for sending one shot commands only The receive byte packet accesses the register commanded by the last read byte packet lf a receive byte packet was preceded by a write byte or send byte packet more recently than a read byte packet then the behavior is undefined Tables 31 through 35 diagram the five packet types In these figures S represents the SMBus start bit P represents a stop bit Ack represents an acknowledge and represents a negative acknowledge The thermal sensor transmits those bits that are shaded and the SMBus host controller transmits those bits that are non shaded Table 36 shows the encoding of the command byte Table 31 Write Byte ESA bas Cs ess wae Aa Command SS M e E Table 32 Read Byte SMBus Packet ES ess wrie T T Commana Aek 5 sss eed mae T TTS Table 33 Send Byte SMBus Packet Ce p e o O cond 0 e Table 34 Receive Byte SMBus Packet a pr 48 msu s Sm RRR nn sammen we ewww ww oe K A RR S KRSR ew ee IS PROCESSOR FEATURES 1 This is an 8 bit field The devic
119. s closely as possible with those for the Pentium III Xeon processor The meaningless for Pentium Ill Xeon processor at 600 MHz L2 Cache Voltage field is replaced with a more useful OCVR Output field The Pentium Ill Xeon processor at 600 MHz SC330 1 has a pin defined A56 VIN_SENSE that allows the baseboard to directly measure the actual OCVR input voltage and pin B83 AN_CORE_VSENSE that is an analog representation of the voltage at the OCVR output This voltage can be compared with the desired voltage indicated by the PIR field to determine if the OCVR input output voltage is varying from desired levels 42 zum w we www III KRSR Kee KE o A m R eee r M R 8 w PROCESSOR FEATURES Systems implementing analog sensing should read the PIROM first then compare that value with the measured VIN_SENSE rather than assuming any specific value The value of AN_CORE_VSENSE is implementation dependent and cannot be assumed to be any particular value Systems may derive benefit by monitoring its stability but should not make assumptions about its value In Table 26 text in bold represents the new defined fields for the Pentium III Xeon processor at 600 MHz 43 om eS oe cee we ewww oe ee ew ee AA PROCESSOR FEATURES Table 26 processor Information ROM Format OffsevSecton oras Funn O os O OE O emon e Daroma Teas e rocescorData tress Bye HT pa ache Data ncctess Bve pomer Ooh not presen p
120. sed on the same system bus For more information on the GTL specification see the Pentium Pro Family Developer s Manual Volume Order Number 242690 AGTL inputs use differential receivers that require a reference signal VREF VREF is used by the receivers to determine if a signal is a logical O or a logical 1 The Pentium III Xeon processor at 600 MHz generates its own version of VREF VREF must be generated on the baseboard for other devices on the AGTL system bus Termination is used to pull the bus up to the high voltage level and to control signal integrity on the transmission line The processor contains on cartridge termination resistors that provide termination for the AGTL bus These specifications assume the equivalent of 5 FIVE AGTL loads and termination resistors to ensure the proper timings on rising and falling edges See test conditions described with each specification Like the Pentium lll Xeon processor the timing specifications of the Pentium Ill Xeon processor at 600 MHz are defined to points internal to the processor packaging Analog signal simulation of the system bus is required when developing Pentium lll Xeon processor at 600 MHz based systems to ensure proper operation over all conditions Pentium III Xeon Processor Signal Integrity Models are available for simulation 3 2 Power and Ground Pins By implementing an On Cartridge Voltage Regulator OCVR the Pentium III Xeon processor at 600 MHz eliminates
121. sensor is composed of control logic SMBus interface logic a precision analog to digital converter and a precision current source The thermal sensor drives a small current through the p n junction of a thermal diode located on the same silicon die as the processor core The forward bias voltage generated across the thermal diode is sensed and the precision A D converter derives a single byte of thermal reference data or a thermal byte reading System management software running on the processor or on a microcontroller can acquire the data from the thermal sensor to thermally manage the system Upper and lower thermal reference thresholds can be individually programmed for the thermal diode Comparator circuits sample the register where the single byte of thermal data thermal byte reading is stored These circuits compare the single byte result against programmable threshold bytes The alert signal on the Pentium Ill Xeon processor at 600 MHz SMBus SMBALERT will assert when either threshold is crossed To increase the usefulness of the thermal diode and thermal sensor Intel has added a new procedure to the manufacturing and test flow of the Pentium IIl Xeon processor at 600 MHz This procedure determines the Thermal Reference Byte and programs it into the processor Information ROM The Thermal Reference Byte is 47 mw eS oe cee we ewww Se oe A A e ee A PROCESSOR FEATURES uniquely determined for each unit The procedure causes
122. specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel swebsite at http www intel com Copyright O Intel Corporation 1999 2000 Third party brands and names are the property of their respective owners PENTIUMO III XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache TABLE OF CONTENTS PRODUCT FEATURES it aa nda I 1 INTRODUCTIION c sscsssssssssssssssessscessscossncossncosssssessssossssosassssssesssscsssscessscessscesssconssconsascusascosassossssosaesssscosssceseseess 6 2 1 S E C CARTRIDGE TERMINOLOGY 22 REFERENCES eas taer eist 3 ELECTRICAL SPECIFICATIONS SYSTEM BUS AND VRE POWER AND GROUND PINS DECOUPLING GUIDELINES 3 3 J CLOCK FREQUENCIES AND SYSTEM BUS CLOCK RATIOS sese MIXING PROCESSORS OF DIFFERENT FREQUENCIES VOLTAGE IDENTIFICATION cio EEEE AE ETE EEEE dottar SYSTEM BUS UNUSED PINS AND TEST PINS eee Ked SYSTEM BUS SIGNAL GROUPS s ni ranna eia ealon notte eneeier EEE EE arena ree erei Eene 7 2 ASYNCHRONOUS VS SYNCHRONOUS FOR SYSTEM BUS SIGNALS ACCESS PORT TAP CONNECTION ii aee E E E E EEEE SS MAXIMUM RATINOS sese eee U PROCESSOR DC SPRCIFICATIONS sse 1 AGTL SYSTEM BUS SPECIFICATIONS aaa ae ao 2 SYSTEM BUSAC SPECIFICATION S ssc ccccesectusancos tit n SIGNAL QUALI
123. stem chassis across the heat sink and out of the system chassis System integrators should perform thermal testing using thermocouples see the section entitled Processor Thermal Analysis to evaluate the thermal efficiency of the system 9 3 2 Boxed Processor Passive Heat sink Performance The boxed processor s passive heat sink is designed to provide effective heat transfer between the processor package thermal plate and the air immediately surrounding the heat sink The direction and temperature of air flowing across the heat sink variably affects the efficiency of the heat sink Figure 36 shows the thermal efficiency of the boxed processor heat sink using three different directions of airflow horizontal top down and normal to the plane of the thermal plate The performance characterization was completed in a wind tunnel using a processor running at maximum power and at maximum thermal specification The characterization assumes that air entering the heat sink is at constant temperature and uniformly traverses the heat sink and that heated air is evacuated from the chassis and is not re circulated The characterization also assumes natural obstructions such as the motherboard in a top down airflow model To determine if a particular chassis has appropriate airflow to effectively cool the processor measure the upstream temperature Tavsenr the ambient air temperature within the chassis and the velocity of the air entering the heat sin
124. t allocate longer or larger Undershoot OEM s are encouraged to follow Intel provided layout guidelines All values specified by design characterization ON OahoN 4 3 Non GTL Signal Quality Specifications There are three signal quality parameters defined for non AGTL signals Overshoot Undershoot Ringback and Settling Limit The three signal quality parameters are shown in Figure 14 for the non AGTL signal group at the processor core pads Overshoot Undershoot shown in Figure 14 is for illustrative purposes only to help explain Ringback and Settling Limit Refer to Figure 13 for an illustration of Overshoot Undershoot specifications 35 es eS nn cee we mew r R K e KR Se o we ew ee AI SIGNAL QUALITY Overshoot Settling Limit Rising Edge Ringback Falling Edge Ringback Voltage Settling Limit Undershoot Figure 14 Non AGTL Overshoot Undershoot Seitling Limit and Ringback 4 3 1 2 5V Signal Overshoot Undershoot Guidelines The Overshoot Undershoot guideline limits transitions beyond V CC or VSS due to fast signal edge rates Refer to Figure 14 for an illustration of Overshoot Undershoot specifications for non AGTL signals The processor may be damaged if Overshoot Undershoot specifications are not met The Overshoot Undershoot specification is shown in Table 23 Table 23 2 5V Tolerant Signal Group Overshoot Undershoot at the Processor Core Pins 1 2 3 4 5 6 7 8 9 Overshoot Undershoot Max Pulse Duration nS
125. t least 2 bus clocks but no longer than 20 bus clocks Table 1 System Bus to Core Frequency Ratio Configuration Ratio of BCLK to 133 MHz EBL PWRUP LINT 1 LINT 0 IGNNE A20M Core Frequency Target Reg 25 22 Frequency Va Gare Wy A Aa ee 2 9 somHz omo H H_ L H p15 667mMHz ooo e I L_ _ H_ CH rjr ad L rjr Tr a i ag Tr TI II 83 Wz 0100 hs _ us SA 800 MHz fot PH es6MHz_ THH oz 999 MHz 101 u Ji n E ans toomH iio H_ H_ H_ I E ngaeng ttm H _ a w H_ IJI EF Fr Fr EEE x x r Iii Tr jr 10 s es s wenn nn sammen we w mwn Sw o Kee K A RR S KRSR ew eee ANI ELECTRICAL SPECIFICATIONS NOTE The frequency multipliers supported are shown in Table 1 other combinations will not be validated nor supported by Intel Also each multiplier is only valid for use on the product of the frequency indicated in Table 1 Clock multiplying within the processor is provided by the internal PLL requiring a constant frequency BCLK input The BCLK frequency ratio cannot be changed dynamically during normal operation or any low power modes The BCLK frequency ratio can be changed when RESET is active assuming that all RESET specifications are met See Figure 1 for the timing relationship between the system bus multiplier signals RESET and normal processor operation Using CRESET CMOS Reset and the timing shown in Figure 1 the circuit in Figure 2 can be used to
126. t rise glitch free and monotonically to 2 5V 4 If the BCLK signal meets its AC specification within 150ns of turning on then the PWRGD Inactive Pulse Width specification is waived and BCLK may start after PWRGD is asserted PWRGD must still remain below ViL_mAx until all the voltage planes meet the voltage tolerance specifications 24 msu s svenn nn sammen we ewww ww o A A RR S KRSR ew eee AI ELECTRICAL SPECIFICATIONS Table 15 System Bus AC Specifications Reset Conditions 1 T16 Reset Configuration Signals Figure 8 Before deassertion of A 14 05 BHOR FLUSH INIT Setup Time T17 Reset Configuration Signals Figure 8 After clock that A 14 05 BRO FLUSH deasserts RESET INIT Hold Time Reset Configuration Signals mS Figure 8 Before deassertion of A20M IGNNE LINT 1 0 RESET Setup Time Reset Configuration Signals BCLKs Figure 8 After assertion of A20M IGNNE LINT 1 0 RESET 1 Delay Time Reset Configuration Signals 2 20 BCLKs Figure 8 After clock that A20M IGNNE deasserts RESET LINT 1 0 Hold Time Figure 9 NOTES 1 For a Reset the clock ratio defined by these signals must be a safe value their final or lower multiplier within this delay unless PWRGD is being driven inactive Table 16 System Bus AC Specifications APIC Clock and APIC I O at the processor Core 1 TA Parameter T21 PICCLK Frequency T29A PICD 1 0 Valid Delay 1 5 8 7 nS Figure 5 Rising Edge T29B
127. table before a subsequent rising edge of PWRGD It must also meet the minimum pulse width specification in Table 13 and be followed by an 8 mS RESET pulse The PWRGD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation Current VRM 8 3 on baseboard specification requires VRM_PWRGD to be asserted when its output is within 12 of nominal value In the Pentium Ill Xeon processor at 600 MHz PWRGD is logically ANDed with OCVR_OK before being applied to the core PWRGD_CORE According to legacy EMTS documents RESET negation is expected 1 mS after seeing PWRGD_CORE becoming valid by the processor core The OCVR is not expected to provide a valid OCVR_OK signal assertion within 13 mS of seeing 90 of its input voltage The delay before the assertion of OCVR_OK may cause a race condition between RESET and the valid PWRGD_CORE that is seen at the core It is recommended to relax the deassertion of RESET to meet this critical constrain Careful analysis needs to be done in existing platforms Refer to Figure 41 and Figure 42 below for new timing relationship requirements 95 PENTIUMO III XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX RESET VRM_PWRGD CPU_PWR_GD 2 8 5 12V 90 of Vin Nominal l VCC_CPU Vout OCVR Li Vin OCVR Figure 41 PWRGD Relationship at Power On
128. tate or Z state If the designer desires to drive the SA1 or SA2 pin with logic the designer must ensure that the pins are at valid input levels see Table 9 before VCCsmB begins to ramp The system designer must also ensure that their particular system implementation does not add excessive capacitance gt 50 pF to the address inputs Excess capacitance at the address inputs may cause address recognition problems Figure 16 shows a logical diagram of the pin connections Table 40 and Table 41 describe the address pin connections and how they affect the addressing of the devices Table 40 Thermal Sensor SMBus Addressing Address Hex Upper Address1 8 bit Address Word on Serial Bus Slot Select o T BM 3 bro a a a HT A A o o A A e S Ta A E TS NOTES 1 Upper address bits are decoded in conjunction with the select pins 2 A tri state or Z state on this pin is achieved by leaving this pin unconnected Note that system management software must be aware of the slot number dependent changes in the address for the thermal sensor Table 41 Memory Device SMBus Addressing Address Upper Memory Device Addressed Hex Address1 Device Select SA1 SAO OA 7 4 azi 3 haa 2 AOH Ath h 1010 es EEPROM 1 Se a A x lt x lt MC AC CI A CI A AE ACTO A A CI CI S e TT Cawan soo 1 0 1 x ETT MECO o0 1 1 0 x IET Cenan soo 1 1 1 __ ETT Though this addressing scheme is targeted
129. tating Interconnect 2 Way System Bus Signal Agent 0 Pins Agent 1 Pins BREQO BRO BR3 BREQ1 BR14 BRO During power up configuration the central agent must assert its BRO signal All symmetric agents sample their BR 3 0 pins on active to inactive transition of RESET The pin on which the agent samples an active level determines its agent ID All agents then configure their BREQ 3 0 signals to match the appropriate bus signal protocol 10 1 15 CORE_AN_SENSE 0 This signal is tied to the VCC seen at the processor core and represents the output of the OCVR This signal provides the ability to monitor the stability of the OCVR in high reliability applications The voltage seen at this pin is the actual operating voltage of the core with integrated L2 Cache minus IR drops due to trace routing in the Cartridge 10 1 16 D 63 00 1 0 The D 63 00 Data signals are the data signals These signals provide a 64 bit data path between the Pentium Ill Xeon processor at 600 MHz system bus agents and must connect the appropriate pins on all such agents The data driver asserts DRDY to indicate a valid data transfer 10 1 17 DBSY I O The DBSY Data Bus Busy signal is asserted by the agent responsible for driving data on the Pentium Ill Xeon processor at 600 MHz system bus to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on all Pentium
130. te s Pentium III Xeon processor at 600 MHz refers to Pentium Ill Xeon Processors that utilize On Cartridge Voltage Regulator technology or OCVR The OCVR regulates V cc core the appropriate cartridge input voltage to the required processor core voltage Vcc cru The OCVR was developed to provide the necessary regulation to guarantee the highest possible frequency of operation for the 600 MHz Pentium III Xeon processor s Pentium III Xeon processor refers to a Pentium III Xeon Processor at 500MHz or 550MHz a 100MHz system bus without an OCVR and requires separate VCC CORE amp L2 voltage sources s FMB Flexible Motherboard Specification A set of specifications to which a design is targeted to allow forward compatibility with existing and future processors s L1 cache Integrated static RAM used to maintain recently used information Due to code locality maintaining recently used information can significantly improve system performance in many applications The L1 cache is integrated directly on the processor core e L2 cache The L2 cache is integrated directly on the processor core for the Pentium Ill Xeon processor at 600 MHz or is located on the substrate for the Pentium Ill Xeon processor e 2 8V Pentium lll Xeon processor refers to a Pentium Ill Xeon processor at 600 MHz that can be powered with 2 8 volts applied to its VCC_CORE pins e 5 12V Pentium lll Xeon processor refers to a Pentium Ill Xe
131. tem logic must then release these signals for normal operation 10 1 27 INIT 1 The INIT Initialization signal when asserted resets integer registers inside all processors without affecting their internal L1 or L2 caches or floating point registers Each processor then begins execution at the power on reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins of all Pentium Ill Xeon processor at 600 MHz system bus agents If INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built In Self Test BIST 93 PENTIUMO III XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX 10 1 28 INTR see LINT 0 10 1 29 LINT 1 0 1 The LINT 1 0 Local APIC Interrupt signals must connect the appropriate pins of all APIC Bus agents including all processors and the core logic or I O APIC component When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a non maskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default
132. the program at the assembly code level as well as read and write registers memory and I O The on chip debug features will be controlled from a Windows NT 4 0 software application running on a Pentium or Pentium Pro processor based PC with a PCI card slot See Figure 29 E PCI Add In Card LJ Plugs in to your host PC 12 5 in 2m Cable 7 H 2 in Cable H Debug Port Connector Torn J H Connects to Debug E Port on target board Buffer Board 000816a Figure 29 Hardware Components of the ITP 8 1 2 DEBUG PORT CONNECTOR DESCRIPTION 74 mru eS oe cee we A m r R K e KR Se KRSR See K o ng Ree ew ee AI INTEGRATION TOOLS The ITP will connect to the system through the debug port Recommended connectors to mate the ITP cable with the debug port on the board are available in either a vertical or right angle configuration Both configurations fit into the same board footprint The connectors are manufactured by AMP Incorporated and are in the AMPMODU System 50 line Following are the AMP part numbers for the two connectors e Amp 30 pin shrouded vertical header 104068 3 e Amp 30 pin shrouded right angle header 104069 5 NOTE These are high density through hole connectors with pins on 0 050 in by 0 100 in centers Do not confuse these with the more common 0 100 in by 0 100 in center headers The debug port must be mounted on the system baseboard the processor does not contain a debug port 8 1
133. to enable the devices on the cartridge at adjacent addresses The Y bit is hard wired on the cartridge to V SS 0 for the Scratch EEPROM and pulled to VCCsmB 1 for the processor Information ROM The XX bits are defined by the processor slot via the SAO and SA1 pins on the SC330 connector These address pins are pulled down weakly 10 K on the cartridge to ensure that the memory components are in a known state in systems that do not support the SMBus or only support a partial implementation The Z bit is the read write bit for the serial bus transaction The thermal sensor internally decodes 1 of 3 upper address patterns from the bus of the form 0011XXXZb 1001XXXZb or 0101XXXZb The device s addressing as implemented includes a Hi Z state for one address pin SA2 and therefore supports 6 unique resulting addresses The ability of the system to drive this pin to a Hi Z state is dependent on the baseboard implementation The pin must be left floating The system should drive SA1 and SAO and will be pulled low if not driven by the 10 K ohm pull down resistor on the processor substrate Driving these signals to a Hi Z state would cause ambiguity in the memory device address decode possibly resulting in the devices not responding thus timing out or hanging the SMBus As before the Z bit is the read write bit for the serial bus transaction For more information on the usage of these pins see section 5
134. tor dimensions and retention enabling features of the S E C cartridge The processor edge connector defined in this document is referred to as SC330 1 This connector definition is mechanically the same as the existing SC300 See the SC330 connector specifications for further details on the edge connector Table 44 and Table 45 provide the edge finger and SC330 1 connector signal definitions for Pentium III Xeon processor at 600 MHz The signal locations on the SC330 edge connector are to be used for signal routing simulation and component placement on the baseboard THERMAL PLATE HETENTION HOLES 42 PLES j i L HERE CONTACTS AN l 4 4 me001 wmf Figure 22 Isometric View of S E C Cartridge NOTES Use of retention holes and retention indents are optional 11 For SC330 connector specifications see the SC330 Connector Specification 12 All dimensions in inches for figures 23 through 28 58 mru eS oe cee we A m r R K e KR Sw KRSR See K o g Kee mew ee r n R 8 we MECHANICAL SPECIFICATIONS 4 FRON 3 760 012 1 00 016 1 880 012 2 6381 033 IX 6 32UNC X 2B Figure 23 S E C Cartridge Cooling Solution Attach Details Notes follow 59 msu Sm RRR oe cee we mew we Se re A A m R Ke ee r M R 8 w MECHANICAL SPECIFICATIONS 325 004 5 350 008 4 125 002 2X 280 008 GHT 015 6 000 nag Figure 24 S E C Cartridge Retention E
135. ts from the processor are indeterminate unless otherwise specified On observing active RESET all Pentium Ill Xeon processor at 600 MHz system bus agents will deassert their outputs within two clocks A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Pentium II processor Developer s Manual The processor may have its outputs tri stated via power on configuration Otherwise if INIT is sampled active during the active to inactive transition of RESET the processor will execute its Built In Self Test BIST Whether or not BIST is executed the processor will begin program execution at the reset vector default O_FFFF_FFFOh RESET must connect the appropriate pins of all Pentium III Xeon processor at 600 MHz system bus agents 10 1 43 RP I O The RP Request Parity signal is driven by the request initiator and provides parity protection on ADS and REQ 4 0 It must connect the appropriate pins of all Pentium Ill Xeon processor at 600 MHz system bus agents A correct parity signal is high if an even number of covered signals is low and low if an odd number of covered signals are low This definition allows parity to be high when all covered signals are high 10 1 44 RS 2 0 I 97 PENTIUMO III XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX The RS 2 0 Response Status signals are driven by the respo
136. uency of Overshoot Undershoot occurrence relative to a Clock Since the highest frequency of assertion of an AGTL or a CMOS signal is every other clock an AF 1 indicates that the specific Overshoot or Undershoot waveform occurs EVERY OTHER clock cycle e g 1 0 1 0 system bus switching pattern Thus an AF 0 01 indicates that the specific Overshoot or Undershoot waveform occurs 1 time in every 200 CLK cycles The specifications provided in Table 22 show the Maximum Pulse Duration allowed for a given Overshoot Undershoot Magnitude at a specific Activity Factor Each Table entry is independent of all others meaning that the Pulse Duration reflects the existence of Overshoot Undershoot Events of that Magnitude ONLY A platform with an overshoot undershoot that just meets the Pulse Duration for a specific Magnitude where the AF lt 1 means that there can be NO other Overshoot Undershoot events even of lesser Magnitude note that if AF 1 then the event occurs at all times and no other events can occur Note Activity Factor for AGTL signals is referenced to BCLK frequency Note Activity Factor for CMOS signals is referenced to PICCLK frequency 4 2 2 4 Determining if a System meets the Overshoot Undershoot Specifications The overshoot undershoot specifications listed in the following tables specify the allowable overshoot undershoot for a single overshoot undershoot event However most systems will have multiple overshoot and or unders
137. uired to cool the Pentium III Xeon processor at 600 MHz in the platform environment 54 mru eS oe cee we A m r R K e KR Sw oe ee ew ee AS THERMAL SPECIFICATIONS 6 1 2 PLATE FLATNESS SPECIFICATION The thermal plate flatness for the Pentium IIl Xeon processor at 600 MHz is specified to 0 010 across the entire thermal plate surface with no more than a 0 003 step anywhere on the surface of the plate as shown in Figure 18 0037 1 00K1 00 FLATNESS REFERENCE Figure 18 Plate Flatness Reference 6 2 Processor Thermal Analysis 6 2 1 THERMAL SOLUTION PERFORMANCE Processor cooling solutions should attach to the thermal plate The processor cover is not designed for thermal solution attachment The complete thermal solution must adequately control the thermal plate below the maximum and above the minimum specified in Table 42 The performance of any thermal solution is defined as the thermal resistance between the thermal plate and the ambient air around the processor thermal plate to ambient The lower the thermal resistance between the thermal plate and the ambient air the more efficient the thermal solution is The required thermal plate to ambient is dependent upon the maximum allowed thermal plate temperature TPLATE the local ambient temperature TLA and the thermal plate power PPLATE 8 thermal plate to ambient TPLATE TLA PPLATE The maximum TPLATE and the thermal plate power are listed
138. upon THERMTRIP until after the RESET input is de asserted Until this time the THERMTRIP output is indeterminate 10 1 59 TMS I The TMS Test Mode Select signal is a TAP support signal used by debug tools 10 1 60 TRDY I The TRDY Target Ready signal is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of all Pentium IIl Xeon processor at 600 MHz system bus agents 10 1 61 TRST I The TRST Test Reset signal resets the Test Access Port TAP logic Pentium IIl Xeon processor at 600 MHz self reset during power on therefore it is not necessary to drive this signal during power on reset 10 1 62 VID_L2 4 0 VID_CORE 4 0 O The VID Voltage ID pins can be used to support automatic selection of power supply voltages These pins are not signals but are either an open circuit or a short circuit to VSS on the processor The combination of opens and shorts defines the voltage required by the processor The VID pins are needed to cleanly support voltage specification variations on Pentium III Xeon processor at 600 MHz and Pentium III Xeon processors See Table 2 for definitions of these 100 PENTIUMO III XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX pins The power supply must supply the voltage that is requested by these pins or disable itself See section 3 9 for the maximum rating for t
139. upported ratios for each processor The BCLK period allows for 0 5 nS tolerance for clock driver variation See the CK98WS Clock Synthesizer Driver Specification for further information Due to the difficulty of accurately measuring clock jitter in a system it is recommended that a clock driver be used that is designed to meet the period stability specification into a test load of 10 to 20 pF This should be measured on the rising edges of adjacent BCLKs crossing 1 25V at the processor core pin The jitter present must be accounted for as a component of BCLK timing skew between devices The clock driver s closed loop jitter bandwidth must be set low to allow any PLL based device to track the jitter created by the clock driver The 20 dB attenuation point as measured into a 10 to 20 pF load should be less than 500 kHz This specification may be ensured by design characterization and or measured with a spectrum analyzer See the CK98WS Clock Synthesizer Driver Specification for further details Not 100 tested Specified by design characterization as a clock driver requirement This frequency range is specified by the CK98WS Clock Synthesizer Driver Specification and is guaranteed by design only not tested 23 AS r R s sew r p m m r R R e K S Pus seen sw ew ee r n R R e ELECTRICAL SPECIFICATIONS Table 13 AGTL Signal Group System Bus AC Specifications at the processors Core Ri 50 ohms Terminated to 1 5V fre Para
140. will respond to snoop phase transactions initiated by ADS on the system bus while in Stop Grant state or in Auto HALT Power Down state When a snoop transaction is presented upon the system bus the processor will enter the HALT Grant Snoop state The processor will stay in this state until the snoop on the system bus has been serviced whether by the processor or another agent on the system bus After the snoop is serviced the processor will return to the Stop Grant state or Auto HALT Power Down state as appropriate 40 mw eS oe cee we ewww Se oe A A e ee A PROCESSOR FEATURES 5 1 5 SLEEP STATE STATE 5 The Sleep state is a very low power state in which the processor maintains its context maintains the PLL and has stopped all internal clocks The Sleep state can only be entered from Stop Grant state Once in the Stop Grant state verified by the termination of the Stop Grant Bus transaction cycle the SLP pin can be asserted causing the Pentium IIl Xeon processor at 600 MHz to enter the Sleep state The system must wait 100 BCLK cycles after the completion of the Stop Grant Bus cycle before SLP is asserted For an MP system all processors must complete the Stop Grant bus cycle before the subsequent 100 BCLK wait and assertion of SLP can occur The processor is in Sleep state 10 BCLKs after the assertion of the SLP pin The latency to exit the Sleep state is 10 BCLK cycles The SLP pin is not recognized in the Normal or Aut
141. wing options e Enabled or disabled e Asserted optionally for internal errors along with IERR e Asserted optionally by the request initiator of a bus transaction after it observes an error e Asserted by any bus agent when it observes an error in a bus transaction 10 1 8 BINIT I O The BINIT Bus Initialization signal may be observed and driven by all Pentium III Xeon processor at 600 MHz system bus agents and if used must connect the appropriate pins of all such agents If the BINIT driver is enabled during power on configuration BINIT is asserted to signal any bus condition that prevents reliable future information If BINIT observation is enabled during power on configuration and BINIT is sampled asserted all bus state machines are reset and any data which was in transit is lost All agents reset their rotating ID for bus arbitration to the state after reset and internal count information is lost The L1 and L2 caches are not affected If BINIT observation is disabled during power on configuration a central agent may handle an assertion of BINIT as appropriate to the Machine Check Architecture MCA of the system 10 1 9 BNR 1 0 The BNR Block Next Request signal is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Since multiple agents might need to request a bus stall at the same time BNR is a
142. wire OR signal which must connect the appropriate pins of all Pentium Ill Xeon processor at 600 MHz system bus agents In order to avoid wire OR glitches associated with simultaneous edge transitions driven by multiple drivers BNR is activated on specific clock edges and sampled on specific clock edges 10 1 10 BP 3 2 1 0 The BP 3 2 Breakpoint signals are outputs from the processor that indicate the status of breakpoints 10 1 11 BPM 1 0 1 0 The BPM 1 0 Breakpoint Monitor signals are breakpoint and performance monitor signals They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance 10 1 12 BPRI I The BPRI Bus Priority Request signal is used to arbitrate for ownership of the Pentium IIl Xeon processor at 600 MHz system bus lt must connect the appropriate pins of all Pentium IIl Xeon processor at 600 MHz system bus agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI 10 1 13 BRO I O BR 3 1 1 90 PENTIUMO III XEON PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX The BR 3 1 Bus Request pins drive the BREQ 3 0 signals on the system The BR 3 0 pins are
143. z Figure 6 Setup and Hold Timings 28 s es eS oe cee we rs www seen s sw we cee we mew eee r n R 8 w ELECTRICAL SPECIFICATIONS RESET Configuration A20M IGNNE LINT 1 0 Configuration seyasi Bros LLL LD T9 GTL Input Hold Time T8 GTL Input Setup Time T10 RESET Pulse Width T16 Reset Configuration Signals A 14 5 BRO FLUSH INIT Setup Time T17 Reset Configuration Signals A 14 5 BRO FLUSH INIT Hold Time T20 Reset Configuration Signals A20M IGNNE LINT 1 0 Hold Time T19 Reset Configuration Signals A20M IGNNE LINT 1 0 Delay Time T18 Reset Configuration Signals A20M IGNNE LINT 1 0 Setup Time DAND 704 Figure 7 System Bus Reset and Configuration Timings eck T NA N I SNS NS X V CCcoRE VTT v cc 2 5 PWRGOOD RESET Configuration A20M IGNNE LINT 1 0 HHHH A tT Valid Ratio T15 PWRGOOD Inactive Pulse Width T10 RESET Pulse Width T20 Reset Configuration Signals A20M IGNNE LINT 1 0 Hold Time ONO7AGh Figure8 Power On Reset and Configuration Timings 29 AS r u ewe w mwn et vvv mu sw wn ew m w R e ELECTRICAL SPECIFICATIONS TDI TMS Non Test Input Signals TDO Non Test Output Signals T43 All Non Test Inputs Setup Time T44 All Non Test Inputs Hold Time T40 TDO Float Delay T37 TDI TMS Setup Time T38 TDI TMS Hold Time T39 TDO Valid Delay T41 All Non Test

Intel Pentium III Xeon 600 MHz

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