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Intel Pentium 200 MHz

1. O 0 0 0 0 0 0 0 0 0 0 0 0 0 O OO OOO0O0000 0 0 0 5 D SEATING PLANE gt A 4 Li lt Figure 12 SPGA Package Dimensions Table 18 SPGA Package Dimensions Millimeters Inches Symbol Min Notes Min Max Notes A 2 62 2 97 0 103 0 117 0 69 0 84 Ceramic Lid 0 027 0 033 A2 3 31 3 81 Ceramic Lid 0 130 0 150 0 43 0 51 0 017 0 020 49 28 49 78 1 940 1 960 D1 45 59 45 85 1 795 1 805 1 2 29 2 79 0 090 0 110 L 3 05 3 30 0 120 0 130 N 296 Lead Count 296 Lead Count S 152 254 0 100 44 intel PENTIUM PROCESSOR WITH MMX TECHNOLOGY CHIP CAPACITOR SEATING 3 PLANE HEAT red 3r Fee E j 2 4 92090 8989 8989 9 909 ze E E 95959 i o 20867 95900 950 24 1 65 8 9 99 2000 e ee 640 2959 DO ze E m x 50 1 0 0 25 152 COR
2. 9 Ax 37 97 7 ANZ A 3397 ws s AN 7 133 134 vs e 25 7 Us A AN ANM Vss 06 18 H02 Po2 U35 736 AF36 2 24 B08 B20 H36 P36 2 AHo2 14 AM26 B10 B22 R02 V36 apse 7 16 28 B12 B24 K36 R36 Abo AL37 amis 0 B14 B26 x36 36 amos 20 7 B16 B28 M36 T36 202 AFo2 10 22 NC A37 S35 AL19 R34 W33 AN35 533 W35 INC A03 2 co ANO3 ANOS NOTES 1 The FRCMC is not defined for the Pentium processor with technology This pin should be left as a NC or tied to via an external pull up resistor on the Pentium processor with MMX technology 2 PICCLK CLK are 3 3V tolerant only on the Pentium processor with MMX technology Please refer to the Pentium Processor Family Developer s Manual Order Number 241428 for the CLK and PICCLK signal quality specification 2 2 Design Notes For reliable operation always connect unused inputs to an appropriate signal level Unused active low inputs should be connected to Unused active high inputs should be connected to GND No Connect NC pins must remain unconnected Connection of NC or INC pins may result in component failure or incompatibility with processo
3. P04 SCYC ALI7 APCHK 5 D P4 IGNNE amp 4 4 9 036 INIT SMIACT amp 1 AK10 DP1 230 INTR LINTO AD34 TCK M34 2 ALT DP2 C25 INV 005 N35 BES 12 Wo5 TDO N33 BE4 AL13 DP4 C07 Lock AH04 TMS P34 5 DP5 WIOR 704 TRSTH 1 DP6 202 05 VCC2DET amp ALO1 BE7 16 DP7 NOS NMILINT AC33 AM06 _ 204 4 PCD AGOS WB WT AAOS BP2 803 W03 PCHK amp AF04 BP3 S05 FERR _ 005 234 BRDY amp X04 FLUSH 7 Q03 BRDYCK R04 Dual Processor APIC Clock Control Private Interface H34 18 _ 4 PICDO J33 Y33 PBREQ DPEN BF1 X34 PHIT AA08 PICD1 135 STPCLKK V34 ACO3 APICEN Vcc2 A17 A07 001 1 ANT A15 G01 S01 ACO A13 101 001 AEO1 15 AM Lot wor AG01 17 A09 Not 01 9 19 12 intel PENTIUM PROCESSOR WITH MMX TECHNOLOGY Table 1 Pin Cross Reference by Pin Name xPGA Package Cont d
4. 15 PENTIUM amp PROCESSOR WITH TECHNOLOGY intel Table 2 Quick Pin Reference Cont d Symbol Type Name and Function BUSCHK The bus check input allows the system to signal an unsuccessful completion of a BUSCHK request bus cycle If this pin is sampled active the Pentium processor with MMX technology will latch the address and control signals in the machine check registers If in addition the MCE bit in CR4 is set the Pentium processor with technology will vector to the machine check exception NOTE To assure that BUSCHK will always be recognized STPCLK must be deasserted any time is asserted by the system before the system allows another external bus cycle If BUSCHK is asserted by the system for a snoop cycle while STPCLK remains asserted usually if MCE 1 the processor will vector to the exception after STPCLK is deasserted But if another snoop to the same line occurs during STPCLK assertion the processor can lose the CACHE of transfers in the cycle For Pentium processor with technology initiated cycles thecache pin indicates internal cacheability of the cycle if a read and indicates a burst write back cycle if a write If this pin is driven inactive during a read cycle the Pentium processor with MMX technology will not cache the returned data regardless of the state of the KEN pin This pin is also used to determine the cycle length
5. 34 25 24 19 1 40 0 9 55 23 20 Without Heatsink 14 14 134 121 97 70 Heatsinks are omni directional pin aluminum alloy Features were based on standard extrusion practices for a given height Pin size ranged from 50 to 129 mils Pin spacing ranged from 93 to 175 mils Based thickness ranged from 79 to 200 mils Heatsink attach was 0 005 of thermal grease Attach thickness of 0 002 will improve performance approximately 0 3 C Watt 48 intel PENTIUM PROCESSOR WITH MMX TECHNOLOGY Theta ca C W Air Flow Rate LFM 0 100 k 200 lt 400 600 800 0 2 0 4 0 6 0 8 1 0 1 2 14 Heat Sink Height in Figure 15 Thermal Resistance vs Heatsink Height SPGA Packages 49 PENTIUM PROCESSOR WITH TECHNOLOGY intel Table 21 Thermal Resistances for PPGA Packages Heat Sink Height cA C Watt vs Laminar Airflow linear ft min inches o 10 200 400 800 0 25 0 4 78 64 43 34 28 0 35 0 4 ss 73 58 38 26 0 45 0 4 82 es 51 27 23 0 55 0 4 8 45 24 z 0 65 0 4 75 58 a 28 22 19 0 80 0 4 51 37 26 20 18 1 00 0 4 45 24 19 16 1 20 0 4 57 41 31 22
6. 241428 for more details PWT The page write through pin reflects the state of the PWT bit in CR3 the page directory entry or the page table entry The PWT pin is used to provide an external write back indication on a page by page basis R S The run stop input is provided for use with the Intel debug port Please refer to the Pentium Processor Family Developer s Manual Order Number 241428 for more details 21 PENTIUM amp PROCESSOR WITH TECHNOLOGY intel Table 2 Quick Pin Reference Cont d Symbol Type Name and Function RESET RESET forces the Pentium processor with MMX technology to begin execution at a known state All the Pentium processor with MMX technology internal caches will be invalidated upon the RESET Modified lines in the data cache are not written back FLUSH and INIT are sampled when RESET transitions from high to low to determine if tristate test mode or checker mode will be entered or if Built In Self Test BIST will be run SCYC The split cycle output is asserted during misaligned LOCKed transfers to indicate that more than two cycles will be locked together This signal is defined for locked cycles only It is undefined for cycles which are not locked The system management interruptcauses system management interrupt request to be latched internally When the latched SMI is recognized on an instruction boundary the
7. Pentium processor with MMX technology must meet this specification for dual processor operation for the FLUSH and RESET signals 14 All TTL timings are referenced from 1 5V 15 To guarantee proper asynchronous recognition the signal must have been de asserted inactive for a minimum of two clocks before being returned active and must meet the minimum pulse width 16 This input may be driven asynchronously However when operating two processors dual processing mode FLUSH and RESET must be asserted synchronously to both processors 17 When driven asynchronously RESET NMI FLUSH R S INIT and must be de asserted inactive for a minimum of two clocks before being returned active 18 Timings are valid only when dual processor is present 19 Maximum time is valid from rising edge of RESET 20 Minimum time is valid after falling edge of RESET 21 The D C W R CACHE and A5 A31 signals are sampled only on the CLK that ADS is active 22 order to override the internal defaults and guarantee that the BF 1 0 inputs remain stable while RESET is active these pins should be strapped directly to or through a pull up pull down resistor to Vcca or ground Driving these pins with active logic is not recommended unless stability duringt RESET can be guaranteed Similarly CPUTYP should also be strapped directly to or through a pull up pull down resistor to Vcca or ground 23 RESET is synch
8. Technology AC Specifications for 66 MHz Bus Operation Cont d See Table 10 for Vcc and Tcase specifications 0 pF Setup Time Symbol Unit Figure Notes t7 ADS ADSC AP A3 A31 10 0 ns 6 1 PWT PCD 0 7 D C W R CACHE SCYC LOCK Float Delay tsa IERR FERR Valid 1 0 8 3 ns 5 4 Valid Delay 1 0 7 0 ns 5 4 toa BREQ Valid Delay 1 0 8 0 ns 5 4 top SMIACT Valid Delay 1 0 7 8 ns 5 4 toc Valid Delay 1 0 6 8 ns 5 Valid Delay 1 0 6 8 ns 5 HITM Valid Delay 0 7 6 0 ns 5 1 3 Valid Delay 1 0 10 0 ns 5 PRDY Valid Delay 1 0 8 0 ns 5 112 00 063 7 Write Data Valid 1 3 7 5 ns 5 Delay 00 063 Write Data Float 10 0 ns 6 1 114 5 1 Setup Time 6 0 ns 7 26 115 A5 A31 Hold Time 1 0 ns 7 INV AP Setup Time 5 0 ns 7 ti b EADS Setup Time 5 0 ns 7 117 EADS INV AP Hold Time 1 0 ns 7 tiga KEN Setup Time 5 0 ns 7 t18b WB WT Setup Time 4 5 ns 7 119 WB WT Hold 1 0 7 120 BRDY BRDYC Setup Time 5 0 ns 7 t21 BRDY BRDYC Hold Time 1 0 ns 7 t22 AHOLD BOFF Setup Tim
9. The Pentium processor with MMX technology is packaged in 296 pin staggered pin grid array ceramic SPGA or plastic PPGA packages The pins are arranged in a 37 x 37 matrix and the package dimensions are 1 95 x 1 95 Table 17 A 1 25 x 1 25 copper tungsten heat spreader may be attached to the top of some of the ceramic packages This package design with spreader has been replaced with a package which has no attached spreader In this section both ceramic spreader and non spreader as well as plastic packages are shown Package summary information is provided in Table 17 The mechanical specifications for the Pentium processor with MMX technology provided in Table 18 and Table 19 Figure 12 and Figure 13 show the package dimensions Table 17 Package Information Summary for Pentiumf Processor with Technologty Package Type Total Pins Pin Array Package Size Ceramic Staggered Pin Grid Array SPGA 296 37 x 37 1 95 x 1 95 4 95 cm x 4 95 cm Plastic Staggered Pin Grid Array PPGA 296 37 x 37 1 95 x 1 95 4 95 cm x 4 95 cm 43 PENTIUM PROCESSOR WITH TECHNOLOGY intel Pin C3 y OOOO0O0O00000000000
10. is internally masked by the Pentium processor with MMX technology when configured as a Dual processor 1 yo As outputs the address lines of the processor along with the byte enables define the physical area of memory or I O accessed The external system drives the inquire address to the processor on A31 A5 ADS The address strobe indicates that a new valid bus cycle is currently being driven by the Pentium processor with MMX technology ADSC The address strobe copy is functionally identical to ADS AHOLD In response to the assertion ofaddress hold the Pentium processor with MMX technology will stop driving the address lines A31 A3 and AP in the next clock The rest of the bus will remain active so data can be returned or driven for previously issued bus cycles AP yo Address parity is driven by the Pentium processor with MMX technology with even parity information on all Pentium processor with MMX technology generated cycles in the same clock that the address is driven Even parity must be driven back to the Pentium processor with MMX technology during inquire cycles on this pin in the same clock as EADS to ensure that correct parity check status is indicated by the Pentium processor with MMX technology The address parity check status pin is asserted two clocks after EADS is sampled active if the Pentium processor with MMX technology has detected a parity err
11. number CLK the device The clock input provides the fundamental timing for the Pentium processor with technology Its frequency is the operating frequency of the Pentium processor with MMX technology external bus and requires TTL levels All external timing parameters except TDI TDO TMS TRST and PICDO 1 are specified with respect to the rising edge of CLK This pin is 3 3V tolerant only on the Pentium processor with MMX technology Please refer to the Pentium Processor Family Developer s Manual Order Number 241428 for the CLK and PICCLK signal quality specification NOTE It is recommended that CLK begin toggling within 150 ms after reaches its proper operating level This recommendation is to ensure long term reliability of CPUTYP strapped to Vcca CPU type distinguishes the Primary processor from the Dual processor In a single processor environment or when the Pentium processor with MMX technology is acting as the Primary processor in a dual processing system CPUTYP should be strapped to Vss The Dual processor should have CPUTYP D C between data and code or special cycles The data code output is one of the primary bus cycle definition pins It is driven valid in the same clock as the ADS signal is asserted D C distinguishes 16 PENTIUM amp PROCESSOR WITH TECHNOLOGY Table 2 Quick Pin Reference Cont d Symbol Type Name and Function
12. 10 Vcc and Tcase Specifications Symbol Parameter Min Nom Max Unit Notes TCASE Case Temperature 0 70 C 2 Vcc2 Voltage 2 7 2 8 2 9 V Range 2 8 3 579601 Vcc3 Voltage 3 135 3 3 3 6 V Range 3 3 596 49 0996 1 1 See the Vcc measurement specification section earlier in this chapter Table 11 3 3V DC Specifications See Table 10 for Vcc and Tcase assumptions 1 Symbol Unit Notes Input Low Voltage 0 3 0 8 V TTL Level Input High Voltage 2 0 Voc3 0 3 V TTL Level 3 Output Low Voltage 0 4 V TTL Level 1 4 Output High Voltage 2 4 V TTL Level 2 NOTES Parameter measured at 4 mA 2 Parameter measured at 3 mA 3 Parameter measured at nominal which is 3 3V 4 n dual processing systems up to a 10 mA load from the second processor may be observed on the signal Based on silicon characterization data of PCHK will remain less than 400 mV even with a 10 mA load PCHK will increase to approximately 500 mV with 14 mA load worst case for a DP system with a 4 mA system load Table 12 Icc Specifications Measured at Vcc2 2 9V and Vcca 3 6V Symbol Parameter Min Max Unit Notes 2 Power Supply
13. 13 INIT FLUSH Hold Time t42a Reset Configuration Signals 2 0 CLK To RESET falling edge INIT FLUSH Setup Time 16 Async ta2b Reset Configuration Signals 2 0 CLK To RESET falling edge 36 intel PENTIUM amp PROCESSOR WITH TECHNOLOGY Table 15 Pentium Processor with Technology AC Specifications for 66 MHz Bus Operation Cont d See Table 10 for Vcc and Tcase specifications 0 pF Symbol Unit Figure Notes INIT FLUSH BRDYC 27 BUSCHK Hold Time Async Reset Configuration Signals 3 0 CLK To RESET falling edge BRDYC BUSCHK Setup 27 Time Async taza BF1 Setup Time 1 0 ms 8 RESET falling edgel t43b BFO BF1 CPUTYP Hold Time 2 0 CLK E RESET falling edge l43c APICEN 4 Setup Time 2 0 CLK RESET falling APICEN 4 Hold Time 2 0 CLK To RESET falling edge t44 Frequency 16 0 MHz 145 Period 62 5 ns 4 146 High Time 25 0 ns 4 2V 1 t47 Low Time 25 0 ns 4 0 8V 1 5 0 ns 4 2 0V 0 8V 1 8 9 149 Rise Time 5 0 ns 4 0 8V 2 0V 1 8 9 150 TRST Pulse Width 40 0 ns 10 Asynchronous 1 151 TDI TMS Setup Time 5 0 ns 9 7 152 TDI 5 Hold Ti
14. 166 MHz Pentium processor with MMX technology does not operate beyond the 66 MHz bus frequency and only supports the 2 5 bus to core ratio it does not support the 1 3 1 2 or 2 3 bus to core ratios Table3 clarifies summarizes these Specifications Table 15 Pentium Processor with Technology AC Specifications for 66 MHz Bus Operation See Table 10 for Vcc and Tcase specifications 0 pF Symbol Unit Figure Notes Frequency 33 33 66 6 MHz 4 Period 15 0 30 0 ns 4 tib Period Stability 250 ps Adjacent Clocks 1 25 to High Time 4 0 ns 4 2 1 Low Time 4 0 ns 4 0 8V 1 t4 CLK Fall Time 0 15 1 5 ns 4 2 0 0 8 1 5 t5 Rise Time 0 15 1 5 ns 4 0 8V 2 0V 1 5 tea PWT Valid 1 0 7 0 ns 5 teb AP Valid Delay 1 0 8 5 ns 5 tec 7 LOCK Valid Delay 0 9 7 0 ns 5 4 ted ADS Valid Delay 0 8 6 0 ns 5 tee ADSCtt D C W R SCYC 0 8 7 0 ns 5 Valid Delay tet M IO Valid Delay 0 8 5 9 ns 5 teg 16 Valid Delay 0 5 6 6 ns 5 teh 17 1 Valid Delay 0 6 6 6 ns 5 34 intel PENTIUM amp PROCESSOR WITH TECHNOLOGY Table 15 Pentium Processor with
15. 18 16 1 40 0 4 52 az 28 20 17 15 None 12 129 122 112 77 63 54 Heatsinks are omni directional pin aluminum alloy Features were based on standard extrusion practices for a given height Pin size ranged from 50 to 129 mils Pin spacing ranged from 93 to 175 mils Based thickness ranged from 79 to 200 mils Heatsink attach was 0 005 of thermal grease Attach thickness of 0 002 will improve performance approximately 0 3 C Watt 50 PENTIUM PROCESSOR WITH MMX TECHNOLOGY Theta ca C W Heat Sink Height in Air Flow Rate LFM 0 100 k 200 gt 400 600 800 Figure 16 Thermal Resistance vs Heatsink Height PPGA Packages 51
16. A29 AK34 AN33 2 4129 23 A24 AG35 A30 6 A7 AL3 A13 28 22 A25 AJ85 AJ83 32 4 AL27 A20 21 A26 _ Data 013 026 024 D39 052 1 027 053 005 02 5 015 A85 028 D22 D4 05 D54 E 03 633 016 029 042 055 04 _ 07 D30 056 05 F34 08 A33 044 057 06 5 019 032 04 058 405 7 020 033 0146 04 059 08 021 034 047 060 105 09 C37 022 035 _ 103 Dio 35 023 D49 Eo D62 X 011 024 C27 097 012 050 D63 012 vse 025 038 D51 11 PENTIUM amp PROCESSOR WITH TECHNOLOGY Table 1 Pin Cross Reference by Pin Name Package Cont d intel Control 20 BREQ ure AK06 PRDY ACO5 ADS 05 BUSCHK ALO7 HITM PWT ALO3 ADSCK AMO2 HLDA R S AHOLD vo4 035 HOLD 4 RESET 20 Dic 4
17. Of HIT amp A20MK 1 5 BE7 CLK RESET A19 A17 15 A13 9 5 29 28 AJ AJ BREQ HLDA ADS A31 A25 VSS AH VSS __LOCK A26 22 AG voce SMIACT PCD A27 A24 VCC3 AF AF vs A21 VSS AE VGC2 PBREQHAPCHK vCC3 AD AD VSS INTR VSS AC VCC2 PRDY NM 5 VCC3 AB AB VSS HOLD SM VSS AA voce INIT IGNNE VCC3 2 7 VSS 55 1 PEN VSS Y 2 FRCMC VCC3 x e x VSS _ BRD BF vss KEN NC VCC3 v Ns Em Pin Side View Peu 85 CACHER INV vos vss T Ves 465 S o 5 2 2 NC NC R o o o o R VSS NC _ VSS alo o PMOBPOFERR amp TRST amp CPUTYP VCC3 P VSS IERR TMS vss N o 063 M o o o M VSS 062 VSS E o 061 060 VCC3 PICD1 K K VSS D59 00 _ VSS J o J 057 058 PICDO 02 H H VSS 056 NIST 955 G o o o G VCC2 055 D53 53 v6c3 F o o 0 6 051 DP5 05 04 054 D52 049 04
18. P 2 N A FERR 2 Low 1 Low 1 3 Low 1 High IERR Low LOCK 1 Low Bus Hold BOFF M IOs 1 D C 1 W R 1 N A Bus Hold BOFF Low BP3 2 PM1 BP1 High High PWT PCD High Bus Hold BOFF SCYC 1 High Bus Hold BOFF SMIACT Low TDO N A states except Shift DR Shift IR Voc2DET Low NOTES All output and input output pins are floated during tristate test mode except IERR 1 These signals when two Pentium processor with MMX technology are operating in dual processing mode 2 These signals are undefined when the processor is configured as a Dual processor 3 M S pin has an internal pull up resistor 24 intel PENTIUM PROCESSOR WITH MMX TECHNOLOGY Table 5 Input Pins Synchronous Internal Name Active Level Asynchronous Resistor Qualified 20 1 Low Asynchronous AHOLD High Synchronous APICEN High Synchronous RESET Pull up BFO N A Synchronous RESET Pull down Synchronous RESET Pull up Low Synchronous BRDY Low Synchronous Pull up Bus State T2 112 BRDYC Low Synchronous Pull up Bus State T2 112 BUSCHK Low Synchronous Pull up BRDY CL
19. decodes the prefetched instructions So the Pentium processors can execute the 6 instruction The control ROM contains the microcode which controls the sequence of operations that must be performed to implement the Pentium processor architecture The control ROM unit has direct control over both pipelines The Pentium processors contain a pipelined floating point unit that provides a significant floating point performance advantage over previous generations of processors Symmetric dual processing in a system is supported with two Pentium processors The two processors appear to the system as a single Pentium processor Operating systems with dual processing support properly schedule computing tasks between the two processors This scheduling of tasks is transparent to software applications and the end user Logic built into the processors support a glueless interface for intel easy system design Through a private bus the two Pentium processors arbitrate for the external bus and maintain cache coherency Dual processing is supported in a system only if both processors are operating at identical core and bus frequencies In this document in order to distinguish between two Pentium processors in dual processing mode one processor will be designated as the Primary processor and the other as the Dual processor The Pentium processors are produced on the enhanced 0 35 um CMOS process which allows high device density an
20. 0 MICROPROCESSOR ARCHITECTURE 2 2 Design 13 OVERVIEW 3 2 3 Quick Pin 13 1 1 Pentium Processor Family Architecture 5 2 4 Pin Reference Tables 24 1 2 Pentium Processor with MMX 2 5 Pin Grouping According to Function 27 00 7 1 2 1 FULL SUPPORT FOR INTEL MMX 3 0 ELECTRICAL SPECIFICATIONS 28 TECHNOLOGY 7 3 1 Electrical Characteristics and Differences 1 2 2 DOUBLE CODE AND DATA CHACHES between the Pentium Processor with TO 16K 7 Technology and the Pentium 1 2 3 IMPROVED BRANCH PREDICTION 7 Processor 133 150 166 200 28 1 2 4 ENHANCED PIPELINE pU TP T 3 1 4 POWER SUPPLIES 28 1 2 5 DEEPER WRITE BUFFERG 8 3 1 2 CONNECTION SPECIFICATIONS 28 1 3 Mobile Pentiun Processor with SEESCBUEEEEUMOBEES pestes d pan Technology s iniussu 8 3 2 Absolute Maximum Ratings 3 3 DC Specifications 2 0 PINOUT enirn eene eren 9 EY 3 3 4 AC 2 1 Pinout and Pin Descriptions 9 2 1 1 PENTIUM PROCESSOR WITH 4 0 MECHANICAL SPECIFICATIONS 43 MMX TECHNOL
21. 111 Pentium processor at 120 MHz iCOMP Index 2 0 rating 100 Pentium processor at 100 MHz iCOMP Index 2 0 rating 90 Pentium processor at 90 MHz iCOMP Index 2 0 rating 81 Pentium processor at 75 MHz iCOMP Index 2 0 rating 67 The Pentium processor family supports the features of previous Intel Architecture processors and provides significant enhancements and additions including the following e Superscalar Architecture e Dynamic Branch Prediction e Pipelined Floating Point Unit 4 intel e Improved Instruction Execution Time Separate Code and Data Caches e Writeback MESI Protocol in the Data Cache e 64 Bit Data Bus e Bus Cycle Pipelining e Address Parity e Internal Parity Checking e Execution Tracing e Performance Monitoring EEE 1149 1 Boundary Scan e System Management Mode e Virtual Mode Extensions e Dual processing support e On chip local APIC device In addition to the features listed above the Pentium processor with MMX technology offers the following enhancements over Pentium processor 133 150 166 200 e Support for Intel MMX technology e Doubled code and data cache sizes to 16 KB each e Improved branch prediction e Enhanced pipeline e Deeper write buffers The following features are supported by the Pentium processor 133 150 166 200 but these features are not supported by the Pentium processor with MMX technology e Functional redundancy check and Lock Step ope
22. 2 and pins are intel specified at different voltages See Table 10 for the specification The display should show continuous sampling of the voltage line at 20 mV div and 500 ns div with the trigger point set to the center point of the range Slowly move the trigger to the high and low ends of the specification and verify that excursions beyond these limits are not observed There are no allowances for crossing the high and low limits of the voltage specification For more information on measurement techniques see the Voltage Guidelines for Pentium Processors with MMX Technology application note Order Number 243186 3 1 2 1 2 Decoupling Recommendations Liberal decoupling capacitance should be placed near the Pentium processor with MMX technology The Pentium processor with MMX technology when driving its large address and data buses at high frequencies can cause transient power surges particularly when driving large capacitive loads Low inductance capacitors and interconnects are recommended for best high frequency electrical performance Inductance be reduced by shortening circuit board traces between the Pentium processor with MMX technology and decoupling capacitors as much as possible These capacitors should be evenly distributed around each component on the power plane Capacitor values should be chosen to ensure they eliminate both low and high frequency noise components For the Pentium pr
23. 34 036 038 DP4 D45 D47 INC B o 011 013 016 020 55 VSS VSS_ VSS VSS 55 55 VSS VSS VSS 55 VSS 043 INC A o o NC D15 D18 D22 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VCC2 VCC2 D41 INC 5 535 NOTE 35532555552 2 19 18 17 16 5 13 2 1 10 3 87 6 5 4 3 21 1 The is not defined for Pentium processor with technology Pin Y35 should be left as a NC or tied to Vccs via an external pull up resistor PP0008a Figure 2 Pentium Processor with MMX Technology SPGA and PPGA Package Pinout Top Side View PENTIUM PROCESSOR WITH TECHNOLOGY intel 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 o AN INC_ _ FLUSH VCC2 2 2 VCC3 VCC3_VCC3_VCC3_ 10 A6 _ NC _ VSS AM e ADSC EADS W R VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 4 A30 AL o AL 2 PWT HITM BUSCHK BEO BE2 BE4 BEG SCYC NC 20 A18 16 4 12 7 55 AK AP D
24. 43187 3 1 2 2 3 3V Inputs and Outputs The inputs and outputs of the Pentium processor with MMX technology comply with the 3 3 JEDEC standard levels Both inputs and outputs are also TTL compatible although the inputs cannot tolerate voltage swings above the Vins max specification System support components which use TTL compatible inputs will interface to the Pentium processor with MMX technology without extra logic This is because the Pentium processor drives according to the 5V TTL specification but not beyond 3 3V For Pentium processor with MMX technology inputs the voltage must not exceed the 3 3V Vin3 max specification System support components consist of 3 3V devices or open collector devices In an open collector configuration the external resistor should be biased to Vcca All pins including the CLK and PICCLK of the Pentium processor with MMX technology are 3 3V tolerant only If an 8259A interrupt controller is used for example the system must provide level converters between the 8259A and the Pentium processor with MMX technology 3 1 2 3 NC INC and Unused Inputs All NC and INC pins must remain unconnected For reliable operation always connect unused inputs to an appropriate signal level Unused active low inputs should be connected to Unused active high inputs should be connected to Ves ground 29 PENTIUM PROCESSOR WITH TECHNOLOGY 3 1 2 4 Private Bus Wh
25. 5V CLK Tv t5 149 t60e Tw 14 148 1601 Tx t8 147 1608 t1 t45 1606 Tz 12 t46 t60c Figure 4 Clock Waveform 40 intel PENTIUM amp PROCESSOR WITH TECHNOLOGY Tx 16 18 19 t10 111 112 1601 160 t80a 189 Figure 5 Valid Delay Timings Signal Tx t7 113 Ty t6min t12min Figure 6 Float Delay Timings CLK Tx 114 116 118 120 122 124 126 128 131 134 1600 to PICCLK t81 183 Ty 115 117 119 121 123 125 127 129 132 135 t60h to 182 184 Figure 7 Setup and Hold Timings 41 PENTIUM PROCESSOR WITH TECHNOLOGY intel CLK RESET Config Tt 140 Tu 141 Tv 137 T w t42 3 143 187 Tx 1436 1434 1431 188 Ty 138 139 Tz 136 Figure 8 Reset and Configuration Timings TCK TDI TMS TDO Output Signals Input Signals Tr 157 Ts 158 154 Tv 151 Tw 152 Tx 153 Ty 155 Tz 156 Figure 9 Test Timings Tx Tx 150 Figure 10 Test Reset Timings 42 PENTIUM PROCESSOR WITH MMX TECHNOLOGY Signal Level 5596 VS often 50 Delay Flight Time 50 V 35 Veg At Receiver Pin 0 uF Load Driver Pin with Figure 11 50 Percent Vcc Measurement of Flight Time 4 0 MECHANICAL SPECIFICATIONS
26. 6 D42 07 06 VCC3 050 048 044 040 039 037 035 033 030 028 026 023 019 DPI 012 D8 DPO c 047 045 DP4 038 036 034 032 031 029 027 025 024 021 17 014 010 09 o o gt o o B 043 vss V s 55 VSS 158 166 166 156 VSS VSS VSS V S 020 016 D13 Dit A o o o o o o o o o o G o A 041 VCC2 VCC2 VCC2 VCC2 VCC2 VCC3 VCC3 VvCC3 VCC3 022 018 015 NC 12 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 NOTE 1 The is not defined for Pentium processor with MMX technology Pin Y35 should be left as a or tied to Vccs via an external pull up resistor PP0009a 10 Figure 3 Pentium Processor with Technology SPGA and PPGA Package Pinout Pin Side View intel PENTIUM amp PROCESSOR WITH TECHNOLOGY 2 1 2 PIN CROSS REFERENCE TABLE FOR PENTIUM PROCESSOR WITH MMX Table 1 Pin Cross Reference by Pin Name Package Address A3 5 A9 AK30 5 AKe6 A27 4 34 A10 ANS AL25 A22 AH36 A28 AK36 AK32 Aii A17 24 A23
27. AE o o o o o O AE VCC3 23 VCC2 AD o o o o AD VSS INTR PBGNT VSS VCC3 NMI VCC2 AB VSS __ SMl HOLD_ VSS AA VCC3 IGNNE INIT WB WT VCC2 2 2 VSS VSS O Y VCC3 BFO BRDYC VCC2 X o o X VSS BRDY VSS w VCC3 NC NC EWBE VCC2 V U 5 VSS eae Top Side View Gee VES VCC3 VSS CACHE VCC2 T o o o o T VSS _ VCC3 VSS 5 5 VCC3 NC NC BP2 VCC2 R o o o R VSS NC VSS Q ola VCC3 CPUTYP TRST amp VCC2 VSS TMS IERR VSS N o o o o o N VCC3 TDI TDO DP7 D63 VCC2 M o M VSS 062 VSS L L VCC3 PICD1 060 061 VCC2 K o K VSS 00 059 VSS J VCC3 D2 PICDO 058 057 2 H o o H VSS 056 VSS G o o o D1 03 053 055 VCC2 D4 05 5 051 DP6 E VCC3 D6 D7 042 046 049 D52 D54 D DPO 08 012 019 023 026 028 D30 D33 D35 D37 D39 D40 D44 D48 050 o o o o o o o o o o o o o o o o o 09 D10 D14 D17 021 024 2 025 027 029 031 032 0
28. BRDY DPEN low RESET Pull up PICDO N A Pull up PICD1 N A Pull down NOTES 1 output and input output pins are floated during tristate test mode except IERR and 2 have Pull downs during RESET only Table 7 Inter Processor Input Output Pins Name Active Level Internal Resistor PHIT Low Pull up PHITM Low Pull up PBGNT Low Pull up PBREQ Low Pull up NOTES For proper inter processor operation the system cannot load these signals 26 intel PENTIUM PROCESSOR WITH MMX TECHNOLOGY 2 5 Pin Grouping According to Function Table 8 organizes the pins with respect to their function Table 8 Pin Functional Grouping Function Pins Clock CLK Initialization RESET INIT BF1 BFO Address Bus 1 BE7 BE0 Address Mask 20 Data Bus D63 DO Address Parity AP APCHK APIC Support PICCLK PICDO 1 Data Parity 7 PCHK PEN Internal Parity Error IERR System Error BUSCHK Bus Cycle Definition M lO W R CACHE SCYC LOCK Bus Control ADS ADSC BRDY BRDYC NA Page Cacheability PCD PWT Cache Control KEN WB WT Cache Snooping Consistency AHOLD EADS HIT HITM INV Cache Flush FLUSH Write Ordering EWBE Bus Arbitration BOFF BREQ HOLD HLDA Dual Processing Private Bus Control
29. Current 6500 mA 233 MHz 5700 mA 200 Mhz 1 4750 mA 166 MHz 1 Power Supply Current 750 mA 233 MHz 650 mA 200 MHz 1 540 mA 166 MHz 1 31 PENTIUM PROCESSOR WITH TECHNOLOGY intel NOTES 15 This value should be used for power supply design It was determined using worst case instruction mix and maximum Power supply transient response decoupling capacitors must be sufficient to handle the instantaneous current changes occurring during transitions from Stop Clock to full Active modes Table 13 Power Dissipation Requirements for Thermal Design Measured at Vcc2 2 8V and Vcca 3 3V Parameter Typical Max Unit Notes Active Power 7 9 5 17 0 6 Watts 233 MHz 7 3 5 15 7 6 Watts 200 MHz 6 1 6 13 1 6 Watts 166 MHz Stop Grant Auto Halt 2 61 Watts 233 MHz 3 Powerdown Power 2 41 Watts 200 MHz 3 2 05 Watts 166 MHz 3 Stop Clock Power 0 03 0 3 Watts All frequencies NOTES 1 This is the typical power dissipation in a system This value is expected to be the average value that will be measured in a system using a typical device at 2 2 8V running typical applications This value is highly dependent upon the specific System configuration Typical power specifications are not tested Systems must be designed to thermally dissipate the maximum active power dissipation It is determined using worst case instruction m
30. Hz Bus Operation See Table 10 for Vcc and Tcase assumptions PENTIUM PROCESSOR WITH TECHNOLOGY Symbol Parameter Min Max Unit Figure Notes PBREQ PBGNT PHIT 0 0 2 0 ns 5 11 24 Flight Time PHITM Flight Time 0 0 1 8 ns 5 11 24 5 1 Setup Time 3 7 ns 7 18 D C W R CACHE 4 0 ns 7 18 21 LOCK SCYC Setup Time tg3c ADS Setup Time 5 8 ns 7 18 21 8 HITM Setup Time 6 0 ns 7 18 21 t83e HLDA Setup Time 6 0 ns 7 18 21 CACHE Hold Time 1 0 ns 7 18 21 ADS D C 0 8 ns 7 18 21 A5 A31 HLDA SCYC Hold Time tg4c LOCK Hold Time 0 9 ns 7 18 21 84 HITM Hold Time 0 7 ns 7 18 21 85 DPEN Valid Time 10 0 CLK 18 19 23 86 DPEN Hold Time 2 0 CLK 18 20 23 7 APIC ID BEO BE3 Setup 12 0 CLK 8 To falling Edge of Time RESET 23 tes APIC ID Hold 2 0 CLK 8 From Falling Edge of Time RESET 23 tgo D P Valid Delay 1 0 8 0 ns 5 Primary Processor Only NOTES Notes 2 6 and 14 are general and apply to all standard TTL signals used with the Pentiun processor family er models to account for signal flight time Each valid de delays 1 Not 100 2 TTL tested Guaranteed by design characterization test waveforms are assumed to be 0 to 3V transitions with 1 V ns rise and fall t
31. K N A CPUTYP High Synchronous RESET Pull down EADS Low Synchronous EWBE Low Synchronous BRDY FLUSH Low Asynchronous HOLD High Synchronous IGNNE 1 Low Asynchronous INIT High Asynchronous INTR High Asynchronous INV High Synchronous EADS LINT 1 0 High Asynchronous APICEN at RESET Low Synchronous First BRDY NA NA Low Synchronous Bus State T2 TD T2P NMI High Asynchronous PEN Low Synchronous BRDY PICCLK High Asynchronous Pull up R S N A Asynchronous Pull up RESET High Asynchronous SMI Low Asynchronous Pull up STPCLK Low Asynchronous Pull up TCK N A Pull up TDI N A Synchronous TCK Pull up TMS N A Synchronous TCK Pull up TCK TRST Low Asynchronous Pull up WB WT N A Synchronous First BRDY NA NOTES 1 Undefined when the processor is configured as a Dual processor 25 PENTIUM PROCESSOR WITH MMX TECHNOLOGY Table 6 Input Output Pins 1 intel Active Qualified Internal Name Level When Floated when an input Resistor A31 A3 N A Address Hold Bus Hold BOFF EADS N A Address Hold Bus Hold BOFF EADS Low Address Hold Bus Hold BOFF RESET Pull down 2 063 00 Bus Hold BOFF BRDY DP7 DPO N A Bus Hold BOFF
32. NER PN bear DETAL A Figure 13 PPGA Package Dimensions Table 19 PPGA Package Dimensions Millimeters Inches Symbol Min Max Notes Min Max Notes A 2 72 3 33 0 107 0 131 1 83 2 23 0 072 0 088 A2 1 00 0 039 B 0 40 0 51 0 016 0 020 D 49 43 49 63 1 946 1 954 Di 45 59 45 85 1 795 1 805 02 23 44 23 95 0 923 0 943 2 29 2 79 0 090 0 110 F1 17 56 0 692 F2 23 04 0 907 3 05 3 30 0 120 0 130 N 296 Lead Count 296 Lead Count 45 PENTIUM PROCESSOR WITH TECHNOLOGY Table 19 PPGA Package Dimensions Millimeters Inches Symbol Min Max Notes Min Max Notes 1 1 52 2 54 0 060 0 100 5 0 THERMAL SPECIFICATIONS The Pentium processor with MMX technology is specified for proper operation when case temperature Tcase Tc is within the specified range of 0 C to 70 C 5 1 Measuring Thermal Values To verify that the proper Tc is maintained it should be measured at the center of the package top surface opposite of the pins The measurement is made in the same way with or without a heatsink attached When a heatsink is attached a hole smaller than 0 150 diameter should be drilled through the heatsink to allow probing the center of the package See Figure 14 for an illustration of how to measure TC To minimize the measurement errors it is recommended to use the following approach e Use 36 gauge or finer diameter K T or J type thermocou
33. OGY PINOUT 9 2 1 2 PIN CROSS REFERENCE TABLE FOR 5 0 THERMAL SPECIFICATIONS POPP 46 PENTIUM PROCESSOR 5 1 Measuring Thermal Values 46 WITH 11 5 1 1 THERMAL EQUATIONS AND DATA 46 PENTIUM amp PROCESSOR WITH TECHNOLOGY 1 0 MICROPROCESSOR ARCHITECTURE OVERVIEW The Pentium processor with MMX technology extends the Intel Pentium family of microprocessors It is binary compatible with the 8086 88 80286 Intel386 DX Intel386 SX Intel486 DX Intel486 SX Intel486 DX2 and Pentium processors 60 66 75 90 1 00 1 20 133 150 166 200 The Pentium processor family currently includes the following products e Pentium processor with MMX technology Pentium processor with MMX technology at 233 MHz iCOMPS Index 2 0 rating 203 Pentium processor with MMX technology at 200 MHz iCOMP Index 2 0 rating 182 Pentium processor with MMX technology at 166 MHz iCOMP Index 2 0 rating 160 e Pentium processor 133 150 166 200 The name Pentium processor 133 150 166 200 will be used in this document to refer to the Pentium processor with 133 150 166 and 200 MHz versions of the Pentium processor Pentium processor at 200 MHz iCOMP Index 2 0 rating 142 Pentium processor at 166 MHz iCOMP Index 2 0 rating 127 Pentium processor at 150 MHz iCOMP Index 2 0 rating 114 Pentium processor at 133 MHz iCOMP Index 2 0 rating
34. PBGNT PBREQ PHIT PHITM Interrupts INTR NMI Floating Point Error Reporting FERR IGNNE System Management Mode SMI SMIACT TAP Port TCK TMS TDI TDO TRST Breakpoint Performance Monitoring PM1 BP1 BP3 2 Power Management STPCLK Miscellaneous Dual Processing CPUTYP D P Debugging R S PRDY Voltage Detection VCC2DET 27 PENTIUM amp PROCESSOR WITH TECHNOLOGY 3 0 ELECTRICAL SPECIFICATIONS This section describes the electrical differences between the Pentium processor with MMX technology and the Pentium processor 133 150 166 200 as well as the AC and DC specifications of the Pentium processor with MMX technology 3 1 Electrical Characteristics and Differences between the Pentium Processor with MMX Technology and the Pentium Processor 133 150 166 200 When designing a Pentium processor with MMX technology system from a Pentium processor 133 150 166 200 system there are a number of electrical differences that require attention Designing a single motherboard that supports various members of the Pentium processor family including the Pentium processor with MMX technology Pentium processor 133 150 166 200 Pentium OverDrive processor or future Pentium OverDrive processor can be easily accomplished Refer to the Pentium Processor Flexible Motherboard Design Guidelines application note Order Number 243187 for more information an
35. Pentium processor with MMX technology family consists of three products Detailed information on Mobile Pentium processors with MMX technology based on the enhanced CMOS process technology is available in the datasheet Mobile Pentium Processor with MMX Technology Order Number 243292 Please reference the datasheet for correct pinout mechanical thermal and electrical specifications In 2 0 PENTIUM PROCESSOR WITH MMX TECHNOL PINOUT OGY 2 1 Pinout and Pin Descriptions 2 1 1 PENTIUM PROCESSOR WITH MMX TECHNOLOGY PINOUT 3 5 4 5 91006288 27 553252 2 9 BH 6 5 0 9 87 6543 24 o o AN VSS NC A6 A10 VCC3 VCC3 VCC3 VCC3 VCC2 VCC2 VCC2 2 FLUSH INC INC INC AM 4 8 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ADSC AL O o o o AL VSS A3 A11 A12 A14 A16 A18 A20 NC SCYC 6 4 BE2 BUSCHK HITM 2 AK DET AK A28 A29 A5 A9 A13 A15 A17 Ai9 RESET CLK BE7 5 BE3 1 A20M o o o VSS A25 A31 ADS _ BREQ AH 9 22 26 LOCK VSS o O AG VCC3 24 A27 PCD SMIACT VCC2 AF AF VSS A21 VSS
36. The dual primary processor indication The Primary processor drives this low when it is driving the bus otherwise it drives this pin high is always driven D P can be sampled for the current cycle with ADS like a status pin This pin is defined only on the Primary processor Dual processing is supported in a System only if both processors are operating at identical core and bus frequencies Within these restrictions two processors of different steppings may operate together in a system 063 00 yo These are the 64 data lines for the processor Lines 07 00 define the least significant byte of the data bus lines D63 D56 define the most significant byte of the data bus When the CPU is driving the data lines they are driven during the T2 T12 or T2P clocks for that cycle During reads the CPU samples the data bus when BRDY is returned DP7 DPO yo These are the data parity pins for the processor There is one for each byte of the data bus They are driven by the Pentium processor with MMX technology with even parity information on writes in the same clock as write data Even parity information must be driven back to the Pentium processor with MMX technology on these pins in the same clock as the data to ensure that the correct parity check status is indicated by the Pentium processor with MMX technology DP7 applies to D63 56 DPO applies to D7 0 DPEN PICDO Vo Dual processing enable is an o
37. am desktop applications as well as for workstations The Pentium processor with MMX technology is compatible with the entire installed base of applications for MS DOS Windows OS 2 and UNIX The Pentium processor with MMX technology is the first microprocessor to support Intel MMX technology Furthermore the Pentium processor with MMX technology superscalar architecture can execute two instructions per clock cycle Enhanced branch prediction and separate caches also increase performance The pipelined floating point unit delivers workstation level performance Separate code and data caches reduce cache conflicts while remaining software transparent The Pentium processor with MMX technology has 4 5 million transistors and is built on Intel s enhanced CMOS silicon technology The Pentium processor with MMX technology may contain design defects or errors known as errata that may cause the product to deviate from published specifications Current characterized errata are available on request 1997 Order Number 243185 004 Information in this document is provided connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products includi
38. ata caches can be accessed simultaneously while the data cache supports two data references simultaneously The data cache supports a write back or alternatively write through on a line by line basis policy for memory updates 1 2 3 IMPROVED BRANCH PREDICTION Dynamic branch prediction uses the Branch Target Buffer BTB to boost performance by predicting the most likely set of instructions to be executed The BTB has been improved on the Pentium processor with MMX technology to increase its accuracy Further the Pentium processor with MMX technology has four prefetch buffers that can hold up to four successive code streams 1 2 4 ENHANCED PIPELINE An additional pipeline stage has been added and the pipeline has been enhanced to improve performance 7 PENTIUM PROCESSOR WITH TECHNOLOGY The integration of the MMX pipeline with the integer pipeline is very similar to that of the floating point pipeline Under some circumstances two MMX instructions or one integer and one MMX instruction can be paired and issued in one clock cycle to increase throughput The enhanced pipeline is described in more detail in the Pentium Processor Family Developer s Manual Order Number 241428 1 2 5 DEEPER WRITE BUFFERS A pool of four write buffers is now shared between the dual pipelines to improve memory write performance intel 1 3 Mobile Pentium Processor with Technology Currently Intel s Mobile
39. bus to core ratio and a specific minimum to maximum bus frequency range corresponding to a minimum to maximum core frequency range Operation in other bus to core ratios or outside the specified operating frequency range is not supported For example the 166 MHz Pentium processor with technology does not operate beyond the 66 MHz bus frequency and only supports the 2 5 bus to core ratio it does not support the 1 3 1 2 or 2 3 bus to core ratios Table clarifies and summarizes these Specifications Table 3 Bus Frequency Selections BF1 BFO Bus Core Ratio Frequency MHz Frequency MHz 0 1 1 3 66 200 33 100 0 0 2 5 66 166 33 83 1 0 1 2 1 2 N A 2 N A 2 1 1 2 7 66 233 33 17 NOTES 1 This is the default bus to core ratio for the Pentium processor with MMX technology If the BF pins are left floating the processor will be configured for the 1 2 bus to core frequency ratio 2 Currently there are no products that support these bus fractions 23 PENTIUM amp PROCESSOR WITH TECHNOLOGY intel 2 4 Pin Reference Tables Table 4 Output Pins Name Active Level When Floated ADS 1 Low Bus Hold BOFF ADSC Low Bus Hold BOFF APCHK Low 7 4 Low Bus Hold BOFF BREQ High CACHE 1 Low Bus Hold BOFF D
40. ck for each clock in which a parity error was detected Parity is checked only for the bytes on which valid data is returned When two Pentium processors with MMX technology are operating in dual processing mode may be driven two or three clocks after is returned 20 PENTIUM amp PROCESSOR WITH TECHNOLOGY Table 2 Quick Pin Reference Cont d Symbol Type Name and Function PEN The parity enable input along with CR4 MCE determines whether a machine check exception will be taken as a result of a data parity error on a read cycle If this pin is sampled active in the clock a data parity error is detected the Pentium processor with MMX technology will latch the address and control signals of the cycle with the parity error in the machine check registers If in addition the machine check enable bit in CR4 is set to 1 the Pentium processor with MMX technology will vector to the machine check exception before the beginning of the next instruction PHIT Vo Private hit is a hit indication used when two Pentium processors with MMX technology are configured in dual processing mode in order to maintain local cache coherency should be left unconnected if only one Pentium processor with MMX technology exists in a system PHITM yo Private modified hit is a hit on a modified cache line indication used when two Pentium processors with MMX techno
41. ction FLUSH When asserted the cache flush input forces the Pentium processor with MMX arbitration problems technology to write back all modified lines in the data cache and invalidate its internal caches A Flush Acknowledge special cycle will be generated by the Pentium processor with MMX technology indicating completion of the write back and invalidation If FLUSH is sampled low when RESET transitions from high to low tristate test mode is entered If two Pentium processors with MMX technology are operating in dual processing mode and FLUSH is asserted the Dual processor will perform a flush first without a flush acknowledge cycle then the Primary processor will perform a flush followed by a flush acknowledge cycle NOTE If the FLUSH signal is asserted in dual processing mode it must be deasserted at least one clock prior to BRDY of the FLUSH Acknowledge cycle to avoid DP pull up resistor Functional Redundancy Checking is not supported on thePentium processor with MMX technology The pin is not defined for the Pentium processor with MMX technology This pin should be left as a NC or tied to via an external as a result of an inquire cycle and retains its value between the cycles The hit indication is driven to reflect the outcome of an inquire cycle If an inquire cycle hits a valid line in either the Pentium processor with MMX technology data instr
42. current cycle have not yet completed The Pentium processor with MMX technology will issue ADS for a pending cycle two clocks after is asserted The Pentium processor with MMX technology supports up to 2 outstanding bus cycles NMI LINT1 The non maskable interrupt request signal indicates that an external non maskable interrupt has been generated If the local APIC is enabled this pin becomes LINT1 PBGNT Private bus the grant line that is used when two Pentium processors with technology are configured dual processing mode in order to perform private bus arbitration PBGNT should be left unconnected if only one Pentium processor with MMX technology exists in a system PBREQ Private bus requestis the request line that is used when two Pentium processor with MMX technology are configured in dual processing mode in order to perform private bus arbitration PBREQ should be left unconnected if only one Pentium processor with MMX technology exists in a system PCD The page cache disable pin reflects the state of the PCD bit in CR3 the Page Directory Entry or the Page Table Entry The purpose of PCD is to provide an external cacheability indication on a page by page basis PCHK The parity check output indicates the result of a parity check on a data read It is driven with parity status two clocks after BRDY is returned PCHK remains low one clo
43. cute all integer and floating point instructions The v pipe can execute simple integer instructions and the FXCH floating point instructions PENTIUM PROCESSOR WITH TECHNOLOGY Branch Verif amp Target Addr V Pipeline Floating Point U Pipeline Connection Unit Unit Address Generate am Sr Register File gt U Pipeline V Pipeline MMX Unit Integer Register File ALU ALU u Pipeline E ME 32 Bit Addr Bus Figure 1 Pentium Processor with MMX Technology Block Diagram The separate code and data caches are shown The data cache has two ports one for each of the two pipes the tags are triple ported to allow simultaneous inquire cycles The data cache has a dedicated Translation Lookaside Buffer TLB to translate linear addresses to the physical addresses used by the data cache The code cache branch target buffer and prefetch buffers are responsible for getting raw instructions into the execution units of the Pentium processor Instructions are fetched from the code cache or from the external bus Branch addresses are remembered by the branch target buffer The code cache TLB translates linear addresses to physical addresses used by the code cache The decode unit
44. cycles The Pentium processor with MMX 18 intel PENTIUM PROCESSOR WITH TECHNOLOGY Table 2 Quick Pin Reference Cont d Symbol Type Name and Function IERR The internal error pin is used to indicate internal parity errors If a parity error occurs on a read from an internal array the Pentium processor with MMX technology will assert the IERR pin for one clock and then shutdown IGNNE This is the ignore numeric error input This pin has no effect when the NE bit in CRO is set to 1 When the CRO NE bit is 0 and the IGNNE pin is asserted the Pentium processor with MMX technology will ignore any pending unmasked numeric exception and continue executing floating point instructions for the entire duration that this pin is asserted When the CRO NE bit is 0 IGNNE is not asserted a pending unmasked numeric exception exists SW ES 1 and the floating point instruction is one of FINIT FCLEX FSTENV FSAVE FSTSW FSTCW FENI FDISI or FSETPM the Pentium processor with MMX technology will execute the instruction in spite of the pending exception When the CRO NE bit is 0 IGNNE is not asserted a pending unmasked numeric exception exists SW ES 1 and the floating point instruction is one other than FINIT FCLEX FSTENV FSAVE FSTSW FSTCW FENI FDISI or FSETPM the Pentium processor with MMX technology will stop execution and wait for an external interrupt IGNNE is internally masked w
45. d lower power dissipation In addition to the SMM features described above the Pentium processor supports clock control When the clock to the Pentium processor is stopped power dissipation is virtually eliminated The combination of these improvements makes the Pentium processor a good choice for energy efficient desktop designs The Pentium processor supports fractional bus operation This allows the internal processor core to operate at high frequencies while communicating with the external bus at lower frequencies The Pentium processor contains an on chip Advanced Programmable Interrupt Controller APIC This APIC implementation supports multiprocessor interrupt management with symmetric interrupt distribution across all processors multiple subsystem support 8259A compatibility and inter processor interrupt support The architectural features introduced in this chapter are more fully described in the Pentium Processor Family Developer s Manual Order Number 241428 1 2 Pentium Processor with MMX Technology The Pentium processor with MMX technology is a significant addition to the Pentium processor family Available at 166 200 and 233 MHz it is the first microprocessor to support Intel s MMX technology The Pentium processor with MMX technology is both Software and pin compatible with previous members of the Pentium processor family It contains 4 5 million transistors and is manufactured on Intel s enhanc
46. d specific implementation examples The following sections highlight key electrical issues pertaining to the Pentium processor with MMX technology power supplies connection specifications and buffer models 3 1 1 POWER SUPPLIES The main electrical difference between the Pentium processor with MMX technology and the Pentium processor 133 150 166 200 is the operating voltage The Pentium processor with technology requires two separate voltage inputs Vcc2 and Vcc3 The Vcce pins supply power to the Pentium processor with MMX technology core while the Vcc3 pins supply power to the processor I O pins The Pentium processor 133 150 166 200 on the other hand requires a single voltage supply for all Vcc pins This single supply powers both the core and pins of the Pentium processor 133 150 166 200 By connecting all of the Vcc2 pins together and all the Vcc3 pins together on separate power islands 28 intel Pentium processor 133 150 166 200 designs can easily be converted to support the Pentium processor with MMX technology In order to maintain compatibility with Pentium processor 133 150 166 200 based platforms the Pentium processor with MMX technology supports the standard 3 3V specification on its Vccs pins 3 1 1 1 Power Supply Sequencing There is no specific power sequence required for powering up or powering down the separate 2 and supplies of the Pentium processor with MMX technology It
47. e 5 5 ns 7 t23 AHOLD BOFF Hold Time 1 0 ns 7 EWBE HOLD 5 0 ns 7 35 PENTIUM PROCESSOR WITH TECHNOLOGY intel Table 15 Pentium Processor with Technology AC Specifications for 66 MHz Bus Operation Cont d See Table 10 for Vcc and Tcase specifications 0 pF Symbol Parameter Min Max Unit Figure Notes 1045 Setup Time 4 8 ns 7 BUSCHK EWBE Hold 1 0 ns 7 Time 1256 HOLD Hold Time 1 5 ns 7 126 A20M INTR STPCLK Setup 5 0 ns 7 12 16 Time 27 A20M INTR STPCLK Hold 1 0 ns 7 13 Time 128 INIT FLUSH NMI SMI 5 0 ns 7 12 16 17 IGNNE Setup Time 129 INIT FLUSH NMI SMI 1 0 ns 7 13 Hold Time INIT FLUSH NMI SMI 2 0 CLK 15 17 IGNNE Pulse Width Async 131 R S Setup Time 5 0 ns 7 12 16 17 t32 R S Hold Time 1 0 ns 7 13 R S Pulse Width Async 2 0 CLK 15 17 t34 00 063 7 Read Data 2 8 ns 7 Setup Time 135 00 063 7 Read Data Hold 1 5 ns 7 Time t36 RESET Setup Time 5 0 ns 8 12 16 t37 RESET Hold Time 1 0 ns 8 13 t38 RESET Pulse Width Vcc amp CLK 15 0 CLK 8 17 Stable 9 RESET Active After amp 1 0 ms 8 Power up Stable 140 Reset Configuration Signals 5 0 ns 8 12 16 17 INIT FLUSH Setup Time t41 Reset Configuration Signals 1 0 ns 8
48. ed 0 35 micron CMOS process which allows voltage reduction technology for low power and high density This enables the Pentium processor with MMX technology to remain within the thermal PENTIUM PROCESSOR WITH MMX TECHNOLOGY envelope of the original Pentium processor while providing a significant performance increase addition to the architecture described in the previous section for the Pentium processor family the Pentium processor with MMX technology has several additional micro architectural enhancements compared to the Pentium processor 133 150 166 200 which are described below 1 2 1 FULL SUPPORT FOR INTEL MMX TECHNOLOGY MMX technology is based on the Single Instruction Multiple Data SIMD technique which enables increased performance on wide variety of multimedia and communications applications Fifty seven new instructions and four new 64 bit data types are supported in the Pentium processor with MMX technology All existing operating system and application software are fully compatible with the Pentium processor with MMX technology 1 2 2 DOUBLE CODE AND DATA CACHES TO 16K EACH On chip level 1 data and code cache sizes have been doubled to 16 KB each and are 4 way set associative on the Pentium processor with MMX technology Larger separate internal caches improve performance by reducing average memory access time and providing fast access to recently used instructions and data The instruction and d
49. edge when the TAP controller is in an appropriate state TMS The value of the test mode select input signal sampled at the rising edge of controls the sequence of TAP controller state changes TRST When asserted the test reset input allows the TAP controller to be asynchronously initialized Voce The Pentium processor with MMX technology has 25 2 8Vpower inputs Vcca The Pentium processor with MMX technology has 28 3 3Vpower inputs Vcc2DET Vcc2 detect is used in flexible motherboard implementations to configure the voltage output set point appropriately for the Voce inputs of the processor 22 intel PENTIUM PROCESSOR WITH TECHNOLOGY Table 2 Quick Pin Reference Cont d Symbol Type Name and Function Vss The Pentium processor with MMX technology has 53ground inputs W R Write read is of the primary bus cycle definition pins It is driven valid in the same clock as the ADS signal is asserted W R distinguishes between write and read cycles WB WT The write back write through input allows a data cache line to be defined as write back or write through on a line by line basis As a result it determines whether a cache line is initially in the S or E state in the data cache Core and bus frequencies can be set according to Table 3 below Each Pentium processor with MMX technology specified to operate within a single
50. en two Pentium processors with MMX technology are operating in dual processor mode a private bus exists to arbitrate for the processor bus and maintain local cache coherency The private bus consists of two pinout changes 1 Five pins are added PBREQ PBGNT PHIT PHITM D P 2 output pins become pins ADS D C W R CACHE LOCK HIT HITM HLDA SCYC BE 4 The new pins are given AC specifications of valid delays at 0 pF setup times and hold times Simulate with these parameters and their respective buffer models to guarantee that proper timings are met The AC specification gives input setup and hold times for the ten signals that become pins These setup and hold times must only be met when a dual processor is present in the system 3 1 3 BUFFER MODELS The structure of the buffer models for the Pentium processor with MMX technology and the Pentium processor 133 150 166 200 are identical Some of intel the values of the components have changed to reflect the minor manufacturing process and package differences between the processors The system should see insignificant differences between the AC behavior of the Pentium processor with MMX technology and the Pentium processor 133 150 166 200 Simulation of timings using the Pentium processor with MMX technology buffer models is recommended to ensure robust system designs Pay specific attention to the signal quality re
51. he current cycle is cacheable or not and is consequently used to determine cycle length When the Pentium processor with MMX technology generates a cycle that can be cached CACHE asserted and is active the cycle will be transformed into a burst line fill cycle 19 PENTIUM PROCESSOR WITH TECHNOLOGY intel Table 2 Quick Pin Reference Cont d Symbol Type Name and Function LINTO INTR If the APIC is enabled this pin islocal interrupt 0 If the APIC is disabled this pin is INTR LINT1 NMI If the APIC is enabled this pin islocal interrupt 1 If the APIC is disabled this pin is NMI LOCK The bus lock pin indicates that the current bus cycle is locked ThePentium processor with MMX technology will not allow a bus hold when LOCK is asserted but AHOLD and BOFF are allowed LOCK goes active in the first clock of the first locked bus cycle and goes inactive after the BRDY is returned for the last locked bus cycle LOCK is guaranteed to be de asserted for at least one clock between back to back locked cycles M lO The memory input output is one of the primary bus cycle definition pins It is driven valid in the same clock as the ADS signal is asserted distinguishes between memory and cycles An active next address input indicates that the external memory system is ready to accept a new bus cycle although all data transfers for the
52. hen the Pentium processor with MMX technology is configured as a Dual processor INIT The Pentium processor with MMX technology initialization input pin forces the Pentium processor with MMX technology to begin execution in a known state The processor state after INIT is the same as the state after RESET except that the internal caches write buffers and floating point registers retain the values they had prior to INIT INIT may NOT be used in lieu of RESET after power up If INIT is sampled high when RESET transitions from high to low thePentium processor with MMX technology will perform built in self test prior to the start of program execution INTR LINTO An active maskable interrupt input indicates that an external interrupt has been generated If the IF bit in the EFLAGS register is set thePentium processor with MMX technology will generate two locked interrupt acknowledge bus cycles and vector to an interrupt handler after the current instruction execution is completed INTR must remain active until the first interrupt acknowledge cycle is generated to assure that the interrupt is recognized If the local APIC is enabled this pin becomes LINTO INV The invalidation input determines the final cache line state S or in case of an inquire cycle hit It is sampled together with the address for the inquire cycle in the clock EADS is sampled active KEN The cache enable pin is used to determine whether t
53. imes is specified for a 0 pF load The system designer should use I O buf 3 Non test outputs and inputs are the normal output or input signals besides TRST TDI and TMS These timings correspond to the response of these signals due to boundary scan operations 4 APCHK FERR IERR LOCK and are glitch free outputs Glitch free signals monotonically transition without false transitions i e glitches 0 8V ns 0 3V ns input rise fall time lt 8V ns input rise fall time x 5V ns Referenced to TCK rising edge Referenced to TCK falling edge 1 ns can be added to the maximum TCK rise and fall times for every 10 MHz of frequency below 33 MHz 0 During debugging do not use the boundary scan timings 455 to 158 39 PENTIUM PROCESSOR WITH TECHNOLOGY intel 11 This is a flight time specification that includes both flight time and clock skew The flight time is the time from where the unloaded driver crosses 1 5 5095 of min Vcc to where the receiver crosses the 1 5V level 5096 of min Vcc See Figure 11 The minimum flight time minus the clock skew must be greater than zero 12 Setup time is required to guarantee recognition on a specific clock Pentium processor with MMX technology must meet this specification for dual processor operation for the FLUSH and RESET signals 13 Hold time is required to guarantee recognition on a specific clock
54. intel PENTIUM amp PROCESSOR WITH MMX TECHNOLOGY Maximum Operating Frequency 166 MHz 200 MHz 233 MHz iCOMPS Index 2 0 Rating 160 182 203 NOTE Contact Intel Corporation for more information about Index 2 0 ratings Support for Technology m Enhanced CMOS Silicon Technology Compatible with Large Software Base m 4 Mbyte Pages for Increased TLB Hit MS DOS Windows OS 2 UNIX Rate 32 Bit Processor with 64 Bit Data Bus m IEEE 1149 1 Boundary Scan Superscalar Architecture m Dual Processing Configuration A Enhanced Pipelines m Internal Error Detection Features Two Pipelined Integer Units Capable of Two Instructions per m Multi Processor Support Clock Multiprocessor Instructions Pipelined MMX Unit Support for Second Level Cache Pipelined Floating Point Unit m On Chip Local APIC Controller m Separate Code and Data Caches MP Interrupt Management 16 Kbyte Code 16 Kbyte Write 8259 Compatible Back Data m Power Management Features MESI Cache Protocol System Management Mode m Advanced Design Features Clock Control Deeper Write Buffers m Fractional Bus Operation Enhanced Branch Prediction 233 MHz Core 66 MHz Bus Feature 200 MHz Core 66 MHz Bus Virtual Mode Extensions 166 MHz Core 66 MHz Bus The Pentium processor with MMX technology extends the Pentium processor family providing performance needed for mainstre
55. ion and one that prefetches code according to the BTB so the needed code is almost always prefetched before it is needed for execution The floating point unit has been completely redesigned over the Intel486 processor Faster algorithms provide up to 10X speed up for common operations including add multiply and load Pentium processors include separate code and data caches are integrated on chip to meet performance goals Each cache has a 32 byte line size Each cache has a dedicated Translation Lookaside Buffer TLB to translate linear addresses to physical addresses The data cache is configurable to be write back or write through on a line by line basis and follows the MESI protocol The data cache tags are triple ported to support two data transfers and an PENTIUM PROCESSOR WITH TECHNOLOGY inquire cycle in the same clock The code cache is an inherently write protected cache The code cache tags are multi ported to support snooping Individual pages can be configured as cacheable or non cacheable by software or hardware The caches can be enabled or disabled by software or hardware The Pentium processors have increased the data bus to 64 bits to improve the data transfer rate Burst read and burst write back cycles are supported by the Pentium processors In addition bus cycle pipelining has been added to allow two bus cycles to be in progress simultaneously The Pentium processors Memory Management Unit contai
56. is recommended that the and Vccs supplies be either both ON or both OFF within one second of each other 3 1 2 CONNECTION SPECIFICATIONS Connection specifications for the power and ground inputs 3 3V inputs and outputs and the NC INC and unused inputs are discussed in the following sections 3 1 2 1 Power and Ground For clean on chip power distribution the Pentium processor with MMX technology in PPGA and SPGA packages has 28 power 25 2 core power and 53 Vss ground inputs Power and ground connections must be made to all external Vcc and Vss pins of the Pentium processor with MMX technology On the circuit board all Vcca pins must be connected to a 3 3V Vcc plane All gt pins must be connected to 2 8V plane All Vss pins must be connected to a Vss plane 3 1 2 1 1 Vcc2 and Measurement Specification The values of 2 and should be measured at the bottom side of the processor pins using an oscilloscope with a 3 dB bandwidth of at least 20 MHz 100 MS s digital sampling rate There should be a short isolation ground lead attached to a processor pin on the bottom side of the board The measurement should be taken at the following Voco Vss pairs AN13 AM10 AN21 AM18 29 AM26 AC37 Z36 U37 R36 L37 H36 A25 B28 A17 B20 A7 B10 G1 K2 S1 V2 AC1 Z2 One half of these pins are 2 while the others are the operating ranges for the Vcc
57. ix with Vcc2 2 8V and 3 3 and also takes into account the thermal time constants of the package Stop Grant Auto Halt Power Down Power Dissipation is determined by asserting the STPCLK pin or executing the HALT instruction Stop Clock Power Dissipation is determined by asserting the STPCLK and then removing the external CLK input Active Power typ is the average power measured in a system using a typical device running typical applications under normal operating conditions at nominal and room temperature Active Power is the maximum power dissipation under normal operating conditions at nominal V c2 worst case temperature while executing the worst case power instruction mix Active power max is equivalent to Thermal Design Power max 32 intel PENTIUM amp PROCESSOR WITH TECHNOLOGY Table 14 Input and Output Characteristics Symbol Parameter Min Max Unit Notes CiN Input Capacitance 15 pF 4 Co Output Capacitance 20 pF 4 Capacitance 25 pF 4 CLK Input Capacitance 15 pF 4 CTIN Test Input Capacitance 15 pF 4 Ctout Test Output Capacitance 20 pF 4 Test Clock 15 pF 4 Input Leakage Current 215 0 lt lt gt Vin gt Voc 1 Output Leakage Current 215 0 lt lt Vin gt Vin gt 1 Input Leakage Cur
58. l thermal conductivity and process of die attach is thermal resistance from package case to the ambient values shown in these tables are typical values The actual ca values depend on the heatsink design interface between heatsink and package the air flow in the system and thermal interactions between processor and surrounding components through PCB and the ambient Figure 15 and Figure 16 show Table 20 Table21 graphical format intel PENTIUM PROCESSOR WITH TECHNOLOGY SPGA Figure 14 Technique fore Measuring Tc on PPGA and SPGA Packages 47 PENTIUM PROCESSOR WITH TECHNOLOGY intel Table 20 Thermal Resistance for SPGA Packages Heatsink Height 8ca C Watt vs Laminar Airflow linear ft min inches 10 20 400 800 0 25 0 9 as 0 35 0 9 76 41 34 29 0 45 0 9 85 71 54 37 30 26 0 55 0 9 se 66 48 33 27 24 0 65 0 9 zs 44 25 ae 0 80 0 9 54 40 29 23 21 1 00 0 9 48 37 27 22 19 1 20 0 9 44
59. logy are configured in dual processing mode in order to maintain local cache coherency PHITM should be left unconnected if only one Pentium processor with MMX technology exists in a system PICCLK The APIC interrupt controller serial data bus clock is driven into the programmable interrupt controller clockinput of the Pentium processor with MMX technology This pin is 3 3V tolerant only on the Pentium processor with MMX technology Please refer to the Pentium Processor Family Developer s Manual Order Number 241428 for the and PICCLK signal quality specification PICDO 1 APICEN Programmable interrupt controller data lines 0 10f the Pentium processor with MMX technology comprise the data portion of the APIC 3 wire bus They are open drain outputs that require external pull up resistors These signals are multiplexed with DPEN APICEN respectively 1 0 These pins function as part of the performance monitoring feature The breakpoint 1 0 pins are multiplexed with theperformance monitoring 1 0 pins The PB1 and PBO bits in the Debug Mode Control Register determine if the pins are configured as breakpoint or performance monitoring pins The pins come out of RESET configured for performance monitoring PRDY The probe ready output pin is provided for use with the Intel debug port Please refer to the Pentium amp Processor Family Developer s Manual Order Number
60. me 13 0 ns 9 7 Valid Delay 2 5 20 0 ns 9 8 154 Float Delay 25 0 ns 9 1 8 455 All Non Test Outputs Valid Delay 2 5 20 0 ns 9 3 8 10 156 Non Test Outputs Float Delay 25 0 ns 9 1 3 8 10 157 Non Test Inputs Setup Time 5 0 ns 9 3 7 10 158 Non Test Inputs Hold Time 13 0 ns 9 8 7 10 APIC AC Specifications teoa PICCLK Frequency 2 0 16 66 4 m PICCLK Period 60 0 500 0 ns 4 PICCLK High Time 15 0 ns 4 60 PICCLK Low Time 15 0 ns 4 37 PENTIUM PROCESSOR WITH TECHNOLOGY intel Table 15 Pentium Processor with Technology AC Specifications for 66 MHz Bus Operation Cont d See Table 10 for Vcc and Tcase specifications 0 pF Symbol Unit Figure Notes teoe PICCLK Rise Time 0 15 2 5 ns 4 teot PICCLK Fall Time 0 15 2 5 ns 4 609 PICDO 1 Time 3 0 ns 7 PICCLK PICDO 1 Hold Time 2 5 ns 7 PICDO 1 Valid Delay 4 0 38 0 ns 5 From PICCLK 28 teoj PICDO 1 Valid Delay HtoL 4 0 22 0 ns 5 From PICCLK 28 Please refer to Table 16 for footnotes 38 intel Table 16 Pentium Processor with MMX Technology Dual Processor Mode AC Specifications for 66 M
61. ng liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other property right Intel products are intended for use in medical lite saving life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Pentium Processor with technology may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained from Intel Corporation P O Box 7641 Mt Prospect IL 60056 7641 or call 1 800 879 4683 or visit Intels website at http www intel com Third party brands and names are the property of their respective owners COPYRIGHT INTEL CORPORATION 1997 PENTIUM amp PROCESSOR WITH TECHNOLOGY PAGE PAGE 1
62. ns optional extensions to the architecture which allow 4 Kbyte and 4 Mbyte page sizes The Pentium processors have added significant data integrity and error detection capability Data parity checking is still supported on a byte by byte basis Address parity checking and internal parity checking features have been added along with a new exception the machine check exception As more and more functions are integrated on chip the complexity of board level testing is increased To address this the Pentium processors have increased test and debug capability The Pentium processors implement IEEE Boundary Scan Standard 1149 1 In addition the Pentium processors have specified 4 breakpoint pins that correspond to each of the debug registers and externally indicate a breakpoint match Execution tracing provides external indications when an instruction has completed execution in either of the two internal pipelines or when a branch has been taken System Management Mode SMM has been implemented along with some extensions to the SMM architecture Enhancements to the virtual 8086 mode have been made to increase performance by reducing the number of times it is necessary to trap to a virtual 8086 monitor Figure 1 shows a block diagram of the Pentium processor with MMX technology as a representative of the Pentium processor family The block diagram shows the two instruction pipelines the u pipe and the v pipe The u pipe can exe
63. ocessor with MMX technology the power consumption can transition from a low level of power to a much higher level or high to low power very rapidly A typical example would be entering or exiting the Stop Grant State Another example would be executing a HALT instruction causing the Pentium processor with MMX technology to enter the AutoHALT Power Down State or transitioning from HALT to the Normal State All of these examples may cause abrupt changes in the power being consumed by the Pentium processor with MMX technology Note that the AutoHALT Power Down feature is always enabled even when other power management features are not implemented Bulk storage capacitors with a low Effective Series Resistance ESR in the 100 to 1000 range are required to maintain a regulated supply voltage during the interval between the time the current load changes and the point that the regulated power PENTIUM PROCESSOR WITH MMX TECHNOLOGY supply output can react to the change in load In order to reduce the ESR it may be necessary to place several bulk storage capacitors in parallel These capacitors should be placed near the Pentium processor with MMX technology on both the and Vcc3 plane to ensure that the supply voltage stays within specified limits during changes in the supply current during operation Detailed decoupling recommendations are provided in the Flexible Motherboard Design Guidelines application note Order Number 2
64. or on the address bus during inquire cycles APCHK will remain active for one clock each time a parity error is detected including during dual processing private snooping APICEN PICD1 Advanced Programmable Interrupt Controller Enableenables or disables the on chip APIC interrupt controller If sampled high at the falling edge of RESET the APIC is enabled APICEN shares a pin with the PICD1 signal 14 intel PENTIUM PROCESSOR WITH MMX TECHNOLOGY Table 2 Quick Pin Reference Cont d Symbol Type Name and Function BE7 BE4 BE3 BE0 The byte enable pins are used to determine which bytes must be written to external memory or which bytes were requested by the CPU for the current cycle The byte enables are driven in the same clock as the address lines A31 3 Additionally the lower 4 byte enables BE3 BE0 are used on the Pentium processor with MMX technology as APIC ID inputs and are sampled at RESET In dual processing mode 4 is used as an input during Flush cycles BF 1 0 The bus frequency pins determine the bus to core frequency ratio BF 1 0 are sampled at RESET and cannot be changed until another non warm 1 ms assertion of RESET Additionally BF 1 0 must not change values while RESET is active See Table for Bus Frequency Selections BOFF The backoff input is used to abort all outstanding bus cycles that have not yet completed In res
65. ples The laboratory testing was done using a thermocouple made by Omega part number 5TC TTK 36 36 e Attach the thermocouple bead or junction to the center of the package top surface using high thermal conductivity cements The laboratory testing was done by using Omega Bond part number OB 100 e The thermocouple should be attached at 90 degree angle as shown in Figure 14 e The hole size should be smaller than 0 150 in diameter e Make sure there is no contact between thermocouple cement and heatsink base The contact will affect the thermocouple reading 46 5 1 1 THERMAL EQUATIONS AND DATA For the Pentium processor with MMX technology an ambient temperature TA air temperature around the processor is not specified directly The only restriction is that Tc is met To calculate TA values the following equations may be used Tc P Oca Osa Where Ambient and case temperature Case to ambient thermal resistance C Watt OJA Junction to ambient thermal resistance C Watt Junction to case thermal resistance C Watt P Maximum power consumption Watt Table 20 and Table 21 list the and Oca values for the Pentium processor with MMX technology with passive heatsinks is thermal resistance from die to package case values shown in these tables are typical values The actual values depend on actua
66. ponse to BOFF the Pentium processor with MMX technology will float all pins normally floated during bus hold in the next clock The processor remains in bus hold until BOFF is negated at which time the Pentium processor with MMX technology restarts the aborted bus cycle s in their entirety PM BP 1 0 The breakpoint pins BP3 0 correspond to the debug registers DR3 DRO These pins externally indicate a breakpoint match when the debug registers are programmed to test for breakpoint matches BP1 and BPO are multiplexed with theperformance monitoring pins PM1 and PMO The PB1 and bits in the Debug Mode Control Register determine if the pins are configured as breakpoint or performance monitoring pins The pins come out of RESET configured for performance monitoring BRDY The burst ready input indicates that the external system has presented valid data on the data pins in response to a read or that the external system has accepted the Pentium processor with MMX technology data in response to a write request This signal is sampled in the T2 T12 and T2P bus states BRDYC The burst ready copy is functionally identical to BRDY BREQ The bus request output indicates to the external system that the Pentium processor with MMX technology has internally generated a bus request This signal is always driven whether or not the Pentium processor with MMX technology is driving its bus
67. processor enters System Management Mode SMIACT An active system management interrupt activeoutput indicates that the processor is operating in System Management Mode STPCLK Assertion of the stop clock input signifies a request to stop the internal clock of the Pentium processor with MMX technology thereby causing the core to consume less power When the CPU recognizes STPCLKZ the processor will stop execution on the next instruction boundary unless superseded by a higher priority interrupt and generate a stop grant acknowledge cycle When STPCLK is asserted the Pentium processor with MMX technology will still respond to interprocessor and external snoop requests The testability clock input provides the clocking function for the Pentium processor with MMX technology boundary scan in accordance with the IEEE Boundary Scan interface Standard 1149 1 It is used to clock state information and data into and out of the Pentium processor with MMX technology during boundary scan TDI The test data inputis a serial input for the test logic TAP instructions and data are shifted into the Pentium processor with MMX technology on the TDI pin on the rising edge of TCK when the TAP controller is in an appropriate state TDO The test data output is a serial output of the test logic instructions and data are shifted out of the Pentium processor with MMX technology on the TDO pin on TCK s falling
68. r steppings 2 3 Quick Pin Reference This section gives a brief functional description of each of the pins For a detailed description see the Hardware Interface chapter in the Pentium Processor Family Developers Manual Order Number 241428 NOTE All input pins must meet their AC DC specifications to guarantee proper functional behavior 13 PENTIUM PROCESSOR WITH TECHNOLOGY The symbol at the end of a signal name indicates that the active or asserted state occurs when the signal is at a low voltage When symbol is not present after the signal name the signal is active or asserted at the high voltage level Square brackets around a signal name indicate that the signal is intel The following pins become l O pins when two Pentium processors with MMX technology operating in a dual processing environment ADS CACHE HIT HITM HLDA LOCK M lO D C W R SCYC BE 4 defined only at RESET Table 2 Quick Pin Reference Symbol Type Name and Function A20M When the address bit 20 mask pin is asserted the Pentiun processor with MMX technology emulates the address wraparound at 1 Mbyte which occurs on the 8086 by masking physical address bit 20 A20 before performing a lookup to the internal caches or driving a memory cycle on the bus The effect of 2 is undefined in protected mode A20M must be asserted only when the processor is in real mode A20M
69. ration e Support for Intel 82498 82493 and 82497 82492 cache chipset products e Split line accesses to the code cache intel For a more detailed description of the Pentium processor family products please refer to the Pentium Processor Family Developer s Manual Order Number 241428 1 1 Pentium Processor Family Architecture The application instruction set of the Pentium processor family includes the complete Intel486 processor family instruction set with extensions to accommodate some of the additional functionality of the Pentium processors All application software written for the Intel386 Intel486 family microprocessors will run on the Pentium processors without modification on chip memory management unit MMU is completely compatible with the Intel386 family and Intel486 family of processors The Pentium processors implement several enhancements to increase performance The two instruction pipelines and floating point unit Pentium processors are capable of independent operation Each pipeline issues frequently used instructions in a single clock Together the dual pipes can issue two integer instructions in one clock or floating point instruction under certain circumstances two floating point instructions in one clock Branch prediction is implemented in the Pentium processors To support this Pentium processors implement two prefetch buffers one to prefetch code in a linear fash
70. rent 200 Vin 2 4 3 lit Input Leakage Current 400 Vin 0 4 2 5 1 This parameter is for inputs outputs without an internal pull up or pull down 2 This parameter is for inputs with an internal pull up 3 This parameter is for inputs with an internal pull down 4 Guaranteed by design 5 This specification applies to the pin when it is driven as an input 9 in JTAG mode 33 PENTIUM PROCESSOR WITH TECHNOLOGY 3 4 Specifications The AC specifications consist of output delays input setup requirements and input hold requirements AC specifications with the exception of those for the TAP signals and APIC signals are relative to the rising edge of the CLK input All timings are referenced to 1 5 volts for both 0 and 1 logic levels unless otherwise specified Within the sampling window a synchronous input must be stable for correct Pentium processor with MMX technology operation Each valid delay is specified for a 0 pF load The System designer should use buffer modeling to account for signal flight time delays intel Each Pentium processor with MMX technology specified to operate within a single bus to core ratio and a specific minimum to maximum bus frequency range corresponding to a minimum to maximum core frequency range Operation in other bus to core ratios or outside the specified operating frequency range is not supported For example the
71. ronous in dual processing mode All signals which have a setup or hold time with respect to a falling or rising edge of RESET in UP mode should be measured with respect to the first processor clock edge in which RESET is sampled either active or inactive in dual processing mode 24 The PHIT and PHITM signals operate at the core frequency 25 These signals are measured on the rising edge of adjacent CLKs at 1 5V To ensure a 1 1 relationship between the amplitude of the input jitter and the internal and external clocks the jitter frequency spectrum should not have any power spectrum peaking between 500 kHz and 1 3 of the CLK operating frequency The amount of jitter present must be accounted for as a component of CLK skew between devices The internal clock generator requires a constant frequency CLK input to within 250 ps Therefore the CLK input cannot be changed dynamically 26 dual processing mode timing 114 is replaced by Timing t14 is required for external snooping e g address setup to the CLK in which EADS is sampled active in both uniprocessor and dual processor modes 27 BRDYC and are used as reset configuration signals to select buffer size 28 This assumes an external pull up resistor to Vcc and a lumped capacitive load The pull up resistor must be between 300 ohms and 1K ohms the capacitance must be between 20 pF and 240 pF and the RC product must be between 6 ns and 36 ns VOL for PICDO 1 is 0 5
72. strictions imposed by 3 3V buffers 3 2 Absolute Maximum Ratings Table 9 provides stress ratings only Functional operation at the Absolute Maximum Ratings is not implied guaranteed Functional operating conditions are given in the AC and DC specification tables Extended exposure to the maximum ratings may affect device reliability Furthermore although the Pentium processor with MMX technology contains protective circuitry to resist damage from electrostatic discharge always take precautions to avoid high static voltages or electric fields Table 9 Absolute Maximum Ratings Symbol Unit Notes Storage Temperature 65 150 Case Temperature Under 65 110 Bias Vcca Supply Voltage with 0 5 4 6 V respect to Vss Vcc2 Supply Voltage with 0 5 3 7 V respect to Vss Only Buffer DC Input 0 5 0 5 not to V Voltage exceed Vcc3 WARNING Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage These are stress ratings only Operation beyond the DC specifications is not recommended or guaranteed and extended exposure beyond the DC specifications may affect device reliability 30 intel PENTIUM PROCESSOR WITH MMX TECHNOLOGY 3 3 DCSpecifications Table 10 and Table 11 list the DC Specifications of the Pentium processor with MMX technology Table
73. uction cache this pin is asserted two clocks after EADS is sampled asserted If the inquire cycle misses the Pentium processor with MMX technology cache this pin is negated two clocks after EADS This pin changes its value only HITM until the line is completely written back The hit to a modified line output is driven to reflect the outcome of an inquire cycle It is asserted after inquire cycles which resulted in a hit to a modified line in the data cache It is used to inhibit another bus master from accessing the data HLDA driven one clock cycle after HLDA is de asserted The bus hold acknowledge pin goes active in response to a hold request driven to the processor on the HOLD pin It indicates that the Pentium processor with technology has floated most of the output pins and relinquished the bus to another local bus master When leaving bus hold HLDA will be driven inactive and the Pentium processor with MMX technology will resume driving the bus If the Pentium processor with MMX technology has a bus cycle pending it will be HOLD technology will recognize HOLD during reset In response to the bus hold request the Pentium processor with MMX technology will float most of its output and input output pins and assert HLDA after completing all outstanding bus cycles The Pentium processor with MMX technology will maintain its bus in this state until HOLD is de asserted HOLD is not recognized during LOCK
74. utput of the Dual processor an input of the Primary processor The Dual processor drives DPEN low to the Primary processor at RESET to indicate that the Primary processor should enable dual processor mode DPEN may be sampled by the system at the falling edge of RESET to determine if the dual processor socket is occupied is multiplexed with PICDO EADS This signal indicates that a validexternal address has been driven onto the Pentium processor with technology address pins to be used for an inquire cycle EWBE The external write buffer empty input when inactive high indicates that a write cycle is pending in the external system When the Pentium processor with MMX technology generates a write and EWBE is sampled inactive the Pentium processor with MMX technology will hold off all subsequent writes to all E or M state lines in the data cache until all write cycles have completed as indicated by EWBE being active FERR The floating point error pin is driven active when an unmasked floating point error occurs FERR is similar to the ERROR on the Intel887 math coprocessor is included for compatibility with systems using DOS type floating point error reporting FERR is never driven active by the Dual processor 17 PENTIUM PROCESSOR WITH TECHNOLOGY intel Table 2 Quick Pin Reference Cont d Symbol Type Name and Fun

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