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Dataram 8GB DDR3-1333

1. Front Side Back Side Name Function 1 Vrerpal31 DQ25 61 A2 91 DQ41121Vss HEI Vss 181A1 211Vss CB 7 0 Data Check Bits 2 Vss 82 Vss 62 Von 92 Vss 122DQ4 152 DM3 182 Voo 212DM5 DQ 63 0 Data Bits 3 DQO 33 DQS3 63 CK1 93 DQS5f123 DAS 153 NC 183 Voo 213NC DQS 8 0 DQS 8 0 Differential Data Strobes 4 DQ1 34 DOS3 64 CK1 94 DQS5f124Vss 154 Vss 184 CKO 214Vss DM 8 0 Data Mask 5 Vss 35 Vss 65 Voo 95 Vss f125DmMo 155 DQ30 185 CKO 215DQ46 CK 1 0 CK 1 0 Differential Clock Inputs 6 DQS0 36 DQ26 66 Voo 96 DQ42 126NC 156DQ31 186 Voo 216 DQ47 CKE 1 0 Clock Enables 7 DQSO 37 DQ27 67 Vreca 97 DQ43 127 Vss 157 Vss 187 Event 217 Vss CAS Column Address Strobe 8 Vss 38 Vss 68 Par_In NC 98 Vss 128DQ6 158 CB4 188 AO 218 DQ52 RAS Row Address Strobe 9 DQ2 39CB0 69 VDD 99 DQ48 129 DQ7 159 CB5 189 Voo 219DQ53 S 3 0 Chip Selects 10DQ3 40CB1 70 A10 AP 100 DQ49 130 Vss 160 Vss 190 BA1 220Vss_ WE Write Enable 11Vss MI Vss 71 BAO 101Vss 131 DQ12 161 DM8 191 Mon 221DM6 A 15 0 Address Inputs 12DQ8 42 DQS8 72 Vpop 102 DQS6132 DQ13 162 NC 192 RAS 222NC BA 2 0 Bank Addresses 13DQ9 43 DQS8 73 WE 103 DQS6 133 Vss 163 Vss 193 S0 223 Vss ODT 1 0 On Die Termination Inputs 14Vss_ MA Vss 74 CAS 104Vss 134DM1 164 CB6 194 Voo 224DQ54 SA 2 0 SPD Address 15 DQS1 45 CB2 75 Voo 105DQ50 135NC 165 CB7 195O0DTO 225DQ55 SCL SPD Clock Input 16 DQS1 46 CB3 76 S1 106 DQ51 136 Vss 166 Vss 196 A13 226 Vss SDA SPD Data Input Output 17 Vss
2. Front view le 133 35 5 250 l 9 50 0 374 30 00 1 181 z E a i mie i 0 681 O t NNNMNNN Nnnn NNANANAANNMNANAANAAAAANAANHANAANANANAAARANNANAAAAAANN y 5 00 A 0 197 cel 5 175 47 00 71 00 0 204 1 850 2 795 123 00 lt 4 843 P Back view Side view 4 00 Max 0 157 Max 4 00 Min 0 157 Min 1 27 10 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches EEN a a a p a a E Psa Document 06981 Revision A 26 OCT 11 Dataram Corporation 2011 Page 2 D patagan DTM64380A Omega Wue and Performa S1O S0 O DMRO O DQSRO O DQSRO O DQS DOS CS DM DQS DOS CS D DQR 7 0 O 1 0 7 0 VO 7 0 DMR1 O DQSR1 O DQSR1 O DQS DOS CS DM DQS DOS CS D DQR 15 8 VO 7 0 VO 7 0 DMR2 DQSR2 DQSR2 DQS DOS DQR 23 16 O O 7 0 CS DM DQS DOS VO 7 0 DMR3 DQSR3 DQSR3 DQS DOS CS DM DQS DOS DQR 31 24 O 1 017 0 VO 7 0 DMR8 DQSR8 DQSR8 DQS DOS CS DM DQS DOS CBRI7 0 VO 7 0 1 0 7 0 All 15 OHMS DQ 63 0 O VWA O DQR 63 0 CB 7 0 O VW CBRI7 0 DQS 8 0 O VW O DQSR 8 0 IDQS 8 0 O WAN O DASRIB 0 DM 8 0 O VA O DMR 8 0 GLOBAL SDRAM CONNECTS All 39 OHMS BA 2 0 A 15
3. 47 0 53 tck Clock Cycle Time tck 1 5 1 875 ns Clock Low Level Width tcL avg 0 47 0 53 tck Data Input Hold Time after DQS Strobe toH 65 ps DQ Input Pulse Width toipw 400 ps DQS Output Access Time from Clock tpascK 255 255 ps Write DQS High Level Width tbasH 0 45 0 55 tck avg Write DQS Low Level Width toast 0 45 0 55 tcx avg DQS Out Edge to Data Out Edge Skew toasa 125 ps Data Input Setup Time Before DQS Strobe tos 30 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tck avg DQS Falling Edge to Clock Setup Time toss 0 2 tck avg Clock Half Period tup minimum of tcy or tet ns Address and Command Hold Time after Clock tin 140 ps Address and Command Setup Time before Clock tis 65 ps Load Mode Command Cycle Time turD 4 tck DQ to DQS Hold Lou 0 38 tck avg Active to Precharge Time tras 36 9 trEFI ns Active to Active Auto Refresh Time tre 49 125 ns RAS to CAS Delay trop 13 125 ns Average Periodic Refresh Interval 0 C lt Tcase lt 85 C REFI 7 8 us Average Periodic Refresh Interval 0 C lt Tcase lt 95 C Ion 3 9 us Auto Refresh Row Cycle Time trFc 260 ns Row Precharge Time trp 13 125 ns Read DQS Preamble Time RPRE 0 9 Note 1 tck avg Read DQS Postamble Time terest 0 3 Note 2 tck avg Row Active to Row Active Delay tRRD Max 4nCK 6ns ns Internal Read to Precharge Command Delay tRTP Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twPRE 0 9 tck avg Write DQS Postamble Time twpst 0
4. 47 Vss 77 ODT1 107 Vss 137 DQ14 167 NC TEST 197 Von 227 DQ60 EVENT Temperature Sensing 18 DQ10 48 Vr NC 78 Voo 108 DQ56 138 DQ15 168 RESET 198 S3 NC 228 DQ61 RESET Reset for register and DRAMs 19DQ11 49 Vr NC 79 S2 NC 109DQ57 f139Vss 169 CKE1 199 Vss 229Vss PAR_IN Parity bit for Addr Ctrl 20Vss 50 CKEO 80 Vss 110Vss 140 DQ20 170 Voo 200DQ36 230DM7 ERR_OUT Error bit for Parity Error 21 DQ16 51 Vbo 81 DQ32 111 DQS7141 DQ21 171 A15 201DQ37 231NC A12 BC Combination input Addr12 Burst Chop 22 DQ17 52 BA2 82 DQ33 112 DQS7 142 Vss 172A14 202 Vss 232 Vss A10 AP Combination input Addr10 Auto precharge 23Vss 53 Err_Our NC 83 Vss 113Vss 143 DM2 173 Voo 203 DM4 233 DQ62 Vss Ground 24 DQS2 54 Von 84 DQS4 114 DQ58 144NC 174A12 IBC 204 NC 234 DQ63 Von Power 25 DQS2 55 A11 85 DQS4 115 DQ59 Map Ve 175 A9 205 Vss 235 Vss VppsPo SPD EEPROM Power 26Vss 56A7 86 Vss 116Vss 146 DQ22 176 Von 206 DQ38 236 Vbospo VreFDa Reference Voltage for DQ s 27 DQ18 57 Von 87 DQ34 117 SA0 147 DQ23 177 A8 207 DQ39 237 SA1 Vrerca Reference Voltage for CA 28 DQ19 58 A5 88 DQ35 118 SCL f148Vss 178 A6 208 Vss 238 SDA Vr Termination Voltage 29Vss 59A4 89 Vss 119SA2 ag DQ28 179 Voo 209DQ44 239Vss NC No Connection 30 DQ24 60 Von 90 DQ40 120Vrr 150 DQ29 180 A3 210DQ45 240 Vrr Not used Document 06981 Revision A 26 OCT 11 Dataram Corporation 2011 Page 1 rr DTM64380A 8 GB 240 Pin 2Rx8 Unbuffered ECC DDR3 DIMM
5. READ to Bank Active Read Ipp1 PRECHARGE 630 mA Precharge Current Precharge Power Ipp2P Precharge power down current Slow exit 270 MA Down Current Precharge Power Ipp2P Precharge power down current Fast exit 270 MA Down Current Precharge Quiet xx Precharge quiet standby current Standby Current oecH SCH E Precharge Standby Ipp2N Precharge standby current 360 mA Current Active Power Down Ipp3P Active power down current 360 mA Current Active Standby Lakes Active standby current 450 mA Current Operating Burst Burst write operating current Write Current Geh ST mA Operating Burst Burst read operating current Read Current ve ote ae Burst Refresh Ipp5 Refresh current 1485 mA Current Self Refresh Ipp6 Self refresh temperature current MAX Tc 85 C 270 mA Current Operating Bank nterlesve Read Ipp7 All bank interleaved read current 1710 mA Current One module rank in this operation rest in IDD2P slow exit All module ranks in this operation Document 06981 Revision A 26 OCT 11 Dataram Corporation 2011 Page 6 D patagan DTM64380A MEE o GB 240 Pin 2Rx8 Unbuffered ECC DDR3 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit Internal read command to first data taa 13 125 20 ns CAS to CAS Command Delay tceco 4 tck Clock High Level Width tcH avg 0
6. Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Von 1 425 1 5 1 575 V UO Reference Voltage VREFDQ 0 49 Mon 0 50 Mon 0 51 Von V 1 UO Reference Voltage VREFCA 0 49 Vpp 0 50 Von 0 51 Voo V 1 Notes The value of Vrer is expected to equal one half Vpp and to track variations in the Vor DC level Peak to peak noise on Vrer may not exceed 1 of its DC value For Reference Vpp 2 15 mV DC Input Logic Levels Single Ended T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vue VREF 0 1 Vpop V Logical Low Logic 0 Vuupe Vss Vrer 0 1 V AC Input Logic Levels Single Ended T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin ac VREF 0 175 V Logical Low Logic 0 Vit ac Vrer 0 175 V Document 06981 Revision A 26 OCT 11 Dataram Corporation 2011 Page 4 D patagan DTM64380A Opeerging aue and Performance 8 GB 240 Pin 2Rx8 Unbuffered ECC DDR3 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Differentia
7. contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06981 Revision A 26 OCT 11 Dataram Corporation 2011 Page 12
8. 0 IRAS ICAS MWE VTT All 39 OHMS CKE 1 0 ODT 1 0 ow S 1 0 VTT All 240 OHMS Rech Vss DMR4 O DQSR4 O DQSR4 O DQR 39 32 O DMR5 O 8 GB 240 Pin 2Rx8 Unbuffered ECC DDR3 DIMM a E DQS DAS CS DM DQS DAS CS DM VO 7 0 VO 7 0 DQSR5 O DQSR5 O DQRI47 40 O DMR6 O DOS DOS CS DM DQS DOS CS DM VO 7 0 VO 7 0 DQSR6 DQR 55 48 DMR7 DQSR7 DQR 63 56 1DQS DQS CS DM 1 0 7 0 DQS DOS Te DQS CS DM VO 7 0 VO 7 0 2 2 pF CK 1 0 Ob CK 1 0 VoD All 36 OHMS 100 nf CKO CKO 100 nf ICK1 CK1 V DECOUPLING DDSPD te Serial PD VoD t All Devices VREF_DQ t i T i All SDRAMs Vss T All Devices VREF_CA All SDRAMs Ver Es All SDRAMs EVENT TEMPERATURE MONITOR SERIAL PD SES SCL SAO SA1 SA2 Document 06981 Revision A 26 OCT 11 Dataram Corporation 2011 Page 3 D patagan DTM64380A 8 GB 240 Pin 2Rx8 Unbuffered ECC DDR3 DIMM Opening Wue and Performans Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TsTORAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperature Operating Tease 0 95 C Voltage on Vpp relative to Vss Vop 0 4 1 975 V Voltage on Any Pin relative to Vss Vin
9. 0x11 121 Module Manufacturing Date 0x33 122 Module Serial Number 0x42 123 Module Serial Number Ox2F 124 Module Serial Number 0x45 125 Module Serial Number 0x27 126 Cyclical Redundancy Code CRC CRC 0x54 127 Cyclical Redundancy Code CRC CRC 0x98 128 Module Part Number M 0x4D 129 Module Part Number 3 0x33 130 Module Part Number 9 0x39 131 Module Part Number 1 0x31 132 Module Part Number B 0x42 133 Module Part Number 1 0x31 134 Module Part Number G 0x47 135 Module Part Number 7 0x37 136 Module Part Number 3 0x33 137 Module Part Number B 0x42 138 Module Part Number H 0x48 139 Module Part Number 0 0x30 140 Module Part Number 0x2D 141 Module Part Number C 0x43 142 Module Part Number H 0x48 143 Module Part Number 9 0x39 144 145 Module Part Number 0x20 146 147 Module Revision Code UNUSED 0x00 148 DRAM Manufacturer ID Code Least Significant Byte 0x80 149 DRAM Manufacturer ID Code Most Significant Byte OxCE 150 175 Manufacturer s Specific Data UNUSED 0x00 176 255 Open for customer use UNUSED 0x00 Note Bytes 119 125 and 150 255 may be different than shown A a Ig Ge a a aa Document 06981 Revision A 26 OCT 11 Dataram Corporation 2011 Page 11 ttc DIM64380A 8 GB 240 Pin 2Rx8 Unbuffered ECC DDR3 DIMM DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information
10. 3 tck avg Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min 2 The maximum postamble is bound by tHZDQS max C a a E E a a a E E S Document 06981 Revision A 26 OCT 11 Dataram Corporation 2011 Page 7 tre DTM64380A uwiereed 8 GB 240 Pin 2Rx8 Unbuffered ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Byte Function Value Hex Number of Bytes Used Number of Bytes in SPD Device CRC Coverage 0 Bit 3 Bit 0 SPD Bytes Used 176 0x92 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 1 SPD Revision Rev 1 1 0x11 2 Key Byte DRAM Device Type DDR3 SDRAM 0x0B Key Byte Module Type 3 Bit 3 Bit 0 Module Type UDIMM 0x02 Bit 7 Bit 4 Reserved 0 SDRAM Density and Banks 4 Bit 3 Bit 0 Total SDRAM capacity in megabits 4Gb 0x04 Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved 0 SDRAM Addressing 5 Bit 2 Bit 0 Column Address Bits 10 0x21 Bit 5 Bit 3 Row Address Bits 16 Bit 7 6 Reserved 0 Module Nominal Voltage VDD Bit 0 NOT 1 5 V operable Bit 1 1 35 V operable Bit 2 1 2X V operable 6 Bit 3 Reserved 0x00 Bit 4 Reserved Bit 5 Reserved Bit 6 Reserved Bit 7 Reserved Module Organization 7 Bit 2 Bit 0 SDRAM Devic
11. Refresh PASR Module Thermal Sensor 32 Bit 6 Bit 0 Thermal Sensor Accuracy 0 0x80 Bit 7 Thermal Sensor With TS SDRAM Device Type Bit 6 Bit 0 Non Standard Device Description 0 33 Bit 7 SDRAM Device Type Std Mono 0x00 34 59 Reserved UNUSED 0x00 Module Nominal Height 60 Bit 4 Bit 0 Module Nominal Height max inmm 29 lt h lt 30 0x0F Bit 7 Bit5 Reserved 0 Module Maximum Thickness 61 Bit 3 Bit 0 Front in mm baseline thickness 1mm 1 lt th lt 2 0x11 Bit 7 Bit 4 Back in mm baseline thickness 1 mm 1 lt th lt 2 Reference Raw Card Used 62 Bit 4 Bit 0 Reference Raw Card RICE 0x64 Bit 6 Bit 5 Reference Raw Card Revision Rev 3 Bit 7 Reserved 0 Address Mapping from Edge Connector to DRAM 63 Bit 0 Rank 1 Mapping Registered DIMM Reserved Mirrored 0x01 Bit 7 Bit 1 Reserved 0 64 116 Module Specific Section UNUSED 0x00 117 Module Manufacturer ID Code Least Significant Byte 0x80 EE EE Ech Document 06981 Revision A 26 OCT 11 Dataram Corporation 2011 Page 10 tre DTM64380A quam ene bs 8 GB 240 Pin 2Rx8 Unbuffered ECC DDR3 DIMM 118 Module Manufacturer ID Code Most Significant Byte OxCE 119 Module Manufacturing Location 0x01 120 Module Manufacturing Date
12. e Width 8 Bits 0x09 Bit 5 Bit 3 Number of Ranks 2 Rank Bit 7 6 Reserved 0 Module Memory Bus Width 8 Bit 2 Bit 0 Primary bus width in bits 64 Bits 0x0B Bit 4 Bit 3 Bus width extension in bits 8 Bits Bit 7 Bit 5 Reserved 0 Fine Timebase FTB Dividend Divisor 9 Bit 3 Bit 0 Fine Timebase FTB Divisor 1 0x11 Bit 7 Bit 4 Fine Timebase FTB Dividend 1 EH Document 06981 Revision A 26 OCT 11 Dataram Corporation 2011 Page 8 rr DIM64380A quinones 8 GB 240 Pin 2Rx8 Unbuffered ECC DDR3 DIMM 1 MTB 10 Medium Timebase MTB Dividend 0 125ns 01 8 MTB 11 Medium Timebase MTB Divisor 0 125ns 9x08 12 ISDRAM Minimum Cycle Time tCKmin 1 5ns 0x0C 13 Reserved UNUSED 0x00 CAS Latencies Supported Least Significant Byte Bit 0 CL 4 Bit 1 CL 5 Bit 2 CL 6 X 14 Bit 3 CL 7 X 0x3C Bit 4 CL 8 X Bit 5 CL 9 X Bit 6 CL 10 Bit 7 CL 11 CAS Latencies Supported Most Significant Byte Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 15 Bit 3 CL 15 0x00 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved 16 Minimum CAS Latency Time tAAmin 13 125ns 0x69 17 Minimum Write Recovery Time tWRmin 15 0ns 0x78 18 Minimum RAS to CAS Delay Time tRCDmin 13 125ns 0x69 19 Minimum Row Active to Row Act
13. ive Delay Time tRRDmin 6 0ns 0x30 20 Minimum Row Precharge Delay Time tRPmin 13 125ns 0x69 Upper Nibbles for tRAS and tRC 21 Bit 3 Bit 0 tRAS Most Significant Nibble 1 0x11 Bit 7 Bit 4 tRC Most Significant Nibble 1 22 no Active to Precharge Delay Time tRASmin Least Significant 36 0ns 0x20 23 a Active to Active Refresh Delay Time tRCmin Least Significant 49 125ns 0x89 Minimum Refresh Recovery Delay Time tRFCmin Least Significant 260 0ns 24 Byte 0x20 25 Gg Refresh Recovery Delay Time tRFCmin Most Significant 260 0ns 0x08 26 Minimum Internal Write to Read Command Delay Time tWTRmin 7 5ns 0x3C 27 Minimum Internal Read to Precharge Command Delay Time tRTPmin 7 5ns 0x3C nn Tee Document 06981 Revision A 26 OCT 11 Dataram Corporation 2011 Page 9 tre DTM64380A qurm eek 8 GB 240 Pin 2Rx8 Unbuffered ECC DDR3 DIMM Upper Nibble for tFAW 28 Bit 3 Bit 0 FAW Most Significant Nibble 0 0x00 Bit 7 Bit 4 Reserved 0 29 sal Four Activate Window Delay Time tFAWmin Least Significant 30 0ns OxFO SDRAM Optional Features Bit 0 RZQ 6 X 30 Bit 1 RZQ 7 X 0x83 Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support SDRAM Drivers Supported Extended Temperature Range X Extended Temperature Refresh Rate Auto Self Refresh ASR 31 On die Thermal Sensor ODTS Readout 0x01 Reserved Reserved Reserved Partial Array Self
14. l Input Logic High VIH DIFF 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low Vu pr DC Vss AC Vss 0 4 0 200 V a ane a Cross Point Voltage Vx 0 150 0 150 v Capacitance T 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO CK1 CK1 Cox 7 2 13 5 pF Input Capacitance Address BA 2 0 A 15 0 RAS CAS ANE C 13 5 27 pF Input Capacitance Control SO S1 CKEO CKE1 ODTO ODT1 C 6 8 13 5 pF Input Output Capacitance gear CB 7 0 DQSI8 0 DQS 8 0 Cio 3 5 pF ZQ Capacitance ZQ Cza S 6 pF DC Characteristics Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current lit 18 18 HA 1 2 Any input 0 V lt VIN lt VDD Output Leakage Current Jo 10 10 HA 2 3 OV lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ s DQS DQS and ODT are disabled C EECHER Document 06981 Revision A 26 OCT 11 Dataram Corporation 2011 Page 5 D patagan DTM64380A MEE o GB 240 Pin 2Rx8 Unbuffered ECC DDR3 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Test Condition Max unit Value Operating One Bank Active Ipp0 Operating current One bank ACTIVATE to PRECHARGE 540 mA Precharge Current Operating One Operating current One bank ACTIVATE to
15. ttc DIM64380A 8 GB 240 Pin 2Rx8 Unbuffered Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high Operating Voltage 1 5 V 0 075 V I O Type SSTL_15 On board PC temperature sensor with integrated Serial Presence Detect SPD EEPROM Data Transfer Rate 10 6 Gigabytes sec Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 6 7 8 and 9 Differential Data Strobe signals SDRAM Addressing Row Col Bank 16 10 3 Fully ROHS Compliant Pin Configuration ECC DDR3 DIMM Identification DTM64380A 1Gx72 8GB 2Rx8 PC3 10600E 9 11 E3 Performance range Clock Module Speed CL trep trp 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Description DTM64380A is an Unbuffered 1Gx72 memory module which conforms to JEDEC s DDR3 PC3 10600 standard The assembly is Dual Rank Each Rank is comprised of nine 512Mx8 DDR3 1333 Samsung SDRAMs One 2K bit EEPROM is used for Serial Presence Detect A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating temperature of 95C Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals Pin Description

Dataram 8GB DDR3-1333

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