Dataram 4GB 2Rx8 PC3-10600R-9
Contents
1. AC Operating Conditions PARAMETER Symbol Min Max Unit Internal read command to first data taa 13 125 20 ns CAS to CAS Command Delay tceco 4 tck Clock High Level Width tcH avg 0 47 0 53 tck Clock Cycle Time tck 1 5 1 875 ns Clock Low Level Width tcL avg 0 47 0 53 tck Data Input Hold Time after DQS Strobe toH 65 ps DQ Input Pulse Width toipw 400 ps DQS Output Access Time from Clock tpascK 255 255 ps Write DQS High Level Width Iooen 0 45 0 55 tck avg Write DQS Low Level Width toast 0 45 0 55 tck avg DQS Out Edge to Data Out Edge Skew toasa 125 ps Data Input Setup Time Before DQS Strobe tos 30 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tck avg DQS Falling Edge to Clock Setup Time toss 0 2 tck avg Clock Half Period tHP minimum of tcy or teL ns Address and Command Hold Time after Clock Du 140 ps Address and Command Setup Time before Clock tis 65 ps Load Mode Command Cycle Time turD 4 tck DQ to DQS Hold Lou 0 38 tcx avg Active to Precharge Time tras 36 O tREFI ns Active to Active Auto Refresh Time tre 49 125 ns RAS to CAS Delay trop 13 125 ns Average Periodic Refresh Interval 0 C lt Tcase lt 85 C REFI 7 8 us Average Periodic Refresh Interval 0 C lt Tcase lt 95 C REFI 3 9 us Auto Refresh Row Cycle Time trFc 160 ns Row Precharge Time trp 13 125 ns Read DQS Pr2. Bit 0 Primary bus width in bits Bit 4 Bit 3 Bus width extension in bits Bit 7 Bit 5 Reserved Fine Timebase FTB Dividend Divisor Bit 3 Bit 0 Fine Timebase FTB Divisor 2 Bit 7 Bit 4 Fine Timebase FTB Dividend 5 Medium Timebase MTB Dividend 0 125ns Medium Timebase MTB Divisor 0x0 0 125ns 12 SDRAM Minimum Cycle Time tCKmin 0x0 UNUSED 0x00 CAS Latencies Supported Least Significant Byte BitO CL 4 Bit 1 CL 5 Bit 2 CL 6 Bit 3 CL 7 Bit 4 CL 8 Bit 5 CL 9 Bit 6 CL 10 Bit 7 CL 11 Document 06944 Revision A 3 Oct 11 Dataram Corporation 2011 Page 8 DPDATARAM DTM64328D DA 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM CAS Latencies Supported Most Significant Byte 0x00 Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 Bit 3 CL 15 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved 16 Minimum CAS Latency Time tAAmin 13 125ns 0x69 17 Minimum Write Recovery Time tWRmin 0x78 Minimum RAS to CAS Delay Time tRCDmin 13 125ns Minimum Row Active to Row Active Delay Time RRDmin 0x3 Minimum Row Precharge Delay Time tRPmin 13 125ns 0x6 Upper Nibbles for tRAS and tRC Bit 3 Bit 0 tRAS Most Significant Nibble Bit 7 Bit 4 tRC Most Significant Nibble Minimum Active to Precharge Delay Time tRASmin Least Significant Byte ee Least Significant
3. DpasR20 DQSR6 O DQSR2 DQSR6 DMR2 DMR6 TDQSR11 TDQSR15 DQR 23 16 DQR 55 48 O DQSR3 DQSR7 O DQSR3 DQSR7 O DMR3 DMR7O TDQSR12 ITDQSR16 O DQR 31 24 DQR 63 56 DQSR8 IDQSR8 O DMR8 TDQSR17 CBR 7 0 TO SDRAMS VDD Von All All 39 OHMS 100 nF All 39 OHMS 100 nF 22 OHMS r All 15 OHMS See Ee IS LCLK 1 0 RCLK 1 0 DOIS3 0 O WA O g Q 63 0 63 0 IS1 WJ IRS1 ILCLKI1 0 IRCLKI1 0 CB 7 0 O VVW _ CBRI7 0 PART Mu BA 2 0 R A 15 0 WA H AAR DQS 8 0 O VWA O _ DasR s 0 RAS WW aen DQS 8 0 O WAN O_ DASRIB 0 CAS WN ty fe ee ME WA I WER DM 8 0 O VW O_ DMRJB 0 CKEO VWW a CKEOR vo ja CKE1 WA X CKEIR DECOUPLING i ITDQS 17 9 O VW O TDQSR 17 9 ODT AN 9 SCENE VDDSPD te Serial PD ODT1 W w ODTIR VDD All Devices PAR IN WA ERR OUT VREF_DQ t T All SDRAMs GLOBAL SDRAM CONNECTS Co L R CLK 1 0 y Vss All Devices 120 All 39 OHMS OHMS 3 REF_CA Es All SDRAMs BA 2 0 R ICKO L R CLK 1 0 VTT m AI SDRAMs RASR SDRAMS ICASR INER VTT nT All 240 OHMS TEMPERATURE MONITOR e All 39 OHMS E SCL Berg SDA 8 NM ODT 1 0 R owed SAO SA1 SA2 RS 1 0 VTT Vss Document 06944 Revision A 3 Oct 11 Dataram Corporation 2011 Page 3 Garson DTMe4328D Cep Vale rd Petipa Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability 4GB 240 Pin 2Rx8 Regis
4. 1 0 On Die Termination Inputs 15 DQS1 45 CB2 75 Voo 105 DQ50 135 TDQS10 165 CB7 495O0DTO 225DQ55 SA 2 0 SPD Address 16DQS1 46CB3 76 S4 106 DQ51 136 Vss 166 Vss 196 A13 226 Vss SCL SPD Clock Input 17 Vss 47 Vss 77ODT1 f407Vss f137DQ14 167 NC TEST 197 Voo 227DQ60 SDA SPD Data Input Output 18DQ10 48 Vr 78 Voo 108 DQ56 f138DQ15 168 RESET 198 S3 NC 228 DQ61 EVENT Temperature Sensing 19DQ11 M er 79 S2 NC 109 DQ57 139 Vss 169 CKE1 199 Vss 229 Vss RESET Reset for register and DRAMs 20 Vss 50 CKEO 80 Vss 110Vss f140DQ20 170 Vop 200DQ36 230 DM7 PAR IN Parity bit for Addr Ctrl 21DQ16 GI Ven 81DQ32 111 DQS7f141 DQ21 1171 A15 201 DQ37 231 TDQS16 ERR_OUT Error bit for Parity Error 22DQ17 52 BA2 82DQ33 112 DQS7 142 Vss 172 A14 1202 Vss 232 Vss A12 BC Combination input Addr12 Burst Chop 23 Vss 53 Err Our 83 Vss 113Vss 143DM2 173 Voo 203DM4 233DQ62 A10 AP Combination input Addr10 Auto precharge 24 DQS2 54 Voo 84 DQS4 114 DQ58 f144 TDQS11 174 A12 BC 204 TDQS13 234DQ63 Vss Ground 25DQS2 55 A11 85DQS4 115 DQ59 145 Vss 175 A9 1205 Vss 235 Vss Von Power 26 Vss 56 A7 86 Vss 116Vss f146DQ22 176 Vbo 206 DQ38 236 Vbosro VopsPo SPD EEPROM Power 27DQ18 57 Voo 87DQ34 117sa0 f147DQ23 177A8 207 DQ39 237 SA1 Vrerpa Reference Voltage for DQ s 28DQ19 58A5 88Da35 J118 scL 148 Vss 178 A6 1208 Vss 238 SDA VREFCA Reference Voltage for CA 29 Vss 59 Ad 89 Vss 119SA2 f149DQ28 179 Vop 209 DQ44 239 Vss Vor Termination Voltage 3
5. 0DQ24 60 Voo 90DQ40 120V 150DQ29 180A3 210 DQ45 240 Vrr NC No Connection Not used Document 06944 Revision A 3 Oct 11 Dataram Corporation 2011 Page 1 rz DTM64328D Rea 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM Front view le 133 35 5 250 9 50 0 374 30 00 1 184 E 17 30 0 681 O IDDIE LANM O y 5 00 4 0 197 2 50 5 175 47 00 0 098 pa gt 71 00 0 204 1 850 2 795 123 00 k 4 843 Back view Side view 4 00Max 0 157 Max WI 4 00 Min 0 157 Min O NNNNNNNNNNNNMNNNNNNNNNMNNNNNINNNNNNNNNNNMNNNN NNNMNNN O 1 27 10 IA 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches Document 06944 Revision A 3 Oct 11 Dataram Corporation 2011 Page 2 rz DTM64328D 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM i FY PDAS ed Pete IRS1 O IS DQSRO DQSR4 DQSRO DQSR4 DMRO DMR4 ITDQSR9 ITDQSR13 Ra Oo oO o Ra Oo 0 2 26 468 26 26866 26 268 6S ke a a oo a a aG Eo ES E E S DQRI7 0 VO 7 0 RANK 0 VO 7 0 RANK 1 DQR 39 32 O 0 7 0 RANK 0 VO 7 0 RANK 1 DQSR1 DQSR5 DQSR1 DQSR5 DMR DMR5 ITDQSR10 ITDQSR14 DQR 15 8 DQR 47 40 O I 017 0
6. 1 Page 4 Cep Vale rd Petipa Garson DTMe4328D Differential Input Logic Levels T 0 to 70 C Voltage referenced to Vss 0 V 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High VIH DIFF 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low Vu mer DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage relative to VDD 2 Vix ous eee y Capacitance T 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO Cok 1 5 2 5 pF Input Capacitance Address BA 2 0 A 15 0 RAS CAS WE Ci 1 5 2 5 pF Input Capacitance Control S 1 0 CKE 1 0 ODT 1 0 C 1 5 2 5 DQ 63 0 CB 7 0 DQS 8 0 DQS 8 0 Input Output Capacitance DM 8 0 TDQS 17 9 Cio 3 5 pF DC Characteristics T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current lit 18 18 yA 1 2 Any input 0 V lt VIN lt VDD Output Leakage Current lot 10 10 yA 2 3 OV lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled Document 06944 Revision A 3 Oct 11 Dataram Corporation 2011 Page 5 Garson DTMe4328D eebe 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM lbo Specifications and Conditions Ta 0 to 70 C Volt
7. Byte Minimum Refresh Recovery Delay Time tRFCmin Least Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Most 160 0ns 0x0 Significant Byte iwem Se Nena TE oe tWTRmin Lo Minimum Internal Read to Precharge Command Delay Time 0x3 tRTPmin 28 Upper Nibble for tFAW Bit 3 Bit 0 tFAW Most Significant Nibble Bit 7 Bit 4 Reserved Minimum Four Activate Window Delay Time tFAWmin Least Significant Byte SDRAM Optional Features Bit 0 RZQ 6 Bit 1 RZQ 7 Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support SDRAM Drivers Supported Extended Temperature Range Extended Temperature Refresh Rate Auto Self Refresh ASR On die Thermal Sensor ODTS Readout Reserved Reserved Reserved Reserved Reserved 0x80 32 Reseved CSC E ow 15 16 17 18 19 20 21 22 23 25 26 27 29 30 31 32 Document 06944 Revision A 3 Oct 11 Dataram Corporation 2011 Page 9 Garson DTMe4328D eebe 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM Module Nominal Height Ox0F Bit 4 Bit 0 Module Nominal Height max in mm 29 lt h lt 30 Bit 7 Bits Reserved 0 Module Maximum Thickness 0x11 Bit 3 Bit 0 Front in mm baseline thickness 1 mm 1 lt th lt 2 Bit 7 Bit 4 Back in mm baseline thickness 1 mm 1 lt th lt 2 Reference Raw Card Used 0x01 Bit 4 Bit 0 Reference Raw Card Bit 6 Bi
8. Opany Vale rd efi lt DTM64328D a 2s aah ei ab ee eg ebe bee mi e Hunt Peep evs k Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high Operating Voltage 1 5V 0 075 I O Type SSTL_15 On board 12C temperature sensor with integrated serial presence detect SPD EEPROM Data Transfer Rate 10 6 Gigabytes sec Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM Identification DTM64328D 512Mx72 4GB 2Rx8 PC3 10600R 9 11 BO Performance range Clock Module Speed CL trep Ze 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Description DTM64328D is a registered 512Mx72 memory module which conforms to JEDEC s DDR3 PC3 10600 standard The assembly is Dual Rank Each Rank is comprised of nine 256Mx8 DDR3 Hynix SDRAMs One 2K bit EEPROM is used for Serial Presence Detect and a combination register PLL with Address and Command Parity is also used Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals in a Fly by topology A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating temperature of 95C Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 6 7 8 an
9. age referenced to Vss 0 V PARAMETER Symbol Test Condition Max unit Value Operating One Bank Active Ibn0 Operating current One bank ACTIVATE to PRECHARGE 468 mA Precharge Current Operating One Operating current One bank ACTIVATE to READ to Bank Active Read Ipp1 PRECHARGE 558 mA Precharge Current Precharge Power Ipp2P Precharge power down current Slow exit 216 mA Down Current Precharge Power Ipp2P Precharge power down current Fast exit 270 mA Down Current Precharge Quiet xx Precharge quiet standby current Standby Current oecH SE uy Precharge Standby Ipp2N Precharge standby current 450 mA Current A iry Power Down Ibo3P Active power down current 270 mA urrent pape Standby Ibo3N Active standby current 486 MA urrent Operating Burst x Burst write operating current Write Current Geh SA Operating Burst x Burst read operating current Read Current oi 919 mA See Refresh Lafe Refresh current 2070 mA urrent Ge Refresh Ipp6 Self refresh temperature current MAX Tc 85 C 216 mA urrent Operating Bank interleave Read Ipp7 All bank interleaved read current 3240 mA Current One module rank in this operation the rest in IDD2P slow exit All module ranks in this operation Document 06944 Revision A 3 Oct 11 Dataram Corporation 2011 Page 6 D3Zparagan DTM64328D eebe 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM
10. d 9 Bi Directional Differential Data Strobe signals SDRAM Addressing Row Col Bank 15 10 3 Fully RoHS Compliant Pin Configuration Pin Description Front Side Back Side Name Function 1 Vreroa 31 DQ25 61 A2 91 DQ41 121 Vss 151 Vss 181 A1 211 Vss CBI7 0 Data Check Bits 2 Vss 32 Vss 62 Von 92 Vss 122 D4 152 DM3 182 Voo 212 DM5 DQ 63 0 Data Bits 3 DQO 33 DQS3 63 CK1 93 DQS5 123 DAS 153 TDQS12 183 Ven 213 TDQS14 DQS 8 0 DQS 8 0 Differential Data Strobes 4 DQ1 34 DQS3 64 CK1 94 DQS5 124 Vss 154 Vss 184 CKO 214 Vss DM 8 0 Data Mask 5 Vss 35 Vss 65 Voo 95 Vss 125DMO 155DQ30 485 CKO 215DQ46 TDQS 17 9 Termination Data Strobe 6 DQSO 36DQ26 66 Vbo 96 DQ42 126 TDQS9 156 DQ31 186 Voo 216DQ47 CK 1 0 CK 1 0 Differential Clock Inputs 7 DQSO 387 DQ27 67 Vrerca 97 DQ43 127 Vss 157 Vss 187 Event 217 Vss CKE 1 0 Clock Enables 8 Vss 38 Vss 68 Parin 98 Vss 128DQ6 158 CB4 188 A0 218DQ52 CAS Column Address Strobe 9 DQ2 39 CBO 69 VDD 99 DQ48 129 DQ7 159 CB5 189 Voo 219DQ53 RAS Row Address Strobe 10 DQ3 40 CB1 70A10 AP 100 DQ49 130 Vss 160 Vss 190 BA1 220 Vss S 3 0 Chip Selects 11 Vss 41 Vss 71BA0 101Vss f 31DQ12 161DM8 191 Voo 221 DM6 WE Write Enable 12 DQ8 42 DQS8 72 Voo 102 DQS6f132DQ13 162 TDQS17 192 RAS 222 TDQS15 A 15 0 Address Inputs 13 DQ9 43 DQS8 73 WE 103 DQS6 133 Vss 163 Vss 193 SO 223 Vss BA 2 0 Bank Addresses 14 Vss 44 Vss 74 CAS 104Vss 134DM1 164 CB6 194 Voo 224DQ54 ODT
11. eamble Time RPRE 0 9 Note 1 tck avg Read DQS Postamble Time terest 0 3 Note 2 tck avg Row Active to Row Active Delay trRD Max 4nCK 6ns ns Internal Read to Precharge Command Delay for Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twPRE 0 9 tck avg Write DQS Postamble Time twest 0 3 tck avg Write Recovery Time twr 15 ns Internal Write to Read Command Delay twtr Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min 2 The maximum postamble is bound by tHZDQS max Document 06944 Revision A 3 Oct 11 Dataram Corporation 2011 Page 7 I DPATARAM DTM64328D eebe 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Function Number of Bytes Used Number of Bytes in SPD Device CRC Coverage Bit 3 Bit 0 SPD Bytes Used 176 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 2 Key Byte DRAM Device Type DDR3 0x0B SDRAM Key Byte Module Type Bit 3 Bit 0 Module Type RDIMM Bit 7 Bit 4 Reserved 0 SDRAM Density and Banks Bit 3 Bit 0 Total SDRAM capacity in megabits 1Gb Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved Bit 2 Bit 0 Column Address Bits Bit 5 Bit 3 Row Address Bits Bit 7 6 Reserved Module Organization Bit 2 Bit 0 SDRAM Device Width Bit 5 Bit 3 Number of Ranks Bit 7 6 Reserved Module Memory Bus Width Bit 2
12. n 2Rx8 Registered ECC DDR3 DIMM 149 DRAM Manufacturer ID Code Most Significant Byte UNUSED 150 175 Manufacturer s Specific Data UNUSED 176 255 Open for customer use UNUSED Bytes 122 125 change per DIMM Document 06944 Revision A 3 Oct 11 Dataram Corporation 2011 Page 11 I DPATARAM DTM64328D Ba cool dati NSL p hi ay 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM E DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06944 Revision A 3 Oct 11 Dataram Corporation 2011 Page 12
13. t 5 Reference Raw Card Revision Bit 7 Reserved Address Mapping from Edge Connector to DRAM 0x05 Bit 0 Rank 1 Mapping Registered DIMM Reserved Bit 7 Bit 1 Reserved UNUSED UNUSED a UNUSED UNUSED UNUSED 0x0 O O oO 64 66 67 68 69 70 71 112 113 114 116 117 118 Module Specific Section Register Revision Number Module Specific Section Module Specific Section Module Specific Section Module Specific Section Module Specific Section Module Manufacturer ID Code Least Significant Byte Module Manufacturer ID Code Most Significant Byte Module Manufacturing Location Module Manufacturing Date Module Serial Number 119 120 121 122 125 126 Cyclical Redundancy Code CRC CRC C UNUSED 127 128 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 Cyclical Redundancy Code CRC Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Revision Code DRAM Manufacturer ID Code Least Significant Byte CR lt A T A A M 4 3 2 UNUSED Document 06944 Revision A 3 Oct 11 Dataram Corporation 2011 Page 10 Garson DTM64328D eebe 4GB 240 Pi
14. tered ECC DDR3 DIMM PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TsTORAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperature Operating Tease 0 95 C Voltage on Vpp relative to Vss Vop 0 4 1 975 V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Vop 1 425 1 5 1 575 V UO Reference Voltage VREFDQ 0 49 Mon 0 50 Mon 0 51 Von V 1 UO Reference Voltage VREFCA 0 49 Mon 0 50 Vpp 0 51 Voo V 1 Notes 1 The value of Vrer is expected to equal one half Vpp and to track variations in the Voo DC level Peak to peak noise on Vrer may not exceed 1 of its DC value For Reference Vpp 2 15 mV DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vue VREF 0 1 Vpop V Logical Low Logic 0 Vuupe Vss Veer 0 1 V AC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vuac VREF 0 175 vV Logical Low Logic 0 Vit ac Vrer 0 175 V Document 06944 Revision A 3 Oct 11 Dataram Corporation 201
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