Dataram 2GB DDR2 SDRAM
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1. Parameter Symbol MIN MAX Units Notes CMD2DATA 0x40 Data Rate 667 tC2D_AMB 16 2 19 ns CMD2DATA 0x46 Data Rate 667 tC2D_AMB 17 7 20 5 ns Resample Delay 6 tRESAMPLE 0 9 1 4 ns 1 Resync Delay 7 8 9 tRESYNC 2 3 2 ns 2 NOTES 1 tRESAMPLE is the delay from the southbound input to the southbound output or the northbound input to the northbound output when in resample mode measured from the center of the data eye 2 tRESYNC is the delay from the southbound input to the southbound output or the northbound input to the northbound output when in resync mode measured from the center of the data eye nnn nnn _ So Document 06530 Revision A 20 Apr 09 Dataram Corporation 2009 Page 9 DNE 2 GB 240 Pin DDR2 FB DIMM AMB Power Specification 0 to 70 C Voltage referenced to Vss OV Parameter Symbol Test Condition y Value Unit idle Single or last FBDIMM LO state idle 0 BW primary channel 1 5V 2600 Current IDD IDLE O secondary channel disabled CKE high command and mA address lines stable DDR2 SDRAM clock active 1 8V 700 Idle First FBDIMM LO state idle 0 BW primary and secondary 1 5V 3400 Current IDD IDLE 1 enabled high command and address lines mA stable DDR2 SDRAM clock active 1 8 V 700 TDP BW Single or Last DIMM LO State TDP Channel 45V 3000 Active IDD 0 BW 2 4GB s 6672. 1 27 1 10 0 0500 40 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches p M Document 06530 Revision 20 Apr 09 Dataram Corporation 2009 Page 2 D Optimizing Value and Performance Py DTM65525B 2 GB 240 Pin DDR2 FB DIMM 151 50 e DQS9 O e DQS13 paso 0054 10080 10084 o o o 229 o o o 29 o o N 29 o nO N SQ g 8 988 8 8 g 8 eag 8 8 988 2 DQR 7 0 O o 7 0 VO 7 0 DQ 39 32 O 10 7 0 VO 7 0 DQS10 O 00514 O 051 0055 10051 10055 o o o z9 Q Q o 22 o o o 290 o o N 290 g 2 245 8 8 8 8 985 8 8 2 4 DQ 15 8 0 1 7 0 VO 7 0 47 40 O
3. DTM65525B Zd Wi Optimizing Value and Performance Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 35 mm high Data Transfer Rate 6 4 Gigabytes sec Operating Voltage VDD 1 8 V 40 1 VCC 1 5V 0 1 SMBus interface to AMB for configuration register access MBIST and IBIST test functions Transparent mode for DDR2 SDRAM test support Full DIMM Heat Spreader High speed differential point to point link Fully ROHS Compliant Pin Configurations Front side Back side 2 GB 240 Pin DDR2 FB DIMM Identification DTM65525B 256Mx72 2GB 2Rx8 2 6400 555 11 0 Performance range Clock Module Speed CL trcp trp 400MHz DDR2 800 5 5 5 333MHz DDR2 667 4 4 4 avete neam A Description The DTM65525B is a Dual Rank PC2 6400 Fully Buffered 256MX72 ECC DIMM that conforms to the JEDEC FB DIMM standard Each rank is comprised of nine Hynix 128 8 DDR2 DRAMs One IDT Rev C1 Advanced Memory Buffer AMB is used as the interface between the system memory bus and DIMM DRAMs One 2K bit EEPROM is used for Serial Presence Detect For improved thermal performance a Full DIMM Heat Spreader with thermal interface material TIM is attached to the front and back of the DIMM 1 VDD 31 PN3 61 PN9 91 PS9 121 VDD 151 VDD 32 PN3 62 VSS 92 VSS 122 VDD 152 3 VDD 33 VSS 63 PN10 93 PS5 123 VDD 153 4 VSS 34 PN4 64
4. 1 0 7 0 VO 7 0 DQS11 O 00515 O DQS2 0056 10052 DQS6 o o o z9 o o o z9 o 229 o o o 229 8 8 485 8 8 988 88 8 8 74 gt 4 DQ 23 16 O 1 0 7 0 VO 7 0 55 48 1 0 7 0 VO 7 0 DQS12 e DQS16 O e DQS3 O DQS7 10053 10087 zy a zo zo 2 SQ 8 8 488 8 8 8 8 Sag 8 g a gt a a 2 DQ 31 24 O 4 VO 7 0 7 0 DQ 63 565 O 1 0 7 0 VO 7 0 DQS17 O e DQS8 O 10058 8 8 888 8 8 8 28 scL gt M h SDA a a x a SPD CB z 0 0 1 0 7 0 VO 7 0 WP p RR SA0 SA1 SA2 PNO PN13 DQ0 DQ63 PNO PN13 CBO CB7 All address command control clock NAN 50 59 DQS0 DQS17 50 59 DQS0 DQS8 SNO SN13 A 180 gt CS 00 08 SNO SN13 CKEO gt 00 08 580 859 151 gt ICS 09 017 VIT gt Terminators 1550 1559 B CKE1 gt CKE D9 D17 ODT gt ODT all SDRAMs VCC AMB X BAO BA2 all SDRAMs 1 SA1 SA2 1 0 15 all SDRAMs RAS all SDRAMs VDDSPD SPD AMB ICAS all SDRAMs RESET all SDRAMs SCK amp SCK CK amp CK all SDRAMs VDD DRAMS AMB VREF DRAMS There are two physical copies of each address command control clock VSS e e DRAMS SPD AMB Document 06530 Revision A 20 Apr 09 Dataram Corporation 2009 Page 3
5. 1 GHz to 2 4GHz RX termination resistance RRX 13 41 55 D D RX resistance difference RRX Match DC 4 RRX Match DC 24 RRX D RRX D RRX D RRX D Lane to lane PCB skew at RX LRX PCB SKEW 14 6 Ul Lane to Lane PCB skew at the Receiver that must be tolerated Minimum RX Drift Tolerance TRX DRIFT 15 400 ps Minimum data tracking 3dB bandwidth FTRK 16 0 2 a MHz Electrical idle entry detect time lt 60 ns Electrical idle exit detect time TEI EXIT DETECT 30 ns Bit Error Ratio BER 18 10 Document 06530 Revision A 20 Apr 09 Dataram Corporation 2009 Page 7 yee DTM65525B 2 GB 240 Pin DDR2 FB DIMM Mm Optimizing Value and Performance NOTES FOR RECEIVER INPUT SPECIFICATIONS 1 Specified at the package pins into a timing and voltage compliant test setup Note that signal levels at the pad are lower than at the pin 2 Single ended voltages below that value that are simultaneously detected on D and D are interpreted as the Electrical Idle condition Worst case margins are determined by comparing EI levels with common mode levels during normal operation for the case with transmitter using small voltage swing see RX Single ended Electrical Idle Levels and RX Common Mode Levels 3 Multiple lanes need to detect the El condition before the device can act upon the EI detection 4 Specified at the package pins into a timing and voltage compliance test setup 5 Thi
6. 20 SDRAM Minimum Row Active to Row Active Delay 21 SDRAM Minimum Row Precharge Time tRP SDRAM Upper Nibbles for tRAS and tRC Bit 3 Bit 0 tRAS Most Significant Nibble Bit 7 Bit 4 tRC Most Significant Nibble 23 SDRAM Minimum Active to Precharge Time tRAS 24 SDRAM Minimum Active to Active Refresh Time tRC 25 SDRAM Minimum Refresh Recovery Time Delay tRFC LSB 127 5ns 26 SDRAM Minimum Refresh Recovery Time Delay tRFC MSB 127 5ns 0 01 SDRAM Minimum Internal Write to Read Command Delay 7 5ns 0 1 tWTR 2 SDRAM Minimum Internal Read to Precharge Command Delay 7 5ns 0 1 tRTP Burst Lengths Supported AIN Bit 0 BL 4 Bit 1 BL 8 Bit 6 Bit 2 TBD Bit 7 Burst Chop SDRAM Terminations Supported Bit 0 150 ohms ODT Bit 1 75 ohms ODT Bit 2 50 ohms ODT Bit 6 Bit 3 TBD SDRAM Drivers Supported Bit 0 Weak Driver Bit 7 Bit 1 TBD SDRAM Average Refresh Interval tREFI Double Refresh mode bit High Temperature self refresh rate support indication Bit 0 Bit Average Refresh Interval tREFI uS 7 8 Bit 5 Bit 4 TBD 0 Bit 6 High Temperature Self Refresh 1 Required Bit 7 Double Refresh Requirement 1 Supported Tcasemax Delta Bit 3 Bit 0 DT4R4W Delta Subfield B 0 4 C Bit 7 Bit 4 Tcasemax Subfield A 2 C SDRAM Case Temperature Rise from Ambie
7. 200 mV 0 45 90mV and VRX CM ACp p 13 The termination small signal resistance tolerance across voltages from 100mV to 400mV shall not exceed 5 with regard to the average of the values measured at 100mV and at 400mvV for that pin 14 This number represents the lane to lane skew between TX and RX pins and does not include the transmitter output skew from the component driving the signal to the receiver This is one component of the end to end channel skew in the AMB specification 15 Measured from the reference clock edge to the center of the input eye This specification is met across specified voltage and temperature ranges Drift rate of change is significantly below the tracking capability of the receiver 16 This bandwidth number assumes the specified minimum data transition density Maximum jitter at 0 2MHz is 0 05UI 17 The specified time includes the time required to forward the El entry condition 18 BER per differential lane Document 06530 Revision A 20 Apr 09 Dataram Corporation 2009 Page 8 DE 2 GB 240 Pin DDR2 FB DIMM Advanced Memory Buffer FBD Timing Electrical Parameter Symbol MIN MAX Units El Assertion Pass Through Timing PROPAGATE 4 CLKs El Deassertion Pass Through Timing tEID tBitlock CLKs Assertion Duration 100 CLKs Bit Lock Interval tBITLOCK 119 Frames Frame Lock Interval tFRAMELOCK 154 Frames Advanced Memory Buffer Latency Parameters
8. 67 READ 3396 WRITE primary channel enabled secondary channel disabled high command 48V 1300 i address lines stable DDR2 SDRAM clock active TDP BW First DIMM LO State TDP Channel 45V 3900 Active IDD TDP 1 BW 2 4GB s 667 DIMM BW 1 6GB s 667 67 READ 33 Power WRITE primary channel enabled secondary channel enabled mA CKE high command and address lines stable DDR2 SDRAM 1 8 V 1000 clock active IDD TRAINING Primary and secondary channels enabled 100 toggle on all 1 5V 4000 Training E channel lanes DDR2 SDRAM devices idle 0 BW CKE HIGH mA command and address lines stable DDR2 SDRAM clock active 1 8 V 0 7 C __ 7L c il Document 06530 Revision A 20 Apr 09 Dataram Corporation 2009 Page 10 DP DATARAM Optimizing Value and Performance DTM65525B 2 GB 240 Pin DDR2 FB DIMM DRAM AC Characteristics AC operating conditions unless otherwise noted Parameter Symbol n i Unit Note Value Value Row Cycle Time 57 5 ns Auto Refresh Row Cycle Time 105 ns Row Active Time tras 45 70K ns Row Address to Column Address Delay trop 12 5 ns Row Active to row Active Delay 7 5 ns Column Address to Column Address Delay tccp 2 CLK Row Precharge time trp 12 5 ns Write Recovery Time twr 15 ns Auto Precharge Write Recovery Precharge Time
9. Banks Bit 5 Bit 3 Column Address Bits Bit 7 Bit 5 Row Address Bits Module Physical Attributes 0x23 Bit 3 Bit 0 Module Thickness mm 7 lt lt 8 0 Bit 4 Bit 2 Module Height mm 30 lt lt 35 Bit 7 6 Reserved 0 0x07 Bit 3 Bit 0 Module Type FB DIMM Bit 7 Bit 4 Reserved 0 Module Organization 0x11 Bit 3 Bit 0 SDRAM Device Width Bit 5 Bit 3 Number of Ranks Bit 7 6 Reserved Fine Timebase Dividend Divisor 0x00 Bit 3 Bit 0 Fine Timebase FTB Dividend 0 Bit 7 Bit 4 Fine Timebase FTB Divisor 0 ol 0 25ns 0 25ns 11 SDRAM Minimum Cycle Time tCKmin 12 SDRAM Maximum Cycle Time tCKmax SDRAM CAS Latencies Supported Bit 3 Bit 0 Minimum CL clocks Bit 7 Bit 4 CL Range clocks 14 SDRAM Minimum CAS Latency Time tAAmin SDRAM Write Recovery Times Supported 0x32 Bit 3 Bit 0 Minimum WR clocks Bit 7 Bit 4 WR Range clocks SDRAM Write Recovery Time tWR 17 SDRAM Write Latencies Supported 0x42 Document 06530 Revision A 20 Apr 09 Dataram Corporation 2009 Page 13 65525 MM 2 GB 240 Pin DDR2 FB DIMM Bit 3 Bit 0 Minimum WL clocks Bit 7 Bit 4 WL Range clocks SDRAM Additive Latencies Supported Bit 3 Bit 0 Minimum AL clocks Bit 7 Bit 4 AL Range clocks 5 19 SDRAM Minimum RAS to CAS Delay tRCD
10. DTM65525B 2 GB 240 Pin DDR2 FB DIMM Optimizing Value and Performance Absolute Maximum Ratings Parameter Symbol Rating Unit Note Temperature DDR2 DRAM Case 0 to 95 C 1 2 Temperature Storage Tsrc 55 to 100 1 Voltage pin relative to Vss Vin Vout 0 3 to 1 75 V 1 Voltage on Vcc relative to Vss Vcc 0 3 to 1 75 V 1 Voltage on Vpp relative to Vss 0 5 to 2 3 V 1 Voltage on Vrr relative to Vss Vit 0 5 to 2 3 V 1 Power Dissipation Pp 21 1 NOTES 1 Operation at or above absolute maximum rating can adversely affect device reliability 2 85 lt lt 95 C treri 3 9 us max DC Operating Conditions Ta 0 to 70 C Voltage referenced to Vss OV Parameter Symbol Minimum Typical Maximum Unit Note AMB Supply Voltage 1 425 1 5 1 59 V DDR2 Supply Voltage Vpp 1 7 1 8 1 9 V Termination Voltage Vit 0 48 x VDD 0 50 x VDD 0 52 x VDD V EEPROM Supply Voltage SPD VppsPD 3 0 3 3 3 6 V Input High Voltage SPD Vinc 2 1 VppsPD V 1 Input Low Voltage SPD 1 0 V 1 Input High Voltage RESET BFUNC 1 0 V 2 Input Low Voltage RESET BFUNC ViL C 0 5 V 1 Leakage Curent RESET BFUNC IL 90 90 pA 2 Leakage Curent Link I 5 5 Notes 1 Applies to SMB and SPD bus signals 2 Applies to AMB CMOS signal RESET Document 06530 Revision A 20 Apr 09 Dataram Corporatio
11. Rise from Ambient due to AMB 93 0 5 Idle 0 State DT AMB Idle 0 C AMB Case Temperature Rise from Ambient due to AMB in 113 0x71 Idle_1 State DT AMB ldle_1 C AMB Case Temperature Rise from Ambient due to AMB in 101 0x65 Idle 2 State DT AMB Idle 2 C 91 Case Temperature Rise from Ambient due to AMB in 155 Ox9B Active 1 State DT AMB Active 1 C AMB Case Temperature Rise from Ambient due to AMB in 127 Ox7F Active 2 State DT AMB Active 2 C 93 AMB Case Temperature Rise from Ambient due to AMB in LOs UNUSED 0x00 State DT AMB LOs C 98 AMB Junction Temperature Maximum C 18 04 99 Reeva 101 AMBPersonaityBytes Prein aizaion foo 102_ AMB Personality Bytes Pre initializaton 0 0 A i 0 0 109 Personality Bytes Post initialization MB Personality Bytes Post initialization EFi Personality Bytes Post initialization 114 i J p EN 7116 Manufacturers JEDECID Code J 7117 Module ID Module Manufacturers JEDEC TD Code 7118 Module ID Module Manufacturer s JEDECID Code 119 Module ID Module Manufacturing Location 120 127 Module ID Module Manufacturing Location 7 ID Module Serial Number 125 126 Redundancy Code CRC 127 Redundancy Code CRC ER ie Part Number 131 Docu
12. necessarily tested on each device and they may be Document 06530 Revision A 20 Apr 09 Dataram Corporation 2009 Page 11 DE 2 GB 240 Pin DDR2 FB DIMM AC Operating Conditions AC operating conditions unless otherwise noted Min Max Symbol Unit Note Value Value DQ Input Pulse Width toipw 0 35 CLK Read DQS Preamble Time 0 9 1 1 CLK Read DQS Postamble Time trest 0 4 0 6 CLK Write DQS Preamble Hold Time twPRE 0 35 CLK Write DQS Postamble Time twPsT 0 4 0 6 CLK Mode Register Set Delay tMRD 2 CLK Exit Self Refresh to Non Read Command txsnr tRFC 10 ns Exit Self Refresh to Read Command 200 7 8 1 Average Periodic Refresh Interval 3 9 Hs 2 NOTES 1 For0C lt Tease 5 85 2 For 85 lt Tcase 5 95 Document 06530 Revision A 20 Apr 09 Corporation 2009 Page 12 65525 Se 2 GB 240 Pin DDR2 FB DIMM SERIAL PRESENCE DETECT MATRIX Function Value Hex Number of Serial PD Bytes Written SPD Device Size CRC Coverage Bit 3 Bit 0 SPD Bytes Used 176 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 SPD Revision 0x11 Key Byte DRAM Device Type DDR2 FBDIMM Voltage Levels of this Assembly Bit 3 Bit 0 Power Supply 1 Bit 7 Bit 4 Power Supply 2 SDRAM Addressing Bit 1 0 Number of
13. PN10 94 PS5 124 VSS 154 5 VDD 35 PN4 65 VSS 95 VSS 125 VDD 155 6 VDD 36 VSS 66 11 96 56 126 VDD 156 7 VDD 37 5 67 11 97 PS6 127 VDD 157 8 VSS 38 5 68 VSS 98 VSS 128 55 158 9 VCC 39 VSS 69 VSS 99 PS7 129 VCC 159 10 VCC 40 13 70 50 100 57 130 160 11 55 41 PN13 71 PSO 101 55 131 55 161 12 42 VSS 72 55 102 58 132 162 13 43 VSS 73 PS1 103 58 133 163 14 55 44 RFU 74 51 104 55 134 55 164 15 VTT 45 RFU 75 VSS 105 RFU2 135 VTT 165 16 VID1 46 VSS 76 PS2 106 RFU2 136 VIDO 166 17 RESET 47 VSS 77 52 107 55 137 M TEST 167 18 VSS 48 12 78 VSS 108 VDD 138 VSS 168 19 RFU2 49 PN12 79 PS3 109 VDD 139 RFU2 169 20 RFU2 50 VSS 80 PS3 110 VSS 140 RFU2 170 21 VSS 51 PN6 81 VSS 111 VDD 141 VSS 171 22 PNO 52 PN6 82 54 112 VDD 142 5 0 172 23 PNO 53 VSS 83 54 113 VDD 143 SNO 173 24 55 54 PN7 84 VSS 114 55 144 55 174 25 1 55 PN7 85 55 115 VDD 145 SN1 175 26 PN1 56 VSS 86 RFU1 116 VDD 146 SN1 176 27 VSS 57 PN8 amp 87 RFU1 117 VTT 147 55 177 28 PN2 58 PN8 amp 88 VSS 118 SA2 148 SN2 178 29 PN2 59 VSS 89 VSS 119 SDA 149 SN2 179 30 VSS 60 9 90 59 120 SCL 150 VSS 180 NOTE M TEST is not used SN3 ISN3 VSS SN4 ISN4 VSS SN5 ISN5 VSS SN13 ISN13 VSS VSS RFU1 RFU1 VSS VSS SN12 15 12 VSS SN6 SN6 VSS SN7 ISN7 VSS SN8 SN8 VSS SN9 Pin Names Pin Names Function 181 SN9 211 SS9 SCK SCK Sy
14. common mode ouiput voltage for small VTX CM ACp p S 1 4 _ 70 swing VTX CM AC VTX D VTX D 2 Min D VTX D 2 Maximum single ended voltage in El condition DC AC VTX IDLE SE 5 6 2 50 mV Maximum single ended voltage in El condition DC only Mr 20 Maximum peak to peak differential voltage in El condition VTX IDLE DIFFp p 6 __ 40 Single ended voltage w r t VSS on D D VTX SE 1 7 75 750 Minimum TX eye width 3 2 and 4 Gb s TTX Eye MIN 1 9 10 0 7 en Ul Maximum TX deterministic jitter 3 2 and 4 Gb s TTX DJ DD 1 9 10 11 S 0 2 Ul Instantaneous pulse width TTX PULSE 12 0 85 Ul Differential TX output rise fall time TTX RISE TTX 30 90 ps Given by 2096 8096 voltage levels FALL 1 Mismatch between rise and fall times TTX RF MISMATCH 20 Differential return loss RLTX DIFF 8 Measured over 0 1 GHz to 2 4GHz Common mode return loss RLTX CM 6 dB Measured over 0 1 GHz to 2 4GHz Transmitter termination resistance RTX 13 41 55 Q D D TX resistance difference RTX Match DC 4 RTX Match DC 24 RTX D RTX D RTX D RTX D Bounds are applied separately to high and low output voltage states Lane to lane skew at TX LTX SKEW 1 14 16 100 3UI ps Lane to lane skew at TX LTX SKEW 2 15 16 100 2UI ps TTX DRIFT 240 s Maximum TX Drift resync mode RESYNC 17 p TTX DRIFT 120 s Maximum TX Drift resample mode only RESAMPLE 17 p Bit Error Rat
15. io BER 18 10 Document 06530 Revision A 20 Apr 09 Dataram Corporation 2009 Page 5 DTM65525B 2 GB 240 Pin DDR2 FB DIMM Mm Ld Optimizing Value and Performance NOTES FOR TRANSMITTER OUTPUT SPECIFICATIONS 1 Specified at the package pins into a timing and voltage compliance test load Common mode measurements to be performed using a 101010 pattern 2 This is the ratio of the VTX DIFFp p of the second and following bits after a transition divided by the VTx DIFFp p of the first bit after a transition 3 De emphasis is disabled in the calibration state 4 Includes all sources of AC common mode noise 5 Single ended voltages below that value that are simultaneously detected on D and D are interpreted as the Electrical Idle condition 6 Specified at the package pins into a voltage compliance test load Transmitters must meet both single ended and differential output E1 specifications 7 This specification considered with Vnx ipLE se pc implies a maximum 15mV single ended DC offset between Tx and Rx pins during the electrical idle condition This in turn allows a ground offset between adjacent FB DIMM agents of 26mV when worst case termination resistance matching is considered 8 The maximum value is specified to be at least VTX DIFFp p L 4 L VTX CM ACp p 2 9 This number does not include the effects of SSC or reference clock jitter 10 These timing specifications apply to re
16. it 4 Rank 1 Data DRAM ODT 150 Ohms Bit 7 Bit 6 Rank 1 Ecc DRAM ODT Disabled 76 77 7 79 UNUSED 81 82 83 84 85 Channel Protocols Supported Most Significant Byte UNUSED Back to back Turnaround Cycles 0x10 Bit 1 Bit 0 Rank Read to Read 0 add l clock Bit Bit 2 Write to Read 0 add l clock Bit 5 Bit 4 Read to Write 1 add l clock Bit 7 Bit 6 TBD 0 AMB Read Access Time for DDR2 800 AMB LINKPARNXT 1 0 11 Bit 3 Bit 0 Read Access Fine Granularity UI Bit 7 Bit 4 Read Access Coarse Granularity tCK lii Read Access Time for DDR2 667 AMB LINKPARNXT 1 0 10 Channel Protocols Supported Least Significant Byte Bit 0 DDR2 Base Non ECC Protocol 0 Not Supported Bit 1 DDR2 Base ECC Protocol 1 5 Bit 7 Bit 2 TBD 0 Bit 3 Bit 0 Read Access Fine Granularity UI Bit 7 Bit 4 Read Access Coarse Granularity tCK CE Read Access Time for DDR2 533 AMB LINKPARNXT 1 0 01 Bit 3 Bit 0 Read Access Fine Granularity UI Bit 7 Bit 4 Read Access Coarse Granularity tCK p il Document 06530 Revision A 20 Apr 09 Dataram Corporation 2009 Page 15 DTM65525B MM 2 GB 240 Pin DDR2 FB DIMM 87 Thermal Resistance of AMB Package from Top Case to 21 2 Ambient Psi T A AMB C W 88 Case Temperature
17. ment 06530 Revision A 20 Apr 09 Dataram Corporation 2009 108 AMB Personality Bytes Post initialization 0x2 0x20 0x80 x9C 0x00 0x80 xFC 0x70 0x60 x7F xB3 0x01 0x91 0x01 0x00 0x00 0x7 Page 16 DTM65525B Se 2 GB 240 Pin DDR2 FB DIMM 182 186 ModdePatNumer o R 189 ModdePatNumer O 141 ModdePatNumer 8 42 MeddePatNumer O 8 48 MeddePatNumer 1 2 7144 ModdePatNumer oO 5 45 ModdePatNumer O mq Beine Specific Data UNUSED 175 176 Open for customer use UNUSED 0x00 255 5 5 2 5 p M __ Document 06530 Revision A 20 Apr 09 Dataram Corporation 2009 Page 17 I715 177771 DTM65525B MEM gt GB 240 pin DDR2 FB DIMM Mm d Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or
18. n 2009 Page 4 DTM65525B n Optimizing Value and Performance Differential Transmitter Output Specification 2 GB 240 Pin DDR2 FB DIMM Parameter Symbol MIN MAX Units Differential peak to peak output voltage for large voltage VTX DIFFp p L 1 900 1300 mV swing VTX DIFFp p 22 VTX D VTX D Differential peak to peak output voltage for regular voltage VTX DIFFp p_R 1 800 mV swing VTX DIFFp p 2 VTX D VTX D Differential peak to peak output voltage for small voltage VTX DIFFp p_S 1 520 mV swing VTX DIFFp p 2 VTX D VTX D DC common code output voltage for large voltage swing VTX CM_L 1 Ze 375 mV Defined as VTX CM DC avg of VTX D VTX D 2 DC common mode output voltage for small voltage swing VTX CM S 1 135 280 mV Defined as VTX CM DC avg of VTX D VTX D 2 De emphasized differential output voltage ratio for 3 5 dB VTX DE 3 5 3 4 dB de emphasis Ratio 1 2 3 De emphasized differential output voltage ratio for 6 dB de VTX DE 6 Ratio 1 2 3 7 emphasis AC peak to peak common mode output voltage for large VTX CM ACp p L 1 4 22 90 mV swing VTX CM AC Max VTX D VTX D 2 Min VTX D VTX D 2 AC peak to peak common mode ouiput voltage for regular VTX CM ACp p R 1 4 __ 80 mV swing VTX CM AC Max VTX D VTX D 2 Min VTX D VTX D 2 AC peak to peak
19. nits Differential peak to peak input voltage VRX DIFFp p_L 1 170 1300 VRX DIFFp p 2 VRX D VRX D Maximum single ended voltage for El condition DC AC VRX IDLE SE 2 3 4 65 mV Maximum single ended voltage for El condition DC only 4 35 mV Single ended voltage w r t VSS on D D VRX SE 4 300 900 mV Single pulse peak differential input voltage VRX DIFF PULSE 4 6 85 Amplitude ratio between adjacent symbols VRX DIFF ADJ e 3 1100mV VRX DIFFp p lt 1300mV RATIO HI 4 7 Amplitude ratio between adjacent symbols VRX DIFF ADJ 4 VRX DIFFp p lt 1100 RATIO 4 7 Maximum inherent timing error 3 2 and 4 Gb s TRX TJ MAX 4 8 9 0 4 UI Maximum RX inherent deterministic timing error 3 2 and 4 TRX DJ DD 4 8 9 10 m 0 3 Ul Gb s Single pulse width at zero voltage crossing TRX PW ZC 4 6 0 55 UI Single pulse width at minimum level crossing TRX PW ML 4 6 0 2 a Ul rur RX input rise fall time given by 20 80 voltage TRX RISE TRX FALL 50 _ ps evels Common mode of the input voltage VRX CM 1 11 120 400 mV Defined as VRX CM DC avg of VRX D VRX D 2 AC peak to peak common mode of input voltage VRX CM VRX CM ACp p 1 DP 270 mV AC Max VRX D VRX D 2 Min VRX D VRX D 2 Ratio of VRX CM ACp p to minimum VRX DIFFp p VRX CM EH Ratio 12 45 Differential return loss RLRX DIFF 9 dB Measured over 0 1 GHz to 2 4GHz Common mode return loss RLRX CM 6 dB Measured over 0
20. nt due to Activate Precharge minus 2 8 C offset temperature DTO C Bit 1 Bit 0 Reserved Bit 7 Bit 2 DTO SDRAM Case Temperature Rise from Ambient due to 5 Precharge Quiet Document 06530 Revision A 20 Apr 09 Dataram Corporation 2009 Page 14 7 8 30 31 32 33 34 35 36 DTM65525B MM 2 240 DDR2 FB DIMM EN ee Case Temperature Rise from Ambient due to Precharge 1 095 Power Down DT2P C 38 SDRAM Case Temperature Rise from Ambient due to Active 0x28 Standby DT3N C 39 SDRAM Case Temperature Rise from Ambient due to Page Open Burst Read DT4R4W Mode Bit DT4R DT4R4W Mode Bit Bit 0 DT4R4W Mode Bit Subfield B 0 4 C 0 Bit 7 Bit 1 DT4R Subfield A 0 4 C 18 8 Bd Case Temperature Rise from Ambient due to Burst 19 5 Refresh DT5B C ER Case Temperature Rise from Ambient due to Bank 20 5 0x29 Interleave Reads with Auto Precharge DT7 C UNUSED 77 R Coria po QR ODT control for Rank 0 and rank 1 Reads and writes QR ODT1 ODT2 control for reads 8 ODT Definition for Rank 2 and 3 Bit 1 Bit 0o Rank 2 Data DRAM ODT Disabled Bit 3 Bit 2 Rank 2 Ecc DRAM ODT Disabled Bit 5 Bit 4 Rank 3 Data DRAM ODT Disabled Bit 7 Bit 6 Rank 3 Ecc DRAM ODT Disabled FBD ODT Definition for Rank 0 and 1 Bit 1 Bit 0 Rank 0 Data DRAM ODT 150 Ohms Bit 3 Bit 2 Rank 0 Ecc DRAM ODT Disabled Bit 5 B
21. reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06530 Revision A 20 Apr 09 Dataram Corporation 2009 Page 18
22. s specification considered with VTx IDLE SE Dc implies a maximum 15mV single ended DC offset between TX and RX pins during the electrical idle condition This in turn allows a ground offset between adjacent FB DIMM of 26mV when worstcase termination resistance matching is considered 6 The single pulse mask provides sufficient symbol energy for reliable RX reception Each symbol complies with both the single pulse mask and the cumulative eye mask see RX Single Pulse Min Width and Amplitude Mask Pulse Shifted Early and RX Single Pulse Min Width and Amplitude Mask Pulse Shifted Late 7 The relative amplitude ratio limit between adjacent symbols prevents excessive inter symbol interference in the Rx Each symbol must comply with the peak amplitude ratio with regard to both the preceding and subsequent symbols see RX Maximum Adjacent Symbol Amplitude 8 This number does not include the effects of SSC or reference clock jitter 9 This number includes setup and hold of the RX sampling flop 10 Defined as the dual dirac deterministic timing error as described in Section 4 2 2 of the JEDEC FB DIMM High Speed Differential PTP Link Draft Spec rev 0 8 11 Allows for 15mV DC offset between transmit and receive devices 12 The received differential signal satisfies both this ratio as well as the absolute maximum AC peak to peak common mode specification For example if VRX DIFFp p is 200mV the maximum AC peak to peak common mode is the lesser of
23. stem Clock Input 182 VSS 212 VSS PN PN 13 0 Primary Northbound Data 183 SN10 213 SS5 PS PS 9 0 Primary Southbound Data 184 SN10 214 SS5 SN SN 13 0 Secondary Northbound Data 185 VSS 215 VSS SS SS 9 0 Secondary Southbound Data 186 SN11 216 556 SCL Serial Clock EEPROM 187 SN11 217 SS6 SDA Serial Data EEPROM 188 VSS 218 VSS RESET AMB Reset Signal 189 VSS 219 SS7 VCC AMB Core Power and AMB Channel 190 SSO 220 SS7 nterface Power 1 5 V 191 SSO 221 VSS VDD DRAM Power and AMB DRAM I O 192 VSS 222 SS8 Power 1 8 V 193 SS1 223 SS8 VTT DRAM Address Command Clock 194 SS1 224 VSS Termination Power VDD 2 195 VSS 225 RFU2 VDDSPD SPD Power 196 SS2 226 RFU2 VSS Ground 197 SS2 227 VSS RFU Reserved For Future Use 198 VSS 228 SCK DNU Do Not Use 199 SS3 229 5 M_TEST Margin Test 200 SS3 230 VSS SA 2 0 Serial Address EEPROM 201 VSS 231 VDD 202 SS4 232 VDD 203 SS4 233 VDD 204 VSS 234 VSS 205 VSS 235 VDD 206 RFU1 236 VDD 207 RFU1 237 208 55 238 VDDSPD 209 VSS 239 5 0 210 559 240 SA1 Document 06530 Revision 20 Apr 09 Dataram Corporation 2009 Page 1 ME 2 GB 240 Pin DDR2 FB DIMM Front view 133 35 zi 5 250 3 00 0 118 30 35 1 191 4 em 55 518 67 00 51 00 0 0 204 2 638 2 008 123 00 4 843 Back view Side view 7 49 Max 0 295 Max w heatspreader 4 00 0 157 Min
24. sync mode only 11 Defined as the dual dirac deterministic jitter as described in Section 4 of the JEDEC FB DIMM High Speed Differential PTP Link Draft Spec rev 0 8 12 Pulse width measured at OV differential 13 The termination small signal resistance tolerance across voltages from 100mV to 400mV shall not exceed 5 with regard to the average of the values measured at 100mV and at 400mv for that pin 14 Lane to Lane skew at the Transmitter pins for an end component 15 Lane to Lane skew at the Transmitter pins for an intermediate component assuming zero Lane to Lane skew at the Receiver pins of the incoming PORT 16 This is a static skew A FB DIMM component is not allowed to change its lane to lane phase relationship after initialization 17 Measured from the reference clock edge to the center of the output eye This specification is met across specified voltage and temperature ranges for a single component Drift rate of change is significantly below the tracking capability of the receiver 18 BER per differential lane For a complete definition of Bit Error Ratio refer to JEDEC s Compliance Methodology section Document 06530 Revision A 20 Apr 09 Dataram Corporation 2009 Page 6 DTM65525B DP DATARAM d Optimizing Value and Performance Differential Receiver Input Specification 2 GB 240 Pin DDR2 FB DIMM Parameter Symbol MIN U
25. toa twn Pes trp 7 us System Clock Cycle Time tck 2500 8000 ps Clock High Level Width tcu 0 48 0 52 CLK Clock Low Level Width 0 48 0 52 CLK DQ output access time from CK amp CK tac 0 400 0 400 ns DQS Out edge to Clock Edge skew tpasck 0 350 0 350 ns DQS Out edge to Data out edge skew toasa 0 200 ns Data Out hold time from DQS tau tup taus ns 1 Data hold skew factor tous 0 300 ns 1 Clock Half Period tup min tcu ns 1 Input Setup Time fast slew rate tis 0 175 ns 2 3 5 6 Input Hold Time fast slew rate 0 250 ns 2 3 5 6 Input Pulse Width tiew 0 6 CLK 6 Write DQS High Level Width 0 35 CLK Write DQS Low Level Width 0 35 CLK CLK to First Rising edge to DQS In tposs 0 25 0 25 CLK Data In Setup Time to DQS In DQ amp DM tps 0 050 ns Data In Hold Time to DQS In DQ amp DM 0 125 ns NOTES 1 This calculation accounts for tposo max the pulse width distortion of on chip and jitter 2 3 For command address input slew rate gt 1 0V ns 4 For command address input slew rate gt 0 5V ns and 1 0V ns 5 CK CK slew rates gt 1 0V ns 6 guaranteed by design or tester correlation T Data latched at both rising and falling edges of Data Strobes DQS Data sampled at the rising edges of the clock A0 A13 BAO BA2 S 1 0 RAS 5 These Parameters guarantee device timing but they are not
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