Dataram 2GB DDR3 SDRAM
Contents
1. Front view 133 35 5 250 A 9 50 0 374 30 00 1 181 17 30 0 681 Y Y 5 00 A 0 197 da 5478 Ja ah 47 00 71 00 gt 0 204 1 850 2 795 123 00 ie 4 843 Back view Side view 4 00Max 0 157 Max 4 00 Min 0 157 Min 1 27 10 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches no Page 2 Document 06566 Revision A 24 Sep 09 Dataram Corporation 2009 ra DTM64315B A 2GB 240 Pin 1Rx4 Registered ECC DDR3 DIMM IRSO O DQSO O ee O DQSO O DQS9 O Vss O E op IDQS DQS CS DM DQS DQS CS DM DQR 3 0 O 1 0 3 0 DQR 7 4 O 1 0 3 0 DQS1 O DQS10 O g DQS DAS DQS pas DQR 11 8 O 1 0 3 0 DQR 15 12 O 1 0 3 0 DQS2 O IDQS11 O a DQS2 O DQS11 O DQS DAS DQS DAS DQR 19 16 O 1 0 3 0 DQR 23 20 O 1 0 3 0 DQS3 O DQS12 O DQS3 O DQS12 O DQS DQS DQS DAS DQR 27 24 O 1 0 3 0 DQR 31 28 O 1 0 3 0 IDQS8 O DQS17 O DQS8 O DQS17 O a DQS DAS DQS DAS CBR 3 0 O 1 0 3 0 CBRI 7 4 O 1 0 3 0 IDQS4 O g Das13 O Ml DQS4 O DQS13 O E DQS DQS DQS DAS DQR 35 32 O 1 0 3 0 DQR 39 36 O 1 0 3 0 IDQS5 O a DQS14 O a DQS5 O DQS14 O DQS DAS DQS DAS DQR 43 40 O 1 0 3 0 DQR 47 44 O 1 0 3 0 DQS6 O DQS15 O DQS6 O DQS15 O a DQS DAS DQS DAS DQR 51 48 O 1 0 3 0 DQR 55 52 O 1 0 3 0 DQS7 O DQS16 O2. 36 0ns Byte Minimum Active to Active Refresh Delay Time tRCmin Least Significant 49 5ns Byte Minimum Refresh Recovery Delay Time tRFCmin Least Significant 24 Byte 110 0ns N N OO NO 28 Bit 3 Bit 0 tFAW Most Significant Nibble 0 Bit 7 Bit 4 Reserved 0 29 il Four Activate Window Delay Time tFAWmin Least Significant yte SDRAM Optional Features Bit 0 RZQ 6 X 30 Bit 1 RZQ 7 X Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support Document 06566 Revision A 24 Sep 09 Dataram Corporation 2009 Page 9 Ox6C 0x78 Ox6C 0x30 Ox6C 0x11 0x20 0x8C 0x03 0x3C 0x3 O OxFO ra DTM64315B 31 os 68 69 2GB 240 Pin 1Rx4 Registered ECC DDR3 DIMM SDRAM Drivers Supported Module Thermal Sensor Bit 6 Bit 0 Thermal Sensor Accuracy 0 Bit 7 Thermal Sensor With TS SDRAM Device Type Bit 6 Bit 0 Non Standard Device Description 0 Bit 7 SDRAM Device Type Std Mono Bit 4 Bit 0 Module Nominal Height max in mm 29 lt h lt 30 Bit 7 Bit5 Reserved 0 Module Maximum Thickness Bit 3 Bit 0 Front in mm baseline thickness 1 mm Bit 7 Bit 4 Back in mm baseline thickness 1 mm Reference Raw Card Used Bit 4 Bit 0 Reference Raw Card R C C Bit 6 Bit 5 Reference Raw Card Revision Rev 1 Bit 7 Reserved 0 Registered DIMM Module Attributes Bit 1 Bit 0 of Re
3. Optimizing Value and Performance Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high Operating Voltage 1 5V 0 075 I O Type SSTL_15 On board 12C temperature sensor with integrated serial presence detect SPD EEPROM Data Transfer Rate 10 6 Gigabytes sec Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 6 7 8 and 9 Bi Directional Differential Data Strobe signals SDRAM Addressing Row Col Bank 14 11 3 Fully ROHS Compliant Pin Configuration Front Side Back Side 1 Vrerpa 31 DQ25 61 A2 91 DQ41 121 Vos 1151 Vss 181 A1 De 1862 Ves 62 Vo 92 Vss 122DQ4 152DQS12 182 Vo 3 DQO 33 DQS3 63 CK1 93 DQS5l123DQ5 153 DQS12 183 Vo 4 DQ1 34DQS3 64 CK1 94 DQS5 124Vss 154 Vss 184 CKO 5 Ves 35Vss 65 Vop 95 Vss 125DQS9 155 DQ30 185 CKO 6 DQSO 36 DQ26 66 Vop 96 DQ42 126 DQS9 156 DQ31 186 Vop 7 DQSO 37 DQ27 67 RERA 97 DQ43 127Vss 1157 Vss 187 Event 8 Ves 38Vss 68 Par In 98 Vss 128DQ6 158 CB4 188 AO 9 DQ2 39CBO 69 VDD 99 DQ48 li29DQ7 159 CB5 189 Von 10DQ3 40 CB1 70 A10 AP 100 DQ49 130 Vss 1160 Vss 190 BA1 ties ies 71 BAO 101 Vss 131DQ12 161 DQS17 191 Vo 12DQ8 42 DQS8 TaN 102 DQS6f132 DQ13 162 DQS17 192 RAS 13DQ9 43 DQS8 73 WE 103 DQS6 133 Vss 1163 Vss 193 SO 14 Ves 44 Vs 74 CAS 104 Vss 1134 DQS10 164 CB6 194 Voo 15 DQS1 45 CB2 75 Von 105 DQ
4. DQS7 O DQS16 O DQS DAS DQS DAS DQR 59 56 O 1 0 3 0 DQR 63 60 O 1 0 3 0 All 15 OHMS TO SDRAMS VDD VDD DQ 63 01 O VW O _ DQR 63 0 i All 39 OHMS 100 nF All 39 OHMS 100 nF CB 7 0 O WW O CBRI 7 0 22 OHMS 180 M IRSO LCLK 1 0 RCLK1 0 DQS 17 0 O WMN O DAQSR 17 0 S1 BA 2 0 BA 2 0 R LCLK 1 0 IRCLK 1 0 DQS 17 0 O WN O DQSR 17 0 AL15 0 ALI5 01R RAS RASR CAS CASR GLOBAL SDRAM CONNECTS ME Pre Ve DECOUPLING ES All 39 OHMS ee a CKEOR VDD All Devices BA 2 0 R V 2 0 ODTO O ODTOR REF_DQ Al FORAM A 15 0 R M Vss All Devices RASR PAR_IN ar ERR OUT VREF CA All SDRAMs ICASR CKO L R CLK 1 0 Vr m NI SDRAM IWER VTT 120 OHMS ICKO IL R CLK 1 0 EVENT ONE eses All 240 OHMS Q TEMPERATURE MONITOR SDA CKEOR SDRAMS YN SCL SERIAL PD ODTOR V CSOR VTT ss Document 06566 Revision A 24 Sep 09 Dataram Corporation 2009 Page 3 DRDATARAM DTM64315B ME 2GB 240 Pin 1Rx4 Registered ECC DDR3 DIMM Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability Ambient Temperature Operating DNS OU ARE OS ME 20e C DRAM Case Temperature Operating Tas 0 95 C Voltage on Vpp relative to Vss V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditio
5. Operating Bank interleave Read eg All bank interleaved read current 3600 mA Current Document 06566 Revision A 24 Sep 09 Dataram Corporation 2009 Page 6 A 2GB 240 Pin 1Rx4 Registered ECC DDR3 DIMM AC Operating Conditions Internal read command to first data ns CAS to CAS Command Delay RSR RE A E Clock High Level Width ie Lx Clock Low Level Width tox Data Input Hold Time after DQS Strobe II ps DQS Output Access Time from Clock 255 ps Write DQS High Level Width tox avg Write DQS Low Level Width tok ava 125 DQS Out Edge to Data Out Edge Skew Data Input Setup Time Before DQS Strobe DQS Falling Edge from Clock Hold Time toe f oa o DQS Falling Edge to Clock Setup Time toss 02 fo Address and Command Hold Time after Clock IA Address and Command Setup Time before Clock tis a 65 ps Load Mode Command Cycle Time we A DQ t0 DOS Hold tam oa Active to Precharge Time ns Active to Active Auto Refresh Time tee Las Average Periodic Refresh Interval 0 C lt Tcase lt 85 C Average Periodic Refresh Interval 0 C lt Tease 95 C ten 39 ps Auto Refresh Row Cycle Time NS ns Row Precharge Time trp ee Read DOS Preamble Time NES 09 Not tck avg Read DQS Postamble Time tok avg Row Active to Row Active Delay ter Max 4nCK 6ns ns Internal Read to Precharge Command Delay tare Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twere 09 e Write DOS P
6. 50 135 DQS10 165 CB7 195 ODTO 16 DQS1 46CB3 76 S1 106 DQ51 136 Vss 1166 Vss 196 A13 irVes 47 Vex 77 ODT1 107 Vss 1137 DQ14 167 NC TEST 197 Vo 18 DQ10 48 Vr 78 Vpp 108 DQ56 138DQ15 168 RESET 198 S3 NC 19DQ11 149 Vr 79 82 NC 109 DQ57 139 Vss 169 CKE1 199 Vss 20 Vss 50CKEO 80 Vss 110Vss 140DQ20 170 Vop 200 DQ36 21DQ16 51 Vop 81 DQ32 111 DQS7 141DQ21 171 A15 201 DQ37 22 DQ17 52BA2 82 DQ33 112 DQS7 f142 Vss 172 A14 202 Vss 23Vss 53 Err_Our 83 Vss 113Vss 143 DQS11 173 Vo 203 DQS13 24 DQS2 54 Vop 84 DQS4 114 DQ58 144 DQS11 174 A12 BC 204 DQS13 25 DQS2 55 A11 85 DQS4 115 DQ59 145 Vss 1175 A9 205 Vss 26Vss 56A7 86 Vss 116Vss i46DQ22 176 Vi 206 DQ38 27DQ18 57 Vo 87 DQ34 117 SAO 147 DQ23 177 A8 207 DQ39 28 DQ19 58 A5 88 DQ35 118 SCL hi48Vss 178 AG 208 Vss 29Vss 59A4 89 Vss 119SA2 149DQ28 179 Voo 209 DQ44 30 DQ24 60 Vo 90 DQ40 120 Vrr 150DQ29 180 A3 210 DQ45 dl Not used 2GB 240 Pin 1Rx4 Registered ECC DDR3 DIMM Identification DTM64315B 256Mx72 2GB 1Rx4 PC3 10600R 9 10 C1 Performance range Clock Module Speed CL trep trp 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Description DTM64315B is a registered 256Mx72 memory module which conforms to JEDEC s DDR3 PC3 10600 standard The assembly is a Single Rank comprised of eighteen 256Mx4 DDR3 Hynix SDRAMs One 2K bit EEPROM is used for Serial Presence Detect and a
7. Ox00 0 Ox00 x lt O gt lt O O1 O O O1 0x01 0x91 0x0 O gt lt NO 0x20 0x4 0x41 O OO X xX X X gt lt A oO NI OQ N gt gt olj 0 ojo X X Rio N 0x3 JEJE OI IR Rh O J O U MS 2GB 240 Pin 1Rx4 Registered ECC DDR3 DIMM Module Part Number 0x33 142 3 145 Module Part Number O 146 147 Module Revision Code e Document 06566 Revision A 24 Sep 09 Dataram Corporation O 2009 Page 12 aa D1M64315B MA D Optimizing Value and Performance 2GB 240 Pin 1Rx4 Registered ECC DDR3 DIMM IVIDATARAM PR D ptimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06566 Revision A 24 Sep 09 Dataram Corporation O 2009 Page 13
8. combination register PLL with Address and Command Parity is also used Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals in a Fly by topology A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating temperature of 95C Pin Description Function 211 Vss CB 7 0 Data Check Bits 212 DQS14 DA 63 0 Data Bits 213 DQS12 DQS 17 0 DQS 17 0 f Differential Data Strobes 214 Vss CK 1 0 CK 1 0 Differential Clock Inputs 215 DQ46 CKE 1 0 Clock Enables 216 DQ47 ICAS Column Address Strobe 217 Vss RAS Row Address Strobe 218 DQ52 S 3 0 Chip Selects 219 DQ53 WE Write Enable 220 Vss A 15 0 Address Inputs 221 DQS15 BA 2 0 Bank Addresses 222 DQS15 ODT 1 0 On Die Termination Inputs 223 Vss SA 2 0 SPD Address 224 DQ54 SCL SPD Clock Input 225 DQ55 SDA SPD Data Input Output 226 Vss Vss Ground 227 DQ60 Vop Power 228 DQ61 Vppspp SPD EEPROM Power 229 Vss VREFDQ Reference Voltage for DQ 230 DQS16 Vrerca Reference Voltage for CA 231 DQS16 Vr Termination Voltage 232 Vss Event Temperature Sensing 233 DQ62 NC No Connection 234 DQ63 235 Vss 236 Vopspo 237 SA1 238 SDA 239 Vss 240 Vi Document 06566 Revision A 24 Sep 09 Dataram Corporation O 2009 Page 1 MPDATARAM DTM64315B Md Optimizing Value and Performance 2GB A 240 Pin 1Rx4 Registered ECC DDR3 DIMM
9. gisters used on RDIMM 1 Register Bit 3 Bit 2 of Rows of DRAMs on RDIMM 1 Row Bit 7 Bit 4 Reserved 0 Bit 6 Bit O Heat Spreader Thermal Characteristics 0 Bit 7 Heat Spreader Solution No HS Register Manufacturer ID Code Least Significant Byte Optional UNUSED Register Manufacturer ID Code Most Significant Byte Optional UNUSED Register Revision Number Optional Register Type Bit 2 0 Support Device SSTE32882 Bit 7 3 Reserved 0 SSTE32882 RC1 MS Nibble RCO LS Nibble Reserved SPD must UNUSED be programmed as 0x00 Document 0 6566 Revision A 24 Sep 09 Dataram Corporation O 2009 Page 10 O O x lt x lt 00 00 O O gt lt O 0x00 OxOF 0x11 0x00 0x00 O O O O gt lt gt lt gt lt gt lt TI O O N TI al N Ox00 Ox00 DRDATARAM DTM6431 D B 7 T T T 7 T 77 112 113 114 117 118 119 120 121 122 125 O Optimizing Value and Performance 2GB 240 Pin 1Rx4 Registered ECC DDR3 DIMM SSTE32882 RC3 MS Nibble RC2 LS Nibble Drive Strength Command Address 0 Bit 1 Bit 0 RC2 DA3 4 Value RESERVED Bit 3 Bit 2 RC2 DBAO 1 Value RESERVED Bit 5 Bit 4 RC3 DA4 3 value Command Address A Outputs Moderate Bit 7 Bit 6 RC3 DBAO 1 value Command Address B Outputs Moderate SSTE32882 RC5 MS Nibble RC4 LS Nibble Drive Strength Control and Cl
10. idend Divisor Bit 3 Bit O Fine Timebase FTB Divisor 2 Bit 7 Bit 4 Fine Timebase FTB Dividend 1 MTB Medium Timebase MTB Dividend 0 125ns 5 11 8 MTB Medium Timebase MTB Divisor 0 125ns SDRAM Minimum Cycle Time tCKmin 13 Reserved UNUSED 14 CAS Latencies Supported Least Significant Byte BitO CL 4 Bit 1 CL 5 Document 06566 Revision A 24 Sep 09 Dataram Corporation 2009 Page 8 Hex 0x92 0x10 Ox0B 0x00 0x08 0x0 0x00 O O x CO O IDDRDATARAM DTM64315B ME 2GB 240 Pin 1Rx4 Registered ECC DDR3 DIMM Bit 2 CL 6 X Bit 3 CL 7 X Bit 4 CL 8 X Bit 5 CL 9 X Bit 6 CL 10 Bit 7 CL 11 CAS Latencies Supported Most Significant Byte Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 Bit 3 CL 15 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved 6 Minimum CAS Latency Time tAAmin 13 5ns 15 0ns 8 Minimum RAS to CAS Delay Time tRCDmin 13 5ns la ll N O1 Minimum Write Recovery Time tWRmin 9 Minimum Row Active to Row Active Delay Time tRRDmin 6 0ns 20 Minimum Row Precharge Delay Time tRPmin 13 5ns Upper Nibbles for tRAS and tRC Bit 3 Bit 0 tRAS Most Significant Nibble Bit 7 Bit 4 tRC Most Significant Nibble Minimum Active to Precharge Delay Time tRASmin Least Significant NO O O O O x lt gt lt gt lt gt lt 00 O N O O O O O
11. ns T 0 to 70 C Voltage referenced to Vss O V PARAMETER Symbol Minimum Typical Maximum Un Note I O Reference Voltage 0 49 Voo 0 50 Voo 0 51 Von 1 I O Reference Voltage VREFCA 0 49 Vop 0 50 Vip 0 51 Vip 1 Notes 1 The value of Vrer is expected to equal one half Vpp and to track variations in the Vpp DC level Peak to peak noise on Vrer may not exceed 1 of its DC value For Reference Vpp 2 15 mV DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Emol Minimum Mtra Unit Logical Low Logic 0 7 DC 0 1 V AC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss O V PARAMETER Srmbol_ Minimum Maximum Unit Logical Low Logic 0 7 AC Veer 0 175 V Document 06566 Revision A 24 Sep 09 Dataram Corporation 2009 Page 4 ra DTM64315B ES 2GB 240 Pin 1Rx4 Registered ECC DDR3 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage relative to VDD 2 Vix 0 150 0 150 V Capacitance T1 25 C f 100 MHz Input Capacitance Clock KO CKO CKO Input Capacitance Control S 1 0 CKE 1 0 ODT 1 0 oo pao Input Output Capacitance a 0 CB 7 0 DQS 17 0 DQS 17 0 AS ZQ Ca
12. ock 4 Bit 1 Bit 0 RC4 DA3 4 Control Signals A Outputs Moderate Bit 3 Bit 2 RC4 DBAO 1 Control Signals B Outputs Moderate Bit 5 Bit 4 RC5 DA4 3 value Y1 Y1 and Y3 Y3 Clock Outputs Moderate Bit 7 Bit 6 RC5 DBAO 1 value YO YO and Y2 Y2 Clock Outputs Moderate 2 SSTE32882 RC7 MS Nibble RC6 LS Nibble 3 re SSTE32882 RC9 MS Nibble RC8 LS Nibble 4 SSTE32882 RC11 MS Nibble RC10 LS Nibble 5 SSTE32882 RC13 MS Nibble RC12 LS Nibble 6 SSTE32882 RC15 MS Nibble RC14 LS Nibble m Module Specific Section Module Specific Section Module Specific Section Module Manufacturer ID Code Least Significant Byte Module Manufacturer ID Code Most Significant Byte Module Manufacturing Location Module Manufacturing Date Module Serial Number 126 Cyclical Redundancy Code CRC 127 128 132 133 134 135 136 137 138 139 OO Cyclical Redundancy Code CRC Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number 140 Module Part Number 141 Module Part Number UNUSED UNUSED UNUSED UNUSED CR C CRC 7 A A M OU O O 3 O 5 o D al O O JJ O o O 5 gt N Aa O O y o U D F D y 3 O O y O y O 5 O N Page 11 0x50 Ox00 Ox00 Ox00 Ox00 Ox00
13. ostamble Time EA O Write Recovery Time te 1 ns Internal Write to Read Command Delay twtr Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min 2 The maximum postamble is bound by tHZDQS max Document 06566 Revision A 24 Sep 09 Dataram Corporation 2009 Page 7 A 2GB 240 Pin 1Rx4 Registered ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Number of Bytes Used Number of Bytes in SPD Device CRC Coverage 0 Bit 3 Bit O SPD Bytes Used 176 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 __ SPD Revision Key Byte DRAM Device Type DDR3 SDRAM Key Byte Module Type Bit 3 Bit 0 Module Type RDIMM Bit 7 Bit 4 Reserved 0 SDRAM Density and Banks Bit 3 Bit 0 Total SDRAM capacity in megabits 1Gb Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved SDRAM Addressing Bit 2 Bit 0 Column Address Bits 11 Bit 5 Bit 3 Row Address Bits 14 Bit 7 6 Reserved 0 O O O O O O O gt lt gt lt X gt lt gt lt gt lt gt lt O Ol O O O NO UU NO NO Reserved UNUSED Module Organization Bit 2 Bit 0 SDRAM Device Width 4 Bits Bit 5 Bit 3 Number of Ranks 1 Rank Bit 7 6 Reserved 0 Bit 2 Bit 0 Primary bus width in bits 64 Bits Bit 4 Bit 3 Bus width extension in bits 8 Bits Bit 7 Bit 5 Reserved 0 Fine Timebase FTB Div
14. pacitance A DC Characteristics T1 0 to 70 C Voltage referenced to Vss 0 V Input Leakage Current 1 2 Any input 0 V lt VIN lt VDD loL 10 10 UA 2 3 Output Leakage Current OV lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled Document 06566 Revision A 24 Sep 09 Dataram Corporation 2009 Page 5 iaa D 1M64315B A 2GB 240 Pin 1Rx4 Registered ECC DDR3 DIMM lbp Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Test Condition Max Unit Value Operating One l Bank Active ER Operating current One bank ACTIVATE to PRECHARGE 1440 mA Precharge Current Operating One Operating current One bank ACTIVATE to READ to Bank Active Read Ibo1 PRECHARGE 1710 mA Precharge Current 80 Precharge Power Do2P Precharge power down current Slow exit MA Down Current 1 Precharge Power lon2P Precharge power down current Fast exit 540 mA Down Current Precharge Quiet Precharge quiet standby current Precharge Standby y Precharge standby current EN mA Current Active Power Down Active power down current Current Ibb3P 540 mA Active Standby Active standby current Operating Burst Burst write operating current Operating Burst Burst read operating current Burst Refresh Refresh current Self Refresh Self refresh temperature current MAX Tc 85 C 180 mA Current
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