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Intel Celeron P4500

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1. 53 5 1 1 Intel Graphics Dynamic Frequency nr 53 5 1 2 Intel Graphics Dynamic Frequency Thermal Design Considerations and EET 54 5 1 3 Idle Power Specifications ne 56 5 1 4 Intelligent Power Sharing Control 2 2 1 57 5 1 5 Component Power Measurement Estimation 58 5 2 Thermal Management 1 nnn 58 5 2 1 Processor Core Thermal Features 1 nnn nnn 58 5 2 2 Integrated Graphics and Memory Controller Thermal Features 65 5 2 3 Platform Environment Control Interface PECI 202022 2 68 Signal Description sies ala pe EUR IDE QC B CURE DER 70 6 1 System Memory Interface 71 6 2 Memory Reference and Compensation 50 eee 73 6 3 Reset and Miscellaneous Signals 0 00 0 ene 74 6 4 PCI Express Graphics Interface 5 mmn 75 6 5 Embedded DisplayPort 44 40 0 6 1 ETE
2. 94 Storage Condition 5 95 Datasheet Table 7 40 Table 7 41 Table 7 42 Table 7 43 Table 7 44 Table 7 45 Table 7 46 Table 7 47 Table 8 48 Table 8 49 Table 8 50 Table 8 51 Datasheet Processor Core VCC Active and Idle Mode DC Voltage and Current Specifications 96 Processor Uncore I O Buffer Supply DC Voltage and Current Specifications 98 Processor Graphics VID based VAXG Supply DC Voltage and Current mus 99 DDR3 Signal Group DC 100 Control Sideband and TAP Signal Group DC 5 101 PCI Express DC Specifications ceder ree re eR EP RETI E ELE PET Ys 102 eDP DC Specifications aaa kn FEET cian 103 PEC DC Electrical LIMITS a Pte e led ale n 104 rPGA988A Processor Pin List by Pin 110 rPGA988A Processor Pin List by Pin 124 BGA1288 Processor Ball List by Ball Name 142 BGA1288 Processor Ball List by Ball Number
3. 43 4 2 4 COPe C StateS iv tke KG RO UOCE KE KE ERE Ra 44 4 2 9 Package C States ios 45 4 3 MC Power Management icc RR Kd 48 4 3 1 Disabling Unused System Memory 5 2 2 7 7 424 4 4 49 4 3 2 DRAM Power Management Initialization 2 22 20 2 2 22 49 4 4 PCle Power Management e 50 4 5 Power 4 4 51 4 6 Integrated Graphics Power 000500 51 4 6 1 Intel Display Power Saving Technology 5 0 Intel DPST 5 0 51 4 6 2 Graphics Render C State 2 2 2 2 4 2 4 2 nnn 51 4 6 3 Graphics Performance Modulation 51 4 6 4 Intel Smart 2D Display Technology Intel 52007 51 4 7 Thermal Power Management 4 nnne nnne nn nnn nn 52 Thermal Management eta ka e ea CERE ERO ERR UTR RR LAUREA cac na 53 5 1 Thermal Design Power and Junction
4. iL 1 750 08 SIDE VIEW DETAIL A SCALE 20 1 t 1 PACKAGE UNDERF ILL 0 57 0 37 MAX PACKAGE SUBSTRATE D e TOT NTT Datasheet 179 Processor Pin and Signal I nformation intel Figure 8 26 rPGA Mechanical Package Sheet 2 of 2 ToS 1900 9 0961 MAIN NOL1108 189138 3 2 3IevWOTW 9071 EHUHHE EU 225020 589999 555 80099b0o20D009220 L 66000000 H HEERE 25000 3222 NJIA 2015 MAIN 401 18 90953 65 Datasheet 180 intel Processor Pin and Signal Information Figure 8 27 BGA Mechanical Package Sheet 2 of 2 21 25 OQ vinys 610953 now zie 61105 00 Od 3931102 01551 0022 amp Or 31 2
5. 4 7 22 2 222 15 1 4 Power Management senem nhe reme he enne nnn nn 15 1 4 1 Processor eee ea e RE EE K ga a eger 15 1 4 2 SySLeImu scies hie ERR RE 15 1 4 3 Memory Controller eror terret A N 16 1 4 4 POI EXPRESS Elder Doce d ds lcd 16 pamm 16 1 4 6 Integrated Graphics Controller mme 16 1 5 Thermal Management 5 4 2 2 442 4 4 144 1 nnn 16 1 6 2 e ct rur ER e cR E e gud 16 1 7 Terminology ios erat desit Ee ea datar ate adc 17 1 8 lt Related Documents cte peru ERE chides POR VH ER PE LE ERRARE ERE EN 19 2 20 2 1 System 20 2 1 1 System Memory Technology 20 2 1 2 System Memory Timing Support mne 21 2 1 3 System Memory Organization Modes a r 21 2 1 4 Rules for Populating Memory 10 5 mme 23 2 1 5 Technology Enhancements of Intel Fast Memory Access I
6. RSTIN Reset In When asserted this signal will asynchronously reset the processor logic CMOS This signal is connected to the PLTRST output of the PCH 7 0 Breakpoint and Performance Monitor Signals Outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance 1 0 GTL DBR Debug Reset Used only in systems where no debug port is implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive system reset This signal only routes through the package and does not connect to the the processor silicon itself 74 Datasheet Signal Description tel Table 6 24 Reset Miscellaneous Signals Sheet 2 of 2 Direction Buffer PRDY A processor output used by debug tools to determine processor debug Me m GTL readiness PREQ PREQ Used by debug tools to request debug operation of the processor Asynchronous GTL RSVD RESERVED All signals that are RSVD and No Connect RSVD TP RSVD NCTF must be left unconnected on the Test Point RSVD NCTF board However Intel recommends that all Non Critical to RSVD TP signals have via test points Function 6 4 PCI Express Graphics Interface Signals Table 6 25 PCI Express Graphics Interface Signals Type PEG RX 15 0 PCI Express Graphics Receive PEG_RX 15 0 Differential Pair PCI Express PEG_TX 15 0 PCI E
7. gt lt lt 5 maala gt Datasheet 141 m e Processor Pin and Signal I nformation 1 tel Table 8 50 BGA1288 Processor Ball List by Ball Name Table 8 50 BGA1288 Processor Ball Sheet 2 of 37 List by Ball Name Buffer Type Sheet 1 of 37 1 AD69 COMP2 AC70 COMP3 AD71 m DC TEST A5 A DC TEST A68 DC TEST A69 DC TEST A71 DC TEST BR1 B DC TEST BR71 DC TEST BT1 B DC TEST BT3 B DC TEST BT69 Buffer Type BCLKAC71 A DIFF CLK BCLK DIFF CLK BCLK ITP DIFF CLK BCLK 1 DIFF CLK 4 A 7 6 6 6 K K 6 K M N A A A A A A 1 DC TEST BT71 BT71 DC TEST DC TEST BV3 DC TEST BV5 O DC TEST BV68 NEN NEN lt lt lt lt K69 BPM 7 M69 CATERR 1 G CFG O AL CMO CFG 1 CMO AK2 K7 K8 71 0 9 GTL 7 GTL 2 GTL 65 GTL 62 GTL GTL 69 GTL 69 GTL 61 TL 14 2 CFG 2 2 K4 2 7 F4 2 H1 C2 C4 E2 D1 F8 F6 B7 DC TEST BV69 BV69 DC TEST BV71 DC TEST C3 C DC TEST C69 C DC_TEST_C71 DC TEST E1 DC TEST E71
8. 160 intel Revision History Revision Description Revision Date Number Initial release October 2010 8 Datasheet Features Summary intel 1 1 1 Note Datasheet Features Summary Introduction Intel Celeron P4000 and U3000 mobile processor seriesis the next generation of 64 bit multi core mobile processor built on 32 nanometer process technology Based on the low power high performance Nehalem micro architecture the processor is designed for a two chip platform as opposed to the traditional three chip platforms processor GMCH and ICH The two chip platform consists of a processor and the Platform Controller Hub PCH and enables higher performance lower cost easier validation and improved x y footprint The PCH may also be referred to as Mobile Intel 5 Series Chipset formerly Ibex Peak M Intel Celeron P4000 and U3000 mobile processor series is designed for the Calpella platform and is offered in rPGA988A and BGA1288 package respectively Included in this family of processors is Intel HD graphics and memory controller die on the same package as the processor core die This two chip solution of a processor core die with an integrated graphics and memory controller die is known as a multi chip package MCP processor 1 Throughout this document Intel Celeron P4000 and U3000 mobile processor series is referred to as processor 2 Throughout this document Intel HD graphics is referred
9. 56 35 W Standard Voltage SV Processor Idle 57 Signal Description Buffer Types nmm 66 nnn 70 Memory Channel nasa 71 Memory Channel B rure e EXE 72 Memory Reference and Compensation 73 Reset and Miscellaneous Signals sess 74 PCI Express Graphics Interface 5 75 Intel Flexible Display Interface rr r 76 DMI Processor to PCH Serial Interface 77 rs m 77 78 Error and Thermal 79 PoWer Sequericilg 80 Processor Power Signals iecit hair RR ERE YR 81 Ground and NCTE uo er 83 Processor Internal Pull Up Pull 83 Voltage Identification Definition 2 2 meme 86 Market Segment Selection Truth Table for 510 2 0 90 Signal Groups 1 91 Processor Absolute Minimum and Maximum
10. PEG ICOMPI PEG RCOMPO PEG RBIAS NOTES 1 Refer to Chapter 6 for signal description details 2 SA and SB refer to DDR3 Channel A and DDR3 Channel B 3 These signals are only applicable for the BGA package 4 These signals are only applicable for the rPGA988A package All Control Sideband Asynchronous signals are required to be asserted deasserted for at least eight BCLKs in order for the processor to recognize the proper signal state See Section 7 10 for the DC specifications 7 7 Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic Intel recommends the processor be first in the TAP chain followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Two copies of each signal may be required with each driving a different voltage level Datasheet 93 n tel I Electrical Specifications 7 8 Absolute Maximum and Minimum Ratings Table 7 38 specifies absolute maximum and minimum ratings At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limit
11. ozr o wes nensi cw rae emos wus 1 GTL PREQ AP27 Async GTL PROC_DPRSLPV AM34 CMOS R PROCHOT AN26 Async 1 0 GTL PSI AN33 Async CMOS RESET_OBS AP26 Async CMOS RSTIN RSVD pM ov neve 247 G p A19 Table 8 49 rPGA988A Processor Pin List by Pin Name 126 n tel Processor Pin and Signal I nformation Table 8 49 rPGA9884A Processor Pin Table 8 49 rPGA988A Processor Pin List by Pin Name List by Pin Name RSVD TP RSVD TP RSVD TP RSVD TP SA 5 0 SA BS 1 SA 5 2 SA SA SA CK 1 SA_CK 0 SA 1 SA CKE 0 SA 1 SA_CS 0 SA_CS 1 SA DMI0 SA DM 1 SA DM 2 SA DM 3 4 SA DM 5 SA DMI6 127 Datasheet e Processor Pin and Signal I nformation I n tel Table 8 49 rPGA988A Processor Pin Table 8 49 rPGA988A Processor Pin List by Pin Name List by Pin Name Buffer Type SA 48 DDR3 SA 49 10 DDR3 SA DQI 50 AR11 1 0 SA_DQ 51 AL11 DDR3 I O 5 52 AM9 1 0 8 7 Buffer Type DDR DDR SA 12 SA 13 SA 14 DDR SA 15 DDR 89 87 8 65 SA DQ 16 Hio DDR 8 9 Gm A A A A lt SA DQ 17 DDR SA 18 DDR SA 00 19 DDR SA 00 20 DDR SA
12. Asynchronous VccPwRGooD 1 VrTPWRGOOD CMOS Input Single Ended jb Asynchronous SM DRAMPWROK CMOS Input Single Ended Asynchronous RESET OBS CMOS Output Single Ended 1 Asynchronous GTL PRDY THERMTRIP Output Single Ended Asynchronous GTL PREQ Input Single Ended GTL Bi directional CATERR BPM 7 0 Single Ended Asynchronous Bi PECI directional Single Ended p Asynchronous GTL PROCHOT Bi directional Single Ended qa CMOS Input PM_SYNC PM_EXT_TS 0 PM_EXT_TS 1 CFG 17 0 Single Ended qb CMOS Input RSTIN Single Ended r CMOS Output PROC_DPRSLPVR VID 6 sELECT Single Ended s CMOS VID 5 3 CSC 2 0 NN Single Ended Analog Input COMPO 1 COMP2 COMP3 SM RCOMP 2 0 IsENSE Analog Output SA DIMM VREFDQ SB DIMM VREFDQ 3 Power ck t ta u v w No Connect Test RSVD RSVD TP RSVD NCTF Point X y z Single Ended Power Ground Other Single Ended Asynchronous PSI CMOS Output Sense Points Vcc_SsENSE 55 SENSE SENSE Vss SENSE VTT VAXG SENSE 55 SENSE Other SKTOCC DBR PROC DETECT VCAPO VCAP VCAP2 92 Datasheet Electrical Specifications n tel Table 7 37 Signal Groups Sheet 3 of 3 sem 5580 4 I ntegrated Graphics PCI Express Graphics Single Ended ae Analog Input PEG
13. pee aus ws e sus vo sue sor o am sessi ew o DDR3 DDR3 iw 2 9 Ola 2 2 m sus Saas ws sus Sawer pomo O suo saman pom o sus soon m e BH53 SA 0142 DDR3 C285 BH59 SA_DM 7 DDR3 D D BF59 BG15 SA DQ 21 BG17 SA 18 BG24 SA DQI30 O O O O O O G O O O U D uj WW NI N NI NIN ejeje o DM BJ o 5 H 00 00 w mnm m m A A Oy uy gt Ul R3 R3 R3 R3 R3 R3 R3 R3 169 Datasheet Processor Pin and Signal I nformation Datasheet Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 21 of 37 6 SA DQI 60 DDR sss am DDR m s ol lt lt WwW OU N N N P O BJ S Q A o 5 OjO O O O O O o o 9 9 2 n 913 91919 91919 0 9191 10 0 9 9 1 9 G GO l G Gl GI 91095 19 9519191 9 919109 1 O z 2 Ww w Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 22 of 37 38 BL40 BL47 SA ODT 1 BL55 VSS GND GND I 170 Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 23 of 37
14. 10 DDR3 1 0 RSVD SA DMI 2 BM15 DDR3 RSVD SA DM 3 BN24 DDR3 RSVD SA BG44 DDR3 RSVD SA DM 5 BG53 DDR3 RSVD SA DM 6 BN62 DDR3 RSVD SA DMI 7 59 DDR3 RSVD SA DQI0 ATs DDR3 1 0 RSVD SA_DQ 1 6 DDR3 11 0 RSVD SA_DQ 2 BBS DDR3 1 0 VCAPO VSS SENSE wa SA DQI3 9 DDR3 1 0 VCAPO SENSE wes SA_DQI4 7 DDR3 1 0 RSVD_NCTF ae SA_DQI5 Ave 1 0 RSVD_TP BR5 SA DQI 6 BEG DDR3 1 0 RSVD_NCTF BT5 SA DQI7 Bes DDR3 1 0 RSVD NCTF BV6 SA DQI8 1 0 RSVD NCTF BV8 SA DQI9 1 0 RSVD_NCTF S SA 10 BK5 DDR3 O RSVD NCTF SA 11 BH13 DDR3 RSVD NCTF SA DQ 12 BF9 DDR3 RSVD TP AN7 SA DQ 13 BF6 DDR3 1 O RSVD TP SA 14 BK7 DDR3 RSVD TP AUI NEN SA DQ 15 BN8 DDR3 O SA BS 0 BT38 DDR3 SA DQ 16 BN11 DDR3 1 0 SA BS 1 BH38 DDR3 SA DQ 17 BNO 1 0 SA 5 2 BF21 DDR3 SA DQ 18 BG17 DDR3 1 0 145 Datasheet 8 Processor Pin and Signal I nformation n te 6 Table 8 50 BGA1288 Processor Ball Table 8 50 BGA1288 Processor Ball List by Ball Name List by Ball Name Sheet 9 of 37 Sheet 10 of 37 SA DQ 19 BK15 DDR SA DQI 20 DDR SA DQI 21 BG15 DDR SA DQI 22 BH17 DDR SA DQI 23 BK17 DDR SA DQI 24 BN20 DDR SA DQ 25 BN17 DDR SA DQI 26 BK25 DDR SA DQI 27 BH25 DDR SA DQI 28 BJ20 DDR SA DQI 29 BH21 DDR SA DQI 30 BG24 DDR S
15. 21 DDR SA DQI22 DDR SA DQI23 DDR we 5 5 5 8 BEBE DDR SA DQI24 SA DQI 60 AT12 DDR3 SA DQ 25 DDR SA DQI26 DDR SA DQI27 DDR N N I 00 SA SA 09512 s C9 F8 9 3 1 SA DQI28 DDR O SA_DQ 29 DDR SA_DQ 30 DDR 17 19 is Ke WP SA 31 P9 DDR AHS ARS AC AF6 AGS NT lt lt ojojo lt lt ojojo A M SA_DQS 5 AK10 1 0 SA 32 DDR SA DQ 33 DDR SA DQ 34 DDR SA DQ 35 DDR SA DQ 36 SA DQ 37 SA DQ 38 7 DDR SA 39 DDR SA DQ 40 DDR SA DQI41 DDR SA 42 DDR SA 43 DDR SA 44 DDR SA 45 7 DDR SA DQ 46 DDR SA DQI47 DDR ojojo SA DQS 7 AR13 DDR3 1 0 H G A A SA_DQS 0 pos v s O H SA_DQS 3 SA_DQS 4 AH SA_DQS 5 1 SA DQS 6 1 0 SA 005 7 1 0 O O O lt BBB 7 7 C6 10 G8 K7 J8 G7 10 17 17 6 M8 L9 L6 K8 H5 F5 K6 K7 F6 G5 K8 AL7 8 g 2 oj O W 2 W WI W 2 W Datasheet 128 n tel Processor Pin and Signal I nformation Table 8 49 rPGA9884A Processor Pin Table 8 49
16. intel Processor Pin and Signal I nformation 49 rPGA988A Processor Pin Table 8 Table 8 49 rPGA988A Processor Pin List by Pin Name List by Pin Name x ewm ew f 55 SENSE AJ35 A15 wear are _ AT1 sw mx lt o z 5 VSS VSS NCTF VSS SENSE VT 136 Datasheet n tel Processor Pin and Signal I nformation Table 8 49 rPGA9884A Processor Pin Table 8 49 rPGA988A Processor Pin List by Pin Name List by Pin Name RE K26 REF VITPWRGOOD 15 5 137 Datasheet intel Processor Pin and Signal I nformation Figure 8 21 BGA1288 Ballmap Top View Upper Left Quadrant 138 8 amp 5 7 E 3 3 5 Datasheet Processor Pin and Signal I nformation intel Figure 8 22 BGA1288 Ballmap Top View Upper Right Quadrant E 5 8 CCTs Bu ET M ER TERI 48 vs 3 ad ES 8 B B 8 gt 5 5 B 8 5 5 8 H E 4 8 3 DI 6 8 8 3 3 II 5 9 8 8 8 3 1
17. 5 Based on junction temperature of 50 C 98 Datasheet 5 em Electrical Specifications Table 7 42 Processor Graphics VI D based Supply DC Voltage and Current Specifications GFX VID VID Range for Vayg SV ULV Non VR LL Non VR Load Line Contribution for contribution VAXG rPGA BGA Max Current for Integrated Graphics Rail SV ULV Iccrpc_vaxG Thermal Design Current TDC for Integrated Graphics Rail SV ULV NOTES 1 These are pre silicon estimates and are subject to change 2 Minimum values assume Graphics Render C state RC6 is enabled 3 Vaxg is a VID Based rail driven by an Intel MVP6 5 compliant voltage regulator 4 This specification assumes Intel Turbo Boost Technology with Intelligent Power Sharing is enabled Figure 7 15 l Axc Static and Ripple Voltage Regulation Vaxe V Slope LLaxc at package SENSE and VSSAXG SENSE pins Differential Remote Sense required Vaxc nov t 2 296 GFX VID Vaxc 7 GFX VID VAXG_MIN LLAxG cCMAX_VAXG 2 2 GFX_VID VID 2 2 Vaxc Total tolerance window GFX_DPRSLPVR de asserted DC set point LL tolerance AC ripple for Standard and Enhanced Performance Frequency Modes VAXG Datasheet 99 n tel 7 Electrical Specifications Table 7 43 DDR3 Signal Group DC Specifications Symbol Parameter Apna roup Input Low Voltage
18. G18 1 Db 2 2 2 2 3 A32 C30 1 0 Processor Pin and Signal Information Table 8 49 rPGA988A Processor Pin List by Pin Name PEG RX 13 PEG RX 14 PEG RX 15 PEG RX4 0 PEG RX4 1 PEG RX4 2 PEG RX4 3 PEG 4 4 PEG 5 PEG 6 PEG RX4 7 PEG RX4 8 PEG RX4 9 PEG RX4 10 PEG RX4 11 PEG RX4 12 PEG RX4 13 PEG RX4 14 PEG 15 PEG TX 0 PEG TX 1 PEG TX 2 PEG TX 3 PEG TX 4 PEG TX 5 PEG TX 6 PEG TX 7 PEG TX 8 PEG TX 9 PEG TX 10 PEG TX 11 PEG TX 12 PEG TX 13 PEG TX 14 PEG TX 15 PEG TX4 0 A28 B29 A30 K35 G35 32 3 3 3 3 3 3 3 2 3 3 3 3 3 3 3 2 K2 G30 G29 F28 E27 D28 C27 C25 L33 Buffer Type PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe Datasheet Processor Pin and Signal I nformation Datasheet Table 8 49 rPGA988A Processor Pin List by Pin Name EXE Type ec nem wi rae Pcie o wes eap mso rae pescar um rae pesce ws we pm rae peser o ec rae ms rae o wee ns rae em o wes rae o Pee
19. Intel Graphics Dynamic Frequency Typical workloads are not intensive enough to push both the processor core and the integrated graphics and memory controller towards their TDP limit simultaneously As such the opportunity exists to share thermal power between the components and boost the performance of either the processor core or integrated graphics and memory controller on demand This intelligent power sharing capability is implemented by Intel Turbo Boost Technology Driver on these processors When enabled the integrated graphics and memory controller can increase its thermal power consumption above its own component TDP limit However the sum of component thermal powers adhere to the specified MCP thermal power limit On this processor Intel Graphics Dynamic Frequency is implemented via a combination of Intel silicon capabilities graphics driver and the Intel Turbo Boost Technology driver If Intel provides Intel Graphics Dynamic Frequency support for the target operating 53 Caution 5 1 2 n tel I Thermal Management system that is shipped with the customer s platform and Intel Graphics Dynamic Frequency is enabled the Intel Turbo Boost Technology driver and graphics driver must be installed and operating to keep the product operating within specification limits The TURBO POWER CURRENT LIMIT MSR is exclusively reserved for Intel Turbo Technology Driver use Under no circumstances should this value be altered from the defau
20. RX 0 5 CFG 3 3 6 6 7 R T T CMO 6 CFG 4 CMO A CFG 5 CMO CFG 6 CMO CFG 7 CMO CFG 8 AF4 CMO CFG 9 CMO CFG 10 A A A G RX 1 F A DMI_RX 2 K F D D CMO D D CFG 11 CMO EH RX 3 12 CFG 12 ACA CMO ADI 9 DMI_RX 0 7 CFG 13 CFG 14 CFG 15 CMO Are CFG 16 AF6 CMO 87 CFG 17 CMO COMPO AE66 Analog CMO A CMO DMI TX 0 G 7 Dn TX 1 M15 DM DMI TX 2 G13 D D DMI _ RX 2 K8 D D D MI MI MI DMI_RX 1 MI MI MI MI MI MI Datasheet 142 n tel Processor Pin and Signal I nformation Table 8 50 BGA1288 Processor Ball Table 8 50 BGA1288 Processor Ball List by Ball Name List by Ball Name Sheet 3 of 37 Sheet 4 of 37 et oS Buffer Type GFX_VID 4 AN71 CMOS GFX VID 5 AM67 CMOS PEG_CLK 121 DIFF CLK PEG RCOMPO 1 RX 2 G PEG RX 3 M PEG RX 4 J G G G G DMI TX 3 111 DMI DMI_TX 0 DMI_TX 1 DMI_TX 2 DMI_TX 3 DPLL_REF_SSCLK DPLL_REF_SSCLK FDI_FSYNC 0 FDI_FSYNC 1 FDI_INT FDI_LSYNC 0 FDI_LSYNC 1 FDI TX 0 FDI TX 1 FDI TX 2 FDI TX 3 FDI TX 4 FDI TX 5 FDI TX 6 FDI TX 7 FDI 4 0 FDI TX4 1 FDI TX4 2 FDI TX4 3 FDI TX4 4 FDI TX4 5 FDI TX4 6 FDI TX4 7 GFX DPRSLPVR GFX GFX GFX VID 1 GFX VID 2 AG70 CMOS G
21. Sheet 29 of 37 Sheet 30 of 37 Datasheet 156 n tel Processor Pin and Signal I nformation Table 8 50 BGA1288 Processor Ball Table 8 50 BGA1288 Processor Ball List by Ball Name List by Ball Name Sheet 31 of 37 Sheet 32 of 37 Buffer Buffer Type Type BU55 GND G30 GND BU58 GND G43 GND BU62 GND G47 GND BU7 GND 648 GND G53 GND G57 GND C68 G70 GND D10 D13 H36 GND D17 GN H43 GND D20 GN H53 GND D24 GN GND D27 GN GND D34 GN GND D38 GN GND 041 GND E12 GN GND E16 GN GND E30 GN K25 GND E33 GN K32 GND GND K34 GND K36 GND GND K43 GND K53 GND GND K64 GND L13 GND 47 GND 148 GND GND L57 GND GND L70 GND G20 GND G24 GND M36 GND 157 Datasheet intel Processor Pin and Signal I nformation Table 8 50 BGA1288 Processor Ball Table 8 50 BGA1288 Processor Ball List by Ball Name Sheet 34 of 37 List by Ball Name Sheet 33 of 37 Analog EN Analog VSSAXG SENSE AF10 Analog EN F63 VSS SENSE VIT 53 2 Uu 5 Uu 2 R12 CMOS Analog EN VIT SELECT AN1 N13 VIT SENSE 158 Datasheet n tel Processor Pin and Signal I nformation Table 8 50 BGA1288 Processor Ball Table 8 50 BGA1288 Processor Ball List by Ball Name List by Ball Name Sheet 35 of 37 Sheet 36 of 37 Buffer Buffer Type Type VITO AN35 REF VIT U32 REF VITO AN59 REF VITO U33 REF VTTO AN60 REF VTTO U35 REF V
22. When activated during writes the corresponding data groups in the SDRAM are masked There is one SB DM 7 0 for every data byte lane SB DQS 7 0 Data Strobes SB DQS 7 0 and its complement signal group make up DDR3 differential strobe pair The data is captured at the crossing point of SB DQS 7 0 and its SB DQS2 7 0 during read and write transactions SB DQS2 7 0 Data Strobe Complements These are the 1 0 complementary strobe signals DDR3 SB_DQ 63 0 Data Bus Channel B data signal interface to the SDRAM data bus DDR3 72 Datasheet Signal Description tel Table 6 22 Memory Channel Sheet 2 of 2 Direction SB MA 15 0 Memory Address These signals are used to provide the multiplexed row column DDR3 address to the SDRAM SB CK 1 0 SDRAM Differential Clock Channel B SDRAM Differential clock signal pair The DDR3 crossing of the positive edge of SB CK and the negative edge of its complement SB_CK are used to sample the command and control signals on the SDRAM SB_CK 1 0 SDRAM I nverted Differential Clock Channel SDRAM Differential clock signal DDR3 pair complement SB CKE 1 0 Clock Enable 1 per rank Used to O Initialize the SDRAMs during power up DDR3 Power down SDRAM ranks Place all SDRAM ranks into and out of self refresh during STR Chip Select 1 per rank Used to select particular SDRAM components during the DDR3 active state The
23. mw ws ga 8 LM S sr m pn roc NO e PEG_RX 6 Lac m LN 7 ns w rw 19 NNNM Processor Pin and Signal I nformation Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 32 of 37 cu per pe ps ws e K71 BCLK ITP DIFF CLK 2 FDI_TX 0 FDI 13 VSS GND 20 PEG TX 15 PEG CLK Diff CLK PEG TX4 11 PEG TX4 8 PEG TX4 1 Ei he ree Due ws m ws wc fef s mami x mo vc ef De RM NM Datasheet Processor Pin and Signal I nformation Datasheet Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 33 of 37 Buffer Type PROC DETECT THERMTRI P Async PECI Asyn PEG TX 13 PCIe PEG_TX 12 PCle PEG_TX 11 PCle PEG_TX 2 PCle PEG TX 1 PCIe PEG_TX 0 PCle N21 N17 N51 N57 N61 CATERR PROCHOT Async 1 0 RESET_OBS Async CMOS 2 z z z m c Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 34 of 37 PEG RXz 3 4 o 71 2 Uu FDI TX 3 FDI_TX 5 FDI_TX 5 VSS SENSE VIT aes eo z R21 VCCPLL VCCPLL R41 R42 VSS VSS R48 VCC R50 VSS R51 VCC R53 VSS R55 VCC R57
24. 8 8 3 5 lt lt _ IE E Datasheet 139 intel Figure 8 23 BGA1288 Ballmap Top View Lower Left Quadrant Processor Pin and Signal I nformation 9 MS 155 VS vs 6 WS vs 155 AS ws 155 ws 10 74 VC 66 x WC m 694 VC 69 TTO PL 9 41 ss 66 VS TTO MC 8 6 CE2 MS 7 2 2 MS 8 RR 8 8 8 8 8 2 8 MC t 2 Em T xC VC VC mam A 5 5 gm 195 x 55 C 5 m NEN E E vm mm ss 5 xu Menu 140 Datasheet Processor Pin and Signal I nformation intel Figure 8 24 BGA1288 Ballmap Top View Lower Right Quadrant
25. 87 Datasheet Table 7 35 Voltage Identification Definition Sheet 3 of 4 pep 1 eal o 7 od E 1 88 p E HE NS NE NEUE NEN ue qu 9 jJ ME NE ou NE NE Electrical Specifications 0 8250 I 0 8000 0 7875 0 7750 0 7625 0 7500 0 7375 0 7250 0 7125 0 7000 0 6875 0 6750 0 6625 pow 0 6375 o A N ul Datasheet intel Electrical Specifications lt 9 9 ES Jg o o gt d m i a F gt 9 5 gt a gt a gt N a gt m a gt a 1 a gt gt m m m m ri m 89 Datasheet l n tel gt Electrical Specifications Table 7 36 Market Segment Selection Truth Table for MSID 2 0 voc wares p we o o emm I Co o Co oa posee 1 1 7 5 90 9 1 3 o Standard Voltage SV 35 W Supported 3 Lacu ees 1 NOTES MSID 2 0 signals are provided to indicate the maximum platform capability to the processor MSID is used on rPGA988A platforms only 3 Processors specified
26. DDR3 RSVD VSS RSVD_TP VDDQ SB 1 DDR3 VSS SB_CK 1 DDR3 SA_MA 6 DDR3 N SA_MA 15 DDR3 SA_CK 1 DDR3 VSS N SA CK 1 DDR3 VCC E SB_RAS DDR3 VCC E VSS N VCC VCC VCC VCC VCC VCC E VCC E VCC E SA_MA 1 DDR3 VDDQ REF SB_BS 1 DDR3 VSS GND VDDQ REF SB CK 0 DDR3 123 Datasheet e Processor Pin and Signal I nformation I n tel Table 8 49 rPGA988A Processor Pin Table 8 49 rPGA988A Processor Pin List by Pin Name List by Pin Name aaa Type Type ras i DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DIFF CLK DIFF CLK A C A G G G G D B24 D23 B23 23 A24 23 B22 21 D25 F24 E23 23 D24 24 F23 H23 18 A17 F17 E17 17 F18 D17 D22 21 D20 18 22 E20 F20 19 E22 21 D19 D18 FD FD FD FD FD FD FD FD FD FD FD D Datasheet 124 intel 125 Table 8 49 rPGA988A Processor Pin 4 4 FDI_TX 5 FDI TX4 6 FDI_TX 7 GFX_DPRSLPVR GFX_IMON GFX_VID 0 GFX_VID 1 GFX_VID 2 GFX_VID 3 GFX_VID 4 GFX_VID 5 GFX_VID 6 GFX_VR_EN ISENSE KEY PECI PEG_CLK PEG_CLK RBIAS RCOMPO RX 0 RX 1 RX 2 RX 3 RX 4 RX 5 RX 6 RX 7 RX 8 RX 9 RX 10 RX 11 RX 12 List by Pin Name
27. L28 2 2 20 PEG TX 4 PCle PROC_DPRSLPVR CMOS PEG TX 5 PCle 6 F68 N7 G3 L40 N38 N32 B39 B37 H32 PEG_TX 6 34 PCle D36 B30 D33 28 25 24 Q 4 51 Async CMOS RESET OBS Async CMOS RSTIN G3 CMOS RSVD BE71 RSVD BE69 RSVD RSVD RSVD AW70 RSVD A10 NEN NEN RSVD 69 RSVD TP 71 E NEN E PEG TX 7 D36 PCle TX 8 PCle TX 9 B30 PCle TX 10 D33 PCle PEG TX 11 N28 PCle N PEG_TX 12 M PCle N PEG TX 13 N24 PCle PEG TX 14 PCle PEG TX 15 PCle PEG_TX 0 40 PCle 111 PCle PEG_TX 2 PCle PEG_TX 3 D40 PCle RSVD AC69 PEG_TX 4 PCle RSVD_TP AC71 RSVD AH66 RSVD AK66 RSVD AK69 RSVD 71 RSVD AM66 RSVD PEG 51 PCIe PEG_TX 6 PCle PEG_TX 7 PCle PEG_TX 8 PCle PEG TX4 9 PCle PEG_TX 10 PCle Datasheet 144 n tel Processor Pin and Signal I nformation Table 8 50 BGA1288 Processor Ball Table 8 50 BGA1288 Processor Ball List by Ball Name List by Ball Name Sheet 7 of 37 Sheet 8 of 37 Buffer Buffer Type Type RSVD SA_CAS BK43 DDR3 RSVD SA CK 0 BM34 DDR3 RSVD SA CK 1 BK36 DDR3 RSVD SA_CK 0 BP35 DDR3 RSVD SA_CK 1 BH36 DDR3 RSVD SA_CKE 0 BF20 DDR3 RSVD SA_CKE 1 24 DDR3 RSVD SA 5 101 BH40 DDR3 RSVD 5 1 47 DDR3 1 0 RSVD SA DM 0 10 DDR3 RSVD SA DMI 1
28. SB_DQS 4 DDR3 1 0 gt N Fm LINES BEP ie r qve a hen pen LE per ES es ae gt hem ve HET 38 geom jv Table 8 48 rPGA988A Processor Pin List by Pin Number Tm SB DQ 39 ETA SA_DQS 4 DDR Te we 5 AH18 VAXG AH19 VAXG AH20 AH21 VAXG AH26 27 28 29 0 lt 5 5 AH32 AH33 AH34 AH35 si AJ3 SB DQ 34 DDR3 1 0 112 intel 113 Table 8 48 rPGA988A Processor Pin List by Pin Number 9 mo esp ec ser GND f eG K w Kx EH EA AJ4 AJ5 AJ6 AJ7 I O 1 0 AJ9 AJ 10 11 12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 1 0 1 0 21 J22 23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 3 3 G G G G G 1 0 N N N ND EF ND EF EF ND EF T N T T 1 0 R R R VAXG R G G G D D D L D L L D AK2 5 45 1 0 AK3 SB_DQ 40 1 0 AK4 SB_DQ 41 1 0 Ae C a ap ae An am ABS Aro Ber T a a CEN FEB 8 GE As 0 CESE As e LM Pr
29. Table 8 50 BGA1288 Processor Ball Table 8 50 BGA1288 Processor Ball List by Ball Name List by Ball Name Sheet 15 of 37 Sheet 16 of 37 as asas Type Type TRST P69 CMOS VAXG REF VAXG REF VAXG VAXG REF VAXG SENSE VAXG REF VCAPO VAXG REF VCAPO VAXG REF VCAPO VAXG REF VCAPO VAXG RE VCAPO VAXG RE VCAPO PWR VAXG RE VCAPO VAXG RE VCAPO VAXG VCAPO PWR VAXG RE VCAPO VAXG RE VCAPO VAXG RE VCAPO PWR VAXG RE VCAPO VAXG RE VCAPO VAXG VCAPO PWR VAXG RE VCAPO VAXG RE VCAPO VAXG VCAPO VAXG VCAPO VAXG VCAPO VAXG VCAPO VAXG VCAPO VAXG VCAPO VAXG VCAPO VAXG VCAP1 VAXG VCAP1 VAXG VCAP1 VAXG VCAP1 VAXG VCAP1 VAXG VCAP1 149 Datasheet m e Processor Pin and Signal I nformation 1 tel Table 8 50 BGA1288 Processor Ball Table 8 50 BGA1288 Processor Ball List by Ball Name List by Ball Name Sheet 17 of 37 Sheet 18 of 37 REF REF REF REF REF REF REF REF REF REF REF PWR PWR PWR PWR Datasheet 150 n tel Processor Pin and Signal I nformation Table 8 50 BGA1288 Processor Ball Table 8 50 BGA1288 Processor Ball List by Ball Name List by Ball Name Sheet 19 of 37 Sheet 20 of 37 151 Datasheet m e Processor Pin and Signal I nformation 1 tel Table 8 50 BGA1288 Processor Ball Table 8 50 BGA1288 Processor Ball List by Ball Name List by Ball Name Sheet 21 of 37 Sheet 22 of 37 ELE VSS 15 GND VSS A19 GND VSS A22 GND VSS A26 GND
30. VSS A29 GND VSS A33 GND VSS A45 GND VSS A48 GND VSS A52 GND VSS A55 GND VSS A59 GND VSS 64 GND VSS A66 GND 8 vss Z lt lt O O Datasheet 152 n tel Processor Pin and Signal I nformation Table 8 50 BGA1288 Processor Ball Table 8 50 BGA1288 Processor Ball List by Ball Name List by Ball Name Sheet 23 of 37 Sheet 24 of 37 rename has d Bl d Type Type 42 GND GND AA62 GND GND ABIS GND GNE 21 GND nee AB24 GND AGS GND 28 GND AHI GND A833 GND GND GND 4 GND AB9 GND GNE 1 GND AC5 GND 153 Datasheet m e Processor Pin and Signal I nformation 1 tel Table 8 50 BGA1288 Processor Ball Table 8 50 BGA1288 Processor Ball List by Ball Name List by Ball Name Sheet 25 of 37 Sheet 26 of 37 Datasheet 154 n tel Processor Pin and Signal I nformation Table 8 50 BGA1288 Processor Ball Table 8 50 BGA1288 Processor Ball List by Ball Name List by Ball Name Sheet 27 of 37 Sheet 28 of 37 Buffer Buffer Type Type AU14 GND AY17 GND AU4 GN GND 1 GN AY8 GND 9 GN 40 GND GND 44 GND GND B48 GND GND GNE B55 GND GND B58 GND GND B62 GND GND B65 GND GND CND 1 GND GND GND GND 155 Datasheet m e Processor Pin and Signal I nformation 1 tel Table 8 50 BGA1288 Processor Ball Table 8 50 BGA1288 Processor Ball List by Ball Name List by Ball Name
31. voltages within specification output decoupling must be properly designed Design the board to ensure that the voltage provided to the processor remains within the specifications listed in Table 7 35 Failure to do so can result in timing violations or reduced lifetime of the processor Voltage Rail Decoupling The voltage regulator solution must provide sufficient decoupling to compensate for large current swings generated during different power mode transitions e provide low parasitic resistance from the regulator to the socket meet voltage and current specifications as defined in Table 7 35 Processor Clocking BCLK BCLK The processor utilizes a differential clock to generate the processor core s operating frequency memory controller frequency and other internal clocks The processor core frequency is determined by multiplying the processor core ratio by 133 MHz Clock multiplying within the processor is provided by an internal phase locked loop PLL which requires a constant frequency input with exceptions for Spread Spectrum Clocking SSC The processor s maximum core frequency is configured during power on reset by using its manufacturing default value This value is the highest core multiplier at which the processor can operate 85 l n tel gt Electrical Specifications 7 3 1 Note PLL Power Supply An on die PLL filter solution is implemented on the processor Refer to Table 7 35 for DC specifi
32. 1 BCLK ef ef ef Datasheet 81 i n tel I Signal Description Table 6 32 Processor Power Signals Sheet 2 of 3 Type VID 6 VI D 6 0 Voltage I D Pins Used to 6 VID 5 3 CSCI2 0 support automatic selection of power supply CMOS VID 2 0 MSIDI2 0 voltages VCC These are CMOS signals that are driven by the processor CSC 2 0 VI D 5 3 Current Sense Configuration bits for ISENSE gain setting This value is latched on the rising edge of VTTPWRGOOD MSID 2 0 VID 2 0 Market Segment Identification is used to indicate the maximum platform capability to the processor A processor will only boot if the MSID 2 0 pins are strapped to the appropriate setting or higher on the platform see Table 7 36 for MSID encodings MSID is used to help protect the platform by preventing a higher power processor from booting in a platform designed for lower power processors MSID 2 0 are latched on the rising edge of VTTPWRGOOD NOTE VID 5 3 and VID 2 0 are bi directional As an input they are CSC 2 0 and MSID 2 0 respectively VIT SELECT The SELECT signal is used to select the correct VTT voltage level for the processor VCC SENSE Voltage Feedback Signals to an Intel MVP 6 5 VSS SENSE Compliant VR Use VCC SENSE to sense voltage and VSS SENSE to sense ground near the silicon with little noise VIT SENSE Isolated low impedance connection to the VSS SENSE VTT processor VTT voltage and gr
33. 2 4 2 1 4 2 4 2 2 2 4 2 3 2 4 2 4 Table 2 3 Datasheet intel Cursors A and B Cursors A and B are small fixed sized planes dedicated for mouse cursor acceleration and are associated with Planes A and B respectively These planes support resolutions up to 256 x 256 each VGA Used for boot safe mode legacy games etc Can be changed by an application without OS driver notification due to legacy requirements Display Pipes The display pipe blends and synchronizes pixel data received from one or more display planes and adds the timing of the display output device upon which the image is displayed This is clocked by the Display Reference clock inputs The display pipes A and B operate independently of each other at the rate of 1 pixel per clock They can attach to any of the display ports Each pipe sends display data to the PCH over the Intel Flexible Display Interface Intel FDI Display Ports The display ports consist of output logic and pins that transmit the display data to the associated encoding logic and send the data to the display device i e LVDS HDMI DVI SDVO etc All display interfaces connecting external displays are now repartitioned and driven from the PCH with the exception of the eDP DisplayPort Embedded DisplayPort eDP The DisplayPort abbreviated as DP different than the generic term display port specification is a VESA standard DisplayPort consolidates internal and external co
34. 7 D VSS N FDI_TX 4 D FDI TX 4 D TX 3 M DMI_TX 1 DM VTT1 E VTT1 E VTT1 SB DQSI2 1 0 VSS GND Datasheet Processor Pin and Signal I nformation Datasheet Table 8 48 rPGA988A Processor Pin List by Pin Number Buffer Type SA DMI 2 DDR3 vss GND SA_DQS 2 DDR3 1 0 SA_DQ 16 DDR3 1 O GND H1 RSVD_TP RSVD Ie s NEM MENS EM bees wm Es K PEG TX4 10 H31 PEG TX 7 V ew PEG RX 2 PEG RX 1 SB 23 DDR3 SB 22 DDR3 1 0 SB DQ 19 DDR3 1 0 SB 54 2 DDR3 SB DQI 24 DDR3 1 0 SB DQ 18 DDR3 SA 22 DDR3 o Table 8 48 rPGA988A Processor Pin List by Pin Number Type DDR3 1 0 DDR3 DDR3 vwo WF Vm TTo RE RD m RE yss GND GND REF REF REF REF REF REF ms GND SB DM 3 DDR3 SB DQ 25 DDR3 SB DQ 29 DDR3 SB DQ 28 DDR3 SA DQ 18 DDR3 I 120 Processor Pin and Signal I nformation intel Table 8 48 rPGA988A Processor Pin Table 8 48 rPGA988A Processor Pin List by Pin Number List by Pin Number Buffer Buffer Type Type VSS M5 SB DQSI3 DDR3 1 0 K10 M6 SA 25 DDR3 1 0 K26 M7 SA DMI3 DDR3 K27 VSS M8 SA 26 DDR3 1 0 K28 M9 SA DQS 3 DDR3 1 0 K29 M1 VSS N K3 M26 VCCPLL E K3 M27 RSVD K3 M2 K3 VSS M2
35. 8 18 Socket G rPGA988A Pinmap Top View Upper Right Quadrant 107 8 19 8 20 Figure 8 21 Figure 8 22 Figure 8 23 Figure 8 24 Figure 8 25 Figure 8 26 Figure 8 27 Tables Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 4 5 Table 4 6 Table 4 7 Table 4 8 Table 4 9 Table 4 10 Table 4 11 Table 4 12 Table 4 13 Table 4 14 Table 4 15 Table 4 16 Table 5 17 Table 5 18 Table 5 19 Table 6 20 Table 6 21 Table 6 22 Table 6 23 Table 6 24 Table 6 25 Table 6 26 Table 6 27 Table 6 28 Table 6 29 Table 6 30 Table 6 31 Table 6 32 Table 6 33 Table 6 34 Table 7 35 Table 7 36 Table 7 37 Table 7 38 Table 7 39 Socket G rPGA988A Pinmap Top View Lower Left Quadrant 108 Socket G rPGA988A Pinmap Top View Lower Right Quadrant 109 BGA1288 Ballmap Top View Upper Left Quadrant 138 BGA1288 Ballmap Top View Upper Right Quadrant 139 BGA1288 Ballmap Top View Lower Left Quadrant 140 BGA1288 Ballmap Top View Lower Right Quadrant 141 rPGA Mechanical Package Sheet 1 2 179 rPGA Mechanical Package Sheet 2 2 180 BGA Mechanical Package Sheet 2 2 41 4 4 2 7 2 27 0722 181 Support
36. 9NIN34O 151539 824105 VOR X99821 2 MAIA W 0 01108 909 9 90 oo oo 000009 000000000000000 000000000000000 0O00000000000000 000000000000000 oooooooooooooool 000000000000000 000000000000000 000000000000000 000000000000000 0000000000000 9o 000 0000 o 00000000000000 go 06800 oco o00000000000000 999 0000000000000 99 9999099009 00000000000 M 000000000000 o 9 oo 000000000000 9o ooo 91 31 25 1 120
37. Ball List by Ball Name List by Ball Name Sheet 13 of 37 Sheet 14 of 37 SB 009143 BT57 DDR SB DQ 44 BP56 DDR SB DQ 45 BT55 DDR SB DQ 46 BU60 DDR SB DQ 47 BV59 DDR SB DQ 48 BV61 DDR SB DQ 49 BP60 DDR SB DQ 50 BR66 DDR SB DQ 51 BR64 DDR SB DQ 52 BR62 DDR SB DQ 53 BT61 DDR SB DQ 54 BN68 DDR SB DQ 55 BL69 DDR SB DQ 56 BJ71 DDR SB DQ 57 BF70 DDR SB DQ 58 BG71 DDR SB DQ 59 BC67 DDR SB DQ 60 BK70 DDR SB DQ 61 BK67 DDR SB 009162 BD71 DDR SB 00163 BD69 DDR SB DQS 2 BV13 DDR SB DQS 3 BT17 DDR SB DQS 4 BT50 DDR SB DQS 5 BU56 DDR SB BV62 DDR SB DQS 7 BJ69 DDR SB DQSz 0 DDR SB_DQS 1 DDR SB_DQS 2 BU12 DDR SB_DQS 3 BT19 DDR SB_DQS 4 BT52 DDR SB_DQS 5 BV55 DDR SB_DQS 6 BU63 DDR3 UJ SB DQS 7 1 0 SB MA 10 SB MA 11 SB MA 12 SB MA 13 SB MA 14 SB MA 15 SB ODT 0 SB ODTI1 SB RAS ss SM DRAMPWROK AM5 Async CMOS SM DRAMRST BJ12 DDR3 SM BV33 SM_RCOMP 1 BP39 SM_RCOMP 2 BV40 TAPPWRGOOD Async CMOS eos Lm Dm Y70 T67 T69 CMOS P71 CMOS T70 N17 N65 g THERMTRIP GTL Fes Cwos gt lt 3 a I o a 5 5 w Wl W t W W WI 0 W W W W W WwW o Datasheet 148 n tel Processor Pin and Signal I nformation
38. Bridge Express port Device 1 PCI Express extends the configuration space to 4096 bytes per device function as compared to 256 bytes allowed by the Conventional PCI Specification PCI Express configuration space is divided into a PCI compatible region which consists of the first 256 bytes of a logical device s configuration space and an extended PCI Express region which consists of the remaining configuration space The PCI compatible region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express configuration access mechanism described in the PCI Express Enhanced Configuration Mechanism section The PCI Express Host Bridge is required to translate the memory mapped PCI Express configuration space accesses from the host processor to PCI Express configuration cycles To maintain compatibility with PCI configuration addressing mechanisms it is recommended that system software access the enhanced configuration space using 32 bit operations 32 bit aligned only See the PCI Express Base Specification for details of both the PCI compatible and PCI Express Enhanced configuration mechanisms and transaction rules PCI Express Ports and Bifurcation The external graphics attach PEG on the processor is a single 16 lane x16 port that can be configured at narrower widths bifurcated into two x8 PCI Express ports that may train to narrower widths The
39. DPLL_REF_SSCLK DPLL_REF_SSCLK 120 MHz Embedded DisplayPort eDP Datasheet 35 intel 3 1 1 3 1 2 36 Technologies I ntele Virtualization Technology Intel Virtualization Technology Intel VT makes a single system appear as multiple independent systems to software This allows multiple independent operating systems to run simultaneously on a single system Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets Intel Virtualization Technology Intel VT x added hardware support in the processor to improve the virtualization performance and robustness Intel Virtualization Technology for Directed I O Intel VT d adds chipset hardware implementation to support and improve 1 virtualization performance and robustness Intel VT x specifications and functional descriptions are included in the Intele 64 and 32 Architectures Software Developer s Manual Volume and is available at http www intel com products processor manuals index htm Intel VT x Objectives Intel VT x provides hardware acceleration for virtualization of IA platforms Virtual Machine Monitor VMM can use Intel VT x features to provide improved reliable virtualized platforms By using Intel VT x a VMM is Robust VMMs no longer need to use paravirtualization or binary translation This means that they will be able to run off the shelf OSs and applications w
40. Display synchronization FDI FSYNC FDI LSYNC Frame and Line Synchronization e One Interrupt signal used for various interrupts from the FDI INT signal shared by both Intel FDI Links e PCH supports end to end lane reversal across both links 1 4 Power Management Support 1 4 1 Processor Core Full support of ACPI C states as implemented by the following processor C states Ultra low voltage supports CO Ci C1E C3 Deep Power Down Technology code named C6 Standard voltage supports CO C1 C3 e Enhanced Intel SpeedStep Technology 1 4 2 System 50 S3 S4 S5 Datasheet 15 1 4 3 1 4 4 1 4 5 1 4 6 1 5 1 6 16 Features Summary Memory Controller e Conditional self refresh Intel amp Rapid Memory Power Management Intel RMPM e Dynamic power down PCI Express e 05 and L1 ASPM power management capability DMI e 05 and L1 ASPM power management capability I ntegrated Graphics Controller Intel Smart 2D Display Technology Intel S2DDT Intel amp Display Power Saving Technology Intel amp DPST Graphics Render C State RC6 Thermal Management Support Digital Thermal Sensor Adaptive Thermal Monitor THERMTRIP and PROCHOT support On Demand Mode Open and Closed Loop Throttling Memory Thermal Throttling External Thermal Sensor TS on DIMM and TS on Board Render Thermal Throttling Fan speed control with DTS Package e Intel
41. E Processor Pin and Signal I nformation Table 8 49 rPGA988A Processor Pin List by Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC RE Analog RE RE RE REF REF REF REF REF REF REF REF REF Datasheet intel Processor Pin and Signal I nformation 49 rPGA988A Processor Pin Table 8 49 rPGA988A Processor Pin Table 8 List by Pin Name List by Pin Name 132 Datasheet intel 133 Table 8 49 rPGA988A Processor Pin List by Pin Name Y35 REF VCC SENSE VCCPLL VCCPLL VCCPLL VCCPWRGOOD 0 CMOS Async VCCPWRGOOD 14 5 VDDQ B VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VID O VID 1 VID 2 CSC 0 VID 3 CSC 1 VID 4 CSC 2 VID 5 VID 6 VSS td A23 A29 GND GND GND Processor Pin and Signal Information Table 8 49 rPGA988A Processor Pin List by Pin Name GND GND GND Datasheet m 8 Processor Pin and Signal I nformation I n tel Table 8 49 rPGA988A Processor Pin Table 8 49 rPGA988A Processor Pin List by Pin Name List by Pin Name GND GND GND GND GND GND Datasheet 134 n tel Processor Pin and Signal I nformation Table 8 49 rPGA9884A Processor Pin Table 8 49 rPGA988A Processor Pin List by Pin Name List by Pin Name GND GND GND GND GND GND 135 Datasheet
42. Number Sheet 13 of 37 omm AW12 REF AW14 REF e RU e wis e aw mi e viol a z lt Q Q Q 2 2 z z 2 Z z Z a 090191521212 Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 14 of 37 AW24 VTTO DDR AW26 VTTO DDR AW28 VTTO DDR AW30 VTTO DDR AW32 VTTO DDR amas awa ew Ama PR Awa anso veso ew awsa e aw mue wm 72 s z s z 3 0 3 0 37 0 P O 2 2 2 2 z O 5 O l 79 O 2 N AY15 N AY19 N AY21 166 167 ntel Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 15 of 37 VSS VSS VSS VSS VSS VSS 2 2 VSS VSS VCAP1 VCAP1 VCAP1 CAPO CAPO 0 gt ol 2 41 QO s ol z o zl al zo VCAP em em e 21 PEG RX 11 AY55 60 62 z AY71 was LN mm LAN gt 5 m 8 PCIe 0 D vu S 4 5 o Processor Pin
43. R59 o 2 2 O 2 176 8 tel Processor Pin and Signal I nformation Table 8 51 BGA1288 Processor Ball Table 8 51 BGA1288 Processor Ball List by Ball Number List by Ball Number Sheet 35 of 37 Sheet 36 of 37 VSS RSVD RSVD VSS m ee RSVD FDI TX 6 FDI_TX 6 VSS ke pes RSVD DPLL REF SSCLK E 028 pw 30 VTTO z vm 33 VTTO us vm e ver vm VTTO VTTO VTTO 177 Datasheet 178 Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 37 of 37 her vem pw ws vei se vc 28 hw ws 28 wa vc hus ws on wa vc ws 28 vc er ws hs vc er ws vs ws wm _ y LK O ss DRF 5 DPLL REF SSCLK DIFF C VCCPWRGOOD 0 Async CMOS TAPPWRGOOD Async CMOS W69 W71 Y2 Y67 70 Y Processor Pin and Signal I nformation Datasheet Processor Pin and Signal I nformation n tel 8 2 Package Mechanical nformation Figure 8 25 rPGA Mechanical Package Sheet 1 of 2 or 2 COMMENTS PACKAGE MECHANICAL DRAWING DO SCALE DRAWING KEYING PINS COMMENTS BOTTOM VIEW
44. advantages of the Dual Channel Symmetric Interleaved and Dual Channel Asymmetric Modes Memory is divided into a symmetric and a asymmetric zone The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached In this mode the system runs with one zone of dual channel mode and one zone of single channel mode simultaneously across the whole memory array Figure 2 2 Intel Flex Memory Technology Operation TOM Non interleaved access 2 1 3 2 1 22 Dual channel interleaved access B The largest physical memory amount of the smaller size memory module The remaining physical memory amount of the larger size memory module CHA Dual Channel Symmetric Mode Dual Channel Symmetric mode also known as interleaved mode provides maximum performance on real world applications Addresses are ping ponged between the channels after each cache line 64 byte boundary If there are two requests and the second request is to an address on the opposite channel from the first that request can be sent before data from the first request has returned If two consecutive cache lines are requested both may be retrieved simultaneously since they are ensured to be on opposite channels Use Dual Channel Symmetric mode when both Channel A and Channel B SO DIMM connectors are populated in any order
45. and Signal I nformation Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 16 of 37 B23 RX4 10 PEG RX 9 PEG RX4 8 PEG RX 7 PEG TX 9 E PEG TX4 7 PCle 39 3 PCle 840 VSS 42 vcc 44 55 46 vcc 48 vss VCC VCC 55 vss 56 vcc 58 vss 60 vcc 62 55 ter O 2 m Q oy wj 00 pee Sa omer mom o vo _ w gt N Datasheet e Processor Pin and Signal I nformation I n tel Table 8 51 BGA1288 Processor Ball Table 8 51 BGA1288 Processor Ball List by Ball Number List by Ball Number Sheet 17 of 37 Sheet 18 of 37 Buffer Type BB17 VDDQ REF vilolvio 2 2 3 O Ql z Z Z o o Gal VI V 02 ol 9 2 2 2 2 2 2 21 CO SB CO 5 REF REF O z O z 2 9 2 Dl Bla a a a 5 Wy w Datasheet 168 8 tel Processor Pin and Signal I nformation Table 8 51 BGA1288 Processor Ball Table 8 51 BGA1288 Processor Ball List by Ball Number List by Ball Number Sheet 19 of 37 Sheet 20 of 37 Buffer Buffer Type Type pee faces sxomap ons we mmus we pen
46. as integrated graphics 3 Integrated graphics and memory controller die is built on 45 nanometer process technology 4 Intel Celeron P4000 U3000 mobile processor seriesis not Intel vPro eligible intel Platform Features Summary Figure 1 1 Intel amp Celeron amp P4000 and U3000 mobile processor series on the Calpella PCI Express x16 OR Express x 1 10 Intel Flexible DMI2 Display Interface x4 Intel Management Engine Mobile Intel 5 Series Chipset PCH 800 1066 MT s 2 Channels 1 SO DIMM Channel DDR3 SO DIMMs 7 6 Ports GE TN 14 Ports Intel HD Audio SMBUS 20 Controller Link 1 8 PCI Express x1 Ports 2 5 GT s Gigabit Network Connection Datasheet Features Summary intel 1 2 1 2 1 Note 1 3 1 3 1 Datasheet Processor Feature Details Two execution cores e A 32 KB instruction and 32 KB data first level cache L1 for each core e A 512 KB shared instruction data second level cache L2 256 KB for each core Up to 2 MB shared instruction data third level cache L3 shared among all cores Supported Technologies Intel Virtualization Technology Intel VT x Intel 64 architecture Execute Disable Bit Please refer to the Intel Celeron P4000 U3000 mobile processor series Specification Update for feature support details Interfaces System Memory Support One or two channels of DDR3 me
47. code named state C3 To C1 The decision to demote a core from Deep Power Down Technology code named C6 state to C3 or C3 Deep Power Down Technology code named C6 state to C1 is based on each core s immediate residency history Upon each core Deep Power Down Technology code named C6 state request the core C state is demoted to C3 or C1 until a sufficient amount of residency has been established At that point a core is allowed to go into C3 Deep Power Down Technology code named C6 state Each option can be run concurrently or individually This feature is disabled by default Package C States The processor supports CO C1 C1E C3 and Deep Power Down Technology code named C6 state package idle power states The following is a summary of the general rules for package C state entry These apply to all package C states unless specified otherwise A package C state request is determined by the lowest numerical core C state amongst all cores A package C state is automatically resolved by the processor depending on the core idle power states and the status of the platform components Each core can be at a lower idle power state than the package if the platform does not grant the processor permission to enter a requested package C state The platform may allow additional power savings to be realized in the processor Refer to Section 4 3 2 2 9 For package C states the processor is not required to enter CO before
48. damage latent or otherwise may occur The table also specifies sustained storage temperature relative humidity and time duration limits these limits specify the maximum or minimum 94 Datasheet Electrical Specifications n tel device storage conditions for a sustained period of time At conditions outside sustained limits but within absolute maximum and minimum ratings quality and reliability may be affected Table 7 39 Storage Condition Ratings Tabsolute storage The non operating device storage temperature 25 C 125 C 1 2 3 4 Damage latent or otherwise may occur when exceeded for any length of time Tsustained storage The ambient storage temperature in shipping media for a sustained period of time RHsustained storage The maximum device storage relative humidity 60 24 C for a sustained period of time Time sustained storage prolonged or extended period of time typically 0 Months 6 Months 7 associated with customer shelf life 1 Refers to a component device that is not assembled in a board or socket and is not electrically connected to a voltage reference or I O signal 2 Specified temperatures are not to exceed values based on data collected Exceptions for surface mount reflow are specified by the applicable J standard Non adherence may affect processor reliability 3 Tabsolute storage applies to the unassembled component only and does not apply to the shipping media moisture barrier bag
49. designed hysteresis the integrated graphics will continue to switch to lower frequency voltage operating points Once the DTS reports a temperature below the hysteresis value the render clock frequency and voltage will be restored to its pre thermal event state The Render Thermal Throttling must be enabled for the product to remain within specification Platform Environment Control I nterface The Platform Environment Control Interface is a one wire interface that provides a communication channel between Intel processor and chipset components to external monitoring devices The processor implements a PECI interface to allow communication of processor thermal information to other devices on the platform The processor provides a digital thermal sensor DTS for fan speed control The DTS is calibrated at the factory to provide a digital representation of relative processor temperature Averaged DTS values are read via the PECI interface The PECI physical layer is a self clocked one wire bus that begins each bit with a driven rising edge from an idle level near zero volts The duration of the signal driven high depends on whether the bit value is a Logic 0 or Logic 1 also includes variable data transfer rate established with every message The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components Bus spee
50. due to noise on the unused signals typically handled automatically when input receiver is disabled 4 4 PCI e Power Management Active power management support using LOs and L1 states All inputs and outputs disabled 12 13 Ready state 50 Datasheet Power Management 4 5 4 6 4 6 1 4 6 2 4 6 3 4 6 4 Datasheet DMI Power Management Active power management support using LOs L1 state I ntegrated Graphics Power Management Intel Display Power Saving Technology 5 0 Intel DPST 5 0 Intel DPST maintains visual experience by managing display image brightness and contrast while adaptively dimming the backlight As a result the display backlight power can be reduced by up to 2596 depending on Intel DPST settings and system use Intel DPST 5 0 provides enhanced image quality over the previous version of Intel DPST Graphics Render C State Render C State RC6 is a technique designed to optimize the average power to the graphics render engine during times of idleness of the render engine RC6 is entered when the graphics render engine blitter engine and the video engine have no workload being currently worked on and no outstanding graphics memory transactions When the render engine idleness condition is met The graphics VR will lower the graphics voltage rail into a lower voltage state 0 3 V The render frequency clock will shut down Graphics Performance Modulation Technology Graphics
51. factory PECI provides an interface for external devices to read the DTS temperature for thermal management and fan speed control More detailed information may be found in the Platform Environment Control Interface PECI Specification 7 11 1 DC Characteristics interface operates at a nominal voltage set by V set of DC electrical specifications shown in Table 7 47 is used with devices normally operating from a Vir interface supply V r nominal levels will vary between processor families All devices will operate at the Vr level determined by the processor installed in the system For specific nominal levels refer to Table 7 43 Datasheet 103 l n tel I Electrical Specifications Table 7 47 PECI DC Electrical Limits 02757 Ver 05007 vr edge Tresno 05507 ver 97257 Vr N A Sourd High Level Output Source mA Vou 0 75 sink Low Level Output Sink VoL 0 25 leaka High Impedance State Leakage to Vieak lleak High Impedance Leakage to GND N A 100 Vieak Vnoise Signal Noise Immunity above 300 MHz Vin Vn Vp la NOTES 1 supplies the PECI interface PECI behavior does not affect min max specifications 2 The leakage specification applies to powered devices on the PECI bus 7 11 2 Input Device Hysteresis The input buffers in both
52. from internal malicious software based attack by preventing relocation of key system data structures like IDT interrupt descriptor table GDT global descriptor table LDT local descriptor table and TSS task segment selector A VMM using this feature can intercept by a VM exit attempts to relocate these data structures and prevent them from being tampered by malicious software I ntel Graphics Dynamic Frequency Graphics render frequency are selected by the Intel graphics driver dynamically based on graphics workload demand as permitted by Intel Turbo Boost Technology Driver The processor core die and the integrated graphics and memory controller core die have an individual TDP limit If one component is not consuming enough thermal power to reach its TDP the other component can increase its TDP limit and take advantage of the unused thermal power headroom For the integrated graphics this could mean an increase in the render core frequency above its rated frequency and increased graphics performance Please note that processor Turbo is not supported on Celeron processor skus Processor Utilization of Intel Graphics Dynamic Frequency require the following Graphics driver e Intel Turbo Boost Technology Driver Enabling Intel Turbo Boost Technology and Intel Graphics Dynamic Frequency will maximize the performance of the GPU within its specified power levels Compared with previous generation products Intel Turbo Boo
53. gt o 5 Ww W W W W W W WwW O O O g lt 2 wj w wl O Ww Ww OO OO OO O OO OO OO OO OO OO OO OO OO OO W OO OO W W Ww Datasheet 146 n tel Processor Pin and Signal I nformation Table 8 50 BGA1288 Processor Ball Table 8 50 BGA1288 Processor Ball List by Ball Name List by Ball Name Sheet 11 of 37 Sheet 12 of 37 memes ser m s Type Type SA MA 11 SB DQI7 BH2 1 0 SA MA 12 SB DQI8 BG4 1 0 SA MA 13 SB 0191 BG1 1 0 SA MA 14 SB DQ 10 BR6 1 0 SA MA 15 SB 11 BR8 1 0 SA ODTIO SB DQ 12 1 0 SA_ODT 1 SB DQ 13 BK2 1 0 SA_RAS SB DQ 14 BU9 1 0 SA_WE SB_DQ 15 1 0 SB_BS 0 SB_DQ 16 1 0 SB_BS 1 SB DQ 17 1 0 SB_BS 2 SB_DQ 18 1 0 SB_CAS SB_DQ 19 1 0 SB CK 0 SB 20 1 0 SB CK 1 SB 21 1 0 SB_CK 0 SB_DQ 22 1 0 SB_CK 1 SB_DQ 23 1 0 SB_CKE 0 SB_DQ 24 1 0 SB_CKE 1 SB_DQ 25 1 0 SB CS 0 SB 26 1 0 SB_CS 1 SB DQI27 1 0 SB DMIO BB4 SB_DQ 28 1 0 SB_DM 1 4 SB 29 1 0 SB_DM 2 SB_DQ 30 1 0 SB_DM 3 SB_DQ 31 1 0 SB_DM 4 58 32 1 0 SB_DM 5 58 331 1 0 SB DM 6 SB 34 1 0 SB_DM 7 SB DQ 35 1 0 147 Datasheet e Processor Pin and Signal I nformation I n tel Table 8 50 BGA1288 Processor Ball Table 8 50 BGA1288 Processor
54. mew mel VSS SB_DQS 1 VSS SA DQ 17 1 0 mmi 54 pom wo BN13 SA 5052 1 0 BN17 SA DQI25 1 0 BN21 SA_ DOSI ms soma ms sums oos mr Sans O s vo mom o me wes eva us 98 sep poma serail o mm sea po o ws pea o TER o c o o m o uo uo 4 4 a 2 2 gt 2 gt 2 ala ofj NJ uw wl sS olal 5 o Processor Pin and Signal I nformation Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 24 of 37 Buffer Type DDR3 BP35 SA CK 0 DDR3 SM_RCOMP 1 SB_CS 0 DDR3 5 35 1 0 NE SA 00516 SB 00 49 DC TEST BR1 UJ 79 o BR69 BT24 BT26 BT27 BT29 BT31 Datasheet Processor Pin and Signal I nformation Datasheet Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 25 of 37 ELM 68 69 TEST 69 lt lt lt O O O DDR 2 gt gt gt 5 5 5 a UJ UJ Ww wl wl wt wt wl wl Ww Ww OO Ww Ww O z 9 2 z S G O z gt 5 G Table 8 51 BGA1288 Processor Ball List by Ball Nu
55. operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases Clock modulation is automatically engaged as part of the TCC activation when the frequency VID targets are at their minimum settings Processor performance will be decreased by the same amount as the duty cycle when clock modulation is active Snooping and interrupt processing are performed in the normal manner while the TCC is active Digital Thermal Sensor Each processor execution core has an on die Digital Thermal Sensor DTS which detects the core s instantaneous temperature The DTS is the preferred method of monitoring processor die temperature because t is located near the hottest portions of the die t can accurately track the die temperature and ensure that the Adaptive Thermal Monitor is not excessively activated Temperature values from the DTS can be retrieved through A software interface via processor Model Specific Register MSR A processor hardware interface as described in Platform Environment Control Interface PECI on page 68 When temperature is retrieved by processor MSR it is the instantaneous temperature of the given core When temperature is retrieved via PECI it is the average temperature of each execution core s DTS over a programmable window default window of 256 ms Intel recommends using the PECI output reading f
56. rPGA988A Processor Pin List by Pin Name List by Pin Name Buffer SA 4 EN SB DDR3 O SA MA 5 SB 1 DDR3 SA 8 SB_DQ 4 DDR3 I O SA MA 9 SB 5 DDR3 SA MA 10 D4 DDR3 SB_DQ 6 DDR3 1 0 SA MA 11 SB DQI7 DDR3 1 0 SA_MA 12 DDR3 SB DQI8 DDR3 1 0 SA MA 13 G DDR3 SB 9 DDR3 1 0 SA MA 14 DDR3 SB DQ 10 DDR3 O SA MA 15 DDR3 SB 11 DDR3 SA D DDR3 SB DQ 12 DDR3 O SA ODTI1 F DDR3 SB DQ 13 DDR3 1 0 SA_RAS B DDR3 SB DQ 14 DDR3 O SA E DDR3 SB 15 DDR3 SB BS 0 B DDR3 SB DQ 16 DDR3 1 0 SB_BS 1 w DDR3 SB DQ 17 DDR3 1 0 SB 5 2 DDR3 SB DQ 18 DDR3 I O SB_CAS C DDR3 SB 19 DDR3 1 0 SB CK 0 ws DDR3 SB_DQ 20 DDR3 I O SB_CK 1 DDR3 SB_DQ 21 DDR3 1 0 SB_CK 0 DDR3 SB_DQ 22 DDR3 I O SB_CK 1 DDR3 SB_DQ 23 DDR3 1 0 SB_CKE 0 DDR3 SB_DQ 24 DDR3 O SB_CKE 1 DDR3 SB_DQ 25 DDR3 SB_CS 0 B8 DDR3 SB_DQ 26 DDR3 O SB_CS 1 D6 DDR3 SB_DQ 27 DDR3 SB_DM 0 D4 DDR3 SB_DQ 28 DDR3 O SB_DM 1 DDR3 SB_DQ 29 DDR3 SB_DM 2 DDR3 SB DQI30 DDR3 1 0 SB DMI 3 DDR3 SB 31 DDR3 1 0 SB_DM 4 DDR3 SB_DQ 32 AF3 DDR3 1 0 SB_DM 5 AL2 SB DQ 33 1 DDR3 1 0 SB DM 6 ARA DDR3 SB DQI 34 DDR3 1 0 SB DMI 7 AT8 DDR3 SB DQ 35 AK1 DDR3 1 0 129 Datasheet e Processor Pin and Signal I nformation I n tel Table 8 49 rPGA988A Processor Pi
57. remain LOW while any reset is active until the BIOS writes to a configuration register Using this method CKE is guaranteed to remain inactive for much longer than the specified 200 micro seconds after power and clocks to SDRAM devices are stable Conditional Self Refresh The processor conditionally places memory into self refresh in the package C3 and C6 low power states When entering the Suspend to RAM STR state the processor core flushes pending cycles and then enters all SDRAM ranks into self refresh In STR the CKE signals remain LOW so the SDRAM devices perform self refresh The target behavior is to enter self refresh for the package and states as long as there are no memory requests to service The target usage is shown in Table 4 16 49 i n tel I Power Management Table 4 16 Targeted Memory State Conditions Mode Memory State with I nternal Graphics Memory State with External Graphics CO C1 CIE Dynamic memory rank power down based on Dynamic memory rank power down based on idle conditions idle conditions C3 C6 If the internal graphics engine is idle and there If there are no memory requests then enter are no pending display requests when in single self refresh Otherwise use dynamic memory display mode then enter self refresh rank power down based on idle conditions Otherwise use dynamic memory rank power down based on idle conditions Self Refresh Mode Self Refresh Mode Memory
58. the graphics driver and processor core will adjust their Intel Turbo Boost Technology performance dynamically to stay within the limit Note The processor PECI pin must be connected to the PCH PECI pin in order for Intel Turbo Boost Technology to properly function Datasheet 57 i n tel gt Thermal Management 5 2 5 2 1 Caution 5 2 1 1 58 Component Power Measurement Estimation Error The processor input pin ISENSE informs the processor core of how much amperage the processor core is consuming This information is provided by the processor core VR The process will calculate its current power based upon the ISENSE input information and current voltage state The internal graphics and memory controller power is estimated by the GFX driver using PMON Any error in power estimation or measurement may limit or completely eliminate the performance benefit of Intel Turbo Boost Technology When a power limit is reached Power sharing control will adaptively remove Intel Turbo Boost Technology states to remain with the MCP thermal power limit Power sharing control assumes the power error is always accurate so if the ISENSE input reports power greater than the actual power control mechanisms will lower performance before the actual TDP power limit is reached Intelligent Power sharing will provide better overall Intel Turbo Boost Technology performance with increasing VR current sense accuracy Designers and system manufacturers sho
59. 011 3 JLVYLSANS g vua 11 12 1 303 3 38 48134039 131113 11128434080 401 5 55 99728 Xr sex 1H9 3H LN3NOdMOJ 318VAO1V L O ANO ISN IWIYILYN NY 183404402 TINI 804 3 83538 1 V3WV SIHI NOIIVNOdNO 131N 40 LN3SNOO NILLIYM 3 LNOHLIM 031 3100 YO 034 14510 03200084384 035012510 38 LON AVN S1N31N05 SLI NV 35N30 3NOD NI 435012510 SI 11 NOIIVMNOJNI 1VI1N3013NOD NOI1VNOdNOD TALNI SNIVINOD ONIMVYO STHL 610953 S 8 181 Datasheet
60. 3 3 SA DQ 2 EIE SA DQ 27 1 MS em o 202 s SA 2 SA post sA 54 2 3 SA 16 SA 008 2 comp _ 21 MEM SA_DO 17 1 SA DQ 9 SA DM 2 lt n O 5 2 SA 1 106 Datasheet Processor Pin and Signal I nformation intel Figure 8 18 Socket G rPGA988A Top View Upper Right Quadrant VSSAXG_SE NSE VAXG_SEN SE GFX VID 3 GFX VID 1 GFX VID 2 GFX VID 4 GFX VID 0 vss 0 Datasheet VAXG SA_DQ 59 SA_DQS vss SA DQ 6 SA DGS 2 7 MS 94 poro TS 1 3 Vi ele DM 7 0 GOOD 1 EM 00 5 8 PM RSTIN SA DQ 61 1 THERM TR CATERR SM_DRA IP MPWROK 107 n e Processor Pin and Signal I nformation Figure 8 19 Socket G rPGA988A Pinmap Top View Lower Left Quadrant vss vss VCC vcc vcc vcc vss vss vss Nee VSS x EO 25 hs ig i EG_TX 10 is 4 PEG_TX PEG_TX PEG_TX PEG_TX 151 151 18 8 uiu vss X PEG TX PEG TX vs 113 13 114 TX PEG TX PEG TX 55 7 55 14 1151 151 VTT1 vs N x 108 Datasheet m Processor Pin and Signal I nformation n tel Figure 8 20 Socket G rPGA988A Top View Lower Right Quadrant
61. 3 2 5 2 1 3 3 5 2 1 3 4 5 2 1 4 Datasheet Voltage Regulator Protection PROCHOT may be used for thermal protection of voltage regulators VR System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached By asserting PROCHOT pulled low and activating the TCC the VR will cool down as a result of reduced processor power consumption Bi directional PROCHOT can allow VR thermal designs to target thermal design current instead of maximum current Systems should still provide proper cooling for the VR and rely on bi directional PROCHOT only as a backup in case of system cooling failure Overall the system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP Thermal Solution Design and PROCHOT Behavior With a properly designed and characterized thermal solution it is anticipated that PROCHOT will only be asserted for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable However an under designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may 9 Cause a noticeable performance loss Result in prolonged operatio
62. 3 Dual Channel Symmetric Interleaved and Dual Channel Asymmetric Modes 23 Figure 2 4 PCI Express Layering Diagram mme 25 Figure 2 5 Packet Flow through the Layers r mmm 26 Figure 2 6 PCI Express Related Register Structures the 27 Figure 2 7 Integrated Graphics Controller Unit Block 29 Figure 2 8 Processor Display Block 32 Figure 4 9 Idle Power Management Breakdown of the Processor 42 Figure 4 10 Thread and Core C State Entry and 42 Figure 4 11 Package C State Entry and 47 Figure 5 12 Frequency and Voltage mmm 60 Figure 7 13 Active Vcc and Icc Loadline PSI Asserted 97 Figure 7 14 Active Vcc and Loadline PSI Not Asserted 97 Figure 7 15 VAXG IAXG Static and Ripple Voltage Regulation 99 Figure 7 16 Input Device 1 104 Figure 8 17 Socket G rPGA988A Pinmap Top View Upper Left Quadrant 106 Figure
63. 33 PSI Async CMOS AN35 ISENSE AP1 RSVD_NCTF P2 A VSS GND 1 0 lt lt Table 8 48 rPGA988A Processor Pin List by Pin Number lt 5 G G SB_DQS 6 LHe e ee 18 sis sls sls 55 5 5 AP5 AP6 AP7 AP8 AP9 AP11 SA_DQS 6 DDR3 AP12 SA_DQ 55 DDR3 5 5 5 5 5 5 5 5 5 AP14 SA_DQ 63 DDR3 AP15 PM_EXT_TS 1 CMOS 13 V 2 wee N N N N N E N E E N E AP21 VAXG 26 RESET OBS Async CMOS 27 PREQ Async GTL AP29 TDO M CMOS AP30 RSVD 1 2 2 RSVD RSVD 35 RSVD NCTF lt 115 n tel Processor Pin and Signal I nformation Table 8 48 rPGA988A Processor Pin Table 8 48 rPGA988A Processor Pin List by Pin Number List by Pin Number Buffer Buffer Type Type AR1 RSVD NCTF 2 RSVD TP AR2 RSVD NCTF RSVD NCTF VSS GND AT4 SB_DQ 50 DDR3 1 0 AR4 SB_DM 6 DDR3 AT5 SB_DQ 54 DDR3 1 0 5 SB 54 6 DDR3 1 0 6 SB DQ 55 DDR3 1 0 AR VSS N AT7 SB DQI60 DDR3 1 0 AR SB_DQS 7 DDR3 1 0 AT8 SB_DM 7 DDR3 AR SB_DQS 7 DDR3 1 0 AT SB_DQ 59 DDR3 1 0 AR VSS N AT10 SB_DQ 63 DDR3 1 0 AR10 SB_DQ 62 DDR3 1 0 AT11 SA_DQ 54 DDR3 1 0 AR11 SA_DQ 50 DDR3 1 0 AT12 SA DQI60 DDR3 1 0 AR12 N AT13 SA_DQS I7 DDR3 1 0 AR13 SA 7
64. 88A Processor Pin List by Pin Number List by Pin Number Buffer Buffer Type Type VSS GND 58 0914 DDR3 1 0 SB DMI O DDR3 E5 GND SB DQS 0 DDR3 1 0 SA DQ 10 DDR3 1 0 GND SA DQ 14 DDR3 1 0 SA DMI1 DDR3 VSS GND SA DQI8 DDR3 1 0 SA DQ 12 DDR3 1 0 vss N E10 SA_DQI6 DDR3 1 0 SA_DQ 5 DDR3 1 0 11 VSS N VTTO E El VTTO E VTTO E El vss GN VTTO E E1 VTTO E RE 1 RSVD TP RSVD DIFF M ee te PEG_CLK DIFF CLK FDI_FSYNC 1 CMOS FDI_LSYNC 1 CMOS 1 vss N FDI_TX 3 FD El FDI_TX 5 FD FDI_TX 2 FD E2 FDI_TX 5 D D E21 VSS N M E2 VSS N M E2 a Es em VSS E2 E2 E2 VSS qe _ E3 VSS E33 E34 E35 VSS GND 118 Datasheet intel Table 8 48 rPGA988A Processor Pin List by Pin Number Buffer Type F5 F6 F7 F8 F9 F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 F2 F2 F2 F2 F2 F2 F2 F2 F2 F2 F3 F3 F3 F33 F34 F35 G1 G2 G3 119 SB_DQ 13 DDR3 1 0 SM_DRAMRST DDR3 SA_DQ 11 DDR3 1 0 SA_DQS 1 DDR3 1 0 SA_DQS 1 DDR3 1 0 SA_DQ 9 DDR3 1 0 VTTO E VTTO E VTTO E VTTO E _ VSS N VSS N 5 5 VSS N a VSS VSS SB 20 1 0 SB_DQ 17 1 0 VSS GND SB_DQ 15 1 0 SB_DQ 21 1 0 Processor Pin and Signal Information Table 8 48 rPGA988A Processor Pin List by Pin Number Buffer Type VSS GND GND E VTTO E VTTO E VTTO E VIT SELECT CMOS FDI_TX 7 D FDI_TX
65. A DQI 31 BG25 DDR SA DQI 32 BJ40 DDR SA DQI 33 BM43 DDR SA DQ 34 BF47 DDR SA DQ 35 48 DDR SA DQI 36 40 DDR SA DQI 37 BH43 DDR SA_DQ 38 BN44 DDR SA_DQ 39 BN47 DDR SA_DQ 40 BN48 DDR SA_DQ 41 BN51 DDR SA_DQ 42 BH53 DDR SA_DQ 43 55 DDR SA DQ 44 48 DDR SA DQ 45 48 DDR SA DQ 46 BM53 DDR SA DQ 47 BN55 DDR SA DQ 48 BF55 DDR SA DQ 49 BN57 DDR SA DQ 50 BN65 DDR SA DQ 51 BJ61 DDR SA DQ 52 BF57 DDR SA DQ 53 BJ57 DDR SA DQ 54 BK64 DDR UJ SA DQ 55 BK61 DDR SA DQ 56 63 DDR SA DQ 57 BF64 DDR SA 58 BB64 DDR SA 59 BB66 DDR SA DQ 60 66 DDR SA DQ 61 BF65 DDR SA 62 AY64 DDR SA DQI63 BC70 DDR SA 5 1 DDR SA DQSI 2 BL13 DDR SA DQSI 3 BN21 DDR SA 5 4 BK44 DDR SA_DQS 5 BH51 DDR SA_DQS 6 BM60 DDR SA 5 7 64 DDR SA DQS 0 DDR SA DQS 1 BJ7 DDR SA 54 2 BN13 DDR SA DQS 3 BL21 DDR SA 005 4 BH44 DDR SA DQS 5 BK51 DDR SA DQS 6 BP58 DDR SA 005 7 BE62 DDR SA MA 0 BT36 DDR SA MA 1 BP33 DDR SA 2 BV36 DDR SA MAL3 BG34 DDR SA MA 4 BG32 DDR SA MA 5 BN32 DDR SA MA 6 BK32 DDR SA MAL7 BJ30 DDR SA 8 BN30 DDR SA MA 9 BF28 DDR SA MA 10 BH34 DDR3 UJ 5 lt lt lt lt O O O lt lt lt lt I
66. A1288 Processor Ball List by Ball Number Sheet 10 of 37 omm AL71 GFX DPRSLPVR CMOS CFG 1 CMOS SM DRAMPWROK Async CMOS VCCPWRGOOD 1 Async CMOS lt 5 ws pee AM67 GFX VID 5 CMOS 70 GFX VID 6 CMOS AN1 VTT SELECT CMOS O 2 m VTTO O AM2 AM5 AM7 AM8 VSS ANA VSS AN5 VSS AN7 AN9 VTT AN12 N N E E E E E E E E E E E E E ae REF z 2 164 165 Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 11 of 37 Dm VSS VCAPO VSS VCAP0 VTTO VTTO VSS RSVD ND C io AR14 hs ee pss fo pss Lee 985 f i f gt m T 7 Z AR21 LN wer vs w ma vs was pen La Processor Pin and Signal nformation Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 12 of 37 mw vem VSS VCAP0 VSS VCAP0 en VITO VTTO 5 we mm mem Ew ees owes 1 pus mo m o wu evo a war 8 _ ans vs NO _ ane ws s 28 Mme 98 Datasheet Processor Pin and Signal I nformation Datasheet Table 8 51 BGA1288 Processor Ball List by Ball
67. AB37 AB39 EH p ser Processor Pin and Signal I nformation Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 4 of 37 men ve we 42 VSS VCC VSS VCC VSS VCC VSS VCC VSS mi 2 2 ojm ojn 0 al a 79 lt lt gt gt NIN oi ejes pee _ _ _ mer mms s mon wwe mom _ GND CMOS CMOS AC10 GND GND GND gt 5 8 2 p p p gt gt gt gt O O O O o S Datasheet Processor Pin and Signal I nformation Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 5 of 37 AD26 AD28 AD30 AD32 AD33 AD35 AD37 AD39 AD41 AD42 AD44 AD46 AD48 AD50 AD51 AD53 AD55 AD57 AD59 AD60 AD62 VAXG 1 VSS Datasheet Buffer Type REF REF REF REF REF REF REF REF REF REF REF REF REF Analo Analo CMO vl zl eo O z z z z n oj gt O 9 8 O z CMO Analo Analog REF REF REF REF REF olol 5 2 2 9 Table 8 51 BGA1288 Processor Ball List by Ball Numb
68. B addresses where any of Bits 63 36 are Datasheet Features Summary intel 1 3 3 Datasheet non zero with an Unsupported Request response Upstream write transactions to addresses above 64 GB will be dropped Re issues configuration cycles that have been previously completed with the Configuration Retry status PCI Express reference clock is 100 MHz differential clock buffered out of system clock generator Power Management Event PME functions Static lane numbering reversal Does not support dynamic lane reversal as defined optional by the PCI Express Base Specification PCI Express 1x16 configuration Normal 1x16 PEG RX 15 0 PEG TX 15 0 Reversal 1x16 PEG RX 0 15 PEG TX 0 15 Supports Half Swing low power low voltage mode Message Signaled Interrupt MSI and MSI X messages PEG Lanes shared with Embedded DisplayPort see eDP Section 1 3 6 Polarity inversion Direct Media Interface DMI Compliant to Direct Media Interface second generation DMI 2 Four lanes in each direction 2 5 GT s point to point DMI interface to PCH is supported Raw bit rate on the data pins of 2 5 Gb s resulting in a real bandwidth per pair of 250 MB s given the 8b 10b encoding used to transmit data across this interface Does not account for packet overhead and link maintenance Maximum theoretical bandwidth on interface of 1 GB s in each direction simultaneously for an aggregate of 2 GB s when DMI x4 Share
69. Celeron P4000 and 03000 mobile processor series is available is available on 37 5 x 37 5 mm rPGA package rPGA988A Standard Voltage only A 34 x 28 mm BGA package BGA1288 Ultra Low voltage only Datasheet Features Summary intel 1 7 Terminology Block Level Transfer DDR3 Third generation Double Data Rate SDRAM memory technology DisplayPort Direct Memory Access pec Direct Media Interface Enhanced Intel Technology that provides power management capabilities to laptops SpeedStep amp Technology Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system See the Intel 64 and 32 Architectures Software Developer s Manuals for more detailed information Legacy component Graphics Memory Controller Hub Graphics Processing Unit The legacy 1 Controller Hub component that contains the main PCI interface LPC interface USB2 Serial and other I O functions It communicates with the legacy G MCH over a proprietary interconnect called DMI LVDS Low Voltage Differential Signaling A high speed low power data transmission standard used fo
70. DDR3 1 0 AT14 SA DQI 59 DDR3 1 0 AR14 SA 62 DDR3 1 0 AT15 PECI 1 0 AR15 VSS N AT16 VAXG E AR16 AT17 VSS N AR17 18 VAXG E AR18 VAXG AT19 VAXG E AR19 AT20 VSS GN AR20 AT21 VAXG E Hor ARIS N AR24 vss N ARDS a AR26 53 N AR27 TDO 2 AT28 PRDY Async AR30 BCLK_ITP DIFF AR31 VSS GN AT31 RSVD EE AR32 RSVD 32 RSVD AR33 RSVD AT33 1 VSS 116 Datasheet Processor Pin and Signal I nformation Datasheet Table 8 48 rPGA988A Processor Pin List by Pin Number amp VSS GND VSS GND VSS N 1 VSS GN 1 VTTO E 1 VSS GN 1 VTTO E s CLK B1 VSS N B1 VSS GN B2 VSS GN B2 DMI_RX 2 DM B2 DMI_RX 2 M B2 DMI RX 0 M B2 VSS N B2 PEG_ICOMPI B2 PEG_RCOMPO B28 PEG RX4 13 B29 PEG RX 14 B30 PEG RX4 14 B31 VSS GND B32 PEG RX4 11 B33 PEG RX 9 B34 VSS NCTF B35 RSVD NCTF 1 Table 8 48 rPGA988A Processor Pin List by Pin Number Type DDR3 1 0 DDR3 1 0 DDR3 1 0 DDR3 1 0 DDR3 1 0 DDR3 1 0 DDR3 1 0 recor NN LENS e NEN NEN DMI_RX 1 PEG_TX 15 PEG RX 12 PEG RX4 12 PEG RX4 9 RSVD NCTF SB 8 DDR3 SB 9 117 n tel Processor Pin and Signal I nformation Table 8 48 rPGA988A Processor Pin Table 8 48 rPGA9
71. EN 76 6 6 Intel Flexible Display Interface 0 76 Datasheet Datasheet VEI pe 77 77 6 9 TAR SIGH AMS uses ETT 78 6 10 Error and Thermal Protection 79 6 11 lt 2 a bonia de AR EUER 80 6 12 Processor Power 5 t kadna nnne nn nn nn nnn nnn 81 6 13 Ground and AG RIP Ra Rd DR PR Y Mong eae OR 83 6 14 Processor Internal Pull Up Pull Down r menm nnns 83 7 Electrical 6 85 7 1 JPower and Ground PINS ee or un ense dre Roe Rc ef e ROLES Rd RR E CER 85 7 2 Decoupling G ldellries u eint retient e KIA E LARA 85 7 2 1 Voltage Rail 0 ne 85 7 3 Processor Clocking BCLK BCLK recens nennt peser ee inel da 85 7 3 1 MPLE Power Supply s eene eh n Saca caben Sont aypa 86 7 4 Voltage Identification VID 2 1 1 4 4 441 1 01 4 4 1 4 4 4 nns 86 7 5 R
72. FX VID 3 AH71 CMOS 2 5 E o PEG RX 6 PEG RX 7 PEG RX 8 PEG RX 9 PEG RX 10 PEG RX 11 PEG RX 12 PEG RX 13 PEG RX 14 PEG RX 15 B19 18 B16 015 PEG RX4 0 G40 PEG RX4 1 638 Pcie H34 P34 628 H25 D12 138 634 M34 128 PEG RX 5 625 Pcie Q4 828 27 825 24 B21 B21 v Q Cle Cle Cle Cle Cle v aja v Q D B12 13 D12 F40 38 34 34 28 25 K24 B28 27 B25 24 B19 B18 B16 D15 40 38 H34 P34 28 H25 H24 143 Datasheet e Processor Pin and Signal I nformation I n tel Table 8 50 BGA1288 Processor Ball Table 8 50 BGA1288 Processor Ball List by Ball Name List by Ball Name Sheet 5 of 37 Sheet 6 of 37 Buffer Type PCIe TX4 11 128 Pcie TX4 12 KN 521 PEG_RX 7 PEG_RX 8 PCle PEG_RX 9 PCle PEG_TX 13 M PEG_RX 10 PCle PEG_TX 14 G21 PM_EXT_TS 0 Aves cmos 1 0 PM_EXT_TS 1 AV64 cmos 1 0 PRDY U71 Async GTL 6 4 PEG RX 11 PCIe PREQ U69 Async 1 7 0 PEG_RX 12 PCle PEG_RX 13 PCle PEG_RX 14 PCle PEG_RX 15 PCle PEG TX 0 PCle PEG TX 1 PCle TX 2 PCle N38 TX 3 B39 PCle H32 GTL
73. ID 4 CMOS VSS GND CSC O VID 3 CMOS SM_RCOMP 1 VSS GND SB DQ 47 DDR3 AM5 VSS GND I O 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Processor Pin and Signal Information Table 8 48 rPGA988A Processor Pin List by Pin Number Buffer Type AM6 SB_DQ 42 DDR3 1 0 AM7 SA_DM 5 DDR3 AM8 VSS GND AM9 SA DQ 52 DDR3 1 0 AM10 SA_DQ 49 DDR3 1 0 11 VSS GND AM12 SA DQ 56 DDR3 1 0 AM13 SA_DQ 58 DDR3 1 0 AM14 VSS GN CMOS AM17 VSS N AM20 VSS N AM26 TAPPWRGOOD Async CMOS AM27 VSS N AM28 CFG 1 CMOS AM30 CFG 0 CMOS AM31 CFG 5 CMOS AM32 CFG 7 CMOS AM33 CSC 2 VID 5 CMOS I O AM34 PROC_DPRSLPV CMOS R AM35 viDI6 CMOS 1 SM RCOMP 2 AN2 SB DQ 43 DDR3 1 0 SB 00153 1 0 AN4 SB_DQ 52 1 0 Datasheet Processor Pin and Signal I nformation Datasheet Table 8 48 rPGA988A Processor Pin List by Pin Number Buffer Type AN6 SB DQ 51 DDR3 I O AN7 SB DQ 56 DDR3 1 0 AN8 SA_DQ 48 DDR3 1 0 SA DQI 53 DDR3 1 0 10 SA DMI6 DDR3 AN11 SA DQS 6 DDR3 1 0 AN12 SA_DQ 57 DDR3 1 0 DDR3 AN13 SA DMI 7 AN14 VCCPWRGOOD Async 1 5 15 EXT 54 0 5 AN16 VAXG AN18 VAXG AN19 VAXG REF N lt O lt 5 5 AN22 GFX VIDI2 AN24 VIDI6 AN25 DBR K S AN26 PROCHOT Async GTL AN27 VCCPWRGOOD Async 0 CMOS AN29 CFG 6 AN30 CFG 12 AN32 CFG 13 AN
74. IP pin 5 em Asynchronous 1 0 Asynchronous GTL Asynchronous 1 0 GTL 1 0 79 n tel I Signal Description 6 11 Power Sequencing Table 6 31 Power Sequencing Type VCCPWRGOOD_0 VCCPWRGOOD 0 and VCCPWRGOOD 1 VCCPWRGOOD 1 Power Good Processor Input The Asynchronous CMOS processor requires these signals to be a clean indication that VCC VCCPLL and VTT supplies are stable and within their specifications BCLK is stable and has been running for a minimum number of cycles Both signals must then transition monotonically to a high state VCCPWRGOOD 0 and VCCPWRGOOD 1 can be driven inactive at any time but BCLK and power must again be stable before a subsequent rising edge of these signals VCCPWRGOOD 0 and VCCPWRGOOD 1 should be tied together and connected to the PROCPWRGD output signal of the PCH SM DRAMPWROK SM DRAMPWROK Processor Input Connects to DRAMPWROK Asynchronous CMOS VITPWRGOOD VTTPWRGOOD Processor nput processor requires this input signal to be Asynchronous CMOS clean indication that the VTT power supply is stable and within specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state Note it is not valid for VTTPWRGOOD to be deasserted wh
75. K3 VSS M3 K3 PEG RX4 0 M31 1 VDDQ E M3 L2 VSS N M3 L3 SB 26 DDR3 1 0 M3 4 SB DQS 3 DDR3 1 0 M3 L5 VSS N N1 L6 SA 28 DDR3 1 0 N2 L7 SA DQI24 DDR3 1 0 N3 L8 VSS N VDDQ E 19 SA DQI27 DDR3 1 0 SB 31 DDR3 1 0 L1 VTTO E VSS N L2 VCCPLL E VDDQ E SB MA 15 DDR3 wm L2 L2 L2 L3 L3 L32 L33 L34 L35 1 2 M3 4 VCCPLL E VSS VSS SB DQI27 1 0 SB_DQ 30 1 0 SA_DQ 30 1 0 VTTO E VSS N VSS N vss vss VSS VSS vss vss VSS VSS Datasheet m 8 Processor Pin and Signal I nformation I n tel Table 8 48 rPGA988A Processor Pin Table 8 48 rPGA988A Processor Pin List by Pin Number List by Pin Number GND SB MA 14 DDR3 SA CKE 1 DDR3 SA 01 DDR3 VSS N SA MA 7 SA MA 11 DDR3 SA MA 14 DDR3 VDDQ VDDQ SB MA 5 DDR3 RSVD T2 E E T3 SB MA 4 DDR3 SB MA 6 DDR3 SB MA 12 DDR3 SB MA 8 DDR3 SB MA 9 DDR3 SB MA 7 DDR3 SB BS 2 DDR3 7 1 VSS GN VCC REF U10 VCC REF REF U27 VDDQ SA_MA 12 DDR3 SB MA 0 DDR3 SA MA 9 DDR3 SA BS 2 DDR3 RSVD Datasheet 122 n tel Processor Pin and Signal I nformation Table 8 48 rPGA988A Processor Pin Table 8 48 rPGA988A Processor Pin List by Pin Number List by Pin Number u Type Type U29 VCC U30 VCC VSS U31 VCC VSS U3 VSS VCC vss VCC VSS VCC E VSS SA MA 4 DDR3 VSS SB MA 1 DDR3 SB MA 3
76. PEG port is being designed to be compliant with the PCI Express Base Specification Revision 2 0 27 intel 2 2 3 1 2 2 3 2 2 3 Note 2 3 1 2 3 2 2 3 3 28 Interfaces PCI Express Bifurcated Mode When bifurcated the signals which had previously been assigned to Lanes 15 8 of the single x16 Primary port are reassigned to lanes 7 0 of the x8 Secondary Port This assignment applies whether the lane numbering is reversed or not PCI Express Port 0 is mapped to PCI Device 1 and PCI Express Port 1 is mapped to PCI Device 6 Static Lane Numbering Reversal Does not support dynamic lane reversal as defined optional by the PCI Express Base Specification PCI Express 1x16 configuration e Normal 1x16 PEG RX 15 0 PEG TX 15 0 Reversal 1x16 RX 0 15 PEG TX 0 15 DMI DMI connects the processor and the PCH chip to chip DMI2 is supported The DMI is similar to a four lane PCI Express supporting up to 1 GB s of bandwidth in each direction Only DMI x4 configuration is supported DMI Error Flow DMI can only generate SERR in response to errors never SCI SMI MSI PCI INT or GPE Any DMI related SERR activity is associated with Device O Processor PCH Compatibility Assumptions The processor is compatible with the PCH and is not compatible with any previous G MCH or ICH products DMI Link Down The DMI link going down is a fatal unrecoverable error If the DMI data link goes to data l
77. PEG_RX 11 VSS 026 PEG_RX 9 27 vss 29 PEG_RX 7 31 vss PEG TX 10 VSS TX 7 VSS DC TEST E1 aM RSVD NCTF us ws 98 V V V Datasheet Processor Pin and Signal I nformation Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 29 of 37 Buffer Type E71 DC TEST E71 RSVD NCTF DMI_RX 0 DMI_RX 0 DMI_TX 3 F21 PEG_TX 14 PCle PEG RX 0 VSS SENSE Analo VCC SENSE Analo PROC DPRSLPVR CMO PSI RSTIN F71 CMO G21 PEG 141 PEG RX 5 PEG RXz 4 PCIe o o o 2 z 5 lt 2 z z O z 2 2 2 gt a 8 8 5 Datasheet Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 30 of 37 c es me d E 8 UL LEN E o a lt Z O 2 O z z G51 O 2 eo K Async CMOS DMI_TX 0 cle 9 ar fe Ms ws s VTTPWRGOOD H17 v Q 2 2 51 ND I DMI TX 3 ow mcer wes mw mers ow ow xu mw meni 174 175 ntel Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 31 of 37 im pee ae PEG CLK DIFF CLK PEG RX 4 PCle Us meras see
78. Performance Modulation Technology GPMT is a method for optimizing the power efficiency in the graphics render engine while continuing to render 3D objects during battery operation The GPMT feature will dynamically switch the render frequency based on the render workload on power policy skew and environmental conditions Intel Smart 2D Display Technology Intel S2DDT Intel S2DDT reduces display refresh memory traffic by reducing memory reads required for display refresh Power consumption is reduced by less accesses to the IMC Intel S2DDT is most effective with Display images well suited to compression such as text windows slide shows etc Poor examples are 3D games e Static screens such as screens with significant portions of the background showing 2D applications CPU benchmarks etc or conditions when the CPU is idle Poor examples are full screen 3D games and benchmarks that flip the display image at or near display refresh rates 51 4 7 Thermal Power Management See Section 5 Thermal Management on page 53 for all graphics thermal power management related features 52 Datasheet Thermal Management l n tel Caution ou 5 1 1 Datasheet Thermal Management A multi chip package MCP processor requires a thermal solution to maintain temperatures of the processor core and graphics memory core within operating limits A complete thermal solution provides both the component level and the system le
79. R SB DQ 57 DDR SB 00158 DDR SB DQ 59 DDR SB DQ 60 SB DQ 61 SB DQ 62 AR10 DDR SB DQ 63 AT10 DDR SB DQSIO DDR SB 5 1 DDR SB 5 2 DDR SB 5 3 5 DDR G2 lt lt lt lt lt lt SB_DQS 4 DDR SB_DQS 5 DDR SB DQSI6 DDR SB_DQS 7 DDR SM_RCOMP 1 SM_RCOMP 2 TAPPWRGOOD AM26 Async CMOS 05 F4 J4 L4 AH2 AL4 AR5 AR8 U5 v2 T5 v3 R1 T8 R2 R4 R5 AB5 P3 R3 AF7 P5 N1 AC7 AD1 Y7 AC6 F6 AL1 AM1 AN1 G4 G3 4 AK3 AKA M6 AN2 AK5 AK2 M4 M3 5 6 ANA AN3 5 6 7 6 9 AT7 AP9 C5 E3 H4 M5 G2 15 5 7 O 5 5 w Ww Wy Ww W W 2 W 2 W 2 W UJ Datasheet 130 131 Table 8 49 rPGA988A Processor Pin List by Pin Name TCK TDI TDI M TDO TDO M THERMTRIP TMS TRST VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG Se Type 15 16 AK16 REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF EF P p gt WO gt 2
80. SA 5 SB DA SA SA SA SB_BS SB_MA SB_MAI SB_MAI SB_MA SB_MAI SB_ 2 71 1 12 61 41 CK S 5 od n EX SB SB 54131 I7 Ps EN SA DQ DMI sA SB_DQ QI SB_CKE SB_CKEISB_DQI 553 26 3l 25 513 30 0 n 27 SA Del _DQI SA_DQ SB DQ SB 28 S4 3 26 i oi Isa SA DQ sA 5 por sB 01 5 por 5 0 5 por SB DQ 31 S 2 22 18 S 2 19 22 SA_DQI 5 SA 5 DQI SB DQ sB E ISA SA DQ SA DQ SB gt 1 201 21 SM DR sa el SA 5 5 por AMRST SB_DQ SB 0 5 58 a sp 54111 13 5 111 141 5 zel SA DQI SA DQI SA T 55 SB_DQ SB_DM 14 iU 5111 11 SA qu SB DQ Dor S 0 0 9 SA DQI SA DQ SA polsA 5 58 Do 5 _ SB_ ane SB D 1 54101 10 151 5101 121 VIT SE SA sa SA DQI SB DQI vss NC vss DPLL R VSS_SE Datasheet 109 Processor Pin and Signal I nformation Datasheet Table 8 48 rPGA988A Processor Pin List by Pin Number Buffer Type A3 A4 A5 A6 A7 A8 9 A10 A11 A12 A1 A1 A15 1 1 18 19 20 21 22 23 24 25 26 27 28 29 0 RSVD SB DQ 6 DDR3 SB DQ 1 DDR3 SB 5 DDR3 SA 3 DDR3 SA DQ 7 DDR3 VSS ND SA_DQ 0 DDR3 VTTO EF VTTO EF VTTO E VTTO RE VSS_SENSE_VT Ana
81. Short averaging times will make the averaged temperature values respond more quickly to DTS changes Long averaging times will result in better overall thermal smoothing but also incur a larger time lag between fast DTS temperature changes and the value read via PECI Within the processor the DTS converts an analog signal into a digital value representing the temperature relative to PROCHOT circuit activation The conversions are in integers with each single number change corresponding to approximately 1 C DTS values reported via the internal processor MSR will be in whole integers As a result of the PECI averaging function described above DTS values reported over PECI will include a 6 bit fractional value Under typical operating conditions where the temperature is close to PROCHOT the fractional values may not be of interest But when the temperature approaches zero the fractional values can be used to detect the activation of the PROCHOT circuit An averaged temperature value between 0 and 1 can only occur if the PROCHOT circuit has been activated during the averaging window As PROCHOT circuit activation time increases the fractional value will approach zero Fan control circuits can detect this situation and take appropriate action as determined by the system designers Of course fan control chips can also monitor the PROCHOT pin to detect PROCHOT circuit activation via a dedicated input on the package 69 Signal Descr
82. Suspend to RAM Gp ecept RTC Suspend to Disk S uy Off except RTC Soft Off Table 4 12 D S and C State Combination 4 2 40 Graphics Adapter C1 C1E Auto Halt Displaying Deep sleep Displaying Not displaying Not displaying Graphics Core is powered off Not displaying suspend to disk Processor Core Power Management CO C3 C6 Any N A N A _ Displaying 5 s Aw _ _ oS While executing code Enhanced Intel SpeedStep Technology optimizes the processor s frequency and core voltage based on workload Each frequency and voltage operating point is defined by ACPI as a P state When the processor is not executing code it is idle A low power idle state is defined by ACPI as a C state In general lower power C states have longer entry and exit latencies Datasheet Power Management l n tel j 4 2 1 Enhanced Intel SpeedStep Technology The following are the key features of Enhanced Intel SpeedStep Technology e Multiple frequency and voltage points for optimal performance and power efficiency These operating points are known as P states e Frequency selection is software controlled by writing to processor MSRs The voltage is optimized based on the selected frequency and the number of active processor cores If the target frequency is higher than the current frequency Vcc is ramped up in s
83. TTO REF VTTO REF VIT REF VITO REF VITO REF RE VITO REF VIT RE VTTO RE vito HE VITO RE 0 RE VITO RE vito _ RE RE i RE REF RE RE RE RE RE R23 RE RE R24 RE RE R26 E RE R28 E R15 E R30 E R17 E R32 E R19 E R33 EF RER R35 REF U23 EF REF U24 REF U28 PP U30 159 Datasheet Processor Pin and Signal I nformation Datasheet Table 8 50 BGA1288 Processor Ball List by Ball Name Sheet 37 of 37 wz Wa ws kuwa mo im Z N P VITPWRGOOD E Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 1 of 37 Buffer Type DC TEST A5 RSVD NCTF SN SN 10 Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 2 of 37 vss LEN m messa Desr Peran i ws 160 161 ntel Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 3 of 37 42 VSS AA44 VCC AA VSS 48 VCC 50 VSS 5 VSS 5 57 lt lt ojo P gt gt v NIN s 8 Di d Z RSVD RSVD TP LSYNC 1 CMOS FDI INT CMOS CFG 17 CMOS hs we e fe ee a fe wo ee_ hs me Z AB12 AB17 G ojo a O Z AB35
84. Table 7 45 PCI Express DC Specifications Symbol panies Parameter VTX DIFF p p a Differential Peak to Peak Tx Voltage Swing Tx AC Peak Common Mode Output Voltage Gen 1 Only ZTX DIFF DC a DC Differential Tx Impedance Gen 1 Only DC Common Mode Rx Impedance ZRX DIFF DC a DC Differential Rx Impedance Gen1 Only Differential Rx Input Peak to Peak i a Voltage Gen 1 only Rx AC Peak Common Mode Input Voltage x d d d c c c c NOTES 1 Refer to the PCI Express Base Specification for more details 2 Vtx ac cm pp and VrTx_Ac cM p are defined in the PCI Express Base Specification Measurement is made over at least 10 9 UI As measured with compliance test load Defined as 2 Vrxp COMP resistance must be provided on the system board with 196 resistors COMP resistors are to Vss PEG ICOMPI RCOMPO are the same resistor RMS value Measured at Rx pins into a pair of 50 Q terminations into ground Common mode peak voltage is defined by the expression max Vd Vd V CMDC DC impedance limits are needed to guarantee Receiver detect The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled to ensure that the Receiver Detect occurs properly Compensation of this impedance can start immediately and the 15 Rx Common Mode Impedance constrained by RLRX CM to 50 Q 20 must be within the specified ra
85. Thermal Protection Type CATERR PECI Datasheet PROCHOT THERMTRI P Catastrophic Error This signal indicates that the system has experienced a catastrophic error and cannot continue to operate The processor will set this for non recoverable machine check errors or other unrecoverable internal errors External agents are allowed to assert this pin which will cause the processor to take a machine check exception PECI Platform Environment Control Interface A serial sideband interface to the processor it is used primarily for thermal power and error management Details regarding the PECI electrical specifications protocols and functions can be found in the RS Platform Environment Control Interface Specification Revision 2 0 Processor Hot PROCHOT goes active when the processor temperature monitoring sensor s detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled This signal can also be driven to the processor to activate the TCC Thermal Trip The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating temperature to ensure that there are no false trips The processor will stop all execution when the junction temperature exceeds approximately 130 C This is signaled to the system by the THERMTR
86. VP 6 5 compliant VRs The processor continues to execute instructions However the processor will halt instruction execution for frequency transitions 60 Datasheet Thermal Management tel 5 2 1 1 2 5 2 1 2 Note Datasheet If a processor load based Enhanced Intel SpeedStep Technology P state transition through MSR write is initiated while the Adaptive Thermal Monitor is active there are two possible outcomes e f the P state target frequency is higher than the processor core optimized target frequency the p state transition will be deferred until the thermal event has been completed e f the P state target frequency is lower than the processor core optimized target frequency the processor will transition to the P state operating point Clock Modulation If the frequency voltage changes are unable to end an Adaptive Thermal Monitor event the Adaptive Thermal Monitor will utilize clock modulation Clock modulation is done by alternately turning the clocks off and on at a duty cycle ratio between clock on time and total time specific to the processor The duty cycle is factory configured to 37 5 and 62 5 off and cannot be modified The period of the duty cycle is configured to 32 microseconds when the TCC is active Cycle times are independent of processor frequency A small amount of hysteresis has been included to prevent excessive clock modulation when the processor temperature is near its maximum
87. accessing one SO DIMM It supports a maximum of one unbuffered non ECC DDR3 SO DIMM per channel thus allowing up to two device ranks per channel DDR3 Data Transfer Rates 800 MT s PC3 6400 and 1066 MT s PC3 8500 DDR3 SO DIMM Modules Raw Card A double sided x16 unbuffered non ECC Raw Card B single sided x8 unbuffered non ECC Raw Card C single sided x16 unbuffered non ECC Raw Card D double sided x8 stacked unbuffered non ECC Raw Card F double sided x8 planar unbuffered non ECC e DDR3 DRAM Device Technology Standard 1 Gb and 2 Gb technologies and addressing are supported for x16 and x8 devices There is no support for memory modules with different technologies or capacities on opposite sides of the same memory module If one side of a memory module is populated the other side is either identical or empty Table 2 1 Supported SO DI MM Module Configurations of of Row Raw DIMM DRAM DRAM of Physical Col Card Capacit Device Organization DRAM Device Address Version P y Technology 9 Devices END LL 20 Datasheet I nterfaces n tel Table 2 1 Supported SO DI MM Module Configurations of of Row of Raw BRAM DRAM of Physical Col Banks Card Capacit Device Organization PRAM Device Address Inside Version P y Technology 9 Devices Ranks Bits DRAM NOTES 1 System memory configurations are based on availability and are subject to change 2 Only Ra
88. ad all notes associated with each parameter Datasheet 95 n tel 7 Electrical Specifications 7 10 1 Voltage and Current Specifications Table 7 40 Processor Core VCC Active and Idle Mode DC Voltage and Current Specifications Symbol Parameter LUN VID VID Range for Highest a 800 Frequency Mode 0 750 LFM_VID VID Range for Lowest 0 775 Mode 0 725 LM Maximum Processor Core VR Step VID resolution SLOPE Processor Loadline a Non VR LL Non VR Loadline contribution Contribution for 1 Unless otherwise noted all specifications in this table based pre silicon estimates and simulations or empirical data These specifications will be updated with characterized data from silicon measurements at a later date 2 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Please note this differs from the VID employed by the processor during a power or thermal management event Intel Adaptive Thermal Monitor Enhanced Intel SpeedStep Technology or Low Power States 3 The voltage specification requirements are defined across VCC SENSE and VSS SENSE pins on the bottom side of the baseboard 4 Refer to Figure 7 13 and Figure 7 14 for the minimum typical a
89. ads are converted within the processor to the equivalent MWAIT C state request Therefore P LVLx reads do not directly result in reads to the system The feature known as 1 0 MWAIT redirection must be enabled in the BIOS Note The P LVLx I O Monitor address needs to be set up before using the P LVLx 1 0 read interface Each P LVLx is mapped to the supported MWAIT Cx instruction as follows Table 4 14 P LVLx to MWAIT Conversion P LVL2 MWAIT C3 The P LVL2 base address is defined in the PMG CAPTURE MSR described in the RS Nehalem Processor Family BWG P LVL3 MWAI T C6 C6 No sub states allowed The BIOS can write to the C state range field of the PMG CAPTURE MSR to restrict the range of I O addresses that are trapped and emulate MWAIT like functionality Any P LVLx reads outside of this range does not cause an 1 redirection to MWAIT Cx like request They fall through like a normal 1 instruction Note When P LVLx instructions are used MWAIT substates cannot be defined The MWAIT substate is always zero MWAIT redirection is used By default P redirections enable the MWAIT break on EFLAGS IF feature which triggers a wakeup on an interrupt even if interrupts are masked by EFLAGS IF Datasheet 43 i n tel Power Management 4 2 4 4 2 4 1 4 2 4 2 4 2 4 3 44 Core C states The following are general rules for all core C states unless specified otherwise e A cor
90. and similar characteristics as listed in Table 7 37 The buffer type indicates which signaling technology and specifications apply to the signals the differential signals and selected DDR3 and Control Sideband signals have On Die Termination ODT resistors There are some signals that do not have ODT and need to be terminated on the board Table 7 37 Signal Groups Sheet 1 of 3 di as Group m System Reference Clock Differential a CMOS Input BCLK BCLK PEG_CLK PEG_CLK DPLL_REF_SSCLK DPLL_REF_SSCLK Differential CMOS Output BCLK_ITP BCLK_ITP DDR3 Reference Clocks2 Differential c DDR3 Output SA_CK 1 0 SA_CK 1 0 SB CK 1 0 SB_CK 1 0 DDR3 Command Signals Single Ended d DDR3 Output SA 54 SB RAS SA 5 SB CAS SA WE SB SA MA 15 0 SB MA 15 0 SA BS 2 0 SB BS 2 0 SA DM 7 0 SB DM 7 0 SM DRAMRST SA_CS 1 0 58 CS 1 0 SA ODT 1 0 SB ODT 1 0 SA CKE 1 0 SB CKE 1 0 DDR3 Data Signals Single ended SA DQ 63 0 SB DQ 63 0 Differential DDR3 Bi directional SA DQS 7 0 SA DQS 7 0 SB DQS 7 0 58 DQS 7 0 TAP ITP XDP Single Ended CMOS Input TMS TRST Single Ended CMOS Input TDI TDI_M Single Ended CMOS Open Drain TDO TDO_M Output Single Ended i Asynchronous TAPPWRGOOD CMOS Output Datasheet 91 n tel 2 Electrical Specifications Table 7 37 Signal Groups Sheet 2 of 3 _ Control Sideband Single Ended
91. anted a request to a package state but has allowed a package C6 state In package C3 state the L3 shared cache is snoopable Package C6 State A processor enters the package C6 low power state when Atleast one core is in the C6 state The other cores are a or lower power state and the processor has been granted permission by the platform In package C6 state all cores have saved their architectural state and have had their core voltages reduced to zero volts The L3 shared cache is still powered and snoopable in this state The processor remains in package C6 state as long as any part of the L3 cache is active Power Status Indicator PSI and DPRSLPVR PSI 4 and DPRSLPVR are signals used to optimize VR efficiency over a wide power range depending on amount of activity within the processor core The PSI signal is utilized by the processor core to Improve intermediate and light load efficiency of the voltage regulator when the processor is active P states Optimize voltage regulator efficiency in very low power states Assertion of DPRSLPVR indicates that the processor core is in a C6 low power state The VR efficiency gains result in overall platform power savings and extended battery life I MC Power Management The main memory is power managed during normal operation and in low power ACPI Cx states Datasheet Power Management l n tel j 4 3 1 4 3 2 4 3 2 1 4 3 2 2 Datashee
92. are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor number for details Intel Intel SpeedStep Celeron Intel vPro and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2010 Intel Corporation All rights reserved 2 Datasheet Contents 1 Features Summary Ratte siesta ee suy 9 l l Jntrod ctlOn sete E 9 12 Processor Feature Details ree iu Eee ERRAT beret 11 1 2 1 Supported Technologies 1 2 2 24 4 4 4 1 4 emere nnn 11 13 EE 11 1 3 1 System Memory 0 hene enne ne 11 1 3 2 PEI EXPress iiid eo reta Ka unn KA ERR Es EU 12 1 3 3 Direct Media Interface 6 66 3 13 1 3 4 Platform Environment Control Interface 2 4 14 1 3 5 Intel HD Graphics cece ete eee mmn 14 1 3 6 Embedded DisplayPort 4 0 4 44 4 4 0 4 15 1 3 7 Intel Flexible Display Interface Intel
93. ase Specification for details of PCI Express The processor has one PCI Express controller that can support one external x16 PCI Express Graphics Device or two external x8 PCI Express Graphics Devices The primary PCI Express Graphics port is referred to as PEG 0 and the secondary PCI Express Graphics port is referred to as PEG 1 PCI Express Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged The PCI Express configuration uses standard mechanisms as defined in the PCI Plug and Play specification The initial recovered clock speed of 1 25 GHz results in 2 5 Gb s direction which provides a 250 MB s communications channel in each direction 500 MB s total That is close to twice the data rate of classic PCI The fact that 8b 10b encoding is used accounts for the 250 MB s where quick calculations would imply 300 MB s The PCI Express architecture is specified in three layers Transaction Layer Data Link Layer and Physical Layer The partitioning in the component is not necessarily along these same boundaries Refer to Figure 2 4 for the PCI Express Layering Diagram PCI Express Layering Diagram Physical Physical Logical Sub block Logical Sub block Electrical Bub block Electrical Bub block RX TX RX PCI Express uses packets to communicate information between components Packets are formed in the Transaction and Data Link Layers to carry the
94. at which the integrated graphics and memory controller must start throttling It may optionally enable integrated graphics and memory controller throttling when the temperature is exceeded This trip point may provide an interrupt to ACPI or other software when it is crossed in either direction Software could optionally set this as an interrupt when the temperature exceeds this level setting 65 i n tel gt Thermal Management 5 2 2 1 3 5 2 2 1 4 Note 5 2 2 1 5 5 2 2 1 6 5 2 2 2 66 Catastrophic Trip Point This trip point is set at the temperature at which the integrated graphics and memory controller must be shut down immediately without any software support This trip point may be programmed to generate an interrupt enable throttling or immediately shut down the system via Halt or via THERMTRIP assertion Crossing a trip point in either direction may generate several types of interrupts Recommended Programming for Available Trip Points See the integrated graphics and memory controller BIOS Specification for recommended Trip Point programming Aux Trip Points 0 1 2 3 should be programmed for software and firmware control via interrupts HOT Trip Point should be set to throttle integrated graphics and memory controller to avoid T max of 100 C Catastrophic Trip Point should be set to halt operation to avoid maximum Tj of 130 C Crossing a trip point in either direction may generate several types of interru
95. ates at or below its maximum operating temperature Processor core power reduction is achieved by Datasheet Thermal Management tel 5 2 1 1 1 Datasheet Adjusting the operating frequency via the core ratio multiplier and input voltage via the VID signals e Modulating starting and stopping the internal processor core clocks duty cycle The Adaptive Thermal Monitor dynamically selects the appropriate method BIOS is not required to select a specific method as with previous generation processors supporting Intel Thermal Monitor 1 TM1 or Intel Thermal Monitor 2 TM2 The temperature at which the Adaptive Thermal Monitor activates the Thermal Control Circuit is not user configurable but is software visible in the A32 TEMPERATURE TARGET 0x1A2 MSR Bits 23 16 The Adaptive Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines Note that the Adaptive Thermal Monitor is not intended as a mechanism to maintain processor TDP The system design should provide a thermal solution that can maintain TDP within its intended usage range Frequency VI D Control Upon TCC activation the processor core attempts to dynamically reduce processor core power by lowering the frequency and voltage operating point The operating points are automatically calculated by the processor core itself and do not require the BIOS to program them as with previous generations of Intel processo
96. cations Voltage Identification VI D The processor uses seven voltage identification pins VID 6 0 to support automatic selection of the processor power supply voltages VID pins for the processor are CMOS outputs driven by the processor VID circuitry A dedicated graphics voltage regulator is required to deliver voltage to the integrated graphics controller Like the processor core the integrated graphics controller will use seven voltage identification pins GFX VID 6 0 to set the nominal operating voltage GFX VID pins for the graphics core are CMOS outputs driven by the graphics core VID circuitry Table 7 35 specifies the voltage level for VID 6 0 and GFX VID 6 0 0 refers to a low voltage level VID signals are CMOS push pull drivers Refer to Table 7 44 for the DC specifications for these signals The VID codes will change due to temperature frequency and or power mode load changes in order to minimize the power of the part A voltage range is provided in Table 7 35 The specifications are set so that one voltage regulator can operate with all supported frequencies Individual processor VID values may be set during manufacturing so that two devices at the same core frequency may have different default VID settings This is shown in the VID range values in Table 7 35 The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage This will represent a DC shift i
97. ce Table 6 21 Memory Channel A Sheet 1 of 2 Type SA BS 2 0 Bank Select These signals define which O banks are selected within each SDRAM rank DDR3 SA WE Write Enable Control Signal Used with SA_RAS and SA 5 along with DDR3 SA 5 to define the SDRAM Commands SA RAS RAS Control Signal Used with SA CAS SA along with SA 5 to define DDR3 the SRAM Commands SA 5 CAS Control Signal Used with SA RAS SA WE along with SA 5 to define DDR3 the SRAM Commands SA DM 7 0 Data Mask These signals are used to mask individual bytes of data the case of a DDR3 partial write and to interrupt burst writes When activated during writes the corresponding data groups in the SDRAM are masked There is one SA DM 7 0 for every data byte lane SA DQS 7 0 Data Strobes SA DQS 7 0 and its I O complement signal group make up a DDR3 differential strobe pair The data is captured at the crossing point of SA DQS 7 0 and its SA_DQS 7 0 during read and write transactions SA_DQS 7 0 Data Strobe Complements These are the complementary strobe signals DDR3 SA DQ 63 0 Data Bus Channel A data signal interface to 1 0 the SDRAM data bus DDR3 SA MA 15 0 Memory Address These signals are used to provide the multiplexed row column DDR3 address to the SDRAM SA CK 1 0 SDRAM Differential Clock Channel A SDRAM Differential clock signal pair The DDR3 crossing o
98. client and host models must use a Schmitt triggered input design for improved noise immunity Use Figure 7 16 as a guide for input buffer design Figure 7 16 Device Hysteresis Y Vy TD High Range Maximum Vp _ g Minimum Vp Minimum Hysteresis Valid Input Signal Range Maximum Vs Minimum PECI Low Range PECI Ground 104 Datasheet m Processor Pin and Signal I nformation n tel 8 Processor Pin and Signal Information 8 1 Processor Pin Assignments Provides a listing of all processor pins ordered alphabetically by pin name for the rPGA988A and BGA1288 package respectively e Table 8 48 and Table 8 51 provides a listing of all processor pins ordered alphabetically by pin number for the rPGA988A and BGA1288 package respectively Figure 8 21 Figure 8 22 Figure 8 23 Figure 8 24 show the Top Down view of the rPGA988A pinmap e Figure 8 21 Figure 8 22 Figure 8 23 Figure 8 24 show the Top Down view of the BGA1288 ballmap Datasheet 105 e n tel Processor Pin and Signal Information Figure 8 17 Socket G rPGA988A Pinmap Top View Upper Left Quadrant 58 1 1 SB MA 5 SB CK f lt n SA_BS 2 SB BS 2 SA_DO 31 MEME SA_CKE O 5 d SA 5 SA DQ 3 3 SA DQ 2 SA DM
99. d error checking and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information Fan Speed Control with Digital Thermal Sensor Digital Thermal Sensor based fan speed control Tran is a recommended feature to achieve optimal thermal performance At the Tray temperature Intel recommends full cooling capability well before the DTS reading reaches Tj An example of this would be Tran Tj max 10 Datasheet Thermal Management tel 5 2 3 2 Datasheet Processor Thermal Data Sample Rate and Filtering The processor digital thermal sensor DTS provides an improved capability to monitor device hot spots which inherently leads to more varying temperature readings over short time intervals To reduce the sample rate requirements on PECI and improve thermal data stability vs time the processor DTS implements an averaging algorithm that filters the incoming data This filter is expressed mathematically as PECI t PECI t 1 1 2 X Temp PECI t 1 where e PECI t is the new averaged temperature e PECI t 1 is the previous averaged temperature e Temp is the raw temperature data from the DTS e X is the Thermal Averaging Constant The Thermal Averaging Constant is a BIOS configurable value that determines the time in milliseconds over which the DTS temperature values are averaged the default time is 256 ms
100. e C State is determined by the lowest numerical thread state e g Thread 0 requests while Thread 1 requests resulting a core CIE state See Table 4 11 Acore transitions to CO state when An interrupt occurs There is an access to the monitored address if the state was entered via an MWAIT instruction For core C1 C1E and core an interrupt directed toward a single thread wakes only that thread However since both threads are no longer at the same core C state the core resolves to CO e For core C6 an interrupt coming into either thread wakes both threads into CO state e Any interrupt coming into the processor package may wake any Core CO State The normal operating state of a core where code is being executed Core C1 CIE State C1 CIE is a low power state entered when all threads within core execute HLT or MWAIT C1 C1E instruction A System Management Interrupt SMI handler returns execution to either Normal state or the C1 CIE state See the Intel 64 and 32 Architecture Software Developer s Manual Volume 3A 3B System Programmer s Guide for more information While a core is C1 C1E state it processes bus snoops and snoops from other threads For more information on CIE see Package 1 1 Core C3 State Individual threads of a core can enter the state by initiating a P LVL2 1 0 read to the P BLK or an MWAIT C3 instruction A core in C3 sta
101. e and TLP sequence number and submits them to Physical Layer for transmission across the Link The receiving Data Link Layer is responsible for checking the integrity of received TLPs and for submitting them to the Transaction Layer for further processing On detection of TLP error s this layer is responsible for requesting retransmission of TLPs until information is correctly received or the Link is determined to have failed The Data Link Layer also generates and consumes packets which are used for Link management functions Physical Layer The Physical Layer includes all circuitry for interface operation including driver and input buffers parallel to serial and serial to parallel conversion PLL s and impedance matching circuitry It also includes logical functions related to interface initialization and maintenance The Physical Layer exchanges data with the Data Link Layer in an implementation specific format and is responsible for converting this to an appropriate serialized format and transmitting it across the PCI Express Link at a frequency and width compatible with the remote device Datasheet Interfaces 2 2 2 Figure 2 6 2 2 3 Datasheet intel PCI Express Configuration Mechanism The PCI Express external graphics link is mapped through a PCI to PCI bridge structure PCI Express Related Register Structures in the Processor PCI PCI Bridge representing PCI PCI Compatible Express root PCI Host
102. e f Input High Voltage e f IL Output Low Voltage c d e f H LI o I B mn 0 57 Vppq Vppo 2 TERM Vppo Vppo 2 Ron Output High Voltage c d e f DDR3 Clock Buffer On Resistance N H H DDR3 Clock Buffer On Resistance H NJ A DDR3 Command Buffer On Resistance DDR3 Command Buffer On Resistance DDR3 Control Buffer On Resistance Resistance N N N H DDR3 Control Buffer On DDR3 Data Buffer On Resistance DDR3 Data Buffer On Resistance Data ODT On Die Termination for d Data Signals N N Input Leakage Current COMP Resistance COMP Resistance t COMP Resistance t N NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value 3 Vip is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 Vin and Voy may experience excursions above However input signal drivers must comply with the signal quality specifications This is the pull down driver resistance Refer to processor I O Buffer Models for I V characteristics TERM is the termination on the DIMM and in not control
103. e insertion of the DRAM commands between the Activate Precharge and Read Write commands normally used as long as the inserted commands do not affect the currently executing command Multiple commands can be issued in an overlapping manner increasing the efficiency of system memory protocol Out of Order Scheduling While leveraging the J ust in Time Scheduling and Command Overlap enhancements the IMC continuously monitors pending requests to system memory for the best use of bandwidth and reduction of latency If there are multiple requests to the same open page these requests would be launched in a back to back manner to make optimum use of the open memory page This ability to reorder requests the fly allows the IMC to further reduce latency and increase bandwidth efficiency DRAM Clock Generation Every supported SO DIMM has two differential clock pairs There are total of four clock pairs driven directly by the processor to two SO DIMMs System Memory Pre Charge Power Down Support Details The IMC supports and enables slow exit DDR3 DRAM Device pre charge power down DLL control During a pre charge power down a slow exit is where the DRAM device DLL is disabled after entering pre charge power down for potential power savings Datasheet Interfaces 2 2 2 2 1 Figure 2 4 Datasheet intel PCI Express Interface This section describes the PCI Express interface capabilities of the processor See the PCI Express B
104. ed SO DIMM Module 1 20 DDR3 System Memory Timing Support m 21 eDP PEG Ball Mapping serae het eerta ee E ERR ERA AU EH ERO EIER 33 Processor Reference nnn nn nnn 35 Eheim Em 38 Processor Core Package State 38 Integrated Memory Controller 39 39 DMI States roa es 39 Integrated Graphics Controller States sess 39 S and C State CombinatlOns R 40 D 5 and State Combination 40 Coordination of Thread Power States at the Core 43 P LVLx to MWAIT 1 1 mme mmn rennen 43 Coordination of Core Power States at the Package 46 Targeted Memory State 2 2 4 50 Intel Celeron P4000 mobile processor series Dual Core SV Thermal Power SPECICATION S 56 18 W Ultra Low Voltage ULV Processor Idle Power
105. entering any other C state 45 i n tel Power Management The processor exits a package C state when a break event is detected Depending on the type of break event the processor does the following f a core break event is received the target core is activated and the break event message is forwarded to the target core If the break event is not masked the target core enters the core CO state the processor enters package CO If the break event is masked the processor attempts to re enter its previous package state e f the break event was due to a memory access or snoop request But the platform did not request to keep the processor in a higher package C state the package returns to its previous C state And the platform requests a higher power C state the memory access or snoop request is serviced and the package remains in the higher power C state Table 4 15 shows package C state resolution for a dual core processor Figure 4 11 summarizes package C state transitions Table 4 15 Coordination of Core Power States at the Package Level Deep Power Down Technology code named C6 state NOTE 1 If enabled the package C state will be CIE if all actives cores have resolved a core C1 state or higher 46 Datasheet Power Management l n tel j Figure 4 11 Package C State Entry and Exit 4 2 5 1 4 2 5 2 Datasheet The normal operating state for the processor The process
106. er Sheet 6 of 37 AF23 AF24 AF26 AF28 AF30 AF32 AF33 AF35 AF37 AF39 AF41 AF42 AF44 AF46 AF48 AF50 AF51 AF53 AF55 AF57 P E E E E E E E E E E E E E E E E E E E E N N 162 8 tel Processor Pin and Signal I nformation Table 8 51 BGA1288 Processor Ball Table 8 51 BGA1288 Processor Ball List by Ball Number List by Ball Number Sheet 7 of 37 Sheet 8 of 37 Buffer mem 15 fos 1 rua 1 en T VSS VSS VSS VSS VSS VSS mo 1 ws 98 0 0 0 2 2 2 2 O LL VSS VSS VCAP1 VCAP1 VCAP1 VCAPO AK50 AH60 gt v o EM RUN F gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt A A AlLALALA A AlLALA ul bA f p p w w Wl w NIN ejeje o o P5 N N O A w of LUN Lg 163 Datasheet Processor Pin and Signal I nformation Datasheet Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 9 of 37 Type AL12 AL15 AL17 AL33 O O 2 REF REF REF REF AL37 AL59 vial s o o Z Z Z Z gt 0 9 v z gt gt o x 2 Z v z REF REF AL62 AL69 GFX IMON 5 o alJ Table 8 51 BG
107. eserved or Unused Signals ccr rere xx EHE toner 90 7 6 Signal GrOUDS reete RR RR R E REP IR p b Re d rA PFR IPC 91 7 7 Test Access Port 2 ehem enn 93 7 8 Absolute Maximum and Minimum 065 94 7 9 Storage Conditions Specifications 0 Hmm nenne 94 720 DC Specificatlols pRR kisi XR YE kukaa 95 7 10 1 Voltage and Current 5 0 0 mme 96 7 11 Platform Environmental Control Interface DC Specifications 103 7 11 1 Characteristics CET ra 103 7 11 2 Input Device 2 424 4 4 enn nn nn 104 8 Processor Pin and Signal Information sss 105 8 1 Processor Pin Assignments creed bees ER GG qa 105 8 2 Package Mechanical memes nnn nn nnn nn 179 Figures Figure 1 1 Intel Celeron P4000 03000 mobile processor series on the Calpella Plat ONN i EL 10 Figure 2 2 Intel Flex Memory Technology Operation 22 Figure 2
108. f the positive edge of SA CK and the negative edge of its complement SA CK are used to sample the command and control signals on the SDRAM SA_CK 1 0 SDRAM Inverted Differential Clock O Channel A SDRAM Differential clock signal DDR3 pair complement Datasheet 71 n tel I Signal Description Table 6 21 Memory Channel A Sheet 2 of 2 Type SA CKE 1 0 Clock Enable 1 per rank Used to O Initialize the SDRAMs during power up DDR3 Power down SDRAM ranks Place all SDRAM ranks into and out of self refresh during STR SA_CS 1 0 Chip Select 1 per rank Used to select O particular SDRAM components during the DDR3 active state There is one Chip Select for each SDRAM rank SA ODT 1 0 On Die Termination Active Termination Control DDR3 Table 6 22 Memory Channel B Sheet 1 of 2 e Direction SB BS 2 0 Bank Select These signals define which banks selected within each SDRAM rank DDR3 SB_WE Write Enable Control Signal Used with SB 5 and SB 5 along with DDR3 SB 5 to define the SDRAM Commands SB RAS RAS Control Signal Used with SB CAS SB_WE along with SB CSz to define DDR3 the SRAM Commands SB_CAS CAS Control Signal Used with SB_RAS SB_WE along with SB CSz to define DDR3 the SRAM Commands SB DM 7 0 Data Mask These signals are used to mask individual bytes of data in the case of a DDR3 partial write and to interrupt burst writes
109. for use with a 1 9 Reserved or Unused Signals The following are the general types of reserved RSVD signals and connection guidelines RSVD these signals should not be connected e RSVD TP these signals should be routed to a test point e RSVD NCTF these signals are non critical to function and may be left un connected Arbitrary connection of these signals to Vcc Vm or to other signal including each other may result in component malfunction or incompatibility with future processors See Chapter 8 for a pin listing of the processor and the location of all reserved signals For reliable operation always connect unused inputs or bi directional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground Vss Unused outputs maybe left unconnected however this may interfere with some Test Access Port TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bi directional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Resistor values should be within 20 of the impedance of the baseboard trace unless otherwise noted in the appropriate platform design guidelines For details see Table 7 44 Datasheet Electrical Specifications n tel 7 6 Signal Groups Signals are grouped by buffer type
110. ge Conditions A non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor landings should not be connected to any supply voltages have any 1 5 biased or receive clocks Upon exposure to free air i e unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material cache memory convey sni processor Datasheet Features Summary intel 1 8 Related Documents Document Number Location Public Specifications Advanced Configuration and Power Interface Specification 3 0 http www acpi info PCI Local Bus Specification 3 0 http www pcisig com specifications PCI Express Base Specification 2 0 http www pcisig com DDR3 SDRAM Specification http www jedec org DisplayPort Specification http www vesa org Intel 64 and IA 32 Architectures Software Developer s Manuals http www intel com products processor manuals index htm Datasheet 19 l n tel I nterfaces 2 Interfaces This chapter describes the interfaces supported by the processor 2 1 System Memory Interface 2 1 1 System Memory Technology Supported The Integrated Memory Controller IMC supports DDR3 protocols with two independent 64 bit wide channels each
111. h generation graphics core Intel amp Dynamic Video Memory Technology Intel amp DVMT support Intel Graphics Performance Modulation Technology Intel GPMT Intel Smart 2D Display Technology Intel S2DDT Intel Clear Video Technology 2 Hardware Acceleration WMV9 VC1 Hardware Acceleration AVC Hardware Acceleration ProcAmp Advanced Pixel Adaptive De interlacing Sharpness Enhancement De noise Filter High Quality Scaling Film Mode Detection 3 2 pull down and Correction Intel TV Wizard 12 EUs Dedicated analog and digital display ports are supported through the Intel 5 Series Chipset PCH Datasheet Features Summary intel 1 3 6 Embedded DisplayPort eDP e Shared with PCI Express Graphics port e Shared on upper four logical lanes after any lane reversal eDP 3 0 map to PEG 12 15 non reversed eDP 3 0 map to PEG 3 0 reversed Concurrent eDP and PEG x1 supported 1 3 7 Intel Flexible Display Interface Intel FDI Carries display traffic from the integrated graphics controller the processor to the legacy display connectors in the PCH e Based on DisplayPort standard Two independent links one for each display pipe Four unidirectional downstream differential transmitter pairs Scalable down to 3X 2X or 1X based on actual display bandwidth requirements Fixed frequency 2 7 GT s data rate Two sideband signals for
112. h integrated graphics and memory controller and DDR3 power during periods of high activity As a result these features can help control temperature and help prevent thermally induced component failures These features include e Bandwidth throttling triggered by memory loading e Bandwidth throttling triggered by integrated graphics and memory controller heating THERMTRIP support e Render Thermal Throttling I nternal Digital Thermal Sensor The integrated graphics and memory controller incorporates one on die digital thermal sensor for thermal management The thermal sensor may be programmed to cause hardware throttling and or software interrupts Hardware throttling includes render thermal throttling and main memory programmable throttling thresholds Sensor trip points may also be programmed to generate various interrupts including SCI SMI INTR and SERR The internal thermal sensor reports six trip points Aux0 Aux1 Aux2 Aux3 Hot and Catastrophic trip points in order of increasing temperature 0 1 Aux2 Aux3 Temperature Trip Points These trip points may be set dynamically if desired and provides a configurable interrupt mechanism to allow software to respond when a trip is crossed in either direction These auxiliary temperature trip points do not automatically cause any hardware throttling but may be used by software to trigger interrupts Hot Temperature Trip Point This trip point is set at the temperature
113. h test which removes failing pixels and eliminates unnecessary processing overhead The Windower uses the parameters provided by the SF unit in the object specific rasterization algorithms The WIZ unit rasterizes objects into the corresponding set of pixels The Windower is also capable of performing dithering whereby the illusion of a higher resolution when using low bpp channels in color buffers is possible Color dithering diffuses the sharp color bands seen on smooth shaded objects Datasheet Interfaces 2 4 1 3 2 4 1 4 2 4 1 4 1 2 4 1 4 2 Datasheet intel Video Engine The Video Engine handles the non 3D media video applications It includes support for VLD and MPEG2 decode in hardware 2D Engine The 2D Engine contains BLT Block Level Transfer functionality and an extensive set of 2D instructions To take advantage of the 3D during engine s functionality some BLT functions make use of the 3D renderer Integrated Graphics VGA Registers The 2D registers consists of original VGA registers and others to support graphics modes that have color depths resolutions and hardware acceleration features that go beyond the original VGA standard Logical 128 Bit Fixed BLT and 256 Fill Engine This BLT engine accelerates the GUI of Microsoft Windows operating systems The 128 bit BLT engine provides hardware acceleration of block transfers of pixel data for many common Windows operations The BLT engine can be used f
114. ifferential bus clock pair to ITP BCLK_ITP Diff Clk PEG_CLK Differential PCI Express Based CLK Graphics DMI Clock In These pins receive Diff Clk B a 100 MHz Serial Reference clock from the external clock synthesizer This clock is used to generate the clocks necessary for the support of PCI Express This also is the reference clock for Intel amp FDI DPLL REF SSCLK Embedded Display Port PLL Differential l DPLL_REF_SSCLK Clock In With or without SSC 120 MHz Diff Clk Datasheet 77 intel 6 9 TAP Signals Table 6 29 TAP Signals Signal Name TCK TRST Signal Description Description Direction Buffer p Type TCK Test Clock Provides the clock input for the processor Test Bus also known as CMOS the Test Access Port TDI Test Data In Transfers serial test data into the processor TDI provides the CMOS serial input needed for JTAG specification support Test Data Output 5 Test Data for the GPU Memory core Tie TDI M M together on the CMOS motherboard Test Data Output from the processor O core Tie TDO M and TDI M together on the CMOS motherboard TMS Test Mode Select J specification support signal used by debug CMOS tools TRST Test Reset Boundary Scan test reset 5 TAPPWRGOOD Power good for ITP O Asynchronous CMOS 78 Datasheet Signal Description 6 10 Error and Thermal Protection Table 6 30 Error and
115. ile VCCPWRGOOD 0 and VCCPWRGOOD 1 is asserted SKTOCCZ rPGA988A only SKTOCC Socket Occupied PROC DETECT BGA only PROC DETECT Processor Detect pulled to ground on the processor package There is no connection to the processor silicon for this signal System board designers may use this signal to determine if the processor is present 80 Datasheet Signal Description tel 6 12 Processor Power Signals Table 6 32 Processor Power Signals Sheet 1 of 3 Direction Buffer Signal Name Description Processor core power rail VIT Processor 1 power rail 1 05 V and Ref VTTO and VTT1 VTT1 should share the same VR VDDQ DDR3 power rail 1 5 V VCCPLL Power rail for filters and PLLs 1 8 V ISENSE Current Sense from an Intel MVP6 5 Compliant Regulator to the processor core PROC DPRSLPVR Processor output signal to Intel MVP 6 5 controller to indicate that the processor is in CMOS the package C6 state PSI Processor Power Status Indicator This signal is asserted when the processor core Asynchronous CMOS current consumption is less than 15 A Assertion of this signal is an indication that the VR controller does not currently need to provide ICC above 15 A The VR controller can use this information to move to a more efficient operating point This signal will de assert at least 3 3 us before the current consumption will exceed 15 A The minimum PSI assertion and de assertion time is
116. information from the transmitting component to the receiving component As the transmitted packets flow through the other layers they are extended with additional information necessary to handle packets at those layers At the receiving side the reverse process occurs and 25 intel Interfaces Figure 2 5 2 2 1 1 2 2 1 2 2 2 1 3 26 packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally for Transaction Layer Packets to the form that can be processed by the Transaction Layer of the receiving device Packet Flow through the Layers Sequence x L Transaction Layer Data Link Layer Physica Layer Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer The Transaction Layer s primary responsibility is the assembly and disassembly of Transaction Layer Packets TLPs TLPs are used to communicate transactions such as read and write as well as certain types of events The Transaction Layer also manages flow control of TLPs Data Link Layer The middle layer in the PCI Express stack the Data Link Layer serves as an intermediate stage between the Transaction Layer and the Physical Layer Responsibilities of Data Link Layer include link management error detection and error correction The transmission side of the Data Link Layer accepts TLPs assembled by the Transaction Layer calculates and applies data protection cod
117. ink down after the link was up then the DMI link hangs the system by not allowing the link to retrain to prevent data corruption This is controlled by the PCH Downstream transactions that had been successfully transmitted across the link prior to the link going down may be processed as normal No completions from downstream non posted transactions are returned upstream over the DMI link after a link down event Datasheet Interfaces 2 4 intel Intel HD Graphics Controller This section details the 2D 3D and video pipeline and their respective capabilities The integrated graphics is powered by a refresh of the fifth generation graphics core and supports twelve fully programmable execution cores Full precision floating point operations are supported to enhance the visual experience of compute intensive applications The integrated graphics controller contains several types of components the graphics engines planes pipes port and the Intel FDI The integrated graphics has a 3D 2D Instruction Processing unit to control the 3D and 2D engines respectively The integrated graphics controller s 3D and 2D engines are fed with data through the IMC The outputs of the graphics engine are surfaces sent to memory which are then retrieved and processed by the planes The surfaces are then blended in the pipes and the display timings are transitioned from display core clock to the pixel dot clock Figure 2 7 ntegrated Graphics Contr
118. intel Intel Celeron amp Mobile Processor P4000 and U3000 Series Datasheet Revision 001 October 2010 Document Number 324471 001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RI GHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATI NG TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS OTHERWISE AGREED IN WRITING BY INTEL THE INTEL PRODUCTS ARE NOT DESI GNED NOR INTENDED FOR ANY APPLI CATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJ URY OR DEATH MAY OCCUR Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information A Intel processor numbers
119. iption Signal Description This chapter describes the processor signals They are arranged in functional groups according to their associated interface or category The following notations are used to describe the signal type Output Pin Bi directional Input Output Pin The signal description also includes the type of buffer used for the particular signal Table 6 20 Signal Description Buffer Types 70 s PCI Express PCI Express interface signals These signals are compatible with PCI Express 2 0 Signalling Environment AC Specifications and are AC coupled The buffers are not 3 3 V tolerant Refer to the PCle specification Intel Flexible Display interface signals These signals are compatible with PCI Express 2 0 Signaling Environment AC Specifications but are DC coupled The buffers are not 3 3 V tolerant DMI Direct Media Interface signals These signals are compatible with PCI Express 2 0 Signaling Environment AC Specifications but are DC coupled The buffers are not 3 3 V tolerant CMOS CMOS buffers 1 1 V tolerant DDR3 DDR3 buffers 1 5 V tolerant Analog reference or output May be used as a threshold voltage or for buffer compensation Gunning Transceiver Logic signaling technology Voltage reference signal Signal has no timing relationship with any reference clock NOTES 1 Qualifier for a buffer type Datasheet Signal Description 5 em 6 1 System Memory Interfa
120. is point the THERMTRI P signal will go active THERMTRIP activation is independent of processor activity and does not generate any bus cycles Critical Temperature Detection Critical Temperature detection is performed by monitoring the processor temperature and temperature gradient This feature is intended for graceful shutdown before the THERMTRI 4 is activated If the processor s Adaptive Thermal Monitor is triggered the temperature remains high a critical temperature status and sticky bit are latched in the thermal status MSR register and also generates a thermal interrupt if enabled The assertion of critical temperature bit indicates that processor can no longer be assumed to be working reliably For more details on the interrupt mechanism refer to the Intel 64 and I A 32 Architectures Software Developer s Manuals Datasheet Thermal Management tel 5 2 2 5 2 2 1 5 2 2 1 1 5 2 2 1 2 Datasheet I ntegrated Graphics and Memory Controller Thermal Features The integrated graphics and memory controller provides the following features for monitoring the integrated graphics and memory controller temperature and triggering thermal management One internal digital thermal sensor Hooks for an external thermal sensor mechanism which can either be TS on DI MM or TS on Board The integrated graphics and memory controller has implemented several silicon level thermal management features that can lower bot
121. is the lowest frequency of all memory modules placed in the system as determined through the SPD registers on the memory modules The system memory controller supports only one SO DIMM 23 l n tel Interfaces 2 1 5 2 1 5 1 2 1 5 2 2 1 5 3 2 1 6 2 1 7 24 connector per channel For dual channel modes both channels must have an SO DIMM connector populated For single channel mode only a single channel can have an SO DIMM connector populated Technology Enhancements of Intel Fast Memory Access Intel FMA The following sections describe the J ust in Time Scheduling Command Overlap and Out of Order Scheduling Intel FMA technology enhancements J ust in Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next The most efficient request is picked from all pending requests and issued to system memory J ust in Time to make optimal use of Command Overlapping Thus instead of having all memory access requests go individually through an arbitration mechanism forcing requests to be executed one at a time they can be started without interfering with the current request allowing for concurrent issuing of requests This allows for optimized bandwidth and reduced latency while maintaining appropriate command spacing to meet system memory protocol Command Overlap Command Overlap allows th
122. isplay traffic from the integrated graphics controller to the PCH display I O s Intel FDI supports two independent channels one for pipe A and one for pipe B Each channel has four transmit Tx differential pairs used for transporting pixel and framing data from the display engine e Each channel has one single ended LineSync and one FrameSync input 1 V CMOS signaling One display interrupt line input 1 V CMOS signaling ntel FDI may dynamically scalable down to 2X or 1X based on actual display bandwidth requirements e Common 100 MHz reference clock is sent to both processor and PCH Each channel transports at a rate of 2 7 Gbps e PCH supports end to end lane reversal across both channels no reversal support required 2 5 Platform Environment Control I nterface The PECI is a one wire interface that provides a communication channel between a PECI client processor and a PECI master usually the PCH The processor implements a PECI interface to 34 Datasheet Interfaces intel e Allow communication of processor thermal and other information to the master 9 Read averaged Digital Thermal Sensor DTS values for fan speed control 2 6 Interface Clocking 2 6 1 I nternal Clocking Requirements Table 2 4 Processor Reference Clocks Reference Input Clocks Input Frequency Associated PLL BCLK BCLK 133 MHz Processor Memory Graphics PEG_CLK PEG_CLK 100 MHz PCI Express DMI Intel FDI
123. ithout any special steps Enhanced Intel VT enables VMMs to run 64 bit guest operating systems on x86 processors More reliable Due to the hardware support VMMs can now be smaller less complex and more efficient This improves reliability and availability and reduces the potential for software conflicts More secure The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system I ntel e VT x Features The processor core supports the following Intel VT x features e Extended Page Tables EPT is hardware assisted page table virtualization It eliminates VM exits from guest OS to the VMM for shadow page table maintenance Virtual Processor IDs VPID Ability to assign a VM ID to tag processor core hardware structures such as Datasheet Technologies 3 2 Note Datasheet intel TLBs This avoids flushes on VM transitions to give a lower cost VM transition time and an overall reduction in virtualization overhead Guest Preemption Timer Mechanism for a VMM to preempt the execution of a guest OS after an amount of time specified by the VMM The VMM sets a timer value before entering a guest The feature aids VMM developers in flexibility and Quality of Service QoS guarantees Descriptor Table Exiting Descriptor table exiting allows a VMM to protect a guest OS
124. l applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained periods of time A range of power is to be expected among the components due to the natural variation in the manufacturing process Nevertheless the individual component powers are not to exceed the component TDPs specified Concurrent package power refers to the actual power consumed by the package while TDP applications are running simultaneously by the processor core and the integrated graphics controller An example of this could be the processor core running a Prime95 application and the integrated graphics core running a Star Wars Jedi Knight menu simultaneously The thermal solution needs to ensure that the temperatures of both components do not exceed the maximum junction temperature Tj limit as measured by the DTS and the critical temperature bit Please refer to processor Specification Update for Tjmax value per sku Datasheet Thermal Management n tel I Processor core and integrated graphics and memory controller junction temperatures are monitored by their respective DTS A DTS outputs a temperature relative to the maximum supported junction temperature The error associated with DTS measurements will not exceed 5 C within the operating range Processor core currents is monitored by IMON VR feedback ISENSE and calculated using a moving average method Error associated with power monitoring wil
125. l depend upon individual VR design A thermal solution for an power sharing enabled system needs to ensure that the Tj limit is not exceeded while operating under the two extreme power conditions between the processor core and the integrated graphics and memory controller components Projected range in advance of the measured product data Measured values will be available after silicon characterization 10 For power sharing designs it is recommended to establish the full cooling capability within 10 C of the Tj max specifications Some processors may have a different Tj max value please refer to the processor Specification Update for details 11 In rare occasions the specified maximum power limits may be violated when the package is not at a thermally constrained environment While running intensive graphical and computational workloads simultaneously the concurrent package power may exceed specified limits in exceptional occasions Nevertheless the individual component powers are not to exceed the component TDPs specified Intel Celeron Mobile Processor U3000 Series Dual Core ULV Thermal Power Specifications Power Sharing Design o Points dig Processor number CPU Core W Int Gfx amp Memory Controller w Pkg Concurrent Power w 13 CPU Core GHz CPU Core Extreme W 97 Int Gfx Extreme W 97 MCP Thermal Power Limit W CPU Core 9 Int Gfx amp Memory Controller 9C Int Gfx MH
126. led by the Processor The minimum and maximum values for these signals are programmable by BIOS to one of the two sets COMP resistance must be provided on the system board with 196 resistors COMP resistors are to Vss 100 Datasheet Electrical Specifications n tel Table 7 44 Control Sideband and TAP Signal Group DC Specifications lt lt lt lt lt lt lt lt lt I lt lt T k 1 r 5 i 1 5 1 ja jb m s t aa 9 qb t VoL Row VoH lui 5 Input Leakage Current lu qb Input Leakage Current COMPO COMP Resistance COMP1 COMP Resistance COMP2 COMP Resistance COMP3 t COMP Resistance NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The V referred to in these specifications refers to instantaneous V 3 Refer to the processor I O Buffer Models for I V characteristics 4 between 0 V and Vr Measured when the driver is tristated 5 Vin and Vor may experience excursions above However input signal drivers must comply with the signal quality specifications COMP resistance must be provided on the system board with 196 resistors COMP resistors are to Vss Rsys term is the system termination on the signal DUO Datasheet 101 n tel 7 Electrical Specifications
127. legacy D3D APIs as well as SGI OpenGL Vertex Shader VS Stage The VS stage performs shading of vertices output by the VF function The VS unit produces an output vertex reference for every input vertex reference received from the VF unit in the order received Geometry Shader GS Stage The GS stage receives inputs from the VS stage Compiled application provided GS programs specifying an algorithm to convert the vertices of an input object into some output primitives For example a GS shader may convert lines of a line strip into polygons representing a corresponding segment of a blade of grass centered on the line Or it could use adjacency information to detect silhouette edges of triangles and output polygons extruding out from the edges Clip Stage The Clip stage performs general processing on incoming 3D objects However it also includes specialized logic to perform a Clip Test function on incoming objects The Clip Test optimizes generalized 3D Clipping The Clip unit examines the position of incoming vertices and accepts rejects 3D objects based on its Clip algorithm Strips and Fans SF Stage The SF stage performs setup operations required to rasterize 3D objects The outputs from the SF stage to the Windower stage contain implementation specific information required for the rasterization of objects and also supports clipping of primitives to some extent Windower 12 WIZ Stage The WIZ unit performs an early dept
128. log DIFF CLK DMI_RX 3 DM DMI RX 3 MI VSS ND DMI_RX 0 MI PEG_RBIAS VSS GND VSS GND A32 A33 RSVD NCTF 1 0 1 0 1 0 1 0 1 0 1 0 Table 8 48 rPGA988A Processor Pin List by Pin Number SB BS 0 SA BS 1 SA_RAS DDR3 SB MA 10 DDR3 SB CSZ 0 DDR3 RSVD AB26 AB27 lt o lt g o AB29 110 intel Table 8 48 rPGA988A Processor Pin List by Pin Number Buffer Type AB30 AB31 AB32 AB33 AB34 AB35 1 10 26 27 28 29 AC30 AC31 AC32 AC33 AC34 AC35 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 VSS GND VSS ND VSS N VDDQ E VSS N SA 5 0 DDR3 VSS N SB 5 DDR3 SB DDR3 SB ODT O DDR3 VSS N VCC VCC VCC E revere _ mr mw Processor Pin and Signal I nformation Table 8 48 rPGA988A Processor Pin List by Pin Number som vss N VDDQ E SA CS 1 DDR3 SA DDR3 E VSS VDDQ VSS VSS GND SA DQI 33 DDR3 SA DQI 36 DDR3 Datasheet Processor Pin and Signal I nformation Datasheet Table 8 48 rPGA988A Processor Pin List by Pin Number ws s SB DQ 33 DDR3 1 0 SB_DQS 4 DDR3 1 0 SB_DQ 37 DDR3 1 0 SB_DQ 36 DDR3 SA_DQ 37 DDR3 1 0 SA DM 4 DDR3 SA MALLS DDR3 RSVD AH1 SB_DM 4 DDR3
129. lt register value after reset of the processor Altering this MSR value may result in unpredictable behavior I ntel Graphics Dynamic Frequency Thermal Design Considerations and Specifications When designing a thermal solution for Intel Graphics Dynamic frequency enabled processor e Both component TDPs as well as extreme thermal power levels for the processor core and integrated graphics and memory controller must be considered e Note that the processor can consume close to its maximum thermal power limit more frequently and for prolonged periods of time One must ensure that the component T max limits are not exceeded when either component is operating at its extreme thermal power limit There are two extreme design points The processor core operating at maximum thermal power level which is greater than its component TDP and the integrated graphics and memory controller operating at its minimum thermal power The integrated graphics operates at its maximum thermal power level while the processor core consumes the remaining thermal power budget In both cases the combined component thermal power will not exceed the total MCP package power limit The design approach accommodating two extreme power levels is referred to as a two point design The following notes apply to Table and Table 5 18 ERN NN 54 The component TDPs given are not the maximum power the components can generate Analysis indicates that rea
130. mber Sheet 26 of 37 omm BU35 BU39 SB_CK 1 DDR3 E N lt 40 VDDQ BU42 SB MA 10 DDR3 BU46 SB DDR3 BU49 SB 1 DDR3 BU53 SB 01411 DDR3 BU56 SB DQSI5 DDR3 SB DQ 46 DDR3 BU63 SB DQS 6 DDR3 BU65 SB DMI6 DDR3 BV1 TEST TEST BV3 aM BV5 TEST BV5 BV6 RSVD_NCTF aM BV8 RSVD NCTF 10 58 DQ 15 DDR3 1 0 BV12 SB DQI20 DDR3 1 0 BV13 SB_DQS 2 DDR3 1 0 BV15 5 19 DDR3 1 BV17 SB DQI22 DDR3 1 19 SB DQI29 DDR3 1 BV20 SB 01301 DDR3 1 O 22 SB DQI26 DDR3 1 0 24 58 5 2 DDR3 26 SB 14 DDR3 BV27 SB MA 8 DDR3 29 SB 2 DDR3 31 SB 4 DDR3 172 intel 173 Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 27 of 37 Buffer Type BV34 SB CKz 0 DDR3 BV36 SA MA 2 DDR3 BV38 SB CK 1 DDR3 BV40 SM RCOMP 2 SB BS 1 SB BS 0 Analog SB ODT O DDR3 SB DMIA SB DQ 34 DDR3 sopa o we ws we _ we _ we ocres eve _ BV45 BV47 BV48 BV50 1 0 1 0 w s lt lt lt Uil ule BIN DC_TEST_C3 LEX C3 C5 C6 C6 8 9 C71 10 V GND ms memes Processor Pin and Signal I nformation Table 8 51 BGA1288 Processor Ball List by Ball Number Sheet 28 of 37 VSS
131. mory with a maximum of SO DIMM per channel e Single and dual channel memory organization modes Data burst length of eight for all memory organization modes Memory DDR3 data transfer rates of 800 MT s SV ULV and 1066 MT s SV 64 bit wide channels DDR3 I O Voltage of 1 5 V e Non ECC unbuffered DDR3 SO DIMMs only Theoretical maximum memory bandwidth of 12 8 GB s in dual channel mode assuming DDR3 800 MT s 1 Gb and 2 Gb DDR3 DRAM technologies are supported for x8 and x16 devices Using 2 Gb device technologies the largest memory capacity possible is 8 GB assuming dual channel mode with two x8 double sided un buffered non ECC SO DIMM memory configuration e Up to 32 simultaneous open pages 16 per channel assuming 4 Ranks of 8 Bank Devices e Memory organizations Single channel modes Dual channel modes Intel Flex Memory Technology 11 1 3 2 12 Features Summary Dual channel symmetric Interleaved Dual channel asymmetric Command launch modes of 1n 2n Partial Writes to memory using Data Mask DM signals On Die Termination ODT Intel Fast Memory Access Intel FMA Just in Time Command Scheduling Command Overlap Out of Order Scheduling PCI Express The Processor PCI Express ports are fully compliant to the PCI Express Base Specification Revision 2 0 One 16 lane PCI Express port intended for graphics attach Gen1 2 5 GT s PCI Express freque
132. mpensation Multiplexed with PEG RCOMPO A eDP RBIAS Embedded DisplayPort Resistor Bias Control Multiplexed with PEG RBIAS A 6 6 Intel Flexible Display Interface Signals Table 6 26 Intel amp Flexible Display Interface Sheet 1 of 2 Type TX 3 0 Intel Flexible Display Interface FDI_TX 3 0 Transmit Differential Pair Pipe A FDI Intel amp Flexible Display Interface Frame Sync Pipe CMOS LSYNC 0 Intel amp Flexible Display Interface Line Sync 5 76 Datasheet Signal Description 5 em Table 6 26 ntel amp Flexible Display Interface Sheet 2 of 2 i Direction Buffer TX 7 4 Intel Flexible Display Interface FDI TX4 7 4 Transmit Differential Pair Pipe B O FDI FDI_FSYNC 1 Intel Flexible Display Interface Frame Sync Pipe B CMOS FDI_LSYNC 1 Intel Flexible Display Interface Line Sync 5 FDI INT Intel amp Flexible Display Interface Hot Plug Interrupt CMOS 6 7 DMI Table 6 27 DMI Processor to Serial nterface Direction Buffer DMI_RX 3 0 DMI Input from PCH Direct Media DMI_RX 3 0 Interface receive differential pair DMI DMI_TX 3 0 DMI Output to PCH Direct Media DMI TX 3 0 Interface transmit differential pair 6 8 PLL Signals Table 6 28 PLL Signals Type BCLK Differential bus clock input to the processor BCLK Diff Clk BCLK_ITP Buffered d
133. n Table 8 49 rPGA988A Processor Pin List by Pin Name List by Pin Name s IUD NINE EXE X pue upon NONE IL ONERE EIE 3 TE s Em si E X Buffer Type SB DQ 36 AG4 DDR SB DQI 37 A DDR A SB 005 0 SB 005 1 SB 0053421 SB 54 3 SB 00534441 SB 0053451 SB 54 6 SB 0053471 SB SB MA 1 SB 00138 DDR SB DQ 39 DDR SB DQ 40 DDR SB DQ 41 DDR SB 01421 DDR SB DQ 43 DDR SB_DQ 44 DDR SB_DQ 45 DDR SB_DQ 46 DDR SB_DQ 47 SB_DQ 48 DDR SB_DQ 49 DDR AG Ama ANS SB 09150 DDR ANG ANd ANS ars ATS AT APS DDR lt lt SB MA 5 DDR3 SB 61 DDR3 SB 7 DDR3 SB 8 DDR3 SB 9 DDR3 SB MA 10 DDR3 SB MA 11 DDR3 SB MA 12 DDR3 SB MA 13 DDR3 SB MA 14 DDR3 SB MA 15 DDR3 SB DDR3 SB ODT 1 DDR3 SB 5 DDR3 SB_WE DDR3 SKTOCC AH24 y SM DRAMPWRO AK13 DDR3 SM DRAMRST F6 DDR3 SB DQ 51 DDR SB 52 DDR SB 00153 DDR SB DQ 54 DDR SB DQ 55 DDR SB DQ 56 DD
134. n at or above the specified maximum junction temperature and affect the long term reliability of the processor e May be incapable of cooling the processor even when the TCC is active continuously in extreme situations Low Power States and PROCHOT Behavior If the processor enters a low power package idle state such as or with PROCHOT asserted PROCHOT will remain asserted until e The processor exits the low power state The processor junction temperature drops below the thermal trip point Note that the PECI interface is fully operational during all C states and it is expected that the platform continues to manage processor core thermals even during idle states by regularly polling for thermal data over PECI On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption via clock modulation This mechanism is referred to as On Demand mode and is distinct from Adaptive Thermal Monitor and 63 i n tel gt Thermal Management 5 2 1 4 1 5 2 1 4 2 5 2 1 5 5 2 1 6 64 bi directional PROCHOT Platforms must not rely software usage of this mechanism to limit the processor temperature On Demand Mode can be done via processor MSR or chipset I O emulation On Demand Mode may be used in conjunction with the Adaptive Thermal Monitor However if the system software tries to enable On Demand mode at the same time the TCC is e
135. n the loadline A low to high or high to low voltage state change will result in as many VID transitions as necessary to reach the target core voltage Transitions above the maximum or below the minimum specified VID are not permitted One VID transition occurs in 2 5 us The VR utilized must be capable of regulating its output to the value defined by the new VID values issued DC specifications for dynamic VID transitions are included in Table 7 35 Several of the VID signals VID 5 3 CSC 2 0 and VID 2 0 MSID 2 0 serve a dual purpose and are sampled during reset Refer to the signal description table in Chapter 6 for more information Table 7 35 Voltage Identification Definition Sheet 1 of 4 VID6 VID5 VIDA VID3 VI D2 VID1 VI DO Vcc V LASEL 86 Datasheet intel Electrical Specifications N lt 5 L 5 gt in m Li m 2 F gt o o gt gt gt N a gt m a gt d gt gt L9 em co jm m r m m m m m
136. ncy is supported 1 Raw bit rate on the data pins of 2 5 Gb s resulting in a real bandwidth per pair of 250 MB s given the 8b 10b encoding used to transmit data across this interface This also does not account for packet overhead and link maintenance Maximum theoretical bandwidth on interface of 4 GB s in each direction simultaneously for an aggregate of 8 GB s when x16 Gen 1 Hierarchical PCI compliant configuration mechanism for downstream devices Traditional PCI style traffic asynchronous snooped PCI ordering PCI Express extended configuration space The first 256 bytes of configuration space aliases directly to the PCI compatibility configuration space The remaining portion of the fixed 4 KB block of memory mapped space above that starting at 100h is known as extended configuration space PCI Express Enhanced Access Mechanism Accessing the device configuration space in a flat memory mapped fashion Automatic discovery negotiation and training of link out of reset Traditional AGP style traffic asynchronous non snooped PCI X Relaxed ordering Peer segment destination posted write traffic no peer to peer read traffic in Virtual Channel 0 DMI gt PCI Express Port 0 64 bit downstream address format but the processor never generates an address above 64 GB Bits 63 36 will always be zeros 64 bit upstream address format but the processor responds to upstream read transactions to addresses above 64 G
137. nd are non critical to function BGA only 6 14 Processor nternal Pull Up Pull Down Table 6 34 Processor Internal Pull Up Pull Down Signal Name Pull Up Pull Down SM DRAMPWROK Pull Down 10 20 kQ VCCPWRGOOD 0 Pull Down 10 20 VCCPWRGOOD 1 m w VITPWREOOD Datasheet 83 84 i n tel I Signal Description Table 6 34 Processor Internal Pull Up Pull Down CFG 17 0 Pull Up 5 14 Datasheet Electrical Specifications n tel 7 1 7 2 Caution 7 2 1 7 3 Datasheet Electrical Specifications Power and Ground Pins The processor has Vcc Vtr Vppo Vss ground inputs for on chip power distribution All power pins must be connected to their respective processor power planes while all Vss pins must be connected to the system ground plane Use of multiple power and ground planes is recommended to reduce I R drop The pins must be supplied with the voltage determined by the processor Voltage I Dentification VID signals Likewise the pins must also be supplied with the voltage determined by the GFX VID signals Table 7 35 specifies the voltage level for the various VIDs The voltage levels are the same for both the processor VIDs and GFX VIDs Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large current swings between low and full power states To keep
138. nd maximum allowed for a given current The processor should not be subjected to any and I cc combination wherein Vcc exceeds Vcc for a given current Processor core VR to be designed to electrically support this current Processor core VR to be designed to thermally support this current indefinitely This specification assumes that Intel Turbo Boost Technology with Intelligent Power Sharing is enabled mou 96 Datasheet Electrical Specifications Figure 7 13 Active Vcc and I cc Loadline PSI 4 Asserted max max Vcc nom oc m in i Vcc Tolerance VR St Pt Error 1 1 I 1 1 1 1 E 1 1 1 1 0 Vcc Set Point Error Tolerance is below max Tolerance VID Voltage Range VID 1 596 3mV gt 0 7500V 11 5mV 3mV 0 5000V lt Vcc 0 7500 Figure 7 14 Active Vcc and I cc Loadline PSI 4 Not Asserted Vcc V Slope SLOPE VCC_SENSE VSS_SENSE pins Differential Remote Sense required Vec max pc max Vcc nom Vcc pc min X Vcc Tolerance VR St Pt Error 0 Vcc Set Point Error Tolerance is per below Tolerance VID Voltage Range x VID 1 596 Vec gt 0 7500V x 11 5mV 0 5000V Vcc 0 7500 Datasheet lcc A 97 n tel 7 Electrical Specifications Table 7 41 Processor Uncore 1 Buffer Sup
139. ngaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode If the 1 0 based and MSR based On Demand modes are in conflict the duty cycle selected by the 1 0 emulation based On Demand mode will take precedence over the MSR based On Demand Mode MSR Based On Demand Mode If Bit 4 of the 2 CLOCK MODULATI ON MSR is set to 1 the processor will immediately reduce its power consumption via modulation of the internal core clock independent of the processor temperature The duty cycle of the clock modulation is programmable via Bits 3 1 of the same 2 CLOCK MODULATION MSR In this mode the duty cycle can be programmed from 12 596 on 87 5 off to 87 596 on 12 5 off in 12 596 increments Thermal throttling using this method will modulate each processor core s clock independently O Emulation Based On Demand Mode emulation based clock modulation provides legacy support for operating system software that initiates clock modulation through I O writes to ACPI defined processor clock control registers on the chipset PROC CNT Thermal throttling using this method will modulate all processor cores simultaneously THERMTRI P Signal Regardless of enabling the automatic or on demand modes in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature that risks physical damage to the processor At th
140. nge by the time Detect is entered 10 Low impedance defined during signaling Parameter is captured for 5 0 GHz by RLTX DIFF gt tw 102 Datasheet Electrical Specifications n tel Table 7 46 eDP DC Specifications eDP_HPD eme T m entier vae o 1 T in 95 ass Y eDP AUX eDP AUX VAUX DIFFp p Tx AUX Peak to Peak Voltage at the transmitting device VAUX DIFFp p Rx AUX Peak to Peak Voltage at the receiving device eDP COMPs 1 VAUX DIFFp p 2 Vauxe Vauxml Please refer to the VESA DisplayPort Standard specification for more details 2 COMP resistance must be provided on the system board with 1 resistors See the applicable platform design guide for implementation details COMP resistors are to Vss 3 eDP_ICOMPO eDP_RCOMPO the same resistor 4 These are pre silicon estimates and are subject to change 7 11 Platform Environmental Control I nterface DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external Adaptive Thermal Monitor devices The processor contains a Digital Thermal Sensor DTS that reports a relative die temperature as an offset from Thermal Control Circuit TCC activation temperature Temperature sensors located throughout the die are implemented as analog to digital converters calibrated at the
141. nnection methods to reduce device complexity support cross industry applications and provide performance scalability The integrated graphics supports an embedded DisplayPort eDP interface for display devices that are integrated into the system e g laptop LCD panel All other display interfaces connecting to the LVDS or external panels are driven from the PCH The eDP interface is physically shared with a subset of the PCle interface Specifically eDP 3 0 map to Logical Lanes PEG 12 15 of the PCle interface Mapping for reversed case is eDP 3 0 maps to PEG 3 0 eDP 0 ZPEG 15 in non reversed case In reversed case eDP 0 PEG O eDP PEG Ball Mapping eDP AUX PEG RX 13 PEG RX 2 eDP AUX PEG RX4 13 RX4 2 eDP HPD PEG RX 12 PEG RX 3 33 intel Interfaces Table 2 3 eDP PEG Ball Mapping sor sioner When eDP is enabled the lower logical lanes still available for standard PCle devices using the PEG 0 controller PEG 0 is limited to x1 The board manufacture chooses whether to use eDP and whether to use lane numbering reversal The eDP interface supports link speeds of 1 62 Gbps and 2 7 Gbps on 1 2 or 4 data lanes The eDP and PCI Express x1 may be supported concurrently eDP interface may support 0 596 SSC and non SSC clock settings 2 4 3 Intel Flexible Display Interface The Intel Flexible Display Interface Intel FDI is a proprietary link for carrying d
142. ntegrated Graphics Display Pipes The integrated graphics controller display pipe can be broken down into three components Display Planes Display Pipes e Embedded DisplayPort and Intel FDI Figure 2 8 Processor Display Block Diagram 2 4 2 1 2 4 2 1 1 2 4 2 1 2 32 Plane A Sprite A Cursor A Alpha Blend VGA gt Intel Panel FDI Fitter Plane gt Sprite Cursor B Display Planes A display plane is a single displayed surface in memory and contains one image desktop cursor overlay It is the portion of the display HW logic that defines the format and location of a rectangular region of memory that can be displayed on display output device and delivers that data to a display pipe This is clocked by the Core Display Clock Planes A and B Planes A and B are the main display planes and are associated with Pipes A and B respectively The two display pipes are independent allowing for support of two independent display streams They are both double buffered which minimizes latency and improves visual quality Sprite A and B Sprite A and Sprite B are planes optimized for video decode and are associated with Planes A and B respectively Sprite A and B are also double buffered Datasheet Interfaces 2 4 2 1 3
143. ntel FMA 24 2 1 0 DRAM Clock Generation essere P gu Seek VENERE ER 24 2 1 7 System Memory Pre Charge Power Down Support Details 24 2 2 PCI Express Interface ecce PE REX ER eR EN US 25 2 2 1 PCI Express Architecture 2 hah 25 2 2 2 Express Configuration Mechanism 20 222 27 2 2 3 PCI Express Ports and Bifurcation sciente ke tener 27 2 3 ier 28 2 3 1 DMI Enor aa 28 2 3 2 Compatibility 28 2 3 3 DMI LINK DOWD Ree nni oor 28 2 4 Intel HD Graphics Controller esses memes nnn n nnns 29 2 4 1 3D and Video Engines for Graphics 29 2 4 2 Integrated Graphics Display Pipes sss 32 2 4 3 Intel Flexible Display Interface emen 34 2 5 Platform Environment Control Interface 2 34 2 6 Interface Renal PIDE TIU 35 2 6 1 Internal Clocking Requirements csse nemen nnne 35 Datasheet intel Technologies puis ee
144. ocessor Pin and Signal I nformation Table 8 48 rPGA988A Processor Pin List by Pin Number Buffer Type SB DQ 44 DDR3 SA DQ 34 DDR3 SA DQ 35 DDR3 SA DQ 44 DDR3 SA DQS 5 DDR3 SA DQ 46 DDR3 SA DQ 43 DDR3 SM DRAMPWR D OK THERMTRI P Async GTL 1 0 1 0 1 0 1 0 1 0 1 0 5 AK6 AK7 AK8 AK9 AK10 AK11 AK12 AK13 14 15 16 17 18 19 20 21 22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AK33 4 5 I O 1 0 BPM 2 RSVD_TP E EE EIN Eos DE EN LONE RC E Hom 28 lt S eno wor eno D G R G R R G R G G G G G M G M M M M lt 5 2 3 R3 TL EF ND EF EF ND EF TL TL TL ND ND OS ND OS OS 5 05 5 05 9 3 D 1 2 3 14 Datasheet intel 114 Table 8 48 rPGA988A Processor Pin List by Pin Number Buffer Type AL5 AL6 AL7 AL8 AL AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 AL34 AL35 1 AM2 AM3 SB DOS 5 DDR3 VSS GND SA_DQ 45 DDR3 SA_DQ 47 DDR3 VSS ND SA_DQ 42 DDR3 SA_DQ 51 DDR3 SA 00 61 DDR3 RSTIN CMOS PM_SYNC CMOS VAXG E VSS N VAXG E VAXG E VSS N VAXG E I CFG 4 CMOS VSS N CFG 3 CMOS CSC 1 V
145. oller Unit Block Diagram 2 4 1 2 4 1 1 Datasheet Plane A Video Engine Sprite A P 2D Engine _ Cursor AK Alpha Blend Memory VGA Intel 3D Engine Panel FDI Fitter Vertex Fetch Vertex Plane B Shader Geometry Shader gt Sprite Clipper Strip amp Fan Setup Cursor Windower 12 3D and Video Engines for Graphics Processing The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive All the cores are fully programmable increasing the versatility of the 3D Engine The Gen 5 75 3D engine provides the following performance and power management enhancements Execution units EUs increased to 12 from the previous 10 EUsin Gen 5 0 Includes Hierarchal Z e Includes video quality enhancements 3D Engine Execution Units e Support 12 EUs The EUs perform 128 bit wide execution per clock 29 intel Interfaces 2 4 1 2 2 4 1 2 1 2 4 1 2 2 2 4 1 2 3 2 4 1 2 4 2 4 1 2 5 2 4 1 2 6 30 e Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel processing 3D Pipeline Vertex Fetch VF Stage The VF stage executes 3DPRIMITIVE commands Some enhancements have been included to better support
146. ontrol does the following e Utilizes internal graphics controller dynamic frequency performance states to achieve their highest performance within the rated thermal power envelope Intel Dynamic Frequency enabled processors will offer a range of upside performance capability beyond their rated or guaranteed frequency e Controls the processor core and internal graphics controller Intel Turbo Boost performance states to ensure that overall MCP thermal power consumption does not exceed the specified MCP thermal power limit Limits MCP component usage to ensure that each of the components T max value is not exceeded It is possible that the thermal influence between the MCP components could potentially cause a component to reach its Tj invoking undesirable component hardware auto throttling It is expected that when running the TDP workload power sharing control may limit the entire range of component Intel Turbo Boost capabilities effectively disabling them The principal component of the power sharing control architecture is the policy manager within the Intel Turbo Boost Technology driver which Communicates with the graphics software driver to limit or increase internal graphics thermal power e Communicates with the processor core via the PCH to processor core PECI interface to limit or increase processor core thermal power The Intel Turbo Boost Technology policy manager will set a thermal power limit to which
147. or fan speed or other platform thermal control 61 i n tel gt Thermal Management 5 2 1 3 Note 5 2 1 3 1 62 Code execution is halted in C1 C6 Therefore temperature cannot be read via the processor MSR without bringing a core back into C0 However temperature can still be monitored through PECI in lower C states Unlike traditional thermal devices the DTS outputs a temperature relative to the maximum supported operating temperature of the processor Tj It is the responsibility of software to convert the relative temperature to an absolute temperature The absolute reference temperature is readable in an MSR The temperature returned by the DTS is an implied negative integer indicating the relative offset from T The DTS does not report temperatures greater than Tj The DTS relative temperature readout directly impacts the Adaptive Thermal Monitor trigger point When a DTS indicates that the maximum processor core temperature has been reached a reading of 0x0 on any core the will activate and indicate a Adaptive Thermal Monitor event Changes to the temperature can be detected via two programmable thresholds located in the processor thermal MSRs These thresholds have the capability of generating interrupts via the core s local APIC Refer to the Intel 64 and 32 Architectures Software Developer s Manuals for specific register and programming details PROCHOT Signal PROCHOT process
148. or hot is asserted when the processor core temperature has reached its maximum operating temperature T max This will activate the TCC and signal a thermal event which is then resolved by the Adaptive Thermal Monitor See Figure 5 12 above for a timing diagram of the PROCHOT signal assertion relative to the Adaptive Thermal Response Only a single PROCHOT pin exists at a package level of the processor When any core arrives at the TCC activation point the PROCHOT signal will be driven by the processor core PROCHOT assertion policies are independent of Adaptive Thermal Monitor enabling Bus snooping and interrupt latching are active while the TCC is active Bi Directional PROCHOT By default the PROCHOT signal is defined as an output only However the signal may be configured as bi directional When configured as a bi directional signal PROCHOT can be used for thermally protecting other platform components should they overheat as well When PROCHOT is signaled externally The processor core will immediately reduce processor power to the minimum voltage and frequency supported This is contrary to the internally generated Adaptive Thermal Monitor response e Clock modulation is not activated The TCC will remain active until the system deasserts PROCHOTZ The processor can be configured to generate an interrupt upon assertion and deassertion of the PROCHOT signal Datasheet Thermal Management tel 5 2 1
149. or remains in the normal state when at least one of its cores is in the CO or C1 state or when the platform has not granted permission to the processor to go into a low power state Individual cores may be in lower power idle states while the package is in CO Package CO Package C1 CIE No additional power reduction actions are taken in the package C1 state However if the CIE sub state is enabled the processor automatically transitions to the lowest supported core clock frequency followed by a reduction in voltage The package enters the C1 low power state when At least one core is in the C1 state The other cores are in a or lower power state The package enters the state when All cores have directly requested C1E via MWAIT C1 with a CIE sub state hint All cores are in a power state lower that C1 C1E but the package low power state is limited to C1 C1E via the PMG CST CONFIG CONTROL MSR All cores have requested C1 using HLT or MWAIT C1 and CIE auto promotion is enabled 2 MISC ENABLES 47 i n tel Power Management 4 2 5 3 4 2 5 4 4 2 5 5 4 3 48 No notification to the system occurs upon entry to 61 61 Package C3 State A processor enters the package C3 low power state when e At least one core is in the state The other cores are a or lower power state and the processor has been granted permission by the platform The platform has not gr
150. or the following e Move rectangular blocks of data between memory locations Data alignment To perform logical operations raster ops The rectangular block of data does not change as it is transferred between memory locations The allowable memory transfers are between cacheable system memory and frame buffer memory frame buffer memory and frame buffer memory and within system memory Data to be transferred can consist of regions of memory patterns or solid color fills A pattern is always 8 x 8 pixels wide and may be 8 16 or 32 bits per pixel The BLT engine expands monochrome data into a color depth of 8 16 or 32 bits BLTs can be either opaque or transparent Opaque transfers move the data specified to the destination Transparent transfers compare destination color to source color and write according to the mode of transparency selected Data is horizontally and vertically aligned at the destination If the destination for the BLT overlaps with the source memory location the BLT engine specifies which area in memory to begin the BLT transfer Hardware is included for all 256 raster operations source pattern and destination defined by Microsoft including transparent BLT The BLT engine has instructions to invoke BLT and stretch BLT operations permitting software to set up instruction buffers and use batch processing The BLT engine can perform hardware clipping during BLTs 31 l n tel I nterfaces 2 4 2 I
151. ores Thread 0 Thread 0 Core 0 State Core 1 State Processor Package State Entry and exit of the C States at the thread and core level are shown in below figure Figure 4 10 Thread and Core C State Entry and Exit MWAIT C6 MWAIT C1 e MWAIT C3 Read CLE Enabled pz ds 10 Read While individual threads can request low power C states power saving actions only take place once the core C state is resolved Core C states are automatically resolved by the processor For thread and core C states a transition to and from CO is required before entering any other C state 42 Datasheet Power Management n tel Table 4 13 Coordination of Thread Power States at the Core Level Processor Core Thread 1 C State o g G lt F NOTE If enabled the core C state will be C1E if all actives cores have also resolved a core C1 state or higher 4 2 3 Requesting Low Power Idle States The primary software interfaces for requesting low power idle states are through the MWAIT instruction with sub state hints and the instruction for C1 However software may make C state requests using the legacy method of I O reads from the ACPI defined processor clock control registers referred to as P LVLx This method of requesting C states provides legacy support for operating systems that initiate C state transitions via I O reads For legacy operating systems P LVLx I O re
152. ound They can E 7 used to sense measure voltage near the silicon VAXG Graphics core power rail VAXG SENSE VAXG SENSE and VSSAXG SENSE provide VSSAXG SENSE an isolated low impedance connection to the 7 VAXG voltage and ground They be used to sense or measure voltage near the silicon GFX VID 6 0 GFX VID 6 0 Voltage ID pins are used to support automatic selection of nominal voltages VAXG These are CMOS signals that are driven by the processor GFX VR EN GPU output signal to Intel MVP6 5 compliant VR This signal is used as an on off control to enable disable the GPU VR 82 Datasheet Signal Description tel Table 6 32 Processor Power Signals Sheet 3 of 3 Direction Buffer GFX DPRSLPVR GPU output signal to Intel MVP6 5 compliant O VR When asserted this signal indicates that CMOS the GPU render suspend mode This signal is also used to control render suspend state exit slew rate GFX_IMON Current Sense from an Intel MVP6 5 l Compliant Regulator to the GPU A VDDQ_CK Filtered power for VDDQ BGA Only VTTO_DDR Filtered power for VTTO BGA Only WR Processor Connection to On board decoupling capacitors only 6 13 Ground and NCTF Table 6 33 Ground and NCTF 2 Direction Buffer VSS NCTF Non Critical to Function The pins are for package mechanical reliability DC TEST Daisy Chain Test These pins are for solder joint reliability a
153. ply DC Voltage and Current Specifications Voltage for the memory controller and shared cache defined at the 0 9975 1 1025 motherboard Vtt pinfield via Voltage for the memory controller and shared cache defined across 0 9765 1 05 1 1235 V 2 VIT SENSE and VSS SENSE VTT Processor I O supply voltage for DDR3 DC AC specification 1425 129 VccPLL PLL supply voltage DC AC 1 710 1 890 specification TOL V41 Tolerance defined at the socket DC 2 motherboard VTT pinfield via AC 3 including ripple Tolerance defined across DC 2 VIT SENSE and VSS SENSE VIT AC 5 including ripple TOLppq VDDQ Tolerance DC 4396 2 AC DC 5 TOLccPLL VCCPLL Tolerance AC DC 5 5 UT MN ESSE SV VDDQ Max Current for veg tal C Imax voee 24 Iccmax vec Max Current for Vece Thermal Design Current for Rail SV Average Current for Rail during Standby Standby 1 The voltage specification requirements are defined across at the socket motherboard pinfield vias on the bottom side of the baseboard 2 The voltage specification requirements are defined across VIT SENSE and VSS SENSE VIT pins the bottom side of the baseboard 3 Defined at nominal VTT voltage 4 These are pre silicon estimates and are subject to change
154. power down contents lost Memory power down contents lost 4 3 2 3 Dynamic Power Down Operation Dynamic power down of memory is employed during normal operation Based on idle conditions a given memory rank may be powered down The IMC implements aggressive CKE control to dynamically put the DRAM devices in a power down state The processor core controller can be configured to put the devices in active power down CKE deassertion with open pages or precharge power down CKE deassertion with all pages closed Precharge power down provides greater power savings but has a bigger performance impact since all pages will first be closed before putting the devices in power down mode If dynamic power down is enabled all ranks are powered up before doing a refresh cycle and all ranks are powered down at the end of refresh 4 3 2 4 DRAM 1 Power Management Unused signals should be disabled to save power and reduce electromagnetic interference This includes all signals associated with an unused memory channel Clocks can be controlled on a per SO DIMM basis Exceptions are made for per SO DI MM control signals such as 5 CKE and ODT for unpopulated SO DIMM slots The 1 0 buffer for an unused signal should be tri stated output driver disabled the input receiver differential sense amp should be disabled and any DLL circuitry related ONLY to unused signals should be disabled The input path must be gated to prevent spurious results
155. pts Each trip point has a register that can be programmed to select the type of interrupt to be generated Crossing a trip point is implemented as edge detection on each trip point to generate the interrupts Either edge i e crossing the trip point in either direction generates the interrupt Thermal Sensor Accuracy Taccuracy The error associated with DTS measurement will not exceed 5 within the operating range Integrated graphics and memory controller may not operate above T max spec This value is based on product characterization and is not guaranteed by manufacturing test Software has the ability to program the Teat Thot and Taux trip points but these trip points should be selected with consideration for the thermal sensor accuracy and the quality of the platform thermal solution Overly conservative unnecessarily low temperature settings may unnecessarily degrade performance due to frequent throttling while overly aggressive dangerously high temperature settings may fail to protect the part against permanent thermal damage Hysteresis Operation Hysteresis provides a small amount of positive feedback to the thermal sensor circuit to prevent a trip point from flipping back and forth rapidly when the temperature is right at the trip point The digital hysteresis offset is programmable via processor registers Memory Thermal Throttling Options The integrated graphics and memory controller has two independent mechanism
156. r display connections to LCD panels Multi Chip Package Non Critical to Function NCTF locations are typically redundant ground or non critical reserved so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality Nehalem Intel s 45 nm processor design follow on to the 45 nm Penryn design Datasheet 17 18 tel Features Summary Platform Controller Hub The new 2009 chipset with centralized platform capabilities including the main 1 interfaces along with display connectivity audio features power management manageability security and storage features The PCH may also be referred to using the name Mobile Intel amp 5 Series Chipset Platform Environment Control Interface PCI Express Graphics External Graphics using PCI Express Architecture A high speed serial interface whose configuration is software compatible with the existing PCI specifications The 64 bit single core or multi core component package Processor Core The term processor core refers to Si die itself which can contain multiple execution cores Each execution core has an instruction cache data cache and 256 KB L2 cache All execution cores share the L3 cache A unit of DRAM corresponding four to eight devices in parallel ignoring ECC These devices are usually but not always mounted on a single side of a SO DIMM System Control Interrupt Used in ACPI protocol Stora
157. re is one Chip Select for each SDRAM rank SB ODT 1 0 On Die Termination Active Termination Control DDR3 6 2 Memory Reference and Compensation Table 6 23 Memory Reference and Compensation Type SM RCOMP 2 0 System Memory I mpedance Compensation SA DIMM VREFDQ Memory Channel A B DIMM Voltage SB DIMM VREFDQ Datasheet 73 i n tel I Signal Description 6 3 Reset and Miscellaneous Signals Table 6 24 Reset and Miscellaneous Signals Sheet 1 of 2 Type SM_DRAMRST DDR3 DRAM Reset Reset signal from O processor to DRAM devices One for all DDR3 channels SO DI MMs PM_EXT_TS 0 External Thermal Sensor Input If the 5 1 system temperature reaches a dangerously CMOS gt high value then this signal can be used to trigger the start of system memory throttling COMPO Impedance compensation must be terminated on the system board using A precision resistor COMP1 Impedance compensation must be terminated on the system board using A precision resistor COMP2 Impedance compensation must be terminated on the system board using A precision resistor COMP3 Impedance compensation must be terminated on the system board using A precision resistor PM SYNC Power Management Sync A sideband signal to communicate power management CMOS status from the platform to the processor RESET OBS This signal is an indication of the processor
158. rie n Keane ERE ER AR KE 36 3 1 Intel Virtualization mne 36 3 1 1 I tel amp VI x een reti dade ioo eit CR ER RTI ERE RE IER 36 3 1 2 Wntel amp VT x Features iuis eene tnn etra e ER Ren e ERR ECCE GR Rot 36 3 2 Intel Graphics Dynamic Frequency emen ene enn nnn 37 Power Management nee lt lt C EXER 38 4 l States Supported iei 38 4 1 1 System Stat S RR YTAREDERTRDRRRRR RR kiqa 38 4 1 2 Processor Core Package Idle 5 1 mmm 38 4 1 3 Integrated Memory Controller 5 2 00 39 4 4 PCIe Link u u EE Marne YR or ion 39 4 1 5 DMI States niei RERO HERERFERERERERIRRERKRRRJR E RR 39 4 1 6 Integrated Graphics Controller 39 4 1 7 Interface State Combinations sss meme 40 4 2 Processor Core Power 40 4 2 1 Enhanced Intel SpeedStep 41 4 2 2 Low Power Idle nr nen nnn nnn 41 4 2 3 Requesting Low Power Idle
159. routing methods are applicable for both thermal sensors placed on the motherboard TS on Board and or thermal sensors located on the memory modules TS on DI MM THERMTRI P Operation The integrated graphics and memory controller can assert THERMTRIP Thermal Trip to indicates that its junction temperature has reached a level beyond which damage may occur Upon assertion of THERMTRIP the integrated graphics and memory 67 i n tel gt Thermal Management 5 2 2 5 Caution 5 2 3 5 2 3 1 68 controller will shut off its internal clocks thus halting program execution in an attempt to reduce the core junction temperature Once activated THERMTRIP remains latched until RSTIN is asserted Render Thermal Throttling Render Thermal Throttling of the integrated graphics and memory controller allows for the reduction the render core engine frequency and voltage thus reducing internal graphics controller power and integrated graphics and memory controller thermals Performance is degraded but the platform thermal burden is relieved Render Thermal Throttling using several frequency voltage operating points that can be used to throttle the render core If the temperature of the integrated graphics and memory controller internal DTS exceeds the Hot trip point the integrated graphics will Switch to a lower frequency voltage operating point After a timeout the DTS is rechecked and if the DTS temperature is still greater than the
160. rs The processor core will scale the operating points such that e The voltage will be optimized according to the temperature the core bus ratio and number of cores in deep C states The core power and temperature are reduced while minimizing performance degradation A small amount of hysteresis has been included to prevent an excessive amount of operating point transitions when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the operating frequency and voltage transition back to the normal system operating point This is illustrated in Figure 5 12 59 i n tel gt Thermal Management Figure 5 12 Frequency and Voltage Ordering E PROCHOT Once a target frequency bus ratio is resolved the processor core will transition to the new target automatically e On upward operating point transition the voltage transition precedes the frequency transition On a downward transition the frequency transition precedes the voltage transition When transitioning to a target core operating voltage a new VID code to the voltage regulator is issued The voltage regulator must support dynamic VID steps to support this method During the voltage change t will be necessary to transition through multiple VID steps to reach the target operating voltage Each step is 12 5 mV for Intel M
161. s but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time it will either not function or its reliability will be severely degraded when returned to conditions within the functional operating condition limits Although the processor contains protective circuitry to resist damage from Electro Static Discharge ESD precautions should always be taken to avoid high static voltages or electric fields Table 7 38 Processor Absolute Minimum and Maximum Ratings Graphics voltage with respect to Vss SV ULV NOTES 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Vcc Vaxg are VID based rails 7 9 Storage Conditions Specifications Environmental storage condition limits define the temperature and relative humidity to which the device is exposed to while being stored in a moisture barrier bag The specified storage conditions are for component level prior to board attach Table 7 39 specifies absolute maximum and minimum storage temperature limits which represent the maximum or minimum device condition beyond which
162. s or desiccant 4 Component product device storage temperature qualification methods may follow J ESD22 A119 low temp and JESD22 A103 high temp standards when applicable for volatile memory 5 Intel amp branded products are specified and certified to meet the following temperature and humidity limits that are given as an example only Non Operating Temperature Limit 40 to 70 and Humidity 50 to 9096 non condensing with a maximum wet bulb of 28 C Post board attach storage temperature limits are not specified for non Intel branded boards 6 The JEDEC J J STD 020 moisture level rating and associated handling practices apply to all moisture sensitive devices removed from the moisture barrier bag 7 Nominal temperature and humidity conditions and durations are given and tested within the constraints imposed by Tsustained storage and customer shelf life in applicable Intel boxes and bags 7 10 DC Specifications The processor DC specifications in this section are defined at the processor pins unless noted otherwise See Chapter 8 for the processor pin listings and Chapter 6 for signal definitions The DC specifications for the DDR3 signals are listed in Table 7 43 Control Sideband and Test Access Port TAP are listed in Table 7 44 Table 7 40 lists the DC specifications for the processor and are valid only while meeting specifications for junction temperature clock frequency and input voltages Care should be taken to re
163. s 100 MHz PCI Express reference clock 64 bit downstream address format but the processor never generates an address above 64 GB Bits 63 36 will always be zeros 64 bit upstream address format but the processor responds to upstream read transactions to addresses above 64 GB addresses where any of Bits 63 36 are nonzero with an Unsupported Request response Upstream write transactions to addresses above 64 GB will be dropped Supports the following traffic types to or from the PCH DMI gt PCI Express Port 0 write traffic DMI DRAM DMI gt processor core Virtual Legacy Wires VLWs Resetwarn or MSIs only 13 1 3 4 1 3 5 14 Features Summary Processor core gt DMI APIC and MSI interrupt messaging support Message Signaled Interrupt MSI and MSI X messages Downstream SMI SCI and SERR error indication Legacy support for ISA regime protocol PHOLD PHOLDA required for parallel port DMA floppy drive and LPC bus masters DC coupling no capacitors between the processor and the PCH Polarity inversion PCH end to end lane reversal across the link Supports Half Swing low power low voltage Platform Environment Control nterface The PECI is a one wire interface that provides a communication channel between a PECI client the processor and a PECI master the PCH Intel HD Graphics Controller The integrated graphics controller contains a refresh of the fift
164. s that cause system memory throttling TDP Controller The TDP Controller is the main mechanism for limiting MCH power by limiting memory bandwidth Utilized as a thermal throttling mechanism this feature is triggered by the Hot temperature trip point of the Graphics and Memory Controller Datasheet Thermal Management tel Note 5 2 2 3 Note 5 2 2 4 Datasheet digital thermal sensor DTS and initiates duty cycle throttling to delay memory transactions and thereby reducing MCH power Power reduction is memory configuration and application dependant but duty cycle throttling intervals can be customized for maximum throttling efficiency The TDP Controller can also be used as a bandwidth limiter using programmable memory read write bandwidth thresholds Intel sets the default thresholds that will not restrict bandwidth and performance for most applications but these thresholds can be modified to reduce MCH power regardless of DTS temperature The TDP controller can be used as a closed loop thermal throttling CLTT mechanism or an open loop thermal throttling OLTT mechanism although CLTT is recommended DRAM Thermal Management Ensures that the DRAM chips are operating within thermal limits The integrated graphics and memory controller can control the amount of integrated graphics and memory controller initiated bandwidth per rank to a programmable limit via a weighted input averaging filter External Thermal Sen
165. sor nterface Overview The integrated graphics and memory controller supports two inputs for external thermal sensor notifications based on which it can regulate memory accesses The thermal sensors should be capable of measuring the ambient temperature only and should be able to assert PM EXT 54 0 and or PM EXT 54 1 if the pre programmed thermal limits conditions are met or exceeded An external thermal sensor with a serial interface may be placed next to a SO DIMM or any other appropriate platform location or a remote Thermal Diode may be placed next to the SO DIMM or any other appropriate platform location and connected to the external Thermal Sensor Additional external thermal sensor s outputs for multiple sensors be wire OR d together allow signaling from multiple sensors that are physically located separately Software can if necessary distinguish which SO DIMM s is the source of the overtemp through the serial interface However since the SO DIMM s is located the same Memory Bus Data lines any integrated graphics and memory controller based read throttle will apply equally Thermal sensors can either be directly routed to the integrated graphics and memory controller PM EXT 54 0 and PM EXT 54 1 pins or indirectly routed to integrated graphics and memory controller by invoking an Embedded Controller EC connected in between the thermal sensor and integrated graphics and memory controller pins Both
166. st Technology and Intel Graphics Dynamic Frequency will increase the ratio of application power to TDP Thus thermal solutions and platform cooling that are designed to less than thermal design guidance might experience thermal and performance issues since more applications will tend to run at the maximum power limit for significant periods of time For more details refer to Chapter 5 Thermal Management 37 i n tel Power Management 4 Power Management This chapter provides information on the following power management topics e States e Processor Core Integrated Memory Controller IMC e PCI Express Direct Media Interface DMI e Integrated Graphics Controller 4 1 ACPI States Supported The ACPI states supported by the processor are described in this section 4 1 1 System States Table 4 5 System States s G1 S3 Cold Suspend to RAM STR Context saved to memory S3 Hot is not supported by the processor G1 S4 Suspend to Disk STD All power lost except wakeup on PCH G2 S5 Soft off All power lost except wakeup on PCH Total reboot Mechanical off All power AC and battery removed from system 4 1 2 Processor Core Package Idle States Table 4 6 Processor Core Package State Support C3 Execution cores in C3 flush their L1 instruction cache L1 data cache and L2 cache to the L3 shared cache Clocks are shut off to each core C6 Execution cores in this state save
167. t Disabling Unused System Memory Outputs Any system memory SM interface signal that goes to a memory module connector in which it is not connected to any actual memory devices such as SO DIMM connector is unpopulated or is single sided is tri stated The benefits of disabling unused SM signals are Reduced power consumption 9 Reduced possible overshoot undershoot signal quality issues seen by the processor buffer receivers caused by reflections from potentially un terminated transmission lines When a given rank is not populated the corresponding chip select and CKE signals are not driven At reset all rows must be assumed to be populated until it can be proven that they are not populated This is due to the fact that when CKE is tristated with an SO DIMM present the SO DIMM is not guaranteed to maintain data integrity DRAM Power Management and I nitialization The processor implements extensive support for power management on the SDRAM interface There are four SDRAM operations associated with the Clock Enable CKE signals which the SDRAM controller supports The processor drives four CKE pins to perform these operations Initialization Role of During power up CKE is the only input to the SDRAM that has its level is recognized other than the DDR3 reset pin once power is applied It must be driven LOW by the DDR controller to make sure the SDRAM components float DQ and DQS during power up CKE signals
168. te flushes the contents of its L1 instruction cache L1 data cache and L2 cache to the shared L3 cache while maintaining its architectural state All core clocks are stopped at this point Because the core s caches are flushed the processor does not wake any core that is in the C3 state when either a snoop is detected or when another core accesses cacheable memory Datasheet Power Management l n tel j 4 2 4 4 4 2 4 5 4 2 5 Datasheet Core C6 State Individual threads of a core can enter the state by initiating a P LVL3 I O read or an MWAIT C6 instruction Before entering core C6 the core will save its architectural state to a dedicated SRAM Once complete a core will have its voltage reduced to zero volts During exit the core is powered on and its architectural state is restored C State Auto Demotion In general deeper C states such as Deep Power Down Technology code named C6 state have long latencies and have higher energy entry exit costs The resulting performance and energy penalties become significant when the entry exit frequency of a deeper C state is high Therefore incorrect or inefficient usage of deeper C states have a negative impact on battery life In order to increase residency and improve battery life in deeper C states the processor supports C state auto demotion There are two C State auto demotion options Deep Power Down Technology code named C6 state to C3 Deep Power Down Technology
169. teps to an optimized voltage This voltage is signaled by the VID 6 0 pins to the voltage regulator Once the voltage is established the PLL locks on to the target frequency If the target frequency is lower than the current frequency the PLL locks to the target frequency then transitions to a lower voltage by signaling the target voltage on the VID 6 0 pins All active processor cores share the same frequency and voltage In a multi core processor the highest frequency P state requested amongst all active cores is selected Software requested transitions are accepted at any time If a previous transition is in progress the new transition is deferred until the previous transition is completed The processor controls voltage ramp rates internally to ensure glitch free transitions Because there is low transition latency between P states a significant number of transitions per second are possible 4 2 2 Low Power Idle States When the processor is idle low power idle states C states are used to save power More power savings actions are taken for numerically higher C states However higher C states have longer exit and entry latencies Resolution of C states occur at the thread processor core and processor package level Thread level C states are available if Intel Hyper Threading Technology is enabled Datasheet 41 i n tel Power Management Figure 4 9 1 dle Power Management Breakdown of the Processor C
170. their architectural state before removing core voltage 38 Datasheet Power Management 4 1 3 Table 4 7 4 1 4 Table 4 8 4 1 5 Table 4 9 4 1 6 5 em I ntegrated Memory Controller States Integrated Memory Controller States Power up CKE asserted Active mode Pre charge Power down deasserted not self refresh with all banks closed Active Power down deasserted not self refresh with minimum one bank active Self Refresh CKE deasserted using device self refresh Link States PCI e Link States Full on Active transfer state First Active Power Management low power state Low exit latency Lowest Active Power Management Longer exit latency Lowest power state power off Longest exit latency DMI States DMI States NN Full Active transfer state LOs First Active Power Management low power state Low exit latency Lowest Active Power Management Longer exit latency Lowest power state power off Longest exit latency I ntegrated Graphics Controller States Table 4 10 1 ntegrated Graphics Controller States Datasheet 39 i n tel I Power Management 4 1 7 Interface State Combinations Table 4 11 G S and C State Combinations Global Sleep Processor processor Core System Clocks Description G State S State C State State Down ss Of exeepe RTC
171. uld study trade offs on VR component accuracy characteristics such as inductors to find the best balance of cost vs performance for their system price and performance targets Thermal Management Features This section will cover thermal management features for the processor Processor Core Thermal Features Occasionally the processor core will operate in conditions that exceed its maximum allowable operating temperature This can be due to internal overheating or due to overheating in the entire system In order to protect itself and the system from thermal failure the processor core is capable of reducing its power consumption and thereby its temperature until it is back within normal operating limits via the Adaptive Thermal Monitor The Adaptive Thermal Monitor can be activated when any core temperature monitored by a digital thermal sensor DTS exceeds its maximum junction temperature and asserts PROCHOT The assertion of PROCHOT activates the thermal control circuit TCC The TCC will remain active as long as any core exceeds its temperature limit Therefore the Adaptive Thermal Monitor will continue to reduce the processor core power consumption until the TCC is de activated The Adaptive Thermal Monitor must be enabled for the processor to remain within specification Adaptive Thermal Monitor The purpose of the Adaptive Thermal Monitor is to reduce processor core power consumption and temperature until it oper
172. vel thermal management To allow for the optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed so that the processor Remains below the maximum junction temperature T specification at the maximum thermal design power TDP e Conforms to system constraints such as system acoustics system skin temperatures and exhaust temperature requirements Thermal specifications given in this chapter are on the component and package level and apply specifically to the processor Operating the processor outside the specified limits may result in permanent damage to the processor and potentially other components in the system Thermal Design Power and Junction Temperature The TDP of an MCP processor is the expected maximum power from each of its components processor core and integrated graphics and memory controller while running realistic worst case applications TDP applications TDP is not the absolute worst case power of each component It could for example be exceeded under a synthetic worst case condition or under short power spikes production a range of power is to be expected from the components due to the natural variation in the manufacturing process The thermal solution at a minimum needs to ensure that the junction temperatures of both components do not exceed the maximum junction temperature Tj max limit while running TDP applications
173. w Card D SO DIMMs at 1066 5 supported 2 1 2 System Memory Timing Support The IMC supports the following DDR3 Speed Bin CAS Write Latency CWL and command signal mode timings on the main memory interface e CAS Latency tRCD Activate Command to READ or WRITE Command delay e PRECHARGE Command Period e CWL CAS Write Latency Command Signal modes 1n indicates a new command may be issued every clock and 2n indicates a new command may be issued every 2 clocks Command launch mode programming depends on the transfer rate and memory configuration Table 2 2 DDR3 System Memory Timing Support Transfer Rate MT s tRCD tRP CWL tCK tCK tCK CMD Mode NOTES 1 System memory timing support is based on availability and is subject to change 2 1 3 System Memory Organization Modes The IMC supports two memory organization modes single channel and dual channel Depending upon how the SO DIMM Modules are populated in each memory channel a number of different configurations can exist Datasheet 21 l n tel Interfaces 2 1 3 1 2 1 3 2 Single Channel Mode In this mode all memory cycles are directed to a single channel Single channel mode is used when either Channel A or Channel B SO DIMM connectors are populated in any order but not both Dual Channel Mode Intel Flex Memory Technology Mode The IMC supports Intel Flex Memory Technology Mode This mode combines the
174. with the total amount of memory in each channel being the same Datasheet Interfaces Note 2 1 3 2 2 intel When both channels are populated with the same memory capacity and the boundary between the dual channel zone and the single channel zone is the top of memory IMC operates completely in Dual Channel Symmetric mode The DRAM device technology and width may vary from one channel to the other Dual Channel Asymmetric Mode This mode trades performance for system design flexibility Unlike the previous mode addresses start at the bottom of Channel A and stay there until the end of the highest rank in Channel A and then addresses continue from the bottom of Channel B to the top Real world applications are unlikely to make requests that alternate between addresses that sit on opposite channels with this memory organization so in most cases bandwidth is limited to a single channel This mode is used when Intel Flex Memory Technology is disabled and both Channel A and Channel B SO DIMM connectors are populated in any order with the total amount of memory in each channel being different Figure 2 3 Dual Channel Symmetric Interleaved and Dual Channel Asymmetric Modes 2 1 4 Datasheet Dual Channel Interleaved Dual Channel Asymmetric memory sizes must match memory sizes can differ Rules for Populating Memory Slots In all modes the frequency of system memory
175. xpress Graphics Transmit 6 115 01 Differential Pair PCI Express PEG ICOMPI PCI Express Graphics Input Current Compensation PEG PCI Express Graphics Output Current Compensation A PEG RCOMPO PCI Express Graphics Resistance Compensation A PEG RBIAS PCI Express Resistor Bias Control A Datasheet 75 n tel I Signal Description 6 5 Embedded DisplayPort eDP Embedded Display Port Signals Type eDP_TX 3 0 Embedded DisplayPort Transmit Differential 6 eDP TX4 3 0 Pair Nominally eDP TX 3 0 is multiplexed PCI Express with PEG TX 12 15 and eDP_TX 3 0 is multiplexed with TX 12 15 When reversed TX 3 0 is multiplexed with PEG TX 3 0 and eDP_TX 3 0 is multiplexed with TX 3 0 1 0 eDP_AUX Embedded DisplayPort Auxiliary Differential eDP_AUX Pair Nominally eDP_AUX is multiplexed with PCI Express PEG_RX 13 and eDP_AUX is multiplexed with PEG_RX 13 When reversed eDP_AUX is multiplexed with PEG_RX 2 and eDP_AUX is multiplexed with PEG_RX 2 eDP_HPD Embedded DisplayPort Hot Plug Detect Nominally eDP HPD is multiplexed with PCI Express PEG RX 12 When reversed eDP_HPD is multiplexed with RX 3 eDP ICOMPI Embedded DisplayPort Input Current Compensation Multiplexed with PEG ICOMPI A eDP Embedded DisplayPort Output Current and Resistance Compensation Multiplexed with A PEG ICOMPO eDP RCOMPO Embedded DisplayPort Resistance Co
176. z Proc 10 5 Proc 7 Int Gfx 4 Int 11 10 5 7 Int Gfx 4 Int Gfx 11 Hd 17 5 B ul ul ul ul Datasheet 55 n tel gt Thermal Management Table 5 17 Intel Celeron Mobile Processor P4000 Series Dual Core SV Thermal Power Specifications Power Sharing Design Points Int Gfx Extreme W amp 7 Controller 9C MCP Thermal Power Limit W S5 T Processor number CPU Core W Int Gfx amp z Controller w Pkg Concurrent Power w 13 CPU Core GHz Int Gfx MHz CPU Core Extreme W 97 Int Gfx amp Memory rw us xs seme NA Rees pus zs sse wa wa W WX 5 1 3 Idle Power Specifications The idle power specifications in Table and Table 5 18 are not 10096 tested These power specifications are determined by the characterization of the processor currents at higher temperatures and extrapolating the values for the junction temperature indicated Table 5 18 18 W Ultra Low Voltage ULV Processor Idle Power 56 Datasheet Thermal Management l n tel I Table 5 19 35 W Standard Voltage SV Processor Idle Power Idle power in the Package Cle state Idle power in the Package C3 state 5 1 4 I ntelligent Power Sharing Control Overview Based upon knowledge of the processor core and integrated graphics and memory controller thermal power performance state and temperature power sharing c

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