Dataram DTM64343A memory module
Contents
1. Ed WW Optimizing Value and Performance Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 18 75 mm high Operating Voltage 1 5V 0 075 I O Type SSTL_15 On board DC temperature sensor with integrated serial presence detect SPD EEPROM Data Transfer Rate 10 6 Gigabytes sec Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 6 7 8 and 9 Bi Directional Differential Data Strobe signals SDRAM Addressing Row Col Bank 15 10 3 Fully ROHS Compliant Pin Configuration 4GB 240 Pin 2Rx8 Registered ECC DDR3 VLP DIMM Identification DTM64343A 512Mx72 4GB 2Rx8 PC3 10600R 9 10 LO Performance range Clock Module Speed CL trep Ze 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Description DTM64343A is a registered 512Mx72 memory module which conforms to JEDEC s DDR3 PC3 10600 standard The assembly consists of two Ranks Each Rank is comprised of nine 256Mx8 DDR3 Hynix SDRAMs One 2K bit EEPROM is used for Serial Presence Detect and a combination register PLL with Address and Command Parity is also used Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals in a fly by topology A thermal sensor can2. Fast exit 630 mA Precharge Quiet ce i Standby Current Ipp2Q Precharge quiet standby current 900 mA Precharge Standby vi Currant Ipp2N Precharge standby current 900 mA Active Power Down di Current Ipp3P Active power down current 630 mA Active Standby m Current Ipp3N Active standby current 1080 mA Operating Burst 8 Write Current lbo4W Burst write operating current 1755 mA Operating Burst p S Read Current lbp4R Burst read operating current 1710 mA Burst Refresh Se Current Ipp5B Refresh current 3780 mA Self Refresh D ops Current Ipp6 Self refresh temperature current MAX Tc 85 C 270 mA Operating Bank Interleave Read Ipp7 All bank interleaved read current 2385 mA Current One module rank in this operation the rest in IDD2P slow exit All module ranks in this operation Document 06591 Revision A 6 Jul 2010 Dataram Corporation 2010 Page 6 PDATARAM Optimizing Value and Performance DTM64343A 4GB 240 Pin 2Rx8 Registered ECC DDR3 VLP DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit Internal read command to first data taa 13 125 20 ns CAS to CAS Command Delay tcecp 4 tok Clock High Level Width tcH avg 0 47 0 53 tck Clock Cycle Time tck 1 5 1 875 ns Clock Low Level Width toL avg 0 47 0 53 tck Data Input Hold Time after DQS Strobe tou 65 ps DQ Input Pulse Width toipw 400 p
3. Capacitance T 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO Cck 1 5 2 5 pF Input Capacitance Address BA 2 0 A 15 0 RAS CAS WE Ci 1 5 2 5 pF Input Capacitance Control S 1 0 CKE 1 0 ODT 1 0 Ci 1 5 2 5 i DQ 63 0 CB 7 0 DQS 8 0 DQS 8 0 Input Output Capacitance DMI8 0 TDQS 17 9 Cio 3 5 pF DC Characteristics T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current li 18 18 pA 1 2 Any input 0 V lt VIN lt VDD Output Leakage Current lot 10 10 yA 2 3 OV lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled ee a a a a a a a Ee Document 06591 Revision A 6 Jul 2010 Dataram Corporation 2010 Page 5 PDATARAM DTM64343A EE 4GB 240 Pin 2Rx8 Registered ECC DDR3 VLP DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V eg Max F PARAMETER Symbol Test Condition Value Unit Operating One Bank Active leet Operating current One bank ACTIVATE to PRECHARGE 1035 mA Precharge Current Operating One 3 i Bank Active Read ki cites le One bank ACTIVATE to READ to 1125 mA Precharge Current Precharge Power a i Down Current Ibp2P Precharge power down current Slow exit 216 mA Precharge Power oe Down Current Ipp2P Precharge power down current
4. 0 O VWAW O _ DASR 17 0 ICAS EEANN dE WE W INER DM 8 0 O VW O_DMRIB 0 CKEO W D CKEOR g Ge CREI Nuel gt CKE1R v DECOUPLING EN TDQS 17 3 OM TDQSR 17 9 ODTO nn 9 ODTOR DDSPD erial P ODT1 AM H DE ke ODTIR VDD All Devices PARIN WA ERR_OUT VREF_DQ All SDRAMs GLOBAL SDRAM CONNECTS Cep r LR CLK 1 0 Vss All Devices 120 All 39 OHMS OHMS VREF_CA All SDRAMs BA 2 0 R ICKO LR CLK 1 0 VTT m NI SDRAMs A 15 0 R RESET Weg IRASR SDRAMS ICASR WER VTT JEVENT All 240 OHMS TEMPERATURE MONITOR All 39 OHMS SCL SERIAL PD SDA za CKE 1 0 R SEN ODT 1 0 R 11 0 V SAO SA1 SA2 RS 1 0 VTT SS Document 06591 Revision A 6 Jul 2010 Dataram Corporation 2010 Page 3 INATAKAN Optimizing Value and Performance Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability DTM64343A 4GB 240 Pin 2Rx8 Registered ECC DDR3 VLP DIMM PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TstTORAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperature Operating Tcase 0 95 C Voltage on Vpp relative to Vss Vop 0 4 1 975 V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85 C requires 2X refresh Recommended DC Operating Conditions T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Min
5. Latencies Supported Least Significant Byte CH O Bit0 CL 4 Bit 1 CL 5 Bit 2 CL 6 Bit 3 CL 7 Bit 4 CL 8 Bit 5 CL 9 Bit 6 CL 10 Bit 7 CL 11 E 3C TT I Document 06591 Revision A 6 Jul 2010 Dataram Corporation 2010 Page 8 DRPDATARAM DTM64343A DEE 4GB 240 Pin 2Rx8 Registered ECC DDR3 VLP DIMM CAS Latencies Supported Most Significant Byte Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 15 Bit 3 CL 15 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved Minimum CAS Latency Time tAAmin 13 125ns Minimum Write Recovery Time tWRmin i N oO CH CO Minimum RAS to CAS Delay Time tRCDmin 13 125ns Minimum Row Active to Row Active Delay Time tRRDmin Minimum Row Precharge Delay Time tRPmin 13 125ns Upper Nibbles for tRAS and tRC Bit 3 Bit 0 tRAS Most Significant Nibble Bit 7 Bit 4 tRC Most Significant Nibble 1 Minimum Active to Precharge Delay Time tRASmin Least 36 0ns 20 Significant Byte Minimum Active to Active Refresh Delay Time tRCmin Least Eeer 49 125ns Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Least ESCH 160 0ns Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Most 460 0ns 05 Significant Byte Minimum Internal Write to Read Command Delay Time tWTRmin Minimum Internal Read to Precharge Command Delay
6. Time 7 Sas 3C tRTPmin Upper Nibble for tFAW Bit 3 Bit 0 tFAW Most Significant Nibble Bit 7 Bit 4 Reserved Minimum Four Activate Window Delay Time tFAWmin Least Significant Byte SDRAM Optional Features Bit 0 RZQ 6 Bit 1 RZQ 7 Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support oO SDRAM Drivers Supported Extended Temperature Range Extended Temperature Refresh Rate Auto Self Refresh ASR On die Thermal Sensor ODTS Readout Reserved Reserved Reserved Reserved CH CO Cu Document 06591 Revision A 6 Jul 2010 Dataram Corporation 2010 Page 9 DRPDATARAM DTM64343A DEE 4GB 240 Pin 2Rx8 Registered ECC DDR3 VLP DIMM Module Thermal Sensor Bit 7 Thermal sensor incorporated onto this assembly X Bit 6 Bit 0 Undefined UNUSED 33 59 Reserved UNUSED 00 Module Nominal Height Bit 4 Bit 0 Module Nominal Height max in mm 17 lt h lt 18 03 Bit 7 Bit5 Reserved 0 Module Maximum Thickness Bit 3 Bit 0 Front in mm baseline thickness 1 mm 1 lt ths2 11 Registered DIMM Module Attributes Bits 3 2 of rows of DRAMs on RDIMM 05 Bits 1 0 of registers on RDIMM RDIMM Thermal Heat Spreader Solution Reference Raw Card Used Bit 4 Bit 0 Reference Raw Card OA Bit 6 Bit 5 Reference Raw Card Revision Bit 7 Reserved not installed 00 65 66 Module Specifi
7. 0 Page 1 DRPDATARAM DTM64343A DEE 4GB 240 Pin 2Rx8 Registered ECC DDR3 VLP DIMM Front view L 133 35 R 5 250 9 50 0 374 3 18 75 T 0 738 l O mr Tn 5 00 A 0 197 be der 5 175 47 00 0 204 an 1 850 Se 123 00 4 843 Back view Side view 3 94 Max gt 10 155 Max 4 00 Min 0 157 Min i 1 27 4 10 de 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches D E y e a e ee Document 06591 Revision A 6 Jul 2010 Dataram Corporation 2010 Page 2 DEE 4GB 240 Pin 2Rx8 Registered ECC DDR3 VLP DIMM RSO O E KH DASR4 O DQSRO O a DQSR4 O DMROO TDQSR130 TDQSR9O Ka O Q DAR 39 32 O DQRIZ 0 TDQSR140 DQR 47 40 O TDQSR110 TDQSR15O DARI 55 48 oO DAR 23 16 DQSR3 DQSR3 DMR3 TDQSR12 TDQSR16O DQR 63 56 DQR 31 24 DQSR8 O DQSR8 O DMR8O TDQSR17O0 CBR 7 0 VDD Von TO SDRAMS All All 39 OHMS 100 nF All 39 OHMS 100 nF All 15 OHMS ee 220HMS R LCLK 1 0 een RCLK 1 0 eee ad DQ 63 0 O VWw O _DaARIE3 0 Q 63 0 63 0 ist ANN mei ILCLKIT 0 OU et CBI7 0 O VAW O CBR 7 0 PA A j BAl2 0 R A 15 0 Wv A 15 0 R DQS 17 0 O VVW O DQSR 17 0 IRAS Ay IRASR IDQS 17
8. 43DM2 173 Voo 203 DM4 24 IDQS2 54 Voo 84 DQS4 114 DQ58 144 TDQS11 174 A12 BC 204 NC 25DQS2 55 A11 85 DQS4 115 DQ59 145 Vss 175 A9 205 Vss 26Vss 56 A7 86 Vss 116Vss 146DQ22 176 Voo 206 DQ38 27 DQ18 57 Voo 87 DQ34 117SA0 f147DQ23 177 A8 207 DQ39 28 DQ19 58 A5 38 DQ35 118SCL 148 Vss 178 AG 208 Vss 29Vss 9Ad 89 Vss 119SA2 149DQ28 1179 Vpop 209 DQ44 30 DQ24 60 Voo 90 DQ40 120V 150DQ29 180 A3 210 DQ45 Not used ee Function 211 Vss CB 7 0 Data Check Bits 212 DM5 DQ 63 0 Data Bits 213 TDQS14 DQS 8 0 DQS 8 0 Differential Data Strobes 214 Vss DM 8 0 Data Mask 215 DQ46 TDQS 17 9 Termination Data Strobes 216 DQ47 CK 1 0 CK 1 0 Differential Clock Inputs 217 Vss CKE 1 0 Clock Enables 218 DQ52 ICAS Column Address Strobe 219 DQ53 RAS Row Address Strobe 220 Vss S 3 0 Chip Selects 221 DM6 WE Write Enable 222 TDQS15 A 15 0 Address Inputs 223 Vss BA 2 0 Bank Addresses 224 DQ54 ODT 1 0 On Die Termination Inputs 225 DQ55 SA 2 0 SPD Address 226 Vss SCL SPD Clock Input 227 DQ60 SDA SPD Data Input Output 228 DQ61 Vss Ground 229 Vss Mon Power SPD EEPROM Power Reference Voltage for DQ 230 DM7 Vopspp 231 TDQS16 Vrerpa 232 Vss VREFCA 233 DQ62 Vor 234 DQ63 Event 235 Vss NC 236 Vopspp 237 SA1 238 SDA 239 Vss 240 Vir Reference Voltage for CA Termination Voltage Temperature Sensing No Connection Document 06591 Revision A 6 Jul 2010 Dataram Corporation 201
9. c Section Register Revision Number 68 69 Module Specific Section 7 mm Drive Strength Command Address 71 116 Module Specific Section 3 6 Bit 7 Bit 4 Back in mm baseline thickness 1 mm 1 lt ths2 6 6 6 Module Manufacturer ID Code Least Significant Byte Module Manufacturer ID Code Most Significant Byte Module Manufacturing Location Module Manufacturing Date Module Serial Number Cyclical Redundancy Code CRC Cyclical Redundancy Code CRC Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Document 06591 Revision A 6 Jul 2010 Dataram Corporation 2010 2 1 2 3 4 7 0 mus o0 unused o0 unused Im uusep Im UNUSED 00 datecode serial number He CRC me L 44 A 41 T 54 A A1 52 A a M 4D space 28 34 33 34 3 33 space Page 10 DEE 4GB 240 Pin 2Rx8 Registered ECC DDR3 VLP DIMM 146 147 Module Revision Code DRAM Manufacturer ID Code Least Significant Byte UNUSED 00 DRAM Manufacturer ID Code Most Significant Byte UNUSED 00 150 175 Manufacturer s Specific Data UNUSED 00 176 255 Open for customer use UNUSED 00 Document 06591 Revis
10. imum Typical Maximum Unit Note Power Supply Voltage Vop 1 425 1 5 1 575 V UO Reference Voltage VREFDQ 0 49 Von 0 50 Von 0 51 Voo V 1 UO Reference Voltage VREFCA 0 49 Von 0 50 Von 0 51 Von V 1 Notes 1 The value of Vrer is expected to equal one half Voo and to track variations in the Voo DC level Peak to peak noise on Vrer may not exceed 1 of its DC value DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 ViH DC Vrer 0 1 Vpop V Logical Low Logic 0 Vic Vss Vrer 0 1 V AC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin ac Vrer 0 175 V Logical Low Logic 0 Vit ac Vrer 0 175 V a a a a E S a e E Document 06591 Revision A 6 Jul 2010 Dataram Corporation 2010 Page 4 PDATARAM Optimizing Value and Performance DTM64343A 4GB 240 Pin 2Rx8 Registered ECC DDR3 VLP DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High Vun 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low VIL DIFF DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage relative to VDD 2 Vix Sen 0 150 v
11. ion A 6 Jul 2010 Dataram Corporation 2010 Page 11 me 4GB 240 Pin 2Rx8 Registered ECC DDR3 VLP DIMM Ed WW Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06591 Revision A 6 Jul 2010 Dataram Corporation 2010 Page 12
12. monitor the DIMM module and will signal the memory controller if a temperature limit is exceeded Pin Description Front Side Back Side 1 Vrena 31 DQ25 61 A2 91 DQ41 121 Vss 151 Vss 181 A1 2 Vss 32 Ves 62 Von 92 Vss 122DQ4 152 DM3 182 Von 3 DQO 33 DQS3 63 CK1 93 Dassj123Da5 153 TDQS12 183 Voo 4 DQ1 134DQS3 64 CK1 eu DQS5 f124 Vss 154 Vss 184 CKO 5 Vss 35 Vss 65 Voo 95 Vss 125DMO us DQ30 185 CKO 6 DQS0 36 DQ26 66 Von 96 DQ42 126 TDQS9 156 DQ31 186 Voo 7 DQSO 37 DQ27 67 Vrerca 97 DQ43 127 Vss 157 Vss 187 Event 8 Vss 38 Vss 68 Parin 98 Vss 128DQ6 158 CB4 188 A0 9 DQ2 39CB0 69 VDD 99 Da48 f129Da7 159 CBS 189 Vop 10DQ3 40CB1 70A10 AP 100 DQ49 f130 Vss 160 Vss 190 BA1 11Vss MI Vss 71BA0 101Vss f131DQ12 Wei DM8 191 Von 12DQ8 42 DQS8 72 Voo 102 DQS6f132DQ13 162 TDQS17 192 RAS 13DQ9 43 DQS8 73 WE 103 DQS6 133 Vss 163 Vss 193 SO 14 Ven M Ve 74 ICAS 104Vss 134DM1 f164CB6 194 Von 15 DQS1 45 CB2 75 Voo 105 DQ50 135 TDQS10 165 CB7 195 ODTO 16 DQS1 46 CB3 76 S1 106 DQ51 136 Vss 166 Vss 196 A13 17 Ven WI Vss 77 ODT1 107Vss H 7 DO14 167 NC TEST 197 Ven 18 DQ10 48 Vrr 78 Voo 108 DQ56 j138DQ15 168 RESET 198 S3 NC 19DQ11 49 Vr 79 82 NC 109 DQ57 f139 Vss 169 CKE1 199 Vss 20Vss 50 CKEO 80 Vss 110Vss 140DQ20 170 Voo 200 DQ36 21DQ16 51 Voo 81 DQ32 111 DQS7f141DQ21 171 A15 201 DQ37 22 DQ17 52 BA2 82 DQ33 112 DQS7 f142 Vss 172 A14 202 Vss 23Vss 53 Err Our 83 Vss 113Vss 1
13. s DOS Output Access Time from Clock toasck 255 255 ps Write DQS High Level Width toasH 0 45 0 55 tcxiavg Write DQS Low Level Width toast 0 45 0 55 tck avg DQS Out Edge to Data Out Edge Skew toasa 125 ps Data Input Setup Time Before DQS Strobe tos 30 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tek avg DQS Falling Edge to Clock Setup Time toss 0 2 tek avg Clock Half Period tue minimum of tcy or teL ns Address and Command Hold Time after Clock Du 140 ps Address and Command Setup Time before Clock tis 65 ps Load Mode Command Cycle Time tmRD 4 tck DQ to DQS Hold Lou 0 38 tck avg Active to Precharge Time tras 36 O tREFI ns Active to Active Auto Refresh Time tre 49 125 ns RAS to CAS Delay trep 13 125 ns Average Periodic Refresh Interval 0 C lt Tease lt 85 C tREFI 7 8 us Average Periodic Refresh Interval 0 C lt Tcase lt 95 C tREFI 3 9 us Auto Refresh Row Cycle Time force 160 ns Row Precharge Time tre 13 125 ns Read DQS Preamble Time RPRE 0 9 Note 1 tck avg Read DQS Postamble Time trest 0 3 Note 2 tck avg Row Active to Row Active Delay trRD Max 4nCK 6ns ns Internal Read to Precharge Command Delay trtp Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twpRE 0 9 tok avg Write DQS Postamble Time twest 0 3 tok avg Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min 2 The ma
14. ximum postamble is bound by tHZDQS max Document 06591 Revision A 6 Jul 2010 Dataram Corporation 2010 Page 7 DRPDATARAM DTM64343A DEE 4GB 240 Pin 2Rx8 Registered ECC DDR3 VLP DIMM SERIAL PRESENCE DETECT MATRIX Number of Bytes Used Number of Bytes in SPD Device CRC Coverage Bit 3 Bit 0 SPD Bytes Used 176 92 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 Key Byte DRAM Device Type DDR3 SDRAM 0B Key Byte Module Type Bit 3 Bit 0 Module Type Bit 7 Bit 4 Reserved SDRAM Density and Banks Bit 3 Bit 0 Total SDRAM capacity in megabits Bit 6 Bit 4 Bank Address Bits Bit 7 Reserved SDRAM Addressing Bit 2 Bit 0 Column Address Bits Bit 5 Bit 3 Row Address Bits Bit 7 6 Reserved UNUSED Module Organization Bit 2 Bit 0 SDRAM Device Width Bit 5 Bit 3 Number of Ranks Bit 7 6 Reserved Module Memory Bus Width Bit 2 Bit 0 Primary bus width in bits Bit 4 Bit 3 Bus width extension in bits Bit 7 Bit 5 Reserved Fine Timebase FTB Dividend Divisor CH CH oO Ke Bit 3 Bit 0 Fine Timebase FTB Divisor 52 Bit 7 Bit 4 Fine Timebase FTB Dividend 5 se 1 MTB 10 Medium Timebase MTB Dividend 0 125ns 0 i 2 8 MTB 11 Medium Timebase MTB Divisor 0 125ns 12 SDRAM Minimum Cycle Time tCKmin 1 5ns 3 UNUSED CAS
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