Dataram DTM64328B memory module
Contents
1. 2 Document 06086 Revision A 27 Oct 10 Dataram Corporation 2010 Optimizing Value and Performance IRS1O IRSO PE od pn Coo DQSRO IDQSR4 O 9 DMROO ann DMR4 Q RSEN DQR 7 0 O44 1 0 7 0 RANK 0 7 0 RANK 1 DQR 39 32 0 7 0 RANK 0 0 7 0 RANK 1 DQSR1O m allium DQSR5 ml DQSR1O DQSR5O DMR1O DMR5O TDQSR100 TDQSR14 O DQR 15 8 DQR 47 40 DQSR20 DQSR6 DQSR2 O DQSR6 DMR2O DMR6O TDQSR110 TDQSR15O DQR 23 16 DQR 55 48 DQSR30O DQSR7 DQSR3 DQSR7 DMR3O DMR7O TDQSR12O TDQSR16O DQR 81 24 DQR 63 56 DQSR8 DQSR8 DMR8O TDQSR17O CBRI 7 0 TO SDRAMS VDD VDD All All 39 OHMS 100 nF All 39 OHMS 100 nF 22 OHMS All 15 OHMS on LCLK 1 0 RCLK 1 0 ul O NwNN O ids in Ga d ILCLK 1 0 ov RCLK 1 0 a CB 7 0 O O CBR 7 0 2 0 BA 2 0 R A 15 0 A 14 0 R DQS 8 0 Q NNN O DQSR 8 0 IRAS RASR DQS 8 0 O O DQSR 8 0 ICAS ICASR IWE ANER 8 0 O O DMR 8 0 CKEO A CKEOR i 1 CKE1R V DECOUPLING ODT1 Y ODT1R VDD All Devices PAR_IN ERR_OUT VREF DQ All SDRAMs GLOBAL SDRAM CONNECTS CKO L R CLK 1 0 g Vss All Devices 120 All 39 OHMS OHMS REF_CA All SDRAMs BA 2 0 R CKO IL R CLK 1 02. DIM64328B Optimizing Value and Performance 8 zing Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high Operating Voltage 1 5V 0 075 Type SSTL 15 On board 12 temperature sensor with integrated serial presence detect SPD EEPROM Data Transfer Rate 10 6 Gigabytes sec Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 6 7 8 and 9 Bi Directional Differential Data Strobe signals SDRAM Addressing Row Col Bank 15 10 3 Fully RoHS Compliant Pin Configuration Front Side Back Side 2041 121 Vss 151 Vss 181 A1 152 DM3 182 Vpp 153 TDQS12 183 Vp 154 Vss 184 CKO 211 Vas 214 Veg 185 CKO ee ee 1 ae 212 DM5 4GB 240 2Rx8 Registered ECC DDR3 DIMM Identification DTM64328B 512Mx72 4GB 2Rx8 PC3 10600R 9 10 BO Performance range Clock Module Speed CL trep trp 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Description DTM64328B is a registered 512Mx72 memory module which conforms to JEDEC s DDR3 PC3 10600 standard The assembly is Dual Rank Each Rank is comprised of nine 256Mx8 DDR3 Hynix SDRAMs One 2K bit EEPROM is used for Serial Presence Detect and a combination register PLL with Address
3. X Bit 4 8 X Bit 5 CL 9 X Bit 6 CL 10 Bit 7 CL 11 Document 06086 Revision A 27 Oct 10 Dataram Corporation 2010 Page 8 Optimizing Value and Performance 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM 15 CAS Latencies Supported Most Significant Byte Bit 1 RZQ 7 Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support SDRAM Drivers Supported Extended Temperature Range Extended Temperature Refresh Rate Auto Self Refresh ASR On die Thermal Sensor ODTS Readout Reserved Reserved Reserved Reserved Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 Bit 3 CL 15 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved Minimum CAS Latency Time tAAmin 13 125ns Minimum Write Recovery Time tWRmin 15 0ns Minimum RAS to CAS Delay Time tRCDmin 13 125ns Minimum Row Active to Row Active Delay Time tRRDmin 6 0ns Minimum Row Precharge Delay Time tRPmin 13 125ns 21 Upper Nibbles for tRAS and tRC Bit 3 tRAS Most Significant Nibble 1 Bit 7 Bit 4 tRC Most Significant Nibble 1 22 Minimum Active to Precharge Delay Time tRASmin Least 36 0ns oignificant Byte 23 Minimum Active to Active Refresh Delay Time tRCmin 49 125ns Least Significant Byte 24 Minimum Refresh Recovery Delay Time tRFCmin Least 160 0ns oignificant Byte 25 Minimum Refresh R
4. OxOB 0x02 0x19 0x00 O O 8 OxOB 0x52 gt lt O C gt lt Co Byte Function Hex Number of Bytes Used Number of Bytes in SPD Device CRC Coverage Bit 3 SPD Bytes Used 176 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 Coverage Bytes 0 116 SPD Revision Rev 1 0 2 Key Byte DRAM Device Type DDR3 SDRAM 3 Key Byte Module Type Bit 3 Module Type RDIMM Bit 7 Bit 4 Reserved 0 4 SDRAM Density and Banks Bit 3 Total SDRAM capacity in megabits 1Gb Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved 0 5 SDRAM Addressing Bit 2 Column Address Bits 10 Bit 5 Bit 3 Row Address Bits 15 Bit 7 6 Reserved 0 26 Reserved UNUSED T Module Organization Bit 2 Bit 0 SDRAM Device Width 8 Bits Bit 5 Bit 3 Number of Ranks 2 Rank Bit 7 6 Reserved 0 Module Memory Bus Width Bit 2 Primary bus width in bits 64 Bits Bit 4 Bit 3 Bus width extension in bits 8 Bits Bit 7 Bit 5 Reserved 0 Fine Timebase FTB Dividend Divisor Bit 3 Fine Timebase FTB Divisor 2 Bit 7 Bit 4 Fine Timebase FTB Dividend 5 10 Medium Timebase MTB Dividend 1 MTB 0 125ns 11 Medium Timebase MTB Divisor 8 MTB 0 125ns SDRAM Minimum Cycle Time tCKmin 1 5ns Reserved UNUSED 14 CAS Latencies Supported Least Significant Byte CL 4 5 Bit 2 CL 6 X Bit 3 CL 7
5. V TT All SDRAMs RASR SDRAMS CASR oe EVENT e TEMPERATURE MONITOR ZQ SCL SERIAL PD CKE 1 0 R ODT 1 0 R IRS 1 0 ww VTT Vss Document 06086 Revision A 27 Oct 10 Dataram Corporation 2010 4GB 240 2Rx8 Registered ECC DDR3 DIMM SA2 SA1 Page 3 Optimizing Value and Performance 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability Ambient Temperature Operating TA Oo 70 C DRAM Case Temperature Operating Tos 0 95 C Voltage on Vpp relative to Vss V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note I O Reference Voltage 0 49 0 50 0 51 Voo 1 I O Reference Voltage VREFCA 0 49 Vpp 0 50 Vpp 0 51 Vpp 1 Notes 1 The value of Vrer is expected to equal one half Vpp and to track variations the Vpp DC level Peak to peak noise on Vrer may not exceed 1 of its DC value For Reference Vpp 2 15 mV DC Input Logic Levels Single Ended T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Unit Logical Low
6. and Command Parity is also used Both output driver strength and input termination impedance are programmable to maintain signal integrity on the signals in a Fly by topology A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating temperature of 95C Pin Description lt 10003 11 Vas 12 DQ8 13 DQ9 14 Vss 15 DQS1 16 0051 d ss 180010 190011 20 Vss 210016 220017 28 Vss 24 2052 25 DQS2 26 Vss 270018 280019 29 Vss 30 DQ24 108 DQ56 109 DQ57 110 Vss Not used 155 DQ30 156 DQ31 157 Vss 158 CB4 159 CB5 160 Vss 161 DM8 162 TDQS17 163 Vas 164 CB6 186 Vpp 187 Event 188 A0 189 Vpp 190 BA1 191 Vpp 192 RAS 193 S0 194 Vpp 195 ODTO 196 A13 167 NC 197 Voo 168 RESET 169 CKE1 170 Vpp 171A15 198 83 NC 199 Vss 200 DQ36 201 DQ37 202 Vss 203 DM4 205 Vas 206 DQ38 207 DQ39 208 Vas 2090044 210 0045 Function CB 7 0 Data Check Bits DQ 63 0 Data Bits 213 TDQS14 DQS 8 0 DQS 8 0 Differential Data Strobes DM 8 0 Data Mask TDQS 17 9 Termination Data Strobe 2150046 2162047 247 Ve 218 DQ52 219 DQ53 220 Vss 221 DM6 CK 1 0 CK 1 0 222 ITDQS15 A 15 0 223 Vss 224 DQ54 225 DQ55 226 Vss 227 DQ60 228 DQ61 229 Vss 230 DM7 231 TDQS16 232 Vas 233 DQ62 204 TDQS13 234 DQ63 235 Vss 236 Vopspp 237 SA1 238 SDA 239 Vss 240 Vr Di
7. m5 ps Data Input Setup Time Before DQS Strobe ts 30 DQS Falling Edge from Clock Hold Time ton 02 DGS Falling Edge to Clock Setup Time s o tck avg Address and Command Hold Time after Clock Fx y o ps Address and Command Setup Time before Clock tis 6 e ps Load Mode Command Cycle Time tw e Active to Precharge Time ns Active to Active Auto Refresh Time amp 49125 n Average Periodic Refresh Interval 0 C lt Tcase lt 85 C 0 7 78 Us Average Periodic Refresh Interval 0 C lt Tcase lt 95 C otn 39 Us Auto Refresh Row Cycle Time tee 160 i ns Row Precharge Time GERNE ns Read DQS Preamble Time tere 09 tck avg Read DQS Postamble Time tck avg Row Active to Row Active Delay tko Max 4nCK 6ns ns Internal Read to Precharge Command Delay tare Max 4nCK 7 5ns ns Write DQS Preamble Setup Time Write DQS Postamble Time Xe H Write Recovery Time pw 15 n Internal Write to Read Command Delay lwTR 4 7 5ns ns Notes 1 maximum preamble is bound by tLZDQS min 2 The maximum postamble is bound by tHZDQS max Document 06086 Revision A 27 Oct 10 Dataram Corporation 2010 Page 7 Optimizing Value and Performance SERIAL PRESENCE DETECT MATRIX 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM 0x92 0x10
8. to READ to Precharge Current Precharge Power T PCIE E ULLLLLL power down current Slow exit Ipp2P mA Down Current Precharge Power 2 power down current Fast exit Ipp2P mA Down Current Precharge Quiet o2Q Precharge quiet standby current EJ TA Standby Current Precharge Standby Precharge standby current 540 WA Current Active Power Down Iap3P Active power down current 270 mA Current Active Standby Active standby current 630 MA Current Operating Burst Burst write operating current Operating Burst Burst read operating current Read Current Ipp4R os NS Burst Refresh e Refresh current Self refresh temperature current Tc 85 246 mA Operating Bank interleave Read lop7 All bank interleaved read current 1323 mA Current One module rank in this operation the rest in IDD2P slow exit All module ranks in this operation Document 06086 Revision A 27 Oct 10 Dataram Corporation 2010 Page 6 Optimizing Value and Performance 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM AC Operating Conditions Internal read command to first data ns CAS to CAS Command Delay enn Clock High Level Width tox Clock Low Level Width tox Data Input Hold Time after DQS Strobe tu S ps DQ Input Pulse Width tw 400 ps DQS Output Access Time from Clock ps Write DQS High Level Width Write DQS Low Level Width tox avg DQS Out Edge to Data Out Edge Skew was T
9. Logic 0 DC i 0 1 V AC Input Logic Levels Single Ended 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Merimum Unit Logical Low Logic 0 D AC Vner 0 175 V Document 06086 Revision A 27 Oct 10 Dataram Corporation 2010 Page 4 Optimizing Value and Performance 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM Differential Input Logic Levels 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage relative to VDD 2 Vix 0 150 0 150 V Capacitance T4 25 C f 100 MHz 00163 0 7 0058 0 DQS 8 0 Cio pF Input Output Capacitance DM 8 0 TDQS 17 9 DC Characteristics T4 0 to 70 C Voltage referenced to Vss Input Leakage Current Le Any input 0 V VIN VDD lot 10 10 UA 2 3 Output Leakage Current OV lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled Document 06086 Revision A 27 Oct 10 Dataram Corporation 2010 Page 5 Optimizing Value and Performance 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM lbp Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss alue Precharge Current Operating One Operating current One bank ACTIVATE
10. SA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06086 Revision A 27 Oct 10 Dataram Corporation 2010 Page 12
11. ecovery Delay Time tRFCmin Most 160 0ns oignificant Byte 26 Minimum Internal Write to Read Command Delay Time f 5ns tWTRmin 2f Minimum Internal Read to Precharge Command Delay Time 7 5ns tRTPmin 20 Upper Nibble for tFAW Bit 3 tFAW Most Significant Nibble 0 Bit 7 Bit 4 Reserved 0 29 Minimum Four Activate Window Delay Time tFAWmin 30 0ns Least Significant Byte 30 SDRAM Optional Features Bit 0 RZQ 6 X NU 3 32 Reserved 0x00 C gt lt x C gt lt gt 0x01 C gt Co Document 06086 Revision A 27 Oct 10 Dataram Corporation 2010 Page 9 DTM64328BB 1 acu AGB 240 2Rx8 Registered ECC DDR3 DIMM 33 59 Reserved UNUSED 0x00 Module Nominal Height Bit 4 Module Nominal Height max in mm 29 h 30 Bit 7 Bit5 Reserved 0 6 Module Maximum Thickness 0x11 Bit 3 Bit 0 Front in mm baseline thickness 1 mm 1 lt th lt 2 Bit 7 Bit 4 Back in mm baseline thickness 1 mm 1 lt th lt 2 62 Reference Raw Card Used 0x01 Bit 4 Reference Raw Card R C B Bit 6 Bit 5 Reference Raw Card Revision Rev O Bit 7 Reserved 0 63 Address Mapping from Edge Connector to DRAM 0x05 Bit 0 Rank 1 Mapping Registered DIMM Reserved Bit 7 Bit 1 Reserved 33 59 Module Specific Section UNUSED 0x00 Regist
12. er Revision Number Module Specific Section UNUSED Module Specific Section P 0x50 Module Specific Section UNUSED 0x00 Module Specific Section UNUSED Module Specific Section UNUSED 0x00 Module Manufacturer ID Code Least Significant Byte Module Manufacturer ID Code Most Significant Byte 0x91 Module Manufacturing Location UNUSED Module Manufacturing Date 0x20 Module Serial Number Cyclical Redundancy Code CRC CRC 0x20 Cyclical Redundancy Code CRC CRC Module Part Number 0x20 Module Part Number D Module Part Number A 0x41 Module Part Number T Module Part Number A 0x41 Module Part Number R Module Part Number A 0x41 Module Part Number M Module Part Number 0x20 Module Part Number 6 Module Part Number 4 0x34 Module Part Number 3 Module Part Number 2 0x32 Module Part Number 8 Module Part Number 0x20 Module Revision Code DRAM Manufacturer ID Code Least Significant Byte UNUSED 0x00 Document 06086 Revision A 27 Oct 10 Dataram Corporation 2010 Page 10 DTM64328B Optimizing Value and Performance 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM DRAM Manufacturer ID Code Most Significant Byte UNUSED 150 175 Manufacturer s Specific Data UNUSED 176 255 Open for customer use UNUSED Document 06086 Revision A 27 Oct 10 Dataram Corporation 2010 Page 11 AGB 240 2Rx8 Registered ECC DDR3 DIMM OO ptimizing Value and Performance DATARAM CORPORATION U
13. fferential Clock Inputs CKE 1 0 Clock Enables ICAS Column Address Strobe RAS Row Address Strobe S 3 0 Chip Selects AVE Write Enable Address Inputs BA 2 0 Bank Addresses ODT 1 0 On Die Termination Inputs SA 2 0 SPD Address SCL SPD Clock Input SDA SPD Data Input Output EVENT Temperature Sensing RESET Reset for register and DRAMs PAR_IN Parity bit for Addr Ctrl ERR_OUT Error bit for Parity Error A12 BC Combination input Addr12 Burst Chop A10 AP Combination input Addr10 Auto precharge Vss Ground Voppspp SPD EEPROM Power VREFDO Reference Voltage for DQ s VREFCA Reference Voltage for CA Termination Voltage NC No Connection Document 06086 Revision A 27 Oct 10 Dataram Corporation 2010 Page 1 7 DTM64328B Optimizing Value and Performance 4GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM DATARA Front view 133 35 5 250 9 50 0 374 30 00 1 181 17 30 0 681 5 00 25 0 197 am 5 175 gla 47 00 71 00 gt 0 204 1 850 2 795 123 00 i 4 843 Back view Side view 4 00Max 0 157 Max 4 00 Min 0 157 Min 1 27 10 zs 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches
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