Dataram DTM63310P memory module
Contents
1. Front view la 133 35 5 250 10 00 oma 0 394 30 00 _ G 1 181 T D Cc i 17 78 0 700 O ANANAnNNANANANAANANAANAANANAANAANAANANAANAAANAAN _oonononononononononon NMN e Y o ot 2 54 Min 0 100 Min 5 18 63 00 55 00 0 204 in 2 480 2 165 gt 123 00 a i 4 843 Back view Side view 3 94Max 7 0 155 Max D C 4 06 Min 2 G 0 160 Min O NNNMNNN NNNnnn nnn NNNnnn NNNANNNNNNMNMNNANMNN O 1 27 10 ke 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches eee Document 06454 Revision E 24 MAR 08 Dataram Corporation 2008 Page 2 DTM63310 1 GB 128Mx72 240 Pin Registered DDR2 DIMM VSS RSO O _ SCL SERIAL PD SDA WP paso DQS9 O DQSO DAS9 O SA0 SA1 SA2 DQS DQS CS DM DQS DAR 3 0 O 1 0 3 0 DQR 7 4 VO 3 0 bast DQS10 DECOUPLING DQS1 DQS10 DQS DQS CS DM DQS V ppspp t Serial PD DQR 11 8 O 1 0 3 0 DQR 15 12 VO 3 0 VDD AI SDRAMs VREF All SDRAMs pas2 pasi1 Vss E All SDRAMs DQS2 Das11 DAS DAS CS DM DAS DQR 19 16 O 1 0 3 0 DQ2. Byte Function Value Hex 0 Number of Serial PD Bytes written during module production 128 bytes 80 1 Total number of Bytes in Serial Presence Detect device 256 bytes 08 2 Fundamental Memory Type DDR2 08 3 Number of Row Addresses 14 OE 4 Number of Column Addresses 11 0B 5 Module Attributes Number of Ranks Package and Height 60 bits 0 through 2 number of Ranks 1 bit 3 Card on Card No bit 4 DRAM Package Planar bits 5 through 7 Module Height 30mm 6 Module Data Width 72 48 7 Reserved UNUSED 00 8 Voltage Interface Level of this assembly SSTL 1 8V 05 9 SDRAM Cycle time at highest CAS Latency 5ns 50 10 SDRAM Access from Clock time at highest CAS Latency tac 0 6 ns 60 11 DIMM configuration type ECC 02 7 8 us 12 Refresh Rate Type eE 13 Primary SDRAM Width 4 04 14 Error Checking SDRAM Width 4 04 15 Reserved UNUSED 00 16 SDRAM Device Attributes Burst Lengths Supported 0C bits 0 and 1 undefined bit 2 Burst Length 4 yes bit 3 Burst Length 8 yes bits 4 through 7 undefined 17 SDRAM Device Attributes Number of Banks on SDRAM Device 4 04 18 SDRAM Device Attributes CAS Latency 38 bits 0 and 1 undefined bit 2 Latency 2 bit 3 Latency 3 yes bit 4 Latency 4 yes bit 5 Latency 5 yes bits 6 and 7 undefined 19 Reserved UNUSED 00 2
3. Front Side Back Side Name Function 1 VREF 31DQ19 61A4 91 GND 121GND 151 GND 181 VDD 211 Das14 ICAS Column Address Strobe 2 GND 32GND_ 62vDD 92 Das5 fi22 Da4 152 Da28 sf4182 A3 212 DQS14 Err_Out Parity Error Found 3 DQO 33 DQ24 63A2 93 DaSS5 123 Da5 153 DQ29 183 A1 213 GND IRAS Row Address Strobe 4 pat 34paQ25 e4svDoD jo4 GND 124 GND 154 GND f184vDD 214 page RESET Register and PLL Reset 5 GND 35GND 65GND 95 Da42 1125 Dasa 155 DQS12 185 CKO 215 DQ47 S 1 0 Chip Selects 6 DQSO 36 DQS3 66 GND 96 DQ43 126 DaSO 156 DQS12 186 CKO 216 GND MWNE Write Enable 7 paso l37pDas3 67 VDD 7 GND fi27GeND 157 GND 187 VDD 217 DQ52 A 15 0 Address Inputs 8 GND 38GND_ 68 Par_In I98 DaQ48 128 Dae 158 Da30 J188 AO 218 DQ53 BA 2 0 Bank Addresses 9 DQ2 39DQ26 69 VDD 99 DQ49 129 Da7 159 DQ31 189 VDD 219 GND CBI7 0 Data Check Bits 10DQ3 40DQ27 70A10 100 GND 130 GND 160 GND 190 BA1 220 NC CKO CKO Differential Clock Inputs 11GND 41GND_ 71BAO 101 SA2 131 DQ12 161 cB4 191 VDD 221 NC CKE 1 0 Clock Enables 12DQ8 42 CBO 72VDD 102NC 132 DQ13 162 cB5 f192 RAS 222 GND DQI63 0 Data Bits 13 DQ9 43 CB1 73 WE 103 GND 133 enD 163 GND _ 193 SO 223 DQS15 DQS 17 0 DQS 17 0 Differential Data Strobes 14GND 44GND_ 74 CAS_ 104 DQS6 134 Das10 164 DaS17 194 VDD 224 DQS15 GND Ground 15 DQS1 45 DQS8 75 VDD 105 Dase 135 DQS10 165 DQS17 195 ODTO 225 GND NC No Connection 16 DQs1
4. Features 240 pin JEDEC compliant DIMM DTM63310 1 GB 128Mx72 240 Pin Registered DDR2 DIMM Operating Voltage 1 8 V 0 1 VO Type SSTL_18 Data Transfer Rate 400 MHz Data Bursts 4 or 8 bits Sequential or Interleaved ordering Error Checking and Correction ECC bits Programmable I O driver strength OCD Programmable On Die Termination ODT Programmable CAS Latency 3 4 or 5 Differential Single Ended Data Strobe signals SDRAM Addressing Row Col Bank 14 11 2 Fully ROHS Compliant Pin Configuration Identification DTM63310 128Mx72 Performance range Clock Module Speed CL trep trpe 200 MHz DDR2 400 3 3 3 Description DTM63310 is a Registered 128Mx72 memory module which conforms to JEDEC s DDR2 PC2 3200 standard The assembly is comprised of one Rank of eighteen DDR2 DRAMs two Registers one Phase Locked Loop PLL and one 2K bit EEPROM used for Serial Presence Detect Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals Error Checking and Correction bits are provided to ensure data integrity The module will support advanced ECC features Chipkill and Intel SDDC The eighteen Data Strobe signals may be used either as nine differential pairs or as eighteen single ended strobes for use in systems with a mix of x4 and x8 DRAMs Pin Description
5. 46 pasa 76 Si 106 GND 136 GND 166 GND 196 A13 226 DQ54 ODT 1 0 On Die Termination Inputs 17 GND 47GND_ 77 oDT1 107 Das0 137 NC 167 CB6 197 VDD 227 Dass Par_In Parity Bit Address amp Control 18 RESET 48 CB2 78 VDD 108 Das1 138 NC 168 CB7 198 GND 228 GND SA 2 0 SPD Address 19 NC 49 CB3 79GND 109 GND 139 GND 169 GND 199 Da36 229 DAGO SCL SPD Clock Input 20 GND 50GND 80 DQ32 110 Das6 140 DQ14 170 vDD 200 Da37 230 DQ61 SDA SPD Data Input Output 21DQ10 51 VDD 81 DQ33 111 Da57 f41 DQ15 171 CKE1 201 GND 231 GND VDD Power 22 DQ11 52CKEO 82GND 112 GND fi42 GND 172 VDD 202 DQS13 232 DQS16 VDDSPD SPD EEPROM Power 23 GND 53vDD 83 DQS4 113 DQS7 143 DQ20 173 A15 203 DQS13 233 DQS16 VREF Reference Voltage 24 DQ16 54 BA2 84 Das4 114 DQS7 144 DQ21 J174 A14 204 GND 234 GND 25 DQ17 55 Err_Out 85 GND 115 GND f45 enD 175 VDD 205 DQ38 235 DQ62 26 GND 56VDD s6 Da34 116 Da58 146 Das11 176 A12 206 DQ39 236 DQ63 27 DQS2 57 A11 87 DA35 117 DQ59 147 DQS11 177 A9 207 GND 237 GND 28 DQS2 58 A7 88 eND 118 GND i48 enD 178 VDD 208 DQ44 238 VDDSPD 29GND 59 vDD 89DQ40 119 spa f49 DQ22 179 A8 209 DQ45 239 SAO 30 DQ18 60 A5 90 DQ41 120 SCL 150 Da23 180 a6 210 GND 240 SA1 Not Used Document 06454 Revision E 24 MAR 08 Dataram Corporation 2008 Page 1 DATARAM DTM63310 1 GB 128Mx72 240 Pin Registered DDR2 DIMM
6. 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06454 Revision E 24 MAR 08 Dataram Corporation 2008 Page 10
7. CS is HIGH C Ipp5 between valid commands Other control and address bus inputs 3790 mA urrent Peas P ara are switching Data bus inputs are switching Self Refresh loo6 CK and CK at 0 V CKE lt 0 2 V Other control and address bus 290 mA Current ae inputs are floating Data bus inputs are floating All bank interleaving reads lout 0 mA BL 4 CL 3 tcx ee T a loo AL 70 ns taro 7 5 ns CKE is HIGH CS is HIGH between Aa nA valid commands Address bus inputs are stable during deselects Data bus inputs are switching Current Notes 1 For all IbbX measurements tek 5 ns tre 60 ns trcp 15 ns tras 45 ns and tre 15 ns unless otherwise specified 2 All IboX values shown are worst case maximums considering all DRAMs Registers and the PLL Document 06454 Revision E 24 MAR 08 Dataram Corporation 2008 Page 6 DTM63310 DATARAM 1 GB 128Mx72 240 Pin Registered DDR2 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit DQ Output Access Time from Clock tac 0 60 ns CAS io CAS Command Delay tceco 2 tck Clock High Level Width tcH 0 45 0 55 tck Clock Cycle Time tck 5000 8000 ps Clock Low Level Width teL 0 45 0 55 tck Data Input Hold Time after DQS Strobe toH 0 28 ns DQ Input Pulse Width toipw 0 35 tck DQS Output Access Time from Clock toasck 500 500 ps Write DQS High
8. Data Input Hold Time after Strobe ton 0 28 ns 28 36 Write Recovery Time twr 15 ns 3C 37 Internal Write to Read Command Delay twtr 10 ns 28 38 Internal Read to Precharge Command Delay trtp 7 5 ns 1E 39 Memory Analysis Probe Characteristics UNUSED 00 40 Extension of Byte 41 trc and Byte 42 trec 00 Add this value to byte 41 Ons Add this value to byte 42 Ons 41 Minimum Active to Active Auto Refresh Time trc 60 ns 3C 42 Minimum Auto Refresh to Active Auto Refresh Command Period trrc 105 ns 69 43 Maximum Cycle Time tck max 8 ns 80 44 DQS DQ Skew for DQS amp associated DQ Signals toasa 0 35 ns 23 45 Read Data Hold Skew Factor tans 0 45 ns 2D 46 PLL Relock Time 15 us OF 47 61 Reserved UNUSED 00 62 SPD Revision Revision 1 0 10 63 Checksum for Bytes 0 62 checksum F2 64 Module Manufacturer s JEDEC ID Code Dataram ID 7F 65 Module Manufacturer s JEDEC ID Code Dataram ID 91 66 71 Module Manufacturer s JEDEC ID Code UNUSED 00 72 Module Manufacturing Location UNUSED 00 73 90 Module Part Number UNUSED 00 91 92 Module Revision Code UNUSED 00 93 94 Module Manufacturing Date UNUSED 00 95 98 Module Serial Number serial number 99 127 Manufacturer s Specific Data UNUSED 00 Document 06454 Revision E 24 MAR 08 Dataram Corporation 2008 Page 9 DTM63310 Ya Pal Vai 1GB 128Mx72 240 Pin Registered DDR2 Dimm DATARAM DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543
9. Other control and 890 mA Standby Current P9 address bus inputs are stable Data bus inputs are floating Precharge Standby lon2N All banks idle CKE is HIGH CS is HIGH Other control and 1000 mA Current uD address bus inputs are switching Data bus inputs are switching All banks open CKE is LOW Other control and address bus Active PowerDown Ipp3P inputs are sable Data bus inputs are floating Fast Power down 980 mA Current exit Mode Register bit 12 0 Active Power Down All banks open CKE is LOW Other control and address bus lbb3P inputs are stable Data bus inputs are floating Slow Power down 710 mA Current A 7 exit Mode Register bit 12 1 All banks open tras 70 ms CKE is HIGH CS is HIGH between Active Standby Ipp3N valid commands Other control and address bus inputs are 1630 mA Current setae eae switching Data bus inputs are switching All banks open Continuous burst writes BL 4 CL 3 tcx Operating Burst lon4W AL 0 tras 70 ms CKE is HIGH CS is HIGH between valid 2800 mA Write Current RD commands Address bus inputs are switching Data bus inputs are switching All banks open Continuous burst reads lout 0 mA BL 4 CL 3 tck AL 0 xx tras 70 ms CKE is HIGH CS is HIGH Operating Burst Read Current Ipp4R between valid commands Address bus inputs are switching Data 2980 mA bus inputs are switching Burst Refresh Refresh command at every 75 ns CKE is HIGH
10. 0 DIMM type information 01 bit 0 Regular RDIMM 133 35mm yes bit 1 Regular UDIMM 133 35mm no bit 2 SODIMM 67 6mm no bit 3 Micro DIMM 45 5mm no bit 4 Mini RDIMM 82 0mm no bit 5 Mini UDIMM 82 0mm no bits 6 and 7 undefined no 21 Module Attributes 00 bits 0 through 3 undefined bit 4 FET Switch External Enable no bit 5 undefined bit 6 Analysis probe installed no bit 7 undefined 22 SDRAM Device Attributes General 00 bit 0 Supports Weak Driver no bits 1 through 7 undefined 23 Minimum Clock Cycle Time at Reduced CAS Latency CL X 1 5 ns 50 24 Maximum Data Access Time tac from Clock at CL X 1 0 6 ns 60 Document 06454 Revision E 24 MAR 08 Dataram Corporation 2008 Page 8 DTM63310 DATARAM 1 GB 128Mx72 240 Pin Registered DDR2 DIMM 25 Minimum Clock Cycle Time at Reduced CAS Latency CL X 2 5 50 26 Maximum Data Access Time tac from Clock at CL X 2 0 6 60 27 Minimum Row Precharge Time tre 15 ns 3C 28 Minimum Row Active to Row Active Delay trrp 7 5 ns 1E 29 Minimum RAS to CAS Delay trep 15 ns 3C 30 Minimum Active to Precharge Time tras 45ns 2D 31 Module Rank Density 1GB 01 32 Address and Command Setup Time before Clock tis 0 50 ns 50 33 Address and Command Hold Time after Clock tin 0 50 ns 50 34 Data Input Setup Time before Strobe tps 0 15 ns 15 35
11. ARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current lu 5 5 HA Output Leakage Current loz 5 5 pA 2 Output Minimum Source DC Current loH 13 4 mA 3 Output Minimum Sink DC Current lot 13 4 mA 4 Notes 1 These values are guaranteed by design and are tested on a sample basis only 2 DQx and ODT are disabled and 0 V lt Vout lt Vpp 3 Voo 1 7 V Vout 1420 mV Vour Voo lon must be less than 21 Ohms for values of Vout between Von and Vono 280 mV 4 Vpp 1 7 V Vout 280 mV Vour lo must be less than 21 Ohms for values of Vout between 0 V and 280 mV Document 06454 Revision E 24 MAR 08 Dataram Corporation 2008 Page 5 DTM63310 DATARAM 1 GB 128Mx72 240 Pin Registered DDR2 DIMM lbo Specifications and Conditions Voltages referenced to Vss 0 V wa Max PARAMETER Symbol Test Condition Value Unit Operating One CKE is HIGH CS is HIGH between valid commands Address Ban ACHVE l0 bus inputs are switching Data bus inputs are switching 2520 mA Precharge Current Operating One lout 0 mA BL 4 CL 5 ns AL 0 CKE is HIGH CS is Bank Active Read Ipp1 HIGH between valid commands Address bus inputs are 2600 mA Precharge Current switching Precharge Power Ipp2P All banks idle CKE is LOW Other control and address bus inputs 530 mA Down Current Be are stable Data bus inputs are floating Precharge Quiet lpp2Q All banks idle CKE is HIGH CS is HIGH
12. Level Width toasH 0 35 tox Write DQS Low Level Width toast 0 35 tex DQS Out Edge to Data Out Edge Skew toasa 350 ps Data Input Setup Time Before DQS Strobe tos 0 15 ns DQS Falling Edge from Clock Hold Time tosH 0 2 tck DQS Falling Edge to Clock Setup Time toss 0 2 tck Clock Half Period tue minimum of tcy or teL ns Address and Command Hold Time after Clock tin 0 5 ns Address and Command Setup Time before Clock tis 0 5 ns Load Mode Command Cycle Time turD 2 tck DQ to DQS Hold ton tup tans Data Hold Skew Factor tans 450 ps Active to Precharge Time tras 45 120K ns Active to Active Auto Refresh Time tre 60 ns RAS to CAS Delay trop 15 ns Average Periodic Refresh Interval REFI 7 8 us Auto Refresh Row Cycle Time tRFC 75 ns Row Precharge Time tre 15 ns Read DQS Preamble Time RPRE 0 9 1 1 tox Read DQS Postamble Time test 0 4 0 6 tck Row Active to Row Active Delay RRD 7 5 ns Internal Read to Precharge Command Delay tRTP 7 5 ns Write DQS Preamble Setup Time twpres 0 ps Write DQS Postamble Time twest 0 4 0 6 tck Write Recovery Time twr 15 ns Internal Write to Read Command Delay twtr 10 ns Exit Self Refresh to Non Read Command txsnr trec min 10 ns Exit Self Refresh to Read Command txsrp 200 tck Document 06454 Revision E 24 MAR 08 Dataram Corporation 2008 Page 7 DTM63310 DATARAM 1 GB 128Mx72 240 Pin Registered DDR2 DIMM Serial Presence Detect Contents
13. Low Logic 0 Vilac Vrer 0 250 V ee Document 06454 Revision E 24 MAR 08 Dataram Corporation 2008 Page 4 DTM63310 DATARAM 1 GB 128Mx72 240 Pin Registered DDR2 DIMM Differential Input Logic Levels Voltages referenced to Vss 0 V PARAMETER Svmbol Minimum Maximum Unit Note DC Input Signal Voltage Vinc 0 300 Vpp 0 300 V 1 DC Differential Input Voltage Vipioc 0 250 Voo 0 600 V 2 AC Differential Input Voltage Vinac 0 500 Vpp 0 600 V 3 AC Differential Cross Point Voltage Vixac 0 50 Vpb 0 175 0 50 Vpp 0 175 V 4 Notes 1 Vinoc specifies the allowable DC excursion of each input of a differential pair 2 Vipco specifies the input differential voltage i e the absolute value of the difference between the two voltages of a differential pair 3 Viac Specifies the input differential voltage required for switching 4 The typical value of Vixiac is expected to be 0 5 Voo and is expected to track variations in Vpp Capacitance 0 C lt Tease lt 55 C f 100 MHz Vout DC Vpp 2 Vour ac 0 1V p p PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO CIN1 2 3 pF Input Capacitance Address BA 1 0 A 12 0 CS RAS CAS and Control ME CKE ODT CIN ao 4 pF DQ 63 0 CB 7 0 DQS 17 0 Input Output Capacitance DQSI17 0 CIO 3 4 pF DC Characteristics Voltages referenced to Vss 0 V P
14. R 23 20 VO 3 0 pas3 DQS12 DQS3 DQS12 DQS DQS CS DM DQS DQRI27 24 O 1 0 3 0 DQR 31 28 VO 3 0 l I 13 0 31 28 8 0 DQ 63 00 O WA O DQR 63 00 DQS4 DQS13 CB 7 0 O VWW O _ CBRI7 0 DQS4 DQS13 Das DGS 16S OM TE DQS 17 00 O WW O DQSR 17 00 IDQS 17 00 O VVy O O DQSR 17 00 DQR 35 32 O 1 0 3 0 DQR 39 36 VO 3 0 pass DQS14 DQS5 IDQS14 DQS DQS CS DM DQS DQRI43 40 O 1 0 3 0 DQR 47 44 VO 3 0 pas DQS15 IDQS6 DQS15 DAS DAS CS DM DQS cKO PCKO PCK6 PCK8 PCK9 to SDRAMS DQR 51 48 O 1 0 3 0 DQR 55 52 VO 3 0 P DQs7 DQS16 ICKO PCKO PCK6 PCK8 PCK9 to SDRAMS DQS7 DQS16 L IDES DOS JES DM DOS OE PCK7 to Registers DAR 59 56 O 1 0 3 0 DAR 63 60 OJ 1013 0 RESEN IPCK7 to Registers pass DQS17 pass O _ mas O DAS DAS CS DM DQS DAS CS DM CBR 3 0 O 1 0 3 0 CBRI7 4 VO 3 0 REGISTERS SO WA RSO All SDRAMs Notes BAO BA2 A W RBAO RBA2 All SDRAMs 1 Unless otherwise noted resistor values are 22 Ohms 5 A0 A15 V WA RAO RA15 All SDRAMs IRAS WA j RRAS All SDRAMs ICAS Wr IRCAS All SDRAMs CKE0 VWA RCKEO All SDRAMs MWE W j RWE All SDRAMs oDTo vww RODTO All SDRAMs RESET RST PCK7 PCK7 S0 connects to DCS of Register A and CSR of Register B CSR of Register A and DCS of Register B connect to VDD RESET PCK7 and PCK7 connect to both Registers Other signals connect to one of two Re
15. gisters S1 CKE1 and ODT1 are NC Document 06454 Revision E 24 MAR 08 Dataram Corporation 2008 Page 3 DTM63310 DATARAM 1 GB 128Mx72 240 Pin Registered DDR2 DIMM Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TstToRAGE 55 100 C DRAM Case Temperature Operating Tcase 0 85 C Voltage on Vpp relative to Vss Vpp 0 5 2 3 V Voltage on Any Pin relative to Vss Vin Vout 0 5 2 3 V Recommended DC Operating Conditions Voltages referenced to Vss 0 V PARAMETER Svmbol Minimum Tvpical Maximum Unit Note Power Supply Voltage Vpop 1 7 1 8 1 9 V I O Reference Voltage VREF 0 49 Vpp 0 50 Vpp 0 51 Voo V 1 Bus Termination Voltage Vit Vreer 0 04 VREF Vrer 0 04 V Notes 1 The value of Vrer is expected to equal one half Vpp and to track variations in the Voo DC level Peak to peak noise on Veer may not exceed 1 of its DC value DC Input Logic Levels Single Ended Voltages referenced to Vss 0 V PARAMETER Svmbol Minimum Maximum Unit Logical High Logic 1 ViH DC Vrer 0 125 Vpop 0 300 V Logical Low Logic 0 ViL oc 0 300 Vrer 0 125 V AC Input Logic Levels Single Ended Voltages referenced to Vss 0 V PARAMETER Svmbol Minimum Maximum Unit Logical High Logic 1 Vin ac Vrer 0 250 V Logical
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