Dataram DTM67207B memory module
Contents
1. DRAM Case temperature Rise from Ambient due to Active Power Down with 54 Slow PDN Exit DT3Pslow C UNUSED AE DRAM Case Temperature Rise from Ambient due to Page Open Burst 2E Read DT4R4W Mode Bit DT4R DT4R4W Mode Bit C 55 Bit 0 0 if DT4W is greater than DT4R 0 Bits 1 7 DT4R 0 56 Case Temperature Rise from Ambient due to Burst Refresh DT5B UNUSED 4F DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads 57 with Auto Precharge DT7 C UNUSED 128 58 Thermal Resistance of PLL Package from Top to Ambient Psi T A PLL UNUSED 00 C Watt 59 Thermal Resistance of Register Package from Top to Ambient Psi T A UNUSED 00 Register C Watt 60 PLL Case Temperature Rise from Ambient due to PLL Active DT PLL Ac UNUSED 00 tive C Register Case Temperature Rise from Ambient due to Register Active Mode 00 Bit DT Register Active Mode Bit 61 Bit 0 If 0 Unit for Bits 2 7 is 0 75C 0 75 Bit 1 RFU Default O 0 Bits 2 7 Register Active 0 62 ISPD Revision Revision 1 2 12 63 Checksum for Bytes 0 62 Checksum 1F 64 Module Manufacturer s JEDEC ID Code Dataram ID 7F 65 Module Manufacturer s JEDEC ID Code Dataram ID 91 66 71 Module Manufacturer s JEDEC ID Code UNUSED 00 72 Module Manufacturing Location UNUSED 00 73 90 Module Part Number Space 20 91 92 Module Revision Code UNUSED 00 93 94 Module Manufacturing Date Date Code 95 98 Module Serial Number2. Features 200 pin JEDEC SO DIMM Dual sided assembly 67 60 mm 2 661 wide by 30 0 mm 1 181 high Operating Voltage 1 8 V 0 1 I O Type SSTL_18 Data Transfer Rate 5 3 Gigabytes sec Burst Lengths 4 and 8 Programmable I O driver strength OCD Programmable On Die Termination ODT Differential Data Strobe signals SDRAM Addressing Row Col Bank 14 10 3 Two Physical Ranks Fully ROHS Compliant Pin Configurations Front side VREF DQS1 31 DQS1 Vss DQ10 DQ11 Vss 41 Vss DQ16 DQ17 Vss DQS2 not used on the DTM67207B DTM67207B 2 GB 200 Pin Unbuffered non ECC DDR2 SO DIMM Identification DTM67207B 256Mx64 2GB 2Rx8 PC2 4200S 444 12 F1 Performance range Clock Module Speed CL trco trp 266 MHz DDR2 533 4 4 4 200 MHz DDR2 400 3 3 3 NAANA Description The Dataram DTM67207B assembly is a 256M x64bit Unbuffered non ECC memory module that conforms to the JEDEC PC2 4300 standard The DTM67207B assembly is Dual Rank Each rank is comprised of eight Hynix 128Mx8 DDR2 SDRAMs in 60 Ball FBGA packages A 2Kbit EEPROM for serial presence detect pro vides critical timing and configuration information used by the system to identify and configure the memory The assembly is a Small Outline Dual In line Memory Module intended for mounting into 200 pin edge connector sockets Pin Names Back side Pin name Function IRAS Row Ad
3. 63 000 Di 2 480 g Back view Side view 3 50 Max 138 Max ll 4 000 Min 157 Min l 10000 J00000 000000 10 1 000 100 k 040 004 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches Document 06553 Revision A 08 Jul 09 Dataram Corporation 2009 Page 2 DD DATARAM DTM67207B A 2 GB 200 Pin Unbuffered non ECC DDR2 SO DIMM 3 OHMS 1810 S0 O ces O e kf DMRO O DMR4 O HA DQSRO O DQSR4 O A oi dia HEAR DQS DQS CS DM DQS DQS CS DM DQS DQS CS DM DQS DQS CS DM DAQR 7 0 O 1 0 7 0 1 0 7 0 DQR 39 32 O 1 0 7 0 1 0 7 0 DMR10 DMR5 O DQSR10O DQSR5 O DQSR1 0 DQSR5 O DQS DQS CS DM DQS DQS CS DM DQS DQS CS DM DQS DQS CS DM DQR 15 8 O 1 0 7 0 1 0 7 0 DQR 47 40 0 1 0 7 0 1 0 7 0 DMR2 O DMR6 O DQSR2 O DQSR6 O DQSR2 O DQSR6 O AAA DQS DQS CS DM DQS DQS CS DM DQS DQS CS DM i DQS DQS CS DM DQR 23 16 O 1 0 7 0 1 0 7 0 DQR 55 48 0 1 0 7 0 1 0 7 0 DMR3 O DMR7 O DQSR3 O DQSR7 O DQSR3 O DQSR7 O DQS DAS CS DM DOS DAS CS DM DQS DAS CS DM DQS DQS CS DM DQR 31 24 O 1 0 7 0 1 0 7 0 DQR 63 56 0 1 0 7 0 1 0 7 0 a 22 OHMS DQ 63 0 O VW O DQR 63 0 DQS 7 0 O VWW O DQSR 7 0 DQS 7 0 O WW O DQSR 7 0 2 X 200 OHMS DM 7 0 O VA O DMR 7 0 co SDRAM X 8 ICKO GLOBAL SDRAM CONNEC
4. Delay trco 15 ns Average Periodic Refresh Interval t REFI 7 8 us Auto Refresh Row Cycle Time trrc 127 5 ns Row Precharge Time tre 15 ns Read DQS Preamble Time tRPRE 0 9 1 1 tex Read DQS Postamble Time test 0 4 0 6 tex Row Active to Row Active Delay trRD 7 5 ns Internal Read to Precharge Command Delay tRTP 7 5 ns Write DQS Preamble Time twpRE 0 35 ps Write DQS Postamble Time twpest 0 4 0 6 tox Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR 7 5 ns Exit Self Refresh to Non Read Command txsnr trec min 10 ns Exit Self Refresh to Read Command txsRD 200 tck Document 06553 Revision A 08 Jul 09 Dataram Corporation 2009 Page 7 DTM67207B BA gente td At 2 GB 200 Pin Unbuffered non ECC DDR2 SO DIMM SERIAL PRESENCE DETECT MATRIX Byte Function Value Hex O Number of Bytes Utilized by Module Manufacturer 128 bytes 80 1 Total number of Bytes in SPD device 256 bytes 08 2 Memory Type DDR2 SDRAM 08 3 Number of Row Addresses 14 OE 4 Number of Column Addresses 10 OA Module Attributes Number of Ranks Package and Height 61 Number of Ranks 2 5 Card on Card No DRAM Package Planar Module Height 30mm 6 Module Data Width 64 40 7 Reserved UNUSED 00 8 Voltage Interface Level of this assembly SSTL 1 8V 05 9 SDRAM Cycle time Max Supported CAS Laten
5. for signal termination resistors is expected to be set equal to Vrer and must track variations in the DC level of Ver DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Vrer 0 125 Vop 0 300 V 0 300 Vrer 0 125 V Logical High Logic 1 VHC Logical Low Logic 0 ViL Dc AC Input Logic Levels Single Ended T O to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 ViH ac Vrer 0 250 V Logical Low Logic 0 ViL Ac Vrer 0 250 V A ll A A Document 06553 Revision A 08 Jul 09 Dataram Corporation O 2009 Page 4 ee 2 GB 200 Pin Unbuffered non ECC DDR2 SO DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note DC Input Signal Voltage Vinc 0 300 Vpp 0 300 V 1 DC Differential Input Voltage Vipioc 0 250 Voo 0 600 V 2 AC Differential Input Voltage Vinac 0 500 Voo 0 600 V 3 AC Differential Cross Point Voltage Vix Ac 0 50 VDD 0 175 0 50 VDD 0 175 V 4 Notes 1 Vinoc specifies the allowable DC excursion of each input of a differential pair 2 Vipco specifies the input differential voltage i e the absolute value of the difference between the two voltages of a differential pair 3 Vipiac Specifies the input differential voltage required for
6. inputs are switch ing All banks open continuous burst writes BL 4 CL CL Ipp AL Operating Burst Invaw 0 tek tex loo tras trasMAX loo tre tep loo CKE is HIGH 4369 ma Write Current DB S is HIGH between valid commands Address bus inputs are switching Data bus inputs are switching All banks open continuous burst reads lout OMA BL 4 CL Operating Burst Inn4R CL Ipp AL 0 tck tcx Ipp tras trasMAX lpp trp tre loo 1360 mA Read Current 29 CKE is HIGH S is HIGH between valid commands Address bus inputs are switching Data bus inputs are switching tek tcx Ipp refresh command at every trrc loo interval CKE is sind Refresh Cur i o5 HIGH S is HIGH between valid commands Other control and 2040 mA address bus inputs are switching Data bus inputs are switching Self Refresh Cur loo6 CK and CK at OV CKE lt 0 2V Other control and address bus 110 mA rent p inputs are floating Data bus inputs are floating All bank interleaving reads lour 0 mA BL 4 CL CL Ipp AL Operating Bank In trep Ipp 1 X tck loo tex tck Ipp tac trc Ipp tarp terleave Read Cur Ipp7 tero loo trco trco loo CKE is HIGH S is HIGH between valid 2520 mA rent commands Address bus inputs are stable during deselects Data bus inputs are switching Notes 1 All currents are based on DRAM absolute maximum values 2 Unless otherwise specified for all IpX measurements CL loo 4 tex t
7. switching 4 The typical value of Vixiac is expected to be 0 5 Voo and is expected to track variations in Vpp Capacitance T 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO CK1 CK1 CIN1 13 22 pF Input Capacitance Address F and Control BA 2 0 A 13 0 RAS CAS WE CIN2 16 32 pF Input Capacitance Control CKEO CKE1 SO S1 ODTO ODT1 CIN3 8 16 pF Input Output Capacitance DQ 63 0 BOP Al DQSI7 0 CIO 5 8 pF DM 7 0 DC Characteristics Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current Command and Address lu 80 80 yA 1 Input Leakage Current S 1 0 CKE 1 0 lu 40 40 yA 1 ODT 1 0 Input Leakage Current CK 1 0 CK 1 0 lu 40 40 HA 1 Input Leakage Current DM lu 10 10 HA 1 Output Leakage Current DQS DQ loz 10 10 pA 2 Output Minimum Source DC Current loH 13 4 mA 3 Output Minimum Sink DC Current loL 13 4 mA 4 Notes 1 These values are guaranteed by design and are tested on a sample basis only 2 DQxand ODT are disabled and 0 V lt Vout Vop 3 Voo 1 7 V Vour 1420 mV Vour Voo lon must be less than 21 Ohms for values of Vout between Von and Vopn 280 mV 4 Vpp 1 7 V Vout 280 mV Vour lo must be less than 21 Ohms for values of Vout between 0 V and 280 mV Document 06553 Revision A 08 Jul 09 Dataram Corporation O
8. 06 40 Add this value to byte 41 0 Add this value to byte 42 0 5 41 SDRAM Device Minimum Active to Active Auto Refresh Time trc ns 60 3C SDRAM Device Minimum Auto Refresh to Active Auto Refresh 42 Command Period terc ns tate iP 43 SDRAM Device Maximum Cycle Time tck max ns 8 80 44 SDRAM Dev DQS DQ Skew for DAS amp DQ signals toasa ns 0 3 1E 45 DDR SDRAM Device Read Data Hold Skew Factor tans ns 0 4 28 46 PLL Relock Time us UNUSED 00 DRAM maximun Case Temperature Delta C 00 Br DTARAWDelta Bits 0 3 0 Tcasemax delta Bits 7 4 48 DRAN o of DRAM Package from Top Case to Ambient Psi T A UNUSED 4E DRAM Case Temperature Rise from Ambient due to Activate Precharge 20 Mode Bits DTO Mode Bits C 49 Bit 0 If 0 DRAM does not support high temperature self refresh entry 0 Bit 1 If 0 Do not need double refresh rate for the proper operation 0 DTO Bits 2 7 0 50 a from Ambient due to Precharge Quiet UNUSED 1E 54 ce Temperature Rise from Ambient due to Precharge Power Down UNUSED 23 52 a Case Temperature Rise from Ambient due to Active Standby DT3N UNUSED 16 53 de R e from Ambient due to Active Power Down with UNUSED 2c Ee Document 06553 Revision A 08 Jul 09 Dataram Corporation 2009 Page 10 D Pye DTM67207B Optimizing Value and Performance 2 GB 200 Pin Unbuffered non ECC DDR2 SO DIMM
9. 2009 Page 5 ee 2 GB 200 Pin Unbuffered non ECC DDR2 SO DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Test Condition VA Unit Operating One tek tcx Ipp tac trc loo tras trasMIN Ipp CKE is HIGH S is Bank Active IpbpO HIGH between valid commands Address bus inputs are switch 920 mA Precharge Current ing Data bus inputs are switching a lout 0 mA BL 4 CL CL loo A AL O tex tex loo A trc Operating One tac Ipp tras trasMIN lop pa i teco lon CKE A S is Bank Active head loo1 HIGH between valid commands Address bus inputs are switch 1489 mA Precharge Current ing Precharge Power lon2P All banks idle tck tcx lpp CKE is LOW Other control and ad 110 mA Down Current aD dress bus inputs are stable Data bus inputs are floating All banks idle tcx tex Ipp CKE is HIGH S is HIGH Other con Aa Standby Ipp2N trol and address bus inputs are switching Data bus inputs are 640 mA switching r All banks open tcx tck loo CKE is LOW Other control and ad oe loo3P dress bus inputs are stable Data bus inputs are floating Fast 480 mA Power down exit Mode Register bit 12 0 All banks open tck tcx Ipp tras trasMAX Ipp trp trp Ipp Active Standby lon3N CKE is HIGH S is HIGH between valid commands Other control 720 MA Current Di and address bus inputs are switching Data bus
10. BD Analysis probe installed No TBD SDRAM Device Attributes General 02 Includes Weak Driver Supports 50 ohm ODT x Supports PASR Partial Array Self Refresh 22 TBD TBD TBD TBD TBD 23 Minimum Clock Cycle Time at Reduced CAS Latency CL X 1 ns 5 50 24 Maximum Data Access Time tac from Clock at CL X 1 ns 0 5 50 25 Minimum Clock Cycle Time at CL X 2 ns UNUSED 00 26 Maximum Data Access Time tac from Clock at CL X 2 ns UNUSED 00 27 Minimum Row Precharge Time tgp ns 15 3C 28 Minimum Row Active to Row Active Delay tarp ns 7 5 1E 29 Minimum RAS to CAS Delay trcp ns 15 3C 30 Minimum Active to Precharge Time tras ns 45 2D Document 06553 Revision A 08 Jul 09 Dataram Corporation O 2009 Page 9 naa DTM67207B A 2 GB 200 Pin Unbuffered non ECC DDR2 SO DIMM 31 Module Rank Density 1GB 01 32 Address and Command Setup Time Before Clock tis ns 0 25 25 33 Address and Command Hold Time After Clock ti ns 0 37 37 34 Data Input Setup Time Before Strobe tps ns 0 1 10 35 Data Input Hold Time After Strobe tp ns 0 22 22 36 Write Recovery Time twr ns 15 3C 37 Internal write to read command delay twrr ns 7 5 1E 38 Internal read to precharge command delay tarp ns 7 5 1E 39 Memory Analysis Probe Characteristics UNUSED 00 Extension of Byte 41 trc and Byte 42 trrc ns
11. Serial Numben 99 127 Manufacturer s Specific Data UNUSED 00 Document 06553 Revision A 08 Jul 09 Dataram Corporation O 2009 Page 11 rea 2 GB 200 Pin Unbuffered non ECC DDR2 SO DIMM TNIDATARAM Md A Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Da taram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trade marks claimed and owned by Dataram Dataram reserves the right to change products or specifications without notice No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06553 Revision A 08 Jul 09 Dataram Corporation 2009 Page 12
12. TS 58 pt 10 OHMS 2 X 200 OHMS BA 2 0 O VWA O BA 2 0 R A 13 0 O WM O A 13 0 R IRAS O WA O RASR o SDRAM X8 ICAS O WA O CASR WE O WA O WER 5 6 pf 3 OHMS CKEO OM gt ot RANKO O W gt ODTOR eel DECOUPLING 3 OHMS VppsPp Serial PD CKE1 O AM gt CKEIR panic 1 VDD All Devices ODT1 O M4 gt ODTIR VREF All SDRAMs Vss All Devices SCL SERIAL PD SDA SAO SA1 SA2 Document 06553 Revision A 08 Jul 09 Dataram Corporation 2009 Page 3 DR Optimizing Value and Performance Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability DTM67207B 2 GB 200 Pin Unbuffered non ECC DDR2 SO DIMM PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TsTORAGE 55 100 C DRAM Case Temperature Operating Tcase 0 85 C Voltage on Vpp relative to Vss Vop 0 5 2 3 V Voltage on Any Pin relative to Vss Vin Vout 0 5 2 3 V Recommended DC Operating Conditions T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER a ET bra ste Note Power Supply Voltage 1 O Reference Voltage Vrer 0 04 2 Vrer 0 04 VREF Bus Termination Voltage Notes 1 The value of Vrer is expected to equal one half Vpp and to track variations in the Vpp DC level Peak to peak noise on Veer may not exceed 1 of its DC value 2 Vrris not applied directly to the device Vr is a system supply
13. cy CL X ns 3 75 3D 10 SDRAM Access from Clock Highest CAS latency tac ns 0 5 50 DIMM configuration type Non parity Parity or ECC 00 Data Parity Data ECC Address Command Parity 11 TBD TBD TBD TBD TBD 12 Refresh Rate Type us 7 8 SR 82 13 Primary SDRAM Width 8 08 14 Error Checking SDRAM Width None 00 15 Reserved UNUSED 00 SDRAM Device Attributes Burst Lengths Supported 0C TBD TBD Burst Length 4 X 16 Burst Length 8 X TBD TBD TBD TBD 17 SDRAM Device Attributes Number of Banks on SDRAM Device 8 08 Document 06553 Revision A 08 Jul 09 Dataram Corporation 2009 Page 8 D Pye DTM67207B A 2 GB 200 Pin Unbuffered non ECC DDR2 SO DIMM SDRAM Device Attributes CAS Latency 18 TBD TBD Latency 2 18 Latency 3 X Latency 4 X Latency 5 Latency 6 TBD 19 DIMM Mechanical Characteristics Max module thickness mm x lt 3 80 01 DIMM type information 04 Regular RDIMM 133 35mm Regular UDIMM 133 35mm SODIMM 67 6mm X 20 Micro DIMM 45 5mm Mini RDIMM 82 0mm Mini UDIMM 82 0mm TBD TBD SDRAM Module Attributes Refer to Byte 20 for DIMM type information 00 Number of active registers on the DIMM N A for SODIMM 1 Number of PLL on the DIMM N A for UDIMM 0 21 FET Switch External Enable No T
14. dress Strobe ICAS Column Address Strobe IWE Write Enable S 1 0 Chip Select CK 1 0 CK 1 0 Differential Clock CKE 1 0 Clock Enable ODT 1 0 On Die Termination BA 2 0 Bank Select A 13 0 Address Input Multiplexed SCL Serial Clock SDA Serial Data I O SA 1 0 Address EEPROM DQS 7 0 Data Strobes DM 7 0 Data Masks DQ 63 0 Data I Os Data Bus Event Temperature Sensing VREF Reference Voltage Voo Power Supply 1 8V 0 1 Vss Ground VbpsPo Serial EEPROM Power Supply Vss NC No Connects 44 DQ20 144 Vss 194 DQ63 46 DQ21 146 DQS5 196 Vss 48 Vss 148 DQS5 198 SAO VppSPD 50 Event 150 Vss 200 SA1 Document 06553 Revision A 08 Jul 09 Dataram Corporation O 2009 Page 1 ee 2 GB 200 Pin Unbuffered non ECC DDR2 SO DIMM Front view 67 600 re 2 661 30 000 4 1 181 4000 20 000 157 787 2 150 a 47 400 a 2 540 Min 130 11 400 1 866 100 Min 449 4200 H es 165
15. ex lop 3 75 ns trasMAX lop 70 000 ns trasMIN lop 45ns tro loo 60 ns trco loo 15 ns trrc loo 127 5 ns tre lop 15ns tago loo 7 5 ns Document 06553 Revision A 08 Jul 09 Dataram Corporation O 2009 Page 6 ae 2 GB 200 Pin Unbuffered non ECC DDR2 SO DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit DQ Output Access Time from Clock tac 500 500 ps CAS to CAS Command Delay teco 2 tck Clock High Level Width tou 0 45 0 55 tex Clock Cycle Time tex 3750 8000 ps Clock Low Level Width tot 0 45 0 55 tex Data Input Hold Time after DQS Strobe ton 225 ps DQ Input Pulse Width toipw 0 35 tck DQS Output Access Time from Clock toasck 450 450 ps Write DQS High Level Width toosH 0 35 tex Write DQS Low Level Width toast 0 35 tex DQS Out Edge to Data Out Edge Skew toasa 300 ps Data Input Setup Time Before DQS Strobe tos 100 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tck DQS Falling Edge to Clock Setup Time toss 0 2 tck Clock Half Period tue minimum of tch or teL ns Address and Command Hold Time after Clock tn 375 ps Address and Command Setup Time before Clock tis 250 ps Load Mode Command Cycle Time turo 2 tck DQ to DQS Hold ton tup tans Data Hold Skew Factor tans 400 ps Active to Precharge Time tras 45 70K ns Active to Active Auto Refresh Time tre 60 ns RAS to CAS
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