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Dataram DTM65536B memory module

1. Parameter Symbol MIN MAX Units Notes CMD2DATA 0x40 Data Rate 667 tC2D_AMB 16 2 19 ns CMD2DATA 0x46 Data Rate 667 tC2D_AMB 17 7 20 5 ns Resample Delay 6 tRESAMPLE 0 9 1 4 ns 1 Resync Delay 7 8 9 tRESYNC 2 3 2 ns 2 NOTES 1 tRESAMPLE is the delay from the southbound input to the southbound output or the northbound input to the northbound output when in resample mode measured from the center of the data eye 2 tRESYNC is the delay from the southbound input to the southbound output or the northbound input to the northbound output when in resync mode measured from the center of the data eye DEEE Document 06038 Revision A 29 Sep 09 Dataram Corporation 2010 Page 9 TZ DTM655368 A 2 GB 240 Pin DDR2 Low Power FB DIMM AMB Power Specification Ta O to 70 C Voltage referenced to Vss OV Parameter oe Power a Symbol Test Condition Supply Value Unit idle Single or last FBDIMM LO state idle 0 BW primary channel 1 5V 1600 Current IDD_IDLE_O enabled secondary channel disabled CKE high command and mA address lines stable DDR2 SDRAM clock active 1 8V 500 Idle First FBDIMM LO state idle 0 BW primary and secondary 1 5V 2300 Current IDD_IDLE_1 channels enabled CKE high command and address lines mA stable DDR2 SDRAM clock active 1 8V 500 Active Power Active IDD ACTIVE 1 L0 state 50 DRAM BW 15 2900 Power T 167 read 3
2. DRAMS SPD AMB Document 06038 Revision A 29 Sep 09 Dataram Corporation O 2010 Page 3 TA DTM65536B SS 2 GB 240 Pin DDR2 Low Power FB DIMM Absolute Maximum Ratings Parameter Symbol Rating Unit Note Temperature DDR2 DRAM Case Tcase 0 to 95 C 1 2 Temperature Storage Tstc 55 to 100 C 1 Voltage on any pin relative to Vss Vin Vout 0 3 to 1 75 V 1 Voltage on Vcc relative to Vss Vec 0 3 to 1 75 V 1 Voltage on Vpp relative to Vss Vop 0 5 to 2 3 V 1 Voltage on Vrr relative to Vss Vit 0 5 to 2 3 V 1 Power Dissipation Pp 21 W 1 NOTES 1 Operation at or above absolute maximum rating can adversely affect device reliability 2 For85C lt Tcase lt 95 C treri 3 9 us max DC Operating Conditions Ta O to 70 C Voltage referenced to Vss OV Parameter Symbol Minimum Typical Maximum Unit Note AMB Supply Voltage Vcc 1 425 1 5 1 59 V DDR2 Supply Voltage Voo 1 7 1 8 1 9 V Termination Voltage Vit 0 48 x VDD 0 50 x VDD 0 52 x VDD V EEPROM Supply Voltage SPD Vppspp 3 0 3 3 3 6 V Input High Voltage SPD ViHoc 2 1 Vppspp V 1 Input Low Voltage SPD Vioc 1 0 V 1 Input High Voltage RESET BFUNC ViHoc 1 0 V 2 Input Low Voltage RESET BFUNC Vit oc 0 5 V 1 Leakage Curent RESET BFUNC IL 90 90 yA 2 Leakage Curent Link I 5 5 HA Notes 1 Applies to SMB and SPD bus signals 2 Applies to AMB CMOS signal R
3. 2 638 gi 12 008 123 00 4 843 Back view Side view 7 49 Max al 0 295 Max w heatspreader 4 00 Min 0 157 Min 1 27 10 el N 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches lt A E _ _ _Q _Qz gt E _EEE O gt EE EEEEE EEE EE OE ECO OREEOEEOPE E zP y ya Qu ______QQ_OO____ _QEAoAA Page 2 Document 06038 Revision A 29 Sep 09 Dataram Corporation O 2010 TAZZZ DTM655368 Optimizing Value and Performance 2 GB 240 Pin DDR2 Low Power FB DIMM S1 e Iso O gt DM0 O DM4 O e DQSO O DQS4 O DQS0 O DQS4 O 688 688 8 668 8 666 Y A a A a a a a a a a a igj A amp 2 Q E a E a 2 DQR 7 0 O _ 1 0 7 0 A VO 7 0 DQ 39 32 O 1 0 7 0 fal YO 7 0 A DMI O DMS DQSI O 2 DQS5 O e DQS1 O
4. DQS5 O T N 122 n 122 Nn 122 n 12 mn Mm n mn Mm an Nn N el o Q Q Q Y Q A A i A A A A g 8 Q 3 g 8 Q 3 g gt E R amp gt g DQ I5 8 O 1 0 17 0 A VO 7 0 a DQr47 407 o vo 7 01 A YO 7 0 A DM O DM6 O DQs2 o DQS6 O DQs2 O DQS6 O a a n A a a n a a Dn a Za a A A Q o Q Q Q Q Y Q Q Y Q ES E REG aa a Pg DQ 23 16 O _ 1 0 7 0 2 VO 7 0 2 DQ S5 48 O 1 0 7 0 Z VO 7 0 A DM3 DM7 O e DQS3 O DQS7 O DQS3 O DQS7 O e ZAR g a g a a 2 an g a a a a Q Q Q Q E o Q Q Q Q Y os 4 a a 6 2 82g aa 6 ae 4 T A DQ 31 24 O VO 7 0 2 VO 7 0 A DQ 63 56 O 10 7 0 2 VO 7 0 2 DM8 O DQss O DQS8 O S 2 8 8 688 g scL gt gt SDA A i A A A a z gZ SPD CB 7 0 O 101 7 0 2 VO 7 0 2 WP SAO SAI SA2 PNO PN13 DQ0 DQ63 PNO PN13 CB0 CB7 All address command control clock M Vrr PS0 PS9 DQS0 DQS8 PS0 PS9 DQS0 DQS8 SNO SN13 A DMO0 DM8 SNO SN13 ISO gt ICS RANK 0 SS0 SS9 M CKEO gt CKE RANK 0 KET Terminators SS0_ SS9 S1 gt CS RANK 1 SCL B CKEI gt CKE RANK 1 vcc gt AMB SDA ODTO gt ODT RANK 0 SALSA2 ODT gt ODT RANK 1 Sami SA0 BA0 BA2 all SDRAMs VDDSPD PR SPD AMB A0 A15 all SDRAMs calles RESET IRAS all SDRAMs iar SCK amp SCK CAS all SDRAMs VDD DRAMS AMB WE all SDRAMs CK amp CK all SDRAMs i DREAMS There are two physical copies of each address command control clock a VSS
5. 01 Bit 3 Bit 0 Read Access Fine Granularity UI Bit 7 Bit 4 Read Access Coarse Granularity tCK Thermal Resistance of AMB Package from Top Case to Ambient Psi T A AMB C W AMB Case Temperature Rise from Ambient due to AMB in Idle_0 State DT AMB Idle_0 C AMB Case Temperature Rise from Ambient due to AMB in Idle_1 State DT AMB Idle _1 C AMB Case Temperature Rise from Ambient due to AMB in Idle_2 State DT AMB Idle_2 C AMB Case Temperature Rise from Ambient due to AMB in Active _1 State 87 DT AMB Active_1 C AMB Case Temperature Rise from Ambient due to AMB in Active_2 State 70 DT AMB Active_2 C AMB Case Temperature Rise from Ambient due to AMB in LOs State UNUSED DT AMB LOs C Reserved UNUSED AMB Junction Temperature Maximum Tjmax C 125 Ox4A Reserved Reserved UNUSED AMB Personality Bytes Pre initialization DEE _ _ gt L qQ _________________ ___ ______ ___ _O__z Document 06038 Revision A 29 Sep 09 Dataram Corporation O 2010 Page 16 aa DTM655368___ SS 2 GB 240 Pin DDR2 Low Power FB DIMM 102 AMB Personality Bytes Pre initialization 0x02 103 AMB Personality Bytes Pre initialization 0xDA 104 AMB Personality Bytes Pre initialization 0x66 105 AMB Personality Bytes Pre initialization 0x97 106 AMB Personality Bytes Pre initialization 0x9C 107 AMB Personality Bytes Pos
6. Bit 7 Bit 5 Row Address Bits 14 Module Physical Attributes 5 Bit 3 Bit 0 Module Thickness mm 7 lt x lt 8 0 0x23 Bit 4 Bit 2 Module Height mm 30 lt x lt 35 Bit 7 6 Reserved 0 Module Type 6 Bit 3 Bit 0 Module Type FB DIMM 0x07 Bit 7 Bit 4 Reserved 0 Module Organization 7 Bit 3 Bit 0 SDRAM Device Width 8 Bits 0x11 Bit 5 Bit 3 Number of Ranks 2 Rank Bit 7 6 Reserved 0 Fine Timebase Dividend Divisor 8 Bit 3 Bit 0 Fine Timebase FTB Dividend 0 0x00 Bit 7 Bit 4 Fine Timebase FTB Divisor 0 1 MTB 3 Medium Timebase Dividend 0 25ns oxo 4 MTB e Medium Timebase Divisor 0 25ns ox 11 SDRAM Minimum Cycle Time tCKmin 3 0ns Ox0C 12 SDRAM Maximum Cycle Time tCKmax 8 0ns 0x20 SDRAM CAS Latencies Supported 13 Bit 3 Bit 0 Minimum CL clocks 3 0x33 Bit 7 Bit 4 CL Range clocks 3 14 SDRAM Minimum CAS Latency Time tAAmin 15 0ns Ox3C Document 06038 Revision A 29 Sep 09 Dataram Corporation 2010 Page 13 2 GB 240 Pin DDR2 Low Power FB DIMM i oor SDRAM Write Recovery Times Supported 15 Bit 3 Bit 0 Minimum WR clocks 2 0x42 Bit 7 Bit 4 WR Range clocks 4 16 SDRAM Write Recovery Time tWR 15 0ns 0x3C SDRAM Write Latencies Supported 17 Bit 3 Bit 0 Minimum WL clocks 2 0x42 Bit 7 Bit 4 WL Range clocks 4 SDRAM Additive Latenc
7. 226 RFU2 VSS Ground 17 RESET 47 VSS 77 PS2 107 VSS 137 M_TEST 167 VSS 197 SS2 227 VSS RFU Reserved For Future Use 18 VSS 48 PN12 78 VSS 108 VDD 138 VSS 168 SN12 198 VSS 228 SCK DNU Do Not Use 19 RFU2 49 PN12 79 PS3 109 VDD 139 RFU2 169 SN12 199 SS3 229 SCK M_TEST Margin Test 20 RFU2 50 VSS 80 PS3 110 VSS 140 RFU2 170 VSS 200 SS3 230 VSS SA 2 0 Serial Address EEPROM 21 VSS 51 PNG 81 VSS 111 VDD 141 VSS 171 SN6 201 VSS 231 VDD 22 PNO 52 PNG 82 PS4 112 VDD 142 SNO 172 ISN6 202 SS4 232 VDD 23 PNO 53 VSS 83 PS4 113 VDD 143 SNO 173 VSS 203 SS4 233 VDD 24 VSS 54 PN7 84 VSS 114 VSS 144 VSS 174 SN7 204 VSS 234 VSS 25 PN1 55 PN7 85 VSS 115 VDD 145 SN1 175 SN7 205 VSS 235 VDD 26 PN1 56 VSS 86 RFU1 116 VDD 146 SN1 176 VSS 206 RFU1 236 VDD 27 VSS 57 PN8 87 RFU1 117 VTT 147 VSS 177 SN8 207 RFU1 237 VTT 28 PN2 58 PN8 amp 88 VSS 118 SA2 148 SN2 178 SN8 208 VSS 238 VDDSPD 29 PN2 59 VSS 89 VSS 119 SDA 149 SN2 179 VSS 209 VSS 239 SAO 30 VSS 60 PN9 90 PS9 120 SCL 150 VSS 180 SN9 210 SS9 240 SA1 NOTE M_TEST is not used Document 06038 Revision A 29 Sep 09 Dataram Corporation 2010 Page 1 mr DTM65536B A 2 GB 240 Pin DDR2 Low Power FB DIMM IN2DATARA Front view 133 35 a 5 250 gt 9 50 3 00 0 118 0 374 30 35 1 191 yo A 17 30 A l 0 681 DAA nnnm OMA AAA Y ion 2 50 Min 5 18 67 00 51 00 0 098 Min 10 204
8. 3 write mA primary and secondary channels 1 8V 1200 enabled DRAM clock active CKE HIGH Active Power Data Pass Through LO state 50 DRAM BW to downstream TSV a0 Active IDD_ACTIVE_2 DiMM 67 read 33 write primary and TA Power secondary channels enabled CKE HIGH 1 8 V 500 Command and address lines stable DRAM clock active IDD TRAINING Primary and secondary channels enabled 100 toggle on all 1 5V 2300 Training channel lanes DDR2 SDRAM devices idle 0 BW CKE HIGH mA command and address lines stable DDR2 SDRAM clock active 1 8 V 400 Document 06038 Revision A 29 Sep 09 Dataram Corporation O 2010 Page 10 TT DTM65536B 2 GB 240 Pin DDR2 Low Power FB DIMM Optimizing Value and Performance DRAM AC Characteristics AC operating conditions unless otherwise noted Parameter Symbol enn oo Unit Note Value Value Row Cycle Time tre 60 ns Auto Refresh Row Cycle Time trre 127 5 ns Row Active Time tras 45 70K ns Row Address to Column Address Delay trop 15 ns Row Active to row Active Delay trrD 7 5 ns Column Address to Column Address Delay teco 2 CLK Row Precharge time trp 15 ns Write Recovery Time twr 15 ns Auto Precharge Write Recovery Precharge Time toa twel o trp 7 di System Clock Cycle Time tck 3000 8000 ps Clock High Level Width tcH 0 48 0 52 CLK Clock Low Level Width t
9. AMPLE 17 p Bit Error Ratio BER 18 10 Document 06038 Revision A 29 Sep 09 Dataram Corporation 2010 Page 5 a DO TM65536B M7 4 BH Optimizing Value and Performance 2 GB 240 Pin DDR2 Low Power FB DIMM NOTES FOR TRANSMITTER OUTPUT SPECIFICATIONS 1 Specified at the package pins into a timing and voltage compliance test load Common mode measurements to be performed using a 101010 pattern 2 This is the ratio of the VTX DIFFp p of the second and following bits after a transition divided by the VTX DIFFp p of the first bit after a transition 3 De emphasis is disabled in the calibration state 4 Includes all sources of AC common mode noise 5 Single ended voltages below that value that are simultaneously detected on D and D are interpreted as the Electrical Idle condition 6 Specified at the package pins into a voltage compliance test load Transmitters must meet both single ended and differential output E1 specifications 7 This specification considered with Vrx IDLE se DC implies a maximum 15mV single ended DC offset between Tx and Rx pins during the electrical idle condition This in turn allows a ground offset between adjacent FB DIMM agents of 26mV when worst case termination resistance matching is considered 8 The maximum value is specified to be at least VTX DIFFp p L 4 VTx CM L VTX CM ACp p 2 9 This number does nat include the effects of SSC or reference clock jitter 10 These timing speci
10. ESET Document 06038 Revision A 29 Sep 09 Dataram Corporation 2010 Page 4 TRATA DTM655368__ AAA 2 GB 240 Pin DDR2 Low Power FB DIMM Differential Transmitter Output Specification Parameter Symbol MIN MAX Units Differential peak to peak output voltage for large voltage VTX DIFFp p_L 1 900 1300 mV swing VTX DIFFp p 2 VTX D VTX D Differential peak to peak output voltage for regular voltage VTX DIFFp p_R 1 800 mV swing VTX DIFFp p 2 VTX D VTX D Differential peak to peak output voltage for small voltage VTX DIFFp p_S 1 520 mV swing VTX DIFFp p 2 VTX D VTX D DC common code output voltage for large voltage swing VTX CM_L 1 a 375 mV Defined as VTX CM DC avg of VTX D VTX D 2 DC common mode output voltage for small voltage swing VTX CM_S 1 135 280 mv Defined as VTX CM DC avg of VTX D VTX D 2 De emphasized differential output voltage ratio for 3 5 dB VTX DE 3 5 3 4 dB de emphasis Ratio 1 2 3 De emphasized differential output voltage ratio for 6 dB de VTX DE 6 Ratio 1 2 3 5 7 dB emphasis AC peak to peak common mode output voltage for large VTX CM ACp p L 1 4 oe 90 mV swing VTX CM AC Max VTX D VTX D 2 Min VTX D VTX D 2 AC peak to peak common mode output voltage for regular VTX CM ACp p R 1 4 __ 80 mV swing VTX CM AC Max VTX D VTX D 2
11. High Temperature Self Refresh 1 Required Bit 7 Double Refresh Requirement 1 Supported Tcasemax Delta Bit 3 Bit 0 DT4R4W Delta Subfield B 0 4 C 0 8 33 Bit 7 Bit 4 Tcasemax Subfield A 2 C 10 0x52 34 Thermal Resistance of SDRAM Package C W 61 Ox7A SDRAM Case Temperature Rise from Ambient due to Activate Precharge minus 2 8 C offset temperature DTO C Bit 1 Bit 0 Reserved 0 35 Bit 7 Bit 2 DTO 6 0x50 SDRAM Case Temperature Rise from Ambient due to Precharge Quiet 4 7 36 Standby DT2N DT2Q C Ox2F SDRAM Case Temperature Rise from Ambient due to 0 585 37 Precharge Power Down DT2P C 0x27 SDRAM Case Temperature Rise from Ambient due to Active 5 85 38 Standby DT3N C l 0x27 SDRAM Case Temperature Rise from Ambient due to Page Open Burst Read DT4R4W Mode Bit DT4R DT4R4W Mode Bit Bit 0 DT4R4W Mode Bit Subfield B 0 4 C Bit 7 Bit 1 DT4R Subfield A 0 4 C SDRAM Case Temperature Rise from Ambient due to Burst Refresh DT5B C SDRAM Case Temperature Rise from Ambient due to Bank 20 Interleave Reads with Auto Precharge DT7 C Reserved UNUSED QR Control 76 QR ODT control for Rank 0 and rank 1 Reads and writes 0x00 77 QR ODT1 and ODT2 control for reads 0x00 FBD ODT Definition for Rank 2 and 3 Bit 1 Bit 0 Rank 2 Data DRAM ODT Disabled Bit 3 Bit 2 Rank 2 Ecc DRAM ODT Disabled Bit 5 Bit 4 Rank 3 Data DRAM ODT Di
12. Low Power FB DIMM AC Operating Conditions AC operating conditions unless otherwise noted Min Max F Parameter Symbol Unit Note Value Value DQ Input Pulse Width toipw 0 35 CLK Read DQS Preamble Time trPRE 0 9 1 1 CLK Read DQS Postamble Time trest 0 4 0 6 CLK Write DQS Preamble Hold Time twPRE 0 35 CLK Write DQS Postamble Time twest 0 4 0 6 CLK Mode Register Set Delay turo 2 CLK Exit Self Refresh to Non Read Command txsnr tRFC 10 ns Exit Self Refresh to Read Command txsrD 200 CLK aN 7 8 us 1 Average Periodic Refresh Interval tREFI 3 9 us 2 NOTES 1 For0 C lt Tcase 85 C 2 For85C lt Tcase 95 C Document 06038 Revision A 29 Sep 09 Dataram Corporation 2010 Page 12 Ta DTMess3eB SS 2 GB 240 Pin DDR2 Low Power FB DIMM SERIAL PRESENCE DETECT MATRIX Function Value Number of Serial PD Bytes Written SPD Device Size CRC Coverage Bit 3 Bit 0 SPD Bytes Used 176 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 SPD Revision Rev 1 1 Key Byte DRAM Device Type DDR2 FBDIMM Voltage Levels of this Assembly Bit 3 Bit 0 Power Supply 1 Bit 7 Bit 4 Power Supply 2 SDRAM Addressing 1 5V 1 8V 8 4 Bit 1 0 Number of Banks 0x45 Bit 5 Bit 3 Column Address Bits 10
13. Min VTX D VTX D 2 AC peak to peak common mode output voltage for small VTX CM ACp p S 1 4 _ 70 mV swing VTX CM AC Max VTX D VTX D 2 Min VTX D VTX D 2 Maximum single ended voltage in El condition DC AC VTX IDLE SE 5 6 2 50 mV Maximum single ended voltage in El condition DC only DON 20 mV Maximum peak to peak differential voltage in El condition VTX IDLE DIFFp p 6 _ 40 mv Single ended voltage w r t VSS on D D VTX SE 1 7 75 750 mV Minimum TX eye width 3 2 and 4 Gb s TTX Eye MIN 1 9 10 0 7 en UI Maximum TX deterministic jitter 3 2 and 4 Gb s TTX DJ DD 1 9 10 11 0 2 UI Instantaneous pulse width TTX PULSE 12 0 85 UI Differential TX output rise fall time TTX RISE TTX 30 90 ps Given by 20 80 voltage levels FALL 1 Mismatch between rise and fall times TTX RF MISMATCH 20 ps Differential return loss RLTX DIFF 8 __ dB Measured over 0 1 GHz to 2 4GHz Common mode return loss RLTX CM 6 ac dB Measured over 0 1 GHz to 2 4GHz Transmitter termination resistance RTX 13 41 55 Q D D TX resistance difference RTX Match DC 4 RTX Match DC 2 RTX D RTX D RTX D RTX D Bounds are applied separately to high and low output voltage states Lane to lane skew at TX LTX SKEW 1 14 16 100 3UI ps Lane to lane skew at TX LTX SKEW 2 15 16 100 2UI ps TTX DRIFT 240 s Maximum TX Drift resync mode RESYNC 17 p TTX DRIFT 120 s Maximum TX Drift resample mode only RES
14. TZ DTM655368 MA Optimizing Value and Performance IMECRLSHE SEED PO Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 35 mm high Data Transfer Rate 5 3 Gigabytes sec Operating Voltage VDD 1 8 V 40 1 VCC 1 5V 0 1 SMBus interface to AMB for configuration register access MBIST and IBIST test functions Transparent mode for DDR2 SDRAM test support Full DIMM Heat Spreader High speed differential point to point link Fully ROHS Compliant 2 GB 240 Pin DDR2 Low Power FB DIMM Identification DTM65536B 256Mx72 2GB 2Rx8 PC2 5300F 555 11 B0 Performance range Clock Module Speed CL trco trp F 333MHz DDR2 667 5 5 5 267MHz DDR2 533 4 4 4 200MHz DDR2 400 3 3 3 pjaneta neam A Description The DTM65536B is a Dual Rank PC2 5300 Fully Buffered 256MX72 ECC DIMM that conforms to the JEDEC FB DIMM standard Each rank is comprised of nine Samsung 128Mx8 DDR2 DRAMs One IDT Rev L4 Advanced Memory Buffer AMB is used as the interface between the system memory bus and DIMM DRAMs One 2K bit EEPROM is used for Serial Presence Detect For improved thermal performance a Full DIMM Heat Spreader with thermal interface material TIM is attached to the front and back of the DIMM This is a reduced power module Components have been tested and selected for this design with the lowest power consumption Pin Configurations Pin Names Front side Bac
15. V and VRx CM ACp p 13 The termination small signal resistance tolerance across voltages from 100mV to 400mV shall not exceed 51 with regard to the average of the values measured at 100mV and at 400mV for that pin 14 This number represents the lane to lane skew between TX and RX pins and does not include the transmitter output skew from the component driving the signal to the receiver This is one component of the end to end channel skew in the AMB specification 15 Measured from the reference clock edge to the center of the input eye This specification is met across specified voltage and temperature ranges Drift rate of change is significantly below the tracking capability of the receiver 16 This bandwidth number assumes the specified minimum data transition density Maximum jitter at 0 2MHz is 0 05UI 17 The specified time includes the time required to forward the El entry condition 18 BER per differential lane Document 06038 Revision A 29 Sep 09 Dataram Corporation 2010 Page 8 TAZZZ DTM655368 A 2 GB 240 Pin DDR2 Low Power FB DIMM Advanced Memory Buffer FBD Timing Electrical Parameter Symbol MIN MAX Units El Assertion Pass Through Timing tEl PROPAGATE 4 CLKs El Deassertion Pass Through Timing tEID tBitlock CLKs El Assertion Duration tEl 100 CLKs Bit Lock Interval tBITLOCK 119 Frames Frame Lock Interval tFRAMELOCK 154 Frames Advanced Memory Buffer Latency Parameters
16. eL 0 48 0 52 CLK DQ output access time from CK amp CK tac 0 450 0 450 ns DQS Out edge to Clock Edge skew toasck 0 400 0 400 ns DQS Out edge to Data out edge skew toasa 0 240 ns Data Out hold time from DQS ton tup tons ns 1 Data hold skew factor tons 0 340 ns 1 Clock Half Period tur min tc tch ns 1 Input Setup Time fast slew rate tis 0 200 ns 2 3 5 6 Input Hold Time fast slew rate tia 0 275 ns 2 3 5 6 Input Pulse Width tipw 0 6 CLK 6 Write DQS High Level Width toasH 0 35 CLK Write DQS Low Level Width toasL 0 35 CLK CLK to First Rising edge to DQS In tbass 0 25 0 25 CLK Data In Setup Time to DQS In DQ amp DM tos 0 100 ns Data In Hold Time to DQS In DQ amp DM ton 0 175 ns NOTES 1 This calculation accounts for toaselmax the pulse width distortion of on chip and jitter 2 3 For command address input slew rate gt 1 0V ns 4 For command address input slew rate gt 0 5V ns and lt 1 0V ns 5 CK CK slew rates are gt 1 0V ns 6 guaranteed by design or tester correlation 7 Data latched at both rising and falling edges of Data Strobes DQS Data sampled at the rising edges of the clock A0 A13 BAO BA2 CKE S 1 0 RAS CAS WE These Parameters guarantee device timing but they are not necessarily tested on each device and they may be Document 06038 Revision A 29 Sep 09 Dataram Corporation 2010 Page 11 TZ DTM65536B A 2 GB 240 Pin DDR2
17. ermination resistance RRX 13 41 55 Q D D RX resistance difference RRX Match DC 4 RRX Match DC 2 RRX D RRX D RRX D RRX D Lane to lane PCB skew at RX LRX PCB SKEW 14 6 UI Lane to Lane PCB skew at the Receiver that must be tolerated Minimum RX Drift Tolerance TRX DRIFT 15 400 ps Minimum data tracking 3dB bandwidth FTRK 16 0 2 a MHz Electrical idle entry detect time Peon lt 60 ns Electrical idle exit detect time TEI EXIT DETECT as 30 ns Bit Error Ratio BER 18 Se 10 Document 06038 Revision A 29 Sep 09 Dataram Corporation 2010 Page 7 yee DTM65536B M7 4 BH Optimizing Value and Performance 2 GB 240 Pin DDR2 Low Power FB DIMM NOTES FOR RECEIVER INPUT SPECIFICATIONS 1 Specified at the package pins into a timing and voltage compliant test setup Note that signal levels at the pad are lower than at the pin 2 Single ended voltages below that value that are simultaneously detected on D and D are interpreted as the Electrical Idle condition Worst case margins are determined by comparing El levels with common mode levels during normal operation for the case with transmitter using small voltage swing see RX Single ended Electrical Idle Levels and RX Common Mode Levels 3 Multiple lanes need to detect the El condition before the device can act upon the El detection 4 Specified at the package pins into a timing and voltage compliance test setup 5 This specification con
18. fications apply to resync mode only 11 Defined as the dual dirac deterministic jitter as described in Section 4 of the JEDEC FB DIMM High Speed Differential PTP Link Draft Spec rev 0 8 12 Pulse width measured at OV differential 13 The termination small signal resistance tolerance across voltages from 100mV to 400mV shall not exceed 5 with regard to the average of the values measured at 100mV and at 400mV for that pin 14 Lane to Lane skew at the Transmitter pins for an end component 15 Lane to Lane skew at the Transmitter pins for an intermediate component assuming zero Lane to Lane skew at the Receiver pins of the incoming PORT 16 This is a static skew A FB DIMM component is not allowed to change its lane to lane phase relationship after initialization 17 Measured from the reference clock edge to the center of the output eye This specification is met across specified voltage and temperature ranges for a single component Drift rate of change is significantly below the tracking capability of the receiver 18 BER per differential lane For a complete definition of Bit Error Ratio refer to JEDEC s Compliance Methodology section Document 06038 Revision A 29 Sep 09 Dataram Corporation 2010 Page 6 Tyler 2TM65536B _ AAA 2 GB 240 Pin DDR2 Low Power FB DIMM Differential Receiver Input Specification Parameter Symbol MIN MAX Units D
19. ies Supported 18 Bit 3 Bit 0 Minimum AL clocks 0 0x40 Bit 7 Bit 4 AL Range clocks 4 19 SDRAM Minimum RAS to CAS Delay tRCD 15 0ns 0x3C 20 SDRAM Minimum Row Active to Row Active Delay tRRD 7 5ns Ox1E 21 SDRAM Minimum Row Precharge Time tRP 15 0ns 0x3C SDRAM Upper Nibbles for tRAS and tRC 22 Bit 3 Bit 0 tRAS Most Significant Nibble 0x00 Bit 7 Bit 4 tRC Most Significant Nibble 23 SDRAM Minimum Active to Precharge Time tRAS 45 0ns 0xB4 24 SDRAM Minimum Active to Active Refresh Time tRC 60 0ns OXFO 25 TEN Minimum Refresh Recovery Time Delay tRFC 127 5ns OXFE 26 ee Minimum Refresh Recovery Time Delay tRFC 127 5ns 0x01 27 R Minimum Internal Write to Read Command Delay 7 5ns 0x1E SDRAM Minimum Internal Read to Precharge Command 28 Delay tRTP 7 5ns Ox1E SDRAM Burst Lengths Supported Bit 0 BL 4 X 29 Bit 1 BL 8 X 0x03 Bit 6 Bit 2 TBD Bit 7 Burst Chop SDRAM Terminations Supported Bit 0 150 ohms ODT X 30 Bit 1 75 ohms ODT X 0x07 Bit 2 50 ohms ODT X Bit 6 Bit 3 TBD SDRAM Drivers Supported 31 Bit 0 Weak Driver X 0x01 Bit 7 Bit 1 TBD 32 SDRAM Average Refresh Interval tREFI Double Refresh mode bit High 0xC2 Temperature self refresh rate support indication Bit 0 Bit 3 Average Refresh Interval tREFI uS 7 8 Document 06038 Revision A 29 Sep 09 Dataram Corporation 2010 Page 14 yg DTM65536B AAA 2 GB 240 Pin DDR2 Low Power FB DIMM Bit 5 Bit 4 TBD 0 Bit 6
20. ifferential peak to peak input voltage VRX DIFFp p_L 1 170 1300 mV VRX DIFFp p 2 VRX D VRX D Maximum single ended voltage for El condition DC AC VRX IDLE SE 2 3 4 ae 65 mV Maximum single ended voltage for El condition DC only Oo ae 35 mV Single ended voltage w r t VSS on D D VRX SE 4 300 900 mV Single pulse peak differential input voltage VRX DIFF PULSE 4 6 85 mV Amplitude ratio between adjacent symbols VRX DIFF ADJ zm 3 1100mV lt VRX DIFFp p 1300mV RATIO HI 4 7 Amplitude ratio between adjacent symbols VRX DIFF ADJ oe 4 VRX DIFFp p 1100mV RATIO 4 7 Maximum RX inherent timing error 3 2 and 4 Gb s TRX TJ MAX 4 8 9 0 4 UI Maximum RX inherent deterministic timing error 3 2 and 4 TRX DJ DD 4 8 9 10 e 0 3 UI Gb s Single pulse width at zero voltage crossing TRX PW ZC 4 6 0 55 Ul Single pulse width at minimum level crossing TRX PW ML 4 6 0 2 a Ul nie RX input rise fall time given by 20 80 voltage TRX RISE TRX FALL 50 _ ps evels Common mode of the input voltage VRX CM 1 11 120 400 mV Defined as VRX CM DC avg of VRX D VRX D 1 2 AC peak to peak common mode of input voltage VRX CM VRX CM ACp p 1 E 270 mV AC Max VRX D VRX D 2 Min VRX D VRX D 2 Ratio of VRX CM ACp p to minimum VRX DIFFp p VRX CM EH Ratio 12 _ 45 Differential return loss RLRX DIFF 9 dB Measured over 0 1 GHz to 2 4GHz Common mode return loss RLRX CM 6 dB Measured over 0 1 GHz to 2 4GHz RX t
21. k side Pin Names Function 1 VDD 31 PN3 61 PN9 91 PS9 121 VDD 151 SN3 181 SN9 211 SS9 SCK SCK System Clock Input 2 VDD 32 PN3 62 VSS 92 VSS 122 VDD 152 SN3 182 VSS 212 VSS PN PN 13 0 Primary Northbound Data 3 VDD 33 VSS 63 PN10 93 PS5 123 VDD 153 VSS 183 SN10 213 SS5 PS PS 9 0 Primary Southbound Data 4 VSS 34 PN4 64 PN10 94 PS5 124 VSS 154 SN4 184 SN10 214 SS5 SN SN 13 0 Secondary Northbound Data 5 VDD 35 PN4 65 VSS 95 VSS 125 VDD 155 SN4 185 VSS 215 VSS SS SS 9 0 Secondary Southbound Data 6 VDD 36 VSS 66 PN11 96 PS6 126 VDD 156 VSS 186 SN11 216 SS6 SCL Serial Clock EEPROM 7 VDD 37 PN5 67 PN11 97 PS6 127 VDD 157 SN5 187 SN11 217 SS6 SDA Serial Data EEPROM 8 VSS 38 PN5 68 VSS 98 VSS 128 VSS 158 SN5 188 VSS 218 VSS RESET AMB Reset Signal 9 VCC 39 VSS 69 VSS 99 PS7 129 VCC 159 VSS 189 VSS 219 SS7 vec AMB Core Power and AMB Channel 10 VCC 40 PN13 70 PSO 100 PS7 130 VCC 160 SN13 190 SSO 220 SS7 Interface Power 1 5 V 11 VSS 41 PN13 71 PSO 101 VSS 131 VSS 161 SN13 191 SSO 221 VSS DRAM Power and AMB DRAM I O 12 VCC 42 VSS 72 VSS 102 PS8 132 VCC 162 VSS 192 VSS 222 SS8 YDB Power 1 8 V 13 VCC 43 VSS 73 PS1 103 PS8 133 VCC 163 VSS 193 SS1 223 SS8 VTT DRAM Address Command Clock 14 VSS 44 RFU 74 PS1 104 VSS 134 VSS 164 RFU1 194 SS1 224 VSS Termination Power VDD 2 15 VTT 45 RFU 75 VSS 105 RFU2 135 VTT 165 RFU1 195 VSS 225 RFU2 VDDSPD SPD Power 16 VID1 46 VSS 76 PS2 106 RFU2 136 VIDO 166 VSS 196 SS2
22. n O 2010 Page 17 yey OD TM65536B Med BH Optimizing Value and Performance 2 GB 240 Pin DDR2 Low Power FB DIMM TTIDATARAM MUA A A Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06038 Revision A 29 Sep 09 Dataram Corporation 2010 Page 18
23. sabled Bit 7 Bit 6 Rank 3 Ecc DRAM ODT Disabled FBD ODT Definition for Rank 0 and 1 Bit 1 Bit O Rank 0 Data DRAM ODT 150 Ohms Bit 3 Bit 2 Rank 0 Ecc DRAM ODT Disabled Bit 5 Bit 4 Rank 1 Data DRAM ODT 150 Ohms Bit 7 Bit 6 Rank 1 Ecc DRAM ODT Disabled 80 Reserved UNUSED 0x00 81 Channel Protocols Supported Least Significant Byte 0x02 nnn nnn QRJo Q y Quh O _____ __ ____________EPE E __________E E_O9EQ___QRQRQRQR Document 06038 Revision A 29 Sep 09 Dataram Corporation O 2010 Page 15 aa DTM655368___ AAA 2 GB 240 Pin DDR2 Low Power FB DIMM 0 Not Bit 0 DDR2 Base Non ECC Protocol Supported Bit 1 DDR2 Base ECC Protocol 1 Supported Bit 7 Bit 2 TBD 0 82 Channel Protocols Supported Most Significant Byte UNUSED 0x00 Back to back Turnaround Cycles Bit 1 Bit 0 Rank Read to Read 0 add l clock 83 Bit 3 Bit 2 Write to Read 0 add I clock 0x10 Bit 5 Bit 4 Read to Write 1 add clock Bit 7 Bit6 TBD 0 AMB Read Access Time for DDR2 800 AMB LINKPARNXT 1 0 11 Bit 3 Bit 0 Read Access Fine Granularity UI 10 Bit 7 Bit 4 Read Access Coarse Granularity tCK 4 AMB Read Access Time for DDR2 667 AMB LINKPARNXT 1 0 10 Bit 3 Bit 0 Read Access Fine Granularity UI Bit 7 Bit 4 Read Access Coarse Granularity tCK AMB Read Access Time for DDR2 533 AMB LINKPARNXT 1 0
24. sidered with VTX IDLE SE DC implies a maximum 15mV single ended DC offset between TX and RX pins during the electrical idle condition This in turn allows a ground offset between adjacent FB DIMM of 26mV when worstcase termination resistance matching is considered 6 The single pulse mask provides sufficient symbol energy for reliable RX reception Each symbol complies with both the single pulse mask and the cumulative eye mask see RX Single Pulse Min Width and Amplitude Mask Pulse Shifted Early and RX Single Pulse Min Width and Amplitude Mask Pulse Shifted Late 7 The relative amplitude ratio limit between adjacent symbols prevents excessive inter symbol interference in the Rx Each symbol must comply with the peak amplitude ratio with regard to both the preceding and subsequent symbols see RX Maximum Adjacent Symbol Amplitude 8 This number does not include the effects of SSC or reference clock jitter 9 This number includes setup and hold of the RX sampling flop 10 Defined as the dual dirac deterministic timing error as described in Section 4 2 2 of the JEDEC FB DIMM High Speed Differential PTP Link Draft Spec rev 0 8 11 Allows for 15mV DC offset between transmit and receive devices 12 The received differential signal satisfies both this ratio as well as the absolute maximum AC peak to peak common mode specification For example if VRX DIFFp p is 200mV the maximum AC peak to peak common mode is the lesser of 200 mV 0 45 90m
25. t initialization 108 AMB Personality Bytes Post initialization 109 AMB Personality Bytes Post initialization 110 AMB Personality Bytes Post initialization 111 114 AMB Personality Bytes Post initialization 115 AMB Manufacturer s JEDEC ID Code 116 AMB Manufacturer s JEDEC ID Code Module ID Module Manufacturer s JEDEC ID Code Module ID Module Manufacturer s JEDEC ID Code Module ID Module Manufacturing Location 120 121 Module ID Module Manufacturing Location 0x00 122 125 Module ID Module Serial Number 0x00 126 Cyclical Redundancy Code CRC 127 Cyclical Redundancy Code CRC 128 131 Module Part Number 132 Module Part Number Module Part Number Module Part Number Module Part Number 136 Module Part Number 137 Module Part Number 138 Module Part Number 139 Module Part Number 140 Module Part Number 141 Module Part Number 142 Module Part Number 143 Module Part Number 144 Module Part Number 145 Module Part Number 146 147 Module Revision Code UNUSED 148 149 SDRAM Manufacturer s JEDEC ID Code UNUSED 150 175 Manufacturer s Specific Data UNUSED 176 255 Open for customer use UNUSED _ _ ____ az ___EOEO COCO OOO EE GEO lt EO O E lt EE EE y z _ ___ E_________EIE_E________________________Q_Q___I e _ _ gt 8EPEOEOEI5SR3RO RDV 1 U1 A Document 06038 Revision A 29 Sep 09 Dataram Corporatio

Dataram DTM65536B memory module

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