Dataram DTM65523C memory module
Contents
1. Parameter Symbol MIN MAX Units Differential peak to peak output voltage for large voltage VTX DIFEp p L 1 swing _VTX DIFFp p 2 VIX D VTX D Pepe 808 A800 omy Differential peak to peak output voltage for regular voltage VTX DIFFp p RA swing _VTX DIFFp p 2 VTX D VTX D Per 800 m Differential peak to peak output voltage for small voltage VTX DIFFp 1 swing VTX DIFFp p 2 VTX D VTX D p p_S 1 520 my DC common code output voltage for large voltage swing f Defined as VTX CM DC avg of VTX D VTX D 2 VTX CM_L 1 375 mV DC common mode output voltage for small voltage swing Defined as VTX CM DC avg of VTX D VTX D 2 VIXCM_S 1 135 280 mv De emphasized differential output voltage ratio for 3 5 dB VTX DE 3 5 de emphasis Ratio 1 2 3 3 4 dB De emphasized differential output voltage ratio for 6 dB de VTX DE 6 Ratio 1 2 3 emphasis 5 7 dB AC peak to peak common mode output voltage for large swing VTX CM AC Max VTX D VTX D 2 Min VTX VTX CM ACp p L 1 4 oe 90 mV D VTX D 2 AC peak to peak common mode output voltage for regular swing VTX CM AC Max VTX D VTX D 2 Min VTX VTX CM ACp p R 1 4 as 80 mV D VTX D 2 AC peak to peak common mode output voltage for small swing VTX CM AC Max VTX D VTX D 2 Min VTX VTX CM ACp p S 1 4 ee 70 mV D VTX2. Parameter Symbol Rating Unit Note Temperature DDR2 DRAM Case Tcase 0 to 95 C 1 2 Temperature Storage TsTG 55 to 100 C 1 Voltage on any pin relative to Vss Vin Vout 0 3 to 1 75 V 1 Voltage on Vcc relative to Vss Vec 0 3 to 1 75 V 1 Voltage on Vpp relative to Vss Vpop 0 5 to 2 3 V 1 Voltage on Vrr relative to Vss Vit 0 5 to 2 3 V 1 Power Dissipation Pp 21 W 1 Notes 1 Operation at or above absolute maximum rating can adversely affect device reliability 2 For 85 C lt Tease lt 95 C treri 3 9 US Max DC Operating Conditions Ta 0 to 70 C Voltage referenced to Vss OV Parameter Symbol Minimum Typical Maximum Unit Note AMB Supply Voltage Vcc 1 455 1 5 1 575 V DDR2 Supply Voltage Vpp 1 7 1 8 1 9 V Termination Voltage Vit 0 48 x VDD 0 50 x VDD 0 52 x VDD V EEPROM Supply Voltage SPD Vppspp 3 0 3 3 3 6 V Input High Voltage SPD VHoc Vppspp V 1 Input Low Voltage SPD Vioc 1 0 0 8 V 1 Input High Voltage RESET BFUNC ViHoc 1 0 V 2 Input Low Voltage RESET BFUNC Vit oc 0 5 V 2 Leakage Curent RESET BFUNC IL 90 90 yA 2 Leakage Curent Link I 5 5 HA Notes 1 Applies to SMB and SPD bus signals 2 Applies to AMB CMOS signal RESET Document 06026 Revision A 29 Sep 10 Dataram Corporation 2010 Page 4 DP DATARAM DTM65523C Optimizing Value and Performance Differential Transmitter Output Specification 4 GB 240 Pin DDR2 FB DIMM
3. 88 DT AMB Idle _0 C i i 89 AMB Case Temperature Rise from Ambient due to AMB in Idle_1 State 71 47 DT AMB Idle_1 C 90 AMB Case Temperature Rise from Ambient due to AMB in Idle_2 State 58 3A DT AMB Idle_2 C 91 AMB Case Temperature Rise from Ambient due to AMB in Active_1 State 95 5F DT AMB Active_1 C 92 AMB Case Temperature Rise from Ambient due to AMB in Active_2 State 79 4F DT AMB Active_2 C AMB Temperature Rise from Ambient due to AMB in L tate 93 D ED T ature Rise fro ent due to Os Sta UNUSED 00 94 97 Reserved UNUSED 00 98 AMB Junction Temperature Maximum Tjmax C 125 1F 99 Reserved OA 100 Reserved UNUSED 00 101 AMB Personality Bytes Pre initialization AS 102 AMB Personality Bytes Pre initialization 02 103 AMB Personality Bytes Pre initialization DA Document 06026 Revision A 29 Sep 10 Dataram Corporation 2010 Page 16 platt DTM65523C Optimizing Value and Performance 4 GB 240 Pin DDR2 FB DIMM 104 AMB Personality Bytes Pre initialization 66 105 AMB Personality Bytes Pre initialization 97 106 AMB Personality Bytes Pre initialization 9C 107 AMB Personality Bytes Post initialization DB 108 AMB Personality Bytes Post initialization 36 109 AMB Personality Bytes Post initialization 04 110 AMB Personality Bytes Post initialization AF AMB Personality Bytes Post initialization AMB Manufacturer s JEDEC ID Code AMB Ma
4. fee ey 7DQS DAS CS DM IDQS DAS CS DM 7DQS DAS CS DM 7DQS DAS CS DM DQ 55 48 O 1 017 0 VO 7 0 VO 7 0 VO 7 0 DM7 O DQS7 IDQS7 O rs T rs d DaS DQS CS DM 7DQS DQS CS DM DAS DAS CS DM DaS DAS CS DM DQ 63 56 O 1 0 7 0 VO 7 0 VO 7 0 VO 7 0 DM8 O DASS A a a Ee ss ptt iDQS DAS CS DM iDQS DAS CS DM iDQS DAS CS DM iDQS DAS CS DM CBI7 0 OJ 0 7 0 VO 7 0 VO 7 0 VO 7 0 PNO PN13 SNO SN13 vit Tanninatore PNO PN13 SNO SN13 t PS0 PS9 SS0 SS9 e IPS0 PS9 ISS0 SS9 vec AMB DQ0 DQ63 S0 gt ICS D0 D17 CBO CB7 A CKEO gt CKE D0 D17 vppsPp SPB AME DQS0 DQS8 M S1 gt ICS D18 D35 sl IDQS0 DQS8 B CKE1 gt CKE D18 D35 T DM0 DM8 ODT gt ODTO all SDRAMs VDD SDRAMS AMB SCL BAO BA2 all SDRAMs SDA A0 A15 all SDRAMs VREF x SDRAMS SA1 SA2 IRAS all SDRAMs dli SA0 ICAS all SDRAMs T JRESET INE Gi SDRAM vss e e 4 SDRAMS SPD AMB SCK amp SCK Notes 1 DQ to I O wiring may be changed within a nibble 2 There are two physical copies of each address command control CK amp CK all SDRAMs 3 There are four physical copies of each clock All address command control clock VVy Vor SERIAL PD WP SDA SAO SA1 SA2 Document 06026 Revision A 29 Sep 10 Dataram Corporation 2010 Page 3 DP DATARAM DTM65523C Optimizing Value and Performance 4 GB 240 Pin DDR2 FB DIMM Absolute Maximum Ratings
5. Pulse width measured at OV differential The termination small signal resistance tolerance across voltages from 100mV to 400mV shall not exceed 5 with regard to the average of the values measured at 100mV and at 400mV for that pin Lane to Lane skew at the Transmitter pins for an end component Lane to Lane skew at the Transmitter pins for an intermediate component assuming zero Lane to Lane skew at the Receiver pins of the incoming PORT This is a static skew A FB DIMM component is not allowed to change its lane to lane phase relationship after initialization Measured from the reference clock edge to the center of the output eye This specification is met across specified voltage and temperature ranges for a single component Drift rate of change is significantly below the tracking capability of the receiver BER per differential lane Document 06026 Revision A 29 Sep 10 Dataram Corporation 2010 Page 6 Ad A Optimizing Value and Performance Differential Receiver Input Specification lp yw DIM65523C 4 GB 240 Pin DDR2 FB DIMM Parameter Symbol MIN MAX Units Differential peak to peak input voltage VRX DIFFp p 2 VRX D VRX D VRX DIFFp p_l 1 170 1300 mv Maximum single ended voltage for El condition DC AC VRX IDLE SE 2 3 4 SE 65 mV 5 F ak VRX IDLE SE Maximum single ended voltage for El condition DC only DC 2 3 4 5 San
6. eed A Optimizing Value and Performance Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 35 mm high Data Transfer Rate 5 3 Gigabytes sec Operating Voltage VDD 1 8 V 0 1 VCC 1 5V 0 1 SMBus interface to AMB for configuration register access MBIST and IBIST test functions Transparent mode for DDR2 SDRAM test support Full DIMM Heat Spreader High speed differential point to point link Fully ROHS Compliant lp e LA DIM65523C 4 GB 240 Pin DDR2 FB DIMM Identification DTM65523C 512Mx72 4GB 4Rx8 PC2 5300F 555 1 1 W1 Performance range Clock Module Speed CL trcp trp 333MHz DDR2 667 5 5 5 266MHz DDR2 533 4 4 4 200MHz DDR2 400 3 3 3 Description The DTM65523C is a Quad Rank PC2 5300 Fully Buffered 512Mx72 ECC DIMM that conforms to the JEDEC FB DIMM standard Four ranks are each comprised of nine 128Mx8 DDR2 Samsung SDRAMs One IDT Rev L4 Advanced Memory Buffer AMB is used as the interface between the system memory bus and DIMM DRAMs One 2K bit EEPROM is used for Serial Presence Detect For improved thermal performance a Full DIMM Heat Spreader with Thermal Interface Material TIM is attached to the front and back of the DIMM Pin Configurations Pin Names Front side Back side Pin Names Function 1 VDD 31 PN3 61 PN9 91 PS9 121 VDD 151 SN3 181 SN9 211 SS9 SCK SCK System Clock Input 2 VDD 32 PN3 62 VSS 92 VSS 122 VDD 152 SN3 1
7. 198 VSS 228 SCK DNU Do Not Use 19 RFU2 49 PN12 79 PS3 109 VDD 139 RFU2 169 SN12 199 SS3 229 SCK M_TEST Margin Test 20 RFU2 50 VSS 80 PS3 110 VSS 140 RFU2 170 VSS 200 SS3 230 VSS SA 2 0 Serial Address EEPROM 21 VSS 51 PN6 81 VSS 111 VDD 141 VSS 171 SN6 201 VSS 231 VDD 22 PNO 52 PN6 82 PS4 112 VDD 142 SNO 172 ISN6 202 SS4 232 VDD 23 PNO 53 VSS 83 PS4 113 VDD 143 SNO 173 VSS 203 SS4 233 VDD 24 VSS 54 PN7 84 VSS 114 VSS 144 VSS 174 SN7 204 VSS 234 VSS 25 PN1 55 PN7 85 VSS 115 VDD 145 SN1 175 SN7 205 VSS 235 VDD 26 PN1 56 VSS 86 RFU1 116 VDD 146 SN1 176 VSS 206 RFU1 236 VDD 27 VSS 57 PN8 87 RFU1 117 WTF 147 VSS 177 SN8 207 RFU1 237 VTT 28 PN2 58 PN8 88 VSS 118 SA2 148 SN2 178 SN8 208 VSS 238 VDDSPD 29 PN2 59 VSS 89 VSS 119 SDA 149 SN2 179 VSS 209 VSS 239 SA0 30 VSS 60 PN9 90 PS9 120 SCL 150 VSS 180 SN9 210 SS9 240 SA1 NOTE M_TEST is not used Document 06026 Revision A 29 Sep 10 Dataram Corporation 2010 Page 1 DRPATARAM DTM65523C W Optimizing Value and Performance 4 GB 240 Pin DDR2 FB DIMM Front view P 133 35 gt 5 250 200 0 118 0 374 30 35 1 191 i 17 30 A 0 681 y 0 197 2 50 Min 5 18 la 67 00 51 00 0 098 Min 0 204 2 638 2 008 gt 123 00 4 843 Back view Side view a a 7 49 Max 0 295 Max w heatspearder 4 00 Min 0 157 Min 1 27 10 Ale 0 0500 0 0040 Notes Tolerances on
8. DT4R4W Delta SubfieldB 0 4 C 0 4 51 Bit 7 Bit 4 Tcasemax Subfield A 2 C 10 Thermal Resistance of SDRAM Package C W 58 SDRAM Case Temperature Rise from Ambient due to Activate Precharge minus 2 8 C offset temperature DTO C Bit 1 Bit 0 Reserved 0 Bit 7 Bit 2 DTO 6 3 SDRAM Case Temperature Rise from Ambient due to Precharge Quiet Standby DT2N DT2Q C SDRAM Case Temperature Rise from Ambient due to Precharge Power Down DT2P C SDRAM Case Temperature Rise from Ambient due to Active Standby DT3N C SDRAM Case Temperature Rise from Ambient due to Page Open Burst Read DT4R4W Mode Bit DT4R DT4R4W Mode Bit Bit 0 DT4R4W Mode Bit Subfield B 0 4 C 0 Bit 7 Bit 1 DT4R Subfield A 0 4 C 14 8 SDRAM Case Temperature Rise from Ambient due to Burst Refresh DT5B C SDRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto Precharge DT7 C Reserved UNUSED QR Control QR ODT control for Rank 0 and rank 1 Reads and writes QR ODT1 and ODT2 control for reads FBD ODT Definition for Rank 2 and 3 5 7 1 44 6 9 24 5 26 5 Bit 1 Bit 0 Rank 2 Data DRAM ODT 150 Ohms Bit 3 Bit 2 Rank 2 Ecc DRAM ODT 150 Ohms Bit 5 Bit 4 Rank 3 Data DRAM ODT 150 Ohms Bit 7 Bit6 Rank 3 Ecc DRAM ODT 150 Ohms FBD ODT Definition for Rank 0 and 1 Bit 1 Bit 0 Rank 0 Data DRAM ODT 150 Ohms Bit 3 Bit 2 Rank 0 Ec
9. Input Pulse Width toipw 0 35 CLK Read DQS Preamble Time tRPRE 0 9 1 1 CLK Read DQS Postamble Time trest 0 4 0 6 CLK Write DQS Preamble Hold Time tweRE 0 35 CLK Write DQS Postamble Time twest 0 4 0 6 CLK Mode Register Set Delay tmRD 2 CLK Exit Self Refresh to Non Read Command txsnr tRFC 10 ns Exit Self Refresh to Read Command txsrp 200 CLK ae 7 8 us Average Periodic Refresh Interval REFI 7 3 9 Us 2 Notes 1 For0C lt Tease 85 C 2 For 85 C lt Tcase 95 C Document 06026 Revision A 29 Sep 10 Dataram Corporation 2010 Page 12 pyllit DTM65523C Optimizing Value and Performance 4 GB 240 Pin DDR2 FB DIMM SERIAL PRESENCE DETECT MATRIX Byte Function Value Hex Number of SPD Bytes Written SPD Device Size CRC Coverage 0 Bit 3 Bit 0 SPD Bytes Used 176 92 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 1 SPD Revision Rev 1 1 11 2 Key Byte DRAM Device Type asin 09 Voltage Levels of this Assembly 3 Bit 3 Bit 0 Power Supply 1 1 5V 12 Bit 7 Bit 4 Power Supply 2 1 8V SDRAM Addressing 4 Bit 1 0 Number of Banks 8 45 Bit 5 Bit 3 Column Address Bits 10 Bit 7 Bit 5 Row Address Bits 14 Module Physical Attributes 5 Bit 3 Bit 0 Module Thickness mm 7 lt xs8 0 23 Bit 4 Bit 2 Module Height mm 30 lt x lt 35 Bit 7 6 Reserved 0 Module Type 6 Bit 3 Bit 0 Module Type FB DIMM
10. This number represents the lane to lane skew between TX and RX pins and does not include the transmitter output skew from the component driving the signal to the receiver This is one component of the end to end channel skew in the AMB specification Measured from the reference clock edge to the center of the input eye This specification is met across specified voltage and temperature ranges Drift rate of change is significantly below the tracking capability of the receiver This bandwidth number assumes the specified minimum data transition density Maximum jitter at 0 2MHz is 0 05UI The specified time includes the time required to forward the El entry condition BER per differential lane Document 06026 Revision A 29 Sep 10 Dataram Corporation 2010 Page 8 DP DATARAM DTM65523C Optimizing Value and Performance 4 GB 240 Pin DDR2 FB DIMM Advanced Memory Buffer FBD Timing Electrical Parameter Symbol MIN MAX Units El Assertion Pass Through Timing tEl PROPAGATE 4 CLKs El Deassertion Pass Through Timing tEID tBitlock CLKs EI Assertion Duration tEl 100 CLKs Bit Lock Interval tBITLOCK 119 Frames Frame Lock Interval tFRAMELOCK 154 Frames Advanced Memory Buffer Latency Parameters Parameter Symbol MIN MAX Units CMD to Data Latency Data Rate 533 tC2D_AMB 20 3 25 1 ns Resample Delay tRESAMPLE AMB NB RESAMPLE_AMB_SB 0 9 2 2 ns Resync Delay tRESYNC_AMB_NB 23 39 is tRESYN
11. UI tolerated Minimum RX Drift Tolerance TRX DRIFT 15 400 ps Minimum data tracking 3dB bandwidth FTRK 16 0 2 aes MHz ope TEI ENTRY Electrical idle entry detect time DETECT 17 60 ns Electrical idle exit detect time TEI EXIT DETECT 30 ns Bit Error Ratio BER 18 10 Document 06026 Revision A 29 Sep 10 Dataram Corporation 2010 Page 7 lp e7 DIM65523C Ad A Optimizing Value and Performance 4 GB 240 Pin DDR2 FB DIMM NOTES FOR RECEIVER INPUT SPECIFICATIONS hs 2 OV 11 12 13 14 Specified at the package pins into a timing and voltage compliant test setup Note that signal levels at the pad are lower than at the pin Single ended voltages below that value that are simultaneously detected on D and D are interpreted as the Electrical Idle condition Worst case margins are determined by comparing El levels with common mode levels during normal operation for the case with transmitter using small voltage swing see RX Single ended Electrical Idle Levels and RX Common Mode Levels Multiple lanes need to detect the El condition before the device can act upon the El detection Specified at the package pins into a timing and voltage compliance test setup This specification considered with VTX IDLE SE Dc implies a maximum 15mV single ended DC offset between TX and RX pins during the elecrical idle condition This in turn allows a ground offset between adjacent FB DIM
12. 0 AMB balls U1 and U2 tRESYNC_AMB_sBis the measured delay at AMB balls between the center of the first UI of a frame on primary southbound lane 8 AMB balls U29 and U28 and the center of the first UI of the same frame on secondary southbound lane 8 AMB balls Y26 and W26 Document 06026 Revision A 29 Sep 10 Dataram Corporation 2010 Page 9 DP DATARAM DTM65523C Optimizing Value and Performance 4 GB 240 Pin DDR2 FB DIMM AMB Power Specification Ta 0 to 70 C Voltage referenced to Vss OV Parameter z Power P Symbol Test Condition Supply Value Unit Idle Single or last FBDIMM LO state idle 0 BW primary channel 1 5V 2200 Current IDD_IDLE_O jenabled secondary channel disabled CKE high command and mA address lines stable DDR2 SDRAM clock active 1 8V 900 Idle First FBDIMM LO state idle 0 BW primary and secondary 1 5V_ 3000 Current IDD_IDLE_1 channels enabled CKE high command and address lines mA stable DDR2 SDRAM clock active 1 8V 900 TDP BW Single or Last DIMM LO State TDP Channel 15V_ 2600 Active IDD_TDP_O BW 2 4GB s 667 67 READ 33 WRITE primary channel ae Power enabled secondary channel disabled CKE high command and 18V 1600 address lines stable DDR2 SDRAM clock active TDP BW First DIMM LO State TDP Channel Active IDD TDP 1 BW 2 4GB s 667 DIMM BW 1 6GB s 667 67 READ 33 ee 3300 Power _ WRITE primary channel enabled secondary channel en
13. 2 FB DIMM NOTES FOR TRANSMITTER OUTPUT SPECIFICATIONS 1 ako 10 11 12 14 15 16 17 18 Specified at the package pins into a timing and voltage compliance test load Common mode measurements are performed using a 101010 pattern This is the ratio of the VTX DIFFp p of the second and following bits after a transition divided by the VTx DIFFp p of the first bit after a transition De emphasis is disabled in the calibration state Includes all sources of AC common mode noise Single ended voltages below that value that are simultaneously detected on D and D are interpreted as the Electrical Idle condition Specified at the package pins into a voltage compliance test load Transmitters meet both single ended and differential output E1 specifications This specification considered with Vrx IDLE sE bc implies a maximum 15mV single ended DC offset between Tx and Rx pins during the electrical idle condition This in turn allows a ground offset between adjacent FB DIMM agents of 26mV when worst case termination resistance matching is considered The maximum value is specified to be at least VTX DIFFp p L 4 VTX CM L VTX CM ACp p 2 This number does not include the effects of SSC or reference clock jitter These timing specifications apply to resync mode only Defined as the dual dirac deterministic jitter as described in Section 4 of the JEDEC FB DIMM High Speed Differential PTP Link Draft Spec rev 0 8
14. 35 mV Single ended voltage w r t VSS on D D VRX SE 4 300 900 mV Single pulse peak differential input voltage VRX DIFF PULSE 4 6 85 ane mV Amplitude ratio between adjacent symbols VRX DIFF ADJ 1100mV lt VRX DIFFp p lt 1300mV RATIO HI 4 7 7 3 Amplitude ratio between adjacent symbols VRX DIFF ADJ VRX DIFFp p 1100mV RATIO 4 7 7 4 Maximum RX inherent timing error 3 2 and 4 Gb s TRX TJ MAX 4 8 9 0 4 UI aa RX inherent deterministic timing error 3 2 and 4 TRX DJ DD 4 8 9 10 _ 0 3 UI Single pulse width at zero voltage crossing TRX PW ZC 4 6 0 55 Ss UI Single pulse width at minimum level crossing TRX PW ML 4 6 0 2 oe UI i i i TAN oo RX input rise fall time given by 20 80 voltage TRX RISE TRX FALL 50 _ j Common mode of the input voltage Defined as VRX CM DC avg of VRX D VRX D 2 VRAM 120 400 mV AC peak to peak common mode of input voltage VRX CM AC Max VRX D VRX D 2 Min VRX D VRX D 2 VRACM AGP Pt 270 mV Ratio of VRX CM ACp p to minimum VRX DIFFp p VRX CM EH Ratio 12 45 Differential return loss Measured over 0 1 GHz to 2 4GHz Recor 9 a dB Common mode return loss Measured over 0 1 GHz to 2 4GHz REFVEM 6 H dB RX termination resistance RRX 13 41 55 Q D D RX resistance difference o RRX Match DC 2 RRX D RRX D RRX D RRX D RES Machi De ii 4 Lane to lane PCB skew at RX Lane to Lane PCB skew at the Receiver that must be LRX PCB SKEW 14 hs 6
15. 82 VSS 212 VSS PN PN 13 0 Primary Northbound Data 3 VDD 33 VSS 63 PN10 93 PS5 123 VDD 153 VSS 183 SN10 213 SS5 PS PS 9 0 Primary Southbound Data 4 VSS 34 PN4 64 PN10 94 PS5 124 VSS 154 SN4 184 SN10 214 SS5 SN SN 13 0 Secondary Northbound Data 5 VDD 35 PN4 65 VSS 95 VSS 125 VDD 155 SN4 185 VSS 215 VSS SS SS 9 0 Secondary Southbound Data 6 VDD 36 VSS 66 PN11 96 PS6 126 VDD 156 VSS 186 SN11 216 SS6 SCL Serial Clock EEPROM 7 VDD 37 PN5 67 PN11 97 PS6 127 VDD 157 SN5 187 SN11 217 SS6 SDA Serial Data EEPROM 8 VSS 38 PN5 68 VSS 98 VSS 128 VSS 158 SN5 188 VSS 218 VSS RESET AMB Reset Signal 9 VCC 39 VSS 69 VSS 99 PS7 129 VCC 159 VSS 189 VSS 219 SS7 vec AMB Core Power and AMB Channel 10 VCC 40 PN13 70 PSO 100 PS7 130 VCC 160 SN13 190 SSO 220 SS7 Interface Power 1 5 V 11 VSS 41 PN13 171 PSO 101 VSS 131 VSS 161 SN13 191 SSO 221 VSS DRAM Power and AMB DRAM I O 12 VCC 42 VSS 72 VSS 102 PS8 132 VCC 162 VSS 192 VSS 222 SS8 Ma Power 1 8 V 13 VCC 43 VSS 73 PSi 103 PS8 133 VCC 163 VSS 193 SS1 223 SS8 VTT DRAM Address Command Clock 14 VSS 44 RFU 74 IPS14 104 VSS 134 VSS 164 RFU1 194 SS1 224 VSS Termination Power VDD 2 15 VTT 45 RFU 75 VSS 105 RFU2 135 YTT 165 RFU1 195 VSS 225 RFU2 VDDSPD SPD Power 16 VID1 46 VSS 76 PS2 106 RFU2 136 VIDO 166 VSS 196 SS2 226 RFU2 VSS Ground 17 RESET 47 VSS 77 PS2 107 VSS 137 M_TEST 167 VSS 197 SS2 227 VSS RFU Reserved For Future Use 18 VSS 48 PN12 78 VSS 108 VDD 138 VSS 168 SN12
16. 97 Bit 7 Bit 4 Reserved 0 Module Organization 7 Bit 3 Bit 0 SDRAM Device Width 8 Bits 21 Bit 5 Bit 3 Number of Ranks 4 Rank Bit 7 6 Reserved 0 Fine Timebase Dividend Divisor 8 Bit 3 Bit 0 Fine Timebase FTB Dividend 0 00 Bit 7 Bit 4 Fine Timebase FTB Divisor 0 i ss 1 MTB 9 Medium Timebase Dividend 0 25ns 01 10 Medium Timebase Divisor Cone 04 11 SDRAM Minimum Cycle Time tCKmin 3 0ns 0c 12 SDRAM Maximum Cycle Time tCKmax 8 0ns 20 SDRAM CAS Latencies Supported 13 Bit 3 Bit 0 Minimum CL clocks 4 24 Bit 7 Bit 4 CL Range clocks 2 nn EEE oS Document 06026 Revision A 29 Sep 10 Dataram Corporation 2010 Page 13 plait DTM65523C Optimizing Value and Performance 4 GB 240 Pin DDR2 FB DIMM 14 SDRAM Minimum CAS Latency Time taamin 15 0ns 3C SDRAM Write Recovery Times Supported 15 Bit 3 Bit 0 Minimum WR clocks 2 42 Bit 7 Bit 4 WR Range clocks 4 16 SDRAM Write Recovery Time twr 15 0ns 3C SDRAM Write Latencies Supported 17 Bit 3 Bit 0 Minimum WL clocks 3 63 Bit 7 Bit 4 WL Range clocks 6 SDRAM Additive Latencies Supported 18 Bit 3 Bit 0 Minimum AL clocks 0 50 Bit 7 Bit 4 AL Range clocks 5 19 SDRAM Minimum RAS to CAS Delay tren 15 0ns 3C 20 SDR
17. AM Minimum Row Active to Row Active Delay tarp 7 5ns 1E 21 SDRAM Minimum Row Precharge Time trp 15 0ns 3C SDRAM Upper Nibbles for tras and trac 22 Bit 3 Bit 0 tRAS Most Significant Nibble 00 Bit 7 Bit 4 tRC Most Significant Nibble 23 SDRAM Minimum Active to Precharge Time tras 45 0ns B4 24 SDRAM Minimum Active to Active Refresh Time trc 60 0ns FO 25 SDRAM Minimum Refresh Recovery Time Delay tarc LSB 127 5ns FE 26 SDRAM Minimum Refresh Recovery Time Delay trec MSB 127 5ns 01 27 SDRAM Minimum Internal Write to Read Command Delay twtr 7 5ns 1E 28 SDRAM Minimum Internal Read to Precharge Command Delay tarp 7 5ns 1E SDRAM Burst Lengths Supported Bit 0 BL 4 X 29 Bit1 BL 8 X 03 Bit 6 Bit 2 TBD Bit 7 Burst Chop SDRAM Terminations Supported Bit 0 150 ohms ODT X 30 Bit1 750hmsODT X 07 Bit 2 50 ohms ODT X Bit 6 Bit 3 TBD SDRAM Drivers Supported 31 Bit 0 Weak Driver X 01 Bit 7 Bit 1 TBD SDRAM Average Refresh Interval treri Double Refresh mode bit High Temperature 32 E C2 self refresh rate support indication Bit 0 Bit 3 Average Refresh Interval treri US 7 8 Document 06026 Revision A 29 Sep 10 Dataram Corporation 2010 Page 14 pyllit DTM65523C Optimizing Value and Performance 4 GB 240 Pin DDR2 FB DIMM Bit 5 Bit 4 TBD 0 Bit 6 High Temperature Self Refresh 1 Required Bit 7 Double Refresh Requirement ee Tcasemax Delta 33 Bit 3 Bit 0
18. C_AMB_SB Notes 1 tc2D_AMB is the measured delay at AMB balls between the center of the first UI command frame on primary southbound lane 8 AMB balls U29 and U28 and the center of the first UI of return on primary northbound lane 0 AMB balls U1 and U2 CL DRAM CAS latency value frame clock period AL DRAM additional latency value frame clock period This definition assumes that SB lane 8 is the latest lane to arrive at the AMB balls This will typically be the case since SB lane 8 is the longest SB lane on FBDIMMs If due to large lane to lane skew at the DIMM gold finger another lane is the latest lane to arrive at the AMB balls this other lane must be used instead for the tc2D_AmMB measurement tRESAMPLE_AMB_NBis the measured delay at AMB balls between the center of the first UI of a frame on secondary northbound lane 0 AMB balls V4 and V5 and the center of the first UI of the same frame on primary northbound lane 0 AMB balls U1 and U2 tRESAMPLE_AMB_ SB is the measured delay at AMB balls between the center of the first UI of a frame on primary southbound lane 8 AMB balls U29 and U28 and the center of the first UI of the same frame on secondary southbound lane 8 AMB balls Y26 and W26 tRESYNC_AMB_NBis the measured delay at AMB balls between the center of the first UI of a frame on secondary northbound lane 0 AMB balls V4 and V5 and the center of the first UI of the same frame on primary northbound lane
19. D 2 Maximum single ended voltage in El condition DC AC VTX IDLE SE 5 6 n 50 mV Maximum single ended voltage in El condition DC only DE e 20 mV Maximum peak to peak differential voltage in El condition VTX IDLE DIFFp p 6 40 mV Single ended voltage w r t VSS on D D VTX SE 1 7 75 750 mV Minimum TX eye width 3 2 and 4 Gb s TTX Eye MIN 1 9 10 0 7 UI Maximum TX deterministic jitter 3 2 and 4 Gb s TTX DJ DD 1 9 10 11 0 2 UI Instantaneous pulse width TTX PULSE 12 0 85 UI Differential TX output rise fall time TTX RISE TTX Given by 20 80 voltage levels FALL 1 30 90 ps Mismatch between rise and fall times TTX RF MISMATCH 20 ps Differential return loss Measured over 0 1 GHz to 2 4GHz RET DIFPP 8 dB Common mode return loss Measured over 0 1 GHz to 2 4GHz pee 6 as dB Transmitter termination resistance RTX 13 41 55 Q D D TX resistance difference RTX Match DC 2 RTX D RTX D RTX D RTX D RTX Match DC 4 Bounds are applied separately to high and low output voltage states Lane to lane skew at TX LTX SKEW 1 14 16 100 3UI ps Lane to lane skew at TX LTX SKEW 2 15 16 100 2UI ps Maximum TX Drift resync mode pecan 240 ps Maximum TX Drift resample mode only REARED 120 ps Bit Error Ratio BER 18 10 Document 06026 Revision A 29 Sep 10 Dataram Corporation 2010 Page 5 lpia DIM65523C Meee A Optimizing Value and Performance 4 GB 240 Pin DDR
20. M of 26mV when worstcase termination resistance matching is considered The single pulse mask provides sufficient symbol energy for reliable RX reception Each symbol complies with both the single pulse mask and the cumulative eye mask see RX Single Pulse Min Width and Amplitude Mask Pulse Shifted Early and RX Single Pulse Min Width and Amplitude Mask Pulse Shifted Late The relative amplitude ratio limit between adjacent symbols prevents excessive inter symbol interference in the Rx Each symbol must comply with the peak amplitude ratio with regard to both the preceding and subsequent symbols see RX Maximum Adjacent Symbol Amplitude This number does not include the effects of SSC or reference clock jitter This number includes setup and hold of the RX sampling flop Defined as the dual dirac deterministic timing error as described in Section 4 2 2 of the JEDEC FB DIMM High Speed Differential PTP Link Draft Spec rev 0 8 Allows for 15mV DC offset between transmit and receive devices The received differential signal satisfies both this ratio as well as the absolute maximum AC peak to peak common mode specification For example if VRX DIFFp p is 200mV the maximum AC peak to peak common mode is the lesser of 200 mV 0 45 90mV and VRx CM ACp p The termination small signal resistance tolerance across voltages from 100mV to 400mV shall not exceed 50 with regard to the average of the values measured at 100mV and at 400mvV for that pin
21. abled mA CKE high command and address lines stable DDR2 SDRAM 1 8V 1400 clock active IDD TRAINING Primary and secondary channels enabled 100 toggle on all 1 5V 3500 Training E channel lanes DDR2 SDRAM devices idle 0 BW CKE HIGH mA command and address lines stable DDR2 SDRAM clock active 1 8 V 900 nnn Soe Document 06026 Revision A 29 Sep 10 Dataram Corporation 2010 Page 10 DJ DATARAM DTM65523C Optimizing Value and Performance 4 GB 240 Pin DDR2 FB DIMM DRAM AC Characteristics AC operating conditions unless otherwise noted Parameter Symbol n ne Unit Note Value Value Row Cycle Time tre 60 ns Auto Refresh Row Cycle Time treo 127 5 ns Row Active Time tras 45 70K ns Row Address to Column Address Delay trop 15 ns Row Active to row Active Delay RRD 7 5 ns Column Address to Column Address Delay tceco 2 CLK Row Precharge time trp 15 ns Write Recovery Time twr 15 ns Auto Precharge Write Recovery Precharge Time toaL WR tnRP ns System Clock Cycle Time tck 3000 8000 ps Clock High Level Width tcH 0 45 0 55 CLK Clock Low Level Width teL 0 45 0 55 CLK DQ output access time from CK amp CK tac 0 450 0 450 ns DQS Out edge to Clock Edge skew tpascK 0 400 0 400 ns DQS Out edge to Data out edge skew toasa 0 240 ns Data Out hold time from DQS tou
22. all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches Document 06026 Revision A 29 Sep 10 Dataram Corporation 2010 Page 2 IS3 1S2 181 O Optimizing Value and Performance 1S0 O ___ _ DQI7 0 J2 DATARAM DTM65523C 4 GB 240 Pin DDR2 FB DIMM VOJ7 0 DQS DQS ICS DM DQS DQS CS DM VOJ7 0 IDQS DAS VOI 0 ICS D M DQS DQS 1 0 7 0 CS DM DM1 O DQS1 O DAST PT DAS DAS CS DM DaS DAS CS DM DaS DAS CS DM DaS DAQS CS DM DQI15 8 O V0 7 0 VO 7 0 VO 7 0 VO 7 0 DM2 O DaS O ae a a ee ee eee ee ee DQS2 O J Oo T I DAS DAS CS DM IDQS DQS CS DM IDQS DAS CS DM DQ 23 16 O 017 0 VO 7 0 VO 7 0 DM3 O DQS3 O I DQS3 O 7DQS DQS CS DM DaS DAS CS DM DaS DAS CS DM DaS DAS CS DM DQ 31 24 O 1 01 7 0 VO 7 0 VO 7 0 VO 7 0 DM4 O PE DQS4 O IDQS4 O J e eee es ee ee 7DQS DAS CS DM 7DQS DAS CS DM 7DQS DAS CS DM 7DQS DAS CS DM DQ 39 32 OF 1 017 0 VO 7 0 VO 7 0 VO 7 0 DM5 O a Io DASS pass 9 22 7DQS DAS CS DM DAS DAS CS DM DAS DAS CS DM DaS DAS CS DM DQ 47 40 OF 1 017 0 VO 7 0 VO 7 0 VO 7 0 DM6 O a ee Das
23. c DRAM ODT Disabled Bit 5 Bit 4 Rank 1 Data DRAM ODT 150 Ohms Bit 7 Bit 6 Rank 1 Ecc DRAM ODT Disabled 80 Reserved UNUSED 00 81 Channel Protocols Supported Least Significant Byte 02 nnn _ 7L EEE oo Document 06026 Revision A 29 Sep 10 Dataram Corporation 2010 Page 15 platzt DTM65523C Fd wm Optimizing Value and Performance 4 GB 240 Pin DDR2 FB DIMM Bit 0 DDR2 Base Non ECC Protocol Bend d Bit 1 DDR2 Base ECC Protocol a Bit 7 Bit 2 TBD 0 82 Channel Protocols Supported Most Significant Byte UNUSED 00 Back to back Turnaround Cycles Bit 1 Bit 0 Rank Read to Read pog 83 Bit 3 Bit 2 Write to Read ey 10 Bit 5 Bit 4 Read to Write 1 200 Bit 7 Bit6 TBD 0 AMB Read Access Time for DDR2 800 AMB LINKPARNXT 1 0 11 84 Bit 3 Bit 0 Read Access Fine Granularity UI 10 4A Bit 7 Bit 4 Read Access Coarse Granularity tCK 4 AMB Read Access Time for DDR2 667 AMB LINKPARNXT 1 0 10 85 Bit 3 Bit 0 Read Access Fine Granularity UI 6 46 Bit 7 Bit 4 Read Access Coarse Granularity tCK 4 AMB Read Access Time for DDR2 533 AMB LINKPARNXT 1 0 01 86 Bit 3 Bit 0 Read Access Fine Granularity UI 8 38 Bit 7 Bit 4 Read Access Coarse Granularity tCK 3 87 Thermal Resistance of AMB Package from Top Case to Ambient 21 2A Psi T A AMB C W AMB Case Temperature Rise from Ambient due to AMB in Idle_0 State
24. information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06026 Revision A 29 Sep 10 Dataram Corporation 2010 Page 18
25. nufacturer s JEDEC ID Code Module ID Module Manufacturer s JEDEC ID Code Module ID Module Manufacturer s JEDEC ID Code Module ID Module Manufacturing Location Module ID Module Manufacturing Date Module ID Module Serial Number date code serial number Cyclical Redundancy Code CRC Cyclical Redundancy Code CRC Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Revision Code UNUSED SDRAM Manufacturer s JEDEC ID Code UNUSED Manufacturer s Specific Data Open for customer use Document 06026 Revision A 29 Sep 10 Dataram Corporation 2010 UNUSED Page 17 lp pve DIM65523C d A Optimizing Value and Performance 4 GB 240 Pin DDR2 FB DIMM IMI DATARAM Ad BOO ptimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The
26. tup tans ns 1 Data hold skew factor tous 0 340 ns 1 Clock Half Period te gek 5 Sh ns a Input Setup Time fast slew rate tis 0 200 ns 2 3 5 6 Input Hold Time fast slew rate tiH 0 275 ns 2 3 5 6 Input Pulse Width tipw 0 6 CLK 6 Write DQS High Level Width toasH 0 35 CLK Write DQS Low Level Width toast 0 35 CLK CLK to First Rising edge to DQS In toass 0 25 0 25 CLK Data In Setup Time to DQS In DQ amp DM tos 0 100 ns Data In Hold Time to DQS In DQ amp DM tox 0 175 ns Notes 1 2 3 For command address input slew rate gt 1 0 V ns 4 For command address input slew rate gt 0 5 V ns and lt 1 0 V ns 5 CK CK slew rates are gt 1 0V ns 6 guaranteed by design or tester correlation 7 This calculation accounts for tpasa max the pulse width distortion of on chip and jitter Data sampled at the rising edges of the clock AO A13 BAO BA2 CKE S 1 0 RAS CAS WE Data latched at both rising and falling edges of Data Strobes DQS These Parameters guarantee device timing but they are not necessarily tested on each device and they may be Document 06026 Revision A 29 Sep 10 Dataram Corporation 2010 Page 11 DP DATARAM DTM65523C Optimizing Value and Performance 4 GB 240 Pin DDR2 FB DIMM AC Operating Conditions AC operating conditions unless otherwise noted Min Max g Parameter Symbol Unit Note Value Value DQ
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