Dataram 2 GB DDR3 DIMM
Contents
1. 8 MTB 11 Medium Timebase MTB Divisor 0 125ns 08 12 SDRAM Minimum Cycle Time tCKmin 1 25ns Ox0A 13 Reserved UNUSED 0x00 CAS Latencies Supported Least Significant Byte Bit 0 CL 4 Bit 1 CL 5 Bit 2 CL 6 X 14 Bit 3 CL 7 X OxFC Bit 4 CL 8 A Bit 5 CL 9 A Bit 6 CL 10 A Bit 7 CL 11 X CAS Latencies Supported Most Significant Byte Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 15 Bit 3 CL 15 0x00 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved 16 Minimum CAS Latency Time tAAmin 13 125ns 0x69 17 Minimum Write Recovery Time tWRmin 15 0ns 0x78 18 Minimum RAS to CAS Delay Time tRCDmin 13 125ns 0x69 19 Minimum Row Active to Row Active Delay Time tRRDmin 6 0ns 0x30 20 Minimum Row Precharge Delay Time tRPmin 13 125ns 0x69 Upper Nibbles for tRAS and tRC 21 Bit 3 Bit 0 tRAS Most Significant Nibble 1 0x11 Bit 7 Bit 4 tRC Most Significant Nibble 1 22 Minimum Active to Precharge Delay Time tRASmin Least 35 0ns 0x18 Significant Byte 23 Minimum Active to Active Refresh Delay Time tRCmin Least 48 125ns 0x81 Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Least Significant 160 0ns 24 Byte 0x00 25 Gs Refresh Recovery Delay Time tRFCmin Most Significant 460 0ns 0x05 26 Minimum Internal Write to Read Command Delay Time tWTRmin 7 5ns 0x3C 27 Minimum Intern2. 1 SPD Revision Rev 1 1 0x11 DDR3 2 _ Key Byte DRAM Device Type spRAM UN Key Byte Module Type 3 Bit 3 Bit 0 Module Type UDIMM 0x02 Bit 7 Bit 4 Reserved 0 SDRAM Density and Banks 4 Bit 3 Bit 0 Total SDRAM capacity in megabits 2Gb 0x03 Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved 0 SDRAM Addressing 5 Bit 2 Bit 0 Column Address Bits 10 0x19 Bit 5 Bit 3 Row Address Bits 15 Bit 7 6 Reserved 0 Module Nominal Voltage VDD Bit 0 NOT 1 5 V operable Bit 1 1 35 V operable Bit 2 1 2X V operable 6 Bit 3 Reserved 0x00 Bit 4 Reserved Bit 5 Reserved Bit 6 Reserved Bit 7 Reserved Module Organization 7 Bit 2 Bit 0 SDRAM Device Width 8 Bits 0x01 Bit 5 Bit 3 Number of Ranks 1 Rank Bit 7 6 Reserved 0 Module Memory Bus Width 8 Bit 2 Bit 0 Primary bus width in bits 64 Bits 0x03 Bit 4 Bit 3 Bus width extension in bits 0 Bits Bit 7 Bit 5 Reserved 0 Fine Timebase FTB Dividend Divisor 9 Bit 3 Bit 0 Fine Timebase FTB Divisor 1 0x11 Bit 7 Bit 4 Fine Timebase FTB Dividend 1 1 MTB 10 Medium Timebase MTB Dividend 0 125ns 001 DE EE EEN Document 06196 Revision A 22 JUN 11 Dataram Corporation 2011 Page 8 Gr DTM64368B qurm iene bs 2 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM
3. current Write Current Geh E E Operating Burst Burst read operating current Read Current oi 120 E Burst Refresh ku Refresh current 960 mA Current Self Refresh Self refresh temperature current MAX Tc 85 C Ipp6 96 mA Current Operating Bank i Interleave Read ZS All bank interleaved read current 1120 mA Current Document 06196 Revision A 22 JUN 11 Dataram Corporation 2011 Page 6 D patagan DTM64368B SEE 2 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit Internal read command to first data taa 13 125 20 ns CAS to CAS Command Delay tceco 4 tck Clock High Level Width tcH avg 0 47 0 53 tck Clock Cycle Time tck 1 25 1 5 ns Clock Low Level Width tcL avg 0 47 0 53 tck Data Input Hold Time after DQS Strobe toH 45 ps DQ Input Pulse Width toipw 360 ps DQS Output Access Time from Clock tbasck 225 225 ps Write DQS High Level Width tbasH 0 45 0 55 tck avg Write DQS Low Level Width toast 0 45 0 55 tck avg DQS Out Edge to Data Out Edge Skew toasa 100 ps Data Input Setup Time Before DQS Strobe tos 10 ps DQS Falling Edge from Clock Hold Time tosH 0 18 tck avg DQS Falling Edge to Clock Setup Time toss 0 18 tck avg Clock Half Period tp minimum of tcx or tet ns Address and Command Hold Time after Clock Dn 120 ps Address and Comm
4. pF DC Characteristics Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current lit 18 18 HA 1 2 Any input 0 V lt VIN lt VDD Output Leakage Current lot 10 10 HA 2 3 0V lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ s DQS DOS and ODT are disabled C E a a a a a y e E ETE Document 06196 Revision A 22 JUN 11 Dataram Corporation 2011 Page 5 D patagan DTM64368B GREE 5 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Test Condition Max unit Value Operating One Bank Active kt Operating current One bank ACTIVATE to PRECHARGE 360 mA Precharge Current Operating One Operating current One bank ACTIVATE to READ to Bank Active Read Ipp1 PRECHARGE 440 mA Precharge Current Precharge Power Ibo2P Precharge power down current Slow exit 96 mA Down Current Precharge Power Ipp2P Precharge power down current Fast exit 120 mA Down Current Precharge Quiet Precharge quiet standby current Standby Current lo02Q 160 mA chara Standby Ipp2N Precharge standby current 160 mA urrent Active Power Down L b Active power down current 160 mA Current pape Standby Ibo3N Active standby current 280 MA urrent Operating Burst Burst write operating
5. 17 30 0 681 5 00 0 197 i SE 5 175 ae 47 00 gt Le 71 00 gt 0 204 1 850 2 795 123 00 4 843 Back view Side view 2 72 Max 0 107 Max 4 00 Min 0 157 Min 1 27 10 Bes 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches eA Sg Pe a FT a ee ey Nee Document 06196 Revision A 22 JUN 11 Dataram Corporation 2011 Page 2 D patagan DTM64368B Opmany Value ard Performer SO DMRO DQSRO DQSRO om DQ S DOS CS DM DQR 7 0 OF 1 0 7 0 DMR1 DQSsR1 DQSR1 DQ S DOS CS DM DAR 15 8 O 1 0 7 0 DMR2 DQSR2 DQSR2 IDQS DAS DAR 23 16 O 1 0 17 0 DMR3 DQSR3 DQSR3 Or DQS DOS CS DM DQR 31 24 O 1 0 7 0 All 15 OHMS DQ 63 0 O VWA O DARI63 0 DOStz 0 O VA O DQRSI7 0 DQS 7 0 O VWA O DQRS 7 0 DM 7 0 O VA O_DMRIZ 0 GLOBAL SDRAM CONNECTS All 39 OHMS BA 2 0 A 14 0 IRAS ICAS IWE VTT All 39 OHMS CKEO ODTO SO VTT All 240 OHMS ZQ ow V Vss 2 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM DMR4 DQASR4 CH DQSR4 DQS DAS CS DM DQR 39 32 O 1 0 7 0 DMRS DQSR5 DQSR5 DQS DOS CS DM DQR 47 40 O 1 0 7 0 DMR6 DQSR6 DQSR6 DQS DOS CS DM DAR 55 48 O 1 0 7 0 DMR7 DQSR7 O _ DQSR
6. 7 DQS DOS CS DM DQR 63 56 O 1 O 7 0 2 2 pF cko O o _ cko VDD All 36 OHMS 100 nf CKO 75 OHMS CK1 O VW O CK1 V DECOUPLING DDSPD 4 Serial PD VDD zs All Devices VREF_DQ All SDRAMs Vss ES All Devices VREF_CA All SDRAMs Mrt Al SDRAM SCL SERIAL PD SDA SAO SA1 SA2 Document 06196 Revision A 22 JUN 11 Dataram Corporation 2011 D patagan DTM64368B 2 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM Opening Wue and Performans Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TsTORAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperature Operating Tease 0 95 C Voltage on Vpp relative to Vss Vop 0 4 1 975 V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Vop 1 425 1 5 1 575 V UO Reference Voltage VREFDQ 0 49 Mon 0 50 Mon 0 51 Von V 1 UO Reference Voltage VREFCA 0 49 Vpop 0 50 Von 0 51 Voo V 1 Notes 1 The value of Vrer is expected to equal one half Voo and to track variations in the Voo DC level Peak
7. 8 Voo 108 DQ56 138 DQ15 168 RESET 198 S3 NC 228 DQ61 RESET Reset for register and DRAMs 19DQ11 49 Vir 79 S2 NC 109 DQ57 139Vss 169 CKE1 NC 199 Vss 229 Vss PAR_IN Parity bit for Addr Ctrl 20Vss 50 CKEO 80 Vss 110Vss 140 DQ20 170 Voo 200DQ36 230DM7 ERR_OUT Error bit for Parity Error 21 DQ16 51 Mon 81 DQ32 111 DQS7f141 DQ21 171 A15 201 DQ37 231 NC A12 BC Combination input Addr12 Burst Chop 22 DQ17 52 BA2 82 DQ33 112 DQS7 f42 Vss 172 A14 202 Vss 232 Vss A10 AP Combination input Addr10 Auto precharge 23Vss 53 Err_Our NC 83 Vss 113Vss 143 DM2 173 Voo 203 DM4 233 DQ62 Vss Ground 24 IDQS254 Mon 84 DQS4 114 DQ58 144NC 174A12 BC 204 NC 234 DQ63 Von Power 25 DQS2 55 A11 85 DQS4 115 DQ59 f145 Vss 175 A9 1205 Vss 235 Vss VopsPo SPD EEPROM Power 26Vss 56A7 86 Vss 116Vss 146 DQ22 176 Voo 206 DQ38 236 Voperg VreFDa Reference Voltage for DO e 27 DQ18 57 Voo 87 DQ34 117 SA0 147 DQ23 177 A8 207 DQ39 237 SA1 Vreca Reference Voltage for CA 28 DQ19 58 A5 88 DQ35 118 SCL f148Vss 178 A6 1208 Vss 238 SDA Vr Termination Voltage 29Vss 59A4 89 Vss 119SA2 149DQ28 179 Voo 209DQ44 239Vss NC No Connection 30 DQ24 60 Ven 90 DQ40 120 ver 150 DQ29 180 A3 210 DQ45 240 ven Not used Document 06196 Revision A 22 JUN 11 Dataram Corporation 2011 Page 1 rr DIM64368B 2 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM Front view L 133 35 l 5 250 9 50 0 374 30 00 1 181 C
8. 82 Voo 212DM5 DQ 63 0 Data Bits 3 DQO 33 DQS3 63 CK1 93 DQS5123 DAS 153 NC 183 Voo 213 NC DQS 8 0 DQS 8 0 Differential Data Strobes 4 DQ1 34DQS3 64 CK1 194 DQS5 f124Vss 154 Vss 184 CKO 214 Vss DM 8 0 Data Mask 5 Vss 35 Vss 65 Voo 95 Vss 125DMO 155 DQ30 185 CKO 215 DQ46 CK 1 0 CK 1 0 Differential Clock Inputs 6 DQS0 36 DQ26 66 Voo 96 DQ42126NC 156 DQ31 186 Voo 216 DQ47 CKE 1 0 Clock Enables 7 DQSO 37 DQ27 67 Vrerca 97 DQ43 127 Vss 157 Vss 187 Event NC 217 Vss CAS Column Address Strobe 8 Vss 38 Vss 68 Pag In NC 98 Vss f128DQ6 158 CB4 NC 188 An 218 DQ52 RAS Row Address Strobe 9 DQ2 39CB0 NC 69 VDD 99 DQ48 129 DQ7 159 CB5 NC 189 Vpp 219DQ53 S 8 0 Chip Selects 10DQ3 40 CB1 NC 70A10 AP 100 DQ49 f130 Vss 160 Vss 190 BA1 220 Vss WE Write Enable 11Vss 141 Vss 71 BAO 101Vss 131 DQ12 161 DM8 NC 191 Von 221DM6 A 15 0 Address Inputs 12DQ8 42 DQS8 NC 72 Vpop 102 DQS6f132 DQ13 162 NC 192 RAS 222 NC BA 2 0 Bank Addresses 13DQ9 43DQS8 NC_ 73 WE 103 DQS6 f133 Vss 163 Vss 193 S0 223 Vss ODT 1 0 On Die Termination Inputs 14Vss MA Vss 74 ICAS 104Vss 134DM1 164 CB6 NC 194 Von 224 DQ54 SA 2 0 SPD Address 15 DQS1 45 CB2 NC 75 Voo 105DQ50135NC 165CB7 NC 1950DTO 225DQ55 SCL SPD Clock Input 16 DQS1 46 CB3 NC 76 S1 NC 106 DQ51 136 ve 166 Vss 196 A13 226 Vss SDA SPD Data Input Output 17 Vss MI Vss 77 ODT1 NC 107 Vss 137 DQ14 167 NC TEST 197 Voo 227 DQ60 EVENT Temperature Sensing 18 DQ10 48 Vrr 7
9. Module Part Number 0 0x30 ee Module Part Number 0x20 kee Module Revision Code UNUSED 0x00 148 DRAM Manufacturer ID Code Least Significant Byte 0x80 149 DRAM Manufacturer ID Code Most Significant Byte OxCE a Manufacturer s Specific Data 0x00 Kies Open for customer use UNUSED 0x00 Note Bytes 119 125 and 150 255 may be different then shown A a E ee I a ee ga SE a yen Document 06196 Revision A 22 JUN 11 Dataram Corporation 2011 Page 11 tr DIM64368B 2 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM B genet hed sd Wegen DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06196 Revision A 22 JUN 11 Dataram Corporation 2011 Page 12
10. al Read to Precharge Command Delay Time 7 5ns 0x3C tRTPmin Upper Nibble for tFAW 28 Bit 3 Bit 0 tFAW Most Significant Nibble 0 0x00 Bit 7 Bit 4 Reserved 0 aS eae aE a a o d a EE Document 06196 Revision A 22 JUN 11 Dataram Corporation 2011 Page 9 Gr _DTM64368B quinones 2 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM 29 Oe a Window Delay Time tFAWmin Least 30 0ns OxFO SDRAM Optional Features Bit 0 RZQ 6 X 30 Bit 1 RZQ 7 X 0x83 Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support SDRAM Drivers Supported Extended Temperature Range X Extended Temperature Refresh Rate Auto Self Refresh ASR 31 On die Thermal Sensor ODTS Readout 0x01 Reserved Reserved Reserved Partial Array Self Refresh PASR Module Thermal Sensor 32 Bit 6 Bit 0 Thermal Sensor Accuracy 0 0x00 Bit 7 Thermal Sensor No TS SDRAM Device Type Bit 6 Bit 0 Non Standard Device Description 0 33 Bit 7 SDRAM Device Type Std Mono 0x00 Reserved UNUSED 0x00 Module Nominal Height 60 Bit 4 Bit 0 Module Nominal Height max inmm 29 lt h lt 30 0x0F Bit 7 Bits Reserved 0 Module Maximum Thickness 61 Bit 3 Bit 0 Front in mm baseline thickness 1mm 1 lt th lt 2 0x01 Bit 7 Bit 4 Back in mm baseline thickness 1 mm th lt 1 Reference Raw Card Used 62 B
11. and Setup Time before Clock tis 45 ps Load Mode Command Cycle Time turD 4 tck DQ to DQS Hold Lou 0 38 tcK avg Active to Precharge Time tras 35 O treFI ns Active to Active Auto Refresh Time tre 48 125 ns RAS to CAS Delay trop 13 125 ns Average Periodic Refresh Interval 0 C lt Tcase lt 85 C REFI 7 8 us Average Periodic Refresh Interval 0 C lt Tcase lt 95 C REFI 3 9 us Auto Refresh Row Cycle Time trFc 160 ns Row Precharge Time trp 13 125 ns Read DQS Preamble Time RPRE 0 9 Note 1 tck avg Read DQS Postamble Time terest 0 3 Note 2 tck avg Row Active to Row Active Delay trRD Max 4nCK 6ns ns Internal Read to Precharge Command Delay for Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twpRE 0 9 tck avg Write DQS Postamble Time twpst 0 3 tck avg Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min 2 The maximum postamble is bound by tHZDQS max Document 06196 Revision A 22 JUN 11 Dataram Corporation 2011 Page 7 Gr _DTM64368B onnaa Ds 2 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Byte Function Value Hex Number of Bytes Used Number of Bytes in SPD Device CRC Coverage 0 Bit 3 Bit 0 SPD Bytes Used 176 0x92 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116
12. cr DIM64368B 2 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM Identification DTM64368B 256Mx64 2GB 1Rx8 PC3 12800U 11 11 A1 Performance range Clock Module Speed CL trep Ze 800 MHz PC3 12800 11 11 11 667 MHz PC3 10600 10 10 10 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Features Description 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high DTM64368B is an Unbuffered 256Mx64 memory module which conforms to Operating Voltage 1 5 V 0 075 JEDEC s DDR3 PC3 12800 standard The UO Type SSTL_15 assembly is single rank comprised of eight i 256Mx8 DDR3 Samsung SDRAMs One Data Transfer Rate 12 8 Gigabytesisec 2K bit EEPROM is used for Serial Presence Data Bursts 8 and burst chop 4 mode Detect ZQ Calibration for Output Driver and On Die Termination ODT Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 6 7 8 9 10 and 11 Differential Data Strobe signals SDRAM Addressing Row Col Bank 15 10 3 Fully ROHS Compliant Pin Configuration Pin Description Front Side Back Side Name Function 1 Vprerpa 31 DQ25 61 A2 91 DQ41121Vsg_ 151 Vss 181 A1 211Vss CBL7 0 Data Check Bits 2 Vss 32 Vss 62 Ven 92 Vss 122 DQ4 152 DM3 1
13. it 4 Bit 0 Reference Raw Card RICA 0x20 Bit 6 Bit 5 Reference Raw Card Revision Rev 1 Bit 7 Reserved 0 Address Mapping from Edge Connector to DRAM 63 Bit 0 Rank 1 Mapping Registered DIMM Reserved Standard 0x00 Bit 7 Bit 1 Reserved 0 ae Module Specific Section UNUSED 0x00 117 Module Manufacturer ID Code Least Significant Byte 0x80 118 Module Manufacturer ID Code Most Significant Byte OxCE 119 Module Manufacturing Location 0x01 120 Module Manufacturing Date 0x11 a EEGENEN Document 06196 Revision A 22 JUN 11 Dataram Corporation 2011 Page 10 Gr DTM64368B mae 2 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM 121 Module Manufacturing Date 0x15 122 Module Serial Number 0x47 123 Module Serial Number 0x19 124 Module Serial Number OxEE 125 Module Serial Number OxE8 126 Cyclical Redundancy Code CRC CRC 0xC1 127 Cyclical Redundancy Code CRC CRC 0x09 128 Module Part Number M 0x4D 129 Module Part Number 3 0x33 130 Module Part Number 7 0x37 131 Module Part Number 8 0x38 132 Module Part Number B 0x42 133 Module Part Number 5 0x35 134 Module Part Number 7 0x37 135 Module Part Number 7 0x37 136 Module Part Number 3 0x33 137 Module Part Number D 0x44 138 Module Part Number H 0x48 139 Module Part Number 0 0x30 140 Module Part Number 0x2D 141 Module Part Number C 0x43 142 Module Part Number K 0x4B 143
14. to peak noise on Vrer may not exceed 1 of its DC value For Reference Vpp 2 15 mV DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vue VREF 0 1 Vpop V Logical Low Logic 0 Vuupe Vss Veer 0 1 V AC Input Logic Levels Single Ended T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin ac VREF 0 175 vV Logical Low Logic 0 Vuac Vrer 0 175 V Document 06196 Revision A 22 JUN 11 Dataram Corporation 2011 Page 4 D patagan DTM64368B 2 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM Opeerging aue and Performa Differential Input Logic Levels T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Differential Input Logic High VIH DIFF 0 200 DC Vpp AC Vppt0 4 V Differential Input Logic Low Vu pr DC Vss AC Vss 0 4 0 200 V eer ek Cross Point Voltage Vx 0 150 0 150 v Capacitance T 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO Cox 8 4 13 2 pF Input Capacitance Address BA 2 0 A 14 0 RAS CAS ANE Ci 6 10 4 pF Input Capacitance Control SO CKEO ODTO Ci 6 10 4 Input Output Capacitance o DQS 7 0 DQS 7 0 Cio 1 4 2 3 pF ZQ Capacitance ZQ Cza 6
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