Dataram 2GB DDR3 DIMM
Contents
1. 0x00 28 Bit 3 Bit 0 FAW Most Significant Nibble 0 Bit 7 Bit 4 Reserved 0 29 Minimum Four Activate Window Delay Time tFAWmin Least 30 0ns OxFO Significant Byte SDRAM Optional Features Bit 0 RZQ 6 X ER Bit 1 RZQ 7 X Ee Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support SDRAM Drivers Supported Extended Temperature Range X Extended Temperature Refresh Rate 31 Auto Self Refresh ASR 0x01 On die Thermal Sensor ODTS Readout i Reserved Reserved Reserved Partial Array Self Refresh PASR Module Thermal Sensor 32 Bit 6 Bit 0 Thermal Sensor Accuracy 0 0x80 Bit 7 Thermal Sensor With TS SDRAM Device Type Bit 6 Bit 0 Non Standard Device Description 0 33 Bit 7 SDRAM Device Type Std Mono 0x00 34 59 Reserved UNUSED 0x00 Module Nominal Height 60 Bit 4 Bit 0 Module Nominal Height max in mm 29 lt h lt 30 OXOF Bit 7 Bits Reserved 0 Module Maximum Thickness 61 Bit 3 Bit 0 Front in mm baseline thickness 1mm T lt th lt 2 OX Bit 7 Bit 4 Back in mm baseline thickness 1 mm 1 lt th lt 2 Reference Raw Card Used 62 Bit 4 Bit 0 Reference Raw Card R C B 0x21 Bit 6 Bit 5 Reference Raw Card Revision Rev 1 Bit 7 Reserved 0 Registered DIMM Module Attributes 63 Bit 1 Bit 0 of Registers used on RDIMM 1 Register 0x05 Bit 3 Bit 2 of Rows of DRAMs on RDIMM 1 Row Bit 7 Bit 4 Reserved 0 Document 062. RC6 LS Nibble UNUSED 0x00 73 SSTE32882 RC9 MS Nibble RC8 LS Nibble UNUSED 0x00 74 SSTE32882 RC11 MS Nibble RC10 LS Nibble UNUSED 0x00 75 SSTE32882 RC13 MS Nibble RC12 LS Nibble UNUSED 0x00 76 SSTE32882 RC15 MS Nibble RC14 LS Nibble UNUSED 0x00 i 2 5 Module Specific Section UNUSED 0x00 113 Module Specific Section UNUSED 0x00 pe Module Specific Section UNUSED 0x00 117 Module Manufacturer ID Code Least Significant Byte 0x80 118 Module Manufacturer ID Code Most Significant Byte OxCE 119 Module Manufacturing Location 0x01 ae Module Manufacturing Date 0x20 Kee Module Serial Number 0x20 126 Cyclical Redundancy Code CRC CRC 0x66 127 Cyclical Redundancy Code CRC CRC 0x11 Document 06494 Revision A 04 Aug 11 Dataram Corporation 2011 Page 11 IYPDATARAM DTM64332B 2GB 240 Pin 2Rx8 Registered ECC LV DDR3 DIMM Migra Value aed Pifo 128 Module Part Number M 0x4D 129 Module Part Number 3 0x33 130 Module Part Number 9 0x39 131 Module Part Number 3 0x33 132 Module Part Number B 0x42 133 Module Part Number 5 0x35 134 Module Part Number 6 0x36 135 Module Part Number 7 0x37 136 Module Part Number 3 0x33 137 Module Part Number G 0x47 138 Module Part Number B 0x42 139 Module Part Number 0 0x30 140 Module Part Number 0x2D 141 Module Part Number Y 0x59 142 Module Part Number H 0x48 143 Module Part Number 9 0x39
3. Kee Module Part Number 0x20 e Module Revision Code UNUSED 0x00 148 DRAM Manufacturer ID Code Least Significant Byte 0x80 149 DRAM Manufacturer ID Code Most Significant Byte OxCE Kee Manufacturer s Specific Data UNUSED 0x00 es Open for customer use UNUSED 0x00 Note Serial Presence Detect shown for reference only Bytes 119 125 146 147 150 255 value may vary Document 06494 Revision A 04 Aug 11 Dataram Corporation 2011 Page 12 EE 2GB 240 Pin 2Rx8 Registered ECC LV DDR3 DIMM Wen DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06494 Revision A 04 Aug 11 Dataram Corporation 2011 Page 13
4. CBR 7 0 TO SDRAMS VDD Von All All 39 OHMS 100 nF All 39 OHMS 100 nF 22 OHMS r All 15 OHMS See Ee IS LCLK 1 0 RCLK 1 0 DOIS3 0 O WA O g Q 63 0 63 0 IS1 WJ IRS1 ILCLKI1 0 IRCLKI1 0 CB 7 0 O VVW CBR OI PART Mu BA 2 0 R A 15 0 VWA H AAR DQS 8 0 O VWA O _ DasR s 0 RAS WW aen DQS 8 0 O WAN O_ DASRIB 0 CAS WN ty fe ee ME WA I WER DM 8 0 O VW O_ DMRJB 0 CKEO VWW a CKEOR vo ja CKE1 WA X CKEIR DECOUPLING i ITDQS 17 9 OWA O TDQSR 17 9 ODT AN 9 SCENE VDDSPD te Serial PD ODT w Ka oprup VDD All Devices PAR_IN WA ERR OUT VREF_DQ t T All SDRAMs GLOBAL SDRAM CONNECTS Co L R CLK 1 0 y Vss All Devices 120 3 All 39 OHMS OHMS REF_CA All SDRAMs BA 2 0 R ICKO L R CLK 1 0 VTT m AI SDRAMs IRASR SDRAMS cK1 ICASR INER VTT 120 OFM KZ EVENT All 240 OHMS TEMPERATURE MONITOR Se All 39 OHMS D SCL Berg SDA 8 NM ODT 1 0 R owed SAO SA1 SA2 RS 1 0 VTT Vss Document 06494 Revision A 04 Aug 11 Dataram Corporation 2011 Page 3 IYPDATARAM DTM64332B NE 2GB 240 Pin 2Rx8 Registered ECC LV DDR3 DIMM Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TsTORAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperature
5. Pin 2Rx8 Registered ECC LV DDR3 DIMM Front view 9 50 0 374 30 00 1 184 Lt 17 30 0 681 O MAMNNNNNNNNNMMNNNNNNNNNNNNNNNNNNNNNNNMNN ANNM O y 5 00 4 0 197 2 50 5 175 47 00 mrm 0 098 ra e 0 204 1 850 2 795 123 00 4 843 Back view Side view a 4 00Max 0 157 Max 4 00 Min 0 157 Min 1 27 10 alle 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches a ge Document 06494 Revision A 04 Aug 11 Dataram Corporation 2011 Page 2 Value aed Performan erster DTM64332B NIT 2GB 240 Pin 2Rx8 Registered ECC LV DDR3 DIMM IRS1 O IS DQSRO DQSR4 DQSRO DQSR4 DMRO DMR4 ITDQSR9 ITDQSR13 Ra Oo oO o Ra Oo 0 2 26 468 26 26866 26 268 6S ke a a oo a a aG Eo ES E E S DQRI7 0 VO 7 0 RANK 0 VO 7 0 RANK 1 DAR 39 32 OJ 0 7 0 RANK 0 VO 7 0 RANK 1 DQSR1 DQSR5 DQSR1 DQSR5 DMR DMR5 ITDQSR10 ITDQSR14 DQR 15 8 DQR 47 40 O I 017 0 DpasR20 DQSR6 O DQSR2 DQSR6 DMR2 DMR6 TDQSR11 TDQSR15 DN Go ND SO ZOO OO a E EN E EES DQR 23 16 DQR 55 48 O VO 7 0 DQSR3 DQSR7 O DQSR3 DQSR7 O DMR3 DMR7O TDQSR12 ITDQSR16 O DQR 31 24 DQR 63 56 DQSR8 IDQSR8 O DMR8 TDQSR17
6. 1 0 On Die Termination Inputs 15 DQS1 45 CB2 75 Ven 105 DQ50 135 TDQS10 165 CB7 195 ODTO 225 DQ55 SA 2 0 SPD Address 16 DQS1 46 CB3 76 S1 106 DQ51 136 Vss 166 Vss 196 A13 226 Vss SCL SPD Clock Input 17 Vss 47 Vss 77 ODT1 107 Vss 137DQ14 167 NC TEST 197 Ven 227 DQ60 SDA SPD Data Input Output 18 DQ10 48 Vrr 78 Voo 108 DQ56 138DQ15 168 RESET 198 S3 NC 228 DQ61 Vss Ground 19DQ11 49 Vrr 79 S2 NC 109 DQ57 139 Vss 169 CKE1 199 Vss 229 Vss Von Power 20Vss 50 CKEO 80 Vss 110 Vss 140DQ20 170 Voo 200 DQ36 230 DM7 Vppspp SPD EEPROM Power 21 DQ16 51 Voo 81 Doan 111 DQS7 baupon aas 201 DQ37 231 TDQS16 VReFDa Reference Voltage for DQ 22 DQ17 52 BA2 82 Doan 112 DQS7 142 Vss 172 A14 202 Vss 232 Vss VreFcA Reference Voltage for CA 23Vss 53 Err_Our 83 Vss 113 Vss 143DM2 173 Voo 203 DM4 233 DQ62 Ver Termination Voltage 24 IDQS2 54 Non 84 DQS4 114 DQ58 144 TDQS11 174 A12 BC 204 TQDS13 234 DQ63 Event Temperature Sensing 25 DQS2 55 A11 85 DQS4 115 DQ59 145 Vss 175 AQ 205 Vss 235 Vss NC No Connection 26Vss BEAT ER Vss 116 Vss 146DQ22 176 Voo 206 DQ38 236 Vater 27 DQ18 57 Voo 87 DQ34 117 SAO 147DQ23 177 A8 207 DQ39 237 SA1 28 DQ19 58 A5 88 DQ35 Hi SCL 148 Vss 178 A6 208 Vss 238 SDA 29Vss 59A4 89 Vss 119 SA2 149DQ28 179 Voo 209 DQ44 239 Vss 30 DQ24 60 Voo 90 DQ40 120 Vrr 150DQ29 180 A3 210 DQ45 240 Vrr Not used Document 06494 Revision A 04 Aug 11 Dataram Corporation 2011 Page 1 Tg DTM64332B 2GB 240
7. 494 Revision A 04 Aug 11 Dataram Corporation 2011 Page 10 IYPDATARAM DTM64332B M n Wue aed Performan 2GB 240 Pin 2Rx8 Registered ECC LV DDR3 DIMM RDIMM Thermal Heat Spreader Solution 0x00 64 Bit 6 Bit 0 Heat Spreader Thermal Characteristics 0 Bit 7 Heat Spreader Solution No HS 65 Register Manufacturer ID Code Least Significant Byte Optional 0x04 66 Register Manufacturer ID Code Most Significant Byte Optional OxB3 67 Register Revision Number Optional 0x21 Register Type 68 Bit 2 0 Support Device SSTE32882 9x00 Bit 7 3 Reserved 0 69 SSTE32882 RC1 MS Nibble RCO LS Nibble UNUSED 0x00 SSTE32882 RC3 MS Nibble RC2 LS Nibble Drive Strength Command Address 70 Bit 1 Bit 0 RC2 DA3 4 Value RESERVED 0x50 Bit 3 Bit 2 RC2 DBAO 1 Value RESERVED Bit 5 Bit 4 RC3 DA4 3 value Command Address A Outputs Moderate Bit 7 Bit 6 RC3 DBAO 1 value Command Address B Outputs Moderate SSTE32882 RC5 MS Nibble RC4 LS Nibble Drive Strength Control and Clock 71 Bit 1 Bit 0 RC4 DA3 4 Control Signals A Outputs Light 0x00 Bit 3 Bit 2 RC4 DBAO 1 Control Signals B Outputs Light Bit 5 Bit 4 RC5 DA4 3 value Y1 Y1 and Y3 Y3 Clock Outputs Light Bit 7 Bit6 RC5 DBAO0 1 value YO YO and Y2 Y2 Clock Outputs Light 72 SSTE32882 RC7 MS Nibble
8. Bit 6 CL 10 Bit 7 CL 11 CAS Latencies Supported Most Significant Byte Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 13 Bit 3 CL 15 0x00 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved 16 Minimum CAS Latency Time tAAmin 13 125ns 0x69 17 Minimum Write Recovery Time tWRmin 15 0ns 0x78 18 Minimum RAS to CAS Delay Time tRCDmin 13 125ns Ox69 19 Minimum Row Active to Row Active Delay Time tRRDmin 6 0ns 0x30 20 Minimum Row Precharge Delay Time tRPmin 13 125ns 0x69 Upper Nibbles for tRAS and tRC 21 Bit 3 Bit 0 tRAS Most Significant Nibble 1 0x11 Bit 7 Bit 4 tRC Most Significant Nibble 1 Minimum Active to Precharge Delay Time tRASmin Least SS Significant Byte Sells on 23 Minimum Active to Active Refresh Delay Time tRCmin Least 49 125ns_ 0x89 Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Least Significant 110 0ns 24 Byte 0x70 25 ial Refresh Recovery Delay Time tRFCmin Most Significant 110 0ns 0x03 26 Minimum Internal Write to Read Command Delay Time tWTRmin 7 5ns 0x3C 27 Minimum Internal Read to Precharge Command Delay Time 7 5ns 0x3C tRTPmin C a Document 06494 Revision A 04 Aug 11 Dataram Corporation 2011 Page 9 D Pinay DIM64332B Opongny Wate aed Prater 2GB 240 Pin 2Rx8 Registered ECC LV DDR3 DIMM Upper Nibble for tFAW
9. DTM64332B 2GB 240 Pin 2Rx8 Registered ECC LV DDR3 DIMM Identification DTM64332B 256Mx72 2GB 2Rx8 PC3L 10600R 9 11 B1 Performance range Clock Module Speed CL trep Ze 667 MHz PC3L 10600 9 9 9 533 MHz PC3L 8500 8 8 8 533 MHz PC3L 8500 7 7 7 400 MHz PC3L 6400 6 6 6 Features Description 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high DTM64332B is a registered 256Mx72 memory _ _ module which conforms to JEDEC s DDR3L Operating Voltage VDD VDDQ 1 35V 1 283V to 1 45V PC3L 10600 standard The assembly is Dual Backward compatible to VDD VDDQ 1 5V 0 075V Rank Each Rank is comprised of nine 128Mx8 On board 12C temperature sensor with integrated serial presence detect DDR3 Samsung SDRAMs One 2K bit EEPROM SPD EEPROM is used for Serial Presence Detect and a combination register PLL with Address and Command Parity is also used Data Bursts 8 and burst chop 4 mode Both output driver strength and input termination ZQ Calibration for Output Driver and On Die Termination ODT impedance are programmable to maintain signal integrity on the I O signals in a Fly by topology A thermal sensor accurately monitors the DIMM Programmable CAS Latency 6 7 8 and 9 module and can prevent exceeding the maximum operating temperature of 95C Data Transfer Rate 10 6 Gigabytes sec Programmable ODT Dynamic ODT during Writes Bi Directional Diff
10. Operating Tease 0 95 C Voltage on Vpp relative to Vss Vop 0 4 1 975 V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Operation Minimum Typical Maximum Unit Note Voltage Power Supply Voltage Voo 1 35V 1 283 1 35 1 4500 v 1 5V 1 425 1 5 1 575 UO Reference Voltage 1 35V VREFDQ 0 49 Von 0 50 Mo 0 51 Mon V 1 1 5V UO Reference Voltage 1 35V VREFCA ER 0 49 Von 0 50 Mo 0 51 Mon V 1 Notes 1 For Reference Vpp 2 15 mV The value of VREF is expected to equal one half VDD and to track variations in the VDD DC level Peak to peak noise on VREF may not exceed 1 of its DC value For Reference VREF VDD 2 15 mV DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Operation Minimum Maximum Unit Voltage Logical High Logic 1 Vue 1 35V Vrer 0 09 Von V 1 5V Veer 0 1 Von Logical Low Logic 0 Vuupe 1 35V Vss Vrer 0 09 V 1 5V Vss Veer 0 1 AC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Operation Minimum Maximum Unit Voltage Logical High Logic 1 Vin ac 1 35V Vrer 0 160 V 1 5V Vrer 0 175 Logical Low Logic 0 Vilac 1 35V Vrer 0 160 V 1 5V Vrer 0 175 i i Doc
11. Registered ECC LV DDR3 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Test Condition Max Value Loen 1 35V 1 5V Operating One f Bank Active kaf Operating current One bank ACTIVATE to PRECHARGE 998 1120 mA Precharge Current Operating One Operating current One bank ACTIVATE to READ to Bank Active Read Ipp1 PRECHARGE 1090 1183 mA Precharge Current Precharge Power L b Precharge power down current Slow exit 720 760 mA Down Current Precharge Power L b Precharge power down current Fast exit 756 796 mA Down Current Precharge Quiet Precharge quiet standby current Standby Current oc 9067 EE AE Precharge Standby Ipp2N Precharge standby current 816 920 mA Current Active Power Down Active power down current Current Ipp3P 756 850 mA Active Standby Ibo3N Active standby current 906 1000 mA Current Operating Burst x Burst write operating current Write Current lbo4W 1323 1445 mA Operating Burst Burst read operating current Read Current Ipp4R 1313 1435 mA Burst Refresh Ipp5 Refresh current 1473 1585 mA Current Refresh L Self refresh temperature current MAX Tc 85 C 210 210 mA urrent Operating Bank z ntericave Read Ipp7 All bank interleaved read current 1853 1975 mA Current One module rank in this operation the rest in IDD2P slow exit Document 06494 Rev
12. erential Data Strobe signals SDRAM Addressing Row Col Bank 14 10 3 Fully ROHS Compliant Pin Configuration Pin Description Front Side Back Side Name Function 1 Vrerpa 31 DQ25 61 A2 gi DQ4 121 Vss 151 Vss 181 A1 211 Vss CB 7 0 Data Check Bits 2 Ven 32Vss 62 Ven 92 Ve 122 DQ4 152 DM3 182 Vpp 212 DM5 DQ 63 0 Data Bits 3 DQO 33 DQS3 63 CK1 o DQS5 123DQ5 153 TDQS12 183 ven 213 TDQS14 DQSI8 0 DAS 8 0 Differential Data Strobes 4 Da1 34DQs3 64 CK1 94 DQS5 124 Vsg 154 Vss 184 CKO 214 Vss DM 8 0 Data Mask 5 Vss 35 Vss 65 Ven 95 Vss H25DMO 155 DQ30 185 CKO 215 DQ46 TDQS 17 9 Termination Data Strobes 6 DQSO 36 DQ26 66 Von 96 DQ42 126 TDQS9 156 DQ31 186 Von 216 DQ47 CK 1 0 CK 1 0 Differential Clock Inputs 7 DQSO 37 DQ27 67 Vrerca 97 DQ43 127 Vss 157 Vss 187 Event 217 Vss CKE 1 0 Clock Enables 8 Vss 38 Vss 68 Parin 98 Vss H28DQ6 158 CB4 188 AO 218 DQ52 ICAS Column Address Strobe 9 DQ2 39CBO 69 VDD 99 DQ48 H29DQ7 159 CB5 189 Ven 219 DQ53 IRAS Row Address Strobe 10DQ3 40CB1 70 A10 AP 100 DQ49 130 Vss 160 Vss 190 BA1 220 Vss S 3 0 Chip Selects 171 Ve MI Vss 71 BAO 101 Vss 131DQ12 161 DM8 191 Ven 221 DM6 INE Write Enable 12DQ8 42 DQS8 72 Von 102 DQS6 f132DQ13 162 TTDQS17 192 RAS 222 TDQS15 A 15 0 Address Inputs 13DQ9 43 DQS8 73 MWE 103 DQS6 f133Vss 163 Vss 193 S0 223 Vss BA 2 0 Bank Addresses 14Vss 44Vss 74 ICAS 104 Vss 134 DM1 164 CB6 194 Von 224 DQ54 ODT
13. ision A 04 Aug 11 Dataram Corporation 2011 Page 6 IYPDATARAM DTM64332B EN 2GB 240 Pin 2Rx8 Registered ECC LV DDR3 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit Internal read command to first data taa 13 125 20 ns CAS to CAS Command Delay tceco 4 tck Clock High Level Width tcH avg 0 47 0 53 tck Clock Cycle Time tck 1 5 1 875 ns Clock Low Level Width tcL avg 0 47 0 53 tck Data Input Hold Time after DQS Strobe toH 65 ps DQ Input Pulse Width toipw 400 ps DQS Output Access Time from Clock tpascK 255 255 ps Write DQS High Level Width Iooen 0 45 0 55 tck avg Write DQS Low Level Width toast 0 45 0 55 tck avg DQS Out Edge to Data Out Edge Skew toasa 125 ps Data Input Setup Time Before DQS Strobe tos 30 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tck avg DQS Falling Edge to Clock Setup Time toss 0 2 tck avg Clock Half Period tHP minimum of tcy or teL ns Address and Command Hold Time after Clock Du 140 ps Address and Command Setup Time before Clock tis 65 ps Load Mode Command Cycle Time turD 4 tck DQ to DQS Hold Lou 0 38 tcx avg Active to Precharge Time tras 36 O tREFI ns Active to Active Auto Refresh Time tre 49 125 ns RAS to CAS Delay trop 13 125 ns Average Periodic Refresh Interval 0 C lt Tcase lt 85 C REFI 7 8 us Average Periodic Refresh Inte
14. it 0 Column Address Bits 10 0x11 Bit 5 Bit 3 Row Address Bits 14 Bit 7 6 Reserved 0 Module Nominal Voltage VDD Bit 0 NOT 1 5 V operable Bit 1 1 35 V operable X Bit 2 1 2X V operable 6 Bit 3 Reserved 0x02 Bit 4 Reserved Bit 5 Reserved Bit 6 Reserved Bit 7 Reserved Module Organization 7 Bit 2 Bit 0 SDRAM Device Width 8 Bits 0x09 Bit 5 Bit 3 Number of Ranks 2 Rank Bit 7 6 Reserved 0 Module Memory Bus Width 8 Bit 2 Bit 0 Primary bus width in bits 64 Bits 0x0B Bit 4 Bit 3 Bus width extension in bits 8 Bits Bit 7 Bit 5 Reserved 0 Fine Timebase FTB Dividend Divisor 9 Bit 3 Bit 0 Fine Timebase FTB Divisor 1 0x11 Bit 7 Bit 4 Fine Timebase FTB Dividend 1 1 MTB 10 Medium Timebase MTB Dividend 0 125ns Hl Document 06494 Revision A 04 Aug 11 Dataram Corporation 2011 Page 8 IYPDATARAM DTM64332B 2GB 240 Pin 2Rx8 Registered ECC LV DDR3 DIMM Opry Wue aed Petters 8 MTB 11 Medium Timebase MTB Divisor 0 125ns HU 12 SDRAM Minimum Cycle Time tCKmin 1 5ns 0x0C 13 Reserved UNUSED 0x00 CAS Latencies Supported Least Significant Byte Bit 0 CL 4 Bit 1 CL 5 Bit 2 CL 6 X 14 Bit 3 CL 7 X 0x3C Bit 4 CL 8 X Bit 5 CL 9 X
15. rval 0 C lt Tcase lt 95 C REFI 3 9 us Auto Refresh Row Cycle Time trFc 110 ns Row Precharge Time trp 13 125 ns Read DQS Preamble Time RPRE 0 9 Note 1 tck avg Read DQS Postamble Time terest 0 3 Note 2 tck avg Row Active to Row Active Delay trRD Max 4nCK 6ns ns Internal Read to Precharge Command Delay for Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twPRE 0 9 tck avg Write DQS Postamble Time twest 0 3 tck avg Write Recovery Time ban 15 ns Internal Write to Read Command Delay twtr Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min 2 The maximum postamble is bound by tHZDQS max Document 06494 Revision A 04 Aug 11 Dataram Corporation 2011 Page 7 IYPDATARAM DTM64332B EN 2GB 240 Pin 2Rx8 Registered ECC LV DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Byte Function Value Hex Number of Bytes Used Number of Bytes in SPD Device CRC Coverage 0 Bit 3 Bit 0 SPD Bytes Used 176 0x92 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 1 SPD Revision Rev 1 1 0x11 DDR3 2 Key Byte DRAM Device Type SORAM IP Key Byte Module Type 3 Bit 3 Bit 0 Module Type RDIMM 0x01 Bit 7 Bit 4 Reserved 0 SDRAM Density and Banks 4 Bit 3 Bit 0 Total SDRAM capacity in megabits 1Gb 0x02 Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved 0 SDRAM Addressing 5 Bit 2 B
16. ument 06494 Revision A 04 Aug 11 Dataram Corporation 2011 Page 4 DY PDATARAM DIN ENT E E TE DTM64332B 2GB 240 Pin 2Rx8 Registered ECC LV DDR3 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High VIH DIFF 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low Vu pr DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage relative to VDD 2 Vix ous eee y Capacitance T 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO Cok 1 5 2 5 pF Input Capacitance Address BA 2 0 A 15 0 RAS CAS WE Ci 1 5 2 5 pF Input Capacitance Control S 1 0 CKE 1 0 ODT 1 0 C 1 5 2 5 pF DQ 63 0 CB 7 0 DQS 8 0 DQS 8 0 Input Output Capacitance DM 8 0 TDQS 17 9 Cio 2 8 5 pF DC Characteristics Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current lit 18 18 yA 1 2 Any input 0 V lt VIN lt VDD Output Leakage Current lot 10 10 yA 2 3 OV lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled Document 06494 Revision A 04 Aug 11 Dataram Corporation 2011 Page 5 erster DTM64332B NE 2GB 240 Pin 2Rx8
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