Dataram DTM63393C memory module
Contents
1. Document 06008 Revision A 01 Oct 10 Dataram Corporation 2010 Page 8 ees 1GB 240 Pin Unbuffered ECC DDR2 DIMM Latency 2 Latency 3 Latency 4 X Latency 5 X Latency 6 TBD DIMM Mechanical Characteristics Max module thickness x lt 4 10 0x01 mm DIMM type information 0x02 Regular RDIMM 133 35mm Regular UDIMM 133 35mm SODIMM 67 6mm Micro DIMM 45 5mm Mini RDIMM 82 0mm Mini UDIMM 82 0mm TBD TBD SDRAM Module Attributes Refer to Byte20 for DIMM type information 0x00 Number of active registers on the DIMM N A for UDIMM 1 Number of PLL on the DIMM N A for UDIMM 0 FET Switch External Enable No TBD Analysis probe installed No TBD SDRAM Device Attributes General 0x02 Includes Weak Driver Supports 50 ohm ODT Supports PASR Partial Array Self Refresh TBD TBD TBD TBD TBD e A aa 27 28 29 30 21 2 29 24 25 GE eg Cycle Time at Reduced CAS Latency CL 0x3D X 4 Gen Data Access Time tAC 1 from Clock at CL X ae Minin Minimum Clock Cycle Time atCL X 2 ns 1 UNUSED e Data Access Time tAC 1 from Clock at CL X 2 UNUSED Ze Row Precharge Time tRP ns 12 5 12 5 125 Minimum Row Active to Row Active Ke tRRD 75 OX1E EE Minimum Active to SECH Time SE ns A 02 D2. Output Capacitance Geer CB 7 0 DQS 8 0 DQSI8 0 CIO 3 4 pF DC Characteristics T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current Command and Address lu 80 80 yA 1 Input Leakage Current S0 CKE0 ODTO lu 40 40 yA 1 Input Leakage Current CK 2 0 CK 2 0 lu 30 30 yA 1 Input Leakage Current DM lu 10 10 yA 1 Output Leakage Current DQS DQ loz 10 10 yA 2 Output Minimum Source DC Current loH 13 4 mA 3 Output Minimum Sink DC Current Jo 13 4 mA 4 Notes 1 These values are guaranteed by design and are tested on a sample basis only 2 DQx and ODT are disabled and 0 V lt Vour S Von 2 Voo 1 7 V Vout 1420 mV Dour Voo lon must be less than 21 Ohms for values of Vout between Von and Vopn 280 mV A Vpp 1 7 V Vout 280 mV Moullo must be less than 21 Ohms for values of Vout between 0 V and 280 mV e a a y y a E a a E Document 06008 Revision A 01 Oct 10 Dataram Corporation 2010 Page 5 D W Optimizing Value and Performance 1GB 240 Pin Unbuffered ECC DDR2 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V Max PARAMETER Symbol Test Condition Value Unit SE One CKE is HIGH CS is HIGH between valid commands Address bus ank Active oe i itching Data bus inputs are switchin 792 ma Precharge Current inputs are switching Data p itching Oparating One lout 0
3. mA BL 4 CL 5 ns AL 0 CKE is HIGH CS is HIGH Bank Active Read oi between valid commands Address bus inputs are switchin 846 mA Precharge Current H 9 Precharge Power Ibn 2P All banks idle CKE is LOW Other control and address bus inputs 117 mA Down Current RD are stable Data bus inputs are floating Precharge Quiet Ibo2Q All banks idle CKE is HIGH CS is HIGH Other control and 513 mA Standby Current PR address bus inputs are stable Data bus inputs are floating Precharge Standby Ion2N All banks idle CKE is HIGH CS is HIGH Other control and 531 e Current BD address bus inputs are switching Data bus inputs are switching S All banks open CKE is LOW Other control and address bus inputs RE lbb3P_ are stable Data bus inputs are floating Fast Power down exit 378 mA Mode Register bit 12 0 a All banks open CKE is LOW Other control and address bus inputs SC Powei Down lbo3P are stable Data bus inputs are floating Slow Power down exit 180 mA urrent 8 f z Mode Register bit 12 1 All banks open tras 70 ms CKE is HIGH CS is HIGH between see Standby Joh valid commands Other control and address bus inputs are 603 mA urrent ieee SE switching Data bus inputs are switching Operating Burst All banks open Continuous burst writes BL 4 CL z 5 tck AL 0 Write Current opd tras 70 ms CKE is HIGH CS is HIGH between valid commands 1413 mA Address bus inputs are switching Data bus inputs are switching Al
4. 2Max 0 105 Max C C 4 00 Min 0 157 Min O SH 1 27 10 lle 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches a gt Page 2 Document 06008 Revision A 01 Oct 10 Dataram Corporation 2010 ees 1GB 240 Pin Unbuffered ECC DDR2 DIMM DOS DAS DQRI7 0 OF 1 0 7 0 DMR1 Q DQSR1 O DQSR1 DQS DOS DQR 15 8 O 1 0 7 0 DQSR2 DQSR2 DMR3 DQSR3 DQSR3 DQS DOS DQR 31 24 OF 1 017 0 DQSR8 DQSR8 DOS DOS CBRI7 0 VO 7 0 22 OHMS CB 7 0 O WA O _CBRI7 0 DQ 63 0 O VWA O DQR 63 0 DQS 8 0 O VW O DQRS 8 0 DQS 8 0 O VVy O O DQRS 8 0 DM 8 0 O VW O DMR 8 0 GLOBAL SDRAM CONNECTS 10 OHMS BA 2 0 O VWA O BA 2 0 R A 13 0 O VWA O A 13 0 R IRAS O A A O RASR ICAS O AA O CASR WE O WA O IWER CKEO m CKEO 22 pF ODTO ODTO 22 pF Document 06008 Revision A 01 Oct 10 Dataram Corporation 2010 DQSR4 DQS DOS DAR 39 32 VO 7 0 DMRS O DQSR5 DQSR5 DQS DOS DQR 47 40 VO 7 0 DMR6 DQSR6 DQSR6 DQS DOS DQR 55 48 V O 7 0 iDAs pas DQR 63 56 VO 7 0 3 x 200 OHMS CKO SDRAM X 3 CKO 3x1 pF 3 x 200 OHMS CKI SDRAM X 3 ICK1 3x1 pF 3 x 200 OHMS ie SDRAM X 3 ICK2 3x1 pF v
5. Bit 0 If 0 DRAM does not support high temperature self 1 operation 9 5 4 0x60 5 5 DRAM Case Temperature Rise from Ambient due to Precharge Power Down DT2P Degree C DRAM Case Temperature Rise from Ambient due to 7 3 0x31 Active Standby DT3N Degree C DRAM Case temperature Rise from Ambient due to Active 4 6 0x5D Power Down with Fast PDN Exit DT3Pfast Degree C 6 DRAM Case temperature Rise from Ambient due to Active 2 Power Down with Slow PDN Exit DT3Pslow Degree C DRAM Case Temperature Rise from Ambient due to Page Open Burst 0x54 Read DT4R4W Mode Bit DT4R DT4R4W Mode Bit Degree C Bit 0 0 if DT4W is greater than DT4R DTAR Bits 1 7 DRAM Case Temperature Rise from Ambient due to Burst 25 0x32 Refresh DT5B Degree C Document 06008 Revision A 01 Oct 10 Dataram Corporation 2010 Page 10 2 0x58 E x On m ES ae 47 ees 1GB 240 Pin Unbuffered ECC DDR2 DIMM DRAM Case Temperature Rise from Ambient due to Bank 27 5 0x37 Interleave Reads with Auto Precharge DT7 Degree CH Thermal Resistance of PLL Package from Top to Ambient UNUSED 0x00 Psi T A PLL C Watt Thermal Resistance of Register Package from Top to UNUSED 0x00 Ambient Psi T A Register C Watt PLL Case Temperature Rise from Ambient due to PLL UNUSED 0x00 Active DT PLL Active Degree C Register Case Temperature Rise from Ambient due to Register 0x00 Active Mode Bit D
6. DECOUPLING DDSPD be Serial PD VDD All Devices VREF All SDRAMs Vss Ss All Devices SCL SERIAL PD SDA SAO SA1 SA2 Page 3 EE Absolute Maximum Ratings 1GB 240 Pin Unbuffered ECC DDR2 DIMM Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TstoRAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperature Operating Tease 0 95 C Voltage on Vpp relative to Vss Vpp 0 5 2 3 V Voltage on Any Pin relative to Vss Vin Vout 0 5 2 3 V Notes Temperature above 85C requires doubling the refresh rate i e 3 9us instead of 7 8us Recommended DC Operating Conditions T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Von 1 7 1 8 1 9 V UO Reference Voltage VREF 0 49 Voo 0 50 Vpp 0 51 Vpp V 1 Bus Termination Voltage Ver Vrer 0 04 VREF Vrer 0 04 V Notes 1 The value of Vor is expected to equal one half Vpp and to track variations in the Vpp DC level Peak to peak noise on Veer may not exceed 1 of its DC value DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Ve Vrer 0 125 Voo 0 300 V Logical Low Logic 0 Vioc 0 300 Vrer 0 125 V AC Input L
7. S 47 VSS 77 NC 107 DQ50 4137 CK1 167 CB6 197 VDD 227 DQ55 VSS Ground 18 NC 48 CB2 78 VDD Hop DQ51 138 CK1 168 CB7 198 VSS 228 VSS VDD Power 19 NC 49 CB3 79 VSS 109 VSS 139 VSS 169 VSS 199 DQ36 229 DQ60 VDDSPD SPD EEPROM Power 20 VSS 50 VSS 80 DQ32 110 DQ56 140 DQ14 170 VDD 200 DQ37 230 DQ61 VREF Reference Voltage 21 DQ10 51 VDD 81 DQ33 111 DQ57 141 DQ15 171 NC 201 VSS 231 VSS NC No Connection 22 DQ11 52 CKEO 82 VSS 112 VSS 142 VSS 172 VDD 202 DM4 232 DM7 23 VSS 53 VDD 83 DQS4 113 DQS7 143 DQ20 173 A15 203 NC 233 NC 24 DQ16 54 BA2 84 DQS4 114 DQS7 1144 DQ21 174 A14 204 VSS 234 VSS 25 DQ17 55 NC 85 VSS 115 VSS 145 VSS 175 VDD 205 DQ38 235 DQ62 26 VSS 56 VDD 86 DQ34 116 DQ58 f146 DM2 176 A12 206 DQ39 236 DQ63 27 IDQS2 57 A11 87 DQ35 117 DQ59 147 NC 177 A9 207 VSS 237 VSS 28 DQS2 58 A7 88 VSS 118 VSS 148 VSS 178 VDD 208 DQ44 238 VDDSPD 29 VSS 59 VDD 89 DQ40 119 SDA 149 DQ22 179 A8 209 DQ45 239 SA0 30 DQ18 60 A5 90 DQ41 120 SCL 150 DQ23 180 A6 210 VSS 240 SA1 Connected but not used Document 06008 Revision A 01 Oct 10 Dataram Corporation 2010 Page 1 D tee 1GB 240 Pin Unbuffered ECC DDR2 DIMM Front view 133 35 i 5 250 SI 10 00 4 00 0 394 3000 IS c Gm Y Lk 17 80 0 700 o o MNNM S 2 54 Min 5 18 e 63 00 55 00 0 100 Min 0 204 lt 2 480 2 165 a 123 00 4 843 Back view Side view BS 2 7
8. T Register Active Mode Bit Bit OI O Unit for Bits 2 7 is 0 75C Bit 1 RFU Default 0 Register Active Bits 2 7 SPO Ravi Checksum for Bytes 0 62 Po xAQ Module Manufacturer s JEDEC ID Code Dataram ID 5 5 5 6 6 6 6 oan Module Part Number J 36 Module Serial Number re J er Module Serial Number J a Module Serial Number To Manufacturer s Specific Data 7 8 9 1 2 3 4 5 2 5 7 Document 06008 Revision A 01 Oct 10 Dataram Corporation 2010 Page 11 mere 1GB 240 Pin Unbuffered ECC DDR2 DIMM PY2DATARAM d BH Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06008 Revision A 01 Oct 10 Dataram Corporation 2010 Page 12
9. ata Input Hold Time After Strobe SC n Document 06008 Revision A 01 Oct 10 Dataram Corporation 2010 Page 9 A 0x00 A DRPDATARAM DTM63393C i tees 1GB 240 Pin Unbuffered ECC DDR2 DIMM Internal write to read command delay tWTR ns Internal read to precharge command delay tRTP ns Extension of Byte 41 tRC and Byte 42 tRFC ns 0x36 Add this value to byte 41 0 5 41 SDRAM Device Minimum Active to Active Auto Refresh 57 5 0x39 Time tRC ns 42 SDRAM Device Minimum Auto Refresh to Active Auto 127 5 Ox7F Refresh Command Period tRFC ns 44 SDRAM Dev DQS DQ Skew for DQS amp DQ signals 0x14 tDQSQ ns ns 46 PLL Relock Time us UNUSED DT4R4W Delta Bits 0 3 0 Tcasemax delta Bits 7 4 10 DRAM Case Temperature Rise from Ambient due to Activate Precharge Ox5F Mode Bits DTO Mode Bits Degree C refresh entry Bit 1 If 0 Do not need double refresh rate for the proper 1 DTO Bits 2 7 6 DRAM Case Temperature Rise from Ambient due to 0x41 Precharge Quiet Standby DT2N DT2Q Degree C Write Recovery Time WR ns 39 Memory Analysis Probe Characteristics UNUSED 0x00 Add this value to byte 42 0 5 43 SDRAM Device Maximum Cycle Time tCK max ns x80 2 45 DDR SDRAM Device Read Data Hold Skew Factor tQHS 3 DRAM maximun Case Temperature Delta Degree C 4 Thermal Resistance of DRAM Package from Top Case to 58 0x74 Ambient Psi T A DRAM C Watt
10. elay tceco 2 tck Clock High Level Width tou 0 45 0 55 tck Clock Cycle Time tck 2 5 ps Clock Low Level Width teL 0 45 0 55 tck Data Input Hold Time after DQS Strobe toH 125 ps DQ Input Pulse Width toipw 0 35 tck DQS Output Access Time from Clock toasck 350 350 ps Write DQS High Level Width toasH 0 35 tox Write DQS Low Level Width toas 0 35 tck DQS Out Edge to Data Out Edge Skew toasa 200 ps Data Input Setup Time Before DQS Strobe tos 50 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tck DQS Falling Edge to Clock Setup Time toss 0 2 tck Clock Half Period tup minimum of tcy or teL ns Address and Command Hold Time after Clock Dn 250 ps Address and Command Setup Time before Clock tis 175 ps Load Mode Command Cycle Time tmRD 2 tck DQ to DQS Hold Lon thp tans Data Hold Skew Factor Lous 300 ps Active to Precharge Time tras 45 70K ns Active to Active Auto Refresh Time tre 57 25 ns RAS to CAS Delay trep 12 5 ns Average Periodic Refresh Interval tREFI 7 8 US Auto Refresh Row Cycle Time force 105 ns Row Precharge Time trp 12 5 ns Read DQS Preamble Time RPRE 0 9 1 1 tck Read DQS Postamble Time trest 0 4 0 6 tck Row Active to Row Active Delay trrp 7 5 ns Internal Read to Precharge Command Delay trtp 7 5 ns Write DQS Preamble Setup Time twPRES 0 35 ps Write DQS Postamble Time twest 0 4 0 6 tck Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR 7 5 ns Exit Self Refresh to No
11. l banks open Continuous burst reads lout 0 mA BL 4 Operating Burst 4R CL 5 tck AL 0 tras 70 ms CKE is HIGH CS is HIGH 1368 mA Read Current pp between valid commands Address bus inputs are switching Data bus inputs are switching Burst Refresh Refresh command at every 75 ns CKE is HIGH CS is HIGH c Ipp5 between valid commands Other control and address bus inputs are 2052 mA urrent te ee switching Data bus inputs are switching Self Refresh loo6 CK and CK at 0 V CKE lt 0 2 V Other control and address bus 44 m Current Be inputs are floating Data bus inputs are floating All bank interleaving reads lout 0 mA BL 4 CL 5 tex ee SC loo AL tRCD IDD 1 x tCK IDD treo 7 5 ns CKE is HIGH CS 2259 ma Current HIGH between valid commands Address bus inputs are stable during deselects Data bus inputs are switching Note For all Jonk measurements tek 2 5 ns tre 57 25 ns tacp 12 5 ns tras 45 ns and trp 12 5 ns unless otherwise specified All currents are based on DRAM absolute maximum values ae gt eZ Document 06008 Revision A 01 Oct 10 Dataram Corporation 2010 Page 6 tte 1GB 240 Pin Unbuffered ECC DDR2 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit DQ Output Access Time from Clock tac 400 400 ps CAS io CAS Command D
12. n Read Command txsnr trec min 10 ns Exit Self Refresh to Read Command txsrp 200 tck Document 06008 Revision A 01 Oct 10 Dataram Corporation 2010 Page 7 ees 1GB 240 Pin Unbuffered ECC DDR2 DIMM SERIAL PRESENCE DETECT Function 1 2 3 4 5 Module Attributes Number of Ranks Package and Height Faction vas SDRAM Number ofRow Addresses o of Ranks Card on Card DRAM Package Module Height SDRAM Cycle time Max Supported CAS Latency CL X tCK ns 10 SDRAM Access from Clock Highest CAS latency tAC ns DIMM configuration type Non parity Parity or ECC Module Data Width 72 7 UNUSED Voltage Interface Level of this assembly SSTL 1 8V Data Parity Data ECC Address Command Parity TBD TBD TBD TBD TBD Refresh Rate Type us Primary SDRAM Width Error Checking SDRAM Width ow 12 14 15 SDRAM Device Attributes Burst Lengths Supported 7 8 SR UNUSED TBD TBD Burst Length 4 Burst Length 8 TBD TBD TBD TBD O 17 SDRAM Device Attributes Number of Banks on SDRAM Device 18 SDRAM Device Attributes CAS Latency TBD TBD Hex x80 x08 0x08 0 0 CH SUE x0A CH CO ojlo oO CH x ES Q O O O x48 0x00 0x05 0x25 0x40 0x02 CH x82 x08 x08 0x00 0x08 0x30
13. ogic Levels Single Ended CT 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin ac Vrer 0 250 V Logical Low Logic 0 Viac Vreer 0 250 V D EECHER TF Document 06008 Revision A 01 Oct 10 Dataram Corporation 2010 Page 4 ees 1GB 240 Pin Unbuffered ECC DDR2 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note DC Input Signal Voltage Vinc 0 300 Vpp 0 300 V 1 DC Differential Input Voltage Ve 0 250 Voo 0 600 V 2 AC Differential Input Voltage Vipac 0 500 Voo 0 600 V 3 AC Differential Cross Point Voltage Vixac 0 50 VoD 0 175 0 50 Vpop 0 175 V 4 Notes 1 Muno specifies the allowable DC excursion of each input of a differential pair 2 Vipo specifies the input differential voltage i e the absolute value of the difference between the two voltages of a differential pair 3 Viac Specifies the input differential voltage required for switching 4 The typical value of Vixiac is expected to be 0 5 Voo and is expected to track variations in Vor Capacitance T 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CK 2 0 CK 2 0 CIN1 3 6 pF Input Capacitance Address BA 2 0 A 13 0 SO RAS CAS ANE CIN2 9 36 pF and Control CKEO ODTO Input
14. ry Tee DTM63393C Ad A Optimizing Value and Performance 1GB 240 Pin Unbuffered ECC DDR2 DIMM Identification DTM63393C 128Mx72 1GB 1Rx8 PC2 6400E 555 12 F0 Performance range Clock Module Speed CL trep trp 400MHZz PC2 6400 5 5 5 333MHz PC2 5300 5 5 5 266MHz PC2 4200 4 4 4 Features Description 240 pin JEDEC compliant DIMM 133 35mm wide by 30mm DTM63393C is an Unbuffered 128Mx72 memory high module which conforms to JEDEC s PC2 6400 Operating Voltage 1 8 V 0 1 standard The DIMM has one Rank comprised of nine 128Mx8 DDR2 Samsung SDRAMs One 2K VO Type SSTL_18 bit EEPROM is used for Serial Presence Detect Data Transfer Rate 6 4 Gigabytes sec Both output driver strength and input termination _ impedance are programmable to maintain signal Data Bursts 4 or 8 bits Sequential or Interleaved ordering integrity on the I O signals The Data Strobe signals may be used either as differential pairs or as single ended strobes with Programmable On Die Termination ODT the DQS signals disabled Data Mask inputs are provided to selectively prevent data from being written to an 8 bit byte Programmable I O driver strength OCD Programmable CAS Latency 4 or 5 Differential Redundant Data Strobe signals Alternatively these may be used as Redundant Data Strobes for use in systems with a mix of x4 SDRAM Addressing Row Col Bank 14 10 3 and x8 DRAMs Fully ROHS Complian
15. t Pin Configuration Pin Description Front Side Back Side Name Function 1 VREF 31 DQ19 61 A4 91 VSS 121 VSS 151 VSS 181 VDD 211 DM5 CB 7 0 Data Check Bits 2 VSS 32 VSS 62 VDD 92 DQS5 122 DQ4 152 DQ28 182 A3 212 NC DQ 63 0 Data Bits 3 DQO 33 DQ24 63 A2 93 DQS5 123 DQ5 153 DQ29 183 A1 213 VSS DQS 8 0 DQS 8 0 Differential Data Strobes 4 DQ1 34 DQ25 64 VDD 94 VSS 124 VSS 154 VSS 184 VDD 214 DQ46 DM 8 0 Data Mask 5 VSS 35 VSS 65 VSS 95 DQ42 125 DMO 155 DM3 185 CKO 215 DQ47 CK 2 0 CK 2 0 Differential Clock Inputs 6 DQSO 36 DQS3 66 VSS op DQ43 126 NC 156 NC 186 CKO 216 VSS CKEO Clock Enables 7 DQSO 37 DQS3 67 VDD 97 VSS 127 VSS 157 VSS 187 VDD 217 DQ52 ICAS Column Address Strobe 8 VSS 38 VSS 68 NC 98 DQ48 128 DQ6 158 DQ30 188 AO 218 DQ53 RAS Row Address Strobe 9 DQ2 39 DQ26 69 VDD 99 DQ49 129 DQ7 159 DQ31 189 VDD 219 VSS ISO Chip Selects 10 DQ3 40 DQ27 70 A10 100 VSS 130 VSS 160 VSS 190 BA1 220 CK2 IWE Write Enable 11 VSS 41 VSS 71 BAO 101 SA2 131 DQ12 161 CB4 191 VDD 221 CK2 A 15 0 Address Inputs 12 DQ8 42 CBO 72 VDD 102 NC 132 DQ13 162 CB5 192 RAS 222 VSS BA 2 0 Bank Addresses 13 DQ9 43 CB1 73 ANE 103 VSS 133 VSS 163 VSS 193 SO 223 DM6 ODTO On Die Termination Inputs 14 VSS 44 VSS 74 ICAS 104 DQS6 134 DM1 164 DM8 194 VDD 224 NC SA 2 0 SPD Address 15 DQS1 45 DQS8 75 VDD op DQS6 135 NC 165 NC 195 ODTO 225 VSS SCL SPD Clock Input 16 DQS1 46 DQS8 76 NC 106 VSS 136 VSS 166 VSS 196 A13 226 DQ54 SDA SPD Data Input Output 17 VS
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