Dataram DTM63389B memory module
Contents
1. Features 240 pin DIMM 133 35 mm wide by 30 mm high DTM63389B DA ARAM 512MB 240 Pin Unbuffered ECC DDR2 DIMM Operating Voltage 1 8 V 0 1 Type SSTL 18 Data Transfer Rate 5 3 Gigabytes sec Data Bursts 4 or 8 bits Sequential or Interleaved ordering Programmable I O driver strength OCD Programmable On Die Termination ODT Programmable CAS Latency 3 4 or 5 Differential Redundant Data Strobe signals SDRAM Addressing Row Col Bank 13 10 3 Fully ROHS Compliant Pin Configuration Identification DTM63389B 64Mx72 512MB 1Rx16 DDR2 667E 555 Performance range Clock Module Speed CL tncp trp 333MHz DDR2 667 5 5 5 267MHz DDR2 533 4 4 4 200MHz DDR2 400 3 3 3 Description DTM63389B is an Unbuffered 64Mx72 memory module The DIMM has one Rank comprised of five 64Mx16 DDR2 Hynix SDRAMs One 2K bit EEPROM is used for Serial Presence Detect Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals The assembly is a Dual In line Memory Module intended for mounting into 240 pin edge connector sockets Pin Description Front Side Back Side Name Function 1 VREF 31DQ19 61 91 vss 21 vss 151 vss 181 VDD 211 DM5 7 0 Data Check Bits 2 VSS 32 vss 62 VDD 92 DQS5 122 004 520028 182 212 NC DQ 63 0 Data Bits 33DQ24 63 2 09585 122. UNUSED 40 Extension of Byte 41 tRC and Byte 42 tRFC ns 0x06 Add this value to byte 41 Add this value to byte 42 0 5 ii Minimum Active to Active Auto Refresh Time pese B s 42 SDRAM Device Minimum Auto Refresh to Active Auto 127 5 Ox7F Refresh Command Period tRFC ns 43 SDRAM Device Maximum Cycle Time tCK max 8 0 80 44 TA Dev DQS DQ Skew for DQS amp DQ JN SN DDR SDRAM Device Read Data Hold Skew Factor tQHS 0x22 6 8 Relock Time us UNUSED 0x00 x03 47 DRAM maximun Case Temperature Delta Degree 0 DT4R4W Delta Bits 0 3 1 2 Tcasemax delta Bits 7 4 0 48 Thermal Resistance of DRAM Package from Top Case to 0x74 Ambient Psi T A DRAM C Watt 9 Case Temperature Rise from Ambient due to Activate Precharge Mode Bits DTO Mode Bits Degree Bit 0 If 0 DRAM does not support high temperature self 1 refresh entry Bit 1 If 0 Do not need double refresh rate for the proper operation Bits 2 7 50 DRAM Case Temperature Rise from Ambient due to Ox3C Precharge Quiet Standby DT2N DT2Q Degree C 51 DRAM Case Temperature Rise from Ambient due to 1 44 0x60 Precharge Power Down DT2P Degree C 52 DRAM Case Temperature Rise from Ambient due to Active Ox2bE Standby DT3N Degree C 53 DRAM Case temperature Rise from Ambient due to Active 0x58 Power Down with Fast PDN Exit DT3Pfast Degree C 54 DRAM Case temperature Rise f
3. a E Ohms SOhms Ohms 15 8 3 x 200 OHMS CBRI7 0 7 0 ANN E i 7 CD SDRAM X 1 22 Ohms CKO 1x1 pF IT 22 Ohms 2 2 2 pF 7 0 O A O CBR 7 0 Sc SERIAL PD SDA 3 x 200 OHMS DQ 63 0 O O 63 0 ANN 005 8 0 O O DOSR 8 0 SA0 SA1 SA2 his SDRAM X 2 i gt 1095 8 0 O O DQSR 8 0 4 4 DM 8 0 O VW O DMR 8 0 2x1 pF 2 2pF GLOBAL SDRAM CONNECTS 3 x 200 OHMS WN 10 Ohms CKEO zx CKEO ck2 0 O AA O BA 2 0 R 3x15 pF SDRAM X2 12 0 O A AA O A 12 0 R pr c O A O T 4 IRAS IRASR ODTO ODTO 2x1pF ICAS O A ANA O 22 1 5 O N O FE 2 2 pF a Document 06514 Revision A 13 Mar 2009 Dataram Corporation 2009 Page 3 63389 512MB 240 Unbuffered ECC DDR2 DIMM DATARAM Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TsroRAGE 55 100 C Ambient Temperature Operating TA 0 70 C DRAM Case Temperature Operating TcasE 0 95 C Voltage on Vpp relative to Vss 0 5 2 3 V Voltage on Any Pin relative to Vss Vin Vout 0 5 2 3 V Notes Temperature above 85C requires doubling the refresh rate i e 3 9us instead o
4. 150 mA Standby Current PR address bus inputs are stable Data bus inputs are floating Precharge Standby Ion2N All banks idle CKE is HIGH CS is HIGH Other control and 200 mA Current BD address bus inputs are switching Data bus inputs are switching All banks open is LOW Other control and address bus inputs ala Down lpp3P are stable Data bus inputs are floating Fast Power down exit 125 mA ode Register bi Mode Register bit 12 0 Active Power Down All banks open CKE is LOW Other control and address bus inputs Current Ipp3P are stable Data bus inputs are floating Slow Power down exit 60 mA Mode Register bit 12 1 All banks open tras 70 ms is HIGH CS is HIGH between a Ipp3N valid commands Other control and address bus inputs are 250 mA switching Data bus inputs are switching Operating Burst All banks open Continuous burst writes BL 4 CL 5 tcx AL 0 Wie Ipp4W tras 70 ms is HIGH CS is HIGH between valid commands 975 mA Address bus inputs are switching Data bus inputs are switching All banks open Continuous burst reads lout 0 mA BL 4 Operating Burst 4R CL 5 tck AL 0 tras 70 ms is HIGH CS is HIGH 975 mA Read Current pp between valid commands Address bus inputs are switching Data bus inputs are switching Burst Refresh Refresh command at every 75 ns CKE is HIGH CS is HIGH Current 1555 between valid commands Other control and address bus inputs
5. 875 mA switching Data bus inputs are switching Self Refresh loo6 CK and CK at 0 V lt 0 2 V Other control and address bus 50 mA Current BH inputs are floating Data bus inputs are floating All bank interleaving reads lout 0 mA BL 4 CL 5 tex Operating Bank d ADI interleave Read 17 AL tRCD IDD 1 x tCK IDD tarp 7 5 ns is HIGH CS is 1325 mA Current Notes For all measurements 3 ns tac 60 ns trco 15 ns tras 45 ns and trp 15 ns unless otherwise specified HIGH between valid commands Address bus inputs are stable during deselects Data bus inputs are switching All currents are based on absolute maximum values Document 06514 Revision A 13 Mar 2009 Dataram Corporation 2009 Page 6 63389 DATARAM 512MB 240 Pin Unbuffered ECC DDR2 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit DQ Output Access Time from Clock tac 450 450 ps CAS to CAS Command Delay tccp 2 tck Clock High Level Width 0 48 0 52 Clock Cycle Time 3000 8000 5 Clock Low Level Width teL 0 48 0 52 Data Input Hold Time after DQS Strobe 175 DQ Input Pulse Width tpipw 0 35 tck DQS Output Access Time from Clock tpasck 400 400 ps Write DQS High Level Width toasH 0 35 Write DQS Low Level Width 0 3
6. 3 005 153 DQ29 183 A1 213 VSS DQS 8 0 DOS B 0 Differential Data Strobes 4 34 2025 64vDD 94 vss 24 55 t54vss 184 VDD 214 0046 DM 8 0 Data Mask 5 VSS 35 VSS 65 vss 05 0042 125 pomo 155 DM3 185 215 0047 CK 2 0 CK 2 0 Differential Clock Inputs 6 DQSO 136 DQS3 66 vss 0043 126 NC 156 NC 186 CKO 216 VSS CKEO Clock Enables DQs0 37DQs3 67 vss 127 vss 157 vss 187 VDD 217 0052 ICAS Column Address Strobe 8 VSS 38 VSS 68 NC 0048 128 Doe 58 188 AO 218 DQ53 IRAS Row Address Strobe 9 DQ2 390026 69 VDD 99 0049 129 159 DQ31 189 VDD 219 vss 180 Chip Selects 10 70A10 100 vss 3 160 vss 190 220 2 Write Enable 11VSS vss 71 101 131 0012 161 191 VDD 221 ck2 15 0 Address Inputs 12DQ8 42 72 VDD 102 NC 132 2013 162 CB5 192 RAS 222 VSS BA 2 0 Bank Addresses 13 DQ9 CB1 73 103 vss 133 vss 163 vss 193 50 223 DM6 ODTO On Die Termination Inputs 14 VSS M4 vss 74 104 56 134 164 DM8 194 VDD 224 NC SA 2 0 SPD Address 15 DQs1 45 DQs8 75 VDD 105 pase 135 NC 165 NC 195 ODTO 225 VSS SCL SPD Clock Input 160051 46 pasas 76 NC 106 vss i136 vss 166 vss 196 A13 226 00954 SDA SPD Data Input Output 17 vss 47 VSS 77 NC 107 0050 137 167 CB6 197 VDD 227 DQ55 vss Ground 18 NC 48 CB2 78 VDD 108 DQ51 138 CK1 468 198 VSS 228 VSS VDD Power 19 NC
7. 49 CB3 79 vss 109 vss 139 vss 169 vss 99 DQ36 229 VDDSPD SPD EEPROM Power 20VSS 50 VSS DQ32 110 2056 140 DQ14 VDD DQ37 230 0061 VREF Reference Voltage 21 DQ10 51 VDD DQ33 111 0057 141 0015 171 NC 201 vss 231 VSS NC No Connection 220011 52ckEo 82 vss 112 vss 142 vss 172 VDD 202 232 DM7 23 VSS 53 VDD 83 0954 113 DQS7 143 2020 173 A15 203 NC 233 NC 24 0016 54 84 0054 114 Das7 144 0021 174 A14 204 vss 234 vss 25 0017 55 NC 85 VSS 115 vss 145 vss 175 VDD 205 235 0962 26 VSS 56 VDD 86 116 0058 146 DM2 176 A12 206 DQ39 236 DQ63 27 10052 57 11 87 DQ35 117 2059 147 NC 177 A9 207 vss 237 VSS 28 0052 58 A7 88 vss 118 vss 148 vss 178 VDD 208 DQ44 238 VDDSPD 29 VSS 59 VDD 89 DQ40 119 SDA 149 2022 179 A8 209 0045 239 SAO 30 2018 60 A5 90 DQ41 120 SCL 150 00923 180 210 VSS 240 SA1 Connected but not used Document 06514 Revision A 13 Mar 2009 Dataram Corporation 2009 Page 1 63389 DATARAM 512MB 240 Pin Unbuffered ECC DDR2 DIMM Front view 133 35 gt 5 250 10 00 0 394 30 00 1 181 17 80 0 700 5 18 63 00 55 00 0 100 Min 0 204 2 480 2 165 123 00 4 843 Back view Side view NT 2 72Max 0 105 Max C C 4 00 Min 0 157 Min m 1 27 10 ES 0 0500 30 0040 Notes Tol
8. 5 DQS Out Edge to Data Out Edge Skew toasa 240 ps Data Input Setup Time Before DQS Strobe tos 100 ps DQS Falling Edge from Clock Hold Time tosH 0 2 00 Falling Edge to Clock Setup Time toss 0 2 Clock Half Period tup minimum of tc or tci ns Address and Command Hold Time after Clock tin 275 ps Address and Command Setup Time before Clock tis 200 ps Load Mode Command Cycle Time tMRD 2 tck DQ to DQS Hold ton tup tans Data Hold Skew Factor tous 340 ps Active to Precharge Time tras 45 70K ns Active to Active Auto Refresh Time tre 60 ns RAS to CAS Delay trop 15 ns Average Periodic Refresh Interval 7 8 Us Auto Refresh Row Cycle Time 127 5 ns Row Precharge Time trp 15 ns Read DQS Preamble Time tRPRE 0 9 1 1 tck Read DQS Postamble Time trest 0 4 0 6 Row Active to Row Active Delay 7 5 ns Internal Read to Precharge Command Delay 7 5 ns Write DQS Preamble Time twPRE 0 35 ps Write DQS Postamble Time twest 0 4 0 6 Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR 7 5 ns Exit Self Refresh to Non Read Command txsnr trec min 10 ns Exit Self Refresh to Read Command 200 Document 06514 Revision A 13 Mar 2009 Dataram Corporation 2009 Page 7 63389 DATARAM 512MB 240 Pin Unbuffered ECC DDR2 DIMM SERIAL PRESENCE DETECT MATRIX ober of Bes Ule by Module
9. IMM 82 0mm TBD TBD 22 24 25 Number of PLL on the DIMM N A for UDIMM FET Switch External Enable TBD Analysis probe installed TBD SDRAM Device Attributes General 0x03 Includes Weak Driver Supports 50 ohm ODT Supports PASR Partial Array Self Refresh TBD TBD TBD TBD TBD 25 Clock Cycle TimeatCL X 2 ns SDRAM Module Attributes Refer to Byte20 for DIMM type information 0x00 Number of active registers on the DIMM N A for UDIMM T Clock Cycle Time at Reduced CAS Latency CL X _ Hain Data Access Time tAC from Clock at CL X 1 45 MATT Clock Cycle Time at CL X 2 n Minimum Clock Cycle Time atCL X 2 ns Data Access Time tAC from Clock at CL X 2 0 4 a7 minima Row Precharge Time tRP ns 28 Minimum Row Active to Row Active Delay tRRD 29 Minimum RAS to CAS Delay tRCD ns 30 Minimum Active to Precharge Time tRAS ns 34 Data Input Setup Time Before strobe DS 0 5 36 Write Recovery Time tWR ns Document 06514 Revision A 13 Mar 2009 Dataram Corporation 2009 Page 9 63389 DATARAM 512MB 240 Pin Unbuffered ECC DDR2 DIMM Internal write to read command delay tWTR ns Internal read to precharge command delay tRTP ns Memory Analysis Probe Characteristics
10. Vier 000 Number of Column Addresses 5 Module Attributes Number of Ranks Package and Height 0x60 of Ranks 1 Card on Card No DRAM Package Planar Module Height 30mm 8 Module Data Wath oa UNUSED 0x00 Voltage Interface Level of this assembly SSTL 1 8V 72 SDRAM Cycle time Max Supported CAS Latency CL X tCK ns 45 10 SDRAM Access from Clock Highest CAS latency ns DIMM configuration type Non parity Parity or ECC Data Parity Data ECC Address Command Parity TBD TBD TBD TBD TBD 12 Refresh Rate Type us 7 8 SR Primary SDRAM Width 14 Error Checking SDRAM Width UNUSED SDRAM Device Attributes Burst Lengths Supported TBD TBD Burst Length 4 Burst Length 8 TBD TBD TBD TBD 17 SDRAM Device Attributes Number of Banks on SDRAM 0x08 Device 18 SDRAM Device Attributes CAS Latency 0x38 TBD TBD Latency 2 Document 06514 Revision A 13 Mar 2009 Dataram Corporation 2009 Page 8 DTM63389B DATARAM 512MB 240 Pin Unbuffered ECC DDR2 DIMM Latency 3 X Latency 4 X Latency 5 X Latency 6 TBD DIMM Mechanical Characteristics Max module thickness x lt 4 10 0x01 mm 20 DIMM type information 0x02 Regular RDIMM 133 35mm Regular UDIMM 133 35mm SODIMM 67 6mm Micro DIMM 45 5mm Mini RDIMM 82 0mm Mini UD
11. c 0 500 Vpp 0 600 V 3 AC Differential Cross Point Voltage Vix AC 0 50 Vpp 0 175 0 50 Vpp 0 175 V 4 Notes 1 specifies the allowable DC excursion of each input of a differential pair 2 specifies the input differential voltage i e the absolute value of the difference between the two voltages of a differential pair 3 Viac Specifies the input differential voltage required for switching 4 The typical value of Vixac is expected to be 0 5 Voo and is expected to track variations Capacitance T4 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CK 2 0 CK 2 0 CIN1 6 2 8 2 pF Input Capacitance Address and Control BA 2 0 A 13 0 RAS CAS WE CIN2 5 0 10 0 pF Input Capacitance Control CKEO ODTO SO CIN3 31 5 36 5 pF Input Output Capacitance aie or 7 0 8 0 DQSI8 0 CIO 2 5 3 5 pF DC Characteristics 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current Command and Address lu 10 10 pA 1 Input Leakage Current CKO CKO lu 2 2 1 Input Leakage Current CK 1 0 CK 1 0 lu 4 4 1 Input Leakage Current DM lu 2 2 1 Output Leakage Current DQS DQ loz 2 2 2 Output Minimum Source DC Current 13 4 3 Output Minimum Sink DC Current lo 13 4 mA 4 Notes 1 These values are g
12. erances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches Document 06514 Revision A 13 Mar 2009 Dataram Corporation 2009 Page 2 63389 DATARAM 512MB 240 Pin Unbuffered ECC DDR2 DIMM 130 DQSRO o IDQSR4 o DQSRO DASR QO DQSR1 20 85 O DQSR1 5 O DMR4 DMR1 0 4 DMR5 0 4 886888388 amp 268888 2588858 338498 DQR 15 8 O J UIO 15 8 DQRI47 40 o UNO 15 8 DQR 7 0 o 7 0 DQR 39 32 O LIO 7 0 IDQSR2 o IDQSR6 o DASR DASR 9 DQSR3 9 DQSR7 9B 4 1 5 pF DASR E DQSR7 zi DMR DMR6 0 4 DMR3 0 4 DMR7 0 8888889 882888889 27888 8 DQR 31 24 O UNO 15 8 DQR 63 56 O J uro 15 8 DQR 23 16 O LI O 7 0 DQR 55 48 Lo 7 0 129358 o DECOUPLING DQSR8 Serial PD All Devices VREF T All SDRAMs Vss T All Devices DMR gt 20072700 888888 9 22 22 22
13. f 7 8us Recommended DC Operating Conditions T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Vpp 1 7 1 8 1 9 V Reference Voltage VREF 0 49 Vpp 0 50 Vpp 0 51 Vpp V 1 Bus Termination Voltage Vit Vrer 0 04 VREF Vrer 0 04 V Notes 1 The value of Vrer is expected to equal one half Vpp and to track variations in the Vpp DC level Peak to peak noise on Veer may not exceed 196 of its DC value DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vrer 0 125 Vpp 0 300 V Logical Low Logic 0 0 300 Vrer 0 125 V AC Input Logic Levels Single Ended 0 to 70 C Voltage referenced to 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 ViH AC Vrer 0 250 V Logical Low Logic 0 Vreer 0 250 V Document 06514 Revision A 13 Mar 2009 Dataram Corporation 2009 Page 4 63389 DATARAM 512MB 240 Pin Unbuffered ECC DDR2 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Note DC Input Signal Voltage 0 300 Vpp 0 300 V 1 DC Differential Input Voltage 0 250 Vpp 0 600 V 2 AC Differential Input Voltage Vina
14. n A 13 Mar 2009 Dataram Corporation 2009 Page 11 63389 DATARAM 512MB 240 Pin Unbuffered ECC DDR2 DIMM DATARAM DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06514 Revision A 13 Mar 2009 Dataram Corporation 2009 Page 12
15. rom Ambient due to Active 2 2 0x58 Power Down with Slow PDN Exit DT3Pslow Degree C 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read DT4R4W Mode Bit DT4R DT4R4W Mode Bit Degree C Bit 0 if DTAW is greater than Bits 1 7 56 DRAM Case Temperature Rise from Ambient due to Burst 24 5 0x31 Refresh DT5B Degree C Document 06514 Revision A 13 Mar 2009 Dataram Corporation 2009 Page 10 63389 DATARAM 512MB 240 Pin Unbuffered ECC DDR2 DIMM 57 DRAM Case Temperature Rise from Ambient due to Bank 33 5 0x43 Interleave Reads with Auto Precharge DT7 Degree C 58 Thermal Resistance of PLL Package from Top to Ambient UNUSED 0x00 Psi PLL C Watt 59 Thermal Resistance of Register Package from Top to Ambient UNUSED 0x00 Psi T A Register C Watt PLL Case Temperature Rise from Ambient due to PLL Active UNUSED 0x00 DT PLL Active Degree C DT Register Active Mode Bit Bit O If O Unit for Bits 2 7 is 0 75C Bit 1 RFU Default 0 Register Active Bits 2 7 Sz pe Ravan 63 Checksum for Bytes 0 62 Po 64 Module Manufacturer s JEDEC ID Code Dataram ID 65 Manufacturer s JEDEC ID Code Dataram ID 66 71 Module Manufacturer s ID Code UNUSED 0x0 73 50 0 0 5 98 x E sed Specific Data UNUSED 0x00 127 Document 06514 Revisio
16. uaranteed by design and are tested on a sample basis only 2 DQx and ODT are disabled and 0 V lt Vout lt 3 Voo 1 7 V 1420 mV Vpp lou must be less than 21 Ohms for values of Vout between Von and Vpp 280 mV 4 Vpp 1 7 V 280 mV Vourt lo must be less than 21 Ohms for values of Vour between 0 V and 280 mV EN T APSPIS ROC H C UNCK LU UR Document 06514 Revision A 13 Mar 2009 Dataram Corporation 2009 Page 5 DATARAM DTM63389B 512MB 240 Pin Unbuffered ECC DDR2 DIMM lbo Specifications and Conditions T4 0 to 70 C Voltage referenced to Vss 0 V we Max d PARAMETER Symbol Test Condition Value Unit is HIGH CS is HIGH between valid commands Address bus ank Active 1550 input itching Data bus input itchi 450 mA Precharge Current inputs are switching Data bus inputs are switching lour 0 mA BL 4 CL 5 ns AL 0 is HIGH CS is HIGH ank Active Read 1551 bet lid ds Add bus input itchi 575 mA Precharge Current etween valid commands ress bus inputs are switching Precharge Power Ion2P All banks idle CKE is LOW Other control and address bus inputs 50 mA Down Current RD are stable Data bus inputs are floating Precharge Quiet 10929 All banks idle is HIGH CS is HIGH Other control and
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