Dataram 4 GB, 240-Pin
Contents
1. 1680 IRS1 DQSOR DQS9R DQSOR 100598 120 DAS CS DM DQS 00 CS DM DQS DQS CS DM 120 DQS CS DM DOR 3 0 VO 3 0 1 4 1 0 3 0 DQRI 7 4 O V O 3 0 L 03 0 DQS4R DQS10R o DQS1R DQS10R O 1005 DQS CS DM 120 DQS CS DM 129 DQS CS DM 1290 DQS CS DM DQR 11 8 VO 3 0 VO 3 0 DQR 15 12 O 1 0 3 0 VO 3 0 DQS2R O DQS11R e DQS2R DQS11R 1005 00 CS DM DQS DAS CS DM 120 DAS CS DM DQS 005 CS DM DQR 19 16 VO 3 0 I vora o DQR 23 20 1 013 0 L 03 0 DQS3R O DQS12R O DQS3R 1005126 DQS DQS CS DM 120 DAS CS DM DQS DQS CS DM 120 DQS CS DM DQR 27 24 VO 3 0 E 3 A vora o DQR 31 28 O 1 0 3 0 0 0 DQS4R DQS13R DQS4R DQS13R O DQS DAS CS DM 120 DAS CS DM 1 DAS CS DM DQS DQS CS DM DQR 35 32 VO 3 0 VO 3 0 DQR 39 36 3 0 VO 3 0 DQS5R O DQS14R O DQS5R2. TBD TBD 17 SDRAM Device Attributes Number of Banks on SDRAM Device 8 08 SDRAM Device Attributes CAS Latency 38 TBD TBD Latency 2 18 Latency 3 X Latency 4 X Latency 5 X Latency 6 TBD 19 DIMM Mechanical Characteristics Max module thickness mm lt 4 10 01 DIMM type information 01 Regular RDIMM 133 35mm Regular UDIMM 133 35mm SODIMM 67 6mm js 20 Micro DIMM 45 5mm Mini RDIMM 82 0mm Mini UDIMM 82 0mm TBD TBD SDRAM Module Attributes Refer to Byte20 for DIMM type information Number of active registers on the DIMM N A for UDIMM Number of PLLs on the DIMM N A for UDIMM FET Switch External Enable TBD Analysis probe installed TBD SDRAM Device Attributes General Includes Weak Driver Supports 50 ohm ODT Supports PASR Partial Array Self Refresh TBD TBD TBD TBD TBD Minimum Clock Cycle Time at Reduced CAS Latency CL X 1 ns 24 Maximum Data Access Time tAC from Clock at CL X 1 ns 0 50 50 p Rc n Document 06519 Revision A 20 Mar 09 Dataram Corporation 2009 Page 9 DTM63356G DATARAM 4 GB 240 Registered DDR2 DIMM ECC with CMD ADD Parity 25 Minimum Clock Cycle Time at CL X 2 ns 0 50 50 26 Maximu
3. Pin Configuration Pin Description Front Side Back Side Function 1 VREF 31 0019 61A4 91 GND 121 151 181 VDD 211 09814 ICAS Column Address Strobe 2 GND 12GND 62 92 DQS5 22 004 152 0028 182 212 DQS14 Err_Out Parity Error Found 33DQ24 63 2 Dass 23 005 153 DQ29 183 A1 213 GND IRAS Row Address Strobe 4 pat 34 2025 64 94 GND 124 154 184 VDD 0214 0046 Register and PLL Reset 5 GND 15 GND 65GND 95 0042 125 base 155 00812 485 cko 215 0047 IS 1 0 Chip Selects 6 DQs0 36 DQs3 66 96 DQ43 126 Daso 156 DQS12 486 CKO 216 GND Write Enable 7 paso 37DQs3 67 7 GND 127 157 GND 187 VDD 217 0052 A 15 0 Address Inputs 8 GND 38 GND 98 0048 28 Dae 158 DQ30 188 AO 218 DQ53 BA 2 0 Bank Addresses 9 DQ2 39DQ26 99 po49 129 Da7 159 DQ31 189 VDD 219 GND CB 7 0 Data Check Bits 10 40 70 A10 100 GND 130 190 220 NC CKO CKO Differential Clock Inputs 11 GND 41GND 71BAO 101 131 0012 161 191 VDD 221 NC CKE 1 0 Clock Enables 12DQ8 42 CBO 72 VDD 102 NC 132 DQ13 162 5 192 222 GND DQ 63 0 Data Bits 13 DQ9 CB1 73 103 GND 133 163 GND 193 0 223 DQS15 DQS 17 0 DQS 17 0 Differential Data Strobes 14 44GND_ 74 CAS 104 DQS6 134 00510 164 DQS17 194 VDD 224 DQS15 GND
4. 1005146 129 005 CS DM 1005 DQS CS DM 7DQS DQS CS DM 129 005 CS DM DQR 43 40 VO 3 0 VO 3 0 DQR 47 44 O 1 013 0 VO 3 0 DQS6R DQS15R DQS6R 1005158 O 1005 005 CS DM 120 DAS CS DM 120 DAS CS DM 120 DAS CS DM DQR 51 48 VO 3 0 VO 3 0 DQR 55 52 1 013 0 VO 3 0 DQS7R DQS416R DQS7R DQS16R DQS DAS CS DM 120 DQS CS DM 1005 DQS CS DM DQR 59 56 VO 3 0 VO 3 0 DQR 63 60 O O 3 0 VO 3 0 DQS8R O 005176 o DQS8R DQS17R 129 DAS CS DM 120 DQS CS DM 120 DAS CS DM 120 DAS CS DM CBR 3 0 VO 3 0 VO 3 0 CBR 7 4 O 1 013 0 VO 3 0 REGISTERS 30 A RSO 18 SDRAMs Notes DECOUPLING 81 AN IRS1 18 SDRAMs 1 Unless otherwise noted resistor values 22 Ohms 5 Vppspp Serial PD 2 A v RBAO RBA2 All SDRAMs V A0 A15 AAA RAO RA13 All SDRAMs DQ 63 0 O VW O__DQRI63 0 V e n IRAS IRRAS SDRAMs cab Ver 0 O A O ICAS WW IRCAS All SDRAMs 7 0 BRIZI ss All SDRAMs CKEO Av RCKEO 18 SDRAMs DQS 17 O A O DQSR 17 0 CKE1 RCKE1 18 SDRAMs IDQS 17 0 O A O DQSR 17 0 AAN L RWE All SDRAMs AN RODTO 18 SDRAMs PCKO PCK6 PCK8 PCK9 to SDRAMS ODT1 AN RODT1 18 SDRAMs RESET RST L ICKO PCKO PCK6 PCK8 PCK9 to SDRAMS PCK7 L PCK7 _ PCK7 toRegisters PCK7 to Registers Ka
5. DTM63356G DA 4 GB 240 Pin Registered DDR2 DIMM ECC with CMD ADD Parity Identification DTM63356G 512Mx72 Performance Range Clock Module Speed CL tncp 333 MHz DDR2 667 5 5 5 267 MHz DDR2 533 4 4 4 200 MHz DDR2 400 3 3 3 Description DTM63356G is a Registered 512Mx72 memory module which conforms to JEDEC s DDR2 PC2 5300 standard The assembly is comprised of two Ranks of 36 CMOS 256Mx4 DDR2 Hynix Synchronous DRAMs two Registers one Phase Locked Loop PLL and one 2K bit EEPROM used for Serial Presence Detect Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals Error Checking and Correction bits are provided to ensure data integrity The module supports Intel SDDC and Chipkill advanced ECC features The Data Strobe signals may be used either as differential pairs or as single ended strobes with the DQS signals disabled Features 240 pin JEDEC compliant DIMM Operating Voltage 1 8 V 0 1 Type SSTL 18 Data Transfer Rate 5 3 Gigabytes sec Data Bursts 4 or 8 bits Sequential or Interleaved ordering Error Checking and Correction ECC bits Programmable driver strength OCD Programmable On Die Termination ODT Programmable CAS Latency 3 4 or 5 Differential Single Ended Data Strobe signals SDRAM Addressing Row Col Bank 14 11 3 Fully RoHS Compliant
6. 1 Signals for Address and Command Parity Function Vss VDD Err_Out PAR In PAR IN QERR Err Out SCL SERIAL PD SDA WP i i SA0 1 SA2 i i Document 06519 Revision A 20 Mar 09 Dataram Corporation 2009 Page 3 DTM63356G DATARAM 4 GB 240 Pin Registered DDR2 DIMM ECC with CMD ADD Parity Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TsroRAGE 55 100 C DRAM Case Temperature Operating TcasE 0 95 C Voltage on Vpp relative to Vss 0 5 2 3 V Voltage on Any Pin relative to Vss Vin Vout 0 5 2 3 V Recommended DC Operating Conditions Voltages referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Vpp 1 7 1 8 1 9 V Reference Voltage VREF 0 49 Vpp 0 50 Vpp 0 51 Vpp V 1 Bus Termination Voltage Vir Vrer 0 04 VREF Vrer 0 04 V Notes 1 The value of Vrer is expected to equal one half Vpp and to track variations in the Voo DC level Peak to peak noise on Vrer not exceed 1 of its DC value DC Input Logic Levels Single Ended Voltages referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vrer 0 125 Vpp 0 300 V Logical Low Logic 0 0 300 Vrer
7. Ground 15 DQS1 45 Das8 75 VDD 105 pase 135 DQS10 165 DQS17 195 225 GND NC No Connection 160051 46 pasa 76 s 106 GND 136 166 196 A13 226 0954 ODT 1 0 On Die Termination Inputs 17 ODT1 107 0950 137 NC 167 CB6 197 VDD 227 0055 Par In Parity Bit Address amp Control 18 RESET 48 CB2 78 VDD 108 0051 138 NC 168 198 GND 228 GND SA 2 0 SPD Address 19 NC 49 CB3 109 GND 1439 169 199 229 SCL SPD Clock Input 20 GND 50GND 0932 110 Dose 140 0014 170 VDD 200 DQ37 230 DQ61 SDA SPD Data Input Output 21 DQ10 51 VDD 81 DQ33 111 0057 141 0015 171 CKE1 201 GND 231 GND VDD Power 22 DQ11 52 82 GND 112 GND 142 172 VDD 202 DQS13 232 00516 VDDSPD SPD EEPROM Power 23 GND 53 VDD DQS4 113 DQS7 143 2020 173 15 203 DQS13 233 DQS16 VREF Reference Voltage 24 DQ16 54 84 4 114 0057 144 0021 174 14 204 GND 234 GND 25 0017 55 Er 85 GND 115 GND 145 175 VDD 205 DQ38 235 0062 26 GND 56 VDD 86 116 2058 146 DAS11 176 A12 206 2939 236 0063 27 10052 57 11 87 DQ35 117 2059 147 DQS11 177 A9 207 GND 237 GND 28 0052 58 A7 88 GND 118 GND 148 178 VDD 208 0044 238 VDDSPD 29 GND 59 VDD 89 2040 119 sDA 149 2022 179 A8 209 2045 239 SAO 30 2018 60 A5 90 2041 120 scL 150 2023 180 210 GND 240 SA1 Document 06519
8. Revision A 20 Mar 09 Dataram Corporation 2009 Page 1 DATARAM DTM63356G 4 GB 240 Pin Registered DDR2 DIMM ECC with CMD ADD Parity Front view 133 350 5 250 gt 0 157 0 394 30 000 un 1 181 _ 17 80 4 0 701 O NNMAN f ononnnnnnnnnnnnnnnnnnnpnnnnnnnnnnnnnnmn e Y Iis 2 54 Min 5 18 63 00 55 00 0 100 Min 0 2047 274 2 480 gt 2 165 123 00 4 842 Back view Side view _ gt _ 3 94 Max 0 155 Max 4 00 Min 0 157 Min Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed as millimeters inches 1 27 10 0 0500 20 Document 06519 Revision A 20 Mar 09 Dataram Corporation 2009 Page 2 DTM63356G 4 GB 240 Pin Registered DDR2 DIMM ECC with CMD ADD Parity VSS
9. Revision Code Module Manufacturing Date Module Serial Number 99 127 Manufacturer s Specific Data serial number UNUSED 00 Document 06519 Revision A 20 Mar 09 Dataram Corporation 2009 Page 12 DTM63356G DATARAM 4 GB 240 Pin Registered DDR2 DIMM ECC with CMD ADD Parity DATARAM DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06519 Revision A 20 Mar 09 Dataram Corporation 2009 Page 13
10. Strobe 0 18 ns DQ Input Pulse Width tpipw 0 35 tck 00 Output Access Time from Clock tpasck 400 400 ps Write DQS High Level Width toasH 0 35 Write DQS Low Level Width 0 35 DQS Out Edge to Data Out Edge Skew toasa 240 ps Data Input Setup Time Before DQS Strobe tos 100 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tck DGS Falling Edge to Clock Setup Time toss 0 2 tck Clock Half Period tup minimum of tcu or tci ns Address and Command Hold Time after Clock tin 0 275 ns Address and Command Setup Time before Clock tis 0 200 ns Load Mode Command Cycle Time tMRD 2 tck DQ to DQS Hold ton tup tous Data Hold Skew Factor tous 340 ps Active to Precharge Time tras 45 70K ns Active to Active Auto Refresh Time tre 60 ns RAS to CAS Delay trop 15 ns Average Periodic Refresh Interval 7 8 us Auto Refresh Row Cycle Time 127 5 ns Row Precharge Time 15 ns Read DQS Preamble Time tRPRE 0 9 1 1 tck Read DQS Postamble Time trest 0 4 0 6 tck Row Active to Row Active Delay 7 5 ns Internal Read to Precharge Command Delay trtp 7 5 ns Write DQS Preamble Setup Time twPRE 0 35 tck Write DQS Postamble Time twest 0 4 0 6 tck Write Recovery Time twR 15 ns Internal Write to Read Command Delay twTR 7 5 ns Exit Self Refresh to Non Read Command txsnr trec min 10 ns Exit Self Refresh to Read Command txsRD 200 tck Document 06519 Revision A 20 Mar
11. pF Input Capacitance Address BA 2 0 A 19 0 IS 1 0 RAS CAS CIN2 5 7 oF and Control WE CKE 1 0 ODT 1 0 Input Output Capacitance Pesit7 0 CIO 5 8 pF DC Characteristics Voltages referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current lu 10 10 pA 1 Output Leakage Current loz 10 10 pA 2 Output Minimum Source DC Current loH 13 4 mA 3 Output Minimum Sink DC Current lo 13 4 mA 4 Notes 1 These values are guaranteed by design and are tested on a sample basis only 2 DQxand ODT are disabled and 0 V lt Vout lt 3 Vpp 1 7 V 1420 mV Vpp lou must be less than 21 Ohms for values of Vout between Von and Vpp 280 mV 4 Vo 1 7 V Vout 280 mV Vouyr lo must be less than 21 Ohms for values of Vout between 0 V and 280 mV p J Document 06519 Revision A 20 Mar 09 Dataram Corporation 2009 Page 5 DATARAM DTM63356G lbo Specifications and Conditions Voltages referenced to Vss 0 V 4 GB 240 Pin Registered DDR2 DIMM ECC with CMD ADD Parity PARAMETER Symbol Test Condition ax Unit Note Operating One CKE is HIGH CS is HIGH between valid commands Address bus Bank Active 1000 inputs are switching Data bus inputs are switching 2140 mA 1 Precharge Current t Operating One E BI 20 Bank Act
12. 0 125 V AC Input Logic Levels Single Ended Voltages referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 ViH AC Vrer 0 250 V Logical Low Logic 0 ViL AC Vrer 0 250 V Document 06519 Revision A 20 Mar 09 Dataram Corporation 2009 Page 4 DATARAM DTM63356G 4 GB 240 Pin Registered DDR2 DIMM ECC with CMD ADD Parity Differential Input Logic Levels Voltages referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note DC Input Signal Voltage Vinc 0 300 Vpp 0 300 V 1 DC Differential Input Voltage 0 250 Vpp 0 600 V 2 AC Differential Input Voltage Vinac 0 500 Vpp 0 600 V 3 AC Differential Cross Point Voltage Vix AC 0 50 Vpp 0 175 0 50 Vpp 0 175 V 4 Notes 1 the allowable DC excursion of each input of a differential pair 2 specifies the input differential voltage i e the absolute value of the difference between the two voltages of a differential pair 3 Specifies the input differential voltage required for switching 4 The typical value of Vixiac is expected to be 0 5 Voo and is expected to track variations in Capacitance 0 C lt Tease lt 55 C f 100 MHz Voyt DC Vpp 2 Vour ac 0 1V p p PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO CIN1 2 3
13. 09 Dataram Corporation 2009 Page 7 DATARAM DTM63356G SERIAL PRESENCE DETECT MATRIX Function Value 4 GB 240 Pin Registered DDR2 DIMM ECC with CMD ADD Parity Number of Bytes Utilized by Module Manufacturer 128 bytes Total number of Bytes in SPD device 256 bytes Memory Type DDR2 SDRAM Number of Row Addresses Number of Column Addresses 14 Module Attributes Number of Ranks Package and Height of Ranks 2 Card on Card No DRAM Package Planar Module Height 30mm 6 Module Data Width 72 7 Reserved UNUSED 8 Voltage Interface Level of this assembly SSTLA 8V 05 9 Cycle time Max Supported CAS latency CL X tCK ns 3 30 10 SDRAM Access from Clock Highest CAS latency ns 0 45 45 DIMM configuration type Non parity Parity or ECC 06 Data Parity Data ECC X Address Command Parity X 11 TBD TBD TBD TBD 12 Refresh Rate Type us 7 8 SR 82 13 Primary SDRAM Width 4 04 14 Error Checking SDRAM Width 4 04 15 Reserved UNUSED 00 16 SDRAM Device Attributes Burst Lengths Supported 0 TBD TBD Burst Length 4 X Burst Length 8 X TBD TBD Document 06519 Revision A 20 Mar 09 Dataram Corporation 2009 Page 8 DTM63356G DATARAM 4 GB 240 Registered DDR2 DIMM ECC with CMD ADD Parity
14. bient due to Activate Precharge 00 Mode Bits DTO Mode Bits C 49 Bit 0 If 0 DRAM does not support high temperature self refresh entry 1 Bit 1 If 0 Do not need double refresh rate for the proper operation 0 DTO Bits 2 7 0 p H HE M Document 06519 Revision A 20 Mar 09 Dataram Corporation 2009 Page 10 DTM63356G DATARAM 4 GB 240 Pin Registered DDR2 DIMM ECC with CMD ADD Parity 50 DRAM Case Temperature Rise from Ambient due to Precharge Quiet Standby 0 00 DT2N DT2Q C 54 DRAM Case Temperature Rise from Ambient due to Precharge Power Down 0 00 DT2P Degree C DRAM Case Temperature Rise from Ambient due to Active Standby DT3N 52 0 00 Degree C 53 DRAM Case temperature Rise from Ambient due to Active Power Down with 0 00 Fast PDN Exit DT3Pfast Degree C 54 DRAM Case temperature Rise from Ambient due to Active Power Down with 0 00 Slow PDN Exit DT3Pslow Degree C DRAM Case Temperature Rise from Ambient due to Page Open Burst 00 Read DT4R4W Mode Bit DT4R DT4R4W Mode Bit Degree C 55 Bit 0 if DTAW is greater than DT4R 0 DTAR Bits 1 7 0 DRAM Case Temperature Rise from Ambient due to Burst Refresh DT5B 56 0 00 Degree C 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads 0 00
15. her control and address bus inputs are 3510 mA 1 Current switching Data bus inputs are switching Self Refresh CK and CK at 0 V CKE s 0 2 V Other control and address bus Current inputs are floating Data bus inputs are floating 540 mA 2 y All bank interleaving reads 0 mA BL 4 CL 5 tc AL 12 Operating Bank o Interleave Read Ine ns tarp 7 5 ns is HIGH CS is HIGH between valid 4120 mA 1 Current commands Address bus inputs are stable during deselects Data bus inputs are switching Notes 1 For all lpX measurements 3 0 ns tac 60 ns treco 15 ns tras 45 ns and trp 15 ns unless otherwise specified 2 All values shown are worst case maximums considering all DRAMs Registers and the PLL 2 For all lopX measurements one rank active the other rank is in IDD2P Precharge Power Down mode Document 06519 Revision A 20 Mar 09 Dataram Corporation 2009 Page 6 DTM63356G DATARAM 4 GB 240 Registered DDR2 DIMM ECC with CMD ADD Parity AC Operating Conditions PARAMETER Symbol Min Max Unit DQ Output Access Time from Clock tac 450 450 ps CAS to CAS Command Delay tccp 2 tck Clock High Level Width 0 45 0 55 Clock Cycle Time tck 3000 8000 ps Clock Low Level Width teL 0 45 0 55 Data Input Hold Time after DQS
16. ive Read loo Between valid commands Address bus inputs are switching 2320 mA 1 Precharge Current Precharge Power 52 All banks idle is LOW Other control and address bus inputs 540 mA 2 Down Current are stable Data bus inputs are floating Precharge Standby Ion2N All banks idle is HIGH CS is HIGH Other control and 1080 m 2 Current pii address bus inputs are switching Data bus inputs are switching All banks open is LOW Other control and address bus inputs iid ae Down Ipp3P F are stable Data bus inputs are floating Fast Power down exit 810 mA 2 Mode Register bit 12 0 All banks open tras 70 ms is HIGH CS is HIGH between edid Ipp3N valid commands Other control and address bus inputs are 1260 mA 2 switching Data bus inputs are switching Burst All banks open Continuous burst writes BL 4 CL 5 tck AL 0 9 lppAW tras 70 ms is HIGH CS is HIGH between valid commands 3580 mA 1 Write Current Address bus inputs are switching Data bus inputs are switching Operating Burst All banks open Continuous burst reads lour mA BL 4 CL 5 AL 0 tras 70 ms CKE is HIGH CS is HIGH Read Current Ipp4R between valid commands Address bus inputs are switching Data 3580 mA 1 bus inputs are switching Burst Refresh Refresh command at every 127 5 ns CKE is HIGH CS is HIGH Ipp5B between valid commands Ot
17. m Data Access Time tAC from Clock at CL X 2 ns 0 50 60 27 Minimum Row Precharge Time tRP ns 15 3C 28 Minimum Row Active to Row Active Delay tRRD ns 7 5 1E Minimum RAS to CAS Delay tRCD ns 15 Minimum Active to Precharge Time tRAS ns 45 Module Rank Density 2GB Address and Command Setup Time Before Clock tlS ns 0 2 Address and Command Hold Time After Clock ns 0 27 Data Input Setup Time Before Strobe tDS ns 0 1 Data Input Hold Time After Strobe tDH ns 0 17 Write Recovery Time tWR ns 15 Internal write to read command delay tWTR ns 7 5 Internal read to precharge command delay tRTP ns 7 5 Memory Analysis Probe Characteristics UNUSED Extension of Byte 41 tRC and Byte 42 tRFC ns Add this value to byte 41 Add this value to byte 42 SDRAM Device Minimum Active to Active Auto Refresh Time tRC ns SDRAM Device Minimum Auto Refresh to Active Auto Refresh Command Period tRFC ns SDRAM Device Maximum Cycle Time tCK max ns SDRAM Dev DQS DQ Skew for DQS amp DQ signals tDQSQ ns DDR SDRAM Device Read Data Hold Skew Factor tQHS ns PLL Relock Time us DRAM maximun Case Temperature Delta C 00 47 DT4R4W Delta Bits 0 3 Tcasemax delta Bits 7 4 48 Thermal Resistance of DRAM Package from Top Case to Ambient Psi 0 00 DRAM C Watt DRAM Case Temperature Rise from Am
18. with Auto Precharge DT7 C Thermal Resistance of PLL Package from Top to Ambient Psi PLL 58 0 00 C Watt 59 Thermal Resistance of Register Package from Top to Ambient Psi T A 0 00 Register C Watt PLL Case Temperature Rise from Ambient due to PLL Active DT PLL Active Degree C Register Case Temperature Rise from Ambient due to Register Active Mode Bit DT Register Active Mode Bit Bit O If O Unit for Bits 2 7 is 0 75C Bit 1 RFU Default 0 Register Active Bits 2 7 62 SPD Revision Revision 1 2 12 63 Checksum for Bytes 0 62 36 64 Module Manufacturer s JEDEC ID Code Dataram ID 7F 65 Module Manufacturer s JEDEC ID Code Dataram ID 91 66 71 Module Manufacturer s JEDEC ID Code UNUSED 00 pD M ERR HE n M eer Document 06519 Revision A 20 Mar 09 Dataram Corporation 2009 Page 11 DTM63356G DATARAM 4 GB 240 Registered DDR2 DIMM ECC with CMD ADD Parity 72 Module Manufacturing Location UNUSED 00 73 Module Part Number D 44 74 Module Part Number A 41 75 Module Part Number T 54 76 Module Part Number A 41 77 Module Part Number R 52 Module Part Number 4D Module Part Number Module Part Number 20 Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module
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