Dataram DTM63344F memory module
Contents
1. mA 3 Output Minimum Sink DC Current loL 13 4 mA 4 Notes 1 These values are guaranteed by design and are tested on a sample basis only 2 DQx and ODT are disabled and 0 V lt Vout lt Vpp 3 Voo 1 7 V Vout 1420 mV Vour Voo lon must be less than 21 Ohms for values of Vout between Von and Vopn 280 mV 4 Vo 1 7 V Vour 280 mV Vourt lo must be less than 21 Ohms for values of Vout between 0 V and 280 mV a eS a a DO E E a a e OE Document 06607 Revision A 20 SEP 10 Dataram Corporation 2010 Page 5 Dy DATARAM DTM63344F Optimizing Value and Performance 2 GB 240 Pin Unbuffered ECC DDR2 DIMM lbo Specifications and Conditions TA 0 to 70 C Voltage referenced to Vss 0 V 4 Max PARAMETER Symbol Test Condition Value Unit Operating One CKE is HIGH CS is HIGH between valid commands Address Bank Active lpp0 bus inputs are switching Data bus inputs are switchin 675 mA Precharge Current p 9 p 9 Operating One lour 0 MA BL 4 CL 5 ns AL 0 CKE is HIGH CS is Bank Active Read Ipbp1 HIGH between valid commands Address bus inputs are 765 mA Precharge Current switching Precharge Power lop2P All banks idle CKE is LOW Other control and address bus inputs 180 mA Down Current 2 are stable Data bus inputs are floating Precharge Standby lon 2N All banks idle CKE is HIGH CS is HIGH Other control and 630 mA Current A address bus in2. Clock at CL X 1 ns 0x4 Maximum Data Access Time tAC from Clock at CL X 2 ns 0x0 Minimum Row Precharge Time tRP ns 28 Minimum Row Active to Row Active Delay tRRD ns aj U o x o o o o x B Minimum RAS to CAS Delay tRCD ns P15 Minimum Active to Precharge Time tRAS 45 Module Rank Density Address and Command Setup Time Before Clock tIS ns olo x EE U o Ojo x lt X lt M N N O ns 02 Data Input Setup Time Before Strobe DS ns ot Wife Recovery Time WR ns E Internal write to read command delay tWTR ns ae intemal read fo precharge command delay RTP NE 75 50 Extension of Byte 41 tRC and Byte 42 tRFC ns Add this value to byte 41 0 Add this value to byte 42 0 5 SDRAM Device Minimum Active to Active Auto Refresh Time tRC ns SDRAM Device Minimum Auto Refresh to Active Auto Refresh 127 5 Command Period tRFC ns SDRAM Device Maximum Cycle Time tCK max ns BB SISIR wj ONIO o x m 15 7 5 15 45 0 2 0 1 15 7 5 7 5 o x m o E Document 06607 Revision A 20 SEP 10 Dataram Corporation 2010 Page 9 DD DATARAM DTM63344F AN 2 GB 240 Pin Unbuffered ECC DDR2 DIMM 44 SDRAM Dev DQS DQ Skew for DQS amp DQ signals DQSQ ns 0 24 45 DDR SDRAM Device Read Data Hold Skew Factor tQHS ns PLL Relock Time us UNUSED 47 DRAM maximun Case Temperature Delta Deg
3. Da1 340025 ls4vpD 94 vss f24vss 154Vss 184 VDD 214 DQ46 DM 8 0 Data Mask 5 VSS 35 VSS 65 VSS 95 DQ42 125 DMO 155 DM3 185 CKO 215 DQ47 CK 2 0 CK 2 0 Differential Clock Inputs 6 DQSO 36 Das3 66 VSS 96 DQ43 126 NC 156 NC 186 CKO 216 VSS CKE 1 0 Clock Enables 7 paso 37Dbas3 67 VDD 97 vss 127 VSS 157 VSS 187 VDD 217 DQ52 ICAS Column Address Strobe 8 VSS 38 VSS 68NC 98 DQ48 128 pae 158 DAZO 188 AO 218 DQ53 IRAS Row Address Strobe 9 DQ2 39DQ26 69 VDD 99 DQ49 f129 Da7 159DAZ1 189VD D 219 vss S 1 0 Chip Selects 10DQ3 40 DQ27 70410 100vSS 130 VSS jiso vss 190BA1 220 CK2 NE Write Enable 11vss 41 VSS 71 BAO 101 sa2 131 Da12 161 CBA 191 VDD 221 CK2 A 15 0 Address Inputs 12 DAB 42 CBO 72VDD 102NC 132DQ13 162 CB5 192 RAS 222 vss BA 2 0 Bank Addresses 13DQ9 43 CB1 73 WE 103 vss f33vss 163 vss 193 SO 223 DM6 ODTI1 0 On Die Termination Inputs 14vss 44 VSS 74 ICAS 104 DAS6 134 DMI 164 Doma 194VDD 224 NC SA 2 0 SPD Address 15 DQS1 45 DQS8 75VDD 105 pase 135 NC 165 NC 195 ODTO 225 vss SCL SPD Clock Input 16 DQS1 46 pasa 76 51 foe vss 136 vss fiee vss 196413 226 DAS4 SDA SPD Data Input Output 17 VSS 47 VSS 77 ODT1 107 DQ50 137 CK1 167 cBe f197vDD 227 DQ55 VSS Ground 18 NC 48 CB2 78 VDD 108 DQ51 138 CK1 168 cB7 f98vss 228 vss VDD Power 19 NC 49 CB3 79 vss 109vss 139 VSS 169vss 199 DA36 229 DaGO VDDSPD SPD EEPROM Power 20vss 50 VSS
4. 65 123 00 4 843 Back view Side view 7 iti HA AL U U US A 0 157 Min O NO A O CCC NOT U ONO U O 0t 27240 4 sa 0 0500 40 0040 D Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches Document 06607 Revision A 20 SEP 10 Dataram Corporation 2010 Page 2 ID DATARAM DTM63344F eS 2 GB 240 Pin Unbuffered ECC DDR2 DIMM 151 o 150 01 TT II HD DMRO DQRSO O DQSRO O DQS DAS CS DM DQS DAS DQR 7 0 OG VO 7 0 VO 7 0 DMR1 DQSR1 O DQSR1 O IDAS DAS CS DM IDAS DAS CS DM DORI15 8 O 1 0 7 0 VO 7 0 DMR2 DOSR2 9 IDASR2 7 IDAS DQS CS DM IDAS Das CS DM DARI23 16 O 0 7 0 VO 7 0 DMR3 O DOSR3 O DQSR3 O DQS DAS CS DM IDAS DAS CS DM DQRI31 24 O VO 7 0 VO 7 0 DMR8 O e DOSRB DQSR8 O 7 IDAS Das CS DM IDAS Das CS DM CBRI7 0 O V O 7 0 VO 7 0 22 OHMS DQ 63 0 O WA O DQR 63 0 CB 7 0 O VA O CBR 7 0 DAS 8 0 O VWA O DASR 8 0 DAS 8 0 O TVA O DARS 8 0 DM 8 0 O VWAJ O DMR 8 0 GLOBAL SDRAM CONNECTS 7 5 OHMS BA 2 0 O VW O BA 2 0 R A 13 0 O WA O A 13 0
5. 80 DQ32 110 Da56 fi40Da14 170 vDD 200 DQ37 230 DQ61 VREF Reference Voltage 21 Dalo 51 VDD 81 DQ33 111 DQ57 141 DQ15 171 CKE1 201 vss 231 vss NC No Connection 22 DQ11 52 CKE0 82 vss 112 vss 142 vss 172 VDD 202 DM4 232 DM7 23 VSS 53 VDD 83 DQS4 113 DQS7 143 Da20 173 A15 203 NC 233 NC 24 DQ16 54 BA2 84 Das4 114 Das7 144 DAZ1 174 Al4 204 vss 234 vss 25 DQ17 55 NC 85 vss 1145 VSS 145 VSS 175 VDD 205 DQ38 235 DQ62 26VSS 56 VDD 86 DQ34 116 DQ58 146 DM2 176A12 206 DAZY 236 DQ63 27 IDAS2 57 A11 87 DQ35 117 Da59 147 NC 177 AQ 207 VSS 237 VSS 28 DAS2 58 A7 88 vss 118vss i48Vss 178 VDD 208 DQ44 238 VDDSPD 29VSS 59VDD 89 DQ40 119 SDA 149 DQ22 179 AB 209 DQ45 239 SAO 30 DQ18 60 A5 90 DQ41 120 SCL 150 DQ23 180 A6 210 VSS 240 SA1 Connected but not used Document 06607 Revision A 20 SEP 10 Dataram Corporation 2010 Page 1 Dy DATARAM DTM63344F tt 2 GB 240 Pin Unbuffered ECC DDR2 DIMM Front view a 133 35 gt 5 250 10 00 0 594 30 00 3 E 1 181 y ome C 17 80 0 700 S TATA AAA AAA AAA AAA AAA TATA A AAA AA AAA AAA S P 5 00 2 54 Min 0 197 0 100 5 18 63 00 gt 55 00 Min 0 204 2 480 2 1
6. PLL Package from Top to Ambient Psi T A UNUSED 0x0 PLL C Watt 59 Thermal Resistance of Register Package from Top to Ambient Psi UNUSED 0x0 T A Register C Watt PLL Case Temperature Rise from Ambient due to PLL Active DT UNUSED 0x0 PLL Active Degree C Register Case Temperature Rise from Ambient due to Register Active Mode Bit DT Register Active Mode Bit oa oa o O Bit 0 If O Unit for Bits 2 7 is 0 75C Bit 1 RFU Default O Register Active Bits 2 7 Document 06607 Revision A 20 SEP 10 Dataram Corporation 2010 Page 10 DD DATARAM DTM63344F ie 2 GB 240 Pin Unbuffered ECC DDR2 DIMM Ces Checksum Be I re 73 90 Module Part Number 000000000 eo 96 Module Serial Number 000000000 OE bel 97 Module Serial Number 0000000 RO Del 96 Module Serial Number 100000 Cd Document 06607 Revision A 20 SEP 10 Dataram Corporation 2010 Page 11 Tee DTM63344F 2 GB 240 Pin Unbuffered ECC DDR2 DIMM d M Optimizing Value and Performance NY DATARAM ss 4 Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headguarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this
7. R IRAS O A O RASR ICAS OOVA O CASR ME O VWW O MER CKEO 9 ckeo Z 22 pF CKE1 CKE1 I 22 pF ODTO ODTO I 22 pF ODT1 ODTI Z 22 pF SO SO 22 pF 151 51 212 22 pF DMR4 DQRS4 DQSR4 000 DAS DAS DAR 39 32 O VO 7 0 ICS DM DAS DAS CS DM VO 7 0 DMRS DQRSS 00 DQSR5 t DAS DAS DAR 47 40 O VO 7 0 ICS DM DQS DAS CS DM VO 7 0 DMR6 DQRS6 DQSR6 DAS DAS DAR 55 48 O VO 7 0 ICS DM DAS DAS CS DM VO 7 0 DMR7 O DQRS7 DQSR7 DAS DAS DAR 63 46 O VO 7 0 ICS DM ICS DQS DQS DDSPD Vop VREF Vss SCL WP VO 7 0 3 X 200 OHMS aKo SDRAM X 6 ICKO 3 X 200 OHMS ae SDRAM X 6 ICK1 3 X 200 OHMS Ce SDRAM X 6 ICK2 DECOUPLING h Oot Serial PD i ole All Devices F All SDRAMs mm All Devices SERIAL PD e gt spa SA0 SA1 SA2 a a E E a a OE E z Document 06607 Revision A 20 SEP 10 Dataram Corporation 2010 Page 3 2 GB 240 Pin Unbuffered ECC DDR2 DIMM Optimizing Value and Performance Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TSTORAGE 55 100 C Ambient Te
8. SED 6x0 SDRAM Device Attributes Burst Lengths Supported TBD TBD Burst Length 4 Burst Length 8 TBD TBD TBD TBD 17 SDRAM Device Attributes Number of Banks on SDRAM Device 800 SDRAM Device Attributes CAS Latency o x o 00 TBD TBD Latency 2 Latency 3 Latency 4 Latency 5 Latency 6 TBD 19 DIMM Mechanical Characteristics Max module thickness mm 0x01 20 DIMM type information 00 O o x o N Regular RDIMM 133 35mm Regular UDIMM 133 35mm X Document 06607 Revision A 20 SEP 10 Dataram Corporation 2010 Page 8 DD DATARAM DTM63344F ti 2 GB 240 Pin Unbuffered ECC DDR2 DIMM SODIMM Micro DIMM Mini RDIMM Mini UDIMM 67 6mm 45 5mm 82 0mm 82 0mm TBD TBD SDRAM Module Attributes Refer to Byte20 for DIMM type information Number of active registers on the DIMM N A for UDIMM Number of PLL on the DIMM N A for UDIMM FET Switch External Enable TBD Analysis probe installed TBD ala la a SDRAM Device Attributes General Includes Weak Driver Supports 50 ohm ODT Supports PASR Partial Array Self Refresh TBD TBD TBD TBD o x o oO TB Minimum Clock Cycle Time at Reduced CAS Latency CL X 1 ns 3 75 0x3 Maximum Data Access Time tAC from
9. document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06607 Revision A 20 SEP 10 Dataram Corporation 2010 Page 12
10. fter Clock tin 275 ps Address and Command Setup Time before Clock tis 200 ps Load Mode Command Cycle Time turD 2 tck DQ to DQS Hold ton tup tans Data Hold Skew Factor tans 340 ps Active to Precharge Time tras 45 70K ns Active to Active Auto Refresh Time tre 60 ns RAS to CAS Delay trop 15 ns Average Periodic Refresh Interval REFI 7 8 HS Auto Refresh Row Cycle Time RFC 127 5 ns Row Precharge Time tre 15 ns Read DQS Preamble Time RPRE 0 9 1 1 tox Read DQS Postamble Time RPST 0 4 0 6 tck Row Active to Row Active Delay RRD 7 5 ns Internal Read to Precharge Command Delay tRTP 7 5 ns Write DQS Preamble Time twPRE 0 35 ps Write DQS Postamble Time twpsT 0 4 0 6 tck Write Recovery Time twr 15 ns Internal Write to Read Command Delay twtr 7 5 ns Exit Self Refresh to Non Read Command txsnr trec min 10 ns Exit Self Refresh to Read Command txsrp 200 tck Document 06607 Revision A 20 SEP 10 Dataram Corporation 2010 Page 7 py Ly DTM63344F eS 2 GB 240 Pin Unbuffered ECC DDR2 DIMM SERIAL PRESENCE DETECT MATRIX OOA Module Attributes Number of Ranks Package and Height of Ranks 2 Card on Card No DRAM Package Planar Module Height 30mm 0x80 0x08 x0 olo x o m ZE 7 0x05 SDRAM Cycle time Max Supported CAS Latency CL X tCK ns 0x30 10 i 0x02 72 0x82 13 Primary SDRAM Won ro ErorChecking SDRAM f e 14 15 o A UNU
11. mperature Operating Ta 0 70 C DRAM Case Temperature Operating TCASE 0 85 C Voltage on Vpp relative to Vss Vpp 0 5 2 3 V Voltage on Any Pin relative to Vss Vin Vout 0 5 2 3 V Recommended DC Operating Conditions T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER A B ri r a Note Power Supply Voltage O Reference Voltage Bus Termination Voltage Notes Veer 0 04 VREF Vrer 0 04 1 The value of Vger is expected to equal one half Vpp and to track variations in the Vpp DC level Peak to peak noise on Veer May not exceed 1 of its DC value DC Input Logic Levels Single Ended TA 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 VIH DC Vrer 0 125 Voo 0 300 V Logical Low Logic 0 ViL oc 0 300 Vrer 0 125 V AC Input Logic Levels Single Ended TA 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin ac Vrer 0 250 V Logical Low Logic 0 Vilac Vrer 0 250 V o i a a OE eee a Document 06607 Revision A 20 SEP 10 Dataram Corporation 2010 Page 4 ee 2 GB 240 Pin Unbuffered ECC DDR2 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note DC Input Signal Voltage Vinc 0 300 Vpp 0 300 V 1 DC Differential I
12. nput Voltage Vipioc 0 250 Voo 0 600 V 2 AC Differential Input Voltage Vinac 0 500 Voo 0 600 V 3 AC Differential Cross Point Voltage Vixiac 0 50 VDD 0 175 0 50 VDD 0 175 V 4 Notes 1 Vinoc Specifies the allowable DC excursion of each input of a differential pair 2 Vipo specifies the input differential voltage i e the absolute value of the difference between the two voltages of a differential pair 3 Vac Specifies the input differential voltage required for switching 4 The typical value of Vixiac is expected to be 0 5 Voo and is expected to track variations in Vpp Capacitance T 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CK 2 0 CK 2 0 CIN1 6 12 pF Input Capacitance Address and Control BA 2 0 A 13 0 RAS CAS WE CIN2 18 36 pF Input Capacitance Control S 1 0 CKE 1 0 ODT 1 0 CIN3 9 18 pF DQ 63 0 CB 7 0 DASI3 0 Input Output Capacitance DQS 8 0 DMI8 0 CIO 5 7 pF DC Characteristics TA 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current Command and Address lu 80 80 JA 1 Input Leakage Current S 1 0 CKE 1 0 lu 40 40 yA 1 ODT 1 0 Input Leakage Current CK 2 0 CK 2 0 lu 30 30 yA 1 Input Leakage Current DM lu 10 10 yA 1 Output Leakage Current DQS DQ loz 10 10 pA 2 Output Minimum Source DC Current loH 13 4
13. o b 3150 mA valid commands Address bus inputs are stable during deselects Current i aie Data bus inputs are switching One module rank in this operation rest in IDD2P All module ranks in this operation Notes 1 For all IppX measurements tex 3 ns tac 55 ns treco 15 ns tras 40 ns and tre 15 ns unless otherwise specified 2 All lppX values shown are worst case maximums considering all DRAMs a a eS T lO es Document 06607 Revision A 20 SEP 10 Dataram Corporation 2010 Page 6 A 2 GB 240 Pin Unbuffered ECC DDR2 DIMM 3 AC Operating Conditions PARAMETER Symbol Min Max Unit DQ Output Access Time from Clock tac 450 450 ps CAS to CAS Command Delay tceco 2 tck Clock High Level Width tcH 0 48 0 52 tck Clock Cycle Time tck 3000 8000 ps Clock Low Level Width teL 0 48 0 52 tck Data Input Hold Time after DQS Strobe toH 175 ps DQ Input Pulse Width toipw 0 35 tck DQS Output Access Time from Clock toasck 400 400 ps Write DQS High Level Width toasH 0 35 tox Write DQS Low Level Width toast 0 35 tex DQS Out Edge to Data Out Edge Skew toasa 240 ps Data Input Setup Time Before DQS Strobe tos 100 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tck DQS Falling Edge to Clock Setup Time toss 0 2 tck Clock Half Period tue minimum of tcy or tez ns Address and Command Hold Time a
14. puts are switching Data bus inputs are switching z All banks open CKE is LOW Other control and address bus dh Ipp3P inputs are stable Data bus inputs are floating Fast Power down 360 mA exit Mode Register bit 12 0 z All banks open tras 70 ms CKE is HIGH CS is HIGH between Active Standby lbb3N valid commands Other control and address bus inputs are 810 mA Current Rs gt ae switching Data bus inputs are switching All banks open Continuous burst writes BL 4 CL 5 tcx Operating Burst lop W AL 0 tras 70 ms CKE is HIGH CS is HIGH between valid 1215 mA Write Current Dp commands Address bus inputs are switching Data bus inputs are switching All banks open Continuous burst reads lout 0 mA BL 4 Operating Burst Io 4R CL 5 tck AL 0 tras 70 ms CKE is HIGH CS is HIGH 1215 mA Read Current Dp between valid commands Address bus inputs are switching Data bus inputs are switching Burst Refresh Refresh command at every 75 ns CKE is HIGH CS is HIGH Ino5 between valid commands Other control and address bus inputs 1320 mA Current ats arte are switching Data bus inputs are switching Self Refresh loo6 CK and CK at 0 V CKE lt 0 2 V Other control and address bus 180 mA Current pD inputs are floating Data bus inputs are floating A All bank interleaving reads lout 0 mA BL 4 CL 5 tex Operating Bank s AL 70ns taro 7 5 ns CKE is HIGH CS is HIGH between Interleave Read In
15. ree C DT4R4W Delta Bits 0 3 Tcasemax delta Bits 7 4 0 48 Thermal Resistance of DRAM Package from Top Case to Ambient UNUSED 0x00 Psi T A DRAM C Watt 49 DRAM Case Temperature Rise from Ambient due to Activate Precharge Mode Bits DTO Mode Bits Degree C Bit 0 If O Do not need double refresh rate for the proper operation Bit 1 If 0 DRAM does not support high temperature self refresh entry DTO Bits 2 7 0 DRAM Case Temperature Rise from Ambient due to UNUSED 0x00 Precharge Quiet Standby DT2N DT2Q Degree C DRAM Case Temperature Rise from Ambient due to Precharge UNUSED 0x00 Power Down DT2P Degree C 52 DRAM Case Temperature Rise from Ambient due to Active Standby UNUSED 0x00 DT3N Degree C 53 DRAM Case temperature Rise from Ambient due to Active Power UNUSED 0x00 Down with Fast PDN Exit DT3Pfast Degree C 54 DRAM Case temperature Rise from Ambient due to Active Power UNUSED 0x0 Down with Slow PDN Exit DT3Pslow Degree C DRAM Case Temperature Rise from Ambient due to Page Open Burst Read DT4R4W Mode Bit DT4R DT4R4W Mode Bit Degree C Bit 0 0 if DT4W is greater than DT4R 0 DTAR Bits 1 7 0 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh UNUSED 0x0 DT5B Degree C 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave UNUSED 0x0 Reads with Auto Precharge DT7 Degree C 98 Thermal Resistance of
16. yee DIM63344F 2 GB 240 Pin Unbuffered ECC DDR2 DIMM Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high Operating Voltage 1 8 V 0 1 O Type SSTL 18 Data Transfer Rate 5 3 Gigabytes sec Bursts Length 4 and 8 Programmable I O driver strength OCD Programmable On Die Termination ODT Programmable CAS Latency 4 or 5 Differential Redundant Data Strobe signals SDRAM Addressing Row Col Bank 14 10 3 Fully ROHS Compliant Pin Configuration Identification DTM63344F 256Mx72 2GB 2Rx8 PC2 5300E 555 12 G0 Performance range Clock Module Speed CL trep trp 333MHz DDR2 667 5 5 5 267MHz DDR2 533 4 4 4 Description DTM63344F is an Unbuffered ECC 256Mx72 memory module which conforms to JEDEC s DDR2 PC2 5300 standard The assembly consists of two Ranks Each Rank is comprised of nine 128Mx8 DDR2 Samsung SDRAMs One 2K bit EEPROM is used for Serial Presence Detect Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals Pin Description Front Side Back Side Name Function 1 VREF 31DQ19 6144 91 vss 121VSS 151 vss 181 VDD 211 DM5 CBI7 0 Data Check Bits 2 vss 32 VSS 62 VDD 92 Das5 h22 Da4 152 DA28 182 AZ 212 NC DAJ63 0 Data Bits 3 DQO 33D024 6342 933 Das5 123 Da5 153 DQ29 183 A1 213 VSS DASI8 0 DASI3 0 Differential Data Strobes 4
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