Integral INPCIE64G70MXB solid state drive
Contents
1. DD 15 0 o7 host 2 HA ES gt tack DAO DA1 DA2 cso CS1 NOTES 1 See 9 14 1 Initiating an Ultra DMA data out burst 2 The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted nitialing an Ultra DMA data out data burst HSTROBE at host DD 15 0 at host HSTROBE at device laca XXXXXXX XKXXXXXX XXXXXXX at device NOTES 1 See 9 14 2 The data out transfer 2 DD 15 0 and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Sustained Ultra DMA data out burst 19 DD 15 0 host DAO DA1 DA2 CS0 CS1 dd NAO NOTES 1 See 9 14 4 1 Host terminating an Ultra DMA data out burst 2 The definitions for lhe STOP DOMARDY and MSTROBE signal lines are no longer in effect after DMARO and DMACK are negated Host terminating an Ultra DMA data out burst DMARO device DMACK host STOP host ODMARDY device HSTROBE host OD 15 0 host DAO DA1 DA2 cs0 CS1 NOTES 1 See 9 14 4 2 Device pausing an Ultra DMA data out burst 2 The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and OMACK are negated Device term2. eve toy tows tom les tevs tes tores 70 0 ty tuu t taz tzm tzan tees tae lhorpyz SD tack tos NOTES 1 All timing measurement switching points low to high and high to low shall be taken at 1 5 V 2 All signal transitions for a timing parameter shall be measured at the connector specified in the measurement location column For example in the case of ters both STROBE and DMARDY transitions are measured at the sender connector 3 The parameter t yg shall be measured at the recipient s connector farthest from the sender 4 The parameter tu shall be measured at the connector of the sender or recipient that is responding to an incoming transition from the recipient or sender respectively Both the incoming signal and the outgoing response shall be measured at the same connector 5 The parameter taz shall be measured at the connector of the sender or recipient that is driving the bus but must release the bus the allow for a bus turnaround 15 Ultra DMA data burst timing descriptions rye Typical sustained average two cycle time Cycle time allowing for asymmetry and clock variations from STROBE edge to STROBE edge Two cycle time allowing for clock variations from nsing edge to next rising edge or from falling edge to next falling edge of STROBE Data setup time at recipient from data valid until STROBE edge See note 2 5 Data hold time at recipient from STROBE edge until data ma
3. PINASSIGNMENTS 33305 5207555 a Secs Sa ts EA E 5 232 PIN DESCRIPTIONS 2225 tt a es sae SRO e ts cee Ree en ets ane Bien oe 6 ELECTRICAL CHARACTERISTICS sssccsssssssssssssccsssscccssssccccssscccscssscsessssccccssssccecssssecees 8 3 1 ABSOLUTE MAXIMUM RATING da eee 8 3 2 DC CHARACTERISTICS OF 5 0V I O CELLS HOST INTERFACE c cccccecssecesseeesseesees 8 33 AC CHARACTERISTICS 0 A Bek cake eI 9 3 3 1 PIO Data Transfer oooococcccncnononononononononononononononononononononononononononononononeneneninos 9 3 3 2 Multiword DMA Data Transfer ooccccncnnnnnonononononononononononononononononononeninininene 12 3 3 3 Ultra DMA Data Transfer oocccccncnonononononononononononononononononononononononononenenininens 15 3 4 POWER MANAGEMENT tidad tildes 21 SOFTWARE INTERFACE bvsssssssssscseseccsssossessseess cosssccsssesecsssessessssscsccsssssebeseseascessceasseteeesdenseessese 21 4 1 ATA TASK FILE REGISTERS old dd iii eee 21 42 COMMANDSETS coeessddeeeeve tovdeus osdveusccescdovbecapeetsodesbodbedessabsevesdeeseddeseees 22 4 3 IDENTIFY DRIVE INFORMATION 0 cccccccccsccsccecsesscsscsececeesssssssccecesssesessesceeesessseseesees 23 PHYSICAL DIMENSI N 6vsssssssssessedectsssscscsedescecsesnntecscssssosiveenssosnscaseobessesesieasossebadeosseteessiesteoses 25 WEIGHT ivscscsscccvissssscsstevsccssssvescssesseccsssbicestevssesessessesunconsessbacbincess coseceussesescedsviecesseudscsdiesdecssbueieosse 26
4. ty is a limited time out that has a defined minimum t is a limited time out that has a defined maximum 2 80 conductor cabling See 7 3 shall be required in order to meet setup tos tes and hold toy ton times in modes greater than 2 3 Timing for tovs towm tevs and tevy shall be met for lumped capacitive loads of 15 and 40 pf at the connector where the Data and STROBE signals have the same capacitive load value Due to reflections on the cable these timing measurements are not valid in a normally functioning system 4 For all modes the parameter tzjorpy may be greater than teny due to the fact that the host has a pull up on IORDY giving it a known state when released 5 The parameters tos and ton for mode 5 are defined for a recipient at the end of the cable only in a configuration with a single device located at the end of the cable This could result in the minimum values for tos and toy for mode 5 at the middle connector being 3 0 and 3 9 ns respectively 16 DMARQ device DMACK host t _ ts tack je STOP RRA Pl host AAAA HDMARDY host eco T taoroy tee DSTROBE device town DD 15 0 SOOOGOOOPOK SKXKXK OOO DAO DA DA2 eso esi XX XXX NOTES 1 See 9 13 1 Initiating an Ultra DMA data in burst 2 The definitions for the DIOW STOP DIOR HDMARDY HSTROBE and ORDY DDMARDY DSTROBE signal lines are not in effect until DMARO and DMACK are asserted Initi
5. 1 0 Block Diagram PATA Link Controller 1 1 Capacity Specification 16GB 16 441 270 272 16383 16 63 32GB 32 279 224 320 16383 16 63 64GB 64 558 448 640 16383 16 63 2 0 Specification 2 1 Pin Assignments JIC UTC JU MITT Pin Number Signal Pin Number Signal 1 HDO 2 HD15 3 HD1 4 GND 5 HD2 6 HD14 7 HD3 8 HD13 9 GND 10 HD12 11 HD4 12 HD11 13 HD5 14 HD10 15 GND 16 HD9 17 HD6 18 GND 19 HD7 20 HD8 21 GND 22 nHRESET 23 NC 24 nHIOW 25 NC 26 CSEL 27 GND 28 nHIOR 29 GND 30 nDMACK 31 NC 32 DMARQ 33 NC 34 GND 35 GND 36 NC 37 HA0 38 NC 39 HA1 40 GND 41 HA2 42 IORDY 43 nIOIS 16 44 INTRQ 45 nPDIAG 46 nHCS0 47 3V3 48 nHCS1 49 3V3 50 GND 51 3V3 32 nDASP 2 2 Pin Description Pin No Signal I O Description 22 RESET I Hardware reset signal from the host 1 3 5 7 11 13 17 HD0 HD15 Device Data I O 16 bit bi direction Data Bus DD 7 0 are 19 20 16 14 12 used for 8 bit register transfers 10 8 6 2 32 DMARQ DMA Request O For DMA data transfers Device will assert DMARQ when the device is ready to transfer data to or from the host 24 DIOW VO Write I This is the strobe signal used by the host to write to the device register or Data port STOP Stop UDMA Burst The hos
6. Voltage lIohl 4 32 mA 2 4 Vv lin Input Leakage Current No pull up or pull 10 1 10 pA down loz Tri state Output Leakage 10 1 10 pA Current 3 3 AC Characteristics 3 3 1 PIO Data Transfer ADDR valid woyy TV Y See note 1 KAKA NAAA to asiel ta DIOR DIOW WRITE DETE A DSO nN ren an mr lteter DD 7 0 See note 2 READ 7 09 L AA AX See note 2 ts ts Ls loz IORDY See note 3 3 1 JORDY AAA A APODO See note 3 3 2 te tro IORDY NAAA X AA XA AAAA h See note 3 3 3 i NOTES 1 Device address consists of signals CS0 CS1 and DA 2 0 2 Data consists of DD 7 0 3 The negation of ORDY by the device is used to extend the register transfer cycle The determination of whether the cycle is to be extended is made by the host after ta from the assertion of DIOR or DIOW The assertion and negation of ORDY are described in the following three cases 3 1 Device never negates IORDY devices keeps IORDY released no wait is generated 3 2 Device negates IORDY before ta but causes IORDY to be asserted before ts IORDY is released prior to negation and may be asserted for no more than 5 ns before release no wait generated 3 3 Device negates IORDY before ta IORDY is released prior to negation and may be asserted for no more than 5 ns before release wait generated The cycle completes after IORDY is reasserted For cycles where a wait is generated and DIOR is asserted
7. min 20 5 5 tkr DIOR negated pulse width min 50 50 25 See note tkw DIOW negated pulse width min 215 50 25 See note tir DIOR to DMACK delay max 120 40 35 tiw DIOW to DMACK delay max 40 40 35 tu CS 1 0 valid to DIOR DIOW min 50 30 25 ty CS 1 0 hold min 15 10 10 tz DMACK to read data released max 20 25 25 Notes ty is the minimum total cycle tp is the minimum DIOR DIOW assertion time and tk tkg or tkw as appropriate is the minimum DIOR DIOW negation time A host shall lengthen tp and or tx to ensure that ty is equal to the value reported in the devices IDENTIFY DEVICE data 14 3 3 3 Ultra DMA Data Transfer Ultra DMA data burst timing requirements Name Mode 0 Mode 1 A Mod 5 3 Ka 5 Ey 3 3 Mode 6 Measurement s in ns in ns in ns location Min Max Min Max Min Max e Jal 0 Sender Note 3 Sender Recipient Recipient Sender Sender Device Device Host Host Device Sender Device Note 4 Host Host Note 5 Host Device Host Sender Recipient Device Device Host Sender no EG o ml ee Rn S jaja rm pao my D D mj e slo N gt SIN a gt Oo So Sls o nio o mm i NS Poo a oji o Le alk ola 3 is l l e ae ELLE ELE La o a Le nh nN N oo a nN S i k ejsle 8 s el8 Jelse EE a a m 3 3 3 o WS 8 o No o p n o h
8. the Device shall negate DMARO within t of the assertion of the current DIOR ar DIOW pulse The last data word for the burst shall then be transferred by the negation of the current DIOR or DIOW pulse If all data for the command has not been transferred the device shall reassert DMARQ again at any later time to resume the OMA operation as shown in figure 66 Device terminating a Multiword DMA data burst CS0 CS1 tre DMARQ KAAKX See note 2 DMACK See note 1 DIOR DIOW PESO ESO OSO IX XX XXX Write DD 15 0 NOTE 1 To terminate the transmission of a data burst the host shall negate DMACK within t after a DIOR or DIOW pulse No further DIOR or DIOW pulses shall be asserted for this burst 2 If the device is able to continue the transfer of data the device may leave DMARQ asserted and wait for the host to reassert DMACK or may negate DMARO at any time after detecting that DMACK has been negated Host terminating a Multiword DMA data burst 13 Multiword DMA timing parameters Mode 0 Mode 1 Mode2 Note ns ns ns to Cycle time min 480 150 120 See note to DIOR DIOW asserted pulse width min 215 80 70 See note te DIOR data access max 150 60 50 tr DIOR data hold min 5 5 5 tg DIOR DIOW data setup min 100 30 20 ty DIOW data hold min 20 15 10 ti DMACK to DIOR DIOW setup min 0 0 0 ty DIOR DIOW to DMACK hold
9. the device shall place read data on DD 7 0 for tep before asserting IORDY 4 DMACK shall remain negated during a register transfer PIO timing parameters Mode 0 Model Mode2 Mode3 Mode 4 Note ns ns ns ns ns to Cycle time min 600 383 240 180 120 1 4 ti Address valid to 70 50 30 30 25 DIOR DIOW setup min tz DIOR DIOW min 165 125 100 80 70 1 tzi DIOR DIOW recovery time 70 25 1 min tz DIOW data setup min 60 45 30 30 20 t4 DIOW data hold min 30 20 15 10 10 t DIOR data setup min 50 35 20 20 20 to DIOR data hold min 5 5 5 5 5 ts DIOR data tristate max 30 30 30 30 30 2 to DIOR DIOW to address 20 15 10 10 10 10 valid hold min trp Read Data Valid to IORDY 0 0 0 0 0 active if IORDY initially low after ta min ta IORDY Setup time 35 35 35 35 35 3 tg IORDY Pulse Width max 1250 1250 1250 1250 1250 tc IORDY assertion to release 5 5 5 5 5 max Notes 1 tois minimum total cycle tz is minimum DIOR DIOW assertion time and tz is the minimum DIOR DIOW negation time A host implementation shall lengthen tz to ensure that ty is equal to or greater than the value reported in the devices IDENTIFY DEVICE data A device implementation shall support any length host implementation 2 This parameter specifies the time from the negation edge of DIOR to the time that the data is released by t
10. 0 CS1 Chip select I These signals are used to select the Command Block and Control Block registers When DMACK is asserted Cs0 and Cs1 shall be negated and transfers shall be 16 bit wide 52 DASP Device active Device I O During the reset protocol DASP shall be 1 present asserted by Device 1 to indicate that the device is present 47 49 51 VCC P Power supply 9 15 21 27 29 35 GND Ground 4 18 26 34 40 50 Note p o yo p An input from the host system to the device An output from the device to the host system An input output bi direction common Power supply 3 0 Electrical Characteristics 3 1 Absolute Maximum Rating Item Symbol Parameter MIN MAX Unit 1 Von Vss DC Power Supply 0 3 5 5 Vv 2 VIN Input Voltage Vss 0 3 Vppt0 3 Vv 3 Ta Operating Temperature 0 70 C 4 Tst Storage Temperature 25 85 C Parameter Symbol MIN TYP MAX Unit Vpp Voltage Vop 3 0 3 3 3 6 Vv 4 5 5 0 5 5 Vv 3 2 DC Characteristics of 5 0V I O Cells Host Interface Symbol Parameter Conditions MIN TYP MAX Unit Vil Input Low Voltage TTL 5V 0 85 V Vih Input High Voltage 1 25 Vv Vil Input Low Voltage TTL 3 3V 105 V Vih Input High Voltage 1 75 Vv Vol Output Low Voltage loll 4 32 mA 0 4 Vv Voh Output High
11. aling an Ultra DMA data in burst OSTROBE at device DD 15 0 at device OSTROBE at host DD 15 0 VAVA gt ue Pr N at host APODOS XXXXXXX XXXKXXXX NOTES 1 Sos 9 13 2 The data in transfer 2 DD 15 0 and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device Sustained Ultra DMA data in burst 17 DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 DAO DA1 DA2 CS0 CS1 NOTES 1 See 9 13 4 1 Device terminating an Ultra DMA data in burst 2 The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Device terminating an Ultra DMA data in burst ee ae p tu gt tuni gt DMACK ee host le tzan OI pi tee gt Uz a lack STOP host HDMARDY host DSTROBE device DAO DAT DA2 CS0 CS1 NOTES 1 See 9 13 4 2 Host pausing an Ultra DMA data in burst 2 The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Host terminating an Ultra DMA data in burst 18 DMARQ device tur DMACK host tack STOP 7 DDMARDY HSTROBE host
12. ds are zero Word Address Default Value Total Bytes Data Field Type Information General configuration bit significant for 0 044Ah 2 Non removable device 1 xxxxh 2 Default number of cylinders 2 0000h 2 Reserved 3 xxxxh 2 Default number of heads 4 7E00h 2 Retired 5 0200h 2 Retired 6 xxxxh 2 Default number of sectors per track 7 8 xxxxh 4 Number of sectors per device 9 0000h 2 Retired 10 19 xxxxh 20 Serial Number in ASCII 20 0002h 2 Retired 21 0002h 2 Retired Number of ECC Bytes passed on Read Write Long 22 0004h 2 Commands 23 26 Aaaah 8 Firmware revision in ASCII 27 46 xxxxh 40 Model number in ASCII Maximum number of sector that shall be 47 8001h 2 transferred on Read Write Multiple commands 48 0000h 2 Reserved 49 2B00h 2 Capabilities LBA DMA Supported 50 4000h 2 Reserved 51 0200h 2 PIO data transfer cycle timing mode 2 52 0000h 2 Retired 53 0007h 2 Word 54 58 64 70 and 88 are valid 54 xxxxh 2 Current numbers of cylinders 55 xxxxh 2 Current numbers of heads 56 xxxxh 2 Current sectors per track 23 Word Address Default Value Total Bytes Data Field Type Information Current capacity in sectors LBAs Word 57 LSW 57 58 Nnnnh 4 Word 58 MSW 59 0101h 2 Multiple sector setting is valid 60 61 Aaaah 4 Total number of sectors addressable in LBA Mode 62 0000h 2 Re
13. he device 3 The delay from the activation of FIOR or DIOW until the state of IORDY is first sampled If IORDY is inactive then the host shall wait until IORDY is active before the PIO cycle is complete If the device is not driving IORDY negated at the t after the activation of DIOR or DIOW that t shall be met and tgp is not applicable If the device is driving IORDY 10 negated at the time t after the activation of DIOR or DIOW then tRD shall be met and t is not applicable Mode may be selected at the highest mode for the device if CS 1 0 and DA 2 0 do not change between read or write cycle or selects at the highest mode supported by the slowest device if CS 1 0 and DA 2 0 do change between read or write cycles 11 3 3 2 Multiword DMA Data Transfer See note DMACK DIOR DIOW Read DD 15 0 Write DD 15 0 NOTE The host shall not assert DMACK or negate both CSO and CS1 until the assertion of DMARQ is detected The maximum time from the assertion of DMARQ to the assertion of DMACK or the negation of both CSO and CS1 is not defined Initialing a Multiword DMA data burst CS0 CS1 DMARQ DMACK DIOR DIOW Read DD 15 0 Write DD 15 0 Sustaining a Multiword DMA data burst CS0 CS1 ty DMARO See note DMACK DIOR DIOW Read DD 15 0 Write DD 15 0 NOTE To terminate the data burst
14. inating an Ultra DMA data out burst 20 3 4 Power Management System Power Consumption Ta 0 to 70 C Symbol Parameter E Conditions MIN TYP MAX Unit Icer Read current mA O Pi m fremre ECM E A A E it free ECOS IO fo ES ES E CS ESC O E o Ipd Power down current 3 3V mA Note Test Based on 8 pieces of TSOP flash 4 0 Software Interface 4 1 ATA Task File Registers The I O decoding of each register is as follows CS1 CS0 A2 A1 AO DIOR 0 DIOW 1 DIOW 0 DIOR 1 1 0 0 0 0 Data Read Data Write 1 0 0 0 1 Error Feature 1 0 0 1 0 Sector Count Sector Count 1 0 0 1 1 Sector Number LBA7 0 Sector Number LBA7 0 1 0 1 0 0 Cylinder Low LBA 15 8 Cylinder Low LBA 15 8 1 0 1 0 1 Cylinder High LBA 23 16 Cylinder High LBA 23 16 1 0 1 1 0 Drive Head LBA 27 24 Drive Head LBA 27 24 1 0 1 1 1 Status Command 0 1 1 1 0 Alternate Status Device Control 0 1 1 1 1 Drive Address Reserved 21 4 2 Command Sets Below table summarizes the PATA PCIe command set with the paragraphs that follow describing the individual commands and task file for each command No Command Set Code FR SC SN CY DR HD LBA 1 CFA Erase Sector s Coh Y Y Y Y Y Y 2 CFA Reque
15. integral STORAGE TECHNICAL DATASHEET Integral Mini PCle 70mm Specification Version 1 0 Features o Standard ATA IDE Bus Interface 512 Bytes Sector ATA comm and set compatible e Capacities Integral Z Series MLC 16GB 32GB 64GB Integral E Series SLC Please call for availability e Data Transfer mode Support Data Transfer up to PIO mode 6 Support Data Transfer up to Multiword DMA mode 2 Support Data Transfer up to Ultra DMA mode 5 Performance Integral Z Series MLC Flash Sustain Read Speed up to 35MB s Sustain Write Speed up to 15MB Ss Integral E Series SLC Flash Please call for availability Sustain Read Speed up to 45MB s Sustain Write Speed up to 35MB s Temperature Ranges 0 C to 70 C for operating 25 C to 85 C for storage Operating Voltage 3 3V Intelligent ATA IDE Module Built in Embedded Flash File System Implements dynamic wear leveling algorithms and static wear leveling algorithms to increase endurance of flash media Built in ECC corrects up to 12 random bits error per 512 bytes RoHS Compliance 1 0 2 0 3 0 4 0 5 0 6 0 TABLE OF CONTENTS BLOCK DIA GRAM atada dd da tddi 4 1 1 CAPACITY SPECIFICATION 000cccccccccsscsscccccccscssssscesccccecsesssessessesesesseessssseeceessesesseceseeseeees 4 SPECIFICATION 4552233 sstacg iassesscesstasacssesscisasctevsctesdessesacieesedeesunecessbestsdastessossudeeesssotees dassderisvanseeses 5 21
16. st Extended Error Code 03h Y 3 CFA Translate Sector S7h Y 4 CFA Write Multiple w o Erase CDh Y 5 CFA Write Sector w o Erase 38h Y 6 Check Power Mode ESh SE Y 7 Execute Device Diagnostic 90h Y 8 Identify Device ECh S Y se 9 Idle E3h Y Y 10 Idle Immediate Elh Y sa 11 Initialize Device Parameters 91h Y Y Y 12 NOP 00h Y z 13 Read Buffer E4h SE zz Y os on 14 Read DMA C8h Y Y Y Y Y Y 15 Read Multiple C4h Y Y Y Y Y Y 16 Read Sector s 20h Y Y Y Y Y Y 17 Read Verify Sector s 40h Y Y Y Y Y Y 18 Seek 70 Y Y Y Y Y 19 Set Features EFh Y Y is 20 Set Multiple Mode C6h Y Y Ta T 21 Sleep E6h Y S 22 Standby E2h En Y Sa dE 23 Standby Immediate E0h ad Y a 24 Write Buffer E8h Y as 25 Write DMA CAh Y 26 Write Multiple C5h Y 27 Write Sector s 30h Y Note FR Feature Register HD Head No of Drive Head Register SC Sector Count Register LBA LBA mode supported SN Sector Number Register Y Set up 22 CY Cylinder Low High Register DR Drive bit of Drive Head register 4 3 Identify Drive Information Not set up The Identity Drive Command enables Host to receive parameter information from the device The parameter words in the buffer have the arrangement and meanings defined in below table All reserve bits or wor
17. t assert this signal during an UDMA burst to stop the DMA burst 42 IORDY I O channel ready O This signal is used to temporarily stop the host register access read or write when the device is not ready to respond to a data transfer request DDMARDY UDMA ready The device will assert this signal to indicate that the device is ready to receive UDMA data out burst DSTROBE UDMA data When UDMA mode DMA Read is active strobe this signal is the data in strobe generated by the device 26 CSEL Cable select I This pin is used to configure this device as Device 0 or Device 1 30 DMACK DMA I This signal is used by the host in respond acknowledge to DMARQ to initiate DMA transfer 44 INTRQ Interrupt O When this device is selected this signal is the active high Interrupt Request to the host 43 IOIS16 O During PIO transfer mode0 lor 2 this pin indicates to the host the 16 bit data port has been addressed and the device is prepared to send or receive a 16 bit data word When transferring in DMA mode the host must use a 16 bit DMA channel and this signal will not be asserted 37 39 41 HA0 HA2 Device Address I This is 3 bit binary coded Address Bus 45 PDIAG Passed diagnostics VO This signal will be asserted by Device 1 to indicate to Device 0 that Device 1 has completed diagnostics CBLID Cable assembly type identify 46 48 CS
18. tired 63 0n07h 2 Multiword DMA mode 2 and below are supported 64 0003h 2 Advance PIO transfer modes supported Minimum Multiword DMA transfer cycle time 65 0078h 2 120nsec Manufacturer s recommended Multiword DMA 66 0078h 2 transfer cycle time 120nsec Minimum PIO transfer cycle time without flow 67 0078h 2 control 120nsec Minimum PIO transfer cycle time with IORDY flow 68 0078h 2 control 120nsec 69 81 0000h 26 Reserved 82 0002h 2 Supports Security Mode feature set 83 87 0000h 10 Reserved 88 On7Fh 2 Ultra DMA mode 6 and below are supported 89 127 0000h 78 Reserved 128 0021h 2 Enhanced security erase supported 129 159 0000h 62 Reserved vendor unique bytes 160 255 0000h 192 Reserved Note 1 a Vender Specific Configuration 2 n Host Selectable Configuration 24 5 0 Physical Dimension oo o O DN AM 2 2 60 HOLES 69 50 67 00 4 00 3 20 0 00 oo Dn N oo oN 0 Ds on A A NM Top View 3 70 A 69 50 BOTTOM SIDE DETAIL A 0 00 1 10 0 10 ZA 32 10 0 00 Side amp Bottom View Note 1 Unit mm General Tolerance 0 1 25 6 0 Weight 1 8 TSOP Flash 10 2g 2 4 TSOP Flash 8 2g 3 2 TSOP Flash 7 2g 4 1 TSOP Flash 6 7g 26
19. y become invalid See note 2 5 is Data valid setup time at sender from data valid until STROBE edge See note 3 Data valid hold time at sender from STROBE edge until data may become invalid See note 3 CRC word valid hold time at sender from DMACK negation until CRC may become invalid See note 3 Time from STROBE output released to driving until the first transition of critical timing put released to driving until the first transition of critical timing First STROBE time for device to first negate DSTROBE from STOP durina a data in burst Limited interlock time See note 1 nterlock time with minimum See note 1 Unlimited interlock time See note 1 A Envelope time from DMACK to STOP and HDMARDY during data in burst initiation and from DMACK to STOP during data out burst initiation Ready to final STROBE time no STROBE edges shall be sent this long after negation of DMARDY to pause time that recipient shall wait to pause after negatina 2 z Time from STROBE edge to negation of DMARQ or assertion of STOP when sender terminates a burst 5 g 5 S nm uy tus tz za tao E ES O 6 Zz O 4 m 0 1 The parameters ty ty in Figure 74 and Figure 75 and tu indicate sender to recipient or recipient to sender interlocks i e one agent either sender or recipient is waiting for the other agent to respond with a signal before proceeding tu is an unlimited interlock that has no maximum time value
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