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Intel Core QX9775

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1. Thermal Metrology The minimum and maximum case temperatures Tc sE are specified in Table 5 2 is Power W Tease max C Power W Tcase_max C 0 35 0 80 50 0 5 35 9 85 50 9 10 36 9 90 51 8 15 37 8 95 52 8 20 38 7 100 53 7 25 39 7 105 54 6 30 40 6 110 55 6 35 41 5 115 56 5 40 42 5 120 57 4 45 43 0 125 58 4 50 44 4 130 59 3 55 45 3 135 60 2 60 46 2 140 61 2 65 47 2 145 62 1 70 48 1 150 63 0 75 49 0 measured at the geometric top center of the processor integrated heat spreader IHS Figure 5 2 illustrates the location where Tcase temperature measurements should be made For detailed guidelines on temperature measurement methodology refer to the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 77 Figure 5 2 Case Temperature TcAsg Measurement Location 5 2 5 2 1 5 2 1 1 78 Measure from the edge of the top surface of processor IHS 14 75mm u Measure Tcase geometric center of the top surface of the IHS 14 75mm i I i i i See 0 iii 37 5 mm x 37 5mm Substrate NOTE Figure is not to scale and is for reference only Processor Thermal Features Intel Thermal Monitor Features The processor provides two thermal monitor features Thermal Monitor TM1 and Enhanced Thermal Monitor TM2 The Thermal Monitor and Enhanced Thermal Monitor must both be enabled in BIOS fo
2. Table 4 2 Land Listing by Land Number Sheet 17 of he Pin Name EB A Direction AM18 VCC Power Other AM19 VCC Power Other AM20 VSS Power Other AM21 VCC Power Other AM22 VCC Power Other AM23 VSS Power Other AM24 VSS Power Other AM25 VCC Power Other AM26 VCC Power Other AM27 VSS Power Other AM28 VSS Power Other AM29 VCC Power Other AM30 VCC Power Other AN1 VSS Power Other AN2 VSS Power Other AN3 SEE Power Other Output AN4 ENSE Power Other Output AN5 RESERVED AN6 RESERVED AN7 VID_SELECT Power Other Output AN8 VCC Power Other AN9 VCC Power Other AN10 VSS Power Other AN11 VCC Power Other AN12 VCC Power Other AN13 VSS Power Other AN14 VCC Power Other AN15 VCC Power Other AN16 VSS Power Other AN17 VSS Power Other AN18 VCC Power Other AN19 VCC Power Other AN20 VSS Power Other AN21 VCC Power Other AN22 VCC Power Other AN23 VSS Power Other AN24 VSS Power Other AN25 VCC Power Other AN26 VCC Power Other 63 intel 4 2 Table 4 1 64 Land Listing and Signal Description Signal Definitions Signal Definitions Sheet 1 of 11 Name Type Description Notes A 37 3 1 0 A 37 3 Address define a 238 byte physical memory address space In sub phase 1 of the address phase these signals transmit the address of a transaction In sub phase 2 these signals transmit transaction ty
3. Datasheet Land Listing and Signal Description Datasheet Table 4 1 Land Listing by Land Name Sheet 3 of 17 Table 4 1 intel Land Listing by Land Name Sheet 4 of 17 Land Name m s Direction Land Name pon amer ds Direction D27 G13 Source Sync Input Output DP2 H16 Common Clk Input Output D28 F14 Source Sync Input Output DP3 J17 Common Clk Input Output D29 G14 Source Sync Input Output DRDY C1 Common Clk Input Output D30 F15 Source Sync Input Output DSTBNO C8 Source Sync Input Output D31 G15 Source Sync Input Output DSTBN1 G12 Source Sync Input Output D32 G16 Source Sync Input Output DSTBN2 G20 Source Sync Input Output D33 E15 Source Sync Input Output DSTBN3 A16 Source Sync Input Output D34 E16 Source Sync Input Output DSTBPO B9 Source Sync Input Output D35 G18 Source Sync Input Output DSTBP1 E12 Source Sync Input Output D36 G17 Source Sync Input Output DSTBP2 G19 Source Sync Input Output D37 F17 Source Sync Input Output DSTBP3 C17 Source Sync Input Output D38 F18 Source Sync Input Output FERR PBE R3 Open Drain Output D39 Els Source Sync Input Output FORCEPR AK6 CMOS ASync Input D40 E19 Source Sync Input Ou
4. AGTL Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes Vu Input Low Voltage 0 10 0 GTLREF 0 10 V 2 4 6 Vin Input High Voltage GTLREF 0 10 Vit Vqr 0 10 V 3 6 Vou Output High Voltage Vr 0 10 N A VIT V 4 6 Ron Buffer On Resistance 8 25 10 25 12 25 Q 5 lu Input Leakage Current N A N A 100 HA 7 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vi is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value 3 Viu is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 Vin and Voy may experience excursions above Vyr However input signal drivers must comply with the signal quality specifications 5 This is the pull down driver resistance Measured at 0 31 Vr Roy min 0 158 Ry Ron typ 0 167 Rz RoN max 0 175 Rz 6 GTLREF should be generated from V m with a 1 tolerance resistor divider The V referred to in these specifications is the instantaneous Vr 7 Specified when on die Rrr and Roy are turned off Viy between 0 and Vr 29 intel Electrical Specifications Table 2 15 CMOS Signal I nput Output Group and TAP Signal Group DC Specifications Table 2 16 2 13 1 Table 2 17 Vcc Overshoot Specifications 30 Symbol Param
5. intel Intel Core 2 Extreme Processor QX9775 Features Available at 3 2 GHz Intel Intelligent Power Capability e FSB frequency at 1600 MHz e Intel Advanced Digital Media Boost R Optimized for 32 bit applications running on Enhanced Intel Speedstep Technology advdriced 32spiF opersting yciem e4 Supports Intel 64 architecture Two 6 MB Level 2 caches T Intel HD Boost utilizing new SSE4 Supports Execute Disable Bit capability instructions for improved multimedia performance especially for video encoding and photo processing Supports Intel virtualization Technology Binary compatible with applications running on previous members of the Intel microprocessor line System Management mode Intel Wide Dynamic Execution 24 way cache associativity provides S improved cache hit rate on load store e Intel Advanced Smart Cache operations Intel Smart Memory Access 771 land Package The Intel Core 2 Extreme processor QX9775 designed for dual socket configurations delivers Intel s most advanced processor for professional multimedia content creation and for intense visual gaming The processor is designed to deliver performance across applications and usages where end users can truly appreciate and experience the performance Datasheet 7 Introduction 1 Note Datasheet intel Introduction The Intel Core 2 Extreme processor QX9775 is a server workstation pr
6. The Stop Grant state requires chipset and BIOS support on multiprocessor systems In a multiprocessor system all the STPCLK signals are bussed together thus all processors are affected in unison When the STPCLK signal is asserted the processor enters the Stop Grant state issuing a Stop Grant Special Bus Cycle SBC for each processor die The chipset needs to account for a variable number of processors asserting the Stop Grant SBC on the bus before allowing the processor to be transitioned into one of the lower processor power states 85 intel Figure 6 1 Stop Clock State Machine Features HALT or MWAIT Instruction and Normal State Normal execution HALT Bus Cycle Generated INIT BINIT INTR NMI SMI RESET FSB interrupts A STPCLK Asserted STPCLK De asserted Extended HALT or HALT State BCLK running Snoops and interrupts allowed A Snoop Event Occurs Snoop Event Serviced Y Extended HALT Snoop or HALT Snoop State BCLK running Service snoops to caches Stop Grant State BCLK running Snoops and interrupts allowed Snoop Event Occurs Snoop Event Serviced Stop Grant Snoop State BCLK running Service snoops to caches 6 2 1 Normal State This is the normal operating 6 2 2 state for the processor HALT or Extended HALT State The Extended HALT state C1E is enabled via the BIOS
7. 5 3 2 3 5 3 2 4 Table 5 3 84 PECI Specifications PECI Device Address The PECI device address for socket 0 is 30h and socket 1 is 31h Note that each address also supports two domains DomainO and Domain1 For more information on PECI domains please refer to the Platform Environment Control Interface PECI Specification PECI Command Support PECI command support is covered in detail in Platform Environment Control Interface Specification Refer to this document for details on supported PECI command function and codes PECI Fault Handling Requirements PECI is largely a fault tolerant interface including noise immunity and error checking improvements over other comparable industry standard interfaces The PECI client is as reliable as the device that it is embedded in and thus given operating conditions that fall under the specification the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures There are however certain scenarios where PECI is known to be unresponsive Prior to a power on RESET and during RESET assertion PECI is not assured to provide reliable thermal data System designs should implement a default power on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI To protect platforms from potential operational or safety issues due to an abnormal condition on PECI the Host cont
8. Legacy input signals such as A20M IGNNE INIT SMI and STPCLK utilize CMOS input buffers Legacy output signals such as FERR PBE IERRZ PROCHOT and THERMTRIP utilize open drain output buffers All of the CMOS and Open Drain signals are required to be asserted deasserted for at least eight BCLKs in order for the processor to recognize the proper signal state See Section 2 13 for the DC specifications See Chapter 5 for additional timing requirements for entering and leaving the low power states Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic it is recommended that the processor s be first in the TAP chain followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Similar considerations must be made for TCK TDO TMS and TRST Two copies of each signal may be required with each driving a different voltage level Platform Environmental Control Interface PECI DC Specifications PECI is an Intel proprietary one wire interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices The processor contains Digital Thermal Sensor DTS sprinkled both inside and outside the cores in a die These sensors are implemented as analog to
9. Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design refer to the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 The processor implements a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control and to assure processor reliability Selection of the appropriate fan speed is based on the relative temperature data reported by the processor s Platform Environment Control Interface PECI bus as described in Section 5 3 If the value reported via PECI is less than TcoNTRoL then the case temperature is permitted to exceed the Thermal Profile If the value reported via PECI is greater than or equal to TcoNrRoL then the processor case temperature must remain at or below the temperature as specified by the thermal The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT see Section 5 2 Processor Thermal Features Systems that implement fan speed control must be designed to use this data Systems that do not alter the fan speed only need to ensure the case temperature meets the thermal profile specifications The processor supports a single Thermal Profile see Figure 5 1 Table 5 1 With this Thermal Profi
10. digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature PECI provides an interface to relay the highest DTS temperature within a die to external devices for thermal fan speed control More detailed information may be found in the Platform Environment Control Interface PECI Specification DC Characteristics The PECI interface operates at a nominal voltage set by Vz The set of DC electrical specifications shown in Table 2 10 is used with devices normally operating from a Vr interface supply Vr nominal levels will vary between processor families All PECI devices will operate at the Vz level determined by the processor installed in the system For specific nominal V m levels refer to Table 2 3 Datasheet Electrical Specifications Table 2 10 PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Notes Vin Input Voltage Range 0 150 Vit V Vnysteresis HySteresis 0 1 Vir N A V Vn Negative edge threshold voltage 0 275 Vr 0 500 Vr V Vp Positive edge threshold voltage 0 550 Vz 0 725 Vaz V High level output source I 6 0 N A mA source Von 0 75 Vyr Low level output sink lej 0 5 1 0 mA sink VoL 0 25 V4 High impedance state leakage to lieak VTT N A 50 UA 2 Vieak Vow High impedance leakage to GND laic E a N A 10 uA 2 Vieak Vou Cpus Bus c
11. must be connected to a V power source through a resistor for proper processor operation Refer to Section 2 6 for TESTHI grouping restrictions TESTIN1 TESTIN2 TESTIN1 must be connected to a VIT power source through a resistor as well as to the TESTIN2 land of the same socket for proper processor operation TESTIN2 must be connected to a VTT power source through a resistor as well as to the TESTIN1 land of the same socket for proper processor operation THERMTRI P Assertion of THERMTRIP Thermal Trip indicates the processor junction temperature has reached a temperature beyond which permanent silicon damage may occur Measurement of the temperature is accomplished through an internal thermal sensor Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To protect the processor its core voltage Vcc must be removed following the assertion of THERMTRIP Intel also recommends the removal of V when THERMTRI P is asserted Driving of the THERMTRIP signals is enabled within 10 us of the assertion of PWRGOOD and is disabled on de assertion of PWRGOOD Once activated THERMTRIP remains latched until PWRGOOD is de asserted While the de assertion of the PWRGOOD signal will de assert THERMTRIP if the processor s junction temperature remains at or above the trip level THERMTRI P will again be asserted within 1
12. 0 Design Guidelines for further details Power source characteristics must be assured to be stable whenever the supply to the voltage regulator is stable 17 intel Electrical Specifications Table 2 3 Voltage I dentification Definition HEX VID6 VID5 VID4 VID3 VID2 VI D1 Vec_ MAX HEX VI D6 VI D5 VID4 VID3 VID2 VI D1 Vcc_ MAX 7A 1 1 1 1 0 1 0 8500 3C 0 1 1 1 1 0 1 2375 78 1 1 1 1 0 0 0 8625 3A 0 1 1 1 0 1 1 2500 76 1 1 1 0 1 1 0 8750 38 0 1 1 1 0 0 1 2625 74 1 1 1 0 1 0 0 8875 36 0 1 1 0 1 1 1 2750 72 1 1 1 0 0 1 0 9000 34 0 1 1 0 1 0 1 2875 70 1 1 1 0 0 0 0 9125 32 0 1 1 0 0 1 1 3000 6E 1 1 0 1 1 1 0 9250 30 0 1 1 0 0 0 1 3125 6C 1 1 0 1 1 0 0 9375 2E 0 1 0 1 1 1 1 3250 6A 1 1 0 1 0 1 0 9500 2C 0 1 0 1 1 0 1 3375 68 1 1 0 1 0 0 0 9625 2A 0 1 0 1 0 1 1 3500 66 1 1 0 0 1 1 0 9750 28 0 1 0 1 0 0 1 3625 64 1 1 0 0 1 0 0 9875 26 0 1 0 0 1 1 1 3750 62 1 1 0 0 0 1 1 0000 24 0 1 0 0 1 0 1 3875 60 1 1 0 0 0 0 1 0125 22 0 1 0 0 0 1 1 4000 5E 1 0 1 1 1 1 1 0250 20 0 1 0 0 0 0 1 4125 5C 1 0 1 1 1 0 1 0375 1E 0 0 1 1 1 1 1 4250 5A 1 0 1 1 0 1 1 0500 1C 0 0 1 1 1 0 1 4375 58 1 0 1 1 0 0 1 0625 1A 0 0 1 1 0 1 1 4500 56 1 0 T 0 1 1 1 0750 18 0 0 1 T 0 0 1 4625 54 1 0 1 0 1 0 1 0875 16 0 0 1 0 1 1 1 4750 52 1 0 1 0 0 1 1 1000 14 0 0 1 0 1 0 1 4875 50 1 0 1 0 0 0 1 1125 12 0 0 1 0 0 1 1 5000 4E 1 0 0 1 1
13. 1 1 1250 10 0 0 1 0 0 0 1 5125 4C 1 0 0 1 1 0 1 1375 OE 0 0 0 1 1 1 1 5250 4A 1 0 0 1 0 1 1 1500 OC 0 0 0 1 1 0 1 5375 48 1 0 0 1 0 0 1 1625 0A 0 0 0 1 0 1 1 5500 46 1 0 0 0 1 1 1 1750 08 0 0 0 1 0 0 1 5625 44 1 0 0 0 1 0 1 1875 06 0 0 0 0 1 1 1 5750 42 1 0 0 0 0 1 1 2000 04 0 0 0 0 1 0 1 5875 40 1 0 0 0 0 0 1 2125 02 0 0 0 0 0 1 1 6000 3E 0 1 1 1 1 1 1 2250 00 0 0 0 0 0 0 OFF NOTES 18 When the 111111 VID pattern is observed the voltage regulator output should be disabled The VID range includes VID transitions that may be initiated by thermal events assertion of the FORCEPR signal see Section 5 2 4 Extended HALT state transitions see Section 6 2 2 or Enhanced Intel SpeedStep Technology transitions see Section 6 3 The Extended HALT state must be enabled for the processor to remain within its specifications Once the VRM EVRD is operating after power up if either the Output Enable signal is de asserted or a specific VID off code is received the VRM EVRD must turn off its output the output should go to high impedance within 500 ms and latch off until power is cycled Refer to Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines Datasheet m Electrical Specifications n tel Table 2 4 Table 2 5 2 6 Datasheet Loadline Selection Truth Table for LL 1D 1 0 LL ID1 LL IDO Description 0 0 Reserved 0 1 Intel Core 2 Extreme proces
14. 160 VID 0 170 1 2 3 125 VID 0 156 VID 0 166 VID 0 176 1 2 3 130 VID 0 163 VID 0 173 VID 0 183 1 2 3 135 VID 0 169 VID 0 179 VID 0 189 1 2 3 140 VID 0 175 VID 0 185 VID 0 195 1 2 3 145 VID 0 181 VID 0 191 VID 0 201 1 2 3 150 VID 0 188 VID 0 198 VID 0 208 1 2 3 NOTES 1 The Vcc_ min and Vcc wax loadlines represent static and transient limits See Section 2 13 1 for Vcc overshoot specifications 2 This table is intended to aid in reading discrete points on Figure 2 3 3 The loadlines specify voltage limits at the die measured at the VCC DIE SENSE and VSS DIE SENSE lands and across the VCC DIE SENSE2 and VSS DIE SENSE2 lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC DIE SENSE and VSS DIE SENSE lands and VCC DIE SENSE2 and VSS DIE SENSE2 lands Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for socket load line guidelines and VR implementation Datasheet Electrical Specifications Figure 2 3 Table 2 14 Datasheet intel Processor Vcc Static and Transient Tolerance Load Lines VI VI VI Vcc V VI VI VI D 0 000 D 0 050 4 D 0 100 4 D 0 150 4 D 0 200 4 D 0 250 Icc A 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 Voc Maximum Voc Typical Voc Minimum
15. AH10 Power Other VSS AM10 Power Other VSS AH13 Power Other VSS AM13 Power Other VSS AH16 Power Other VSS AM16 Power Other VSS AH17 Power Other VSS AM17 Power Other VSS AH20 Power Other VSS AM20 Power Other VSS AH23 Power Other VSS AM23 Power Other VSS AH24 Power Other VSS AM24 Power Other VSS AH3 Power Other VSS AM27 Power Other VSS AH6 Power Other VSS AM28 Power Other VSS AJ10 Power Other VSS AM4 Power Other VSS AJ13 Power Other VSS AM7 Power Other vss AJ16 Power Other VSS AN1 Power Other VSS AJ17 Power Other VSS AN10 Power Other VSS AJ20 Power Other VSS AN13 Power Other VSS AJ23 Power Other VSS AN16 Power Other VSS AJ24 Power Other VSS AN17 Power Other VSS AJ27 Power Other VSS AN2 Power Other VSS AJ28 Power Other VSS AN20 Power Other VSS AJ29 Power Other VSS AN23 Power Other VSS AJ30 Power Other VSS AN24 Power Other VSS AJ4 Power Other VSS Bl Power Other VSS AK10 Power Other VSS B11 Power Other VSS AK13 Power Other VSS B14 Power Other VSS AK16 Power Other VSS B17 Power Other VSS AK17 Power Other VSS B20 Power Other VSS AK2 Power Other VSS B24 Power Other VSS AK20 Power Other VSS B5 Power Other VSS AK23 Power Other VSS B8 Power Other VSS AK24 Power Other VSS C10 Power Other VSS AK27 Power Other VSS C13 Power Other VSS AK28 Power Other VSS C16 Power Other VSS AK29 Power Other VSS C19 Power Other VSS AK30 Power Other VSS C22 Power Other VSS AK5 Power Other VSS C24 Power Other VSS AK7 Power Other VSS C4 Po
16. AL18 VCC Power Other AK4 VIDA CMOS Async Output AL19 VCC Power Other AK5 VSS Power Other AL20 VSS Power Other AK6 FORCEPR CMOS Async lnput AL21 VCC Power Other AK7 VSS Power Other AL22 vcc Power Other AK8 VCC Power Other AL23 VSS Power Other AK9 VCC Power Other AL24 VSS Power Other AK10 VSS Power Other AL25 VCC Power Other AK11 vCC Power Other AL26 VCC Power Other AK12 vCC Power Other AL27 VSS Power Other AK13 VSS Power Other AL28 VSS Power Other AK14 vCC Power Other AL29 VCC Power Other AK15 VCC Power Other AL30 VCC Power Other AK16 VSS Power Other AMI VSS Power Other AK17 VSS Power Other AM2 RESERVED AK18 VCC Power Other AM3 VID2 CMOS Async Output AK19 VCC Power Other AMA VSS Power Other AK20 vss Power Other AM5 vID6 CMOS Async Output AK21 vcc Power Other AM6 RESERVED AK22 VCC Power Other AM7 VSS Power Other AK23 VSS Power Other AM8 VCC Power Other AK24 VSS Power Other AM9 VCC Power Other AK25 VCC Power Other AMIO vss Power Other AK26 VCC Power Other AM11 VCC Power Other AK27 VSS Power Other AMI2 VCC Power Other AK28 vss Power Other AM13 vss Power Other AK29 VSS Power Other AM14 VCC Power Other AK30 VSS Power Other AM15 VCC Power Other AL1 RESERVED AM16 VSS Power Other AL2 PROCHOT Open Drain Output AMI7 VSS Power Other Datasheet Land Listing and Signal Description Datasheet
17. GTLREF DATA MID and GTLREF DATA END is used for the 4X front side bus signaling group and GTLREF ADD MID and GTLREF ADD END is used for the 2X and common clock front side bus signaling groups GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END must be generated on the baseboard See Table 2 18 for GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END specifications Termination resistors Rrr for AGTL signals are provided on the processor silicon and are terminated to V7 The on die termination resistors are always enabled on the processor to control reflections on the transmission line Intel chipsets also provide on die termination thus eliminating the need to terminate the bus on the baseboard for most AGTL signals Some FSB signals do not include on die termination R77 and must be terminated on the baseboard See Table 2 8 for details regarding these signals The AGTL bus depends on incident wave switching Therefore timing calculations for AGTL signals are based on flight time as opposed to capacitive deratings Analog signal simulation of the FSB including trace lengths is highly recommended when designing a system Contact your Intel Field Representative to obtain the processor signal integrity models which includes buffer and package models Power and Ground Lands For clean on chip processor core power distribution the processor has 223 Vcc power and 267 Vss ground inputs All Vcc lands
18. Ho Pin Name Tear NN Direction AB1 VSS Power Other AD29 vVCC Power Other AB2 IERR Open Drain Output AD30 VCC Power Other AB3 MCERR Common Clk Input Output AE1 TCK TAP Input AB4 A26 Source Sync lnput Output AE2 vss Power Other AB5 A24 Source Sync lnput Output AE3 TESTHI12 Power Other lnput AB6 A17 Source Sync Input Output AE4 RESERVED AB7 VSS Power Other AE5 VSS Power Other AB8 VCC Power Other AE6 RESERVED AB23 VSS Power Other AE7 VSS Power Other AB24 VSS Power Other AE8 SKTOCC Power Other Output AB25 VSS Power Other AE9 VCC Power Other AB26 VSS Power Other AE10 VSS Power Other AB27 VSS Power Other AE11 VCC Power Other AB28 VSS Power Other AE12 VCC Power Other AB29 VSS Power Other AE13 VSS Power Other AB30 VSS Power Other AE14 VCC Power Other AC1 TMS TAP Input AE15 VCC Power Other AC2 DBR Power Other Output AE16 VSS Power Other AC3 VSS Power Other AE17 VSS Power Other AC4 RESERVED AE18 VCC Power Other AC5 A25 Source Sync lnput Output AE19 VCC Power Other AC6 VSS Power Other AE20 VSS Power Other AC7 VSS Power Other AE21 VCC Power Other AC8 VCC Power Other AE22 VCC Power Other AC23 VCC Power Other AE23 VCC Power Other AC24 VCC Power Other AE24 VSS Power Other AC25 VCC Power Other AE25 VSS Power Other AC26 VCC Power Other AE26 VSS Power Other AC27 VCC Power Other AE27 VSS Power Other AC28 VCC Power Other AE28 VSS Power Other AC29 VCC Power Other AE29 VSS Power Othe
19. Signal Description Signal Definitions Sheet 3 of 11 Name Type Description Notes BPM5 BPM4 BPM3 BPM 2 1 BPMO 1 0 1 0 1 0 BPM 5 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 5 0 should connect the appropriate pins of all FSB agents BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a processor output used by debug tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processors BPM 5 4 must be bussed to all bus agents BPMb3 BPMb 2 1 BPMbO 1 0 1 0 BPMb 3 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPMb 3 0 should connect the appropriate pins of all FSB agents BPRI BPRI Bus Priority Request is used to arbitrate for ownership of the processor FSB It must connect the appropriate pins of all processor FSB agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing lo
20. The Extended HALT state must be enabled for the processor to remain within its specifications The Extended HALT state requires support for dynamic VID transitions in the platform 6 2 2 1 HALT State HALT is a low power state entered when the processor have executed the HALT or MWAIT instruction When one of the processor cores execute the HALT or MWAIT instruction that processor core is halted however the other processor continues normal operation The processor will transition to the Normal state upon the occurrence of SMI BINIT INIT LINT 1 0 NMI INTR or an interrupt delivered over the front side bus RESET will cause the processor to immediately initialize itself The return from a System Management Interrupt SMI handler can be to either Normal Mode or the HALT state See the Intel 64 and 1A 32 Architecture Software Developer s Manual 86 Datasheet Features 6 2 2 2 Table 6 2 6 2 3 Datasheet intel The system can generate a STPCLK while the processor is in the HALT state When the system deasserts STPCLK the processor will return execution to the HALT state While in HALT state the processor will process front side bus snoops and interrupts Extended HALT State Extended HALT state is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT state has been enabled via the BIOS When one of the processor cores executes the HALT instructio
21. Topology 82 intel Thermal Specifications PECI Host Controller G5 G5 Processor Socket 0 DomainO Ow xo Ow xo Domain1 Processor Socket 1 ox DomainO ox Domain1 Datasheet m Thermal Specifications n tel 5 3 1 1 Figure 5 5 5 3 1 2 Datasheet TcoNTROL and TCC Activation on PECI based Systems Fan speed control solutions based on PECI utilize a TcoNrRoL value stored in the processor A32 TEMPERATURE TARGET MSR The TcoNrRoL MSR uses the same offset temperature format as PECI though it contains no sign bit Thermal management devices should infer the TconTtroL Value as negative Thermal management algorithms should use the relative temperature value delivered over PECI in conjunction with the TcoNTROL MSR value to control or optimize fan speeds Figure 5 5 shows a conceptual fan control diagram using PECI temperatures The relative temperature value reported over PECI represents the data below the onset of thermal control circuit TCC activation as needed by PROCHOT assertions As the temperature approaches TCC activation the PECI value approaches zero TCC activates at a PECI count of zero Conceptual Fan Control Diagram of PECI based Platforms rt irtercbdltocbBoad adie irgderrertztioa Processor Thermal Data Sample Rate and Filtering The Digital Thermal Se
22. assembled together Refer to the LGA771 Socket Design Guidelines for complete details on the LGA771 socket The package components shown in Figure 3 1 include the following Integrated Heat Spreader IHS Thermal Interface Material TI M Processor Core die Package Substrate Landside capacitors Package Lands Figure 3 1 Processor Package Assembly Sketch IHS Core die TM Substrate ___ Package Lands iid aa Capacitors LGA771 Socket System Board NOTE This drawing is not to scale and is for reference only 3 1 Package Mechanical Drawings The package mechanical drawings are shown in Figure 3 2 through Figure 3 4 The drawings include dimensions necessary to design a thermal solution for the processor including Package reference and tolerance dimensions total height length width and so forth e IHS parallelism and tilt Land dimensions Top side and back side component keepout dimensions Reference datums Note All drawing dimensions are in mm in Datasheet 35 m n tel Mechanical Specifications Figure 3 2 Processor Package Drawing Sheet 1 of 3 3 MODEL ing NOTE Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and Mechanical Design Guidelines See Section 1 2 36 Datasheet Mech
23. designer to calculate the minimum values across the range of Vr 3 GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END is generated from V on the baseboard by a voltage divider of 1 resistors The minimum and maximum specifications account for this resistor tolerance The V referred to in these specifications is the instantaneous Vyr 4 Rrr is the on die termination resistance measured at Vo of the AGTL output driver Measured at 0 31 V m Rrr is connected to V on die 5 COMP resistance must be provided on the system board with 196 resistors Datasheet Electrical Specifications Table 2 19 FSB Differential BCLK Specifications ERRefclk diff Fall rates Symbol Parameter Min Typ Max Unit Figure Notes VL Input Low Voltage 0 150 0 0 0 150 V 2 5 Vu Input High Voltage 0 660 0 710 0 850 V 2 5 NE P Crossing 0 250 0 350 0 550 V 2 5 2 6 2 9 Relative Crossing 0 250 0 5 0 550 0 5 VCROSS rel Point Masse 0 700 MA hag 0 700 V 7 gt 26 38911 Range of Crossin Aueease saa 9 N A N A 0 140 V 2 5 2 6 Vos Overshoot N A N A 1 150 V 2 5 4 Vus Undershoot 0 300 N A N A V 2 5 5 VRBM Ringback Margin 0 200 N A N A V 2 5 6 VTR Threshold Region VCROSS 0 100 N A VCROSS 0 100 V 2 5 7 Input Leakage lu Current N A N A 100 uA 10 Differential Rising ERRefcIk diffRrise and falling edge 0 6 4 V ns 2 7 12 Datasheet NOTES
24. expired the TCC goes inactive and clock modulation ceases With thermal solutions designed to the processor Thermal Profile it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable Refer to the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 The duty cycle for the TCC when activated by the TM1 is factory configured and cannot be modified The TM1 does not require any additional hardware software drivers or interrupt handling routines Enhanced Thermal Monitor TM2 The processor adds supports for an Enhanced Thermal Monitor capability known as Thermal Monitor 2 TM2 This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor TM2 requires support for dynamic VID transitions in the platform When Thermal Monitor 2 is enabled and a high temperature situation is detected the Thermal Control Circuit TCC will be activated for both processor cores The TCC causes the processor to adjust its operating frequency via the bus multiplier and input voltage via the VID signals This combination of reduced frequency and VID results in a reduction to the processor power consumption A processor enabled for Thermal Monito
25. must be connected to the processor power plane while all Vss lands must be connected to the system ground plane The processor Vcc lands must be supplied with the voltage determined by the processor Voltage IDentification VID signals See Table 2 3 for VID definitions Twenty two lands are specified as V which provide termination for the FSB and provides power to the 1 0 buffers The platform must implement a separate supply for these lands which meets the V4 specifications outlined in Table 2 12 13 m n tel Electrical Specifications 2 3 1 2 3 2 2 3 3 14 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large average current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storage Cgyik such as electrolytic capacitors supply voltage during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as a storage well for current when entering an idle condition from a running condition Care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in Table 2 12 Failure to do so can result in timing violations or reduced lifetime of the component Vcc Decoupling Vcc regulator solutions n
26. not rely on software usage of this mechanism to limit the processor temperature If bit 4 of the 1A32_CLOCK_MODULATION MSR is set to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock modulation is programmable via bits 3 1 of the same IA32_CLOCK_MODULATION MSR In On Demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 5 on 12 5 off in 12 5 increments On Demand mode may be used in conjunction with the Thermal Monitor however if the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode PROCHOT Signal An external signal PROCHOT processor hot is asserted when the processor die temperature of any processor cores reaches its factory configured trip point If Thermal Monitor is enabled note that Thermal Monitor must be enabled for the processor to be operating within specification the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT Refer to the Intel 64 and IA 32 Architectures Software Developer s Manual for specific register and programming details Datasheet m Thermal Specifications n tel 5
27. on reset Power On Configuration Option Lands Configuration Option Land Name Notes Output tri state SMI 1 2 Execute BIST Built In Self Test A3 1 2 Disable MCERR observation A9 1 2 Disable BINIT observation A10 1 2 Symmetric agent arbitration ID BR 1 0 1 2 NOTES 1 Asserting this signal during RESET will select the corresponding option 2 Address lands not identified in this table as configuration options should not be asserted during RESET Disabling of any of the cores within the processor must be handled by configuring the EXT_CONFIG Model Specific Register MSR This MSR will allow for the disabling of a single core per die within the package Clock Control and Low Power States The processor supports the Extended HALT state also referred to as C1E in addition to the HALT state and Stop Grant state to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 6 1 for a visual representation of the processor low power states The Extended HALT state is a lower power state than the HALT state or Stop Grant state The Extended HALT state must be enabled via the BI OS for the processor to remain within its specifications For processors that are already running at the lowest bus to core frequency ratio for its nominal operating point the processor will transition to the HALT state instead of the Extended HALT state
28. 0 AP 1 0 BINIT BNR BPRI D 63 0 DBI 3 0 DBSY DEFER DP 3 0 DRDY DSTBN 3 0 DSTBP 3 0 HIT HITM LOCK MCERR REQ 4 0 RS 2 0 RSP TRDY BPM 5 0 BPMb 3 0 RESET BR 1 0 Table 2 8 Non AGTL Signal Description Table Signals with R77 Signals with no R77 FORCEPR PROCHOT 2 A20M BCLK 1 0 BSEL 2 0 COMP 3 0 FERR PBE GTLREF_ADD_MID GTLREF_ADD_END GTLREF DATA MID GTLREF DATA END IERR IGNNE INIT LINTO INTR LINT1 NMI LL ID 1 0 MS ID 1 0 PECI PWRGOOD SKTOCC SMI STPCLK TCK TDI TDO TESTHI 12 8 THERMTRIP TMS TRDY TRST VCC_DIE_SENSE VCC_DIE_SENSE2 VID 6 1 VID SELECT VSS_DIE_SENSE VSS DIE SENSE2 VIT SEL NOTES 1 These signals have Ry in the package with a 80 Q pullup to V7 2 These signals have Ry in the package with a 50 pullup to V Datasheet 21 m n tel Electrical Specifications Table 2 9 2 8 2 9 2 10 2 10 1 22 Signal Reference Voltages GTLREF CMOS A 37 3 ADS ADSTB 1 0 AP 1 0 BINIT BNR BPM 5 0 BPMb 3 0 BPRI BR 1 0 D 63 0 DBI 3 0 DBSY DEFER DP 3 0 DRDY DSTBN 3 0 DSTBP 3 0 FORCEPR HIT HITM LOCK MCERR RESET REQ 4 0 RS 2 0 RSP TRDY A20M LINTO INTR LINT1 NMI IGNNE INIT PWRGOOD SMI STPCLK TCK TDI TMS TRST CMOS Asynchronous and Open Drain Asynchronous Signals
29. 0 us of the assertion of PWRGOOD TMS TMS Test Mode Select is a JTAG specification support signal used by debug tools TRDY TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of all FSB agents TRST TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset VCCPLL The processor implements an on die PLL filter solution The VCCPLL input is used as a PLL supply voltage 73 intel Table 4 1 74 Land Listing and Signal Description Signal Definitions Sheet 11 of 11 Name Type Description Notes VCC_DIE_SENSE VCC_DIE_SENSE2 VCC DIE SENSE and VCC DIE SENSE2 provides an isolated low impedance connection to the processor core power and ground This signal should be connected to the voltage regulator feedback signal which insures the output voltage that is processor voltage remains within specification VID 6 1 VID 6 1 Voltage ID pins are used to support automatic selection of power supply voltages Vcc These are CMOS signals that are driven by the processor and must be pulled up through a resistor Conversely the voltage regulator output must be disabled prior to the voltage supply for these pins becomes invalid The VID pins are needed to support processor voltage specification va
30. 1 2 D dw 10 11 12 Unless otherwise noted all specifications in this table apply to all processor frequencies Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLKO is equal to the falling edge of BCLK1 VHavg is the statistical average of the Vy measured by the oscilloscope Overshoot is defined as the absolute value of the maximum voltage Undershoot is defined as the absolute value of the minimum voltage Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches It includes input threshold hysteresis The crossing point must meet the absolute and relative crossing point specifications simultaneously VHavg Can be measured directly using Vtop on Agilent and High on Tektronix oscilloscopes For VIN between O V and Vy AVcnoss is defined as the total variation of all crossing voltages as defined in note 3 Measured from 200 mV to 200 mV on the differential waveform derived from REFCLK minus REFCLK The signal must be monotonic through the measurement region for rise and fall time The 400 mV measurement window is centered on the differential zero crossing See Figure 2 7 33 m n tel Electrical Specifications Figure 2 5 Differential Clock Wavefor
31. 17 Land Name pos nn Direction Land Name po TL is Direction VCC AE9 Power Other VCC AJ15 Power Other VCC AF11 Power Other VCC AJ18 Power Other VCC AF12 Power Other VCC AJ19 Power Other VCC AF14 Power Other VCC AJ21 Power Other VCC AF15 Power Other VCC AJ22 Power Other VCC AF18 Power Other VCC AJ25 Power Other VCC AF19 Power Other VCC AJ26 Power Other VCC AF21 Power Other VCC AJ8 Power Other VCC AF22 Power Other VCC AJ9 Power Other VCC AF8 Power Other VCC AK11 Power Other VCC AF9 Power Other VCC AK12 Power Other VCC AG11 Power Other VCC AK14 Power Other VCC AG12 Power Other VCC AK15 Power Other VCC AG14 Power Other VCC AK18 Power Other VCC AG15 Power Other VCC AK19 Power Other VCC AG18 Power Other VCC AK21 Power Other VCC AG19 Power Other VCC AK22 Power Other VCC AG21 Power Other VCC AK25 Power Other VCC AG22 Power Other VCC AK26 Power Other VCC AG25 Power Other VCC AK8 Power Other VCC AG26 Power Other VCC AK9 Power Other VCC AG27 Power Other VCC AL11 Power Other VCC AG28 Power Other VCC AL12 Power Other VCC AG29 Power Other VCC AL14 Power Other VCC AG30 Power Other VCC AL15 Power Other VCC AG8 Power Other VCC AL18 Power Other VCC AG9 Power Other VCC AL19 Power Other VCC AH11 Power Other VCC AL21 Power Other VCC AH12 Power Other VCC AL22 Power Other VCC AH14 Power Other VCC AL25 Power Other VCC AH15 Power Other VCC AL26 Power Other VCC AH18 Power Other VCC AL29 Power Other VCC AH19 Power Other VCC AL30 Power Othe
32. 2 0 0 ieee ene nee eene 22 2 10PECI DC Electrical Limits ida rir maternel lee e ieee ped a s ier seda ie iene pce 23 2 11Processor Absolute Maximum Ratings 25 2 12Voltage and Current Specifications 26 2 13Processor VCC Static and Transient Tolerance cece cece aaa aaa teeter 28 2 14AGTL Signal Group DC Specifications sisi 29 2 15CMOS Signal Input Output Group and TAP Signal Group DE SpecIfiCAtION SE Mr 30 2 16Open Drain Output Signal Group DC Specifications 30 2 17VCC Overshoot Specifications seems 30 2 18AGTL Bus Voltage Definitions sise 32 2 19FSB Differential BCLK Specifications 33 3 1 Package Loading Specifications 39 3 2 Package Handling Guidelines ss 40 3 3 Processor Materlals ue iE ERR turp ee Ree EE rennes a TRE aa KMS nesters 40 4 1 Land Listing by Land Name aaa aa aaa aaa memes sese nne eminens esses 46 4 2 Land Listing by Land Number ao retten PA n ERR ECRIRE ETHER Aa 55 4 1 Signal Definitions x c Pee oca exe uh per ames cure i aaa EE eerie es E eeu Dolus 64 5 1 Processor Thermal Specifications sisi 76 5 2 Processor Thermal Profile Table sisi 77 5 3 GetTemp0 GetTemp1 Error Codes memes 84 6 1 Power On Configuration Option Lands cece memes eene 85 6 2 Extended HALT Maximum Power nemen e wana eee emen nennen nnne 87 4 Datasheet Revision History Revision Description Date 001 Initial release February 2008 Datasheet
33. 2 4 5 2 5 5 3 5 3 1 Datasheet PROCHOT is designed to assert at or a few degrees higher than maximum Tcase when dissipating TDP power and cannot be interpreted as an indication of processor case temperature This temperature delta accounts for processor package lifetime and manufacturing variations and attempts to ensure the Thermal Control Circuit is not activated below maximum Tcas_e when dissipating TDP power There is no defined or fixed correlation between the PROCHOT trip temperature or the case temperature Thermal solutions must be designed to the processor specifications and cannot be adjusted based on experimental measurements of Tcasr or PROCHOT FORCEPR Signal The FORCEPR force power reduction input can be used by the platform to cause the processor to activate the TCC If the Thermal Monitor is enabled the TCC will be activated upon the assertion of the FORCEPR signal Assertion of the FORCEPR signal will activate TCC for all processor cores The TCC will remain active until the system deasserts FORCEPR FORCEPR is an asynchronous input FORCEPR can be used to thermally protect other system components To use the VR as an example when FORCEPR is asserted the TCC circuit in the processor will activate reducing the current consumption of the processor and the corresponding temperature of the VR It should be noted that assertion of FORCEPR does not automatically assert PROCHOT As mentioned previously th
34. 4 and IA 32 Intel Software Developer s Manual Documentation Changes http www intel com products processor manuals Datasheet m Electrical Specifications n tel 2 2 1 2 2 Datasheet Electrical Specifications Front Side Bus and GTLREF Most processor FSB signals use Assisted Gunning Transceiver Logic AGTL signaling technology This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates AGTL buffers are open drain and require pull up resistors to provide the high logic level and termination AGTL output buffers differ from GTL buffers with the addition of an active PMOS pull up transistor to assist the pull up resistors during the first clock of a low to high voltage transition Platforms implement a termination voltage level for AGTL signals defined as Vr Because platforms implement separate power planes for each processor and chipset separate Vcc and Vm supplies are necessary This configuration allows for improved noise tolerance as processor frequency increases Speed enhancements to data and address buses have made signal integrity considerations and platform design methods even more critical than with previous processor families The AGTL inputs require reference voltages GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END which are used by the receivers to determine if a signal is a logical O or a logical 1
35. 8 htm The processor supports Intel Virtualization Technology for hardware assisted virtualization within the processor Intel Virtualization Technology is a set of hardware enhancements that can improve virtualization solutions Intel Virtualization Technology is used in conjunction with Virtual Machine Monitor software enabling multiple independent software environments inside a single platform Further details on Intel Virtualization Technology can be found at http developer intel com technology platform technology virtualization index htm i n tel i Introduction 1 1 10 The processor is intended for high performance server and workstation systems The processor supports a Dual Independent Bus DIB architecture with one processor on each bus up to two processor sockets in a system The DIB architecture provides improved performance by allowing increased FSB speeds and bandwidth The processor is packaged in an FC LGA Land Grid Array package with 771 lands for improved power delivery It uses a surface mount LGA771 socket that supports Direct Socket Loading DSL The Intel Core 2 Extreme processor QX9775 based platforms implement independent core voltage Vcc power planes for each processor FSB termination voltage V r is shared and must connect to all FSB agents The processor core voltage uses power delivery guidelines specified by VRM EVRD 11 0 and its associated load line see Voltage Regulator Module VRM and Enterpri
36. A15 Power Other veo BET Power Other VSS A18 Power Other VSS SPR Rowen Other VSS A2 Power Other VSS AF10 Power Other VSS A21 Power Other VSS AF13 Power Other vss A6 Power Other VSS AF16 Power Other VSS A9 Power Other VSS AF17 Power Other VSS AA23 Power Other 9m AF20 Power other VSS AA24 Power Other vee AF23 Power Other VSS AA25 Power Other vos aud Rewer Other VSS AA26 Power Other ve AF25 Power Other VSS AA27 Power Other yon a gt Rower Other VSS AA28 Power Other yes AF27 Power Other VSS AA29 Power Other vss AB Power Other VSS DAB Power Other VSS AF29 Power Other VSS AA30 Power Other yes AF3 Power Other VSS DAG Power Other VSS AF30 Power Other VSS AA7 Power Other Vos AD Power Other VSS ABI Power Other VSS AG10 Power Other VSS AB23 Power Other v55 AGIS Rewer Other VSS AB24 Power Other a AG16 Power Other VSS AB25 Power Other ue AGIT Power Other VSS AB26 Power Other vss AG20 Power Other VSS AB27 Power Other v55 AG23 Power Other VSS AB28 Power Other vee AG24 Power Other 51 52 Land Listing and Signal Description Table 4 1 Land Listing by Land Table 4 1 Land Listing by Land Name Sheet 13 of 17 Name Sheet 14 of 17 Land Name 2 M Direction Land Name gt AB Direction VSS AG7 Power Other VSS AL3 Power Other VSS AH1 Power Other VSS AM1 Power Other VSS
37. D 63 0 Signals Associated Strobes D 15 0 DBIO DSTBNO D 31 16 DBI1 DSTBN1 D 47 32 DBI2 DSTBN2 D 63 48 DBI3 DSTBN3 Data strobe used to latch in D 63 0 Signals Associated Strobes D 15 0 DBIO DSTBPO D 31 16 DBI1 DSTBP1 D 47 32 DBI2 DSTBP2 D 63 48 DBI3 DSTBP3 Datasheet Land Listing and Signal Description Table 4 1 Signal Definitions Sheet 6 of 11 intel Name Type Description Notes FERR PBE FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point error When STPCLK is not asserted FERR PBE is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state For additional information on the pending break event functionality including the identification of support of the feature and enable disable information refer to Vol 3 of the Intel 64 and IA 32 Architectures Software Develo
38. ERVED D14 TMS AC1 TAP Input RESERVED D16 TRDY E3 Common Clk lnput RESERVED El TRST AG1 TAP Input RESERVED E23 VCC AA8 Power Other RESERVED E24 VCC AB8 Power Other RESERVED E5 VCC AC23 Power Other RESERVED E6 VCC AC24 Power Other RESERVED E7 VCC AC25 Power Other RESERVED E29 VCC AC26 Power Other RESERVED F23 VCC AC27 Power Other RESERVED F29 VCC AC28 Power Other RESERVED F6 VCC AC29 Power Other RESERVED G6 VCC AC30 Power Other RESERVED J2 VCC AC8 Power Other RESERVED J3 VCC AD23 Power Other RESERVED N5 VCC AD24 Power Other RESERVED T2 VCC AD25 Power Other RESERVED Y1 VCC AD26 Power Other RESERVED Y3 VCC AD27 Power Other RESERVED AL1 VCC AD28 Power Other RESERVED AK1 VCC AD29 Power Other RESERVED G27 VCC AD30 Power Other RESERVED G26 VCC AD8 Power Other RESERVED G24 VCC AE11 Power Other RESERVED F24 VCC AE12 Power Other RESERVED F26 VCC AE14 Power Other RESERVED F25 VCC AE15 Power Other RESERVED G25 VCC AE18 Power Other RESERVED W3 VCC AE19 Power Other RESET G23 Common Clk Input VCC AE21 Power Other RSO B3 Common Clk Input VCC AE22 Power Other RS1 F5 Common Clk Input VCC AE23 Power Other Datasheet Land Listing and Signal Description Datasheet intel Table 4 1 Land Listing by Land Table 4 1 LandListing by Land Name Sheet 7 of 17 Name Sheet 8 of
39. IO A8 Source Sync Input Output REGI J5 Source Sync Input Output DBI1 G11 Source Sync Input Output REQ2 MB Source Sync Input Output DBI 23 D19 Source Sync Input Output REQ3 K6 Source Sync Input Output DBI3 C20 Source Sync Input Output REQ4 J6 Source Sync Input Output DBR AC2 Power Other Output RESERVED AMD DBSY B2 Common Clk Input Output RESERVED RU DEFER G7 Common Clk Input R SERVER A23 DPO J16 Common Clk lnput Output RESERVED Be DP1 H15 Common Clk Input Output RESERVED ACT 47 Land Listing and Signal Description intel 48 Table 4 1 Land Listing by Land Table 4 1 Land Listing by Land Name Sheet 5 of 17 Name Sheet 6 of 17 Land Name ro Tum Direction Land Name e EN TTE Direction RESERVED AE4 RS2 A3 Common Clk Input RESERVED AE6 RSP H4 Common Clk Input RESERVED AH2 SKTOCC AE8 Power Other Output RESERVED AH7 SMI P2 CMOS ASync Input RESERVED AJ3 STPCLK M3 CMOS ASync Input RESERVED AJ7 TCK AE1 TAP Input RESERVED AK3 TDI AD1 TAP Input RESERVED AM2 TDO AF1 TAP Output RESERVED AN5 TESTHI 10 P1 Power Other Input RESERVED AN6 TESTHI 11 L2 Power Other Input RESERVED B13 TESTHI 12 AE3 Power Other Input RESERVED B23 TESTIN1 w2 Power Other Input RESERVED C23 TESTIN2 U1 Power Other Input RESERVED D1 THERMTRIP M2 Open Drain Output RES
40. Intel Core 2 Extreme Processor QX9775 Datasheet February 2008 Document Number 319128 001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVI DED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DI SCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATI NG TO SALE AND OR USE OF INTEL PRODUCTS INCLUDI NG LIABILITY OR WARRANTI ES RELATI NG TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILI TY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RI GHT Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Core 2 Extreme processor QX9775 may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Alntel processor numbers are not a measure of performance Processor n
41. It is a relatively slow bending event compared to shock and vibration tests 8 Refer to the for information on heatsink clip load metrology Datasheet 39 m n tel Mechanical Specifications 3 4 Table 3 2 3 5 3 6 3 7 Table 3 3 40 Package Handling Guidelines Table 3 2 includes a list of guidelines on a package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Package Handling Guidelines Parameter Maximum Recommended Units Notes Shear ms 1 4 5 70 Ibf di Tensile da 5 2 4 5 25 Ibf os 3 95 N m T 3 4 5 IE 35 LBF in NOTES 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface 3 A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface 4 These guidelines are based on limited testing for design characterization and incidental applications one time only 5 Handling guidelines are for the package only and do not include the limits of the processor Socket Package Insertion Specifications The processor can be inserted and removed 15 times from an LGA771 socket which meets the criteria outlined in the LGA771 Socket Design Guidelines P
42. P1 DSTBN1 D 47 32 DBI2 DSTBP2 DSTBN2 D 63 48 DBI3 DSTBP3 DSTBN3 Synchronous to AGTL Strobes 1 0 ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 BCLK 1 0 Open Drain Output Asynchronous See IERRZ PROCHOT THERMTRIP CMOS Asynchronous Kevnehronmus A20M FORCEPRZ IGNNEZ INIT LINTO INTR Input y LINT1 NMI PWRGOOD SMI STPCLK CMOS Asynchronous Output Asynchronous BSEL 2 0 VID 6 1 FSB Clock Clock BCLK 1 0 Datasheet Electrical Specifications Table 2 6 FSB Signal Groups Sheet 2 of 2 Signal Group Type Signals TAP Input ae to TCK TDI TMS TRST Synchronous to TAP Output TCK TDO COMP 3 0 GTLREF ADD MID GTLREF ADD END GTLREF DATA MID GTLREF DATA END LL ID 1 0 MS ID 1 0 PECI RESERVED SKTOCC TESTIN1 TESTIN2 Pawel Mien POWE ONET TESTHI 12 10 Vec VCC_DIE_SENSE VCC DIE SENSE2 VCCPLL VID SELECT VSS DIE SENSE VSS DIE SENSE2 Vss Vm VIT OUT VIT SEL NOTES 1 Refer to Section 4 2 for signal descriptions 2 These signals may be driven simultaneously by multiple agents Wired OR Table 2 7 outlines the signals which include on die termination Rtr Table 2 8 outlines non AGTL signals including open drain signals Table 2 9 provides signal reference voltages Table 2 7 AGTL Signal Description Table AGTL signals with Rrr AGTL signals with no Rrr A 37 3 ADS ADSTB 1
43. Power Other VCC N27 Power Other VCC AN9 Power Other VCC N28 Power Other VCC J10 Power Other VCC N29 Power Other VCC J11 Power Other VCC N30 Power Other VCC J12 Power Other VCC N8 Power Other VCC J13 Power Other VCC P8 Power Other VCC j14 Power Other VCC R8 Power Other VCC J15 Power Other VCC T23 Power Other VCC J18 Power Other VCC T24 Power Other VCC j19 Power Other VCC T25 Power Other VCC J20 Power Other VCC T26 Power Other VCC J21 Power Other WCC T27 Power Other VCC J22 Power Other VCC T28 Power Other VCC J23 Power Other VCC T29 Power Other VCC J24 Power Other VCC T30 Power Other VCC J25 Power Other VCC T8 Power Other VCC J26 Power Other VCC U23 Power Other VCC J27 Power Other VCC U24 Power Other VCC J28 Power Other VCC U25 Power Other VCC J29 Power Other VCC U26 Power Other VCC J30 Power Other VCC U27 Power Other VCC J8 Power Other VCC U28 Power Other VCC J9 Power Other VCC U29 Power Other VCC K23 Power Other VCC u30 Power Other VCC K24 Power Other VCC U8 Power Other VCC K25 Power Other VCC V8 Power Other VCC K26 Power Other VCC W23 Power Other VCC K27 Power Other VCC W24 Power Other VCC K28 Power Other VCC W25 Power Other VCC K29 Power Other VCC W26 Power Other VCC K30 Power Other VCC W27 Power Other VCC K8 Power Other VCC W28 Power Other VCC L8 Power Other VCC W29 Power Other VCC M23 Power Other VCC w30 Power Other Datasheet Land Listing and Signal Description Dat
44. Processor Package Assembly Sketch issues 35 3 2 Processor Package Drawing Sheet 1 of 3 36 3 3 Processor Package Drawing Sheet 2 Of 3 37 3 4 Processor Package Drawing Sheet 3 of 3 38 3 5 Processor Top side Markings Example aaa ea aaa aaa aaa aaa aaa meme nn 41 3 6 Processor Land Coordinates Top View 42 3 7 Processor Land Coordinates Bottom View 43 5 1 Processor Thermal Profile scr e PA AAA cbr AWA AE KP YR WAW P SONA 76 5 2 Case Temperature TCASE Measurement Location 78 5 3 Thermal Monitor 2 Frequency and Voltage Ordering e eueaa aaa aaa aaa aaa aaa ann eee eae 80 5 4 Processor PECI Topology ueeeeeeae aaa i Prinia PUNEET EE EEE NEE EEIE DRENTSE EEN EEEREN SE 82 5 5 Conceptual Fan Control Diagram of PECI based Platforms cccccceeeeeeee eee eeeeeeeeeeteeenaes 83 6 1 Stop Clock State Machine 2 0 eet eene nn nnn 86 Tables 2 1 Core Frequency to FSB Multiplier Configuration 15 2 2 BSEL 2 0 Frequency Table cece aaa erence mener mener nnne nnns 16 2 3 Voltage Identification Definition ss 18 2 4 Loadline Selection Truth Table for LL ID 1 0 19 2 5 Market Segment Selection Truth Table for MS ID 1 0 seem IHR 19 2 6 FSB Signal Groups roc redes reo ertet A Fees r e etes RA A besos es ered yi d bene Edna 20 2 7 AGTL Signal Description Table ss 21 2 8 Non AGTL Signal Description Table sis 21 2 9 Signal Reference Voltages
45. SS Power Other E28 VSS Power Other D13 D25 Source Sync Input Output E29 RESERVED D14 RESERVED E30 VIT Power Other D15 VSS Power Other F1 VSS Power Other D16 RESERVED F2 Mp Power Other lnput D17 D49 Source Sync Input Output D18 VSS Power Other r4 Mam ees D19 DBI 2s Source Sync lnput Output gt Role Common Cik Input D20 D48 Source Sync lnput Output T6 RESERVED D21 VSS Power Other F7 V33 Fower Other D22 D46 Source Sync lnput Output F8 BRR Source Sync Input Output D23 VCCPLL Power Other Input F9 D18 Source Sync lnput Output D24 vss Power Other F10 VSS Power Other D25 VIT Power Other F11 D23 Source Sync _ Input Output D26 VIT Power Other F12 D24 Source Sync _ Input Output D27 VIT Power Other F13 VSS Power Other D28 VIT Power Other F14 D28 Source Sync Input Output D29 VIT Power Other F15 D30 Source Sync _ Input Output D30 VIT Power Other F16 VSS Power Other El RESERVED Power Other F17 D37 Source Sync _ Input Output E2 vss Power Other F18 D38 Source Sync _ Input Output E3 TRDY Common Clk Input F19 VSS Power Other EA HITM Common Cik Input Output F20 D41 Source Sync _ Input Output E5 RESERVED F21 D43 Source Sync _ Input Output E6 RESERVED F22 vss Power Other E7 RESERVED F23 RESERVED E8 VSS Power Other 2 RESERVED E9 D19 Source Sync lnput Output F25 RESERVED E10 D21 Source Sync lnput Output F26 RESERVED Ell VSS Power Other F27 VTT_SEL Power Other Output E12 DSTBP1 Source Sync l
46. VID to the original value and then change the bus to core frequency ratio back to the original value Stop Grant State When the STPCLK pin is asserted the Stop Grant state of the processor is entered no later than 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle By default the processor will issue two Stop Grant Acknowledge special bus cycles one for each die Once the STPCLK pin has been asserted it may only be deasserted once the processor is in the Stop Grant state All processor cores will enter the Stop Grant state once the STPCLK pin is asserted Additionally all processor cores must be in the Stop Grant state before the de assertion of STPCLK Since the AGTL signal pins receive power from the front side bus these pins should not be driven allowing the level to return to Vr for minimum power drawn by the termination resistors in this state In addition all other input pins on the front side bus should be driven to the inactive state BINIT will not be serviced while the processor is in Stop Grant state The event will be latched and can be serviced by software upon exit from the Stop Grant state 87 intel PR 6 2 4 6 2 4 1 6 2 4 2 88 RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the de assertion of the STPCLK signal A transitio
47. VSS Power Other J30 VCC Power Other H15 DP1 Common Clk Input Output K1 LINTO CMOS Async lnput H16 DP2 Common Clk Input Output K2 vss Power Other H17 VSS Power Other K3 A20M CMOS Async lnput H18 VSS Power Other K4 REQO Source Sync lnput Output H19 VSS Power Other K5 VSS Power Other H20 VSS Power Other K6 REQ3 Source Sync Input Output H21 VSS Power Other K7 VSS Power Other H22 VSS Power Other K8 VCC Power Other 57 58 intel Land Listing and Signal Description Table 4 2 Land Listing by Land Table 4 2 Land Listing by Land Number Sheet 7 of 17 Number Sheet 8 of 17 ily Pin Name Tu dem Direction he Pin Name Rus Direction K23 VCC Power Other N7 VSS Power Other K24 VCC Power Other N8 VCC Power Other K25 VCC Power Other N23 VCC Power Other K26 VCC Power Other N24 VCC Power Other K27 VCC Power Other N25 VCC Power Other K28 VCC Power Other N26 VCC Power Other K29 VCC Power Other N27 VCC Power Other K30 VCC Power Other N28 VCC Power Other La LINT1 CMOS Async lnput N29 VCC Power Other L2 TESTHI11 Power Other Input N30 VCC Power Other L3 VSS Power Other P1 TESTHI10 Power Other Input LA A06 Source Sync Input Output P2 SMI CMOS Async Input L5 AO5 Source Sync Input Output P3 INIT CMOS Async Input L6 VSS Power Other P4 VSS Power Oth
48. ance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor t Not all specified units of this processor support Enhanced Intel SpeedStep Technology See the Processor Spec Finder at http processorfinder intel com or contact your Intel representative for more information Not all specified units of this processor support Thermal Monitor 2 Enhanced HALT State and Enhanced Intel SpeedStep Technology See the Processor Spec Finder at http processorfinder intel com or contact your Intel representative for more information Warning Altering clock frequency and or voltage may i reduce system stability and useful life of the system and processor ii cause the processor and other system components to fail iii cause reductions in system performance iv cause additional heat or other damage and v affect system data integrity Intel has not tested and does not warranty the operation of the processor beyond its specifications Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Intel Pentium Core speedStep and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright O 2008 Intel Corporati
49. anical Specifications Figure 3 3 Processor Package Drawing Sheet 2 of 3 v 1 ee ee ni 7 A EP _ L E CIE 7 p 0 i s e Datasheet Figure 3 4 Processor Package Drawing Sheet 3 of 3 Mechanical Specifications 38 ES D 2206 MISSION COLLEGE BLY i pa 50 ROK S818 Datasheet m Mechanical Specifications n tel 3 2 Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements Decoupling capacitors are typically mounted to either the topside or landside of the package substrate See Figure 3 4 for keepout zones 3 3 Package Loading Specifications Table 3 1 provides dynamic and static load specifications for the processor package These mechanical load limits should not be exceeded during heatsink assembly mechanical stress testing or standard drop and shipping conditions The heatsink attach solutions must not include continuous stress onto the processor with the exception of a uniform load to maintain the heatsink to processor thermal interface Also any mechanical system or component testing should not exceed these limits The processor package substrate should not be used as a mechanical reference or load bearing surface for thermal or mechanical soluti
50. apacitance per node N A 10 pF 3 Signal noise immunity above 300 Vabe EE y 0 1 Var N A Ve NOTE 1 V supplies the PECI interface PECI behavior does not affect V7 min max specifications 2 The leakage specification applies to powered devices on the PECI bus 3 One node is counted for each client and one node for the system host Extended trace lengths might appear as additional nodes 2 10 2 I nput Device Hysteresis The input buffers in both client and host models must use a Schmitt triggered input design for improved noise immunity Use Figure 2 1 as a guide for input buffer design Figure 2 1 Input Device Hysteresis Vn Maximum Vp Minimum Vp a Valid Input Signal Range Maximum Vy Minimum Vy PECI Ground Minimum Hysteresis Datasheet 23 m n tel Electrical Specifications 2 11 Note 2 12 24 Mixing Processors Intel supports and validates dual processor configurations only in which both processors operate with the same FSB frequency core frequency power segments and have the same internal cache sizes Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel Combining processors from different power segments is also not supported Processors within a system must operate at the same frequency per bits 12 8 of the CLOCK_FLEX_MAX MSR however this does not app
51. as the core frequency of the processor As in previous processor generations the processor core frequency is a multiple of the BCLK 1 0 frequency The processor bus ratio multiplier is set during manufacturing The default setting is for the maximum speed of the processor It is possible to override this setting using software see the Intel 64 and IA 32 Architectures Software Developer s Manual This permits operation at lower frequencies than the processor s tested frequency The processor core frequency is configured during reset by using values stored internally during manufacturing The stored value sets the highest bus fraction at which the particular processor can operate If lower speeds are desired the appropriate ratio can be configured via the CLOCK FLEX MAX MSR For details of operation at core frequencies lower than the maximum rated processor speed refer to the Intel 64 and 1A 32 Architectures Software Developer s Manual Clock multiplying within the processor is provided by the internal phase locked loop PLL which requires a constant frequency BCLK 1 0 input with exceptions for spread spectrum clocking Processor DC specifications for the BCLK 1 0 inputs are provided in Table 2 19 These specifications must be met while also meeting signal integrity requirements as outlined in Table 2 19 The processor uses differential clocks Table 2 1 contains processor core frequency to FSB multipliers and their corresponding core freq
52. asheet intel Table 4 1 Land Listing by Land Table 4 1 Land Listing by Land Name Sheet 11 of 17 Name Sheet 12 of 17 Land Name pons Bone dune Direction Land Name pone ae Direction VCC we Power Other VSS AB29 Power Other VCC Y23 Power Other VSS AB30 Power Other VCC Y24 Power Other VSS AB7 Power Other VCC Y25 Power Other VSS AC3 Power Other VCC Y26 Power Other VSS AC6 Power Other VCC Y27 Power Other VSS AC7 Power Other VCC Y28 Power Other VSS AD4 Power Other VCC Y29 Power Other VSS AD7 Power Other VCC Y30 Power Other VSS AE10 Power Other VCC Y8 Power Other VSS AE13 Power Other NE E_SE AN3 Power Other Output VSS AE16 Power Other VSS AE17 Power Other ea ELSE AL8 Power Other Output VSS AE2 Power Other VCCPLL D23 Power Other lnput gt AE2O mower Other VID SELECT AN7 Power Other Output VER AE24 Power Other VIDI ALS CMOS Async Output VSS AE25 joe other VID2 AM3 CMOS Async Output gt gt nee Power Ether VI D3 AL6 CMOS Async Output gt SSE POWIE Other VID4 AK4 CMOS Async Output gt Fr Power Other VI D5 AL4 CMOS Async Output hiis DEUM jj ERE Other VID6 AM5 CMOS Async Output iia AE30 _ Power Other VSS A12 Power Other VSS PET power Other VSS
53. c lnput Output H29 VSS Power Other G15 D31 Source Sync lnput Output H30 BSELI CMOS Async Output G16 D32 Source Sync lnput Output JI VIT OUT Power Other Output G17 D36 Source Sync lnput Output J2 RESERVED G18 D35 Source Sync lnput Output J3 RESERVED G19 DSTBP2 Source Sync Input Output J4 VSS Power Other G20 DSTBN2 Source Sync Input Output J5 REQI Source Sync Input Output G21 D44 Source Sync lnput Output J6 REQ4 Source Sync Input Output G22 D47 Source Sync lnput Output J7 VSS Power Other G23 RESET Common Clk Input J8 VCC Power Other G24 RESERVED J9 VCC Power Other G25 _ RESERVED Jio vcc Power Other G26 RESERVED Jii vcc Power Other G27 BESERVED Ji2 vcc Power Other G28 BeDRI Clk Input J13 vec Power Other G29 BSELO CMOS Async Output J14 VCC Power Other G30 BSEL2 CMOS Async Output J15 VCC Power Other H1 ST PERDATA Power Other lnput J16 DPO Common Clk Input Output 17 DP3 Common Clk Input Output GTLREF_DATA J H2 _MID 7 Power Other Wnpur Ji8 vcc Power Other H3 VSS Power Other j19 VCC Power Other HA RSP Common Clk Input J20 VCC Power Other H5 BR1 Common Clk Input J21 VCC Power Other H6 VSS Power Other J22 VCC Power Other H7 VSS Power Other 123 VCC Power Other H8 VSS Power Other J24 VCC Power Other H9 vss Power Other 125 VCC Power Other H10 VSS Power Other J26 VCC Power Other H11 VSS Power Other 127 VCC Power Other H12 VSS Power Other J28 VCC Power Other H13 VSS Power Other J29 VCC Power Other H14
54. cc and lec combination wherein Vcc exceeds Vcc max at specified Icc Refer to the loadline specifications in Section 2 13 E Thermal Design Power TDP should be used for the processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease These specifications are based on silicon characterization Power specifications are defined at all VIDs found in Table 2 3 The processor may be shipped under multiple VIDs for each frequency The processor s intended for dual processor workstations only Figure 5 1 Processor Thermal Profile Thermal Profile 2U 754 70 65 4 60 4 S ad E 50 4 Thermal Profile 45 Y 0 187 x 35 40 4 35 O 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Power W NOTES 1 Refer to Table 5 2 for discrete points that constitute the thermal profile 2 Implementation of the processor Thermal Profile should result in virtually no TCC 76 activation Furthermore utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss Refer to the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 for system and environmental implementation details Datasheet Thermal Specifications Table 5 2 5 1 2 Datasheet Processor Thermal Profile Table intel
55. cked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI BR 1 0 1 0 The BR 1 0 signals are sampled on the active to inactive transition of RESET The signal which the agent samples asserted determines its agent ID BRO drives the BREQO signal in the system and is used by the processor to request the bus These signals do not have on die termination and must be terminated BSEL 2 0 The BCLK 1 0 frequency select signals BSEL 2 0 are used to select the processor input clock frequency Table 2 2 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processors chipset and clock synthesizer All FSB agents must operate at the same frequency COMP 3 0 COMP 3 0 must be terminated to VSS on the baseboard using precision resistors These inputs configure the AGTL drivers of the processor Datasheet Land Listing and Signal Description Table 4 1 Datasheet Signal Definitions Sheet 4 of 11 intel Name Type Description Notes D 63 0 1 0 D 63 0 Data are the data signals These signals provide a 64 bit data path between the processor FSB agents and must connect the appropriate pins on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are q
56. current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the deassertion of RESET the processor will tri state its outputs See Section 6 1 STPCLK STPCLK Stop Clock when asserted causes processors to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the FSB and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input 72 Datasheet Table 4 1 Land Listing and Signal Description Signal Definitions Sheet 10 of 11 intel Name Type Description Notes TCK TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for JTAG specification support TDO TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for J TAG specification support TESTHI 12 10 TESTHI 12 10
57. e BINIT driver is enabled during power on configuration BINIT is asserted to signal any bus condition that prevents reliable future operation If BINIT observation is enabled during power on configuration see Section 6 1 and BINIT is sampled asserted symmetric agents reset their bus LOCK activity and bus request arbitration state machines The bus agents do not reset their 1 0 Queue IOQ and transaction tracking state machines upon observation of BINIT assertion Once the BINIT assertion has been observed the bus agents will re arbitrate for the FSB and attempt completion of their bus queue and I OQ entries If BINIT observation is disabled during power on configuration a priority agent may handle an assertion of BINIT as appropriate to the error handling architecture of the system BNR 1 0 BNR Block Next Request is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Since multiple agents might need to request a bus stall at the same time BNR is a wired OR signal which must connect the appropriate pins of all processor FSB agents In order to avoid wired OR glitches associated with simultaneous edge transitions driven by multiple drivers BNR is activated on specific clock edges and sampled on specific clock edges Datasheet 65 intel Table 4 1 66 Land Listing and
58. e PROCHOT signal is asserted when a high temperature situation is detected A minimum pulse width of 500 us is recommended when FORCEPR is asserted by the system Sustained activation of the FORCEPR signal may cause noticeable platform performance degradation THERMTRI P Signal Regardless of whether or not Thermal Monitor 1 or Thermal Monitor 2 is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature refer to the THERMTRIP definition in Section 4 2 At this point the FSB signal THERMTRI P will go active and stay active as described in Section 4 2 THERMTRIP activation is independent of processor activity and does not generate any bus cycles Intel also recommends the removal of V Platform Environment Control Interface PECI I ntroduction PECI offers an interface for thermal monitoring of Intel processor and chipset components It uses a single wire thus alleviating routing congestion issues Figure 5 4 shows an example of the PECI topology in a system with the Intel Core 2 Extreme processor QX9775 PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices Also data transfer speeds across the PECI interface are negotiable within a wide range 2 Kbps to 2 Mbps The PECI interface on the processor is disabled by default and must be enabled through BIOS 81 Figure 5 4 Processor PECI
59. e Sync lnput Output C23 RESERVED B8 VSS Power Other C24 VSS Power Other B9 DSTBPO Source Sync lnput Output C25 VTT Power Other B10 D10 Source Sync lnput Output C26 VIT Power Other B11 VSS Power Other C27 VIT Power Other B12 D13 Source Sync lnput Output C28 VIT Power Other B13 RESERVED C29 VIT Power Other B14 VSS Power Other C30 VIT Power Other B15 D53 Source Sync lnput Output D1 RESERVED B16 D55 Source Sync lnput Output D2 ADS Common Clk Input Output B17 VSS Power Other D3 VSS Power Other B18 D57 Source Sync lnput Output D4 HIT Common Clk Input Output B19 D60 Source Sync lnput Output D5 VSS Power Other B20 VSS Power Other D6 VSS Power Other B21 D59 Source Sync lnput Output D7 D20 Source Sync lnput Output 55 56 intel Land Listing and Signal Description Table 4 2 Land Listing by Land Table 4 2 Land Listing by Land Number Sheet 3 of 17 Number Sheet 4 of 17 ig Pin Name A Z Direction eg Pin Name Bo us Direction D8 D12 Source Sync Input Output E24 RESERVED D9 VSS Power Other E25 VSS Power Other D10 D22 Source Sync lnput Output E26 VSS Power Other D11 D15 Source Sync Input Output E27 vss Power Other D12 V
60. e on the VID signals and the processor shifts to the new frequency Note that the top frequency for the processor can not be exceeded f the target frequency is lower than the current frequency the processor shifts to the new frequency and Vcc is then decremented in steps 12 5 mV by changing the target VID through the VID signals 89 90 Features Datasheet
61. ecification applies to the VCCPLL land Baseboard bandwidth is limited to 20 MHz lec tpc is the sustained DC equivalent current that the processor is capable of drawing indefinitely and should be used for the voltage regulator temperature assessment The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion The processor is capable of drawing lec roc indefinitely Refer to Figure 2 1 for further details on the average processor current draw over various time durations This parameter is based on design characterization and is not tested This is the maximum total current drawn from the V plane by only one processor with Ry enabled This specification does not include the current coming from on board termination Rx through the signal line Refer to the Voltage Regulator Design Guidelines to determine the total I drawn by the system This parameter is based on design characterization and is not tested lee vit our IS Specified at 1 1 V Icc reset is specified while PWRGOOD and RESET are asserted The processor is intended for dual processor workstations only Figure 2 2 Processor Load Current versus Time 160 _ 155 T wo c o 145 6 140 D 135 E S 130 o a 125 120 0 01 0 1 1 10 100 1000 Time Duration s NOTES 1 Processor or Voltage Regulator thermal protection circuitry should not trip for load curren
62. eed to provide bulk capacitance with a low Effective Series Resistance ESR and the baseboard designer must assure a low interconnect resistance from the regulator EVRD or VRM pins to the LGA771 socket Bulk decoupling must be provided on the baseboard to handle large voltage swings The power delivery solution must insure the voltage and current specifications are met as defined in Table 2 12 Vr Decoupling Bulk decoupling must be provided on the baseboard Decoupling solutions must be sized to meet the expected load To insure optimal performance various factors associated with the power delivery solution must be considered including regulator type power plane and trace sizing and component placement A conservative decoupling solution consists of a combination of low ESR bulk capacitors and high frequency ceramic capacitors Front Side Bus AGTL Decoupling The processor integrates signal termination on the die as well as a portion of the required high frequency decoupling capacitance on the processor package However additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the FSB Bulk decoupling must also be provided by the baseboard for proper AGTL bus operation Datasheet m Electrical Specifications n tel 2 4 Table 2 1 Datasheet Front Side Bus Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the FSB interface speed as well
63. er L7 VSS Power Other P5 A37 Source Sync Input Output L8 VCC Power Other P6 A04 Source Sync Input Output L23 VSS Power Other P7 VSS Power Other L24 VSS Power Other P8 VCC Power Other L25 VSS Power Other P23 VSS Power Other L26 VSS Power Other P24 VSS Power Other L27 VSS Power Other P25 VSS Power Other L28 VSS Power Other P26 VSS Power Other L29 VSS Power Other P27 VSS Power Other L30 VSS Power Other P28 VSS Power Other M1 VSS Power Other P29 VSS Power Other M2 THERMTRIP Open Drain Output P30 vss Power Other M3 STPCLK CMOS Async lnput R1 COMP3 Power Other Input MA AO7 Source Sync lnput Output R2 VSS Power Other M5 A03 Source Sync lnput Output R3 FERR PBE Open Drain Output M6 REQ2 Source Sync Input Output R4 A08 Source Sync Input Output M7 VSS Power Other R5 VSS Power Other M8 VCC Power Other R6 ADSTBO Source Sync Input Output M23 VCC Power Other R7 VSS Power Other M24 VCC Power Other R8 VCC Power Other M25 VCC Power Other R23 VSS Power Other M26 VCC Power Other R24 VSS Power Other M27 VCC Power Other R25 VSS Power Other M28 VCC Power Other R26 VSS Power Other M29 VCC Power Other R27 VSS Power Other M30 VCC Power Other R28 VSS Power Other N1 PWRGOOD Power Other lnput R29 VSS Power Other N2 IGNNE CMOS Async Input R30 VSS Power Other N3 VSS Power Other T1 COMP1 Power Other lnput N4 A36 Source Sync lnput Output T2 RESERVED N5 RESERVED T3 VSS Power Other N6 VSS Power Other T4 All Sou
64. er AF23 VSS Power Other AH9 VCC Power Other AF24 VSS Power Other AH10 VSS Power Other AF25 VSS Power Other AH11 vCC Power Other AF26 VSS Power Other AH12 VCC Power Other AF27 VSS Power Other AH13 VSS Power Other AF28 VSS Power Other AH14 VCC Power Other AF29 VSS Power Other AH15 VCC Power Other AF30 VSS Power Other AH16 VSS Power Other AG1 TRST TAP Input AH17 VSS Power Other AG2 BPM3 Common Clk Input Output AH18 VCC Power Other AG3 BPM5 Common Clk Input Output AH19 VCC Power Other AG4 A30 Source Sync lnput Output AH20 VSS Power Other AG5 A31 Source Sync lnput Output AH21 VCC Power Other AG6 A29 Source Sync lnput Output AH22 VCC Power Other AG7 VSS Power Other AH23 VSS Power Other AG8 VCC Power Other AH24 VSS Power Other AG9 VCC Power Other AH25 VCC Power Other AG10 VSS Power Other AH26 VCC Power Other AG11 VCC Power Other AH27 VCC Power Other AG12 VCC Power Other AH28 VCC Power Other AG13 VSS Power Other AH29 VCC Power Other AG14 VCC Power Other AH30 VCC Power Other AG15 VCC Power Other AJ1 BPM1 Common Clk Output AG16 VSS Power Other AJ2 BPMO Common Clk Input Output AG17 VSS Power Other AJ3 RESERVED AG18 VCC Power Other AJ4 VSS Power Other AG19 vCC Power Other AJ5 A34 Source Sync lnput Output AG20 VSS Power Other AJ6 A35 Source Sync Input Output AG21 VCC Power Other AJ7 RESERVED AG22 VCC Power Other AJ8 VCC Power Other AG23 VSS Power Other AJ9 VCC Power Other AG24 VSS Power Ot
65. er VSS v30 Power Other VSS V6 Power Other VSS V7 Power Other VSS W4 Power Other VSS W7 Power Other VSS Y2 Power Other VSS Y5 Power Other VSS Y7 Power Other oe AN4 Power Other Output co AL7 Power Other Output VTT A25 Power Other VTT A26 Power Other VTT B25 Power Other VTT B26 Power Other VTT B27 Power Other VTT B28 Power Other VTT B29 Power Other VIT B30 Power Other VIT C25 Power Other VIT C26 Power Other VIT C27 Power Other VIT C28 Power Other VIT C29 Power Other VIT C30 Power Other VIT D25 Power Other VIT D26 Power Other VIT D27 Power Other VIT D28 Power Other VIT D29 Power Other VIT D30 Power Other VIT E30 Power Other VIT F30 Power Other VIT OUT AA1 Power Other Output VTT_OUT jl Power Other Output VTT_SEL F27 Power Other Output Land Listing and Signal Description Datasheet Land Listing and Signal Description Datasheet intel Table 4 2 Land Listing by Land Table 4 2 Land Listing by Land Number Sheet 1 of 17 Number Sheet 2 of 17 he Pin Name ne o Direction E Pin Name im d Direction A2 VSS Power Other B22 D63 Source Sync lnput Output A3 RS2 Common Clk Input B23 RESERVED A4 DO2 Source Sync lnput Output B24 VSS Power Other A5 DO4 Source Sync lnput Output B25 VTT Power Other A6 VSS Power Other B26 VTT Power Othe
66. et If a debug port connector is implemented in the system DBR is a no connect on the processor package DBR is not a processor signal 67 intel Table 4 1 68 Land Listing and Signal Description Signal Definitions Sheet 5 of 11 Name Type Description Notes DBSY 1 0 DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on all processor FSB agents DEFER DEFER is asserted by an agent to indicate that a transaction cannot be ensured in order completion Assertion of DEFER is normally the responsibility of the addressed memory or I O agent This signal must connect the appropriate pins of all processor FSB agents DP 3 0 DRDY 1 0 1 0 DP 3 0 Data Parity provide parity protection for the D 63 0 signals They are driven by the agent responsible for driving D 63 0 and must connect the appropriate pins of all processor FSB agents DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of all processor FSB agents DSTBN 3 0 DSTBP 3 0 1 0 1 0 Data strobe used to latch in
67. eter Min Typ Max Units Notes VIL Input Low Voltage 0 10 0 00 0 3 Vr V 2 6 Vin Input High Voltage 0 7 Vrr Vit Vq 0 1 V 2 VoL Output Low Voltage 0 10 0 0 1 Vir V 2 Vou Output High Voltage 0 9 V r Vit Vrr 0 1 V 2 lo Output Low Current 1 70 N A 4 70 mA 3 loH Output High Current 1 70 N A 4 70 mA 4 lu Input Leakage Current N A N A 100 uA 5 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The Vm referred to in these specifications refers to instantaneous Vr 3 Measured at 0 1 V 4 Measured at 0 9 Vr 5 For Vin between 0 V and Vr Measured when the driver is tristated Open Drain Output Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes VoL Output Low Voltage 0 N A 0 20 Vir V Vou Output High Voltage 0 95 Vir Vit 1 05 Vr V lot Output Low Current 16 N A 50 mA lio Leakage Current N A N A x 200 uA 4 NOTES l Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Measured at 0 2 V 3 Von is determined by value of the external pullup resistor to Vy 4 For Vin between 0 V and Voy Vcc Overshoot Specification The processor can tolerate short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos max Vos max is the maximum allowable overshoot above VID The
68. f time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Datasheet Electrical Specifications Table 2 11 Processor Absolute Maximum Ratings 2 13 Datasheet Symbol Parameter Min Max Unit Notes 2 Vcc Core voltage with respect to Vss 0 30 1 35 V Vit FSB termination voltage with respect to Vss 0 30 1 45 V See See S TCASE Processor case temperature Chapter 5 Chapter 5 c Tsrorace Storage temperature 40 85 C 3 4 5 NOTES 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 3 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation please refer to the processor case temperature specifications 4 This rating applies to the processor and does not include any tray or packaging 5 Failure to adhere to this
69. g the voltage transition Operation at the lower voltage reduces the power consumption of the processor A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the operating frequency and 79 m n tel Thermal Specifications Figure 5 3 5 2 2 5 2 3 80 voltage transition back to the normal system operating point Transition of the VID code will occur first in order to insure proper operation once the processor reaches its normal operating frequency Refer to Figure 5 3 for an illustration of this ordering Thermal Monitor 2 Frequency and Voltage Ordering Tru Temperature Frequency Vcc Time 1 T hysterisis The PROCHOT signal is asserted when a high temperature situation is detected regardless of whether Thermal Monitor 1 or Thermal Monitor 2 is enabled On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Thermal Monitor 1 and Thermal Monitor 2 features On Demand mode is intended as a means to reduce system level power consumption Systems using the processor must
70. heir specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation REQ 4 0 1 0 REQ 4 0 Request Command must connect the appropriate pins of all processor FSB agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB 1 0 Refer to the AP 1 0 signal description for details on parity checking of these signals 71 intel Land Listing and Signal Description Table 4 1 Signal Definitions Sheet 9 of 11 Name Type Description Notes RESET Asserting the RESET signal resets all processors to known states and invalidates their internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least 1 ms after Vcc and BCLK have reached their proper specifications On observing active RESET all FSB agents will deassert their outpu
71. her AJ10 VSS Power Other AG25 VCC Power Other AJ11 VCC Power Other AG26 VCC Power Other AJ12 VCC Power Other AG27 VCC Power Other AJ13 VSS Power Other AG28 VCC Power Other AJ14 VCC Power Other AG29 VCC Power Other AJ15 VCC Power Other AG30 VCC Power Other AJ16 VSS Power Other Datasheet 61 62 Land Listing and Signal Description Table 4 2 Land Listing by Land Table 4 2 Land Listing by Land Number Sheet 15 of Number Sheet 16 of us Pin Name Tuc m Direction he Pin Name kos Direction AJ17 VSS Power Other AL3 VSS Power Other AJ 18 VCC Power Other AL4 VID5 CMOS Async Output AJ19 VCC Power Other AL5 VID1 CMOS Async Output AJ20 VSS Power Other AL6 VID3 CMOS Async Output AJ21 VCC Power Other ALT ene S Power Other AJ 22 VCC Power Other AJ 23 VSS Power Other AL8 SENS py Power Other AJ24 VSS Power Other AL9 VCC Power Other AJ25 VCC Power Other AL10 vss Power Other AJ26 VCC Power Other AL11 VCC Power Other AJ27 VSS Power Other AL12 vcc Power Other AJ 28 VSS Power Other AL13 VSS Power Other AJ29 VSS Power Other AL14 VCC Power Other AJ30 VSS Power Other AL15 VCC Power Other AK1 RESERVED AL16 VSS Power Other AK2 VSS Power Other AL17 VSS Power Other AK3 RESERVED
72. ion the processor enters the HALT Grant Snoop state The processor will stay in this state until the snoop on the front side bus has been serviced whether by the processor or another agent on the front side bus or the interrupt has been latched After the snoop is serviced or the interrupt is latched the processor will return to the Stop Grant state or HALT state as appropriate Extended HALT Snoop State The Extended HALT Snoop state is the default Snoop state when the Extended HALT state is enabled via the BIOS The processor will remain in the lower bus to core frequency ratio and VID operating point of the Extended HALT state While in the Extended HALT Snoop state snoops and interrupt transactions are handled the same way as in the HALT Snoop state After the snoop is serviced or the interrupt is latched the processor will return to the Extended HALT state Datasheet Features 6 3 Datasheet intel Enhanced Intel SpeedStep Technology The processor supports Enhanced Intel SpeedStep Technology This technology enables the processor to switch between multiple frequency and voltage points which results in platform power savings Enhanced Intel SpeedStep Technology requires support for dynamic VID transitions in the platform Switching between voltage frequency states is software controlled For more configuration details also refer to the Intel 64 and 1A 32 Architectures Software Developer s Manual Enhanced Intel S
73. is the highest expected sustainable power while running known power intensive applications TDP is not the maximum power that the processor can dissipate Intel 64 Architecture An enhancement to Intel s A 32 architecture that allows the processor to execute operating systems and applications written to take advantage of the 64 bit extension technology Enhanced Intel SpeedStep Technology Technology that provides power management capabilities to servers and workstations Platform Environment Control I nterface PECI A proprietary one wire bus interface that provides a communication channel between Intel processor and external thermal monitoring devices for use in fan speed control PECI communicates readings from the processor s digital thermometer PECI replaces the thermal diode available in previous processors Intel virtualization Technology Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple robust independent software environments inside a single platform VRM Voltage Regulator Module DC DC converter built onto a module that interfaces with a card edge socket and supplies the correct voltage and current to the processor based on the logic state of the processor VID bits EVRD Enterprise Voltage Regulator Down DC DC converter integrated onto the system board that provides the correct voltage and current to the processor based on the logic state of the process
74. istors R77 For details see Table 2 18 TAP CMOS Asynchronous inputs and CMOS Asynchronous outputs do not include on die termination Inputs and utilized outputs must be terminated on the baseboard Unused outputs may be terminated on the baseboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing The TESTHI signals must be tied to the processor V using a matched resistor where a matched resistor has a resistance value within 20 of the impedance of the board transmission line traces For example if the trace impedance is 50 Q then a value between 40 Q and 60 Q is required The TESTHI signals must use individual pull up resistors as detailed below A matched resistor must be used for each signal TESTHI 10 cannot be grouped with other TESTHI signals TESTHI 11 cannot be grouped with other TESTHI signals TESTHI 12 cannot be grouped with other TESTHI signals 19 m n tel Electrical Specifications 2 7 Table 2 6 20 Front Side Bus Signal Groups The FSB signals have been combined into groups by buffer type AGTL input signals have differential input buffers which use GTLREF DATA and GTLREF ADD as reference levels In this document the term AGTL Input refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output gr
75. le it is expected that the Thermal Control Circuit TCC would only be activated for very brief periods of time when running the most power intensive applications Refer to the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 for details on system thermal solution design thermal profiles and environmental considerations Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the Thermal Design Power TDP indicated in Table 5 1 for the processor instead of the maximum processor power consumption The Thermal Monitor feature is intended to help protect the processor in the event that an application exceeds the TDP recommendation for a sustained time period For more 75 Thermal Specifications details on this feature refer to Section 5 2 Thermal Monitor 1 and Thermal Monitor 2 feature must be enabled for the processor to remain within its specifications Table 5 1 Processor Thermal Specifications Maximum Thermal Minimum Maximum Core Frequency Power Design Power TCASE TCASE Notes w w C C See QX9775 155 150 5 Figure 5 1 1 2 3 4 5 Table 5 2 NOTES 1 These values are specified at Vcc max for all processor frequencies Systems must be 4 5 designed to ensure the processor is not to be subjected to any static V
76. level Commonly used terms are explained here for clarification Intel Core 2 Extreme processor QX9775 Intel 64 bit microprocessor intended for dual processor desktops The processor is based on Intel s 45 nanometer process and packaged in the FC LGA package with four processor cores FC LGA Flip Chip Land Grid Array Package The processor package is a Land Grid Array consisting of a processor core mounted on a pinless substrate with 771 lands and includes an integrated heat spreader IHS LGA771 socket The processor interfaces to the baseboard through this surface mount 771 Land socket See the LGA771 Socket Design Guidelines for details regarding this socket Processor core Processor core with integrated L1 cache L2 cache and system bus interface are shared between the two cores on the die All AC timing and signal integrity specifications are at the pads of the system bus interface Front Side Bus FSB The electrical interface that connects the processor to the chipset Also referred to as the processor system bus or the system bus All memory and I O transactions as well as interrupt messages pass between the processor and chipset over the FSB Dual Independent Bus DIB A front side bus architecture with one processor on each of several processor buses rather than a processor bus shared between Datasheet Introduction Datasheet intel two processor agents The DIB architecture provides im
77. lso include Intel Wide Dynamic Execution enhanced floating point and multi media units Streaming SIMD Extensions 2 SSE2 Streaming SIMD Extensions 3 SSE3 and Streaming SIMD Extensions 4 1 SSE4 1 Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor The floating point and multi media units include 128 bit wide registers and a separate register for data movement SSE3 instructions provide highly efficient double precision floating point SIMD integer and memory management operations The processor supports Intel 64 Architecture as an enhancement to Intel s A 32 architecture This enhancement allows the processor to execute operating systems and applications written to take advantage of the 64 bit extension technology Further details on Intel 64 Architecture and its programming model can be found in the Intel 64 and IA 32 Architectures Software Developer s Manual at http www intel com products processor manuals In addition the processor supports the Execute Disable Bit functionality When used in conjunction with a supporting operating system Execute Disable allows memory to be marked as executable or non executable This feature can prevent some classes of viruses that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system Further details on Execute Disable can be found at http www intel com cd ids developer asmo na eng 14930
78. ly to frequency transitions initiated due to thermal events Extended HALT Enhanced Intel SpeedStep Technology transitions or assertion of the FORCEPR signal See Chapter 5 Not all operating systems can support dual processors with mixed frequencies Mixing processors of different steppings but the same model as per CPUID instruction is supported Details regarding the CPUID instruction are provided in the AP 485 Intel Processor Identification and the CPUID Instruction application note Absolute Maximum and Minimum Ratings Table 2 11 specifies absolute maximum and minimum ratings only which lie outside the functional limits of the processor Only within specified operation limits can functionality and long term reliability be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length o
79. m Crossing Voltage Crossing Voltage Ringback Threshold Margin Region Tp Tp T1 BCLK 1 0 period Overshoot W r w ee uh GA AKA Ringback Undershoot Rising Edge Ringback Falling Edge VL Figure 2 6 Differential Clock Crosspoint Specification 650 600 500 450 550 0 5 VHavg 700 400 250 0 5 VHavg 700 350 Crossing Point mV 300 250 200 T T T T T T T T T T T T T T T T VHavg mV 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 Figure 2 7 Differential Rising and Falling Edge Rates REFCLK 1 1 1 1 1 1 L 1 1 1 1 1 1 minus U 1 1 t i 1 1 i L 1 1 I 1 1 1 i Differential Measurement Points for Rise and Fall Time 88 34 Rise Edge Rate Fall Edge Rate Se S TERE Datasheet m Mechanical Specifications n tel 3 Mechanical Specifications The processor is packaged in a Flip Chip Land Grid Array FC LGA package that interfaces to the baseboard via a LGA771 socket The package consists of a processor core mounted on a pinless substrate with 771 lands An integrated heat spreader IHS is attached to the package substrate and core and serves as the interface for processor component thermal solutions such as a heatsink Figure 3 1 shows a sketch of the processor package components and how they are
80. n that processor core is halted however the other processor core continues normal operation The Extended HALT state is a lower power state than the HALT state or Stop Grant state The Extended HALT state must be enabled for the processor to remain within its specifications The processor will automatically transition to a lower core frequency and voltage operating point before entering the Extended HALT state Note that the processor FSB frequency is not altered only the internal core frequency is changed When entering the low power state the processor will first switch to the lower bus to core frequency ratio and then transition to the lower voltage VID While in the Extended HALT state the processor will process bus snoops Extended HALT Maximum Power Symbol Parameter Min Typ Max Unit Notes Extended HALT PEXTENDED_HALT Gtate Power 16 w 1 2 NOTE 1 The specification is at Tcase 40 C and nominal Vcc The VID setting represents the maximum expected VID when running in HALT state 2 Processors running in the lowest bus ratio supported as shown in Table 2 1 will enter the HALT State when the processor has executed the HALT or MWAIT instruction since the processor is already operating in the lowest core frequency and voltage operating point The processor exits the Extended HALT state when a break event occurs When the processor exits the Extended HALT state it will first transition the
81. n to the Grant Snoop state will occur when the processor detects a snoop on the front side bus see Section 6 2 4 1 While in the Stop Grant state SMI INIT BINIT and LINT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal state Only one occurrence of each event will be recognized upon return to the Normal state While in Stop Grant state the processor will process snoops on the front side bus and it will latch interrupts delivered on the front side bus The PBE signal can be driven when the processor is in Stop Grant state PBE will be asserted if there is any pending interrupt latched within the processor Pending interrupts that are blocked by the EFLAGS IF bit being clear will still cause assertion of PBE Assertion of PBE indicates to system logic that it should return the processor to the Normal state Extended HALT Snoop or HALT Snoop State Stop Grant Snoop State The Extended HALT Snoop state is used in conjunction with the Extended HALT state If the Extended HALT state is not enabled in the BIOS the default Snoop state entered will be the HALT Snoop state Refer to the sections below for details on HALT Snoop state Stop Grant Snoop state and Extended HALT Snoop state HALT Snoop State Stop Grant Snoop State The processor will respond to snoop or interrupt transactions on the front side bus while in Stop Grant state or in HALT state During a snoop or interrupt transact
82. nd VSS_DIE_SENSE lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands with an oscilloscope set to 100 MHz bandwidth 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe 4 The processor must not be subjected to any static Vcc level that exceeds the Vcc max associated with any particular current Failure to adhere to this specification can shorten processor lifetime 5 lec Max Specification is based on maximum Vcc loadline Refer to Figure 2 3 for details The processor is capable of drawing lcc max for up to 10 ms Refer to Figure 2 1 for further details on the average processor current draw over various time durations 6 This specification represents the total current for 7 Vr must be provided via a separate voltage source and must not be connected to Vcc This specification is measured at the land Datasheet Electrical Specifications 10 11 12 13 14 15 16 17 intel Minimum Vcc and maximum lec are specified at the maximum processor case temperature TCASE shown in Figure 5 1 This specification refers to the total reduction of the load line due to VID transitions below the specified VID Individual processor VID values may be calibrated during manufacturing such that two devices at the same frequency may have different VID settings This sp
83. ndling Guidelines ss 40 3 5 Package Insertion Specifications 40 3 6 Processor Mass Specifications issus 40 3 7 Processor Materials imer tiet x GET PAP At OE Ems O uu REALM W A PE EEG AA 40 3 8 Processor Markings arreo meierei nnna aA ne OO R AA PaK dO Oy eens eee dk 41 3 9 Processor Land Coordinates aaa aaa aaa aaa aa aaa akara aaa aaa sin nemen nnns 42 4 Land Listing and Signal Description 45 ArT ETE EE 45 4 2 Signal Definitions eub d A a ap AAA jaded E a A lee RS bead KOBA AG UNE 64 5 Thermal SpeclfiCAtIONsS wy iza Mei ates PARP nA A SA AAAA o a nce EP P 75 5 1 Package Thermal Specifications 75 5 2 Processor Thermal Features 78 5 3 Platform Environment Control Interface PECI aaa aaa aaa emen 81 6 gi s M RNIS 85 6 1 Power On Configuration Options 85 6 2 Clock Control and Low Power States iii 85 6 3 Enhanced Intel SpeedStep Technology eeuaua aaa aaa aaa aaa aaa aa anawa anni ALAM 89 Datasheet 3 Figures 2 1 Input Device Hystereslis eerte O AAA GA ROR eden E RENE RING FM M CIERRE E SAPER 23 2 2 Processor Load Current versus Time 27 2 3 Processor VCC Static and Transient Tolerance Load Lines 29 2 4 VCC Overshoot Example Waveform sise 31 2 5 Differential Clock Waveform uuueeee siemens 34 2 6 Differential Clock Crosspoint Specifications 34 2 7 Differential Rising and Falling Edge Rates 34 3 1
84. ng and falling edge Strobes are associated with signals as shown below Signals Associated Strobes REQI4 0 A 16 3 A 37 36 ADSTBO A 35 17 ADSTB1 Datasheet Land Listing and Signal Description Table 4 1 Signal Definitions Sheet 2 of 11 intel Name Type Description Notes AP 1 0 1 0 AP 1 0 Address Parity are driven by the request initiator along with ADS A 37 3 and the transaction type on the REQ 4 0 signals A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This allows parity to be high when all the covered signals are high AP 1 0 must be connected to the appropriate pins of all processor FSB agents The following table defines the coverage model of these signals Request Signals Subphase 1 Subphase 2 A 37 24 4 APO AP1 A 23 3 AP1 APO REQ 4 0 AP1 APO BCLK 1 0 BINIT 1 0 The differential bus clock pair BCLK 1 0 Bus Clock determines the FSB frequency All processor FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing Vcnoss BINIT Bus Initialization may be observed and driven by all processor FSB agents and if used must connect the appropriate pins of all such agents If th
85. nput Output F28 BCLKO Clk Input E13 D26 Source Sync Input Output F29 RESERVED E14 VSS Power Other F3 BRO Common Clk Input Output E15 D33 Source Sync lnput Output F30 VIT Pawer Other E16 D34 Source Sync Input Output G1 BPMbO Common Clk Input Output E17 VSS Power Other G2 COMP2 Power Other Input E18 D30 Source Sync Input Output G3 BPMb3 Common Clk Input Output E19 D40 Source Sync lnput Output G4 BPMb2 Common Cik Output E20 VSS Power Other G5 PECI Power Other Input Output E21 D42 Source Sync lnput Output G6 RESERVED E22 D45 Source Sync Input Output GI DEFER Common Cik Input E23 RESERVED G8 BPRI 4 Common Clk Input Datasheet Land Listing and Signal Description Datasheet intel Table 4 2 Land Listing by Land Table 4 2 Land Listing by Land Number Sheet 5 of 17 Number Sheet 6 of 17 Pin Signal Pin Signal No Pin Name Buffer Type Direction No Pin Name Buffer Type Direction G9 D16 Source Sync lnput Output H23 VSS Power Other G10 EU a Power Other Input H24 VSS Power Other H25 VSS Power Other G11 DBI 1 Source Sync Input Output H26 VSS Power Other G12 DSTBN1 Source Sync lnput Output H27 VSS Power Other G13 D27 Source Sync lnput Output H28 VSS Power Other G14 D29 Source Syn
86. nsor DTS provides an improved capability to monitor device hot spots which inherently leads to more varying temperature readings over short time intervals The DTS sample interval range can be modified and a data filtering algorithm can be activated to help moderate this The DTS sample interval range is 82 us default to 20 ms max This value can be set in BIOS To reduce the sample rate requirements on PECI and improve thermal data stability vs time the processor DTS also implements an averaging algorithm that filters the incoming data This is an alpha beta filter with coefficients of 0 5 and is expressed mathematically as Current filtered temp Previous filtered temp 2 new sensor temp 2 This filtering algorithm is fixed and cannot be changed It is on by default and can be turned off in BIOS Host controllers should use the min max sample times to determine the appropriate sample rate based on the controller s fan control algorithm and targeted response rate The key items to take into account when settling on a fan control algorithm are the DTS sample rate whether the temperature filter is enabled how often the PECI host will poll the processor for temperature data and the rate at which fan speed is changed Depending on the designer s specific requirements the DTS sample rate and alpha beta filter may have no effect on the fan control algorithm 83 m n tel Thermal Specifications 5 3 2 5 3 2 1 5 3 2 2
87. ocessor using four 45 nm Hi k next generation Intel Core microarchitecture cores The processor is manufactured on Intel s 45 nanometer process technology combining high performance with the power efficiencies of a low power microarchitecture The Intel Core 2 Extreme processor QX9775 maintains the tradition of compatibility with 1A 32 software For this document Intel Core 2 Extreme processor QX9775 is referred to as processor Key processor features include on die primary 32 kB instruction cache and 32 kB write back data cache in each core and 12 MB 2 x 6 MB Level 2 cache with Intel Advanced Smart Cache Architecture The processors Data Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache requests occurs resulting in reduced effective bus latency and improved performance The 1600 MHz Front Side Bus FSB is a quad pumped bus running from a 400 MHz system clock making 12 80 GBytes per second data transfer rates possible Enhanced thermal and power management capabilities are implemented including Intel Thermal Monitor TM1 Thermal Monitor 2 TM2 and Enhanced Intel SpeedStep Technology These technologies are targeted for dual processor configurations in enterprise environments TM1 and TM2 provide efficient and effective cooling in high temperature situations Enhanced Intel SpeedStep Technology provides power management capabilities to servers and workstations Processor features a
88. ocks Data 42 Datasheet Mechanical Specifications n tel Figure 3 7 Processor Land Coordinates Bottom View Voc Vss T 2 39 4 b e 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 AN NZ AN AM AM AL AL AK AK AJ AJ AH AH AG AG AF AF AE AE AD AD Address Common Clock Async Socket 771 Quadrants Bottom View pog pwoomnQie lt xrzzvnic lt lt lt Z 5 gt gt gt uoommorc car amp z amp zvu ac c z ss5o s 123 4 5 6 7 8 9 1011 1213 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Data Vr Clocks Datasheet 43 44 Mechanical Specifications Datasheet m Land Listing and Signal Description n tel 4 4 1 Datasheet Land Listing and Signal Description Land Listing Table 4 1 is a listing of all processor lands ordered alphabetically by Land name Table 4 2 is a listing of all processor lands ordered by land number 45 Land Listing and Signal Description Table 4 1 Land Listing by Land Table 4 1 Land Listing by Land Name Sheet 1 of 17 Name Sheet 2 of 17 Land Name ros Kreta Direction Land Name e meri m Direction A3 M5 Source Sync Input Output BPM1 AJ1 Common Clk Output A4 P6 Source Sync Input Output BPM2 AD2 Common Clk Output A5 L5 Sou
89. on 2 Datasheet Contents 1 I ENOJUCUH N pe TUM 9 lil Terminology oie ere bet e RAE a me beat oreet Kro Pr re edet doi 10 L2 Chis 12 2 Electrical Specifications rec ede tee D ORO ER RR E ERR EAR KE IRL TEE SERE 13 2 1 Front Side Bus and GTEREF zast ty ropa AREA a PiS C naines css Ur AGE E 13 2 2 Power and Ground Lands 0 sisi 13 2 3 Decoupling GUIdELINES rientro re tendum nx etre and on e ee E NR Sex E ERE R GR GA 14 2 4 Front Side Bus Clock BCLK 1 0 and Processor Clocking sene 15 2 5 Voltage Identification VID id es ereeerrenrenes 17 2 6 Reserved Unused and Test Signals 19 2 7 Front Side Bus Signal Groups 20 2 8 CMOS Asynchronous and Open Drain Asynchronous Signals 22 2 9 Test Access Port TAP Connection uumuaaaaa aa aaa aaa eH emen enne nnn nena 22 2 10 Platform Environmental Control Interface PECI DC Specifications 22 2 11 Mixing PFrOCeSSOEIS ient etia eA Ede atre enda NOR Rep Ra du nee EE aaa dE 24 2 12 Absolute Maximum and Minimum Ratings 24 2 13 Processor DC Specifications sisi 25 2 14 AGTLE ESB SpecifiCatlOns ioi teer ramener Enni eir te orev Rene ik Rt Rex a XE mis zi KE RIEN 32 3 Mechanical Specifications eee a R A re A PP PA n LES IR PA a R ERA cede tenga 35 3 1 Package Mechanical Drawings sisi 35 3 2 Processor Component Keepout Zones 39 3 3 Package Loading Specifications issus 39 3 4 Package Ha
90. one Datasheet m Thermal Specifications n tel 5 5 1 5 1 1 Datasheet Thermal Specifications Package Thermal Specifications The processor requires a thermal solution to maintain temperatures within its operating limits Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system As processor technology changes thermal management becomes increasingly crucial when building computer systems Maintaining the proper thermal environment is key to reliable long term system operation A complete solution includes both component and system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor integrated heat spreader IHS Typical system level thermal solutions may consist of system fans combined with ducting and venting This section provides data necessary for developing a complete thermal solution For more information on designing a component level thermal solution refer to the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 Thermal Specifications To allow the optimal operation and long term reliability of Intel processor based systems the processor must remain within the minimum and maximum case temperature TCASE specifications as defined by the applicable thermal profile Table 5 1 and Figure 5 1
91. ons Table 3 1 Package Loading Specifications Board z Parameter Thickness Min Max Unit Notes 1 57 mm 80 311 N 0 062 18 70 Ibf Static 2 16 mm 111 311 N 1 Compressive Load 0 085 25 70 Ibf et 2 54 mm 133 311 N 0 100 30 70 Ibf 311 N max static compressive load N Dynamic 222 N dynamic loading NA NA 1 3 4 5 6 Compressive Load 70 Ibf max static compressive load lbf 50 Ibf dynamic loading Transient Bend 1 57 mm Limits 0 062 NA 750 me 1 3 7 NOTES 1 These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top surface 2 This is the minimum and maximum static force that can be applied by the heatsink and retention solution to maintain the heatsink and processor interface 3 These specifications are based on limited testing for design characterization Loading limits are for the LGA771 socket 4 Dynamic compressive load applies to all board thickness 5 Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement 6 Test condition used a heatsink mass of 1 Ibm with 50 g acceleration measured at heatsink mass The dynamic portion of this specification in the product application can have flexibility in specific values but the ultimate product of mass times acceleration should not exceed this dynamic load 7 Transient bend is defined as the transient board deflection during manufacturing such as board assembly and system integration
92. or VID bits Vcc The processor core power supply Vss The processor ground Vrr FSB termination voltage 11 Introduction intel 1 2 References 12 Material and concepts available in the following documents may be beneficial when reading this document Document Location Intel Core 2 Extreme Processor QX9775 Specification Update http www intel com design processor specupdt 319129 htm Intel Core 2 Extreme Processor QX9775 Thermal and Mechanical Design Guidelines Addendum TMDG http www intel com design processor designex 319130 htm LGA771 Socket Mechanical Design Guide http www intel com design xeon guides 313871 htm Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines http www intel com design processor applnots 313214 htm AP 485 Intel Processor Identification and the CPUID Instruction http www intel com design processor applnots 241618 htm Intel 64 and IA 32 Intel Architecture Software Developer s Manuals Volume 1 Basic Architecture Volume 2A Instruction Set Reference A M Volume 2B Instruction Set Reference N Z Volume 3A System Programming Guide Volume 3B System Programming Guide http www intel com products processor manuals Intel 64 and 1A 32 Intel Architecture Optimization Reference Manual http www intel com products processor manuals Intel 6
93. or processor core See Table 2 13 and V 2 3 4 8 FE QX9775 3 2 GHz Figure 2 3 18 Vec_boot Default VCC Voltage for initial power up 1 10 V 2 VVID_STEP VID step size during a transition 12 5 mV Vvip_sHirt Total allowable DC load line shift from VID steps 450 mV 9 Vr FSB termination voltage DC AC specification 1 045 1 10 1 155 V 7 12 VCCPLL PLL supply voltage DC AC specification 1 455 1 500 1 605 V 11 Processor Number lI cc processor core with 45 8 17 lec multiple VID A 2 QX9775 3 2 GHz 150 Processor Number lcc neseT Core with Icc REsET multiple VI D A 16 17 QX9775 3 2 GHz 150 lec for Vz supply before Vcc stable 8 It A 14 lec for Vr supply after Vcc stable 7 Processor Number Thermal Design Current lec roc TDC A 13 17 18 QX9775 3 2 GHz 130 Cave oe that may be drawn from Vrr our per m m 580 MA 15 lec for lcc GTLREF GTLREF DATA MID GTLREF DATA END 200 HA 6 7 GTLREF_ADD_MID and GTLREF_ADD_END Icc vccPLL lec for PLL supply EZ 260 mA 11 Itcc Icc during active thermal control circuit TCC a 150 A 17 NOTES 1 Unless otherwise noted all specifications in this table are based on final silicon characterization data 2 These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 5 for more information 3 The voltage specification requirements are measured across the VCC_DIE_SENSE a
94. oup as well as the AGTL I O group when driving AGTL asynchronous outputs can become active anytime and include an active PMOS pull up transistor to assist during the first clock of a low to high voltage transition With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock signals whose timings are specified with respect to rising edge of BCLKO ADS HIT HITM etc and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as rising edge of BCLKO Asynchronous signals are still present A20M IGNNE etc and can become active at any time during the clock cycle Table 2 6 identifies which signals are common clock source synchronous and asynchronous FSB Signal Groups Sheet 1 of 2 Signal Group Type Signals AGTL Common Clock Synchronous to BPRI DEFER RESET RS 2 0 RSP Input BCLK 1 0 TRDY AGTL Common Clock Synchronous to Output BCLK 1 0 BPM4 BPM 2 1 BPMb 2 1 ADS AP 1 0 BINIT 2 BNR 2 BPM5 AGTL Common Clock Synchronous to BPM3 BPMO BPMb3 BPMbO BR 1 0 1 0 BCLK 1 0 DBSY DP 3 0 DRDY HIT 2 HITM 2 LOCK MCERR 2 Signals Associated Strobe da A 16 3 ADSTBO AGTL Source Synchronous to A 35 17 ADSTB1 synchronous 1 Q assoc Strobe D 15 0 DBIO DSTBPO DSTBNO D 31 16 DBI1 DSTB
95. ource Sync Input Output A27 AF5 Source Sync Input Output D6 B7 Source Sync Input Output A28 AF4 Source Sync Input Output D73 A7 Source Sync Input Output A29 AG6 Source Sync Input Output D8 A10 Source Sync Input Output A30 AG4 Source Sync Input Output D9 All Source Sync Input Output A31 AG5 Source Sync Input Output D10 B10 Source Sync Input Output A32 AH4 Source Sync lnput Output D11 C11 Source Sync Input Output A33 AH5 Source Sync Input Output D12 D8 Source Sync Input Output A34 AJ5 Source Sync Input Output D13 B12 Source Sync Input Output A35 AJ6 Source Sync Input Output D14 C12 Source Sync Input Output A36 N4 Source Sync Input Output D15 D11 Source Sync Input Output A37 P5 Source Sync Input Output D16 G9 Source Sync Input Output ADS D2 Common Clk Input Output D17 F8 Source Sync Input Output ADSTBO R6 Source Sync lnput Output D18 F9 Source Sync Input Output ADSTB1 AD5 Source Sync Input Output D19 E9 Source Sync Input Output APO U2 Common Clk Input Output D20 D7 Source Sync Input Output AP1 U3 Common Clk Input Output D21 E10 Source Sync Input Output BCLKO F28 Clk Input D22 D10 Source Sync Input Output BCLK1 G28 Clk Input D23 F11 Source Sync Input Output BINIT AD3 Common Clk Input Output D24 F12 Source Sync Input Output BNR C2 Common Clk Input Output D25 D13 Source Sync Input Output BPMO AJ2 Common Clk lnput Output D26 E13 Source Sync Input Output
96. pe information These signals must connect the appropriate pins of all agents on the FSB A 37 3 are protected by parity signals AP 1 0 A 37 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processors sample a subset of the A 37 3 lands to determine their power on configuration See Section 6 1 A20M If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an 1 0 write instruction it must be valid along with the TRDY assertion of the corresponding I O write bus transaction ADS 1 0 ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 37 3 lands All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction This signal must be connected to the appropriate pins on all processor FSB agents ADSTB 1 0 1 0 Address strobes are used to latch A 37 3 and REQ 4 0 on their risi
97. peedStep Technology creates processor performance states P states or voltage frequency operating points which are lower power capability states within the Normal state see Figure 6 1 for the Stop Clock State Machine for supported P states Enhanced Intel SpeedStep Technology enables real time dynamic switching between frequency and voltage points It alters the performance of the processor by changing the bus to core frequency ratio and voltage This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system The processor has hardware logic that coordinates the requested voltage VID between the processor cores The highest voltage that is requested for either of the processor cores is selected for that processor package Note that the front side bus is not altered only the internal core frequency is changed In order to run at reduced power consumption the voltage is altered in step with the bus ratio The following are key features of Enhanced Intel SpeedStep Technology Multiple voltage frequency operating points provide optimal performance at reduced power consumption Voltage frequency selection is software controlled by writing to the processor MSR s Model Specific Registers thus eliminating chipset dependency If the target frequency is higher than the current frequency Vcc is incremented in steps 12 5 mV by placing a new valu
98. per s Manual and the Intel Processor Identification and the CPUID Instruction application note FORCEPR The FORCEPR force power reduction input can be used by the platform to cause the processor to activate the Thermal Control Circuit TCC GTLREF_ADD_MID GTLREF_ADD_END GTLREF_ADD determines the signal reference level for AGTL address and common clock input lands GTLREF_ADD is used by the AGTL receivers to determine if a signal is a logical 0 or a logical 1 Refer to Table 2 18 for additional details GTLREF_DATA_MID GTLREF_DATA_END GTLREF_DATA determines the signal reference level for AGTL data input lands GTLREF_DATA is used by the AGTL receivers to determine if a signal is a logical 0 or a logical 1 Refer to Table 2 18 for additional details HIT HITM 1 0 1 0 HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any FSB agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together IERR IERRZ Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor FSB This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET This signal does not ha
99. proved performance by allowing increased FSB speeds and bandwidth Functional Operation Refers to the normal operating conditions in which all processor specifications including DC AC FSB signal quality mechanical and thermal are satisfied Storage Conditions Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor lands should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air that is unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material Priority Agent The priority agent is the host bridge to the processor and is typically known as the chipset Symmetric Agent A symmetric agent is a processor which shares the same 1 0 subsystem and memory array and runs the same operating system as another processor in a system Systems using symmetric agents are known as Symmetric Multiprocessing SMP systems Integrated Heat Spreader IHS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface Thermal Design Power TDP Processor thermal solutions should be designed to meet this target It
100. r A7 DO7 Source Sync lnput Output B27 VTT Power Other A8 DBIO Source Sync lnput Output B28 VIT Power Other A9 VSS Power Other B29 VIT Power Other A10 DO8 Source Sync lnput Output B30 VTT Power Other A11 DO9 Source Sync lnput Output C1 DRDY Common Clk Input Output A12 VSS Power Other C2 BNR Common Clk Input Output A13 COMPO Power Other lnput C3 LOCK Common Clk Input Output Al4 D50 Source Sync lnput Output C4 VSS Power Other A15 VSS Power Other c5 DO1 Source Sync lnput Output A16 DSTBN3 Source Sync lnput Output C6 DO3 Source Sync lnput Output A17 D56 Source Sync lnput Output C7 VSS Power Other A18 VSS Power Other C8 DSTBNO Source Sync lnput Output A19 D61 Source Sync lnput Output C9 BPMb1 Common Clk Output A20 RESERVED C10 VSS Power Other A21 VSS Power Other C11 D11 Source Sync Input Output A22 D62 Source Sync lnput Output C12 D14 Source Sync Input Output A23 RESERVED C13 VSS Power Other A24 RESERVED C14 D52 Source Sync lnput Output A25 VTT Power Other C15 D51 Source Sync lnput Output A26 VIT Power Other C16 VSS Power Other B1 VSS Power Other C17 DSTBP3 Source Sync lnput Output B2 DBSY Common Clk Input Output C18 D54 Source Sync lnput Output B3 RSO Common Clk Input C19 VSS Power Other B4 DOO Source Sync lnput Output C20 DBI 3s Source Sync lnput Output B5 VSS Power Other C21 D58 Source Sync lnput Output B6 DO5 Source Sync lnput Output C22 VSS Power Other B7 D063 Sourc
101. r AC30 VCC Power Other AE30 VSS Power Other AD1 TDI TAP Input AF1 TDO TAP Output AD2 BPM2 Common Clk Output AF2 BPM4 Common Clk Output AD3 BINIT Common Clk Input Output AF3 VSS Power Other AD4 VSS Power Other AF4 A28 Source Sync lnput Output AD5 ADSTB1 Source Sync lnput Output AF5 A27 Source Sync Input Output AD6 A22 Source Sync lnput Output AF6 VSS Power Other AD7 VSS Power Other AF7 VSS Power Other AD8 VCC Power Other AF8 VCC Power Other AD23 VCC Power Other AF9 VCC Power Other AD24 VCC Power Other AF10 VSS Power Other AD25 VCC Power Other AF11 VCC Power Other AD26 VCC Power Other AF12 VCC Power Other AD27 VCC Power Other AF13 VSS Power Other AD28 VCC Power Other AF14 VCC Power Other Datasheet Land Listing and Signal Description intel Table 4 2 Land Listing by Land Table 4 2 Land Listing by Land Number Sheet 13 of Number Sheet 14 of he Pin Name THU a Direction E Pin Name TE ar Um Direction AF15 VCC Power Other AH1 VSS Power Other AF16 VSS Power Other AH2 RESERVED AF17 VSS Power Other AH3 VSS Power Other AF18 VCC Power Other AH4 A32 Source Sync lnput Output AF19 VCC Power Other AH5 A33 Source Sync lnput Output AF20 VSS Power Other AH6 VSS Power Other AF21 VCC Power Other AH7 RESERVED AF22 VCC Power Other AH8 VCC Power Oth
102. r VCC AH21 Power Other VCC AL9 Power Other VCC AH22 Power Other VCC AM11 Power Other VCC AH25 Power Other VCC AM12 Power Other VCC AH26 Power Other VCC AM14 Power Other VCC AH27 Power Other VCC AM15 Power Other VCC AH28 Power Other VCC AM18 Power Other VCC AH29 Power Other VCC AM19 Power Other VCC AH30 Power Other VCC AM21 Power Other VCC AH8 Power Other VCC AM22 Power Other VCC AH9 Power Other VCC AM25 Power Other VCC AJ11 Power Other VCC AM26 Power Other VCC AJ12 Power Other VCC AM29 Power Other VCC AJ14 Power Other VCC AM30 Power Other 49 50 Land Listing and Signal Description Table 4 1 Land Listing by Land Table 4 1 Land Listing by Land Name Sheet 9 of 17 Name Sheet 10 of 17 Land Name ro Kraz Direction Land Name pon EUN tie Direction VCC AM8 Power Other VCC M24 Power Other VCC AM9 Power Other VCC M25 Power Other VCC AN11 Power Other VCC M26 Power Other VCC AN12 Power Other VCC M27 Power Other VCC AN14 Power Other VCC M28 Power Other VCC AN15 Power Other VCC M29 Power Other VCC AN18 Power Other VCC M30 Power Other VCC AN19 Power Other VCC M8 Power Other VCC AN21 Power Other VCC N23 Power Other VCC AN22 Power Other VCC N24 Power Other VCC AN25 Power Other VCC N25 Power Other VCC AN26 Power Other VCC N26 Power Other VCC AN8
103. r 2 includes two operating points each consisting of a specific operating frequency and voltage which is identical for both processor cores The first operating point represents the normal operating condition for the processor Under this condition the core frequency to system bus multiplier used by the processor is that contained in the CLOCK FLEX MAX MSR and the VID that is specified in Table 2 3 The second operating point consists of both a lower operating frequency and voltage The lowest operating frequency is determined by the lowest supported bus ratio 1 6 for the processor When the TCC is activated the processor automatically transitions to the new frequency This transition occurs rapidly on the order of 5 us During the frequency transition the processor is unable to service any bus requests and consequently all bus traffic is blocked Edge triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency Once the new operating frequency is engaged the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator The voltage regulator must support dynamic VID steps in order to support Thermal Monitor 2 During the voltage change it will be necessary to transition through multiple VID codes to reach the target operating voltage Each step will be one VID table entry see Table 2 3 The processor continues to execute instructions durin
104. r Other VSS F4 Power Other VSS P23 Power Other VSS F7 Power Other VSS P24 Power Other VSS H10 Power Other VSS P25 Power Other VSS H11 Power Other VSS P26 Power Other VSS H12 Power Other VSS P27 Power Other VSS H13 Power Other VSS P28 Power Other VSS H14 Power Other VSS P29 Power Other VSS H17 Power Other VSS P30 Power Other VSS H18 Power Other VSS P4 Power Other VSS H19 Power Other VSS P7 Power Other VSS H20 Power Other VSS R2 Power Other VSS H21 Power Other VSS R23 Power Other VSS H22 Power Other VSS R24 Power Other VSS H23 Power Other VSS R25 Power Other VSS H24 Power Other VSS R26 Power Other VSS H25 Power Other VSS R27 Power Other VSS H26 Power Other VSS R28 Power Other VSS H27 Power Other VSS R29 Power Other VSS H28 Power Other VSS R30 Power Other VSS H29 Power Other VSS R5 Power Other VSS H3 Power Other VSS R7 Power Other VSS H6 Power Other VSS T3 Power Other VSS H7 Power Other VSS T6 Power Other VSS H8 Power Other VSS T7 Power Other VSS H9 Power Other VSS U7 Power Other VSS J4 Power Other VSS V23 Power Other VSS 7 Power Other VSS V24 Power Other VSS K2 Power Other VSS V25 Power Other VSS K5 Power Other VSS V26 Power Other 53 54 Table 4 1 Land Listing by Land Name Sheet 17 of 17 Land Name ros Mol ce Direction VSS V27 Power Other VSS V28 Power Other VSS V29 Power Other VSS V3 Power Oth
105. r Y24 VCC Power Other U27 VCC Power Other Y25 VCC Power Other U28 VCC Power Other Y26 VCC Power Other U29 VCC Power Other Y27 VCC Power Other U30 VCC Power Other Y28 VCC Power Other V1 MS ID1 Power Other Output Y29 VCC Power Other V2 LL IDO Power Other Output Y30 VCC Power Other V3 VSS Power Other AA1 VIT OUT Power Other Output Va A15 Source Sync lnput Output AA2 LL_ID1 Power Other Output V5 A14 Source Sync lnput Output AA3 VSS Power Other V6 VSS Power Other AA4 A21 Source Sync lnput Output V7 VSS Power Other AA5 A23 Source Sync lnput Output V8 VCC Power Other AA6 VSS Power Other V23 VSS Power Other AA7 VSS Power Other V24 VSS Power Other AA8 VCC Power Other V25 VSS Power Other AA23 VSS Power Other V26 VSS Power Other AA24 VSS Power Other V27 VSS Power Other AA25 VSS Power Other V28 VSS Power Other AA26 VSS Power Other V29 VSS Power Other AA27 VSS Power Other v30 VSS Power Other AA28 VSS Power Other W1 MS IDO Power Other Output AA29 VSS Power Other W2 TESTIN1 Power Other lnput AA30 VSS Power Other Datasheet 59 60 Land Listing and Signal Description Table 4 2 Land Listing by Land Table 4 2 Land Listing by Land Number Sheet 11 of Number Sheet 12 of s Pin Name Tuc 4 Direction
106. r the processor to be operating within specifications When both are enabled TM2 will be activated first and TM1 will be added if TM2 is not effective Thermal Monitor TM1 The Thermal Monitor TM1 feature helps control the processor temperature by activating the Thermal Control Circuit TCC when the processor silicon reaches its maximum operating temperature The TCC reduces processor power consumption as needed by modulating starting and stopping the internal processor core clocks The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active Datasheet m Thermal Specifications n tel 5 2 1 2 Datasheet When the TM1 is enabled and a high temperature situation exists that is TCC is active the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor typically 30 5096 Cycle times are processor speed dependent and will decrease as processor core frequencies increase A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has
107. rated into the processor silicon See Table 2 8 for details on which signals do not include on die termination Refer to Table 2 18 for Ry values Valid high and low levels are determined by the input buffers via comparing with a reference voltage called GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END GTLREF DATA MID and GTLREF DATA END is the reference voltage for the FSB 4X data signals GTLREF ADD MID and GTLREF ADD END is the reference voltage for the FSB 2X address signals and common clock signals Table 2 18 lists the GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END specifications The AGTL reference voltages GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END must be generated on the baseboard using high precision voltage divider circuits Table 2 18 AGTL Bus Voltage Definitions 32 Symbol Parameter Min Typ Max Units Notes GTLREF DATA MID Data Bus Reference 0 98 0 667 z 1 02 0 667 GTLREF_DATA_END Voltage Vir 0 667 Mr Vir X 2 3 GTLREF_ADD_MID Address Bus 0 98 0 667 x 1 02 0 667 GTLREF ADD END Reference Voltage VIT 0 667 Mr Va y 2 3 Termination BOT Resistance pull up x 9H a 2 COMP COMP Resistance 49 4 49 9 50 4 Q 5 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The tolerances for this specification have been stated generically to enable system
108. rce Sync Input Output Datasheet Land Listing and Signal Description intel Table 4 2 Land Listing by Land Table 4 2 Land Listing by Land Number Sheet 9 of 17 Number Sheet 10 of hio Pin Name RE 6 Direction E Pin Name Ecol m Direction T5 A09 Source Sync lnput Output W3 RESERVED T6 VSS Power Other W4 VSS Power Other T7 VSS Power Other w5 A16 Source Sync Input Output T8 VCC Power Other W6 A18 Source Sync Input Output T23 VCC Power Other W7 VSS Power Other T24 VCC Power Other ws VCC Power Other T25 VCC Power Other W23 VCC Power Other T26 VCC Power Other W24 VCC Power Other T27 VCC Power Other W25 VCC Power Other T28 VCC Power Other W26 VCC Power Other T29 VCC Power Other W27 VCC Power Other T30 VCC Power Other W28 VCC Power Other U1 TESTIN2 Power Other Input W29 VCC Power Other U2 APO Common Clk Input Output W30 VCC Power Other U3 AP1 Common Clk lnput Output Y1 RESERVED U4 A13 Source Sync lnput Output Y2 vss Power Other U5 A12 Source Sync lnput Output Y3 RESERVED U6 A10 Source Sync lnput Output Y23 VCC Power Other U7 VSS Power Other Y4 A20 Source Sync lnput Output u8 VCC Power Other Y5 VSS Power Other u23 VCC Power Other Y6 A193 Source Sync lnput Output U24 VCC Power Other Y7 VSS Power Other U25 VCC Power Other Y8 VCC Power Other U26 VCC Power Othe
109. rce Sync Input Output BPM3 AG2 Common Clk Input Output A6 L4 Source Sync Input Output BPM4 AF2 Common Clk Output ATE M4 Source Sync Input Output BPM5 AG3 Common Clk Input Output A8 R4 Source Sync Input Output BPMbO Gl Common Clk Input Output A9 T5 Source Sync Input Output BPMb1 C9 Common Clk Output A10 U6 Source Sync Input Output BPMb2 G4 Common Clk Output All T4 Source Sync lnput Output BPMb3 G3 Common Clk Input Output A12 U5 Source Sync Input Output BPRI G8 Common Clk lnput A13 U4 Source Sync Input Output BRO F3 Common Clk Input Output Al4 V5 Source Sync Input Output BR1 H5 Common Clk Input A15 Va Source Sync Input Output BSELO G29 CMOS ASync Output A16 W5 Source Sync Input Output BSEL1 H30 CMOS ASync Output A175 AB6 Source Sync Input Output BSEL2 G30 CMOS Async Output A18 W6 Source Sync Input Output COMPO A13 Power Other Input A19 Y6 Source Sync Input Output COMP1 T1 Power Other Input A20 Y4 Source Sync Input Output COMP2 G2 Power Other Input A20M K3 CMOS ASync Input COMP3 R1 Power Other Input A21 AA4 Source Sync Input Output DO B4 Source Sync Input Output A22 AD6 Source Sync Input Output D1 c5 Source Sync Input Output A23 AA5 Source Sync Input Output D2 A4 Source Sync Input Output A24 AB5 Source Sync Input Output D3 C6 Source Sync Input Output A25 AC5 Source Sync Input Output D4 A5 Source Sync Input Output A26 AB4 Source Sync Input Output D5 B6 S
110. recoverable error without a bus protocol violation It may be driven by all processor FSB agents MCERR assertion conditions are configurable at a system level Assertion options are defined by the following options Enabled or disabled e Asserted if configured for internal errors along with IERR Asserted if configured by the request initiator of a bus transaction after it observes an error e Asserted by any bus agent when it observes an error in a bus transaction For more details regarding machine check architecture refer to the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3 These signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying These signals are not connected to the processor die Both the bits 0 and 1 are logic 1 and are no connects on the package PROCHOT PROCHOT Processor Hot will go active when the processor s temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the Thermal Control Circuit TCC has been activated if enabled The TCC will remain active until shortly after the processor deasserts PROCHOT See Section 5 2 3 for more details PWRGOOD PWRGOOD Power Good is an input The processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within t
111. riations See Table 2 4 for definitions of these pins The VR must supply the voltage that is requested by these pins or disable itself VID SELECT VID SELECT is an output from the processor which selects the appropriate VID table for the Voltage Regulator This signal is not connected to the processor die This signal is a no connect on the processor package VSS DIE SENSE VSS DIE SENSE2 VSS DIE SENSE and VSS DIE SENSE2 provides an isolated low impedance connection to the processor core power and ground This signal should be connected to the voltage regulator feedback signal which insures the output voltage that is processor voltage remains within specification VTT The FSB termination voltage input pins Refer to Table 2 12 for further details VIT OUT The VTT OUT signals are included in order to provide a local V4 for some signals that require termination to Vir on the motherboard VIT SEL The VTT SEL signal is used to select the correct V4 voltage level for the processor VIT SEL is connected to VSS on the processor package NOTES 1 For this processor land the maximum number of symmetric agents is one Maximum number of priority agents is zero 2 For this processor land the maximum number of symmetric agents is two Maximum number of priority agents is zero 3 For this processor land the maximum number of symmetric agents is two Maximum number of priority agents is
112. rocessor Mass Specifications The typical mass of the processor is 21 5 grams 0 76D oz This includes all components which make up the entire processor product Processor Materials The processor is assembled from several components The basic material properties are described in Table 3 3 Processor Materials Component Material Integrated Heat Spreader IHS Nickel over copper Substrate Fiber reinforced resin Substrate Lands Gold over nickel Datasheet m Mechanical Specifications n tel 3 8 Processor Markings Figure 3 5 shows the topside markings on the processor This diagram aids in the identification of the processor Figure 3 5 Processor Top side Markings Example Datasheet 41 m n tel Mechanical Specifications 3 9 Processor Land Coordinates Figure 3 6 and Figure 3 7 show the top and bottom view of the processor land coordinates respectively The coordinates are referred to throughout the document to identify processor lands Figure 3 6 Processor Land Coordinates Top View Voc Vss 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 1 6 5 4 3 2 1 Address Y Socket 771 v Common Clock U U Quadrants u Async Top View R P P N N M M E k K K J J H bed H G G F F E E D D c c B B A 4 A 30 29 28 27 26 25 24 28 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Vr Cl
113. roller should take action to protect the system from possible damage It is recommended that the PECI host controller take appropriate action to protect the client processor device if valid temperature readings have not been obtained in response to three consecutive gettemp s or for a one second time interval The host controller may also implement an alert to software in the event of a critical or continuous fault condition PECI GetTempO and GetTemp1 Error Code Support The error codes supported for the processor GetTemp0 and GetTemp1 commands are listed in Table 5 3 GetTempO GetTemp1 Error Codes Error Code Description 8000h General sensor error 8002h Sensor is operational but has detected a temperature below its operational range underflow Datasheet Features 6 6 1 Table 6 1 6 2 Datasheet intel Features Power On Configuration Options Several configuration options can be configured by hardware The processor samples its hardware configuration at reset on the active to inactive transition of RESET For specifics on these options refer to Table 6 1 The sampled information configures the processor for subsequent operation These configuration options cannot be changed except by another reset All external resets reconfigure the processor for configuration purposes the processor does not distinguish between a warm reset PWRGOOD signal remains asserted and a power
114. se Voltage Regulator Down EVRD 11 0 Design Guidelines for further details VRM EVRD 11 0 will support the power requirements of all frequencies of the processor The processor supports a1600 MHz Front Side Bus operations The FSB uses a split transaction deferred reply protocol and Source Synchronous Transfer SST of address and data to improve performance The processor transfers data four times per bus clock 4X data transfer rate as in AGP 4X Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as a double clocked or a 2X address bus In addition the Request Phase completes in one clock cycle The FSB is also used to deliver interrupts Signals on the FSB use Assisted Gunning Transceiver Logic AGTL level voltages Section 2 1 contains the electrical specifications of the FSB Terminology A 3t symbol after a signal name refers to an active low signal indicating a signal is in the asserted state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic
115. se specifications apply to the processor die voltage as measured across the VCC DIE SENSE and VSS DIE SENSE lands and across the VCC DIE SENSE2 and VSS DIE SENSE2 lands Symbol Parameter Min Max Units Figure Notes Magnitude of Vcc overshoot above Vos MAX yip ee 50 mV 2 4 Time duration of Vcc overshoot above Tos Max VID cc 25 us 2 4 Datasheet m Electrical Specifications n tel Figure 2 4 Vcc Overshoot Example Waveform 2 13 2 Datasheet Example Overshoot Waveform VID 0 050 Vos 2 w o S o gt VID 0 000 Tos 0 5 10 15 20 25 Time us Tos Overshoot time above VID Vos Overshoot above VID NOTES 1 Vos is the measured overshoot voltage 2 Tos is the measured time duration above VID Die Voltage Validation Core voltage VCC overshoot events at the processor must meet the specifications in Table 2 17 when measured across the VCC_DIE_SENSE and VSS_DIE_SENSE lands and across the VCC DIE SENSE2 and VSS DIE SENSE2 lands Overshoot events that are 10 ns in duration may be ignored These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope 31 intel 2 14 Electrical Specifications AGTL FSB Specifications Routing topologies are dependent on the processors supported and the chipset used in the design In most cases termination resistors are not required as these are integ
116. served 0 1 0 Reserved 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 400 MHz 1 L 1 Reserved PLL Power Supply An on die PLL filter solution is implemented on the processor The Vecp input is used for this configuration in Intel Core 2 Extreme processor QX9775 based platforms Refer to Table 2 12 for DC specifications Datasheet m Electrical Specifications n tel 2 5 Datasheet Voltage Identification VI D The Voltage Identification VID specification for the processor is defined by the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor Vcc pins VID signals are open drain outputs which must be pulled up to Vr Refer to Table 2 15 for the DC specifications for these signals A voltage range is provided in Table 2 12 and changes with frequency The specifications have been set such that one voltage regulator can operate with all supported frequencies Individual processor VID values may be calibrated during manufacturing such that two devices at the same core frequency may have different default VID settings This is reflected by the VID range values provided in Table 2 3 The processor uses six voltage identification signals VID 6 1 to support automatic selection of power supply voltages Table 2 3 specifies the voltage level corresponding
117. sor QX9775 1 0 Reserved 1 1 Reserved NOTE The LL_ID 1 0 signals are used to select the correct loadline slope for the processor Market Segment Selection Truth Table for MS ID 1 0 MS ID1 MS IDO Description 0 0 Reserved 0 1 Reserved 1 0 Reserved 1 1 Intel Core 2 Extreme processor QX9775 NOTE The MS ID 1 0 signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying Reserved Unused and Test Signals All Reserved signals must remain unconnected Connection of these signals to Vec Vr Vss or to any other signal including each other can result in component malfunction or incompatibility with future processors See Chapter 4 for a land listing of the processor and the location of all Reserved signals For reliable operation always connect unused inputs or bidirectional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnected however this may interfere with some TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability For unused AGTL input or I O signals use pull up resistors of the same value as the on die termination res
118. specification can affect the long term reliability of the processor Processor DC Specifications The processor DC specifications in this section are defined at the processor die pads unless noted otherwise See Chapter 4 for the processor land listings and signal definitions Voltage and current specifications are detailed in Table 2 12 For platform planning refer to Table 2 13 which provides Vcc static and transient tolerances This same information is presented graphically in Figure 2 3 The FSB clock signal group is detailed in Table 2 19 BSEL 2 0 and VID 6 1 signals are specified in Table 2 14 The DC specifications for the AGTL signals are listed in Table 2 15 Legacy signals and Test Access Port TAP signals follow DC specifications similar to GTL The DC specifications for the PWRGOOD input and TAP signal group are listed in Table 2 15 Table 2 12 through Table 2 17 list the DC specifications for the processor and are valid only while meeting specifications for case temperature TcasE as specified in Chapter 5 Thermal Specifications clock frequency and input voltages Care should be taken to read all notes associated with each parameter 25 intel Table 2 12 Voltage and Current Specifications Electrical Specifications 26 Symbol Parameter Min Typ Max Unit Notes 1 10 VID VID range 0 850 1 3500 V V Processor Number Vcc f
119. st signal and LINT1 NMI becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous These signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration LL ID 1 0 The LL_ID 1 0 signals are used to select the correct loadline slope for the processor These signals are not connected to the processor die LOCK 1 0 LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of all processor FSB agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor FSB it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock Datasheet Land Listing and Signal Description Table 4 1 Datasheet intel Signal Definitions Sheet 8 of 11 Name Type Description Notes MCERR MS ID 1 0 1 0 MCERR Machine Check Error is asserted to indicate an un
120. to the state of VID 6 1 A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the processor socket is empty VID 6 1 111111 or the voltage regulation circuit cannot supply the voltage that is requested the voltage regulator must disable itself See the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for further details Although the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines defines VID 7 0 VID7 and VIDO are not used on the processor VID7 is always hard wired low at the voltage regulator The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage Vcc This will represent a DC shift in the load line It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target core voltage Transitions above the specified VID are not permitted Table 2 12 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 2 13 and Table 2 2 The VRM or EVRD used must be capable of regulating its output to the value defined by the new VID DC specifications for dynamic VID transitions are included in Table 2 12 and Table 2 13 Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11
121. tput p ZE G10 Power Other Input D41 F20 Source Sync Input Output D42 E21 Source Sync Input Output A adna F2 Power Other lnput D43 F21 Source Sync Input Output GTLREF_DAT m ae de D44 G21 Source Sync Input Output A END put D45 E22 Source Sync Input Output A y H2 Power Other Input D46 D22 Source Sync Input Output D47 G22 Source Sync Input Output ans DE Common Cik Input Outpur D48 D20 Source Sync Input Output HITM E4 Common Clk Input Output D49 D17 Source Sync Input Output TERRE APR Open Drain Output D50 Al4 Source Sync Input Output lGNNE N2 CMOS ASync Input D51 C15 Source Sync Input Output INITA P3 CMOS ASync Input D52 C14 Source Sync Input Output LINTO KL CMOS ASync input D53 B15 Source Sync Input Output LINTI EL CMOS ASyne Input D54 C18 Source Sync Input Output LL_IDQ gt Power Other Output D55 B16 Source Sync Input Output EID ARE Power Other Output D564 Aly Source Sync Input Output LOCK c3 Common Clk Input Output D57 B18 Source Sync Input Output MCERR AB3 Common Clk Input Output D58 C21 Source Sync Input Output BIBA bids Power Other Output D59 B21 Source Sync Input Output M5_IDI vi Power Other Output D60 B19 Source Sync Input Output PECI G5 Power Other Input Output D61 A19 Source Sync Input Output PROCHOT JAR Open Drain Output D62 A22 Source Sync Input Output PWRGOOD RE CMOS ASync Input D63 B22 Source Sync Input Output REQO Ie Source Sync Input Output DB
122. ts greater than Icc pc 2 Not 10096 tested Specified by design characterization Datasheet 27 Table 2 13 Processor Vcc Static and Transient Tolerance 28 intel Electrical Specifications Icc A Vcc max V Vcc ryp V Vcc nin V Notes VID 0 000 VID 0 010 VID 0 020 1 2 3 5 VID 0 006 VID 0 016 VID 0 026 1 2 3 10 VID 0 013 VID 0 023 VID 0 033 1 2 3 15 VID 0 019 VID 0 029 VID 0 039 1 2 3 20 VID 0 025 VID 0 035 VID 0 045 1 2 3 25 VID 0 031 VID 0 041 VID 0 051 1 2 3 30 VID 0 038 VID 0 048 VID 0 058 1 2 3 35 VID 0 044 VID 0 054 VID 0 064 1 2 3 40 VID 0 050 VID 0 060 VID 0 070 1 2 3 45 VID 0 056 VID 0 066 VID 0 076 1 2 3 50 VID 0 063 VID 0 073 VID 0 083 1 2 3 55 VID 0 069 VID 0 079 VID 0 089 1 2 3 60 VID 0 075 VID 0 085 VID 0 095 1 2 3 65 VID 0 081 VID 0 091 VID 0 101 1 2 3 70 VID 0 087 VID 0 097 VID 0 108 1 2 3 75 VID 0 094 VID 0 104 VID 0 114 1 2 3 80 VID 0 100 VID 0 110 VID 0 120 1 2 3 85 VID 0 106 VID 0 116 VID 0 126 1 2 3 90 VID 0 113 VID 0 123 VID 0 133 1 2 3 95 VID 0 119 VID 0 129 VID 0 139 1 2 3 100 VID 0 125 VID 0 135 VID 0 145 1 2 3 105 VID 0 131 VID 0 141 VID 0 151 1 2 3 110 VID 0 138 VID 0 148 VID 0 158 1 2 3 115 VID 0 144 VID 0 154 VID 0 164 1 2 3 120 VID 0 150 VID 0
123. ts within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section 6 1 This signal does not have on die termination and must be terminated on the system board RS 2 0 RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of all processor FSB agents RSP RSP Response Parity is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection It must connect to the appropriate pins of all processor FSB agents A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low While RS 2 0 000 RSP is also high since this indicates it is not being driven by any agent ensuring correct parity SKTOCC SKTOCC Socket occupied will be pulled to ground by the processor to indicate that the processor is present There is no connection to the processor silicon for this signal SMI SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt processors save the
124. uad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to strobes and DBI Data DSTBN Group DSTBP DBI D 15 0 0 0 D 31 16 1 1 D 47 32 2 2 D 63 48 3 3 Furthermore the DBI signals determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inverted and therefore sampled active high DBI 3 0 1 0 DBI 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within within a 16 bit group would have been asserted electronically low the bus agent may invert the data bus signals for that particular sub phase for that 16 bit group DBI 3 0 Assignment to Data Bus Bus Signal Data Bus Signals DBIO D 15 0 DBI1 D 31 16 DBI2 D 47 32 DBI3 D 63 48 DBR DBRZ is used only in systems where no debug port connector is implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive system res
125. uencies Core Frequency to FSB Multiplier Configuration Core Frequency Core Frequency with Notes to FSB Multiplier 400 000 MHz Bus Clock 1 6 2 40 GHz 1 2 3 1 7 2 80 GHz 1 2 1 7 5 3 GHz 1 2 1 8 3 20 GHz 1 2 1 8 5 3 40 GHz 1 2 1 9 3 60 GHz 1 2 1 9 5 3 80 GHz 1 2 1 10 4 GHz 1 2 1 10 5 4 20 GHz 1 2 1 11 4 40 GHz 1 2 1 11 5 4 60 GHz 1 22 1 12 4 80 GHz 1 2 1 12 5 5 GHz 1 2 1 13 5 20 GHz 1 2 NOTES 1 Listed frequencies are not necessarily committed production frequencies 2 For valid processor core frequencies see the Intel Core 2 Extreme processor QX9775 Specification Update 3 The lowest bus ratio supported by the processor is 1 6 15 m n tel Electrical Specifications 2 4 1 Table 2 2 2 4 2 16 Front Side Bus Frequency Select Signals BSEL 2 0 Upon power up the FSB frequency is set to the maximum supported by the individual processor BSEL 2 0 are CMOS outputs which must be pulled up to Vy and are used to select the FSB frequency Refer to Table 2 14 for DC specifications Table 2 2 defines the possible combinations of the signals and the frequency associated with each combination The frequency is determined by the processor s chipset and clock synthesizer All FSB agents must operate at the same core and FSB frequency BSEL 2 0 Frequency Table BSEL2 BSEL1 BSELO Bus Clock Frequency 0 0 0 Reserved 0 0 1 Re
126. umbers differentiate features within each processor family not across different processor families See http www intel com products processor number for details Over time processor numbers will increment based on changes in clock speed cache FSB or other features and increments are not intended to represent proportional or quantitative increases in any particular feature Current roadmap processor number progression is not necessarily representative of future roadmaps See www intel com products processor number for details Intel 64 requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 Processor will not operate including 32 bit operation without an Intel 64 enabled BIOS Performance will vary depending on your hardware and software configurations See http www intel com info em64t for more information including details on which processors support Intel 64 or consult with your system vendor for more information Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality ntel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain platform software enabled for it Functionality perform
127. ve on die termination Datasheet 69 intel Table 4 1 70 Land Listing and Signal Description Signal Definitions Sheet 7 of 11 Name Type Description Notes IGNNE IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is deasserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 CRO is set IGNNEZ is an asynchronous signal However to ensure recognition of this signal following an 1 0 write instruction it must be valid along with the TRDY assertion of the corresponding I O write bus transaction INIT INIT Initialization when asserted resets integer registers inside all processors without affecting their internal caches or floating point registers Each processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins of all processor FSB agents LINT 1 0 LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all FSB agents When the APIC functionality is disabled the LINTO INTR signal becomes INTR a maskable interrupt reque
128. wer Other VSS AL10 Power Other VSS C7 Power Other VSS AL13 Power Other VSS D12 Power Other VSS AL16 Power Other VSS D15 Power Other VSS AL17 Power Other VSS D18 Power Other VSS AL20 Power Other VSS D21 Power Other VSS AL23 Power Other VSS D24 Power Other VSS AL24 Power Other VSS D3 Power Other VSS AL27 Power Other VSS D5 Power Other VSS AL28 Power Other VSS D6 Power Other Datasheet Land Listing and Signal Description Datasheet intel Table 4 1 Land Listing by Land Table 4 1 Land Listing by Land Name Sheet 15 of 17 Name Sheet 16 of 17 Land Name p nee 6 Direction Land Name pon Wu Direction VSS D9 Power Other VSS K7 Power Other VSS E11 Power Other VSS L23 Power Other VSS E14 Power Other VSS L24 Power Other VSS E17 Power Other VSS L25 Power Other VSS E2 Power Other VSS L26 Power Other VSS E20 Power Other VSS L27 Power Other VSS E25 Power Other VSS L28 Power Other VSS E26 Power Other VSS L29 Power Other VSS E27 Power Other VSS L3 Power Other VSS E28 Power Other VSS L30 Power Other VSS E8 Power Other VSS L6 Power Other VSS F1 Power Other VSS L7 Power Other VSS F10 Power Other VSS M1 Power Other VSS F13 Power Other VSS M7 Power Other VSS F16 Power Other VSS N3 Power Other VSS F19 Power Other VSS N6 Power Other VSS F22 Power Other VSS N7 Powe

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