Samsung M378T5663EH3-CE6 memory module
Contents
1. DDR2 800 DDR2 667 Parameter Symbol Units Notes min max min max Four Activate Window for 1KB page size products tFAW 35 D 37 5 x ns 32 Four Activate Window for 2KB page size products tFAW 45 x 50 x ns 32 CAS to CAS command delay tCCD 2 x 2 x nCK Write recovery time tWR 15 x 15 x ns 32 Auto precharge write recovery precharge time tDAL WR tnRP x WR tnRP x nCK 33 Internal write to read command delay tWTR 75 x 7 5 x ns 24 32 Internal read to precharge command delay tRTP 7 5 x 7 5 x ns 3 32 Exit self refresh to a non read command tXSNR tRFC 10 D tRFC 10 x ns 32 Exit self refresh to a read command tXSRD 200 x 200 D nCK Exit precharge power down to any command DP 2 x 2 x nCK Exit active power down to read command tXARD 2 D 2 x nCK 1 SEN elu read command tXARDS 8 AL x 7 AL x nCK 1 2 CKE minimum pulse width HIGH and LOW pulse width tCKE 3 D 3 x nCK 27 ODT turn on delay tAOND 2 2 2 2 nCK 16 ODT turn on tAON tAC min tAC max 0 7 tAC min tAC max 0 7 ns 6 16 40 ODT turn on Power Down mode tAONPD tAC min 2 Bees tAC min 2 und ns ODT turn off delay tAOFD 2 5 2 5 2 5 2 5 DCK 17 45 ODT turn off tAOF tAC min tAC max 0 6 tAC min tAC max 0 6 ns 17 43 45 ODT turn off Power Down mode tAOFPD tAC min 2 Sen tAC min 2 tre ns ODT to power down entry latency tANPD 3 x 3 x nCK ODT power down exit latency tAXPD 8 x 8 x nCK OCD drive mode output delay tOIT 0 12 0 12 ns 322. 14 10 5 AC Input Test Conditions eeneg 14 11 0 IDD Specification Parameters Definition ccccceeeeeeeeeeeeeeeeeneeeeeeeeeeeeeeeeeeeeeeeeeeeeaeeeeaneeees 15 12 0 Operating Current E 16 12 1 M378T2863EHS 1GB 128Mx8 8 Module ssnssssssnssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnna 16 12 2 M378T5663EH3 2GB 128Mx8 16 Module sssssssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnna 16 12 3 M391T2863EH3 1GB 128Mx8 9 ECC Module sssssssssnnsnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnna 17 12 4 M391T5663EH3 2GB 128Mx8 18 ECC Module sssssssssnsnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnna 17 12 5 M378T6464EHS 512MB 64Mx16 4 Module EEN EER EEN EENEERNENEER NEE nnn eee RNEEN ENEE ENEE EE 18 Klaue dee 19 14 0 Electrical Characteristics amp AC Timing for DDR2 800 667 cccseeeceeeeeeeeeeeeeeeeeeeeeseeeeees 19 14 1 Refresh Parameters by Device Density ee RRE eene enne nnn nnn nnn nnn nnn nnn nnn nnn nnn nnn 19 14 2 Speed Bins and CL tRCD tRP tRC and tRAS for Corresponding Bin ccce esee nennen 19 14 3 Timing Parameters by Speed Grade eceoene c entente rao nn mnn nan u ein hn rn rua Ex cosas XR ESRRREERASRN EA mnnn nnmnnn nnmnnn 20 15 0 Physical Dimensions eege Eege dE eeng EE Eegen 22 15 1 128Mbx8 based 128Mx64 Module 1 Rank cs
3. 4 0 x64 DIMM Pin Configurations Front side Back side eene 5 5 0 x72 DIMM Pin Configurations Front side Back side eeeeeeeeeeeeeeeeeenneeee 6 6 0 Pin ries ett MM M 6 7 0 Input Output Function E VT e Le E 7 8 0 Functional Block Diagrami EE 8 8 1 1GB 128Mx64 Module M378T2863EHS 2 2 2cececeeeee cence cee eee cece eee eee enar ee esas senna sees eee eee 8 8 2 1GB 128Mx72 ECC Module M391T2863EH3 EEN ENEE c eee c eee cece NEEN EEN cease eneeseseeeeeeeeseeeeenes 9 8 3 2GB 256Mx64 Module M378T5663EH3 2 2 2ceceeec senescence e eee eee ence cece eee nennen ntn nhan nen h ann nrn nnn 10 8 4 2GB 256Mx72 ECC Module M391T5663EH3 ERKENNEN ENEE EEN EEN ENNEN unn nnn ENEE REENEN 11 8 5 512MB 64Mx64 Module M378T6464EHS see EE ENEE R NENNEN EEN cece ence ENEE EEN EEN EE 12 9 0 Absolute Maximum DC Ratings 2 2 2 ccccccccececeseesessnanenansnnenesencecneeeeceeeeeeceeeseeesecenenanncnenes 13 10 0 AC amp DC Operating Conditions eessen eege Eed EES 13 10 1 Recommended DC Operating Conditions SSTL 1 8 sccccsssseceseeeeeeeeeeeeeeeeeeeeeeneeseeeeneeseeesseeneeeees 13 10 2 Operating Temperature Condition eese eee eee eene nennen nnn nn nnn nn hn an nsa EEN KENE asas nsus annua 14 90 3 Input DC Logic Level erc M H ET 14 10 4 input AC Logic me
4. DM CS Dos DAs DM CS DOS DASI DM CS Das DQS DM CS DOS DQS DQ0 wH 1 00 O 0 DQ32 w 1 00 1 0 0 DQ1 w 1 01 DO O 1 D9 DQ33 w 1 01 D4 1 0 1 D13 DQ2 w 4 1 02 O 2 DQ34 w 1 0 2 0 2 DQ3 w 1 03 O 3 DQ35 w 1 0 3 03 DQ4 w 1 04 O 4 DQ36 w 1 0 4 1 0 4 DQ5 w 4 1 05 O 5 DQ37 Ww 1 05 1 05 DOG w 1 06 O 6 DQ38 w 1 06 1 0 6 DQ7 w 1 07 O 7 DQ39 r 1 07 1 07 DQS1 W DQS5 DQS1 a DQS5 NS DM1 M DM5 WS DM CS Dos DAs DM CS Dos DOSI DM CS Dos DQS DM CS Dos DOSI DQ8 w 1 00 O 0 DQ40 1 00 1 0 0 DQ9 w 1 01 D1 O 1 D10 DQ41 w 1 0 1 D5 1 0 1 D14 DQ10 w 1 02 O 2 DQ42 w 1 02 1 0 2 DQ11 w 1 03 O 3 DQ43 w 1 0 3 03 DQ12 A 1 04 0 4 DQ44 A 1 04 1 0 4 DQ13 w 1 05 O 5 DQ45 wr 1 05 1 05 DQ14 wr 1 06 O 6 DQ46 w 1 06 1 0 6 DQ15 w 1 07 O7 DQ47 w 1 07 1 07 DQS2 WS a DQS6 VW DQS2 L DQS6 WS e DM2 W T DM6 W DM CS Dos DQS DM CS pas DQS DM CS Dos DQS DM CS pas DOS DQ16 w 1 00 O 0 DQ48 w 1 00 1 0 0 DQ17 wH 1 01 D2 O 1 D11 DQ49 wH 1 01 D6 01 D15 DQ18 w 1 02 O 2 DQ50 w 1 02 02 DQ19 A 1 0 3 O 3 DQ51 1 0 3 03 DQ20 wr 1 0 4 O 4 DQ52 w 1 0 4 1 0 4 DQ21 w 1 05 O 5 DQ53 A 1 05 1 05 DQ22 A 1 06 O 6 DQ54 w j 1 06 1 0 6 DQ23 r 1 07 O7 DQ55 w 1 07 VOT DQS3 WwW DQS7 Nr DQS3 A DQS7 W DM3 T DM7 AN DM CS Dos DQS DM CS Das Das DM CS Das DQS DM CS bas DQS DQ24 w 1
5. DM CS Dos Dos DM CS Dos Das DM CS Dos Das DQ8 w 1 00 1 0 0 DQ40 1 0 0 1 0 0 DQ9 w 1 01 D1 VO 1 D9 DQ41 w 1 01 D5 VO 1 D13 DQ10 1 0 2 1 0 2 DQ42 w 1 02 1 0 2 DQ11 w 1 03 1 03 DQ43 w 1 03 03 DQ12 1 04 1 0 4 DQ44 wr 1 04 1 0 4 DQ13 w4 1 05 1 05 DQ45 AA 1 05 05 DQ14 w 1 06 1 0 6 DQ46 wr 1 06 1 0 6 DQ15 wr4 1 07 1 07 DQ47 ww 1 07 1 07 DQS6 WS DQS6 NAE e eSI DM6 w DM CS Das DOS DM CS bas DOS DM CS Das Das DM CS Dos Das DQ16 w 1 00 1 0 0 DQ48 w 1 00 1 0 0 DQ17 w 1 01 D2 01 D10 DQ49 w 1 01 D6 01 D14 DQ18 w 1 02 1 0 2 DQ50 wr 1 02 02 DQ19 Wwr 1 03 1 0 3 DQ51 w 1 03 1 0 3 DQ20 wr 1 04 1 0 4 DQ52 w 1 0 4 1 0 4 DQ21 w 1 05 VO5 DQ53 wr lO 5 V05 DQ22 w 1 06 1 0 6 DQ54 w 1 06 1 0 6 DQ23 w 1 07 1 07 DQ55 AA 1 07 1 07 DQS7 AN MA DQS7 AN Nr DM7 DM CS Dos DQS DM CS Das DO DM CS Dos DQS DM CS Dos Das DQ24 w 1 00 1 0 0 DQ56 l O 0 1 0 0 DQ25 w 1 01 D3 I O 1 D11 DQ57 w 1 01 D7 1 0 1 D15 DQ26 w _ 1 0 2 VO 2 DQ58 w 1 0 2 1 0 2 DQ27 Ww 1 03 VO3 DQ59 w 1 03 1 0 3 DQ28 w 1 04 I O 4 DQ60 v 1 04 1 0 4 DQ29 w 1 05 1 05 DQ61 y r4 1 05 1 05 DQ30 w 1 06 1 0 6 DQ62 wvH 1 06 1 0 6 DQ31 w4 1 07 VO7 DQ63 r lO 7 1 07 Vppspp Serial PD RTE DO D15 goe Serial PD VREF DO D15 WP Le SDA Se AO A1 A2 Vss R ee Clock Wiring SAO SA1 SA2 BA2 JQ BA0 BA2 DDR2 SDRAMs DO D15 Clock Input
6. VSWING MAX Input signal maximum peak to peak swing 1 0 V 1 SLEW Input signal minimum slew rate 1 0 Vins 2 3 Notes 1 Input waveform timing is referenced to the input signal crossing through the Vip AC level applied to the device under test 2 The input signal minimum slew rate is to be maintained over the range from Vp_r to Viy AC min for rising edges and the range from Vggr to Mu AC max for falling edges as shown in the below figure 3 AC timings are referenced with input waveforms switching from Vi AC to Vi AC on the positive transitions and Vj AC to Vi AC on the negative transitions Vppa Vi AC min Vj DC min V SWING MAX Veer Vi DC max Vii AC max Vss delta TF delta TR Veer VL AC Viu AC min V Falling Slew EE VL AC max Rising Slew HAC min Veer delta TF delta TR lt AC Input Test Signal Waveform gt um 14 of 25 Rev 1 02 October 2008 ELECTRONICS UDIMM DDR2 SDRAM 11 0 IDD Specification Parameters Definition IDD values are for full operating range of Voltage and Temperature Symbol Proposed Conditions Units Note Operating one bank active precharge current IDDO tCK tCK IDD tRC tRC IDD tRAS tRASmin IDD CKE is HIGH CS is HIGH between valid commands mA Address bus inputs are SWITCHING Data bus inputs are SWITCHING Operating one bank active read precharge current IOUT OmA BL 4 CL CL IDD AL
7. 0 tCK tCK IDD tRC tRC IDD tRAS tRASmin IDD tRCD tRCD IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data pattern is same as IDD4W IDD1 mA Precharge power down current IDD2P All banks idle tCK tCK IDD CKE is LOW Other control and address bus inputs are STABLE Data bus inputs are mA FLOATING Precharge quiet standby current an IDD2Q All banks idle tCK tCK IDD CKE is HIGH CS is HIGH Other control and address bus inputs are STABLE Data mA bus inputs are FLOATING Precharge standby current IDD2N All banks idle tCK tCK IDD CKE is HIGH CS is HIGH Other control and address bus inputs are SWITCHING mA Data bus inputs are SWITCHING Active power down current Fast PDN Exit MRS 12 0 mA IDD3P All banks open tCK tCK IDD CKE is LOW Other control and address bus inputs are STABLE Data bus inputs are FLOATING Slow PDN Exit MRS 12 1 mA Active standby current IDD3N All banks open tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid mA commands Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING Operating burst write current All banks open Continuous burst writes BL 4 CL CL IDD AL 0 tCK tCK IDD tRAS tRASmax IDD tRP IDDAW tRP IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data bus inputs mA are
8. DDR2 SDRAMs A13 w gt A0 A13 DDR2 SDRAMs DO D15 CKO CKO 4 DDR2 SDRAMs CKEO CKE DDR2 SDRAMs D0 D7 CK1 CK1 6 DDR2 SDRAMs CKE1 CKE DDR2 SDRAMs D8 D15 CK2 CK2 6 DDR2 SDRAMs RAS w RAS DDR2 SDRAMs DO D15 Wire per Clock Loading CAS unn CAS DDR2 SDRAMs DO D15 EE Ee WE w WE DDR2 SDRAMs DO D15 oon GE jen EDU AUAM Sd 2 BAX Ax RAS CAS WE resistors 7 5 Ohms 4 5X ODT1 ODT DDR2 SDRAMs D8 D15 i ES Web St ELECTRONICS 10 of 25 Rev 1 02 October 2008 UDIMM DDR2 SDRAM 8 4 2GB 256Mx72 ECC Module M391T5663EH3 Populated as 2 ranks of x8 DDR2 SDRAMs 1 So DQSO WS DQS4 MN e DQSO W DQS4 MN e DMO T DM4 WW
9. Rev 1 02 October 2008 ELECTRONICS UDIMM DDR2 SDRAM 13 0 Input Output Capacitance Vpp 1 8V Vppq 1 8V Ta 25 C Parameter Min Max Min Max Min Max Non ECC REM M378T2863EHS M378T5663EH3 M378T6464EHS ae CCKO 24 26 22 Input capacitance CK and CK CCK1 E 25 E 28 24 CCK2 25 28 24 pF Input capacitance CKE and CS CH 42 42 34 Input capacitance Addr RAS CAS WE CI2 42 42 S 34 Input output capacitance DQ DM DQS DQS CIO 6 10 6 ECC M391T2863EH3 M391T5663EH3 Units FE CCKO 25 28 Input capacitance CK and CK CCK1 R 25 28 CCK2 25 28 pF Input capacitance CKE and CS Cl 44 44 Input capacitance Addr RAS CAS WE Clo 44 44 Input output capacitance DQ DM DQS DQS CIO 6 10 Note DM is internally loaded to match DQ and DQS identically 14 0 Electrical Characteristics amp AC Timing for DDR2 800 667 0 C Toper lt 95 C Vppg 1 8V 0 1V Vpp 1 8V 0 1V 14 1 Refresh Parameters by Device Density Parameter Symbol 256Mb 512Mb 1Gb 2Gb 4Gb Units Refresh to active Refresh command time tRFC 75 105 127 5 195 327 5 ns 0 C lt Tease lt 85 C 7 8 7 8 7 8 7 8 7 8 us Average periodic refresh interval tREFI 85 C lt Tease lt 95 C 3 9 3 9 3 9 3 9 3 9 us 14 2 Speed Bins and CL tRCD tR
10. The used device is 128M x8 DDR2 SDRAM FBGA DDR2 SDRAM Part NO KAT1G084QE 22 of 25 Rev 1 02 October 2008 ELECTRONICS UDIMM DDR2 SDRAM 15 2 128Mbx8 based 128Mx72 Module 1 Rank M391T2863EH3 Units Millimeters 133 35 e gt 131 35 Iw gt E 128 95 J X a ECC qt H e for x72 SPD D 30 00 J C g A EA e 2 B 2 50 A B 63 00 R LA 55 00 d 27 oW o ym o 7 gt C D 1 2702 0 10 7 4 3 00 5 00 S pg y 4 00 p 0 80 0 05 gt 4 00 p E mi pE lt _ gt 1 a 1 L N bh 3 80 0 20 t A S SCH i 4 00 1 50 0 10 ue LL 2 Detail A Detail B The used device is 128M x8 DDR2 SDRAM FBGA DDR2 SDRAM Par
11. avg Data out high impedance time from CK CK tHZ x tAC max x tAC max ps 18 40 DQS DQS low impedance time from CK CK tLZ DQS tAC min tAC max tAC min tAC max ps 18 40 DQ low impedance time from CK CK tLZ DQ 2 tAC min tAC max 2 tAC min tAC max ps 18 40 DQS DQ skew for DQS and associated DQ signals tDQSQ x 200 x 240 ps 13 DQ hold skew factor tQHS x 300 x 340 ps 38 DQ DQS output hold time from DQS tQH tHP tQHS x tHP tQHS x ps 39 DQS latching rising transitions to associated clock edges tDQSS 0 25 0 25 0 25 0 25 tCK avg 30 DQS input HIGH pulse width tDQSH 0 35 x 0 35 x tCK avg DOS input LOW pulse width tDQSL 0 35 x 0 35 x tCK avg DQS falling edge to CK setup time tDSS 0 2 x 0 2 x tCK avg 30 DQS falling edge hold time from CK tDSH 0 2 x 0 2 x tCK avg 30 Mode register set command cycle time tMRD 2 x 2 x nCK MRS command to ODT update delay tMOD 0 12 0 12 ns 32 Write postamble tWPST 0 4 0 6 0 4 0 6 tCK avg 10 Write preamble tWPRE 0 35 x 0 35 x tCK avg Address and control input hold time tiH base 250 x 275 x ps 5 7 9 23 29 Address and control input setup time tlS base 175 x 200 x ps 5 7 9 22 29 Read preamble tRPRE 0 9 1 1 0 9 1 1 tCK avg 19 41 Read postamble tRPST 0 4 0 6 0 4 0 6 tCK avg 19 42 Activate to activate command period for 1KB page size products tRRD 7 5 x 7 5 x ns 4 32 Activate to activate command period for 2KB page size products tRRD 10 x 10 x ns 4 32 20 of 25 Rev 1 02 October 2008 UDIMM DDR2 SDRAM
12. 00 O 0 DQ56 1 00 1 0 0 DQ25 w 1 01 D3 O 1 D12 DQ57 1 01 D7 1 0 1 D16 DQ26 w 1 02 O 2 DQ58 yw 1 02 1 0 2 DQ27 Ww 1 03 O 3 DQ59 w 1 03 03 DQ28 w 1 0 4 O 4 DQ60 w 1 0 4 1 0 4 DQ29 y 1 05 O 5 DQ61 w 1 05 05 DQ30 wr 1 06 O 6 DQ62 wr 1 06 1 0 6 DQ31 w j 1 07 O 7 DQ63 w 1 0 7 1 07 DQS8 WW DQS8 A DM8 l Serial PD DM CS Das DAS DM CS Dos Das SCL WP m gt SDA CBO w 1 00 O 0 AO A1 CB1 w4 1 01 D8 O1 DAT A2 CB2 w 1 02 O 2 CB3 w 1 03 O 3 SAO SA1 SA2 CB4 w 1 04 O 4 CB5 Ww 1 05 O 5 Clock Wiring CB6 w 1 06 O 6 CB7 w 1 07 O 7 Clock Input DDR2 SDRAMs CKO CKO 6 DDR2 SDRAMs BAO0 BA2 vw BAO BA2 DDR2 SDRAMs D0 D17 VppsPp t Serial PD T CK1 CK1 6 DDR2 SDRAMs NW r A0 A13 CKO AO A13 A0 A13 DDR2 SDRAMs DO D17 VopVopa m DO D17 CK2 CK2 6 DDR2 SDRAMs CKEO CKE DDR2 SDRAMs DO D8 V D DO D17 Wire per Clock Loading CKE1 CKE DDR2 SDRAMs D9 D17 REF BR Table Wiring Diagrams WM RAS RAS DDR2 SDRAMs D0 D17 Vee 4 d 4 DO D17 CAS w CAS DDR2 SDRAMs DO D17 Note NEST ee eee eee ee 1 DQ DM DQS DQS resistors 22 Ohms 5 eege 2 BAx Ax RAS CAS WE resistors 7 5 Ohms 5 ODT1 ODT DDR2 SDRAMs D9 D17 11 of 25 Rev 1 02 October 2008 ELECTRONICS UDIMM 8 5 512MB 64Mx64 Module M378T6464EHS Populat
13. 07 DQS2 UDO DQS6 w UDQS DQS2 w UDOS DQS6 w UDOS DM2 w UDM DM6 w UDM DQ16 w 1 0 8 DQ48 w 1 0 8 DQ17 w 1 0 9 DQ49 w 1 09 DQ18 w 1 0 10 DQ50 wr4 1 0 10 DQ19 w 1 0 11 DQ51 w4 1 0 11 DQ20 WW 1 0 12 DQ52 wr4 1 0 12 DQ21 wr 1 0 13 DQ53 wr 1 0 13 DQ22 w 1 0 14 DQ54 w 1 0 14 DQ23 y wr 1 0 15 DQ55 yw 1 0 15 Vodeb Serial PD Clock Wiring Clock Input DDR2 SDRAMs Vop Vppa DO D3 Serial PD CKO CKO NC SCL VREF DO D3 CK1 CK1 2 DDR2 SDRAMs WP m gt SDA a CK2 CK2 2 DDR2 SDRAMs AO A1 A2 Vss ad DO D3 Wire per Clock Loading SAO SA1 SA2 Table Wiring Diagrams BAO BA1 w BAO BA1 DDR2 SDRAMs DO D3 A0 A12 w A0 A12 DDR2 SDRAMs DO D3 CKEO CKE DDR2 SDRAMs DO D3 Not otes RAS Ar RAS DDR2 SDRAMs D0 D3 1 DQ DM DQS DQS resistors 22 Ohms 5 CAS w CAS DDR2 SDRAMs DO D3 4 BAx Ax RAS CAS WE resistors 10 Ohms 5 WE wW WE DDR2 SDRAMs D0 D3 ODTO ODT DDR2 SDRAMs DO D3 ELECTRONICS 12 of 25 Rev 1 02 October 2008 UDIMM DDR2 SDRAM 9 0 Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes Vpp Voltage on Vpp pin relative to Vss 10V 2 3V V 1 Vppo Voltage on Vppg pin relative to Vss 0 5V 2 3V V 1 Von Voltage on Vpp
14. 08 DQ44 119 SDA 239 SAO 30 DQ18 150 DQ23 60 A5 180 A6 89 DQ40 209 DQ45 120 SCL 240 SA1 90 DQ41 210 Vss NC No Connect RFU Reserved for Future Use 1 Pin196 A13 is used for x4 x8 base Unbuffered DIMM 2 The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products DIMMs 6 0 Pin Description Pin Name Description Pin Name Description A0 A13 DDR2 SDRAM address bus CKO CK1 CK2 DDR2 SDRAM clocks positive line of differential pair BAO BA2 DDR2 SDRAM bank select CKO CK1 CK2 DDR2 SDRAM clocks negative line of differential pair RAS DDR2 SDRAM row address strobe SCL I C serial bus clock for EEPROM CAS DDR2 SDRAM column address strobe SDA I2C serial bus data line for EEPROM WE DDR2 SDRAM wirte enable SA0 SA2 I2C serial address select for EEPROM So 1 DIMM Rank Select Lines Von DDR2 SDRAM core power supply CKEO CKE1 DDR2 SDRAM clock enable lines Vppq DDR2 SDRAM UO Driver power supply ODTO ODT1 On die termination control lines VREF DDR2 SDRAM UO reference supply DQO DQ63 DIMM memory data bus Vss Power supply return ground CBO CB7 DIMM ECC check bits VppsPp Serial EEPROM positive power supply DQSO0 DQS8 DDR2 SDRAM data strobes NC Spare Pins no connect DM 0 8 DDR2 SDRAM data masks RESET Not used on UDIMM DQso Dass DDR2 SDRAM differential data strobes TEST SE EE Bos The Vpp and Vppgo pins are tied to t
15. 1 00 DQ48 W 1 0 0 DQ17 Ww 1 01 D2 DQ49 w 1 0 1 D6 DA18 w 1 0 2 DQ50 wr 1 0 2 DQ19 w 1 03 DQ51 w 1 03 DQ20 w 1 0 4 DQ52 w 1 0 4 DQ21 w 1 05 DQ53 w 1 0 5 DQ22 wr 1 0 6 DQ54 w 1 06 DQ23 wr 1 07 DQ55 w 1 0 7 DQs3 W DQS7 W DQS3 v DQS7 S DND 4 DM7 DM CS DOS Das DM CS Das DOS DQ24 w 1 0 0 DQ56 1 0 0 DQ25 w 1 0 1 D3 DQ57 Ww 1 0 1 D7 DQ26 v 1 0 2 DQ58 w 1 0 2 DQ27 Ww 1 0 3 DQ59 W 1 0 3 DQ28 w 1 0 4 DQ60 1 0 4 DQ29 1 05 DQ61 w 1 05 DQ30 wr 1 06 DQ62 w 1 06 DQ31 wr 1 07 DQ63 1 07 DQS8 w Dass w DM8 w Serial PD DM CS Dos DOS SCL E WP k SDA CB0 w4 1 00 CB1 w 1 01 D8 BN Uu ME CB2 w 1 02 CB3 w 1 03 SAO SA1 SA2 CB4 w 1 04 CBS w 1 05 Clock Wiring CB6 w 1 06 CRT Ww 1 07 Voperp SerialPD Clock Input DDR2 SDRAMs Vpp Vppa DO D8 CKO CKO 3 DDR2 SDRAMs CK1 CK1 3 DDR2 SDRAMs BAO BA2 w BAO BA2 DDR2 SDRAMs DO D8 VREF DO D8 CK2 CK2 3 DDR2 SDRAMs T A0 A13 gt A0 A13 DDR2 SDRAMs DO D8 Ves l i l SE Wire per Clock Loading RAS inn RAS DDR2 SDRAMs DO D8 Table Wiring Diagrams CAS di CAS DDR2 SDRAMs DO D8 CKE0 gt CKE DDR2 SDRAMs DO D8 Note geo 1 DQ DM DQS DQS resistors 22 Ohms 5 DAO PAG NIE H WE ROME DDR2 SDRAMS EE 2 BAx Ax RAS CAS WE re
16. 1 CKE1 80 DQ32 200 DQ37 111 DQ57 231 Vss 22 DQ11 142 Vss 52 CKEO 172 Von 81 DQ33 201 Vss 112 Vss 232 DM7 23 Vss 143 DQ20 53 Von 173 NC 82 Vss 202 DM4 113 DQS7 233 NC 24 DQ16 144 DQ21 54 BA2 174 NC 83 Das4 203 NC 114 DQS7 234 Vss 25 DQ17 145 Vss 55 NC 175 Vppa 84 DQS4 204 Vss 115 Vss 235 DQ62 26 Vss 146 DM2 56 VDDQ 176 A12 85 Vss 205 DQ38 116 DQ58 236 DQ63 27 DQS2 147 NC 57 A11 177 A9 86 DQ34 206 DQ39 117 DQ59 237 Vss 28 DQS2 148 Vss 58 AT 178 Vpp 87 DQ35 207 Vss 118 Vss 238 Vppspp 29 Vss 149 DQ22 59 Von 179 A8 88 Vss 208 DQ44 119 SDA 239 SAO 30 DQ18 150 DQ23 60 A5 180 A6 89 DQ40 209 DQ45 120 SCL 240 SA1 90 DQ41 210 Vss NC No Connect RFU Reserved for Future Use 1 Pin196 A13 is used for x4 x8 base Unbuffered DIMM 2 The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products DIMMs um 5 of 25 Rev 1 02 October 2008 ELECTRONICS UDIMM DDR2 SDRAM 5 0 x72 DIMM Pin Configurations Front side Back side Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF 121 Vss 31 DQ19 151 Vss 61 A4 181 Vppa 91 Vss 211 DM5 2 Vss 122 DQ4 32 Vss 152 DQ28 62 Vopo 182 A3 92 DQS5 212 NC 3 DQO 123 DQ5 33 DQ24 153 DQ29 63 A2 183 A1 93 DQS5 213 Vss 4 DQ1 124 Vss 34 DQ25 154 Vss 64 Von 184 Von 94 Vss 214 DQ46 5 Vss 125 DMO 35 Vss 155 DM3 KEY 95 DQ42 215 DQ47 6 DQSO 126 NC 36 DQS3 156 NC 6
17. 13 wW gt RAS N CAS N CKE0 WE wV ODTO SA2 BAO BA2 DDR2 SDRAMs DO D7 A0 A13 DDR2 SDRAMs DO D7 RAS DDR2 SDRAMs D0 D7 CAS DDR2 SDRAMs D0 D7 CKE DDR2 SDRAMs DO D7 Vppspp Vpp Vppa VREF Vss WE DDR2 SDRAMs DO D7 ODT DDR2 SDRAMs DO D7 DQs4 DQs4 DM W DQS5 DQS5 DQ32 WH DQ33 WH DQ34 Ww DQ35 Ww DQ36 DQ37 Ww DQ38 DQ39 DM 1 0 0 VO 1 VO2 y o 3 VO4 1 05 1 0 6 1 07 CS Dos DOSI D4 DMS w DQS6 DQS6 DQ40 wH DQ41 Ww DQ42 WH DQ43 Ww DQ44 wr DQ45 wr DQ46 wr DQ47 wr DM 1 0 0 VO 1 VO2 1 0 3 1 0 4 1 05 1 0 6 1 07 CS Dos DO D5 Ws MW DM yw DQS7 DQS7 DM7 Note DQ48 A DQ49 WH DQ50 WH DQ51 Ww DQ52 Ww DQ53 Ww DQ54 wr DQ55 ww DM 1 0 0 VO 1 VO2 1 03 1 0 4 1 05 lO 6 1 07 CS Dos DOS D6 A WM DQ56 WH DQ57 WH DQ58 Ww DQ59 Ww DQ60 Ww DQ61 yw DQ62 Ww DQ63 wr DM 1 0 0 VO 1 VO2 1 03 I O 4 1 05 1 0 6 1 07 CS Dos DQS D7 Serial PD D0 D7 Clock Wiring DO D7 Clock Input DDR2 SDRAMs bob CKO CKO 2 DDR2 SDRAMs CK1 CK1 3 DDR2 SDRAMs CK2 CK2 3 DDR2 SDRAMs Wire per Cl
18. 25 Rev 1 02 October 2008 am ELECTRONICS UDIMM DDR2 SDRAM 4 0 x64 DIMM Pin Configurations Front side Back side Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF 121 Vss 31 DQ19 151 Vss 61 A4 181 Vopo EN Vss 211 DM5 2 Vss 122 DQ4 32 Vss 152 DQ28 62 Vppa 182 A3 92 Dass 212 NC 3 DQO 123 DQ5 33 DQ24 153 DQ29 63 A2 183 A1 93 DQS5 213 Vss 4 DQ1 124 Vss 34 DQ25 154 Vss 64 Von 184 Vpp 94 Vss 214 DQ46 5 Vss 125 DMO 35 Vss 155 DM3 KEY 95 DQ42 215 DQ47 6 Daso 126 NC 36 DQS3 156 NC 65 Vss 185 CKO 96 DQ43 216 Vss 7 DQSO 127 Vss 37 DQS3 157 Vss 66 Vss 186 CKO 97 Vss 217 DQ52 8 Vss 128 DQ6 38 Vss 158 DQ30 67 Von 187 Von 98 DQ48 218 DQ53 9 DQ2 129 DQ7 39 DQ26 159 DQ31 68 NC 188 AO 99 DQ49 219 Vss 10 DQ3 130 Vss 40 DQ27 160 Vss 69 Von 189 Von 100 Vss 220 CK2 11 Vss 131 DQ12 41 Vss 161 NC 70 A10 AP 190 BA1 101 SA2 221 CK2 12 DQ8 132 DQ13 42 NC 162 NC 71 BAO 191 VDDQ 102 NC TEST 222 Vss 13 DQ9 133 Vss 43 NC 163 Vss 72 VDDQ 192 RAS 103 Vss 223 DM6 14 Vss 134 DM1 44 Vss 164 NC 73 WE 193 SO 104 DQS6 224 NC 15 DQS1 135 NC 45 NC 165 NC 74 CAS 194 Vopo 105 DQS6 225 Vss 16 DOS 136 Vss 46 NC 166 Vss 75 Vppa 195 ODTO 106 Vss 226 DQ54 17 Vss 137 CK1 47 Vss 167 NC 76 S1 196 A131 107 DQ50 227 DQ55 18 NC 138 CK1 48 NC 168 NC 77 ODT1 197 Von 108 DQ51 228 Vss 19 NC 139 Vss 49 NC 169 Vss 78 VDDQ 198 Vss 109 Vss 229 DQ60 20 Vss 140 DQ14 50 Vss 170 Vppa 79 Vss 199 DQ36 110 DQ56 230 DQ61 21 DQ10 141 DQ15 51 VDDQ 17
19. 464 440 mA IDD2P 80 80 80 mA IDD2Q 184 184 184 mA IDD2N 224 224 216 mA IDD3P F 208 208 200 mA IDD3P S 120 120 120 mA IDD3N 296 296 280 mA IDD4W 576 576 520 mA IDD4R 720 720 640 mA IDD5 960 960 920 mA IDD6 80 80 80 mA IDD7 1 360 1 360 1 240 mA Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap 12 2 M378T5663EH3 2GB 128Mx8 16 Module TA 0 C Vpp 1 9V 800 CL 5 800 CL 6 667 CL 5 Symbol Units Notes CE7 CF7 CE6 IDDO 640 640 616 mA IDD1 688 688 656 mA IDD2P 160 160 160 mA IDD2Q 368 368 368 mA IDD2N 448 448 432 mA IDD3P F 416 416 400 mA IDD3P S 240 240 240 mA IDD3N 520 520 496 mA IDD4W 800 800 736 mA IDD4R 944 944 856 mA IDD5 1 184 1 184 1 136 mA IDD6 160 160 160 mA IDD7 1 584 1 584 1 456 mA Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap Rev 1 02 October 2008 ELECTRONICS UDIMM DDR2 SDRAM 12 3 M391T2863EH3 1GB 128Mx8 9 ECC Module Ta 0 C Vpp 1 9V 800 CL 5 800 CL 6 667 CL 5 Symbol Units Notes CE7 CF7 CES IDDO 468 468 450 mA IDD1 522 522 495 mA IDD2P 90 90 90 mA IDD2Q 207 207 207 mA IDD2N 252 252 243 mA IDD3P F 234 234 225 mA IDD3P S 135 135 135 mA IDD3N 333 333 315 mA IDD4W 648 648 585 mA IDD4R 810 810 720 mA IDD
20. 5 1 080 1 080 1 035 mA IDD6 90 90 90 mA IDD7 1 530 1 530 1 395 mA Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap 12 4 M391T5663EH3 2GB 128Mx8 18 ECC Module Ta 0 C Vpp 1 9V 800 CL 5 800 CL 6 667 CL 5 Symbol Units Notes CE7 CF7 CE6 IDDO 720 720 693 mA IDD1 774 774 738 mA IDD2P 180 180 180 mA IDD2Q 414 414 414 mA IDD2N 504 504 486 mA IDD3P F 468 468 450 mA IDD3P S 270 270 270 mA IDD3N 585 585 558 mA IDD4W 900 900 828 mA IDD4R 1 062 1 062 963 mA IDD5 1 332 1 332 1 278 mA IDD6 180 180 180 mA IDD7 1 782 1 782 1 638 mA Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap Rev 1 02 October 2008 ELECTRONICS UDIMM DDR2 SDRAM 12 5 M378T6464EHS 512MB 64Mx16 4 Module TA 0 C Vpp 1 9V Symbol 800 CL 5 800 CL 6 667 CL 5 US MS CE7 CF7 CE6 IDDO 260 260 240 mA IDD1 300 300 280 mA IDD2P 40 40 40 mA IDD2Q 100 100 100 mA IDD2N 128 128 120 mA IDD3P F 112 112 108 mA IDD3P S 60 60 60 mA IDD3N 160 160 148 mA IDDAW 380 380 360 mA IDDAR 500 500 460 mA IDD5 460 460 440 mA IDD6 40 40 40 mA IDD7 800 800 740 mA Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap um 18 of 25
21. 5 Vss 185 CKO 96 DQ43 216 Vas 7 DQSO 127 Vss 37 DQS3 157 Vss 66 Vss 186 CKO 97 Vss 217 DQ52 8 Vss 128 DQ6 38 Vss 158 DQ30 67 Vpp 187 Von ER DQ48 218 DQ53 9 DQ2 129 DQ7 39 DQ26 159 DQ31 68 NC 188 AO 99 DQ49 219 Vss 10 DQ3 130 Vss 40 DQ27 160 Vss 69 Von 189 Von 100 Vss 220 CK2 11 Vss 131 DQ12 41 Vss 161 CB4 70 A10 AP 190 BA1 101 SA2 221 CK2 12 DQ8 132 DQ13 42 CBO 162 CB5 71 BAO 191 Vppa 102 NC TEST 222 Vss 13 Dag 133 Ves 43 CB1 163 Vss 72 VDDQ 192 RAS 103 Vss 223 DM6 14 Vss 134 DM1 44 Vss 164 DM8 73 WE 193 So 104 DQS6 224 NC 15 DQS1 135 NC 45 Dass 165 NC 74 CAS 194 Vppa 105 DQS6 225 Vss 16 DQS1 136 Vss 46 DQS8 166 Vss 75 Vppa 195 ODTO 106 Vss 226 DQ54 17 Vss 137 CK1 47 Vss 167 CB6 76 S1 196 A13 107 DQ50 227 DQ55 18 NC 138 CK1 48 CB2 168 CB7 77 ODT1 197 Von 108 DQ51 228 Vss 19 NC 139 Vss 49 CB3 169 Vss 78 Vppa 198 Vss 109 Vss 229 DQ60 20 Vss 140 DQ14 50 Vss 170 VDDQ 79 Vss 199 DQ36 110 DQ56 230 DQ61 21 DQ10 141 DQ15 51 Vppa 171 CKE1 80 DQ32 200 DQ37 111 DQ57 231 Vss 22 DQ11 142 Vss 52 CKEO 172 Von 81 DQ33 201 Vss 112 Vss 232 DM7 23 Vss 143 DQ20 53 Vpp 173 NC 82 Vss 202 DM4 113 DQS7 233 NC 24 DQ16 144 DQ21 54 BA2 174 NC 83 DQS4 203 NC 114 DQS7 234 Vss 25 DQ17 145 Vss 55 NC 175 Vppa 84 DQS4 204 Vss 115 Vss 235 DQ62 26 Vss 146 DM2 56 Vono 176 A12 85 Vss 205 DQ38 116 DQ58 236 DQ63 27 DQS2 147 NC 57 A11 177 A9 86 DQ34 206 DQ39 117 DQ59 237 Vss 28 DQS2 148 Vss 58 A7 178 Von 87 DQ35 207 Vss 118 Vss 238 VppsPp 29 Vss 149 DQ22 59 Vpp 179 A8 88 Vss 2
22. CB products 3 S of Part number 13th digit stands for reduced layer PCB products 2 0 Features Performance range E7 DDR2 800 F7 DDR2 800 E6 DDR2 667 Unit Speed CL3 400 400 Mbps Speed CL4 533 533 533 Mbps Speed CL5 800 667 667 Mbps Speed CL 6 800 Mbps CL tRCD tRP 5 5 5 6 6 6 5 5 5 CK JEDEC standard Vpp 1 8V 0 1V Power Supply Vppo 1 8V 0 1V e 333MHz fo for 667Mb sec pin 400MHz fck for 800Mb sec pin 8 Banks Posted CAS Programmable CAS Latency 3 4 5 6 Programmable Additive Latency 0 1 2 3 4 5 Write Latency WL Read Latency RL 1 BurstLength 4 8 Interleave Nibble sequential Programmable Sequential Interleave Burst Mode Bi directional Differential Data Strobe Single ended data strobe is an optional feature Off Chip Driver OCD Impedance Adjustment On Die Termination with selectable values 50 75 150 ohms or disable Average Refresh Period 7 8us at lower than a Tease 85 C 3 9us at 85 C lt Tease lt 95 C Support High Temperature Self Refresh rate enable feature Package 60ball FBGA 128Mx8 and 84ball FBGA 64Mx16 All of products are Lead Free Halogen Free and RoHS compliant 3 0 Address Configuration Organization Row Address Column Address Bank Address Auto Precharge 128Mx8 1Gb based Module A0 A13 A0 A9 BAO BA2 A10 64Mx16 1Gb based Module A0 A12 A0 A9 BAO BA2 A10 4 of
23. DRAM FBGA DDR2 SDRAM Part NO KAT1G084QE 24 of 25 Rev 1 02 October 2008 ELECTRONICS UDIMM DDR2 SDRAM 15 4 64Mbx16 based 64Mx64 Module 1 Rank M378T6464EHS Units Millimeters 133 35 i 131 35 S k 128 95 g i S e mE 8 d SPD We 2 gt 30 00 Ur f 2 30 Kp 2 d 2 50 63 00 A R 55 00 d 2T un Hy unt 1 270 0 10 H z 3 00 5 00 ei dee 9 4 00 S 0 80 0 05 gt lt 1 N SE H 3 80 a 0 20 1 3 77 2 2x Jt L t Cum in 4 00 Jc 1 50 0 10 pie 0 e Detail A Detail B The used device is 64M x16 DDR2 SDRAM FBGA DDR2 SDRAM Part NO KAT1G164QE 25 of 25 Rev 1 02 October 2008 ELECTRONICS
24. P tRC and tRAS for Corresponding Bin Speed DDR2 800 E7 DDR2 800 F7 DDR2 667 E6 Bin CL tRCD tRP 5 5 5 6 6 6 5 5 5 Units Parameter min max min max min max tCK CL 3 5 8 5 8 ns tCK CL 4 3 75 8 3 75 8 3 75 8 ns tCK CL 5 2 5 8 3 8 3 8 ns tCK CL 6 2 5 8 ns tRCD 12 5 15 15 ns tRP 12 5 15 15 ns tRC 57 5 60 60 ns tRAS 45 70000 45 70000 45 70000 ns 19 of 25 Rev 1 02 October 2008 am ELECTRONICS UDIMM DDR2 SDRAM 14 3 Timing Parameters by Speed Grade Refer to notes for informations related to this table at the component datasheet E ELECTRONICS DDR2 800 DDR2 667 Parameter Symbol Units Notes min max min max DQ output access time from CK CK tAC 400 400 450 450 ps 40 DQS output access time from CK CK tDQSCK 350 350 400 400 ps 40 Average clock HIGH pulse width tCH avg 0 48 0 52 0 48 0 52 tCK avg 35 36 Average clock LOW pulse width tCL avg 0 48 0 52 0 48 0 52 tCK avg 35 36 CK half pulse period tHP ener x gore eal x ps 37 Average clock period tCK avg 2500 8000 3000 8000 ps 35 36 DQ and DM input hold time tDH base 125 x 175 x ps 6 7 8 21 28 31 DQ and DM input setup time tDS base 50 x 100 x ps 6 7 8 20 28 31 Control amp Address input pulse width for each input tIPW 0 6 x 0 6 x tCK avg DQ and DM input pulse width for each input tDIPW 0 35 x 0 35 x tCK
25. SWITCHING Operating burst read current IDD4R All banks open Continuous burst reads IOUT OmA BL 4 CL CL IDD AL 0 tCK tCK IDD tRAS tRAS m max IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCH ING Data pattern is same as IDDAW Burst auto refresh current EN IDD5B tCK tCK IDD Refresh command at every tRFC IDD interval CKE is HIGH CS is HIGH between valid commands mA Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING Self refresh current Normal mA IDD6 CK and CK at OV CKE x 0 2V Other control and address bus inputs are FLOATING Data bus inputs are FLOATING Low Power mA Operating bank interleave read current All bank interleaving reads IOUT OmA BL 4 CL CL IDD AL tRCD IDD 1 tCK IDD tCK tCK IDD tRC IDD7 tRC IDD tRRD tRRD IDD tFAW tFAW IDD tRCD 1 tCK IDD CKE is HIGH CS is HIGH between valid com mA mands Address bus inputs are STABLE during DESELECTs Data pattern is same as IDD4R Refer to the following page for detailed timing conditions um 15 of 25 Rev 1 02 October 2008 ELECTRONICS UDIMM DDR2 SDRAM 12 0 Operating Current Table 12 1 M378T2863EHS 1GB 128Mx8 8 Module Ta 0 C Vpp 1 9V 800 CL 5 800 CL6 667 CL 5 Symbol Units Notes CE7 CF7 CE6 IDDO 416 416 400 mA IDD1 464
26. UDIMM DDR2 SDRAM DDR2 Unbuffered SDRAM MODULE 240pin Unbuffered Module based on 1Gb E die 64 72 bit Non ECC ECC 60FBGA amp 84FBGA with Lead Free and Halogen Free ROHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS AND IS SUBJECT TO CHANGE WITHOUT NOTICE NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHER WISE TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL OGY ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS AS IS BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND 1 For updates or additional information about Samsung products contact your nearest Samsung office 2 Samsung products are not intended for use in life support critical care medical safety equipment or similar applications where Product failure could result in loss of life or personal or physical harm or any military or defense application or any governmental procurement to which special terms or provisions may apply Samsung Electronics reserves the right to change products or specification without notice 1 of 25 Rev 1 02 October 2008 ELECTRONICS UDIMM DDR2 SDRAM Table of Contents 1 0 DDR2 Unbuffered DIMM Ordering Information eeeeeeeeeeeeeneennnnnne nennen 4 DO POAT le m T 4 3 0 Address Configuration e 4
27. ansmitting device and Ver is expected to track variations in Vppq 2 Peak to peak AC noise on Veer may not exceed 2 Vnge DC 3 Vo of transmitting device must track Vref of receiving device 4 AC parameters are measured with Vpp Vppo and Vpp tied together um 13 of 25 Rev 1 02 October 2008 ELECTRONICS UDIMM DDR2 SDRAM 10 2 Operating Temperature Condition Symbol Parameter Rating Units Notes ToPER Operating Temperature 0 to 95 C 1 2 Note 1 Operating Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 2 At 85 95 C operation temperature range doubling refresh commands in frequency to a 32ms period tREFI 3 9 us is required and to enter to self refresh mode at this temperature range an EMRS command is required to change internal refresh rate 10 3 Input DC Logic Level Symbol Parameter Min Max Units Notes Vin DC DC input logic high Vngr 0 125 Vppo 0 3 V Vi DC DC input logic low 0 3 Vrer 0 125 V 10 4 Input AC Logic Level DDR2 667 DDR2 800 Symbol Parameter Units Notes Min Max Viu AC AC input logic high Vrer 0 200 V Viu AC AC input logic low Vggr 0 200 V 10 5 AC Input Test Conditions Symbol Condition Value Units Notes VREF Input reference voltage 0 5 Vopo V 1
28. ated During a Bank Activate command cycle Address input defines the row address RAO RA13 During a Read or Write command cycle Address input defines the colum address In addition to the column A0 A13 Inout address AP is used to invoke autoprecharge operation at the end of the burst read or write cycle If AP is p high autoprecharge is selected and BAO BA2 defines the bank to be precharged If AP is low autopre charge is disbled During a precharge command cycle AP is used in conjunction with BAO BA2 to control which bank s to precharge If AP is high all banks will be precharged regardless of the state of BAO BA2 If AP is low BAO BA1 BA2 are used to define which bank to precharge DQO DQ63 In Out CBO CB7 Data and Check Bit Input Output pins DM is an input mask signal for write data Input data is masked when DM is sampled High coincident with DMO DM8 Input that input data during a write access DM is sampled on both edges of DQS Although DM pins are input only the DM loading matches the DQ and DQS loading Power and ground for DDR2 SDRAM input buffers and core logic Vpp and Vppg pins are tied to Vpp Vpp Vss Supply Vppa planes on these modules DQS0 DQS8 In Out Data strobe for input and output data For Rawcards using x16 orginized DRAMs DQO 7 connect to the DQS0 DQS8 LDQS pin of the DRAMs and DQ8 17 connect to the UDQS pin of the DRAM These signals and tied at the system planar to either Vss or Vpp to c
29. bab pida clocks remains ON after CKE asynchronously tDelay air a x RUM e as 15 um 21 of 25 Rev 1 02 October 2008 ELECTRONICS UDIMM DDR2 SDRAM 15 0 Physical Dimensions 15 1 128Mbx8 based 128Mx64 Module 1 Rank M378T2863EHS Units Millimeters 133 35 e gt 131 35 Iw gt S 128 95 J X a SPD H B 9 E e EE EM 30 00 J C ji EA e 2 B 2 50 A B 63 00 R LA 55 00 d 27 oW o ym o 7 gt C D 1 270 0 10 7 4 3 00 5 00 E I 4 00 o 0 80 0 05 gt 4 00 E mi pE o Del fi N A 3 80 0 20 A Cum J li 4 00 1 50 0 10 ue LL 2 Detail A Detail B
30. ed as 1 rank of x16 DDR2 SDRAMs DDR2 SDRAM S0 T cs cs DQS 1 w LDQs DQS5 w LDas DQS1 w LDOS DQS5 w LDOS DM1 w LDM DM5 w LDM DQ8 w 4 1 00 DQ40 w 1 0 0 DQ9 w 1 01 DO DQ41 w 1 0 1 D2 DQ10 1 02 DQ42 1 0 2 DQ11 Ww 1 0 3 DQ43 w 1 03 DQ12 w 1 0 4 DQ44 1 0 4 DQ13 4 1 05 DQ45 wH 1 05 DQ14 w 1 06 DQ46 wr 1 06 DQ1I5 w 1 07 DQ47 Ww 1 07 DQS0 w UD Ss DQS4 w UDas DQS0 w UDOS DQS4 w UDOS DMO w UDM DM4 w UDM DO w 1 08 DQ32 WY 1 08 DQ1 w 1 09 DQ33 w 1 0 9 DQ2 w4 1 0 10 DQ34 wr 1 0 10 DQ3 w 1 0 11 DQ35 w 1 0 11 DQ4 w 1 0 12 DQ36 w 1 0 12 DQ5 w I O 13 DQ37 Ww 1 0 13 DQ6 w 1 0 14 DQ38 wr4 1 0 14 DQ7 w 1 0 15 DQ39 Wr 1 0 15 cs cs DQS3 w LDQ DQS7 w LDQS DQS3 w LDOS DQS7 w LDOS DM3 w LDM DM7 w LDM DQ24 w 1 00 DQ56 w 1 00 DQ25 w 1 01 D1 DQ57 vH 1 01 D3 DQ26 w 1 02 DQ58 yw 1 02 DQ27 Ww 1 03 DQ59I W 1 03 DQ28 w 1 04 DQ60 w 1 04 DQ29 w 1 05 DQ61 w 1 05 DQ30 w 1 06 DQ62 w 1 06 DQ31 w 1 07 DQ63 w 1
31. he single power plane on PCB 6 of 25 Rev 1 02 October 2008 am ELECTRONICS UDIMM DDR2 SDRAM 7 0 Input Output Function Description Symbol Type Description CK and CK are differential clock inputs All the SDRAM addr cntl inputs are sampled on the crossing of EE Input positive edge of CK and negative edge of CK Output read data is reference to the crossing of CK and CK Both directions of crossing CKEO CKE1 Input Activates the SDRAM CK signal when high and deactivates the CK Signal When low By deactivating the clocks CKE low initiates the Powe Down mode or the Self Refresh mode p Enables the associated SDRAM command decoder when low and disables the command decoder when S0 S1 Input high When the command decoder is disbled new command are ignored but previous operations continue This signal provides for external rank selection on systems with multiple ranks RAS CAS WE Input RAS CAS and WE ALONG WITH CS define the command being entered When high termination resistance is enabled for all DQ DQ and DM pins assuming the function is enabled ODTe OB Input in the Extended Mode Register Set EMRS VREF Supply Reference voltage for SSTL 18 inputs V Suppl Power supply for the DDR II SDRAM output buffers to provide improved noise immunity For all current DDQ ppy DDR2 unbuffered DIMM designs V shares the same power plane as Vpp pins DDQ DD BAO BA2 Input Selects which SDRAM BANK of four is activ
32. ock Loading Table Wiring Diagrams 1 DQ DM DQS DQS resistors 22 Ohms 5 2 BAx Ax RAS CAS WE resistors 10 Ohms 5 E ELECTRONICS 8 of 25 Rev 1 02 October 2008 UDIMM 8 2 1GB 128Mx72 ECC Module M391T2863EH3 Populated as 1 rank of x8 DDR2 SDRAMs DDR2 SDRAM So DQSO W DQS4 w DQSO W DQS4 WwW DMO DM4 DM CS DOS DQS DM CS Dos DQS DQ0 w 1 00 DQ32 w 1 0 0 DQ1 w 1 01 DO DQ33 w 1 0 1 D4 DQ2 w 1 02 DQ34 w 1 0 2 DQ3 w 1 03 DQ35 W 1 0 3 DQ4 w 1 04 DQ36 w 1 0 4 DOS w 1 05 DQ37 Ww 1 0 5 DQ6 w 1 06 DQ38 w 1 0 6 DQ7 w 1 07 DQ39 Wr 1 07 DQS1 W DQS5 S DQS1 Ww DQS5 wv DM 7w DM5 w DM CS Das Das DM CS Dos DQS DQ8 w 1 00 DQ40 w 1 0 0 pag w 1 01 D1 DQ41 1 0 1 D5 DQ10 Ww 1 0 2 DQ42 1 0 2 DQ11 Ww 1 03 DQ43 vH 1 0 3 DQ12 w 1 0 4 DQ44 w 110 4 DQ13 Ww 1 05 DQ45 w 1 0 5 DQ14 w 1 0 6 DQ46 wr 1 0 6 DQ15 w 1 07 DQ47 Ww 1 07 DQS2 w DQS6 w DQS2 W DQS6 W DN 4 DM6 4 DM CS Das DOS DM CS DOS DOS DQ16 w
33. onfigure the serial SPD EERPOM SA0 SA2 Input address range This bidirectional pin is used to transfer data into or out of the SPD EEPROM A resistor must be connected SDA In Out from the SDA bus line to Vpp to act as a pullup on the system board um 7 of 25 Rev 1 02 October 2008 ELECTRONICS UDIMM DDR2 SDRAM 8 0 Functional Block Diagram 8 1 1GB 128Mx64 Module M378T2863EHS Populated as 1 rank of x8 DDR2 SDRAMs So DQSO DQSO DMO w DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQs3 DQs3 DM DQ0 w 1 00 DOT w4 1 01 DQ2 w 1 02 DQ3 w 1 03 DO wy 1 04 DQ5 w j 1 05 DQ6 w4 1 06 DQ7 w 1 07 CS DOS DQS DO MA MA N DM DQ8 w 1 00 DQ9 wY 1 01 DQ10 w 1 0 2 DQ11 wH 1 03 DQ12 wry 1 04 DQ13 wr 1 05 DQ14 w 1 06 DQ15 wr 1 07 CS bas DOS Di AN DM DQ16 w 1 00 DQ17 w 1 01 DQ18 w 1 02 DQ19 w 1 03 DQ20 w 1 0 4 DQ21 w4 1 05 DQ22 wr 1 06 DQ23 p 1 07 CS bas Das D2 WW AN DM3 H DQ24 w 1 0 0 DQ25 w 1 0 1 DQ26 w I O 2 DQ27 w 1 0 3 DQ28 wry 1 0 4 DQ29 wry 1 05 DQ30 wr 1 06 DQ31 wr 1 07 DM NU CS Dos DOS D3 Serial PD SCL gt WP AU Atl I SDA A2 BAO BA2 SA0 SA1 A0 A
34. pin relative to Vss 0 5V 2 3V V 1 Vin Vout Voltage on any pin relative to Vss 0 5V 2 3V V 1 Ter Storage Temperature 55 to 100 C 1 2 Note 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 10 0 AC amp DC Operating Conditions 10 1 Recommended DC Operating Conditions SSTL 1 8 Rating Symbol Parameter Units Notes Min Typ Max Vpp Supply Voltage 14 1 8 1 9 VppL Supply Voltage for DLL 1 7 1 8 1 9 V 4 VDDQ Supply Voltage for Output 1 7 1 8 1 9 V 4 VREF Input Reference Voltage 0 49 Vppaq 0 50 Vppa 0 51 Vppa mV 1 2 VIT Termination Voltage Vggr 0 04 VREF Vggr 0 04 V 3 Note There is no specific device Vpp supply voltage requirement for SSTL 1 8 compliance However under all conditions Vppo must be less than or equal to Von 1 The value of Vgge may be selected by the user to provide optimum noise margin in the system Typically the value of Vgge is expected to be about 0 5 X Vppq Of the tr
35. sistors 10 Ohms 5 ODTO ODT DDR2 SDRAMs DO D8 ELECTRONICS 9 of 25 Rev 1 02 October 2008 UDIMM 8 3 2GB 256Mx64 Module M378T5663EH3 Populated as 2 ranks of x8 DDR2 SDRAMs Si DDR2 SDRAM So DQso DQso DMO DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQs3 DQs3 DM3 BAO AO WS DQS4 AN MW DQS4 M M T DM4 NAE DM CS Das Das DM CS bas Dos DM CS Das Das DM CS Dos Das DQ0 w 1 00 1 0 0 DQ32 w 1 00 1 0 0 DOT w 1 01 DO 1 0 1 D8 DQ33 w 1 01 D4 1 0 1 D12 DQ2 w 4 1 02 1 0 2 DQ34 w 1 02 1 0 2 DQ3 w 1 03 1 0 3 DQ35 A 1 03 1 0 3 DQ4 w 1 04 1 0 4 DQ36 r 1 04 1 0 4 DQ5 w4 1 05 1 05 DQ37 w 1 05 1 05 DQ6 w4 1 06 1 0 6 DQ38 w 1 06 1 0 6 DQ7 w4 1 07 1 07 DQ39 y r 1 07 1 07 W e DQS5 W DQS5 M M I DM5 AN DM CS Das DO
36. ssccccesseeeeeseeeeeeeeeeseeeneeseeseeeeeeaeeseeeeseseaeenesseneesseneeees 22 15 2 128Mbx8 based 128M x72 Module 1 Rank sccccsseeeeeeeeeeeeeeeeeenenseeeeeseeeeeeeeeesenseseeeenessaeeesseeneeees 23 15 3 128Mbx8 based 256Mx64 x72 Module 2 Ranks eeeeeeee enne nennen nennen nnn nnn nnn nnn nnn nnn nnn nnn 24 15 4 64Mbx16 based 64Mx64 Module 1 Rank eeeeeeeeeeeee eene nenne nnnm nnnm neni nini RENE RENE REENEN EEN 25 2 of 25 Rev 1 02 October 2008 ELECTRONICS UDIMM DDR2 SDRAM Revision History Revision Month Year History 1 0 August 2008 Initial Release 1 01 October 2008 Typo correction 1 02 March 2009 Corrected Typo ELECTRONICS 3 of 25 Rev 1 02 October 2008 UDIMM 1 0 DDR2 Unbuffered DIMM Ordering Information DDR2 SDRAM Part Number Density Organization Component Composition Number of Rank Height x64 Non ECC M378T2863EHS CE7 F7 E6 1GB 128Mx64 128Mx8 K4T 1G084QE 8 1 30mm M378T5663EH3 CE7 F7 E6 2GB 256Mx64 128Mx8 K4T1G084QE 16 2 30mm M378T6464EHS CE7 F7 E6 512MB 64Mx64 64Mx16 K4T1G164QE 4 30mm x72 ECC M391T2863EH3 CE7 F7 E6 1GB 128Mx72 128Mx8 K4T 1G084QE 9 1 30mm M391T5663EH3 CE7 F7 E6 2GB 256Mx72 128Mx8 K4T 1G084QE 18 2 30mm Note 1 H of Part number 12th digit stands for Lead Free Halogen Free and RoHS compliant products 2 3 of Part number 13th digit stands for Dummy Pad P
37. t NO KAT1G084QE 23 of 25 Rev 1 02 October 2008 ELECTRONICS UDIMM DDR2 SDRAM 15 3 128Mbx8 based 256Mx64 x72 Module 2 Ranks M378T5663EH3 M391T5663EH3 Units Millimeters 133 35 gt 131 35 mel gt 128 95 S 4 0 mm lt gt Ed hl X x 8 N A s D ECC SPD m t S for x72 30 00 j LU C ji S e 1 0 max 2 a is TU E 2 50 1 27 0 10 le A B 63 00 A 55 00 lt gt lt gt o EE 5 gt C N A for x64 B C 3 00 5 00 4 00 S do H i 9 E 0 80 0 05 gt lt _ gt 1 2 N 7 k Cus t 4 4 00 1 50 0 10 jQ 1 00 S Detail A Detail B The used device is 128M x8 DDR2 S
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