Samsung 256MB, DDR II SDRAM, 533MHz, soDIMM
Contents
1. 30 596 ODT1 M ODTO M CKE1 M CKEO M 81 M So Ww t DQS0 w 4 DOS CS c o cS co DQS4 w 4 LDQS CS c o CS O DQS0 w LDQS K D LDQS K D DQS4 Nw LDQs K D LDQS K D DMO w LDM E T LDM ET DM4 w4 LDM ET LDM E T pao w 1 00 O 0 DQ32 w 1 00 O 0 DO1 w 1 01 DO O1 D4 DQ33 W 1 01 D2 O1 D6 DQ2 w l 1 02 O 2 DQ34 wr IO 2 O 2 DQ3 wWw 1 03 O 3 DQ35 w 1 0 3 O 3 DQ4 wWw 1 04 O 4 DQ36 w 1 0 4 O 4 DQ5 w 1 05 O 5 DQ37 WY 1 05 O 5 pas w 1 06 O 6 DQ38 W J 1 0 6 O 6 DQ7 w 1 07 O 7 DQ39 WW 1 0 7 O 7 DQS1 w UDQs UDQS DQS5 w UDas UDQS DQS1 w UDGS UDQS DQS5 _wj UDQS UDQS DM1 w J UDM UDM DM5 UDM UDM pas wl 1 08 0 8 DO40 w 1 0 8 O 8 pag w l 1 09 09 DQ41 w 1 0 9 O 9 DQ10 1 0 10 O 10 DQ42 w 1 0 10 O 10 DQ11 w 1 0 11 O 11 DQ43 w 1 0 11 O 11 DQ12 1 0 122. 0 60 0 45 0 03 ELECTRONICS Rev 1 5 Aug 2005 256MB 512MB 1GB Unbuffered SODIMMs DDR2 SDRAM Physical Dimensions 64Mbx8 based 128Mx64 Module 2 Ranks M470T2953BS Y 3 M470T2953BS Y 0 67 60 mm gt 3 8 mm i max 2 00 dn 30 00 4 00 0 10 20 00 p 4 ES O i O e PL 199 i fla m Y 4 1140 47 40 a rr gt 16 25 La 16 49 oar 1 1mm 63 00 max ja ik 2 AJ 200 O o o S e Y 67 60 mm gt DETAIL a DETAIL b FRONT SIDE BACK SIDE 4 20 4 00 0 10 1 0 0 05 5 N 2 70 0 10 1 50 0 10 f D lt o D E a on 1 80 0 10 2 40 0 10 0 60 Pm 1 0 0 05 4 20 Se 0 45 0 03 The used device is 64M x8 DDR2 SDRAM FBGA DDR2 SDRAM Part NO K4T51083Q
3. D7 A2 WP CAS Q DDR2 SDRAMs DO D7 LL WE W DDR2 SDRAMs D0 D7 Clock Wiring Clock Input DDR2 SDRAMs VppSPD Serial PD CKO CKO 4 DDR2 SDRAMs VREF t DDR2 SDRAMs D0 D7 CK1 CK1 4DDR2 SDRAMs Vpp DDR2 SDRAMs D0 D7 Vpp and VppQ Wire per Clock Loading Table Wiring Diagrams Vss DDR2 SDRAMs D0 D7 SPD Notes 1 DQ DM DQS DQS resistors 22 Ohms 5 2 BAx Ax RAS CAS WE resistors 3 0 Ohms 5 Rev 1 5 Aug 2005 ELECTRONICS 256MB 512MB 1GB Unbuffered SODIMMs DDR2 SDRAM Functional Block Diagram 256MB 32Mx64 Module Populated as 1 rank of x16 DDR2 SDRAMs M470T3354BG Z 3 M470T3354BG Z 0 39 5 CKEO M ODTO M so M Daso mwH Lpos CS o c DQS4 w LpQs CS O c DQS0 w LDQS D K DQS4 w 4 LDQS D K DMO w LDM T E DM4 4 LDM T E DQO w 1 00 DQ32 w I O0 DQ1 w 1 01 DO DQ33 v 1 01 D2 DQ2 w 1 02 DQ34 w 1 02 DQ3 w 1 03 DQ35 w 1 0 3 DQ4 w 1 04 DQ36 w 1 0 4 DQ5 w 1 05 DQ37 Ww 1 0 5 DQ6 w 1 06 DQ38 w 1 0 6 DQ7 w 1 07 DQ39 Ww 1 07 DQS1 w 4 upos DQS5 wj UDGS Das1 H _w UDGS Dass w UDOS
4. DO19 w 1 03 O 3 DQ51 w 1 0 3 1 0 3 DQ20 w 1 0 4 O 4 DQ52 w _ 1 0 4 I O 4 DQ21 w 1 05 O 5 DQ53 w _ 1 0 5 1 05 DQ22 w 1 06 O 6 DQ54 W 1 0 6 I O 6 DQ23 W J 1 07 O 7 DQ55 w _ 1 0 7 VO7 bas3 _Wj DOS Twoo c DOS csio c DQS7 w pQSs csoo c DOS cs1o c DQS3 w DOS D K DQS D K DQS7 w DOGS DK DQS D K DM3 w DM T E DM T E DM7 M4 DM T E DM T E DQ24 wW 1 08 0 0 O 8 d d DQ56 w 1 0 8 0 0 708 1 1 DQ25 w 109 D3 O9 D11 DQ57 wW 1 09 D7 VO9 p15 DQ26 w 1 0 10 O 10 DQ58 w 1 0 10 0 10 DQ27 w I O 11 O 11 DQ59 w I O 11 VO 11 DQ28 w 1 0 12 O 12 DQ60 w I O 12 VO 12 DQ29 W 1 0 13 O 13 DQ61 Ww 1 0 13 1 0 13 DQ30 w I O 14 O 14 DQ62 w I O 14 VO 14 DQ31 w 1 0 15 O 15 DQ63 W 1 0 15 VO 15 amp mes 100 596 Clock Wiring W qt DRE SO RAMS DOS DTS sc SCL Clock Input DDR2 SDRAMs Ww gt DDR2 SDRAMs DO D15 SA0 A0 M SM e a SP ll esp CKO CKO 8 DDR2 SDRAMs Ww gt DDR2SDRAMs DO D15 A2 WP CK1 CK1 8 DDR2 SDRAMs WN aw DDR2 SDRAMs DO SDIS LL Wire per Clock Loading DDR2 SDRAMs D0 D15 Table Wiring Diagrams Serial PD Notes DDR2 SDRAMs D0 D15 1 DQ DM DQS DQS resistors 22 Ohms 5 2 BAx Ax RAS CAS WE resistors 10 Ohms 5 DDR2 SDRAMs DO D15 Vpp and VppQ DDR2 SDRAMs DO D15 SPD Rev 1 5 Aug 2005
5. O 12 DQ44 w I O 12 O 12 DQ13 W J I O 13 O 13 DO45 w 1 0 13 O 13 DQ14 wr I O 14 O 14 DO46 w 1 0 14 O 14 DQ15 w 1 015 O 15 DO47 Ww 1 0 15 O 15 I I I I I T T I I I I I DQS2 Mw LbD s CS C o LDQs CS C O pas6 _w pos CS C O LDQs CS C O DQS2 w LDQs K D LDQS K D DQS6 w LDQS K D LDQS K D DM2 w LDM EE LDM pe DM6 w LDM ET LDM EE DQ16 A 1 00 O 0 DQ48 A 1 00 O 0 DQ17 AA lO1 D1 O1 D5 DA49_pr 1 01 D3 O1 D7 DQ18 A 1 0 2 O 2 DQ50_ r 1 02 O 2 DQ19 03 0 3 DO51 0 3 0 3 DQ20 1 0 4 O 4 DO52 O 4 O 4 DO21 Vo5 O 5 DQ53 0 5 O 5 DQ22 VO 6 O 6 DQ54 O 6 O 6 DQ23 A 1 07 O 7 DQ55 A 1 07 O 7 DQS3 _Wj_ UDQS UDQS DQS7 w UDQS UDQS DQS3 w UDQS UDQS Das7 w UDQS UDQS DM3 w 4 UDM UDM DM7 w UDM UDM DQ24 y 1 08 O 8 DQ56 pr 1 08 O 8 DQ25 A 1 09 O 9 DQ57 1 09 O 9 DQ26 A 1 0 10 O 10 DQ58 1 1 0 10 O 10 DQ27 _ vl 1 0 11 O 11 DQ59 A 1 011 O 11 DQ28 _ arn l O 12 O 12 DO60 A 1 0 12 O 12 DQ29 ar 0 13 O 13 DQ61 vl 1 0 13 O 13 DQ30 A 0 14 O 14 DQ62 A 1 0 14 O 14 DQ31 A 1 015 O 15 DQ63 JA 1 015 O 15 3O 5 BAO BA1 m gt DDR2 SDRAMs DO D7 SCL l SCL SA0 A0 spp AO A13 M gt DDR2 SDRAMs DO D7 SA1 A1 SDA RAS MW gt DDR2 SDRAMs DO
6. 1KB page size products tFAW 37 5 37 5 ns Four Activate Window for 2KB page size products tFAW 50 50 ns CAS to CAS command delay tCCD 2 2 tCK Write recovery time tWR 15 x 15 x ns Auto precharge write recovery precharge time tDAL tWR tRP x tWR tRP x tCK Internal write to read command delay tWTR 7 5 x 10 x ns Internal read to precharge command delay tRTP 7 5 7 5 ns Exit self refresh to a non read command tXSNR tRFC 10 tRFC 10 ns Exit self refresh to a read command tXSRD 200 200 tCK Exit precharge power down to any non read command tXP 2 x 2 x tCK Exit active power down to read command tXARD 2 x 2 x tCK mA power down to read command Slow exit Lower tXARDS 6 AL 6 AL tck Rev 1 5 Aug 2005 ELECTRONICS 256MB 512MB 1GB Unbuffered SODIMMs DDR2 SDRAM DDR2 533 DDR2 400 Parameter Symbol Units Notes min max min max CKE minimum pulse width high and low pulse width tCKE tCK ODT turn on delay tAOND 2 2 2 tCK ODT turn on tAON tAC min tAC max 1 tAC min tAC max 1 ns ODT turn on Power Down mode tAONPD tAC miny2 ACKHACC canys ACKHAC as max 1 max 1 ODT turn off delay tAOFD 2 5 2 5 2 5 2 5 tCK ODT turn off tAOF tAC min ee tAC min oe ns 2 5tCK 2 5tCK ODT turn off Power Down mode tAOFPD tAC min 2 tAC max 1 tAC min 2 tAC max 1 ns ODT to power down entry latency tANPD 3 3 tCK ODT power down exit latency tAXPD 8 tCK OCD drive mode output dela
7. 256MB 512MB 1GB Unbuffered SODIMMs DDR2 SDRAM Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes Vpp Voltage on Vpp pin relative to Vss 10V 23V V 1 VDDQ Voltage on Vppg pin relative to Vss 0 5V 23V V 1 VppL Voltage on Vpp pin relative to Vss 0 5V 23V V 1 Vin Vout Voltage on any pin relative to Vss 05V 23V V 1 TsrG Storage Temperature 55 to 100 C 1 2 Note 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard AC amp DC Operating Conditions Recommended DC Operating Conditions SSTL 1 8 Symbol Parameter nating Units Notes Min Typ Max Vpp Supply Voltage 1 7 1 8 1 9 VppL Supply Voltage for DLL 1 7 1 8 1 9 V 4 VDDQ Supply Voltage for Output 1 7 1 8 1 9 V 4 VREF Input Reference Voltage 0 49 Vppo 0 50 Vppa 0 51 Vppa mV 1 2 Vrr Termination Voltage Vngr 0 04 VREF Vggr 0 04 V 3 Note There is no specific device Vpp supply voltage req
8. CL x tCK 3750 8000 5000 8000 ps DQ and DM input hold time tDH 225 x 275 x ps DQ and DM input setup time tDS 100 x 150 x ps Control amp Address input pulse width for each input tIPW 0 6 x 0 6 x tCK DQ and DM input pulse width for each input tDIPW 0 35 x 0 35 x tCK Data out high impedance time from CK CK tHZ x tAC max x tAC max ps DOS low impedance time from CK CK tLZ DOS tAC min tAC max tAC min tAC max ps DO low impedance time from CK CK tLZ DO 2 tACmin tAC max 2 tACmin tAC max ps DOS DO skew for DOS and associated DO signals tDQSQ x 300 x 350 ps DQ hold skew factor tQHS x 400 x 450 ps DQ DQS output hold time from DQS tQH tHP tQHS x tHP tQHS x ps Write command to first DQS latching transition tDQSS WL 0 25 WL 0 25 WL 0 25 WL 0 25 tCK DOS input high pulse width tDOSH 0 35 x 0 35 x tCK DQS input low pulse width tDQSL 0 35 x 0 35 x tCK DQS falling edge to CK setup time tDSS 0 2 x 0 2 x tCK DQS falling edge hold time from CK tDSH 0 2 x 0 2 x tCK Mode register set command cycle time tMRD 2 x 2 x tCK Write postamble tWPST 0 4 0 6 0 4 0 6 tCK Write preamble tWPRE 0 35 x 0 35 x tCK Address and control input hold time tlH 375 x 475 x ps Address and control input setup time tIS 250 x 350 x ps Read preamble tRPRE 0 9 1 1 0 9 1 1 tCK Read postamble tRPST 0 4 0 6 0 4 0 6 tCK Active to active command period for 1KB page size products tRRD 7 5 x 7 5 x ns Active to active command period for 2KB page size products tRRD 10 x 10 x ns Four Activate Window for
9. HIGH between valid mA commands Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING Operating burst write current All banks open Continuous burst writes BL 4 CL CL IDD AL 0 tCK tCK IDD tRAS tRASmax IDD tRP IDD4W mA tRP IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data bus inputs are SWITCHING Operating burst read current IDD4R All banks open Continuous burst reads IOUT 0mA BL 4 CL CL IDD AL 0 tCK tCK IDD tRAS tRAS mA max IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCH ING Data pattern is same as IDD4W Burst auto refresh current IDD5B tCK tCK IDD Refresh command at every tRFC IDD interval CKE is HIGH CS is HIGH between valid commands mA Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING Self refresh current Normal mA IDD6 CK and CK at OV CKE lt 0 2V Other control and address bus inputs are FLOATING Data bus inputs are FLOATING Low Power mA Operating bank interleave read current All bank interleaving reads IOUT 0mA BL 4 CL CL IDD AL tRCD IDD 1 tCK IDD tCK tCK IDD RC IDD7 tRC IDD RRD tRRD IDD tFAW tFAW IDD tRCD 1 tCK IDD CKE is HIGH CS is HIGH between valid mA commands Address bus inputs are STABLE during DESELECTs Data pattern is same as IDD4R Refer to the f
10. data strobes associated with one data byte sourced with data transfers In Write mode the data strobe is sourced by the controller and is centered in the data window In Read mode DQS0 DQS7 In Out the data strobe is sourced by the DDR2 SDRAMs and is sent at the leading edge of the data DQS0 DQS7 window DQS signals are complements and timing is relative to the crosspoint of respective DQS and DQS If the module is to be operated in single ended strobe mode all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed appropriately ML Supply Power supplies for core I O Serial Presence Detect and ground for the module VSS SDA In Out This is a bidirectional pin used to transfer data into or out of the SPD EEPROM A resistor must be connected to Vpp to act as a pull up SCL input This signal is used to clock data into and out of the SPD EEPROM A resistor may be connected from SCL to Vpp to act as p a pull up SA0 SA1 Input Address pins used to select the Serial Presence Detect base address TEST In Out The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules SO DIMMs Rev 1 5 Aug 2005 ELECTRONICS 256MB 512MB 1GB Unbuffered SODIMMs DDR2 SDRAM Functional Block Diagram 512MB 64Mx64 Module Populated as 2 rank of x16 DDR2 SDRAMs M470T6554BG Z 3 M470T6554BG Z 0
11. 0T3354BZ3 LD5 CC 256MB 32Mx64 32Mx16 K4T51163QB 4 1 30mm M470T3354BZ0 LD5 CC 256MB 32Mx64 32Mx16 K4T51163QB 4 1 30mm M470T6554BG Z 3 CD5 CC 512MB 64Mx64 32Mx16 K4T51163QB 8 2 30mm M470T6554BG Z 0 CD5 CC 512MB 64Mx64 32Mx16 K4T51163QB 8 2 30mm M470T6554BZ3 LD5 CC 512MB 64Mx64 32Mx16 K4T51163QB 8 2 30mm M470T6554BZ0 LD5 CC 512MB 64Mx64 32Mx16 K4T51163OB 8 2 30mm M470T2953BS Y 3 CD5 CC 1GB 128Mx64 64Mx8 K4T51083OB 16 2 30mm M470T2953BS Y 0 CD5 CC 1GB 128Mx64 64Mx8 K4T51083OB 16 2 30mm M470T2953BY3 LD5 CC 1GB 128Mx64 64Mx8 K4T51083QB 16 2 30mm M470T2953BY0 LD5 CC 1GB 128Mx64 64Mx8 K4T51083QB 16 2 30mm Note Z and Y of Part number 11th digit stand for Lead free products Note 3 of Part number 12th digit stand for Dummy Pad PCB products Features Performance range D5 DDR2 533 CC DDR2 400 Unit Speed CL3 400 400 Mbps Speed CL4 533 400 Mbps CL tRCD tRP 4 4 4 3 3 3 CK JEDEC standard 1 8V 0 1V Power Supply VDDQ 1 8V 0 1V e 200 MHz fcx for 400Mb sec pin 267MHz fcx for 533Mb sec pin 4 Banks Posted CAS Programmable CAS Latency 3 4 5 Programmable Additive Latency 0 1 2 3 and 4 Write Latency WL Read Latency RL 1 Burst Length 4 8 Interleave nibble sequential Programmable Sequential Interleave Burst Mode Bi directional Differential Data Strobe Single ended data strobe is an optional feature Off Chip Driver OCD Impedan
12. 18 Vpp 167 DQS6 168 Vss 19 DQ3 20 DQ12 69 NC 70 DQS3 119 NC ODT1 120 NC 169 DQS6 170 DM6 21 Vss 22 DQ13 71 Vss 72 Vss 121 Vss 122 Vss 171 Vss 172 Vss 23 DQ8 24 Vss 73 DQ26 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54 25 DO9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55 27 Vss 28 Vss 77 Vss 78 Vss 127 Vss 128 Vss 177 Vss 178 Vss 29 DQS1 30 CKO 79 CKEO 80 NC CKE1 129 DQS4 130 DM4 179 DQ56 180 DQ60 31 DQS1 32 CKO 81 Vpp 82 Vpp 131 DQS4 132 Vss 181 DQ57 182 DQ61 33 Vss 34 Vss 83 NC 84 NC 133 Vss 134 DQ38 183 Vss 184 Vss 35 DQ10 36 DQ14 85 BA2 86 NC 135 DQ34 136 DQ39 185 DM7 186 DQS7 37 DQ11 38 DQ15 87 Vpp 88 Vpp 137 DQ35 138 Vss 187 Vss 188 DQS7 39 Vss 40 Vss 89 A12 90 A11 139 Vss 140 DO44 189 DQ58 190 Vss 41 Vss 42 Vss 91 A9 92 AT 141 DO40 142 DQ45 191 DQ59 192 DQ62 43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 Vss 193 Vss 194 DQ63 45 DQ17 46 DQ21 95 Vpp 96 Vpp 145 Vss 146 DQS5 195 SDA 196 Vss 47 Vss 48 Vss 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SAO 49 DQS2 50 NC 99 A3 100 A2 149 Vss 150 Vss 199 VppSPD 200 SA1 Note NC No Connect NC TEST pin 163 is for bus analysis tool and is not connected on normal memory modules Pin Description Pin Name Function Pin Name Function CKO CK1 Clock Inputs positive line SDA SPD Data Input Output CKO CK1 Clock Inputs negative line SA1 SA0 SPD address CKEO CKE1 Clock Enables DQ0 DQ63 Data Input Output RAS Row Address Strobe DMO DM7 Data Masks CAS Column Address Strobe DQS0 DQS7 Data strobes WE Write Enable
13. 256MB 512MB 1GB Unbuffered SODIMMs DDR2 SDRAM DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb B die 64bit Non ECC INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS AND IS SUBJECT TO CHANGE WITHOUT NOTICE NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS AS IS BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND 1 For updates or additional information about Samsung products contact your nearest Samsung office 2 Samsung products are not intended for use in life support critical care medical safety equipment or similar applications where Product failure couldresult in loss of life or personal or physical harm or any military or defense application or any governmental procurement to which special terms or provisions may apply Samsung Electronics reserves the right to change products or specification without notice Rev 1 5 Aug 2005 ELECTRONICS 256MB 512MB 1GB Unbuffered SODIMMs DDR2 SDRAM DDR2 Unbuffered SODIMM Ordering Information Part Number Density Organization Component Composition Number of Height M470T3354BG Z 3 CD5 CC 256MB 32Mx64 32Mx16 K4T51163OB 4 1 30mm M470T3354BG Z 0 CD5 CC 256MB 32Mx64 32Mx16 K4T51163QB 4 1 30mm M47
14. B Rev 1 5 Aug 2005 ELECTRONICS 256MB 512MB 1GB Unbuffered SODIMMs DDR2 SDRAM Revision History Revision 1 0 Jan 2004 Initial Release Revision 1 1 Jun 2004 Added lead free part number in the ordering information Changed IDD2P Revision 1 2 Jul 2004 Added current values and part number of low power product Revision 1 3 Feb 2005 Added the detail information for mechanical dimension Revision 1 4 Mar 2005 Changed 1GB Functional Block Diagram Revision 1 5 Aug 2005 Changed the IDD Specification Parameters Definition Rev 1 5 Aug 2005 ELECTRONICS This datasheet has been downloaded from www DatasheetCatalog com Datasheets for electronic components
15. D0 D3 Clock Wiring VppSPD Serial PD Clock Input DDR2 SDRAMs VREF DDR2 SDRAMs DO D3 CKO CKO 2 DDR2 SDRAMs CK1 CK1 2 DDR2 SDRAMs V DDR2 SDRAMs DO D3 Vpp and VppQ i a pe p Wire per Clock Loading Vss 4 ib 4 DDR2 SDRAMs DO D3 SPD Table Wiring Diagrams ELECTRONICS Notes 1 DQ DM DQS DQS resistors 22 Ohms 5 2 BAx Ax RAS CAS WE resistors 3 0 Ohms 590 Rev 1 5 Aug 2005 256MB 512MB 1GB Unbuffered SODIMMs DDR2 SDRAM Functional Block Diagram 1GB 128Mx64 Module Populated as 2 ranks of x8 DDR2 SDRAMs M470T2953BS Y 3 M470T2953BS Y 0 BAO BA1 AO A13 RAS CAS ELECTRONICS 30 596 CKE1 Ww ODT1 Ww 81 M CKEO Ww ODTO Ww S0 M t DQS0 w Dos C800 c Dos C810 c DQS4 M pos Too c Das C 10 c DQS0 _w Das D
16. DM1 w UDM DM5 w UDM pas w 1 08 DQ40 1 0 8 pag w 1 09 DQ41 wr 1 09 DO10 wr 1 0 10 DQ42 wr I O 10 DQ11 wr 1 0 11 DQ43 1 0 11 DO12 wJl 1 0 12 DQ44 wr 1 0 12 DQ13 Ww 1 0 13 DQ45 wr 1 0 13 DQ14 w 1 0 14 DQ46 wr 1 0 14 DQ15 w 1 0 15 DQ47 Ww 1 0 15 I I I I I I DQS2 w iOS CS O C DQS6 _w LDQs CS O C DQS2 w LDQS D K DQS6 w LDOS D K DM2 LDM TE DM6 LDM TAE DQ16 wv 1 00 DQ48 wr 1 00 DQ17 1 01 D4 DAa49 w 1 01 D3 DQ18 w 1 0 2 DQA50 w 1 0 2 DO19 1 0 3 DO51 wJ 1 0 3 DQ20 w 1 0 4 DQ52 w 1 04 DQ21 w 1 05 DQ53 w 1 05 DQ22 w 1 06 DQ54 wH 1 06 DQ23 wr 1 07 DO55 w J 1 07 DQS3 w UDQS DQS7 w UDQS DQS3 w UDOS DQS7 _w UDQS DM3 Mw UDM DM7 w UDM DQ24 w 1 0 8 DQ56 1 0 8 DQ25 w 1 0 9 DQ57 Ww 1 0 9 DQ26 w 1 0 10 DQ58 w 1 0 10 DQ27 Ww 1 0 11 DQ59 1 0 11 DQ28 w 1 0 12 DQ60 w 1 0 12 DQ29 w I O 13 DQ61 w I O 13 DQ30 wr I O 14 DQ62 w 1 0 14 DQ31 w 1 015 DQ63 w 1 0 15 30 BAO BA1 W DDR2 SDRAMs D0 D3 SCL SCL SA0 A0 spp AO A13 W gt DDR2 SDRAMs D0 D3 SA1 gt A1 I SDA A2 RAS W DDR2 SDRAMs DO D3 WP CAS W DDR2 SDRAMs D0 D3 WE w gt DDR2 SDRAMs
17. DQS0 DQS7 Data strobes complement S0 S1 Chip Selects TEST Logic Analyzer specific test pin No connect on So DIMM A0 A9 A11 A13 Address Inputs Vpp Core and I O Power A10 AP Address Input Autoprecharge Vss Ground BAO BA1 SDRAM Bank Address VREF Input Output Reference ODTO ODT1 On die termination control VppSPD SPD Power SCL Serial Presence Detect SPD Clock Input NC Spare pins No connect ELECTRONICS Rev 1 5 Aug 2005 256MB 512MB 1GB Unbuffered SODIMMs DDR2 SDRAM Input Output Functional Description Symbol Type Function The system clock inputs All address and command lines are sampled on the cross point of the rising edge of CK and falling CK0 CK1 dee z Pun TIC Input edge of CK A Delay Locked Loop DLL circuit is driven from the clock input and output timing for read operations is syn CK0 CK1 h chronized to the input clock Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE CKEO CKE1 Input MER low initiates the Power Down mode or the Self Refesh mode ET Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high When S0 S1 Input the command decoder is disabled new commands are ignored but previous operations continue Rank 0 is selected by SO Rank 1 is selected by S1 Ranks are also called Physical banks Bie o UIE When sampled at the cro
18. K DQS D K DQS4 w Das D K DOS D K DMO w DM T E DM T E DM4 w DM T E DM T E pao w 1 00 9 20 O 0 mE DQ32 WH 1 0 0 0 Vo 0 mE DQ1 W 1 01 DO O 1 D8 DQ33 Ww IO 1 D4 O1 D12 DQ2 W 1 02 JO 2 DQ34 w 1 0 2 VO2 DQ3 W 1 03 0 3 DQ35 Ww IO 3 1 0 3 DQ4 wW 1 04 O 4 DQ36 W 1 0 4 I O 4 DQ5 wW V05 O 5 DQ37 W j VO 5 1 05 DQ6 wW 1 06 O 6 DQ38 wW 1 06 1 0 6 DQ7 W 1 07 JO 7 DQ39 W IO 7 VO7 DQs1 _wyj DQS csoo c DOS csio c DOS5 J DOS csoo c DOS cs1o c DQS1 DOS D K DQS DK D0S5 y DOGS D K DQS DK DM1 v 4 DM T E DM T E DM5 DM T E DM T E DQ8 w 1 08 0 o O 8 1 41 DO40 W J 1 08 0 0 1 0 8 134 DQ9 w O9 Dp4 O9 pg DQ41 W 1 09 D5 VO9 p13 DQ10 w 1 0 10 O 10 DQ42 w 1 0 10 VO 10 DO11 w IO 11 O 11 DQ43 w VO 11 VO 11 DQ12 w I O 12 O 12 DQ44 W VO 12 VO 12 DQ13 w 1 0 13 O 13 DQ45 w 1 0 13 1 0 13 DQ14 w I O 14 O 14 DQ46 w I O 14 VO 14 DQ15 w 1 0 15 O 15 DQ47 w VO 15 VO 15 DQS2 M DQS CS0O c DOS C810 c DQS6 v DQSs Too c DOS CS O c DQS2 w DOS DK DQS DK DQS6 w DQS DK DQS DK DM2 _wJ DM T E DM T E DM6 w DM T E DM T E DQ16 w 1 00 0 0 O 0 1 1 DQ48 w 1 00 0 0 1 0 0 1 1 DA17 wW4 1 01 pa O1 p10 DQ49 w 1 01 D6 O1 D14 DQ18 w 1 02 O 2 DQ50 w 1 0 2 VO2
19. OB ELECTRONICS Rev 1 5 Aug 2005 256MB 512MB 1GB Unbuffered SODIMMs DDR2 SDRAM Physical Dimensions 32Mbx16 based 32Mx64 Module 1 Rank M470T3354BG Z 3 M470T3354BG Z 0 67 60 mm jat I 2 00 42 00 2 a S a o o 75 o e i Sia L O o Q iga EP 199 Ll LII Y 4 11 40 i 47 40 a 16 25 Fm 63 00 ja m i 2 yu 200 O o o o e Y 67 60 mm pae DETAIL a FRONT SIDE BACK SIDE 4 20 4 00 0 10 1 0 0 05 2 70 0 10 1 50 0 10 4 00 z 0 10 1 0 0 05 1 80 0 10 2 40 0 10 4 20 The used device is 32M x16 DDR2 SDRAM FBGA DDR2 SDRAM Part NO K4T51163QB DETAIL b 2 45 mm j4 Max 1 1mm r Max It SVL 0 070 I GGZ
20. ce Adjustment On Die Termination Average Refresh Period 7 8us at lower than a TcAsg 85 C 3 9us at 85 C lt Tease lt 95 C support High Temperature Self Refresh rate enable feature Package 60ball FBGA 64Mx8 84ball FBGA 32Mx16 All of Lead free products are compliant for ROHS Note For detailed DDR2 SDRAM operation please refer to Samsung s Device operation amp Timing diagram Address Configuration Organization Row Address Column Address Bank Address Auto Precharge 64Mx8 512Mb based Module A0 A13 A0 A9 BA0 BA1 A10 32Mx16 512Mb based Module A0 A12 A0 A9 BA0 BA1 A10 ELECTRONICS Rev 1 5 Aug 2005 256MB 512MB 1GB Unbuffered SODIMMs Pin Configurations Front side Back side DDR2 SDRAM Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF 2 Vss 51 DQS2 52 DM2 101 A1 102 AO 151 DQ42 152 DO46 3 Vss 4 DQ4 53 Vss 54 Vss 103 Vpp 104 Vpp 153 DQ43 154 DQ47 5 DO0 6 DQ5 55 DQ18 56 DQ22 105 A10 AP 106 BA1 155 Vss 156 Vss 7 DO1 8 Vss 57 DO19 58 DQ23 107 BAO 108 RAS 157 DQ48 158 DQ52 9 Vss 10 DMO 59 Vss 60 Vss 109 WE 110 S0 159 DQ49 160 DQ53 11 DQSO 12 Vss 61 DQ24 62 DQ28 111 Vpp 112 Vpp 161 Vss 162 Vss 13 DQSO 14 DQ6 63 DQ25 64 DQ29 113 CAS 114 ODTO 163 NC TEST 164 CK1 15 Vss 16 DO7 65 Vss 66 Vss 115 NC S1 116 A13 165 Vss 166 CK1 17 DO2 18 Vss 67 DM3 68 DQS3 117 Vpp 1
21. cteristics amp AC Timing for DDR2 533 400 SDRAM 0 C lt TcASE lt 95 C VDDQ 1 8V 0 1V Vpp 1 8V 0 1V Refresh Parameters by Device Density Parameter Symbol 256Mb 512Mb 1Gb 2Gb 4Gb Units Refresh to active Refresh command time tRFC 75 105 127 5 195 tbd ns 0 C lt TcasE 85 C 7 8 7 8 7 8 7 8 7 8 us Average periodic refresh interval tREFI 85 C lt Tease lt 95 C 3 9 3 9 3 9 3 9 3 9 us Speed Bins and CL tRCD tRP tRC and tRAS for Corresponding Bin Speed DDR2 533 D5 DDR2 400 CC Bin CL tRCD tRP 4 4 4 3 3 3 Units Parameter min max min max tCK CL 3 5 8 5 8 ns tCK CL 4 3 75 8 5 8 ns tCK CL 5 ns tRCD 15 15 ns tRP 15 15 ns tRC 55 55 ns tRAS 40 70000 40 70000 ns Rev 1 5 Aug 2005 ELECTRONICS 256MB 512MB 1GB Unbuffered SODIMMs DDR2 SDRAM Timing Parameters by Speed Grade Refer to notes for informations related to this table at the bottom Parameter Symbol WU EU Units Notes min max min max DO output access time from CK CK tAC 500 500 600 600 ps DOS output access time from CK CK tDOSCK 450 450 500 500 ps CK high level width tCH 0 45 0 55 0 45 0 55 tCK CK low level width tCL 0 45 0 55 0 45 0 55 tCK CK half period tHP bru x ios x ps Clock cycle time
22. d according to DQ loading cap ELECTRONICS Rev 1 5 Aug 2005 256MB 512MB 1GB Unbuffered SODIMMs DDR2 SDRAM Operating Current Table 1 2 Ta 0 c VDD 1 9V M470T2953BS Y 3 M470T2953BS Y 0 128Mx64 1GB Module Symbol DDRS33 CL 4 DDR533 CL 4 DDR400GCL 3 DDR4008CL 3 Unit NOS IDDO 1 360 760 1 280 760 mA IDD1 1 440 920 1 320 840 mA IDD2P 128 128 128 128 mA IDD2Q 400 400 400 400 mA IDD2N 480 400 480 400 mA IDD3P F 480 240 480 240 mA IDD3P S 240 240 240 240 mA IDD3N 1 120 520 1 040 520 mA IDD4W 2 160 1 160 1 680 1 000 mA IDD4R 2 000 1 160 1 680 1 000 mA IDD5B 2 120 1 720 2 000 1 720 mA IDD6 88 80 88 80 mA IDD7 2 760 1 960 2 680 1 960 mA Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap Input Output Capacitance vpnp 1 8V Vopa 1 8V TA 259C Parameter Min Max Min Max Min Max Non ECC Symbol M470T6554BG Z 3 M470T3354BG Z 3 M470T2953BS Y 3 Units M470T6554BG Z 0 M470T3354BG Z 0 M470T2953BS Y 0 Input capacitance CK and CK CCK 32 24 48 Input capacitance CKE CS Addr RAS CAS WE CI 34 34 42 pF Input output capacitance DQ DM DQS Das CIO 10 6 10 DM is internally loaded to match DQ and DOS identically ELECTRONICS Rev 1 5 Aug 2005 256MB 512MB 1GB Unbuffered SODIMMs DDR2 SDRAM Electrical Chara
23. input logic high Veer 0 125 Vona 0 3 V Vi DC DC input logic low 0 3 Vrer 0 125 V Input AC Logic Level Symbol Parameter Min Max Units Notes VIH AC AC input logic high Veer 0 250 V ViL AC AC input logic low Veer 0 250 V AC Input Test Conditions Symbol Condition Value Units Notes VREF Input reference voltage 0 5 VDDQ V 1 VSWING MAX Input signal maximum peak to peak swing 1 0 V 1 SLEW Input signal minimum slew rate 1 0 Vins 2 3 Notes 1 Input waveform timing is referenced to the input signal crossing through the Viu AC level applied to the device under test 2 The input signal minimum slew rate is to be maintained over the range from Vgge to Vi AC min for rising edges and the range from Vgge to Vi AC max for falling edges as shown in the below figure 3 AC timings are referenced with input waveforms switching from VI AC to Vj4 AC on the positive transitions and V 4 AC to Vj AC on the negative transitions E Vppa FV AC min Vi DO min V SWING MAX _ VREF Vi DC max My AC max Vss delta TF delta TR Vrer Vii AC ma ViH AC min V REF VIL AC max Rising Saws IH AC min VREF Falling Slew delta TF delta TR lt AC Input Test Signal Waveform gt Rev 1 5 Aug 2005 ELECTRONICS 256MB 512MB 1GB Unbuffered SODIMMs DDR2 SDRAM IDD Specification Parameters Definition IDD values are for full operati
24. ng range of Voltage and Temperature Symbol Proposed Conditions Units Notes Operating one bank active precharge current IDDO tCK tCK IDD tRC tRC IDD tRAS tRASmin IDD CKE is HIGH CS is HIGH between valid commands mA Address bus inputs are SWITCHING Data bus inputs are SWITCHING Operating one bank active read precharge current IOUT 0mA BL 4 CL CL IDD AL 0 tCK tCK IDD RC tRC IDD tRAS tRASmin IDD tRCD tRCD IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data pattern is same as IDD4W Precharge power down current IDD2P All banks idle tCK tCK IDD CKE is LOW Other control and address bus inputs are STABLE Data bus inputs are mA FLOATING Precharge guiet standby current IDD2Q All banks idle tCK tCK IDD CKE is HIGH CS is HIGH Other control and address bus inputs are STABLE Data mA bus inputs are FLOATING Precharge standby current IDD1 mA IDD2N All banks idle tCK tCK IDD CKE is HIGH CS is HIGH Other control and address bus inputs are SWITCHING mA Data bus inputs are SWITCHING Active power down current Fast PDN Exit MRS 12 OmA mA IDD3P All banks open tCK tCK IDD CKE is LOW Other control and address bus inputs are STABLE Data bus inputs are FLOATING Slow PDN Exit MRS 12 1mA mA Active standby current IDD3N All banks open tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is
25. ollow ing page for detailed timing conditions Rev 1 5 Aug 2005 ELECTRONICS 256MB 512MB 1GB Unbuffered SODIMMs DDR2 SDRAM Operating Current Table 1 1 Ta 0 c VDD 1 9V M470T6554BG Z 3 M470T6554BG Z 0 64Mx64 512MB Module aM DDR533 CL 4 DDR533 CL 4 DDR400GCL lt 3 DDR4008CL 3 Uii ED IDDO 760 460 720 460 mA IDD1 860 560 760 520 mA IDD2P 64 64 64 64 mA IDD2Q 200 200 200 200 mA IDD2N 240 200 240 200 mA IDD3P F 240 120 240 120 mA IDD3P S 120 120 120 120 mA IDD3N 560 260 520 260 mA IDDAW 1 200 700 1 000 700 mA IDD4R 1 100 700 940 700 mA IDD5B 1 060 860 1 000 860 mA IDD6 44 40 44 40 mA IDD7 1 840 1 060 1 760 1 060 mA Module IDD was calculated on the basis of component IDD and can be differently measured according to DO loading cap M470T3354BG Z 3 M470T3354BG Z 0 32Mx64 256MB Module symbol DDRS33 CL 4 DDRS33 CL 4 DDR400GCL 3 DDR4008CL 3 Unito OES IDDO 480 360 460 360 mA IDD1 580 460 500 420 mA IDD2P 32 32 32 32 mA IDD2Q 100 100 100 100 mA IDD2N 120 100 120 100 mA IDD3P F 120 60 120 60 mA IDD3P S 60 60 60 60 mA IDD3N 280 160 260 160 mA IDDAW 920 600 740 520 mA IDD4R 820 600 680 520 mA IDD5B 780 760 740 760 mA IDD6 22 20 22 20 mA IDD7 1 560 960 1 500 960 mA Module IDD was calculated on the basis of component IDD and can be differently measure
26. ss point of the rising edge of CK and falling edge of CK CAS RAS and WE define the operation RAS CAS WE Input be executed by the SDRAM BAO BA1 Input Selects which DDR2 SDRAM internal bank is activated ODTO ODT4 Input Asserts on die termination for DQ DM DQS and DQS signals if enabled via the DDR2 SDRAM Extended Mode Register Set EMRS During a Bank Activate command cycle defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK During a Read or Write command cycle defines the column address when sampled at the cross A0 A9 point of the rising edge of CK and falling edge of CK In addition to the column address AP is used to invoke autoprecharge A10 AP Input operation at the end of the burst read or write cycle If AP is high autoprecharge is selected and BAO BAn defines the bank A11 A13 to be precharged If AP is low autoprecharge is disabled During a Precharge command cycle AP is used in conjunction with BAO BAn to control which bank s to precharge If AP is high all banks will be pecharged regardiess of the state of BAO BAn inputs If AP is low then BAO BAn are used to define which bank to precharge DO0 DO63 In Out Data Input Output pins The data write masks associated with one data byte In Write mode DM operates as a byte DMO DM7 Input mask by allowing input data to be written if it is low but blocks the write operation if it is high In Read mode DM lines have no effect The
27. uirement for SSTL 1 8 compliance However under all conditions Vppg must be less than or equal 1 fii Vner may be selected by the user to provide optimum noise margin in the system Typically the value of Vgge is expected to be about 0 5 X Vppo of the transmitting device and Vref is expected to track variations in Vppg 2 Peak to peak AC noise on Vgge may not exceed 2 Vggr DC 3 Vtr of transmitting device must track Vper of receiving device 4 AC parameters are measured with Vpp Vppo and Vpp tied together Rev 1 5 Aug 2005 ELECTRONICS 256MB 512MB 1GB Unbuffered SODIMMs Operating Temperature Condition DDR2 SDRAM Symbol Parameter Rating Units Notes TOPER Operating Temperature 0 to 95 C 1 2 3 Note 1 Operating Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 2 At 0 85 C operation temperature range are the temperature which all DRAM specification will be supported 3 At 85 95 C operation temperature range doubling refresh commands in frequency to a 32ms period tREFI 3 9 us is required and to enter to self refresh mode at this temperature range an EMRS command is required to change internal refresh rate Input DC Logic Level Symbol Parameter Min Max Units Notes Vin DC DC
28. y tOIT 0 12 0 12 ns Minimum time clocks remains ON after CKE asynchronously tDelay tISHtCK tIH tISHtCK IH a drops LOW ELECTRONICS Rev 1 5 Aug 2005 256MB 512MB 1GB Unbuffered SODIMMs DDR2 SDRAM Physical Dimensions 32Mbx16 based 64Mx64 Module 2 Rank M470T6554BG Z 3 M470T6554BG Z 0 67 60 mm gt 3 8mm 1 I Max 290 ERE 2 TE rO a b O S A a i 199 fU ELIT y a 1140 47 40 a iet Had 1625 y l 63 00 2 UL m O C Y 67 60 mm DETAIL a DETAIL b FRONT SIDE BACK SIDE 4 20 EDD 1 0 0 05 o 2 70 0 10 1 50 0 10 S he i IAE 1 80 0 10 2 40 0 10 Lou 4 dono 1 0 0 05 4 20 ee MM NDA 0 45 0 03 The used device is 32M x16 DDR2 SDRAM FBGA DDR2 SDRAM Part NO K4T51163
Download Pdf Manuals
Related Search