Kingston Technology ValueRAM KVR667D2Q8F5/4GHE memory module
Contents
1. 234 Vss 25 PN1 145 SN1 55 PN7 175 SN7 84 Vss 204 Vss 115 Vpp 235 Vpp 26 PN1 146 SN1 56 Vss 11176 Vss 85 Vss 205 Vss 116 Vpp 236 Vpp 27 Vss 147 Vss 57 PN8 177 SN8 86 RFU 206 RFU 117 Vit 237 VIT 28 PN2 148 SN2 58 PN8 178 SN8 87 RFU 207 RFU 118 SA2 238 VDDSPD 29 PN2 149 SN2 59 Vss 179 Vss 88 Vss 208 Vss 119 SDA 239 SA0 30 Vss 150 Vss 60 PN9 180 SN9 89 Vss 209 Vss 120 SCL 240 SA1 90 PS9 210 sso RFU Reserved Future Use These pin positions are reserved for forwarded clocks to be used in future module implementations These pin positions are reserved for future architecture flexibility TN EE _ _ 1 The following signals are CRC bits and thus appear out of the normal sequence PN12 PN12 SN12 SN12 PN13 PN13 SN13 SN13 PS9 PS9 SS9 SS9 VALUERAM0889 001 A00 Page 2 f kingston DIMM Connector Pin Description Pin Name Pin Description Count SCK System Clock Input positive line 1 SCK System Clock Input negative line 1 PN 13 0 Primary Northbound Data positive lines 14 PN 13 0 Primary Northbound Data negative lines 14 PS 9 0 Primary Southbound Data positive lines 10 PS 9 0 Primary Southbound Data negative lines 10 SN 13 0 Secondary Northbound Data positive lines 14 SN 13 0 Secondary Northbound Data negative lines 14 SS 9 0 Secondary Southbo2. Page 4 i Kingston Architecture Advanced Memory Buffer Pin Description Pin Name Pin Description Count FB DIMM Channel Signals 99 SCK System Clock Input positive line 1 SCK System Clock Input negative line 1 PN 13 0 Primary Northbound Data positive lines 14 PN 13 0 Primary Northbound Data negative lines 14 PS 9 0 Primary Southbound Data positive lines 10 PS 9 0 Primary Southbound Data negative lines 10 SN 13 0 Secondary Northbound Data positive lines 14 SN 13 0 Secondary Northbound Data negative lines 14 SS 9 0 Secondary Southbound Data positive lines 10 SS 9 0 Secondary Southbound Data negative lines 10 FBDRES To an external precision calibration resistor connected to Vcc 1 DDR2 Interface Signals 175 DQS 8 0 Data Strobes positive lines 9 DQS B8 0 Data Strobes negative lines 9 DQS 17 9 DM 8 0 Data Strobes x4 DRAM only positive lines These signals are driven low to x8 DRAM on writes 9 DQS 17 9 Data Strobes x4 DRAM only negative lines 9 DQ 63 0 Data 64 CB 7 0 Checkbits 8 A 15 0 A A 15 0 B Addresses A10 is part of the pre charge command 32 BA 2 0 A BA 2 0 B Bank Addresses 6 RASA RASB Part of command with CAS WE and CS 3 0 2 CASA CASB Part of command with RAS WE and CS 3 0 2 WEA WEB Part of command with RAS CAS and CS 3 01 2 2 4 4 ODTA ODTB On die Termination Enable CKE 1 0 A CKE 1 0 B Clo
3. 1 05 H O 5 DQ6 1 0 6 106 DQ38 06 H VO 6 DQ7 1 07 107 DQ39 1 07 HNO7 DOS1 DQS5 DQS1 T T pass DQS10 t DQS14 NU 6 Das Das Ras Roas CS Das Das RNG Rens Cs Das Das Bias NU C5 Das Das Rias Rugs CS pas Das RBas Roas CS Pas Dos pas 1 00 H voo DQ40 1 00 H voo DQ9 1 01 D1 H o 1 D10 DQ41 1 01 D5 H 101 D14 DQ10 1 02 H 1 02 DQ42 1 0 2 H 02 Da1 1 0 3 H O3 DQ43 1 03 H 110 3 DQ12 N04 vO4 DQ44 04 H VO 4 DQ13 1 0 5 H VO 5 DQ45 1 0 5 H 05 DQ14 06 H 106 DQ46 1 O 6 H 106 DQ15 1 07 H NO 7 DQ47 1 07 H 107 puo DQS6 DQS2 DAs6 t DOS DQS15 BN Me cs Das bas Blas s cs Das Das Bs NUL CS DOS DOS Was Nos cs Das Das BM puana Das pas Ras Anas CS Das Das pais 1 0 0 H uoo DQ48 1 0 0 H 1 00 00 1 00 DQ17 NO 1 D2 H LO 1 D11 DQ49 4 01 D6 p VO 1 D15 pais I 02 H 102 paso 1 02 H O 2 DQ19 1 03 Hos DQ51 1 03 H 1 03 D Q20 1 04 H NO 4 DQ52 1 0 4 H O 4 DQ21 105 H VO 5 DQ53 05 H N05 DQ22 1 06 Hoe DQ54 1 06 H 106 DQ23 VO 7 H VO 7 Dass 1 07 H 107 DOS3 1 DQS7 DQs3 T DQS7 DQS12 DQS16 T Rios NUL C Das Das Ras Rons CS Das Das Rias Nurs cs pasas RBG Nang cs DOS bas Ros SUL CS Das bas Ros SUG C Das Das RAGS Nos CS DOS Das DQ24 1 00 H 1o 0 VO O Dass 1 0 0 q 1 0 0 100 DQ25 4 1 01 D3 H VO 1 D1
4. 2 DQ57 1 01 D7 H o1 D16 DQ26 02 FO 2 pass 1 02 H 1102 DQ27 03 H VO 3 DQ59 1 03 H 0 3 DQ28 04 H 04 DQ60 1 04 H 0 4 DQ29 1 O 5 H V0 5 DQ61 1 05 H 0 5 DQ30 1 06 H 06 DQ62 1 06 H 06 DQ31 1 07 H W07 DQ63 4 07 HO 7 pass pass DQS17 Blas S cs Das Das Bas Bas cs Dasbas Rbas pas CS DOS Das Ras bas CS DOS Das CB0 1 0 0 H uoo CB1 1 0 1 D8 H uo 1 D17 CB2 1 0 2 H 1102 CB3 1 0 3 H HO 3 CB4 1 0 4 H N04 cB5 1 05 H HO 5 CB6 1 0 6 H O 6 CB7 1 07 H 1107 PNO PN13 SNO SN13 PNO PN13 SNO SN13 PS0 PS9 SS0 SS9 PS0 PS9 L 550 559 A S0 CS D0 D8 S2 gt CS D18 D26 Mb CKEO gt CKE D0 D8 D18 D26 81 gt CS D9 D17 S3 gt CS D27 D35 B CKE1 gt CKE D9 D17 D27 D35 SCL ODT gt ODT all SDRAMs VIT r Terminators SDA BA0 BA2 all SDRAMs SA1 SA2 A0 A15 all SDRAMs Voc AMB SAO RAS all SDRAMs L A 1 L CAS all SDRAMs RESET WE all SDRAMs VppsPD SPD AMB SCK SCK CK CK all SDRAMs T 1 V t D0 D35 AMB i 825 220 DD All address command control clock J VIT VREF D0 D35 Notes T Es Serial PD 1 DQ to I O wiring may be changed within a byte Vss i T i D0 D35 SPD AMB SCL 2 There are two physical copies of each p gt SDA WP AO A1 A2 address command control clock SAO SA1 SA2 VALUERAM0889 001 A00
5. N10 183 SN10 93 PS5 213 SS5 4 Ves 124 Vss 34 PN4 154 SN4 64 PN10 184 SN10 94 PS5 214 SS5 5 Voo 125 Vpp 35 PN4 155 SN4 65 Vss 185 Vss 95 Vss 215 Vss 6 Voo 126 Vpp 36 Vss 156 Vss 66 PN11 186 SN11 96 PS6 216 SS6 7 Vpp 127 Vpp 37 PN5 157 SN5 67 PN11 187 SN11 97 PS6 217 Ss6 8 Vss 128 Vss 38 PN5 158 SN5 68 Vss 188 Vss 98 Vss 218 Vss 9 Vec 129 Voc 39 Vss 159 Vss EY 99 PS7 219 SS7 10 Vec 130 Vcc 40 PN13 160 SN13 69 Vss 189 Vss 100 Ps7 220 SS7 11 Ves 131 Vss 41 PN13 161 SN13 70 PSO 190 sso 101 Vss 221 Vss 12 Voc 132 Vec 42 Vss 162 Vss 71 PS0 191 sso 102 PS8 222 SS8 13 Voc 133 Vcc 43 Vss 163 Vss 72 Vss 192 Vss 103 Ps8 223 SS8 14 Vss 134 Vss 44 RFU 164 RFU 73 PS1 193 SS1 104 Vss 224 Vss 145 Vir 11135 VIT 45 RFU 165 RFU 74 PS1 194 SS1 105 RFU 225 RFU 16 VID1 136 VIDO 46 Vss 166 Vss 75 Vss 195 Vss 106 RFU 226 RFU 17 RESET 137 DNU M_Test 47 Vss 167 Vss 76 PS2 196 ss2 107 Vss 227 Vss 18 Vss 138 Vss 48 PN12 168 SN12 77 PS2 197 ss2 108 Vpp 228 SCK 19 RFU 139 RFU 49 PN12 169 SN12 78 Vss 198 Vss 109 Vpp 229 SCK 20 RFU 140 RFU 50 Vss 170 Vss 79 PS3 199 ss3 110 Vss 230 Vss 21 Vss 141 Vss 51 PNG 171 SN6 80 PS3 200 553 111 Vpp 231 Vpp 22 PNO 142 SNO 52 PN6 172 SN6 81 Vss 201 Vss 112 Vpp 232 Vpp 23 PNO 143 SNO 53 Vss 173 Vss 82 PS4 202 Ss4 113 Vpp 233 Vpp 24 Vss 144 Vss 54 PN7 174 SN7 83 Ps4 203 S84 114 Vss
6. Voltage on V TT pin relative to V ss 0 5 2 3 V Tarc Storage temperature 55 100 C Tease DDR2 SDRAM device operating temperature Ambient 0 95 1 C AMB device operating temperature Ambient 0 110 C Note 1 Above 85 C DRAM case temperature the Auto Refresh command interval has to be reduced to tREFI 3 9 us VALUERAM0889 001 A00 Page 3 Functional Block Diagram f kingston 3 52 S1 S0 Daso Das4 Daso I I DOS4 1 i DQS9 T DQS13 Bias Nas CS DAS DOS Rpas RD GS DAS Das Ahas Roas CS Das DOS Pos S cs Das Das Dos Mos cs DAS DAS aas s TS Das Das DQ0 1 0 0 1 00 DQ32 1 00 H voo DQ1 1 01 DO VO 1 D9 DQ33 1 01 D4 H 101 D13 DQ2 1 0 2 110 2 DQ34 1102 HO 2 DQ3 1 03 110 3 DQ35 1 0 3 H HO 3 DQ4 1 04 104 DQ36 1 0 4 H 1 0 4 DQ5 4 1 0 5 1 10 5 DQ37
7. ck Enable one per rank CS 1 0 A CS 1 0 B Chip Select one per rank CLK 1 0 used on 9 and 18 device DIMMs CLK 3 0 used on 36 device DIMMs CLK 3 2 should be out CLKI3 0 put disabled when not in use CLK 3 0 Negative lines for CLK 3 0 4 DDRC C14 DDR Compensation Common return pin for DDRC_B18 and DDRC C18 1 DDRC B18 DDR Compensation Resistor connected to common return pin DDRC C14 1 DDRC C18 DDR Compensation Resistor connected to common return pin DDRC C14 1 DDRC B12 DDR Compensation Resistor connected to Vss 1 DDRC C12 DDR Compensation Resistor connected to Vpp 1 VALUERAM0889 001 A00 Page 5 Advanced Memory Buffer Pin Description f Kingston SPD Bus Interface Signals 5 SCL Serial Presence Detect SPD Clock Input 1 SDA SPD Data Input Output 1 SA 2 0 SPD Address Inputs also used to select the DIMM number in the AMB 3 Miscellaneous Signals 163 PLLTSTO PLL Clock Observability Output 1 VCCAPLL Analog VCC for the PLL Tied with low pass filter to VCC 1 VSSAPLL Analog VSS for the PLL Tied to ground on the AMB die Do not tie to ground on the DIMM 1 TEST pin Leave floating on the DIMM 6 TESTLO pins Tie to ground on the DIMM 5 BFUNC Tie to ground to set functionality as buffer on DIMM 1 RESET AMB reset signal 1 NC No connect Many NC are connected to VDD on the DIMM to lower the impedance of th
8. e VDD power 129 islands RFU Reserved for Future Use 18 Power Ground Signals 213 Voc AMB Core Power 1 5 Volt 24 VecFBD AMB Channel I O Power 1 5 Volt 8 Vpp AMB DRAM I O Power 1 8 Volt 24 Vppspp SPD Power 3 3 Volt 1 Vss Ground 156 Total 655 1 System Clock Signals SCK and SCK switch at one half the DRAM CK CK frequency 2 TESTLO_AB20 and TESTLO AC20 should be configured for debug purposes on prototype DIMMs each pin should have a zero ohm resistor pulldown to ground and an unpopulated resistor pullup to VCC These resistors can be replaced on production DIMMs with a direct connection to ground VALUERAM0889 001 A00 Page 6 Y n imensions Package D R42 R34 R26 182 199 jL 0912 1819 j o o ooo coo oo 6513 ar v9 082 995 R24 R28 EXISTIT E EE E 99 012 Je 299 1919 o ooo oOo o oo Festa OLIO ata ety 0819 n 282i 2912 O WR WO WB WB o RIG a R2 C44 0000 O NG acs C172 C47 C43 f C46 4 C171 m 5 2 Le RTAS 3 ar oo 000 o o 61d 22 685 29 9112 7 16 Stu C48 ZLE SZ MUN o oo onoono o 691 W129 do DOO Cim o L 6h TOLY 0212 YOLA m ll Baas 2018 2 018 7 f a O J L O R709 711 R707 R706 R708 C107 C108 C106 C104 Ju ong R47 C175 R3 C87 L O bro C14 4p C3 C36 E FEIERT R22 El C86 PRIMARY SID bng 101 L 3 cioog NG R45 C99 o
9. kingston M Memory Module Specifications KVR667D2Q8F5 4GHE 4GB 512M x 72 Bit PC2 5300 CL5 ECC 240 Pin FBDIMM Description This document describes ValueRAM s 512M x 72 bit 4GB PC2 5300 CL5 SDRAM Synchronous DRAM fully buffered ECC quad rank memory module This module is based on thirty six 128M x 8 bit 667MHz DDR2 FBGA components The module also includes an AMB device Advanced Memory Buffer The electrical and mechanical specifications are as follows Feature DRAM Supported FBDIMM Module 240 pin Hynix E die JEDEC Standard Memory Organization 4 rank of x8 devices e DDR2 DRAM Interface SSTL_18 e DDR2 Speed Grade 667 Mbps CAS Latency 5 5 5 e Module Bandwidth 5 3 GB s e DRAM VDD VDDQ 1 8V e AMB VCC VCCFBD 1 5V e EEPROM VDDSPD 3 3V typical e Heat Spreader Full DIMM Heat Spreader FDHS e PCB Height 30 35mm double side e RoHS Compliant VALUERAM0889 001 A00 02 02 10 Page 1 DDR2 240 pin FBDIMM Pinout f kingston Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Side Side Side Side Side Side Side Side 1 Vpp 121 Vpp 31 PN3 151 SN3 61 PN9 181 SN9 91 PS9 211 SS9 2 Vpp 122 Vpp 32 PN3 152 SN3 62 Vss 182 Vss 92 Vss 212 Vss 3 Voo 123 Vpp 33 Vss 153 Vss 63 P
10. os C92 C93 C94 C95 R30 RT C135 C126 C91 R11 z B B C37 R33 eios 127mm C184 amp 133 35 866001 gt 0 75 MAX 30 35 Page 7 R TYP jw DEG 2 PLACES C 1 50 DIA 0 10 c wo N VIEWED FROM LAYER 1 SIDE VALUERAM0889 001 A00
11. und Data positive lines 10 SS 9 0 Secondary Southbound Data negative lines 10 SCL Serial Presence Detect SPD Clock Input 1 SDA SPD Data Input Output 1 SA 2 0 SPD Address Inputs also used to select the DIMM number in the AMB 3 VID 1 0 Voltage ID These pins must be alce for a Fully Mia pde g 3 VID O is Vpp value OPEN 1 8 V GND 1 5 V VID 1 is Vcc value OPEN 1 5 V GND 1 2 V RESET AMB reset signal 1 RFU Reserved for Future Use 16 Vec AMB Core Power and AMB Channel Interface Power 1 5 Volt 8 Vop DRAM Power and AMB DRAM I O Power 1 8 Volt 24 VIT DRAM Address Command Clock Termination Power V pp 2 4 Vois SPD Power 1 Vss Ground 80 The DNU M_Test pin provides an external connection on R Cs A D for testing the margin of Vref which is produced by a voltage divider on the module It DNU M Test is not intended to di used in normal system operation and must not be l 4 connected DNU in a system This test pin may have other features on future card designs and if it does will be included in this specification at that time 4 Total 240 1 System Clock Signals SCK and SCK switch at one half the DRAM CK CK frequency 2 Eight pins reserved for forwarded clocks eight pins reserved for future architecture flexibility Absolute Maximum Ratings Symbol Parameter MIN MAX Units VIN VOUT Voltage on any pin relative to V ss 0 3 1 75 V VCC Voltage on V CC pin relative to V ss 0 3 1 75 V VDD Voltage V DD pin relative to Vss 0 5 2 3 V VIT
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