Home
ADATA 2GB DDR2 PC2-8500 SC Kit
Contents
1. yo vss re soa 159 pas so pos 239 Se 40 paz eo pasz 120 sc vss 20 Doy ao SM ADQYF1A08 DDR2 1066G CL 6 1GB 128Mx8 Pb free Rev 0 2009 03 30 Page 3 of 7 PODaTA Pin Description CK0 CK2 FUNCTION System Clock Active on the positive and negative edge to sample all inputs CK0 CK2 CKEO Clock Enable Nu Masks system clock to freeze operation from the next clock cycle CKE should be enabled at least on cycle prior new command Disable input buffers for power down in standby Disables or Enables device operation by masking or enabling all input except CK CKE and L U DQM Row Column address are multiplexed on the same pins Row Address AO A13 Column Address A0 A9 Auto precharge A10 AP AO0 A13 Address BAO BA2 Banks Select DQ0 DQ63 Data Data and check bit inputs outputs are multiplexed on the same pins Selects bank to be activated during row address latch time Selects bank for read write during column address latch time DQS0 DQS 7 Data Strobe Bi directional Data Strobe DQS0 DQS7 When high termination resistance is enabled for all DQ DQ and DM pins assuming the ODTO On Die Termination function is enabled in the Extended Mode Register Set This pin is recommended to be left No Connection on the device ADQYF1A08 DDR2 1066G CL 6 1GB 128Mx8 Pb free Rev 0 2009 03 30 Page 4 of 7 Block Diagram DQS0 DQS0 A
2. DA A A Wonderful Memory K a d E 1 641165 120 121 184 1185 240 D C K C 0 50 0 020 133 3545 250 min C of On Y D S PETA NTA TT WY ca 27 63 002 480 1 35 00 2 165 5 T2 710410 4 00 0 157 l I C amp de CO C c US e H t Huo0 amp p39 2S o 5 wo C w 0 80 0 05 0 021 Xx9 002 Detail A ADQYF1A08 DDR2 1066G CL 6 1GB 128Mx8 Pb free 005 x 0700472 3 000 118 10 00 0 394 17 8000 70 Note 1 Tolerance 0 127mm 0 005 Inches 4 00 C0 15 7 c 90C0 098 0 2 0MM Ma x 0 05MMC Mind i d 0 20MMCMax O 0 059 4 0 004 0 05MMCMiIn c M Detail B View R B CUptionald Rev 0 2009 03 30 Page 7 of 7
3. DMO DQSI w DOS DMI DOS2 DQS2 DM2 DQS3 DM3 BAO BA2 A0 A15 RAS w CKEO WE ODTO ADQYF1A08 DDR2 1066G CL 6 1GB 128Mx8 Pb free DQ24 DQ25 DQ26 DQ27 DQS4 DQS4 DNA DQO DO DQ DQ3 DQ4 DQS DQ6 DQ7 DO DQS5 DQS5 DM5 DOS DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 D1 DQS6 DQS6 DM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 D2 DQS7 DQS7 DM7 DM CS DQS DQS LO 0 VO 1 UO 2 LO 3 LO 4 LO 5 LO 6 UO 7 D3 DQ28 DQ29 W DQ30 DQ31 Serial PD 5 DATA esr DM CS DQS DQS LO 0 UO 1 LO 2 L O 3 VO 4 UO 5 LO 6 LO 7 D4 DM CS DQS DQS LO 0 LO 1 LO 2 V0 3 1 O 4 LO 5 LO 6 IO 7 D5 DM CS DQS DQS LO 0 LO 1 LO 2 LO 3 LO 4 VO 5 LO 6 D6 D7 Clock Wiring Clock Input DDR2 SDRAMs CK0 CK0 2 DDR2 SDRAMs CK1 CK1 3 DDR2 SDRAMs BAO BA2 SDRAMs D0 D7 A0 A15 SDRAMs D0 D7 RAS SDRAMs D0 D7 CAS SDRAMs D0 D7 SPD CKE SDRAMs D0 D7 DO D8 WE SDRAMs D0 D7 ODT SDRAMs D0 D7 DO D8 DO D amp Rev 0 CK2 CK2 3 DDR2 SDRAMs Wire per Clock Loading TableANiring Diagrams Notes 1 DQx DMx DQSx DQSx resistors 22 Q 5 2 BAx Ax RAS CAS ANE resistors 10 Q x 596 2009 03 30 Page 5 of 7 KBAT Absolute Maximum Ratings Voltage on VDD supply relative to Vss BEEN 1 0 2 3 V Voltage on VDDQ supply relative to Vss 0
4. Off Chip Driver OCD Impedance Adjustment On Die Termination ODT Lead free products are RoHS compliant e EEPROM VDDSPD 3 3V Typical e PCB Height 30 00mm 1 181 Single sided component Clock Cycle Time tCK DDR2 800 tCK 2 5ns DDR2 1066 tCK 1 875ns Refresh to Active Refresh Command Time tRFC 127 5ns ADQYFIAOS DDR2 1066G CL 6 IGB 128Mx8 Pb free Rev 0 2009 03 30 Page 2 of 7 Pin Assignment Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 ver a vss s pas 121 vss__ 161 No ch 201 vss 2 vss 4 ncco e vss 122 pas 162 Nc cas 202 ow 5 Do 43 ncc as masa 123 pas 163 vss 203 No 4 ca a vss a pos 1a vss so nc ome 204 vss 5 vss 45 nc mass ss vss 125 pmo 165 Noc 205 pas 6 maso 46 no oass se Das 126 Nc se vss 206 Doo 7 paso a vss a7 pos 127 vss ser No cee 207 vss 8 vss 4 Noce2 s vss 128 Doe 168 Nc ca7 208 pass 9 pa 49 noces s pao 79 oar 169 vss 29 pas 0 Dos 60 vss o pan vss so von 210 vss vss s vwa o vss 131 pam 11 cker fen oms 2 pa s ce e mass 12 pats 192 vob 22 No 8 Dos ss von 9 pos 133 vss a s 213 vss m vss s Bw o vss t om tv am 24 Doo s ios 55 Nc o pa 1
5. 35 wc vrs von 215 por 16 vast se voa pae vss ie a 216 vss vss s an or vss t ox vr 217 oo pe NO s a pae 138 jc i voo 218 pos p19 Noc s vob pao 139 vss o a 219 vss 2 vss e as too vss pan 180 as 220 co p21 pa e m ror sa ta pass ss von 221 k 2 pon e vooa w2 nomesti 12 vss 182 as 222 vss vss es a s vss o poo 183 m 23 ome 2 Date o voo 14 mase 4 paz se voo 224 NO 25 Dar es vss 105 pose 5 vss ses ck 225 vss vss o vss t vss 146 oma s8 cko 226 pasa 2 masa e vo y pos t47 nc se voo 227 Dos 25 pase e No we pas 148 vss se ao 228 vss vss e vo 109 vss 149 paz se voo 29 Doo 30 Date zo atop to pase 150 pa 190 BM 230 Dos 3 par hr Be m pov ts1 vss 191 von 231 vss 32 vss 72 vwa 12 vss 5 pas 192 mas 282 oW 3 Dam 73 me n masr 9 pom 193 so 283 No pas 74 sas n pos ts vss s von 2w vss 355 vss 75 vwa 15 vss 155 pms 195 oor 235 pas mass 7 s ne Dass 156 nc 196 Ao 2 Doo sr poss 7 oor mr pos 157 vss s voo 287 vss 38 vss vwa ne vss 158 pas 198 vss 238 VDDSPD vas
6. 5 2 3 V Voltage on VDDL supply relative to Vss 0 5 2 3 V Note DDR2 SDRAM component specification Operation Temperature Condition Soi me s so Note 1 If the DRAM case temperature is above 85 C the Auto Refresh command interval has to be reduced to tREFI 3 9us DC Operating Condition Voltage referenced to Vss OV VDD amp VDDQ 1 8V 0 1V Tc 0 to 85 C ote mM w M wm ees J E p Input Reference Voltage 0 49 x VDDQ 0 51 x VDDQ mm Termination Voltage v o VREF 0 04 VREF 0 04 Pov o3 2 Note 1 There is no specific device VDD supply voltage requirement for SSTL 1 8 compliance However under all conditions VDDQ must be less than or equal to VDD 2 The value of VREF may be selected by the user to provide optimum noise margin in the system Typically the value of VREF is expected to be about 0 5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ 3 Peak to peak ac noise on VREF may not exceed 2 VREF ac 4 VTT of transmitting device must track VREF of receiving device 5 VDDQ tracks with VDD VDDL tracks with VDD AC parameters are measured with VDD VDDQ and VDDL tied together ADQYF1A08 DDR2 1066G CL 6 1GB 128Mx8 Pb free Rev 0 2009 03 30 Page 6 of 7 Package Dimensions jJO P B t
7. B t DA A A Wonderful Memory 1 DATA Memory Module Data Sheet A Wonderful Memory ADQYF1A08 DDR2 1066G CL6 240 Pin O C U DIMM 1GB 128M x 64 bits General Description The ADATA s ADQYF1A08 is a 128Mx64 bits 1GB DDR2 1066 CL6 SDRAM over clocking memory module The SPD is programmed to JEDEC standard latency 800Mbps timing of 5 5 5 18 at 1 8V The module is composed of eight 128Mx8 bits CMOS DDR2 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TSSOP TSOP package on a 240pin glass epoxy printed circuit board The ADQYF1A08 is a Dual In line Memory Module and intended for mounting onto 240 pins edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operating frequencies programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features Power supply Normal VDD amp VDDQ 1 8V 0 1V e 1 8V SSTL 18 compatible I O Timing Reference DDR2 800 CL5 5 5 18 at 1 8V DDR2 1066 CL6 6 6 15 at 2 1V Burst Length 4 8 Programmable Additive Latency O 1 2 3 4 Bi directional differential data strobe DQS and DQS Differential clock input CK CK operation DLL aligns DQ and DOS transition with CK transition Double data rate architecture Auto amp Self refresh e Average Refresh period 7 8ps
Download Pdf Manuals
Related Search
Related Contents
1 WELCOME présentation CVE enquete mobilité étudiants avril 2011_FINALE Manuale installazione FitFire_ eng TAFCO WINDOWS NU2-252S-I Installation Guide CPS-V39005-23 AVM FRITZ!Box 7390 International DSL Wi-Fi Ethernet LAN Red, Silver StormChaser Manual - Sound Productions PDFダウンロード(6.76MB) Mechanical ventilation - PACT TXT Fleet Gas 04-07 owners guide Copyright © All rights reserved.
Failed to retrieve file