Elixir 2GB DDR3-1066MHz SO-DIMM
Contents
1. Serial PD Data Entr Byte Description SEU gi Hexadecimal Note BE CG BE CG CRC Covers Bytes 0 116 0 CRC range EEPROM bytes bytes used Total SPD Bytes 256 92 SPD Bytes Used 176 1 SPD revision Revision 10 10 2 DRAM device type DDR3 SDRAM 0B 3 Module type form factor SO DIMM 03 4 SDRAM Device density and banks 8 banks 1Gb 02 5 SDRAM device row and column count 13 rows 10 columns 09 6 Reserved Undefined 00 7 Module ranks and device DQ count 2 ranks 16 bits 0A 8 ECC tag and module memory Bus width Non ECC 64bits 03 9 Fine timebase dividend divisor in ps 2 5ps 52 10 Medium timebase dividend ins 01 11 Medium timebase divisor 8ns 08 12 Minimum SDRAM cycle time tCKmin 1 875ns 1 5ns OF 0c 13 Reserved Undefined 00 14 CAS latencies supported 6 7 8 6 8 9 1C 34 15 CAS latencies supported Undefined 00 16 Minimum CAS latency time tAAmin 13 125ns 13 5ns 69 6C 17 Minimum write recovery time tWRmin 15ns 78 18 Minimum CAS to CAS delay tRCDmin 13 125ns 13 5ns 69 6C 19 Minimum Row Active to Row Active delay tRRDmin 10ns 7 5ns 50 3C 20 Minimum row Precharge delay tRPmin 13 125ns 13 5ns 69 6C 21 Upper nibble for tRAS and tRC 1 1 11 22 Minimum Active to Precharge delay tRASmin 37 5ns 36ns 2C 20 23 Minimum Active to Active Refresh delay tRCmin 50 625ns 49 5ns 95 8C 24 Minimum refresh recovery delay tRFCmin LSB Combo bytes 24 25 70 25 Minimum refresh recovery delay tRFCmin MSB 110ns 03 26 Minimum inte2. 35 DQ11 36 DQ15 87 Voo 88 Vpp 139 Vss 140 DQ38 189 Vss 190 Vss 37 Vss 38 Vss 89 A8 90 A6 141 DQ34 142 DQS39 191 DQ58 192 DQ62 39 DQ16 40 DQ20 91 A5 92 A4 143 DQ35 144 Vss 193 DQ59 194 DQ63 41 DQ17 42 DQ21 93 Voo 94 Voo 145 Vss 146 DQ44 195 Vss 196 Vss 43 Vss 44 Vss 95 A3 96 A2 147 DQ40 148 DQ45 197 SAO 198 EVENT 45 DQS2 46 DM2 97 A1 98 A0 149 DQ41 150 Vss 199 Vppsep 200 SDA 47 DQS2 48 Vss 99 Voo 100 Vpp 151 Vss 152 DQS5 201 SA1 202 SCL 49 Vss 50 DQ22 101 CKO 102 CK1 153 DM5 154 DQS5 203 Vit 204 Vit 51 DQi8 52 DQ23 103 CKO 104 CK1 Note A13 is for 2GB modules only REV1 1 3 04 2009 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64CBH8A5P M2N2G64CB8HA5N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SO DIMM elixir Input Output Functional Description Symbol CKO CK1 CKO CK1 CKEO CKE1 0 RAS CAS WE ODTO ODT1 DMO DM7 DQS0 DQS7 DQS0 DQS7 BAO BA1 BA2 A0 A9 A10 AP A11 A12 BC A13 DQO DQ63 Vop Vppspo Vss Vnerpo VREFCA SDA SCL SAO SA2 EVENT RESET REV1 1 04 2009 Type Input Input Input Input Input Input O Input Input Input Supply Supply 1 0 Input Input Output Input Polarity Cross point Active High Active Low Active Low Active
3. DDR3 1066 DDR3 1333 Symbol Parameter Units Note Min Max VIH DC DC input logic high Vref 0 100 VDD V 1 VIL DC DC input logic low VSS Vref 0 100 V 1 VIH AC AC input logic high Vref 0 175 V 1 VIL AC AC input logic low Vref 0 175 V 1 VrefDQ DC Reference Voltage for DQ DM inputs 0 49 VDD 0 51 VDD V 2 3 VrefCA DC Reference Voltage for ADD CMD inputs 0 49 VDD 0 51 VDD V 2 3 Note 1 For DQ and DM Vref VrefDQ For input only pins except RESET Vref VrefCA 2 The AC peak noise on Vref may not allow Vref to deviate from Vref DC by more than 1 VDD 3 For reference approx VDD 2 15mV REV1 1 11 04 2009 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64CBH8A5P M 2N2G64CB8HA5N 1GB 128M x 64 2GB 256M x 64 elixir Unbuffered DDR3 SO DIMM Operating Standby and Refresh Currents Toase 0 C 85 C Vona Vpp 1 5V 0 075V 1GB 2Ranks base on 64Mx16 DDR3 SDRAMs Symbol Parameter Condition DDR3 1066 DDR3 1333 Unit DDo Operating Current one bank activate Precharge 554 598 mA DD1 Operating Current one bank activate Read Precharge 664 752 mA DD2P 0 Precharge Power Down Current Fast Exit MRO bit A12 0 141 141 mA DD2P 1 Precharge Power Down Current Slow Exit MRO bit A12 1 264 264 mA DD2N Precharge Standby Current 572 616 mA DD2Q Precharge Quiet Standby current 484 528 mA DD3P Active Power
4. I T eevee A hl RA RA RY RAS RA vt e gt vt Vooso SPD TS SCL gt SCL Qe san sao gt A0 Temp Sensor REFDQ a gt SDA SA1 9 A1 Pe Voo es 31 DO D15 A2 EVENT Vss 9 9 gt D0 D15 SPD Temp sensor I cko ___________ D0 D7 EVENT cki _________ D8D15 cKO ________ Do D7 sce CKE ________ 8 D15 SCL CKEO D0 D7 sao gt Ao SPD mE penis l4 SDA pD sai 1 Wi so gt D0 D7 qo S1 p D8 D15 Notes 1 DQ wiring may differ from that shown however DQ DM DQS and DOGS relationships are maintained as shown REV1 1 04 2009 ODTO ODT1 gt D0 D7 p D8 D15 EVENT Temp Sensor RESET p DO0 D15 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64CBH8A5P M2N2G64CB8HA5N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SO DIMM Serial Presence Detect Part 1 of 2 1GB 128Mx64 2Ranks DDR3 SODIMM based on 64Mx16 1 5V DDR3 SDRAMs with SPD el IXIr
5. CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64CBH8A5P M 2N2G64CB8HA5N 1GB 128M x 64 2GB 256M x 64 elixir Unbuffered DDR3 SO DIMM Revision Log Rev Date Modification 0 1 07 2008 Preliminary edition 1 0 09 2008 Official Release 1 1 04 2009 Re move A4P A4N Part Numbers Add A5P and A5N Part Numbers Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd Kueishan Taoyuan 333 Taiwan R O C Tel 886 3 328 1688 Please visit our home page for more information www nanya com Printed in Taiwan 2008 REV1 1 19 04 2009 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice
6. High Active High Cross point Function The system clock inputs All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK A Delay Locked Loop DLL circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high When the command decoder is disabled new commands are ignored but previous operations continue Rank 0 is selected by S0 Rank 1 is selected by S1 When sampled at the positive rising edge of CK and falling edge of CK signals RAS CAS WE define the operation to be executed by the SDRAM Asserts on die termination for DQ DM DQS and DQS signals if enabled via the DDR3 SDRAM mode register The data write masks associated with one data byte In Write mode DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high In Read mode DM lines have no effect The data strobes associated with one data byte sourced with data transfers In Write mode the data strobe is sourced by the controller and is centered in the data window In Read mode the data strobe is sourced by the DDR3 SDRAM and
7. output access time from rising CK tDOSCK 300 300 255 255 ps DQS DOS low impedance time Reference from RL 1 tLZ DQS 600 300 500 250 ps ELS DQS high impedance time Reference from RL tHZ DQS 300 250 ps DGS DQS differential input low pulse width tDQSL 0 4 0 6 0 4 0 6 tCK avg DGS DQS differential input high pulse width tDQSH 0 4 0 6 0 4 0 6 tCK avg DQS DQS rising edge to CK CK rising edge tDQSS 0 25 0 25 0 25 0 25 tCK avg DGS DOGS falling edge setup time to CK CK rising edge tDSS 0 2 0 2 tCK avg DQS DQS falling edge hold time to CK CK rising edge tDSH 0 2 0 2 tCK avg REV1 1 14 04 2009 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64CBH8A5P M2N2G64CB8HA5N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SO DIMM el IXIr DDR3 1066 DDR3 1333 Parameter Symbol Min Max Min Max Units Command and Address Timing DLL locking time tDLLK 512 512 nCK d READ Command to PRECHARGE Command tRTP max 4nCK 7 5ns j max 4nCK 7 5ns oe start of internal write transaction to internal read twTR max 4nCK 7 5ns max 4nCK 7 5ns 7 WRITE recovery time tWR 15 15 E ns Mode Register Set command cycle time tMRD 4 4 nCK Mode Register Set command update delay tMOD max 12nCK 15ns max
8. time with Write command and BL8 ODTH8 6 6 nCK oa RTT turn on delay Power Down with DLL tAONPD 1 9 1 9 ns Asynchronous RTT turn off delay Power Down with DLL tAOFPD 1 9 1 9 ns frozen RTT turn on tAON 300 300 250 250 ps RTT Nom and RTT WR turn off time from ODTLoff tAOF 0 3 0 7 0 3 0 7 tCK avg reference RTT dynamic change skew tADC 0 3 0 7 0 3 0 7 tCK avg Write Leveling Timings First DQS DQS rising edge after write leveling mode is tWLMRD 40 40 nCK programmed DQS DQS delay after write leveling mode is programmed tWLDQSEN 25 25 nCK Write leveling setup time from rising CK CK crossing to rising DQS DQS crossing WLS 245 195 ps Write leveling setup hold from rising CK CK crossing to rising DQS DQS crossing ida 245 195 ps Write leveling output delay tWLO 0 9 0 9 ns Write leveling output error tWLOE 0 2 0 2 ns REV1 1 16 04 2009 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64CBH8A5P M2N2G64CB8HA5N m 1GB 128M x 64 2GB 256M x 64 elixir Unbuffered DDR3 SO DIMM Package Dimensions 1GB 2 Ranks 64Mx16 DDR3 SDRAMs 67 60 0 15 2 661 0 006 2 0 63 60 3 8max 0 079 2 504 0 150max A 30 0 4 0 15 1 181 4 0 006 0 787 1 04 0 07 0 1 E e 0 039 0 004 2x 91 80 0 071 2x 4 0 0 1 0 157 0 004 i 4 LA 4 u u I 1 Ns
9. 12nCK 15ns CAS to CAS command delay tCCD 4 4 nCK Auto precharge write recovery precharge time tDAL min WR roundup tRP tCK avg nCK Multi Purpose Register Recovery Time tMPRR 1 1 ACTIVE to ACTIVE command period for 1KB page size tRRD max 4nCK 7 5ns max 4nCK ens Four activate window for 1KB page size tFAW 37 5 30 7 ns Weve eve setup time to CK referenced to tIS base 125 65 7 ps hee ieee hold time to CK CK referenced to tlH base 200 7 140 ps Calibrating Timing Power up and RESET calibration time tZGinit 512 512 nCK Normal operation Full calibration time tZQoper 256 256 nCK Normal operation Short calibration time tZQCS 64 64 nCK Reset Timing max 5nCK max 5nCK Exit Reset from CKE HIGH to a valid command tXPR tRFC min tRFC min 10ns 10ns Self Refresh Timings max 5nCK max 5nCkK Exit Self Refresh to commands not requiring a locked DLL tXS tRFC min tRFC min 10ns 10ns Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK min tDLLK min nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR pin boe E Pao a Self Refresh Entry SRE O ickoBE max SnCK 10ns max 5nCK 10ns Habs ds after Self Refresh Exit SAX or ioKSRy max SnCK 10ns max 5nCK 10ns Power Down Timings Exit Power Down with DLL on to any valid command Exit Precharge Power Down with DLL frozen to commands not tXP max 3nCK 7 5ns max 3nCK 6ns requiring a
10. 1GB 256Mx64 2Ranks DDR3 SODIMM based on 128Mx8 1 5V DDR3 SDRAMs with SPD elixir Serial PD Data Entry Byte Description TREA Hexadecimal Note BE CG BE CG 61 Module thickness Max E Muriel ae n 11 62 Raw Card ID reference Raw Card F 05 63 DRAM address mapping edge connector Undefined 00 64 116 Reserved 117 118 Module manufacture ID 830B 119 125 Module information 126 127 CRC 84E6 56C0 128 145 Module part number Undefined 146 Module die revision Undefined 00 147 Module PCB revision Nanya Technology 00 148 149 DRAM device manufacturer ID 830B 150 175 Manufacturer reserved Undefined 176 255 Customer reserved REV1 1 10 04 2009 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64CBH8A5P M 2N2G64CB8HA5N m m 1GB 128M x 64 2GB 256M x 64 elixir Unbuffered DDR3 SO DIMM Environmental Requirements Symbol Parameter Rating Units Topr Operating Temperature ambient 0 to 65 C TsrG Storage Temperature 50 to 100 Eo Note Stress greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability Absolute Maximum DC Ratings Symbol Parameter Rating Units Note Vpp
11. 7 tCK AVG T ene om CWL 8 ICK AVG 3 T Supported CL settings 6 7 8 6 8 9 10 nCK Supported CWL Settings 5 6 5 6 7 nCK REV1 1 04 2009 13 elixir NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64CBH8A5P M2N2G64CB8HA5N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SO DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module el IXIr DDR3 1066 DDR3 1333 Parameter Symbol Min Max Min Max Units Clock Timing Minimum Clock Cycle time DLL off mode ik nd 8 8 ns Average high pulse width tCH avg 0 47 0 53 0 47 0 53 tCK avg Average low pulse width tCL avg 0 47 0 53 0 47 0 53 tCK avg Aste Ook Pte cx ex Dime Dm SSG Absolute clock high pulse width tCH abs 0 43 0 43 ps Absolute clock low pulse width tCL abs 0 43 0 43 ps Clock Period Jitter tJIT per 90 90 80 80 ps Clock Period Jitter during DLL locking period tJIT per Ick 80 80 70 70 ps Cycle to Cycle Period Jitter tJIT cc 180 160 ps Cycle to Cycle Period Jitter during DLL locking period tJIT cc lck 160 140 ps Duty Cycle Jitter tJIT duty ps Cumulative error across 2 cycles tERR 2per 132 132 118 118 ps Cumulative error across 3 cycles tERR 3per 157 157 140 140 ps Cumulative er
12. Down Current Always Fast Exit 352 396 mA DD3N Active Standby Current 572 616 mA DD4W Operating Current Burst Write 1258 1522 mA DD4R Operating Current Burst Read 1082 1258 mA DD5B Burst Refresh Current 1170 1258 mA lDD6 Self Refresh Current Normal Temperature Range 0 85C 123 123 mA DD7 All Bank Interleave Read Current 1522 1830 mA Note Module IDD was calculated from component IDD It may differ from the actual measurement Operating Standby and Refresh Currents Tcase 0 C 85 C Vona Vpp 1 5V 0 075V 2GB 2Ranks base on 128Mx8 DDR3 SDRAMs Symbol Parameter Condition DDR3 1066 DDR3 1333 Unit DDo Operating Current one bank activate Precharge 1109 1197 mA IDDi Operating Current one bank activate Read Precharge 1241 1329 mA DD2P 0 Precharge Power Down Current Fast Exit MRO bit A12 0 282 282 mA DD2P 1 Precharge Power Down Current Slow Exit MRO bit A12 1 528 528 mA DD2N Precharge Standby Current 1144 1232 mA I DD2Q Precharge Quiet Standby current 968 1056 mA DD3P Active Power Down Current Always Fast Exit 704 792 mA DD3N Active Standby Current 1144 1232 mA DD4w Operating Current Burst Write 1549 1901 mA DD4R Operating Current Burst Read 1549 1901 mA DD5B Burst Refresh Current 2341 2517 mA lDD6 Self Refresh Current Normal Temperature Range 0 85C 246 246 mA DD7 All Bank Interleave Read Current 2781 3309 mA Note Module IDD was calculated from component IDD It may differ from the actual measureme
13. M2N1G64CBH8A5P M2N2G64CB8HA5N 1GB 128M x 64 2GB 256M x 64 elixir Unbuffered DDR3 SO DIMM Based on 64Mx16 1GB 128Mx8 2GB DDR3 SDRAM A Die Features Performance Speed Sort PC3 8500 PC3 10660 BE CG Unit DIMM CAS Latency 7 9 fck Clock Freqency 533 667 MHz tck Clock Cycle 1 875 1 5 ns fDQ DQ Burst Freqency 1066 1333 Mbps 204 Pin Small Outline Dual In Line Memory Module SO DIMM Programmable Operation 1GB 128Mx64 Unbuffered DDR3 SO DIMM based on 64Mx16 DIMM CAS Latency 5 6 7 8 9 10 DDR3 SDRAM A Die devices Burst Type Sequential or Interleave 2GB 256Mx64 Unbuffered DDR3 SO DIMM based on 128Mx8 Burst Length BC4 BL8 DDR3 SDRAM A Die devices Operation Burst Read and Write Intended for 533MHz 667MHz 800MHz applications Two different termination values Rtt Nom amp Rtt WR Inputs and outputs are SSTL 15 compatible 13 10 2 row column rank Addressing for 1GB Voo Vppo 1 5V 0 075V 14 10 2 row column rank Addressing for 2GB SDRAMs have 8 internal banks for concurrent operation Extended operating temperature rage Differential clock inputs Auto Self Refresh option Data is read or written on both clock edges Serial Presence Detect e DRAM DLL aligns DQ and DGS transitions with clock transitions Gold contacts Address and control signals are fully synchronous to positive 1GB SDRAMs are in 96 ball BGA Package clock edge 2GB SDRAMs are in 78 ball BGA Packa
14. N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SO DIMM elixir Ordering Information Part Number Speed Organization Power Leads Note M2N1G64CBH8A5P BE DDR3 1066 PC3 8500 533MHz 1 875ns CL 7 s aMx64 M2N1G64CBH8A5P CG DDR3 1333 PC3 10600 667MHz 1 500ns CL 9 15V Gold M2N2G64CB8HA5N BE DDR3 1066 PC3 8500 533MHz 1 875ns CL 7 256Mx64 M2N2G64CB8HA5N CG DDR3 1333 PC3 10600 667MHz 1 500ns CL 9 Pin Description CKO CK1 Clock Inputs positive line DQO0 DQ63 Data input output CKO CK1 Clock Inputs negative line DQS0 DQS7 Data strobes CKEO CKE1 Clock Enable DQs0 DQS7 Data strobes complement RAS Row Address Strobe DMO DM7 Data Masks CAS Column Address Strobe EVENT Temperature event pin WE Write Enable RESET Reset pin S0 S1 Chip Selects Vnerba VnEFCA Input Output Reference AO A9 A11 A13 Address Inputs Vopspp SPD and Temp sensor power A10 AP Address Input Auto Precharge SAO SA1 Serial Presence Detect Address Inputs A12 BC Address Input Burst Chop Vtt Termination voltage BAO BA2 SDRAM Bank Address Inputs Vss Ground ODTO ODT1 Active termination control lines Voo Core and I O power SCL Serial Presence Detect Clock Input NC No Connect SDA Serial Presence Detect Data input output Note A13 is only support in 2GB module type REV1 1 04 2009 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change pr
15. S latency time tAAmin 13 125ns 13 5ns 69 6C 17 Minimum write recovery time tWRmin 15ns 78 18 Minimum CAS to CAS delay tRCDmin 13 125ns 13 5ns 69 6C 19 Minimum Row Active to Row Active delay tRRDmin 7 5ns 6ns 3C 30 20 Minimum row Precharge delay tRPmin 13 125ns 13 5ns 69 6C 21 Upper nibble for tRAS and tRC 1 1 11 22 Minimum Active to Precharge delay tRASmin 37 5ns 36ns 2C 20 23 Minimum Active to Active Refresh delay tRCmin 50 625ns 49 5ns 95 8C 24 Minimum refresh recovery delay tRFCmin LSB Combo bytes 24 25 70 25 Minimum refresh recovery delay tRFCmin MSB 110ns 03 26 Minimum internal Write to Read command delay tWTRmin 7 5ns 3C 27 Ms ans Read to Precharge command delay 7 5ns 3C 28 Minimum four active window delay tFAWmin LSB Combo byte 28 29 01 00 29 Minimum four active window delay tFAWmin MSB 37 5ns 30ns 2C FO RZQ 6 30 SDRAM device output drivers suported RZQ 7 83 DLL Off Mode Support Extended Temperature Range 31 SDRAM device thermal and refresh options OBS 8D PASR 32 Module thermal sensor Non Thermal Sensor Support 00 33 SDRAM device type Standard Monolithic Device 00 34 59 Reserved Undefined 60 Module height nominal 29 height lt 30 mm OF REV1 1 9 04 2009 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64CBH8A5P M2N2G64CB8HA5N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SO DIMM Serial Presence Detect Part 2 of 2
16. Voltage on VDD pins relative to Vss 0 7 to 1 95 V 1 2 VDDQ Voltage on VDDQ pins relative to Vss 0 5 to 1 95 V 1 3 Vin VoUT Voltage on I O pins relative to Vss 0 5 to 1 95 V 1 TsrG Storage Temperature 55 to 95 C 1 2 Note 1 Stresses greater than those listed under Absolute Maxiumum Ratings may cause permenent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please referto JESD51 2 standard 3 VDD and VDDQ must be within 300mV of each other at all times Operating temperature Conditions Symbol Parameter Rating Units Note Toase Operating Temperature Ambient 0 to 95 C 1 Note 1 Case temperature is measured at top and center side of any DRAMs 2 TcAsE gt 85 C gt trer 3 9 us DC Electrical Characteristics and Operating Conditions Symbol Parameter Min Typ Max Units Notes VDD Supply Voltage 1 425 1 5 1 575 V 1 2 VDDQ Output Supply Voltage 1 425 1 5 1 575 V 1 2 Note 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together Single Ended AC and DC Input Levels
17. ge RoHS compliance Description M2N1G64CBH8A5P and M2N2G64CB8HASN are unbuffered 204 Pin Double Data Rate 3 DDR3 Synchronous DRAM Small Outline Dual In Line Memory Module SO DIMM organized as two ranks of 128Mx64 1GB and 256Mx64 2GB high speed memory array Modules use eight 64Mx16 1GB 96 ball BGA packaged devices and sixteen 128Mx8 2GB 78 ball BGA packaged devices These DIMMs are manufactured using raw cards developed for broad industry use as reference designs The use of these common design files minimizes electrical variation between suppliers All Elixir DDR3 SODIMMs provide a high performance flexible 8 byte interface in a space saving footprint The DIMM is intended for use in applications operating of 533MHz 667MHz 800MHz clock speeds and achieves high speed data transfer rates of 1066Mbps 1333Mbps 1600Mbps Prior to any access operation the device CAS latency and burst length operation type must be programmed into the DIMM by address inputs A0 A12 1GB A0 A13 2GB and I O inputs BAO BA2 using the mode register set cycle The DIMM uses serial presence detect implemented via a serial EEPROM using a standard IIC protocol The first 128 bytes of SPD data are programmed and locked during module assembly The remaining 128 bytes are available for use by the customer REV1 1 1 04 2009 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64CBH8A5P M2N2G64CB8HA5
18. is sent at the leading edge of the data window DQS Signals are complements and timing is relative to the cross point of respective DQS and DAQS If the module is to be operated in single ended strobe mode all DQS signals must be tied on the system board to Vss and DDR3 SDRAM mode registers programmed appropriately Selects which DDR3 SDRAM internal bank of four or eight is activated During a Bank Activate command cycle defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK During a Read or Write command cycle defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK In addition to the column address AP is used to invoke autoprecharge operation at the end of the burst read or write cycle If AP is high autoprecharge is selected and BAO BAn defines the bank to be precharged If AP is low autoprecharge is disabled During a Precharge command cycle AP is used in conjunction with BAO BAn to control which bank s to precharge If AP is high all banks will be precharged regardless of the state of BAO BAn inputs If AP is low then BAO BAn are used to define which bank to precharge Data Input Output pins Power supplies for core I O Serial Presence Detect Temp sensor and ground for the module Reference voltage for SSTL15 inputs This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor A resistor must be c
19. locked DLL pontis eed wer Down with DLL frozen to commands txepii max 10nGK 24ns max 10nCK 24ns CKE minimum pulse width tCKE pr T me s Command pass disable delay tCPDED 1 1 nCK Power Down Entry to Exit Timing tPD tCKE min 9 tREFI tCKE min 9 tREFI Timing of ACT command to Power Down entry tACTPDEN 1 1 nCK Timing of PRE or PREA command to Power Down entry tPRPDEN 1 1 nCK Timing of RD RDA command to Power Down entry tRDPDEN RL 4 1 RL 4 1 D nCK Timing of WR command to Power Down entry BL8OTF iWRPDEN WL 4 tWR tCK a p WL 4 tWR tCK a _ nCK BL8MRS BC4OTF v9 v9 Bee BOLOI to Power Down entry BLBOTF wrappeEN WL 4 WR 1 WL 44WR 1 nCK Timing of WR command to Power Down entry BCAMRS tWRPDEN idi tCK a du oda nCK Timing of WRA command to Power Down entry BCAMRS tWRAPDEN WL 2 WR 1 WL 2 WR 1 nCK Timing of REF command to Power down entry tREFPDEN 1 1 E nCK Timing of MRS command to Power Down entry tMRSPDEN tMOD min tMOD min REV1 1 15 04 2009 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64CBH8A5P M2N2G64CB8HA5N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SO DIMM el IXIr DDR3 1066 DDR3 1333 Parameter Symbol Min Max Min Max Units ODT Timings ODT high time without write command or with write command and BC4 Obie 4 i BOR ODT high
20. nt REV1 1 12 04 2009 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64CBH8A5P M2N2G64CB8HA5N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SO DIMM Speed Bins Speed Bin DDR3 1066 BE DDR3 1333 CG CL nRCD nRP 7 7 7 9 9 9 Unit Parameter Symbol Min Max Min Max Internal read command to first data tAA 13 125 20 13 5 20 ns ACT to internal read or write delay IRCD 13 125 T 13 5 B T time PRE command period tRP 13 125 13 5 ns ACT to ACT or REF command period tRC 50 625 s 49 5 e ns ACT to PRE command period tRAS 37 5 9 IREFI 36 g tREFI ns CWL 5 tCK AVG Reserved Reserved ns hm CWL 6 7 8 tCK AVG Reserved Reserved ns CWL 5 tCK AVG 2 5 3 3 2 5 3 3 ns CL 6 CWL 6 tCK AVG Reserved Reserved ns CWL 7 8 tCK AVG Reserved Reserved ns CWL 5 tCK AVG Reserved Reserved ns CWL 6 tCK AVG 1 875 25 Reserved ns CL 7 CWL 7 tCK AVG Reserved Reserved ns CWL 8 tCK AVG Reserved Reserved ns CWL 5 tCK AVG Reserved Reserved ns CWL 6 tCK AVG 1875 25 1875 25 ns ni CWL 7 tCK AVG x Reserved ha CWL 8 tCK AVG 5 Reserved ns CWL 5 6 tCK AVG Reserved ns CL 9 CWL 7 tCK AVG 1 5 lt 1 875 ns CWL 8 tCK AVG Reserved ns CWL 5 6 tCK AVG m Reserved ns CL 10 CWL 7 tCK AVG B Reserved ns tCK AVG 1 ar CWL S 6
21. oducts and specifications without notice M2N1G64CBH8A5P M2N2G64CB8HA5N 1GB 128M x 64 2GB 256M x 64 elixir Unbuffered DDR3 SO DIMM 1GB 2GB DDR3 SDRAM SODIMM Pinout Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 Vrerpa 2 Vss 53 DQ19 54 Vss 105 Vop 106 Voo 155 Vss 156 Vss Vss 4 DQ4 55 Vss 56 DQ28 107 A10 AP 108 BA1 157 DQ42 158 DQ46 DQO 6 DQ5 57 DQ24 58 DQ29 109 BAO 110 RAS 159 DQ43 160 DQ47 Dat 8 Vss 59 DQ25 60 Vss 111 Vop 112 Vodo 161 Vss 162 Vss Vss 10 DQSO 61 Vss 62 DQS3 113 WE 114 SO 163 DQ48 164 DQ52 11 DMO 12 DQSO 63 DM3 64 DQS3 115 CAS 116 ODTO 165 DQ49 166 DQ53 13 Vss 14 Vss 65 Vss 66 Vss 117 Vop 118 Voo 167 Vss 168 Vss 15 DQ2 16 DQ6 67 DQ26 68 DQ30 119 A13 NC 120 ODT1 169 DQS6 170 DM6 17 DQ3 18 DQ7 69 DQ27 70 DQ31 121 ST 122 NC 171 DQS6 172 Vss 19 Vss 20 Vss 71 Vss 72 Vss 123 Vop 124 Voo 173 Vss 174 DQ54 21 DQ8 22 DQ12 73 CKEO 74 CKE1 125 NC 126 VagcA 175 DQ50 176 DQ55 23 DQ9 24 DQ13 75 Voo 76 Vpp 127 Vss 128 Vss 177 DQ51 178 Vss 25 Vss 26 Vss 77 NC 78 NC 129 DQ32 130 DQ36 179 Vss 180 DQ60 27 DQS1 28 DM1 79 BA2 80 NC 131 DQ33 132 DQ37 181 DQ56 182 DQ 1 29 DQS1 30 RESET 81 Voo 82 Vpp 133 Vss 134 Vss 183 DQ57 184 Vss 31 Vss 32 Vss 83 A12 BC 84 A11 135 DQS4 136 DM4 185 Vss 186 DQS7 33 DQ10 34 DQ14 85 AQ 86 A7 137 DQS4 138 Vss 187 DM7 188 DQS7
22. onnected from the SDA bus line to Vopspp on the system planar to act as a pull up This signal is used to clock data into and out of the SPD EEPROM and Temp sensor Address pins used to select the Serial Presence Detect and Temp sensor base address The EVENT pin is reserved for use to flag critical module temperature This signal resets the DDR3 SDRAM NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64CBH8A5P M 2N2G64CB8HA5N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SO DIMM Functional Block Diagram 1GB 2 Ranks 64Mx16 DDR3 SDRAMs 7 9 a ol9 o 0puusseg D Eg m sSucr BEBSS8 as amp 8 5 2400hm 2400hm paso M Lpas HH LDQS j HH paso v Do L DOS eas DMO J LDM i LDM E DQ 0 7 N DQ o 7 DO DQ 0 7 D4 bast J UDGS UDQS DaS UDOS T UDQS S DMI N 4 UDM e UDM e DQ 8 15 N 4 DQ 8 15 a DQ 8 15 a ko KD ul x i LUNES ko KO iu xe i pi s ses BeERESESBS BERESESSS lj e 2400hm 2400hm pas2 M Lpas 1 LDQS
23. rnal Write to Read command delay tWTRmin 7 5ns 3C 27 Mie mous Read to Precharge command delay 7 5ns 3C 28 Minimum four active window delay tFAWmin LSB Combo byte 28 29 01 29 Minimum four active window delay tFAWmin MSB 50ns 45ns 90 68 RZQ 6 30 SDRAM device output drivers suported RZQ 7 83 DLL Off Mode Support Extended Temperature Range 31 SDRAM device thermal and refresh options ond 8D PASR 32 Module thermal sensor Non Thermal Sensor Support 00 33 SDRAM device type Standard Monolithic Device 00 34 59 Reserved Undefined 60 Module height nominal 29 lt height lt 30 mm OF REV1 1 7 04 2009 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64CBH8A5P M2N2G64CB8HA5N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SO DIMM Serial Presence Detect Part 2 of 2 1GB 128Mx64 2Ranks DDR3 SODIMM based on 64Mx16 1 5V DDR3 SDRAMs with SPD elixir Serial PD Data Entry Byte Description TRENA Hexadecimal Note BE CG BE CG 61 Module thickness Max E a p mni 11 62 Raw Card ID reference Raw Card A 00 63 DRAM address mapping edge connector Undefined 00 64 116 Reserved 117 118 Module manufacture ID 830B 119 125 Module information 126 127 CRC 5309 BD5F 128 145 Module part number Undefined 146 Module die revision Undefined 00 147 Module PCB revision Nanya Technology 00 148 149 DRAM device man
24. ror across 4 cycles tERR 4per 175 175 155 155 ps Cumulative error across 5 cycles tERR 5per 188 188 168 168 ps Cumulative error across 6 cycles tERR 6per 200 200 177 177 ps Cumulative error across 7 cycles tERR 7per 209 209 186 186 ps Cumulative error across 8 cycles tERR 8per 217 217 193 193 ps Cumulative error across 9 cycles tERR 9per 224 224 200 200 ps Cumulative error across 10 cycles tERR 10per 231 231 205 205 ps tERR npr min tERR npr max tERR npr min tERR npr max Cumulative error across n 11 50 cycles tERR nper 1 0 68In n tUIT 1 0 68In n tUIT 2 1 0 68In n tJIT 1 0 68In n tJIT ps per min per max per min per max Data Timing DQS DOS to DQ skew per group per access tDQSQ 150 125 ps DQ output hold time from DQS DQS tQH 0 38 0 38 tCK avg DQ low impedance time from CK CK tLZ DQ 600 300 500 250 ps DQ high impedance time from CK CK tHZ DQ 300 250 ps ae ep time to DQS DQS reference to Vih ac Vil ac tDS base 25 TBD m pid time to DQS DQS reference to Vih ac Vil ac tDH base 100 TBD ps Data Strobe Timing DGS DQS differential READ Preamble tRPRE 0 9 0 9 tCK avg DQS DQS differential READ Postamble tRPST 0 3 0 3 tCK avg DGS DQS differential output high time tQSH 0 38 0 40 tCK avg DQS DQS differential output low time tQSL 0 38 0 40 tCK avg DGS DQS differential WRITE Preamble tWPRE 0 9 0 9 tCK avg DGS DQS differential WRITE Postamble tWPST 0 3 0 3 tCK avg ag DQS rising dege
25. s 0 25 max 0 010 max 7 n n z z A g gt Q 45 0 03 0 018 0 001 TANE li LL LLLIOagNM 0 6 0 059 n 0 024 Detail A Detail B Units Millimeters Inches Note Device position and scale are only for reference REV1 1 17 04 2009 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64CBH8A5P M2N2G64CB8HA5N m 1GB 128M x 64 2GB 256M x 64 elixir Unbuffered DDR3 SO DIMM Package Dimensions 2GB 2 Ranks 128Mx8 DDR3 SDRAMs 67 60 0 15 2 661 0 006 2 0 63 60 3 8max gt a 0 079 2 504 0 150max ic TO eoo NEL EE e k nad d 3 We NX Detail A NLA Detail B 1 0 07 0 1 n etal 0 03 0 004 2x 01 80 5 p e Ut x lt N to S b i N o 1 M i eG oO T V j E x f A E 7 N 0 45 0 03 EM gpl 3 0 Le 0 018 0 001 Ri _ 0 039 7l we 1 5 0 6 0 059 0 024 Detail A Detail B Units Millimeters Inches Note Device position and scale are only for reference REV1 1 18 04 2009 NANYA TECHNOLOGY
26. s 1 DQ wiring may differ from that shown however DQ DM DQS and DGS relationships are maintained as shown NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64CBH8A5P M2N2G64CB8HA5N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SO DIMM Functional Block Diagram 2GB 2 Ranks 128Mx8 DDR3 SDRAMs eiXxir y VDD VDD z Cterm Cterm a MOMusenbL eeSfe vit Se ve PEGESHese M BE Se Eg KH LII HH 2400hm 2400hm 2400hm 2400hm pas3 J Das EN Das P Das Fe Das x16 I N Das4 pass J 4 Das erc Das muy Ee Das p UE Da
27. s ZO eal pas4 DM3 M DM B DM P DM B DM LAK DM4 DQ 24 31 V DQ O 7 D11 DQ 0 7 D3 DQ 0 7 D4 DQ 0 7 D12 A DQ 32 39 e e e e x x E E 2 E oO e M GA BEREESBSBe BERBESBSSe BEBESBSSe BEBESBS8e q I h 7 1 h 7 hg pot IL hg hot A id uad N N N N 2400hm 2400hm 2400hm 2400hm DOS M E 1 D 1 5 1 D 1 M pase DOST paS ZQ pas za Das za Dos ZQ N unlit N Das Das ai Das Das 1 LAw vase DM M DM 7 DM DM DM LAN DM6 DQ 8 15 N 4 DQ 0 7 Di DQ 0 7 D9 DQ 0 7 D14 DQ 0 7 D6 A DQ 48 55 e e e e a a ES a egBeseS8s eegesegss eeBeseS5s egEsssEBS Oe amp SESOSoFz OBSESOS6oF OB SESOSoF OeSESOS6s z z z 7 N N 2400hm 2400hm 2400hm 2400hm Daso N pas 1 Das 1 DOS 1 pas 1 L AN Das7 paso JN Das Ze c ea Das 2 Das mr Das ROI NI aL Das7 DMO NV DM gt DM S DM iat DM LNM DM7 DQ 0 7 N 4 DQ 0 7 Do DQ 0 7 D8 DQ 0 7 D15 DQ 0 7 D7 I A DQ 56 63 z z z 5 lt L lt a a oO oO oO m BBBESBSse BEEESBSBS BEBESBSBE BEBESBSSE Np d Np x RZRZRZRAR R R RAR R KA hd 2400hm 2400hm 2400hm 2400hm DOS2 J Das SEO Das HNE DQS KA DQS aie L N Dass DQS2 J Das FAS NM est Das AON al Das E um Das CROP ea Dass DM2 M DM DM B DM E DM e M DM5 DQ 16 23 V DQ 0 7 D2 DQ 0 7 D10 DQ 0 7 D13 DQ 0 7 D5 4N DQ 40 47 e e e e x x g E E a a 85 Ez BEBESBSS8e BEBESBSS8E BEBESBSS8Ee BEBESBSS8e
28. ufacturer ID 830B 150 175 Manufacturer reserved Undefined 176 255 Customer reserved REV1 1 8 04 2009 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64CBH8A5P M2N2G64CB8HA5N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SO DIMM Serial Presence Detect Part 1 of 2 2GB 256Mx64 2Ranks DDR3 SODIMM based on 128Mx8 1 5V DDR3 SDRAMs with SPD el IXIr SPD Entry Value Serial PD Data Entry Byte Description Hexadecimal Note BE CG BE CG CRC Covers Bytes 0 116 0 CRC range EEPROM bytes bytes used Total SPD Bytes 256 92 SPD Bytes Used 176 1 SPD revision Revision 10 10 2 DRAM device type DDR3 SDRAM 0B 3 Module type form factor SO DIMM 03 4 SDRAM Device density and banks 8 banks 1Gb 02 5 SDRAM device row and column count 14 rows 10 columns 11 6 Reserved Undefined 00 7 Module ranks and device DQ count 2 ranks 8 bits 09 8 ECC tag and module memory Bus width Non ECC 64bits 03 9 Fine timebase dividend divisor in ps 2 5ps 52 10 Medium timebase dividend ins 01 11 Medium timebase divisor 8ns 08 12 Minimum SDRAM cycle time tCKmin 1 875ns 1 5ns OF 0C 13 Reserved Undefined 00 14 CAS latencies supported 6 7 8 6 8 9 1C 34 15 CAS latencies supported Undefined 00 16 Minimum CA
29. ui no m ms NEL ND pos ANL DM2 M LDM i LDM i DQ 16 23 N DQJ 0 7 D1 DQ 0 7 D5 DQS3 JN UDQS UDQS Dass J 4 UDGS S UDQS S DM3 N 4 UDM e UDM e DQ 24 31 M DQ 8 15 S DQ 8 15 B opurzeUBE5s opuretuRs BESESSS82 BERESES8S J e 2400hm 2400hm DQS4 J 4 Lpas T HH LDQs ds ui DQS4 M bas DaS Iu DM4 JA LDM LDM DQ 32 39 DQ 0 7 D2 DQ 0 7 D6 pas5 JN 4 UDQS UDQS pass J 4 UDGS S UDQS S DM5 M UDM e UDM e DQ 40 47 XN DQ 8 15 a DQ 8 15 a nP G urvv bS ne M urv bS BRSESES8S BBSESBS3s J 2400hm 2400hm pass J LDQS 1 LDQS 1 pas bas reme Das aL DM6 LDM E LDM 7 DQ 48 55 DQ 0 7 D3 DQ 0 7 D7 DQS7 J UDGS UDQS pas7 JN 4 UDGS x UDQS S DM7 M UDM e UDM e DQ 56 63 V DQ 8 15 DQ 8 15 Bl E nP Gurvev bS e BBBESBS8s I vtt J aw iE m VDD VDD REV1 1 5 04 2009 elixir SCL SCL sao gt A0 Temp Sensor SDA SA1 M I PNE Y A2 EVENT EVENT SCL SCL SAO AO SPD SDA SA1 gt Al gt A2 WP Vtt Vit Vppspp SPD TS VnEFCA D0 D7 Vrerpa D0 D7 Voo Pe e D0 D7 Vss 5 P D0 D7 SPD Temp sensor CKO DO D3 CKO DO D3 CK1 D4 D7 ck D4 D7 EVENT y Temp Sensor RESET D0 D7 Note
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