ADATA 4GB DDR3 PC-2000 DC Kit
Contents
1. 0 80x0 05 31 50 1 97 0 20MM Ma x 0 05MMCMin VIEW G L Detail B UP TIONAL 3 806149 61 Detail A EL6711B16_DDR3 2000X CL 9 _2GB 128Mx8_Pb free Rev 0 2009 01 16 Page 7 of 72. 198 No 238 soa Noceo 79 NO ne saz 159 woces vss zo vss 4 Noc so vss 12 vm te vss 20 pas 20 vr EL67IIBI6 DDR3 2000X CL 29 2GB 128MXx Pb free Rev 0 2009 01 16 Page 3 of 7 PONTA oo Pin Description CKO CK1 FUNCTION System Clock Active on the positive and negative edge to sample all inputs CKO CK1 Clock Enable Chip Select Banks Select DQ0 DQ63 Data Data and check bit inputs outputs are multiplexed on the same pins Masks system clock to freeze operation from the next clock cycle CKE should be enabled at least on cycle prior new command Disable input buffers for power down in standby Disables or Enables device operation by masking or enabling all input except CK CKE and L U DQM Row Column address are multiplexed on the same pins Row Address AO A13 Column Address AO A9 _ Auto precharge A10 AP Selects bank to be activated during row address latch time Selects bank for read write during column address latch time DQSO DQS7 Bi directional Data Strobe Data Strobe DQS0 DQS7 When high termination resistance is enabled for all DQ DQ and DM pins assuming the ODTO ODT1 On Die Termination function is enabled in the Extended Mode Register Set This pin is recommended to be left No Connection on the device EL6711B16_DDR3 2000X CL 9 _2GB 128Mx8_Pb free Rev 0 2009 01 16 Page 4 of 7 Block Diagram hp DM CS
3. Average Refresh Period 7 8us at lower then TCASE 85 C 3 9us at 85 C TCASE s 95 C 8 bit pre fetch On Die Termination using ODT pin Internal self calibration Internal self calibration through ZQ pin RZQ 240 ohm 1 e EEPROM VDDSPD 3 3V Typical PCB Height 30 00mm 1 181 Double sided component Clock Cycle Time tCK DDR3 1333 tCK 1 5ns DDR3 2000 tCK 1 0ns Refresh to Active Refresh Command Time tRFC 110ns Lead free products are RoHS compliant EL67IIBI6 DDR3 2000X CL 29 2GB 128MXx Pb free Rev 0 2009 01 16 Page 2 of 7 Pin Assignment VREFDQ Dos amb 161 NCDM8 DM8 201 DOS Com ew e ww pe x w ws m 4 cor vss js moss i vss 164 noces 204 NO 5 ves 45 noose as vase 125 wo 165 Nocs zs vss 6 maso 4e noces se vss 16 nc 166 vss 206 Dos 7 pos ar vss a7 pos v7 vss ser No 207 poo 8 ves No s bos 18 poe 168 meser 2 vss 9 oc a No vss par 169 ckeinc 209 Das w Dos so ckeo o poo 10 vss so voo eo bos ves si vo je bow poa i As zn vss 2 Dos se bw o ves se poo 72 Aw are oms pis o ss mo 9 moss iss vss a vo ais NO m ves 5 vo o poss pw za a ara vss s mas ss an os ves is wc fas o a ais poe s Dos
4. se arz 96 poe 16 vss ie voo ar pov ves s vo o boe pow sr as ar ves pie Don se as o ves 198 pos 1 Ae as poo pio can se a o poe io vss i voo e pos vss 60 von too Doe o Doo j so as zo vss n poe 6 a tor ves pon se a zat om por e voo te mose i vss se voo 22 wo ves 63 ckinc v pose 143 owe se voo 23 vss 24 masz 64 icxino 104 ves se nc 184 cko 24 pow 25 Dose es von tos paso 14s vss ses cko 225 pos vss e vob tos Dos 146 poo 186 voo 2 vss 27 Dom e vnEFCA tor ves w aes ser NC EVENT 227 Daso Dor e No tos pase e vss se ao 28 pos 20 ves e voo 109 pasz poe 189 voo ze vss 30 Dom vo At no ves 150 Doo 190 BA z0 DW 9 pos rz bw m mosz isi vss se vo ast wo s vss 7a vo 12 pasz om se mas 232 vss 33 mass 73 mwe na vss iss No 93 so zo poo s nasso za cas n4 pose 54 vss 19 voo zw Doo ves 75 vob ns pos 55 pos 198 opo 2 vss does 76 sinc ne vss 156 Dos so ais 296 voosro 57 pom 77 omnc nz sw is7 vss 197 voo zv SM ss vss z v ne so 158 nccsa
5. DQS DOS DM CS DOS DQSA DQ U4 DM CS DOS DQS de cre e DATA svosum DM CS DOS DQS U12 Vss DM U13 Vss DM CS2 DOS DQS DM CS DOS DOS U6 U14 Vss DM CS DOS DQS DM CS DOS DOSA DQ24 DQ25 DQ26 DQ27 U11 DQ28 DQ29 DQ30 DQ31 Vss Vss Vss Vss BAO BA2 BAO BA2 SDRAMs UO U15 VDDSPD SPD A0 A15 e AO0 A15 SDRAMs UO U15 Vpp Vppq UO U15 Rank1 UB U18 CKE1 CKE SDRAMs U8 U15 V UO U15 REFDQ o Ta CKEO CKE SDRAMs UO U7 Vss UO U15 CK1 RAS RAS SDRAMs UO U15 mx pu UO U15 c P n CAS e CAS SDRAMs UO U15 WE WE SDRAMs UO U15 ERES ODTO ODT SDRAMs UO U7 WP SDA ODT1 ODT SDRAMs U8 U15 AO A1 A2 CKO CK SDRAMs UO U7 E SA0 CEA T EAS CK1 CK SDRAMs U8 U15 Note 1 For each DRAM a unique ZQ resistor is connected to ground The ZQ resistor is 240 Ohm 1 2 Address mirroring EL67IIBI6 DDR3 2000X CL 29 2GB 128MXx Pb free Rev 0 2009 01 16 Page 5 of 7 PONTA oo Absolute Maximum Ratings Voltage on VDD supply relative to Vss 0 4 2 15 Voltage on VDDQ pin relative to Vss VDDQ 0 4 2 15 Voltage on any pin relative to Vss VIN Vout 0 4 2 15 Storage temperature TStg 55 100 Note DDR3 SDRAM component specification Operation Temperature Condition sma ve m mae Extended Temperature Range O
6. e DATA DATA Memory Module Data Sheet A Wonderful Memory EL6 11B16 DDR3 2000X CL9 240 Pin XMP U DIMM 2GB 256M x 64 bits General Description The ADATA s EL6711B16 is a 256Mx64 bits 2GB 2048MB DDR3 2000 CL9 SDRAM XMP memory module The SPD is programmed to JEDEC standard latency 1333Mbps timing of 9 9 9 24 at 1 5V The module is composed of sixteen 128Mx8 bits CMOS DDR3 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TDFN package on a 240pin glass epoxy printed circuit board The EL6711B16 is a Dual In line Memory Module and intended for mounting onto 240 pins edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operating frequencies programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Power supply Normal VDD amp VDDQ 1 5V 0 075V e 1 5V SSTL 15 compatible I O e XMP Extreme Memory Profile support Timing Reference DDR3 1333 CL9 9 9 24 at 1 5V DDR3 2000 CL9 9 9 24 at 2 05V XMP Profile 1 Burst Length 4 8 Programmable Additive Latency 0 CL 2 or CL 1 clock Bi directional differential data strobe DQS and DQS Differential clock input CK CK operation e DLL aligns DQ and DQS transition with CK transition Addresses are mirrored for second rank
7. ptional 485 7495 Note 1 If the DRAM case temperature is above 85 C the Auto Refresh command interval has to be reduced to tREFI 3 9us DC Operating Condition Voltage referenced to Vss OV VDD amp VDDQ 1 5V 0 075V Tc 0 to 85 C Wee 7 Ww Wweewe wee v Note 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together 3 The AC peak noise on VREF may not allow VREF to deviate from VREF DC by more than 1 VDD for reference approx 15mV 4 For reference approx VDD 2 15mV EL67IIBI6 DDR3 2000X CL 29 2GB 128MXx Pb free Rev 0 2009 01 16 Page 6 of 7 e DATA Package Dimensions ug ui uz Uu15 U14 u13 Ui2 Wit U10 ua Us D Io 4 J n i O 240 188 168 121 0 5009 69 min 2 311 91 009 2X 4 00 157 48 min 30 00 1181 10 Di Hole i 2 489 98 00 2X 4 S N Y 5 175 203 74X 2X 1 2 7 0 10 90 00 3 94 4 00 1850 39 2 1 5C203 7 4X 2X 47 0001850 39 RO70C2 7 562C8X EPN 2 CU gt lt ST KEE 2 10 82 68 4X XSS N RIVE MAAS Note Co i e N 1 Tolerance 0 15mm 5 91mils v ik HO TAIA ist x 2 50 98 43 bro p T x HULU 0 20MMCMa x2 5 00C 196 85 0 05MMCMin 1 50 0 10 99 0643 94
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