ADATA 4GB DDR3 PC3-12800 DC Kit
Contents
1. sw 157 vss 97 27 SM _ _ vss 78 sco 158 198 No 28 soa 39 r9 sw 159 085 199 vss 29 vss 4 vss 12 vss 20 poe 240 vr 6411 16 DDR3 1600G CL 9 2GB 128Mx8 Pb free Rev 2008 10 17 Page 2 of 6 Kon Pin Description CKO CK1 NAME FUNCTION System Clock Active on the positive and negative edge to sample all inputs CKO CK1 Clock Enable Chip Select Banks Select DQ0 DQ63 Data Data and check bit inputs outputs are multiplexed on the same pins Masks system clock to freeze operation from the next clock cycle CKE should be enabled at least on cycle prior new command Disable input buffers for power down in standby Disables or Enables device operation by masking or enabling all input except CK CKE and L U DQM Row Column address are multiplexed on the same pins Row Address A0 A13 Column Address A0 A9 Auto precharge A10 AP Selects bank to be activated during row address latch time Selects bank for read write during column address latch time DQSO DQS7 Bi directional Data Strobe Data Strobe DQS0 DQS7 When high termination resistance is enabled for all DQ DQ and DM pins assuming the ODTO ODT1 On Die Termination function is enabled in the Extended Mode Register Set This pin is recommended to be left No Connection on t2. 3 9us at 85 lt TCASE s 95 8 bit pre fetch On Die Termination using ODT pin Internal self calibration Internal self calibration through ZQ RZQ 240 ohm 1 EEPROM VDDSPD 3 3V Typical PCB Height 30 00mm 1 181 Double sided component Clock Cycle Time tCK DDR3 1600 tCK 1 25ns Refresh to Active Refresh Command Time tRFC 110ns Lead free products are RoHS compliant Pin Assignment nf Erom pem romi Pin mont fpr Baek Pin Baek VREFDQ pos 121 461 NC DM8 201 pox tee E 8 4 wo vss 19 pos 103 vss 28 a oar a vss mos 124 vss 164 204 nc 5 vss 45 noose pasa 125 165 25 vss 6 maso 46 se vss 126 166 vss 26 Dos 7 poo 47 vss j 147 vss 20 pass 8 vss 4s No pos 128 pas 168 meser 208 3 9 wo a vss 149 par 169 20 so fso f 19 vss 170 20 Do vss 5 vo je 181 ms 24 vss s sa o f vss 12 pam 172 22 55 mass 19 vss 79 23 wo m vss 54 pos 1 14 A2 24 ves _ mos ss an 9 vss fis wc 15 9 25 Das _ Das
3. DATA Memory Module Data Sheet A Wonderful Memory AD6411B16 DDR3 1600G CL9 240 U DIMM 2GB 256M x 64 bits General Description The ADATA s AD6411B16 is 256Mx64 bits 2GB 2048MB DDR3 1600 CL9 9 9 24 SDRAM over clocking memory module The SPD is programmed to JEDEC standard latency 1600Mbps timing of 9 9 9 28 at 1 5V The module is composed of sixteen 128Mx8 bits CMOS DDR3 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TDFN package on a 240pin glass epoxy printed circuit board The AD6411B16 is a Dual In line Memory Module and intended for mounting onto 240 pins edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions possible on both edges of DQS Range of operating frequencies programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Power supply Normal VDD VDDQ 1 5V 0 075V e 1 5V SSTL 15 compatible I O Timing Reference DDR3 1600 CL9 9 9 28 at 1 5V DDR3 1600 CL9 9 9 24 at 1 7V Burst Length 4 8 Programmable Additive Latency 0 CL 2 or CL 1 clock Bi directional differential data strobe DQS and DQS Differential clock input CK CK operation e DLL aligns DQ and DQS transition with CK transition Addresses are mirrored for second rank Average Refresh Period 7 8us at lower then TCASE 85
4. 15 Note 1 For each DRAM a unique ZQ resistor is connected to ground The ZQ resistor 15 240 Ohm 1 2 Address mirroring AD64I1B16 DDR3 1600G CL 9 2GB 128Mx8 Pb free Rev 1 2008 10 17 Page 4 of 6 Kon Absolute Maximum Ratings Voltage on VDD supply relative to Vss 0 4 1 975 Voltage on VDDQ pin relative to Vss VDDQ 0 4 1 975 Voltage on any pin relative to Vss VIN Vout 0 4 1 975 Storage temperature TStg 55 100 Note DDR3 SDRAM component specification Operation Temperature Condition amm we ew e Note 1 If the DRAM case temperature is above 85 C the Auto Refresh command interval has to be reduced to tREFI 3 9us DC Operating Condition Voltage referenced to Vss OV VDD amp VDDQ 1 5V 0 075V Tc 0 to 85 exem v _ eee vw wem Note 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together 3 The AC peak noise on VREF may not allow VREF to deviate from VREF DC by more than 1 VDD for reference approx 15 4 For reference approx VDD 2 15mV 6411 16 DDR3 1600G CL 9 2GB 128Mx8 Pb free 1 2008 10 17 Page 5 of 6 Package Dimensions UO U1 U
5. 2 U3 U4 U5 U6 U7 a ol 9 L 1 48 49 120 j 015 U14 U13 U12 U11 U10 U9 Us 240 169 168 121 138 35002 30 905 128 95 076 77 e S S 12 00 472 44 5 ON lt OU Hole 30 00 lt 1181 10 gt uec e TTT 5175 203 74X 2 0 47 00 1850 39 IL ILUS TANZA 47 0061850 39 0 Od 1 FP 2 CN Nu CU 0 866005 231 50 1 97 Detail 3 804149 61 Dow 0 10582 68 4 2 Note 1 Tolerance 0 15mm 5 91mils 6411 16 DDR3 1600G CL 9 2GB 128Mx8 Pb free Detail B 1 2 00 196 852 1 50 0 10 59 06 3 94 gt 3 00 0 10 118 11 3 94 4X gt Ql ur Qul A elc 10 NIM lt e DATA 0 5009 69 min 1 27 0 10 50 00 3 94 0 20 lt gt 0 05 lt 0 20 lt gt 0 0S5MMCMin gt VIEW LES 2008 10 17 UP TIONAL Page 6 of 6
6. he device 6411 16 DDR3 1600G CL 9 2GB 128Mx8 Pb free 1 2008 10 17 Page 3 of 6 gt DATA Block Diagram 51 penis E pena DQSO 3 0054 M14 Nu EE dus DM 65 DOS 005 DM 65 005 0052 DM CS2 DOS DQS DM CS DOS DOS DQO DQ DQ DO1 DQ xl UA U12 004 DQ DQ5 DQ 006 DQ DQ7 DQ DOS14 Vss Vss DQS1 DM1 mmu DM 65 DOS DOS 008 DQ 009 DQ 0010 DQ 0011 DQ DQ12 DQ DQ13 DQ 0014 DQ DQ15 DQ Vss Vss DQS2 pase DM2 r BE DM 65 DOS DOS DM 65 005 005 DM CS2 DOS DQS DM CS DOS 005 0016 DQ DQ17 00 0018 DQ 0019 po U6 U14 DQ20 0021 0022 DQ DQ23 Inq pasas 5 0053 DM3 e Co DM CS DOS 005 DM 65 DOS 0052 0024 DQ DQ25 0026 DQ 0027 __ U11 DQ28 po DQ29 DQ30 DQ 0031 __ Vss Vss Vss Vss V BAO BA2 BAO BA2 SDRAMs UO U15 DDSPD SPD A0 A15 AO0 A15 SDRAMs UO U15 Vpp VppqQ UO U15 Rank1 08 015 CKE1 SDRAMs 08 U15 V UO U15 REFDQ SDRAMs U7 Vss UO U15 a CK1 RAS RAS SDRAMs UO U15 su 00 145 n CAS CAS SDRAMs U15 SDRAMs U15 E E ODTO ODT SDRAMs U7 WP SDA ODT1 ODT SDRAMs U8 U15 AO 1 2 CKO SDRAMs UO U7 SDRAMs U8 U
7. se 18 vss 16 voo 26 pog 7 vs 57 vo oos 17 17 as 27 vss 18 ss as vss 18 pas 178 28 19 so poe 1 vss 19 29 boo vss 10 40 20 vss z poe ot a m vss vay pon er 21 om 22 62 102 mase 2 vss 142 voo 22 wo 23 vss cnc 1 pase 143 183 voo 23 vss 2 amp ikinc 14 vss M4 24 Dow 25 65 vno 105 pos vss 185 25 pass vss 66 vob 106 bos 16 002 186 voo 26 vss _ 67 107 vss 147 187 Novevent 227 Doo 28 e 108 pos 148 vss 48 28 Do vss e 149 49 008 49 voo 29 vss 30 atop vss 150 190 29 DW 5 pos 7 bw m masr 11 vss 9 21 wo s vss 72 pos ts om 12 mas 22 vss 33 moss 73 42 vss 18 so 25 oo s Dass za icas Dos 15 vss 194 voo 234 Dae s vss 75 45 pos 155 pos 195 28 vss 36 76 sinc we vss 156 16 236 voDSPD 5r 77 omnc
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